WO2018049866A1 - 像素驱动电路及像素驱动方法、阵列基板以及显示装置 - Google Patents

像素驱动电路及像素驱动方法、阵列基板以及显示装置 Download PDF

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Publication number
WO2018049866A1
WO2018049866A1 PCT/CN2017/090442 CN2017090442W WO2018049866A1 WO 2018049866 A1 WO2018049866 A1 WO 2018049866A1 CN 2017090442 W CN2017090442 W CN 2017090442W WO 2018049866 A1 WO2018049866 A1 WO 2018049866A1
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WIPO (PCT)
Prior art keywords
driving
transistor
module
scan line
drive
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PCT/CN2017/090442
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English (en)
French (fr)
Inventor
陈沫
熊雄
高吉磊
孙松梅
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020197024884A priority Critical patent/KR102136289B1/ko
Priority to JP2018505459A priority patent/JP2019529960A/ja
Priority to EP17832896.9A priority patent/EP3514786A4/en
Priority to KR1020187003397A priority patent/KR20180039058A/ko
Priority to US15/740,300 priority patent/US10510296B2/en
Publication of WO2018049866A1 publication Critical patent/WO2018049866A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Definitions

  • the present disclosure relates to the field of display technologies, and more particularly, to an OLED pixel driving circuit and a pixel driving method, an array substrate, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal display
  • the current mainstream development direction of OLEDs is to control the magnitude of the current between the source and the drain of the driving transistor by changing the gate voltage of the driving transistor that directly drives the OLED to achieve a change in the luminance of the light, which makes the driving transistor long.
  • the time is in operation, that is, its gate is always maintained in a positive or negative pressure state.
  • the existing thin film transistors (TFTs) of different materials generally have the characteristics that the threshold voltage Vth and the mobility (Mobility) change with time under the DC bias (the positive pressure and the negative pressure change the opposite direction). Therefore, the OLED display panel is prone to gray-scale brightness variation and gray-scale unevenness (due to different characteristics of different TFTs) after a period of operation.
  • a pixel driving circuit is provided.
  • the pixel drive The road includes a drive control module, a first drive module, and a second drive module.
  • the driving control module is connected to the data line, the first scan line, the second scan line, and the first voltage signal end, and is connected to the first driving module via the first node, to the second driving module via the second node, and configured Controlling the first driving module and the second driving module to be turned on when the first scan line outputs the effective voltage signal, and controlling the first driving module and the second driving module when the second scanning line outputs the effective voltage signal
  • the other one is turned on;
  • the first driving module is connected to the driving control module, the second voltage signal end, and the light emitting module, and is configured to drive the light emitting module to emit light under the control of the driving control module.
  • the second driving module is connected to the driving control module, the second voltage signal terminal and the lighting module, and is configured to drive the lighting module to emit light under the control of the driving control module.
  • the first scan line and the second scan line alternately output an effective voltage signal.
  • the driving control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor.
  • a control electrode of the first transistor is coupled to the first scan line, a first electrode of the first transistor is coupled to the data line, and a second electrode of the first transistor is coupled to the first node.
  • a control electrode of the second transistor is coupled to the second scan line, a first electrode of the second transistor is coupled to the data line, and a second electrode of the second transistor is coupled to the second node.
  • the control electrode of the third transistor is coupled to the second scan line, the first electrode of the third transistor is coupled to the first voltage signal terminal, and the second electrode of the third transistor is coupled to the first node.
  • the control electrode of the fourth transistor is coupled to the first scan line, the first electrode of the fourth transistor is coupled to the first voltage signal terminal, and the second electrode of the fourth transistor is coupled to the second node.
  • the first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to the second end of the second capacitor.
  • the first end of the second capacitor is coupled to the second node, and the second end of the second capacitor is coupled to the second end of the first capacitor.
  • the first driving module includes a first driving transistor, a gate of the first driving transistor is coupled to the first node, and a first electrode of the first driving transistor is coupled to the second voltage signal end, A second pole of a drive transistor is coupled to the light emitting module.
  • the second driving module includes a second driving transistor, a gate of the second driving transistor is coupled to the second node, and a first electrode of the second driving transistor is coupled to the second voltage signal end, The second pole of the two driving transistor is coupled to the light emitting module.
  • the transistors in the drive control module are all N-type transistors.
  • the transistors in the drive control module are all P-type transistors.
  • the transistors in the first driving module and the second driving module are all N-type transistors or both are P-type transistors.
  • a pixel circuit comprising the pixel driving circuit and the light emitting module as described above, wherein the pixel driving circuit is coupled to the light emitting module and configured to drive the light emitting module to emit light.
  • the light emitting module includes an organic light emitting diode.
  • an array substrate comprising the pixel circuit as described above.
  • a display device comprising the array substrate as described above.
  • a driving method for driving a pixel circuit as described above in which, in the first stage, an effective voltage signal is input to a first scanning line, to a second The scan line inputs a non-active voltage signal such that the drive control module controls one of the first drive module and the second drive module to turn on.
  • the non-effective voltage signal is input to the first scan line and the second scan line, and the driving control module maintains one of the first driving module and the second driving module to be turned on to drive the light emitting module to emit light.
  • an effective voltage signal is input to the second scan line, and an inactive voltage signal is input to the first scan line such that the drive control module controls the other of the first drive module and the second drive module to be turned on.
  • the non-effective voltage signal is input to the first scan line and the second scan line, and the other of the first drive module and the second drive module is turned on by the drive control module to drive the illumination module to emit light.
  • the transistors in the drive control module are all N-type transistors, the effective voltage signal is a high level signal, and the non-effective voltage signal is a low level signal.
  • the transistors in the drive control module are all P-type transistors, the effective voltage signal is a low level signal, and the non-effective voltage signal is a high level signal.
  • FIG. 1 is a schematic block diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • FIG. 2 is an example circuit diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • Figure 3 is a timing diagram of signals of the pixel circuit shown in Figure 2;
  • FIG. 4 is an equivalent working circuit diagram of the pixel circuit shown in FIG. 2 in the first stage
  • Figure 5 is an equivalent working circuit diagram of the pixel circuit shown in Figure 2 in the second stage
  • Figure 6 is an equivalent working circuit diagram of the pixel circuit shown in Figure 2 in the third stage
  • Figure 7 is an equivalent working circuit diagram of the pixel circuit shown in Figure 2 in the fourth stage
  • FIG. 8 is a schematic flowchart of a driving method of driving the pixel circuit shown in FIG. 1 according to an embodiment of the present disclosure.
  • the transistor due to the source and drain of the transistor (emitter and collector)
  • the poles are symmetrical, and the conduction currents between the source and the drain (emitter and collector) of the N-type transistor and the P-type transistor are opposite in direction, so in the embodiment of the present disclosure, the transistor is uniformly received
  • the middle of the control is called the control pole
  • the signal input is called the first pole
  • the signal output is called the second pole.
  • the transistors employed in the embodiments of the present disclosure are mainly switching transistors and driving transistors.
  • the capacitors employed in the embodiments of the present disclosure may also be replaced by energy storage elements having similar functions.
  • FIG. 1 shows a schematic block diagram of a pixel circuit 100 in accordance with an embodiment of the present disclosure.
  • the pixel circuit 100 may include a pixel driving circuit 110 and a light emitting module 120.
  • the pixel driving circuit 110 may include a driving control module 111, a first driving module 112, and a second driving module 113.
  • the drive control module 111 is connectable to the data line Data, the first scan line Gate1, the second scan line Gate2, the first voltage signal terminal VSS, and is connected to the first drive module 112 via the first node P1, and is connected via the second node P2. Go to the second drive module 113.
  • the driving control module 111 can control the first driving module 112 to be turned on when the first scan line Gate1 outputs the effective voltage signal, and control the second driving module 113 to turn on when the second scan line Gate2 outputs the effective voltage signal.
  • the driving control module 111 can control the second driving module 113 to be turned on when the first scan line Gate1 outputs the effective voltage signal, and control the first driving when the second scan line Gate2 outputs the effective voltage signal. Module 112 is turned on.
  • the effective voltage refers to a voltage that turns on the transistor.
  • the transistor operates, which is capable of outputting the voltage of the first pole of the transistor to its second pole.
  • the non-effective voltage refers to a voltage that turns off the transistor.
  • the transistor does not operate and it cannot output the voltage of the first pole of the transistor to its second pole.
  • the first scan line Gate1 and the second scan line Gate2 alternately output an effective voltage signal, so that the driving transistors in the first driving module 112 and the second driving module 113 are alternately turned on or off. So that the first driving module 112 and the second driving module 113 alternately drive the light emitting module 120 to emit light.
  • the second driving module 113 is in a restored state
  • the first driving module 112 is in a restored state.
  • the driving transistors in the first driving module 112 and the second driving module 113 can all work After a period of time, the recovery period is entered, thereby reducing the variation of the threshold voltage Vth and the mobility of the driving transistor in the first driving module 112 and the second driving module 113 over time, maintaining the initial characteristics of the driving transistor, thereby extending the display. The life of the panel.
  • FIG. 2 shows an example circuit diagram of a pixel circuit 100 in accordance with an embodiment of the present disclosure.
  • the driving control module 111 may include a first transistor T11, a second transistor T21, a third transistor T12, a fourth transistor T22, a first capacitor C1, and a second capacitor C2.
  • the control electrode of the first transistor T11 is coupled to the first scan line Gate1, the first electrode of the first transistor T11 is coupled to the data line Data, and the second electrode of the first transistor T11 is coupled to the first node P1.
  • the control electrode of the second transistor T21 is coupled to the second scan line Gate2, the first electrode of the second transistor T21 is coupled to the data line Data, and the second electrode of the second transistor T21 is coupled to the second node P2.
  • the control electrode of the third transistor T12 is coupled to the second scan line Gate2, the first electrode of the third transistor T12 is coupled to the first voltage signal terminal VSS, and the second electrode of the third transistor T12 is coupled to the first node P1.
  • the control electrode of the fourth transistor T22 is coupled to the first scan line Gate1, the first electrode of the fourth transistor T22 is coupled to the first voltage signal terminal VSS, and the second electrode of the fourth transistor T22 is coupled to the second node P2.
  • the first end of the first capacitor C1 is coupled to the first node P1, and the second end of the first capacitor C1 is coupled to the second end of the second capacitor C2.
  • the first end of the second capacitor C2 is coupled to the second node P2, and the second end of the second capacitor C2 is coupled to the second end of the first capacitor C1.
  • the first driving module 112 may include a first driving transistor T13.
  • the gate of the first driving transistor T13 is coupled to the first node P1, and the first electrode of the first driving transistor T13 is coupled to the second voltage signal terminal VDD.
  • the second electrode of the driving transistor T13 is coupled to the light emitting module 120.
  • the second driving module 113 may include a second driving transistor T23, the gate of the second driving transistor T23 is coupled to the second node P2, the first electrode of the second driving transistor T23 is coupled to the second voltage signal terminal VDD, and the second The second pole of the driving transistor T23 is coupled to the light emitting module 120.
  • the light emitting module 120 can include an organic light emitting diode.
  • the second end of the first capacitor C1, the second end of the second capacitor C2, the second pole of the first driving transistor T13, and the second pole of the second driving transistor T23 are coupled together. Connected to the anode of the organic light emitting diode. The cathode of the organic light emitting diode is grounded.
  • FIG. 3 shows a timing chart of respective signals of the pixel circuit 100 shown in FIG. 2. Below the map The timing chart shown in FIG. 3 describes the operation of the pixel circuit 100 as shown in FIG. 2 in detail. In the following description, assuming that all transistors are N-type transistors, the first voltage signal terminal VSS outputs a low level signal, and the second voltage signal terminal VDD outputs a high level signal.
  • a high level signal is input to the first scan line Gate1, thereby turning on the first transistor T11 and the fourth transistor T22.
  • a low level signal is input to the second scan line Gate2, thereby turning off the second transistor T21 and the third transistor T12.
  • the first transistor T11 Since the first transistor T11 is turned on, the data signal (high level) input from the data line Data is output to the first node P1 through the first transistor T11. At the same time, since the third transistor T12 is turned off, the low-level signal output from the first voltage signal terminal VSS does not affect the voltage of the first node P1, and thus the data signal input from the data line Data causes the voltage of the first node P1 to rise.
  • the first driving transistor T13 is turned on.
  • a high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the first driving transistor T13 to drive the organic light emitting diode to emit light.
  • the second driving transistor T23 is turned off and is in a recovery state.
  • a low level signal is input to the first scan line Gate1 and the second scan line Gate2, and the first to fourth transistors (T11, T21, T12, T22) are all turned off.
  • the voltage of the first node P1 is maintained at a high level by the first capacitor C1, thereby keeping the first driving transistor T13 turned on.
  • a high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the first driving transistor T13, and the organic light emitting diode is kept driven to emit light.
  • the voltage of the second node P2 is maintained at a low level by the second capacitor C2. Therefore, the second driving transistor T23 is turned off and is in a recovery state.
  • the driving current of the organic light emitting diode is only the first Drive transistor T13 controls.
  • a low level signal is input to the first scan line Gate1, thereby turning off the first transistor T11 and the fourth transistor T22.
  • a high level signal is input to the second scan line Gate2, thereby turning on the second transistor T21 and the third transistor T12.
  • the data signal (high level) input from the data line Data is output to the second node P2 through the second transistor T21.
  • the fourth transistor T22 since the fourth transistor T22 is turned off, the low level signal output from the first voltage signal terminal VSS does not affect the voltage of the second node P2. Therefore, the data signal input from the data line Data causes the voltage of the second node P2 to rise.
  • the second driving transistor T23 When the voltage of the second node P2 rises to the threshold voltage Vth of the second driving transistor T23, the second driving transistor T23 is turned on.
  • a high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the second driving transistor T23 to drive the organic light emitting diode to emit light.
  • the first driving transistor T13 is turned off and is in a recovery state.
  • a low level signal is input to the first scan line Gate1 and the second scan line Gate2, and the first to fourth transistors (T11, T21, T12, T22) are all turned off.
  • the voltage of the second node P2 is maintained at a high level by the second capacitor C2, thereby keeping the second driving transistor T23 turned on, and the high level signal from the second voltage signal terminal VDD is output to the organic light emitting diode through the second driving transistor T23.
  • the anode keeps driving the organic light emitting diode to emit light.
  • the voltage of the first node P1 is maintained at a low level by the first capacitor C1. Therefore, the first driving transistor T13 is turned off and is in a recovery state.
  • the driving current of the organic light emitting diode is controlled only by the second driving transistor T23.
  • the pixel circuit 100 then repeats the above four stages of operation.
  • the first capacitor C1 and the second capacitor C2 having the same structural parameters can be selected in the circuit structure design, and the first structural parameters are selected identically.
  • the transistor T13 and the second driving transistor T23 are driven. That is, the capacitance values of the first capacitor C1 and the second capacitor C2 are made the same (so that their charge and discharge times are also the same), and the channel parameters (width and width of the first driving transistor T13 and the second driving transistor T23 are made The length is the same.
  • the transistors in pixel circuit 100 as shown in FIG. 2 may also all be P-type transistors.
  • the following is a detailed description of the operation of the pixel circuit 100 in this case, in which the first voltage signal terminal VSS outputs a low level signal, and the second voltage signal terminal VDD outputs a high level signal.
  • a low level signal is input to the first scan line Gate1, thereby turning on the first transistor T11 and the fourth transistor T22.
  • a high level signal is input to the second scan line Gate2, thereby turning off the second transistor T21 and the third transistor T12.
  • the second transistor T21 Since the second transistor T21 is turned off, the data signal (high level) input from the data line Data cannot be output to the second node P2 through the second transistor T21. At the same time, since the fourth transistor T22 is turned on, the low-level signal output from the first voltage signal terminal VSS lowers the voltage of the second node P2. When the voltage of the second node P2 falls to the threshold voltage Vth of the second driving transistor T23, the second driving transistor T23 is turned on. A high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the second driving transistor T23 to drive the organic light emitting diode to emit light.
  • the data signal (high level) input from the data line Data is output to the first node P1 through the first transistor T11.
  • the third transistor T12 since the third transistor T12 is turned off, the low-level signal output from the first voltage signal terminal VSS does not affect the voltage of the first node P1. Therefore, the data signal input from the data line Data causes the voltage of the first node P1 to rise to a high level, thereby turning off the first driving transistor T13 and in a restored state.
  • the driving current of the organic light emitting diode is controlled only by the second driving transistor T23.
  • a high level signal is input to the first scan line Gate1, thereby turning off the first transistor T11 and the fourth transistor T22.
  • a low level signal is input to the second scan line Gate2, thereby turning on the second transistor T21 and the third transistor T12.
  • the first transistor T11 Since the first transistor T11 is turned off, the data signal (high level) input from the data line Data cannot be output to the first node P1 through the first transistor T11. At the same time, since the third transistor T12 is turned on, the low-level signal output from the first voltage signal terminal VSS lowers the voltage of the first node P1. When the voltage of the first node P1 falls to the threshold voltage Vth of the first driving transistor T13, the first driving transistor T13 is turned on. A high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the first driving transistor T13 to drive the organic light emitting diode to emit light.
  • the data signal (high level) input from the data line Data is output to the second node P2 through the second transistor T21.
  • the fourth transistor T22 since the fourth transistor T22 is turned off, the low level signal output from the first voltage signal terminal VSS does not affect the voltage of the second node P2. Therefore, the data signal input from the data line Data causes the voltage of the second node P2 to rise to a high level, thereby turning off the second driving transistor T23 and in a restored state.
  • a high level signal is input to the first scan line Gate1 and the second scan line Gate2, and the first to fourth transistors (T11, T21, T12, T22) are all turned off.
  • the voltage of the first node P1 is held low by the first capacitor C1, thereby keeping the first driving transistor T13 turned on.
  • a high level signal from the second voltage signal terminal VDD is output to the organic light emitting diode through the first driving transistor T13
  • the anode of the tube keeps driving the organic light emitting diode to emit light.
  • the voltage of the second node P2 is maintained at a high level by the second capacitor C2. Therefore, the second driving transistor T23 is turned off and is in a recovery state.
  • the driving current of the organic light emitting diode is controlled only by the first driving transistor T13.
  • the pixel circuit 100 then repeats the above four stages of operation.
  • the transistors in the drive control module 111 are all N-type transistors and the first drive module 112 and the second drive module 113 are The drive transistors are all P-type transistors.
  • the following is a detailed description of the operation of the pixel circuit 100 in this case in conjunction with the timing chart shown in FIG. 3, in which the first voltage signal terminal VSS outputs a low level signal, and the second voltage signal terminal VDD outputs a high level. signal.
  • a high level signal is input to the first scan line Gate1, thereby turning on the first transistor T11 and the fourth transistor T22.
  • a low level signal is input to the second scan line Gate2, thereby turning off the second transistor T21 and the third transistor T12.
  • the second transistor T21 Since the second transistor T21 is turned off, the data signal (high level) input from the data line Data cannot be output to the second node P2 through the second transistor T21. At the same time, since the fourth transistor T22 is turned on, the low-level signal output from the first voltage signal terminal VSS lowers the voltage of the second node P2. When the voltage of the second node P2 falls to the threshold voltage Vth of the second driving transistor T23, the second driving transistor T23 is turned on. A high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the second driving transistor T23 to drive the organic light emitting diode to emit light.
  • the data signal (high level) input from the data line Data is output to the first node P1 through the first transistor T11.
  • the third transistor T12 since the third transistor T12 is turned off, the low-level signal output from the first voltage signal terminal VSS does not affect the voltage of the first node P1. Therefore, the data signal input from the data line Data causes the voltage of the first node P1 to rise to a high level, thereby turning off the first driving transistor T13 and in a restored state.
  • a low level signal is input to the first scan line Gate1 and the second scan line Gate2, and the first to fourth transistors (T11, T21, T12, T22) are all turned off.
  • the voltage of the second node P2 is held low by the second capacitor C2, thereby keeping the second driving transistor T23 turned on.
  • a high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the second driving transistor T23, and the organic light emitting diode is kept driven to emit light.
  • the voltage of the first node P1 is maintained at a high level by the first capacitor C1. Therefore, the first driving transistor T13 is turned off and is in a recovery state.
  • the driving current of the organic light emitting diode is controlled only by the second driving transistor T23.
  • a low level signal is input to the first scan line Gate1, thereby turning off the first transistor T11 and the fourth transistor T22.
  • a high level signal is input to the second scan line Gate2, thereby turning on the second transistor T21 and the third transistor T12.
  • the first transistor T11 Since the first transistor T11 is turned off, the data signal (high level) input from the data line Data cannot be output to the first node P1 through the first transistor T11. At the same time, since the third transistor T12 is turned on, the low-level signal output from the first voltage signal terminal VSS lowers the voltage of the first node P1. When the voltage of the first node P1 falls to the threshold voltage Vth of the first driving transistor T13, the first driving transistor T13 is turned on. A high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the first driving transistor T13 to drive the organic light emitting diode to emit light.
  • the data signal (high level) input from the data line Data is output to the second node P2 through the second transistor T21.
  • the fourth transistor T22 since the fourth transistor T22 is turned off, the low level signal output from the first voltage signal terminal VSS does not affect the voltage of the second node P2. Therefore, the data signal input from the data line Data causes the voltage of the second node P2 to rise to a high level, thereby turning off the second driving transistor T23 and in a restored state.
  • a low level signal is input to the first scan line Gate1 and the second scan line Gate2, and the first to fourth transistors (T11, T21, T12, T22) are all turned off.
  • the voltage of the first node P1 is held low by the first capacitor C1, thereby keeping the first driving transistor T13 turned on.
  • a high level signal of the signal terminal VDD is output to the anode of the organic light emitting diode through the first driving transistor T13, and the organic light emitting diode is kept driven to emit light.
  • the voltage of the second node P2 is maintained at a high level by the second capacitor C2. Therefore, the second driving transistor T23 is turned off and is in a recovery state.
  • the driving current of the organic light emitting diode is controlled only by the first driving transistor T13.
  • the pixel circuit 100 then repeats the above four stages of operation.
  • the transistors in the drive control module 111 are all P-type transistors and the first drive module 112 and the second drive module 113 are The drive transistors are all N-type transistors.
  • the following is a detailed description of the operation of the pixel circuit 100 in this case, in which the first voltage signal terminal VSS outputs a low level signal, and the second voltage signal terminal VDD outputs a high level signal.
  • a low level signal is input to the first scan line Gate1, thereby turning on the first transistor T11 and the fourth transistor T22.
  • a high level signal is input to the second scan line Gate2, thereby turning off the second transistor T21 and the third transistor T12.
  • the data signal (high level) input from the data line Data is output to the first node P1 through the first transistor T11.
  • the third transistor T12 since the third transistor T12 is turned off, the low-level signal output from the first voltage signal terminal VSS does not affect the voltage of the first node P1. Therefore, the data signal input from the data line Data causes the voltage of the first node P1 to rise.
  • the first driving transistor T13 When the voltage of the first node P1 rises to the threshold voltage Vth of the first driving transistor T13, the first driving transistor T13 is turned on.
  • a high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the first driving transistor T13 to drive the organic light emitting diode to emit light.
  • the second driving transistor T23 is turned off and is in a recovery state.
  • first to first The four transistors (T11, T21, T12, T22) are all turned off.
  • the voltage of the first node P1 is maintained at a high level by the first capacitor C1, thereby keeping the first driving transistor T13 turned on.
  • a high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the first driving transistor T13, and the organic light emitting diode is kept driven to emit light.
  • the voltage of the second node P2 is maintained at a low level by the second capacitor C2. Therefore, the second driving transistor T23 is turned off and is in a recovery state.
  • the driving current of the organic light emitting diode is controlled only by the first driving transistor T13.
  • a high level signal is input to the first scan line Gate1, thereby turning off the first transistor T11 and the fourth transistor T22.
  • a low level signal is input to the second scan line Gate2, thereby turning on the second transistor T21 and the third transistor T12.
  • the data signal (high level) input from the data line Data is output to the second node P2 through the second transistor T21.
  • the fourth transistor T22 since the fourth transistor T22 is turned off, the low level signal output from the first voltage signal terminal VSS does not affect the voltage of the second node P2. Therefore, the data signal input from the data line Data causes the voltage of the second node P2 to rise.
  • the second driving transistor T23 When the voltage of the second node P2 rises to the threshold voltage Vth of the second driving transistor T23, the second driving transistor T23 is turned on.
  • a high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the second driving transistor T23 to drive the organic light emitting diode to emit light.
  • the first driving transistor T13 is turned off and is in a recovery state.
  • a high level signal is input to the first scan line Gate1 and the second scan line Gate2, and the first to fourth transistors (T11, T21, T12, T22) are all turned off.
  • the voltage of the second node P2 is maintained at a high level by the second capacitor C2, thereby keeping the second driving transistor T23 turned on.
  • a high level signal from the second voltage signal terminal VDD is output to the anode of the organic light emitting diode through the second driving transistor T23, and the organic light emitting diode is kept driven to emit light.
  • the voltage of the first node P1 is determined by the first electricity
  • the capacitor C1 is kept at a low level, and therefore, the first driving transistor T13 is turned off and is in a recovery state.
  • the driving current of the organic light emitting diode is controlled only by the second driving transistor T23.
  • the pixel circuit 100 then repeats the above four stages of operation.
  • FIG. 8 is a schematic flowchart of a driving method of driving the pixel circuit 100 shown in FIG. 1 according to an embodiment of the present disclosure.
  • step S802 in the first stage, an effective voltage signal is input to the first scan line, and an inactive voltage signal is input to the second scan line, so that the drive control module controls one of the first drive module and the second drive module to be turned on. .
  • step S804 in the second stage, the non-effective voltage signal is input to the first scan line and the second scan line, and one of the first driving module and the second driving module is turned on to drive the light emitting module to emit light.
  • step S806 in the third stage, the effective voltage signal is input to the second scan line, and the non-effective voltage signal is input to the first scan line, so that the drive control module controls the other of the first drive module and the second drive module. One is open.
  • step S808 in the fourth stage, the non-effective voltage signal is input to the first scan line and the second scan line, and the other of the first driving module and the second driving module is turned on to drive the light emitting module to emit light.
  • the transistors in the driving control module are all N-type transistors
  • the transistors in the first driving module and the second driving module are all N-type transistors
  • the effective voltage signal is a high level signal
  • the effective voltage signal is a low level signal.
  • step S802 in the first stage, a high level signal is input to the first scan line, and a low level signal is input to the second scan line, so that the drive control module controls only the first drive module to be turned on.
  • step S804 in the second stage, a low level signal is input to the first scan line and the second scan line, and only the first driving module is turned on to drive the light emitting module to emit light.
  • step S806 in the third stage, a low level signal is input to the first scan line, and a high level signal is input to the second scan line, so that the drive control module controls only the second drive module to open. start.
  • step S808 in the fourth stage, a low level signal is input to the first scan line and the second scan line, and only the second drive module is turned on to drive the light emitting module to emit light.
  • the transistors in the driving control module are all P-type transistors
  • the transistors in the first driving module and the second driving module are all P-type transistors
  • the effective voltage signal is a low-level signal
  • the effective voltage signal is a high level signal.
  • step S802 in the first stage, a low level signal is input to the first scan line, and a high level signal is input to the second scan line, so that the drive control module controls only the second drive module to be turned on.
  • step S804 in the second stage, a high level signal is input to the first scan line and the second scan line, and only the second drive module is turned on to drive the light emitting module to emit light.
  • step S806 in the third stage, a high level signal is input to the first scan line, and a low level signal is input to the second scan line, so that the drive control module controls only the first drive module to be turned on.
  • step S808 in the fourth stage, a high level signal is input to the first scan line and the second scan line, and only the first driving module is turned on to drive the light emitting module to emit light.
  • the transistors in the driving control module are all N-type transistors
  • the transistors in the first driving module and the second driving module are all P-type transistors
  • the effective voltage signal is a high level signal
  • the non-effective voltage signal is a low level signal.
  • step S802 in the first stage, a high level signal is input to the first scan line, and a low level signal is input to the second scan line, so that the drive control module controls only the second drive module to be turned on.
  • step S804 in the second stage, a low level signal is input to the first scan line and the second scan line, and only the second drive module is turned on to drive the light emitting module to emit light.
  • step S806 in the third stage, a low level signal is input to the first scan line, and a high level signal is input to the second scan line, so that the drive control module controls only the first drive module to be turned on.
  • step S808 in the fourth stage, the input to the first scan line and the second scan line is low.
  • the level signal is maintained and only the first driving module is turned on to drive the light emitting module to emit light.
  • the transistors in the driving control module are all P-type transistors
  • the transistors in the first driving module and the second driving module are all N-type transistors
  • the effective voltage signal is a low-level signal
  • the effective voltage signal is a high level signal.
  • step S802 in the first stage, a low level signal is input to the first scan line, and a high level signal is input to the second scan line, so that the drive control module controls only the first drive module to be turned on.
  • step S804 in the second stage, a high level signal is input to the first scan line and the second scan line, and only the first driving module is turned on to drive the light emitting module to emit light.
  • step S806 in the third stage, a high level signal is input to the first scan line, and a low level signal is input to the second scan line, so that the drive control module controls only the second drive module to be turned on.
  • step S808 in the fourth stage, a high level signal is input to the first scan line and the second scan line, and only the second drive module is turned on to drive the light emitting module to emit light.
  • the pixel circuit and the driving method thereof according to the embodiment of the present disclosure, the array substrate and the display panel, by alternately outputting the effective voltage signal by using the first scan line Gate1 and the second scan line Gate2, so that the first driving module
  • the driving transistors in the 112 and the second driving module 113 are alternately turned on or off, so that the first driving module 112 and the second driving module 113 alternately drive the light emitting module 120 to emit light.
  • the second driving module 113 is in a restored state
  • the driving of the second driving module 113 to drive the lighting module 120 the first driving module 112 is in a restored state.
  • the driving transistors in the first driving module 112 and the second driving module 113 may enter a recovery period after a period of operation, thereby reducing the threshold voltage Vth of the driving transistors in the first driving module 112 and the second driving module 113 and The change in mobility over time maintains the initial characteristics of the drive transistor, thereby extending the life of the display panel.
  • the display device provided by the embodiment of the present disclosure can be applied to any product having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, or a navigator.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, or a navigator.

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Abstract

一种像素驱动电路（110），包括驱动控制模块（111）、第一驱动模块（112）和第二驱动模块（113）。驱动控制模块（111）连接到数据线（Data）、第一扫描线（Gate1）、第二扫描线（Gate2）、第一电压信号端（Vss）、第一驱动模块（112）和第二驱动模块（113），并被配置为当第一扫描线（Gate1）输出有效电压信号时，控制第一驱动模块（112）和第二驱动模块（113）中的一者开启，以及当第二扫描线（Gate2）输出有效电压信号时，控制第一驱动模块（112）和第二驱动模块（113）中的另一者开启。第一驱动模块（112）连接到驱动控制模块（111）、第二电压信号端（VDD）和发光模块（120），并被配置为在驱动控制模块（111）的控制下驱动发光模块（120）发光。第二驱动模块（113）连接到驱动控制模块（111）、第二电压信号端（VDD）和发光模块（120），并被配置为在驱动控制模块（111）的控制下驱动发光模块（120）发光。

Description

像素驱动电路及像素驱动方法、阵列基板以及显示装置
相关申请的交叉引用
本申请要求于2016年09月14日递交的中国专利申请第201610825369.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，更具体地，涉及OLED像素驱动电路及像素驱动方法、阵列基板以及显示装置。
背景技术
随着显示技术的进步，相对于传统的液晶显示(Liquid Crystal Display，LCD)装置，新一代的有机发光二极管(Organic Light Emitting Diode，OLED)显示装置具有更低的制造成本，更快的反应速度，更高的对比度，更广的视角，更大的工作温度范围，不需要背光单元，色彩鲜艳及轻薄等优点，因此OLED显示技术成为当前发展最快的显示技术。
当前OLED的主流发展方向是通过改变直接驱动OLED发光的驱动晶体管的栅极电压，来控制驱动晶体管的源极与漏极之间电流的大小以实现发光亮度的变化，这就使得该驱动晶体管长时间处于工作状态，即其栅极一直维持正压或负压状态。因为现有的不同材料的薄膜晶体管(Thin Film Transistor，TFT)普遍具有在直流偏压下其阈值电压Vth、迁移率(Mobility)随时间推移而变化的特性(正压与负压的改变趋势相反)，所以OLED显示面板在工作一段时间后容易出现灰阶亮度变化、灰度不均(由于不同TFT的特性变化不同所导致)的现象。
发明内容
根据本公开的第一个方面，提供了一种像素驱动电路。该像素驱动电 路包括驱动控制模块、第一驱动模块以及第二驱动模块。驱动控制模块连接到数据线、第一扫描线、第二扫描线、第一电压信号端，并经由第一节点连接到第一驱动模块，经由第二节点连接到第二驱动模块，并被配置为当第一扫描线输出有效电压信号时，控制第一驱动模块和第二驱动模块中的一者开启，以及当第二扫描线输出有效电压信号时，控制第一驱动模块和第二驱动模块中的另一者开启；第一驱动模块连接到驱动控制模块、第二电压信号端和发光模块，并被配置为在驱动控制模块的控制下驱动发光模块发光。第二驱动模块连接到驱动控制模块、第二电压信号端和所述发光模块，并被配置为在驱动控制模块的控制下驱动所述发光模块发光。
在本公开的实施例中，第一扫描线和第二扫描线交替地输出有效电压信号。
在本公开的实施例中，驱动控制模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电容、第二电容。第一晶体管的控制极耦接到第一扫描线，第一晶体管的第一极耦接到数据线，第一晶体管的第二极耦接到第一节点。第二晶体管的控制极耦接到第二扫描线，第二晶体管的第一极耦接到数据线，第二晶体管的第二极耦接到第二节点。第三晶体管的控制极耦接到第二扫描线，第三晶体管的第一极耦接到第一电压信号端，第三晶体管的第二极耦接到第一节点。第四晶体管的控制极耦接到第一扫描线，第四晶体管的第一极耦接到第一电压信号端，第四晶体管的第二极耦接到第二节点。第一电容的第一端耦接到第一节点，第一电容的第二端耦接到第二电容的第二端。第二电容的第一端耦接到第二节点，第二电容的第二端耦接到第一电容的第二端。
在本公开的实施例中，第一驱动模块包括第一驱动晶体管，第一驱动晶体管的栅极耦接到第一节点，第一驱动晶体管的第一极耦接到第二电压信号端，第一驱动晶体管的第二极耦接到发光模块。
在本公开的实施例中，第二驱动模块包括第二驱动晶体管，第二驱动晶体管的栅极耦接到第二节点，第二驱动晶体管的第一极耦接到第二电压信号端，第二驱动晶体管的第二极耦接到发光模块。
在本公开的实施例中，驱动控制模块中的晶体管都为N型晶体管。
在本公开的实施例中，驱动控制模块中的晶体管都为P型晶体管。
在本公开的实施例中，第一驱动模块和第二驱动模块中的晶体管都为N型晶体管或者都为P型晶体管。
根据本公开的第二个方面，提供了一种像素电路，其包括如上所述的像素驱动电路和发光模块，其中，像素驱动电路与发光模块连接，并被配置为驱动发光模块发光。
在本公开的实施例中，发光模块包括有机发光二极管。
根据本公开的第三个方面，提供了一种阵列基板，其包括如上所述的像素电路。
根据本公开的第四个方面，提供了一种显示装置，其包括如上所述的阵列基板。
根据本公开的第五个方面，提供了一种用于驱动如上所述的像素电路的驱动方法，在该驱动方法中，在第一阶段，向第一扫描线输入有效电压信号，向第二扫描线输入非有效电压信号，以使得驱动控制模块控制第一驱动模块和第二驱动模块中的一者开启。在第二阶段，向第一扫描线和第二扫描线输入非有效电压信号，并由驱动控制模块维持第一驱动模块和第二驱动模块中的一者开启，驱动发光模块发光。在第三阶段，向第二扫描线输入有效电压信号，向第一扫描线输入非有效电压信号，以使得驱动控制模块控制第一驱动模块和第二驱动模块中的另一者开启。在第四阶段，向第一扫描线和第二扫描线输入非有效电压信号，并由驱动控制模块维持第一驱动模块和第二驱动模块中的另一者开启，驱动发光模块发光。
在本公开的实施例中，驱动控制模块中的晶体管都为N型晶体管，有效电压信号为高电平信号，以及非有效电压信号为低电平信号。
在本公开的实施例中，驱动控制模块中的晶体管都为P型晶体管，有效电压信号为低电平信号，以及非有效电压信号为高电平信号。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中：
图1是根据本公开的实施例的像素电路的示意性框图；
图2是根据本公开的实施例的像素电路的示例电路图；
图3是如图2所示的像素电路的各信号的时序图；
图4是如图2所示的像素电路的在第一阶段的等效工作电路图；
图5是如图2所示的像素电路的在第二阶段的等效工作电路图；
图6是如图2所示的像素电路的在第三阶段的等效工作电路图；
图7是如图2所示的像素电路的在第四阶段的等效工作电路图；
图8是根据本公开的实施例的驱动如图1所示的像素电路的驱动方法的示意性流程图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开保护的范围。
除非另外定义，否则在此使用的所有术语(包括技术和科学术语)具有与本公开主题所属的领域的技术人员所通常理解的相同含义。进一步将理解的是，诸如在通常使用的词典中定义的那些的术语应解释为具有与说明书上下文和相关技术中它们的含义一致的含义，并且将不以理想化或过于正式的形式来解释，除非在此另外明确定义。如在此所使用的，将两个或更多部分“连接”或“耦接”到一起的陈述应指该部分直接结合到一起或通过一个或多个中间部件结合。
在本公开的所有实施例中，由于晶体管的源极和漏极(发射极和集电 极)是对称的，并且N型晶体管和P型晶体管的源极和漏极(发射极和集电极)之间的导通电流方向相反，因此在本公开的实施例中，统一将晶体管的受控中间端称为控制极，信号输入端称为第一极，信号输出端称为第二极。本公开的实施例中所采用的晶体管主要是开关晶体管和驱动晶体管。另外，本公开的实施例中所采用的电容器也可以由具有类似功能的储能元件来代替。
图1示出根据本公开的实施例的像素电路100的示意性框图。如图1所示，像素电路100可包括像素驱动电路110和发光模块120。像素驱动电路110可包括驱动控制模块111、第一驱动模块112以及第二驱动模块113。驱动控制模块111可连接到数据线Data、第一扫描线Gate1、第二扫描线Gate2、第一电压信号端VSS，并经由第一节点P1连接到第一驱动模块112，经由第二节点P2连接到第二驱动模块113。驱动控制模块111可在第一扫描线Gate1输出有效电压信号时控制第一驱动模块112开启，以及在第二扫描线Gate2输出有效电压信号时控制第二驱动模块113开启。
在本实施例的替代实施例中，驱动控制模块111可在第一扫描线Gate1输出有效电压信号时控制第二驱动模块113开启，以及在第二扫描线Gate2输出有效电压信号时控制第一驱动模块112开启。
在本公开的实施例中，有效电压是指使晶体管导通的电压。在有效电压的情况下，晶体管工作，其能够将该晶体管的第一极的电压输出到其第二极。相应地，非有效电压是指使晶体管截止的电压。在非有效电压的情况下，晶体管不工作，其不能将该晶体管的第一极的电压输出到其第二极。
在本实施例及其替代实施例中，第一扫描线Gate1和第二扫描线Gate2交替输出有效电压信号，使得第一驱动模块112和第二驱动模块113中的驱动晶体管交替地导通或截止，从而使得第一驱动模块112和第二驱动模块113交替地驱动发光模块120发光。换句话说，在第一驱动模块112驱动发光模块120发光期间，第二驱动模块113处于恢复状态，以及在第二驱动模块113驱动发光模块120发光期间，第一驱动模块112处于恢复状态。第一驱动模块112和第二驱动模块113中的驱动晶体管均可以在工作 一段时间后进入恢复期，由此可以减少第一驱动模块112和第二驱动模块113中的驱动晶体管的阈值电压Vth和迁移率随时间推移的变化，维持驱动晶体管的初始特性，从而可以延长显示面板的使用寿命。
图2示出根据本公开的实施例的像素电路100的示例电路图。如图2所示，驱动控制模块111可包括第一晶体管T11、第二晶体管T21、第三晶体管T12、第四晶体管T22、第一电容C1和第二电容C2。第一晶体管T11的控制极耦接到第一扫描线Gate1，第一晶体管T11的第一极耦接到数据线Data，第一晶体管T11的第二极耦接到第一节点P1。第二晶体管T21的控制极耦接到第二扫描线Gate2，第二晶体管T21的第一极耦接到数据线Data，第二晶体管T21的第二极耦接到第二节点P2。第三晶体管T12的控制极耦接到第二扫描线Gate2，第三晶体管T12的第一极耦接到第一电压信号端VSS，第三晶体管T12的第二极耦接到第一节点P1。第四晶体管T22的控制极耦接到第一扫描线Gate1，第四晶体管T22的第一极耦接到第一电压信号端VSS，第四晶体管T22的第二极耦接到第二节点P2。第一电容C1的第一端耦接到第一节点P1，第一电容C1的第二端耦接到第二电容C2的第二端。第二电容C2的第一端耦接到第二节点P2，第二电容C2的第二端耦接到第一电容C1的第二端。
第一驱动模块112可包括第一驱动晶体管T13，第一驱动晶体管T13的栅极耦接到第一节点P1，第一驱动晶体管T13的第一极耦接到第二电压信号端VDD，第一驱动晶体管T13的第二极耦接到发光模块120。
第二驱动模块113可包括第二驱动晶体管T23，第二驱动晶体管T23的栅极耦接到第二节点P2，第二驱动晶体管T23的第一极耦接到第二电压信号端VDD，第二驱动晶体管T23的第二极耦接到发光模块120。
发光模块120可包括有机发光二极管。
如图2所示，在一个示例中，第一电容C1的第二端、第二电容C2的第二端、第一驱动晶体管T13的第二极和第二驱动晶体管T23的第二极共同耦接到有机发光二极管的阳极。有机发光二极管的阴极接地。
图3示出如图2所示的像素电路100的各信号的时序图。下面结合图 3所示的时序图，对如图2所示的像素电路100的工作过程进行详细描述。在以下的描述中，假定所有晶体管都是N型晶体管，第一电压信号端VSS输出低电平信号，第二电压信号端VDD输出高电平信号。
在第一阶段(像素电路100的等效工作电路如图4所示)，Gate1＝1，Gate2＝0，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1输入高电平信号，从而使第一晶体管T11和第四晶体管T22导通。向第二扫描线Gate2输入低电平信号，从而使第二晶体管T21和第三晶体管T12截止。
由于第一晶体管T11导通，从数据线Data输入的数据信号(高电平)通过第一晶体管T11输出到第一节点P1。同时由于第三晶体管T12截止，从第一电压信号端VSS输出的低电平信号不会影响第一节点P1的电压，因此从数据线Data输入的数据信号使第一节点P1的电压升高。当第一节点P1的电压上升至第一驱动晶体管T13的阈值电压Vth时，第一驱动晶体管T13导通。来自第二电压信号端VDD的高电平信号通过第一驱动晶体管T13输出到有机发光二极管的阳极，驱动有机发光二极管发光。
然而，由于第二晶体管T21截止，从数据线Data输入的数据信号(高电平)无法通过第二晶体管T21输出到第二节点P2。同时由于第四晶体管T22导通，从第一电压信号端VSS输出的低电平信号使第二节点P2的电压降为低电平。因此，第二驱动晶体管T23截止，并处于恢复状态。
在第二阶段(像素电路100的等效工作电路如图5所示)，Gate1＝0，Gate2＝0，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1和第二扫描线Gate2输入低电平信号，第一至第四晶体管(T11、T21、T12、T22)都截止。第一节点P1的电压由第一电容C1保持为高电平，从而保持第一驱动晶体管T13导通。来自第二电压信号端VDD的高电平信号通过第一驱动晶体管T13输出到有机发光二极管的阳极，保持驱动有机发光二极管发光。而第二节点P2的电压由第二电容C2保持为低电平，因此，第二驱动晶体管T23截止，并处于恢复状态。
也就是说，在第一和第二阶段，有机发光二极管的驱动电流仅由第一 驱动晶体管T13控制。
在第三阶段(像素电路100的等效工作电路如图6所示)，Gate1＝0，Gate2＝1，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1输入低电平信号，从而使第一晶体管T11和第四晶体管T22截止。向第二扫描线Gate2输入高电平信号，从而使第二晶体管T21和第三晶体管T12导通。
由于第二晶体管T21导通，从数据线Data输入的数据信号(高电平)通过第二晶体管T21输出到第二节点P2。同时由于第四晶体管T22截止，从第一电压信号端VSS输出的低电平信号不会影响第二节点P2的电压。因此从数据线Data输入的数据信号使第二节点P2的电压升高。当第二节点P2的电压上升至第二驱动晶体管T23的阈值电压Vth时，第二驱动晶体管T23导通。来自第二电压信号端VDD的高电平信号通过第二驱动晶体管T23输出到有机发光二极管的阳极，驱动有机发光二极管发光。
然而，由于第一晶体管T11截止，从数据线Data输入的数据信号(高电平)无法通过第一晶体管T11输出到第一节点P1。同时由于第三晶体管T12导通，从第一电压信号端VSS输出的低电平信号使第一节点P1的电压降为低电平。因此，第一驱动晶体管T13截止，并处于恢复状态。
在第四阶段(像素电路100的等效工作电路如图7所示)，Gate1＝0，Gate2＝0，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1和第二扫描线Gate2输入低电平信号，第一至第四晶体管(T11、T21、T12、T22)都截止。第二节点P2的电压由第二电容C2保持为高电平，从而保持第二驱动晶体管T23导通，来自第二电压信号端VDD的高电平信号通过第二驱动晶体管T23输出到有机发光二极管的阳极，保持驱动有机发光二极管发光。而第一节点P1的电压由第一电容C1保持为低电平，因此，第一驱动晶体管T13截止，并处于恢复状态。
也就是说，在第三和第四阶段，有机发光二极管的驱动电流仅由第二驱动晶体管T23控制。
然后像素电路100重复上述四个阶段的工作状态。
为了保持有机发光二极管在各个阶段在相同的数据电压下的发光亮度相同，在电路结构设计上可以选择结构参数完全相同的第一电容C1和第二电容C2，并且选择结构参数完全相同的第一驱动晶体管T13和第二驱动晶体管T23。也就是说，使得第一电容C1和第二电容C2的电容值相同(从而使得它们的充放电时间也相同)，并且使得第一驱动晶体管T13和第二驱动晶体管T23的沟道参数(宽度和长度)相同。
此外，本领域的技术人员应当知道，在本实施例的一个替代实施例中，如图2所示的像素电路100中的晶体管也可以都是P型晶体管。以下是对这种情况下的像素电路100的工作过程的详细描述，其中，第一电压信号端VSS输出低电平信号，第二电压信号端VDD输出高电平信号。
在第一阶段，Gate1＝0，Gate2＝1，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1输入低电平信号，从而使第一晶体管T11和第四晶体管T22导通。向第二扫描线Gate2输入高电平信号，从而使第二晶体管T21和第三晶体管T12截止。
由于第二晶体管T21截止，从数据线Data输入的数据信号(高电平)无法通过第二晶体管T21输出到第二节点P2。同时由于第四晶体管T22导通，从第一电压信号端VSS输出的低电平信号使第二节点P2的电压降低。当第二节点P2的电压下降至第二驱动晶体管T23的阈值电压Vth时，第二驱动晶体管T23导通。来自第二电压信号端VDD的高电平信号通过第二驱动晶体管T23输出到有机发光二极管的阳极，驱动有机发光二极管发光。
然而，由于第一晶体管T11导通，从数据线Data输入的数据信号(高电平)通过第一晶体管T11输出到第一节点P1。同时由于第三晶体管T12截止，从第一电压信号端VSS输出的低电平信号不会影响第一节点P1的电压。因此从数据线Data输入的数据信号使第一节点P1的电压升为高电平，从而使第一驱动晶体管T13截止，并处于恢复状态。
在第二阶段，Gate1＝1，Gate2＝1，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1和第二扫描线Gate2输入高电平信号，第一至第 四晶体管(T11、T21、T12、T22)都截止。第二节点P2的电压由第二电容C2保持为低电平，从而保持第二驱动晶体管T23导通。来自第二电压信号端VDD的高电平信号通过第二驱动晶体管T23输出到有机发光二极管的阳极，保持驱动有机发光二极管发光。而第一节点P1的电压由第一电容C1保持为高电平，因此，第一驱动晶体管T13截止，并处于恢复状态。
也就是说，在第一和第二阶段，有机发光二极管的驱动电流仅由第二驱动晶体管T23控制。
在第三阶段，Gate1＝1，Gate2＝0，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1输入高电平信号，从而使第一晶体管T11和第四晶体管T22截止。向第二扫描线Gate2输入低电平信号，从而使第二晶体管T21和第三晶体管T12导通。
由于第一晶体管T11截止，从数据线Data输入的数据信号(高电平)无法通过第一晶体管T11输出到第一节点P1。同时由于第三晶体管T12导通，从第一电压信号端VSS输出的低电平信号使第一节点P1的电压降低。当第一节点P1的电压的下降至第一驱动晶体管T13的阈值电压Vth时，第一驱动晶体管T13导通。来自第二电压信号端VDD的高电平信号通过第一驱动晶体管T13输出到有机发光二极管的阳极，驱动有机发光二极管发光。
然而，由于第二晶体管T21导通，从数据线Data输入的数据信号(高电平)通过第二晶体管T21输出到第二节点P2。同时由于第四晶体管T22截止，从第一电压信号端VSS输出的低电平信号不会影响第二节点P2的电压。因此从数据线Data输入的数据信号使第二节点P2的电压升为高电平，从而使第二驱动晶体管T23截止，并处于恢复状态。
在第四阶段，Gate1＝1，Gate2＝1，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1和第二扫描线Gate2输入高电平信号，第一至第四晶体管(T11、T21、T12、T22)都截止。第一节点P1的电压由第一电容C1保持为低电平，从而保持第一驱动晶体管T13导通。来自第二电压信号端VDD的高电平信号通过第一驱动晶体管T13输出到有机发光二极 管的阳极，保持驱动有机发光二极管发光。而第二节点P2的电压由第二电容C2保持为高电平，因此，第二驱动晶体管T23截止，并处于恢复状态。
也就是说，在第三和第四阶段，有机发光二极管的驱动电流仅由第一驱动晶体管T13控制。
然后像素电路100重复上述四个阶段的工作状态。
或者在本实施例的又一替代实施例中，在如图2所示的像素电路100中，驱动控制模块111中的晶体管都为N型晶体管而第一驱动模块112和第二驱动模块113中的驱动晶体管都为P型晶体管。以下是结合图3所示的时序图对这种情况下的像素电路100的工作过程的详细描述，其中，第一电压信号端VSS输出低电平信号，第二电压信号端VDD输出高电平信号。
在第一阶段，Gate1＝1，Gate2＝0，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1输入高电平信号，从而使第一晶体管T11和第四晶体管T22导通。向第二扫描线Gate2输入低电平信号，从而使第二晶体管T21和第三晶体管T12截止。
由于第二晶体管T21截止，从数据线Data输入的数据信号(高电平)无法通过第二晶体管T21输出到第二节点P2。同时由于第四晶体管T22导通，从第一电压信号端VSS输出的低电平信号使第二节点P2的电压降低。当第二节点P2的电压下降至第二驱动晶体管T23的阈值电压Vth时，第二驱动晶体管T23导通。来自第二电压信号端VDD的高电平信号通过第二驱动晶体管T23输出到有机发光二极管的阳极，驱动有机发光二极管发光。
然而，由于第一晶体管T11导通，从数据线Data输入的数据信号(高电平)通过第一晶体管T11输出到第一节点P1。同时由于第三晶体管T12截止，从第一电压信号端VSS输出的低电平信号不会影响第一节点P1的电压。因此从数据线Data输入的数据信号使第一节点P1的电压升为高电平，从而使第一驱动晶体管T13截止，并处于恢复状态。
在第二阶段，Gate1＝0，Gate2＝0，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1和第二扫描线Gate2输入低电平信号，第一至第四晶体管(T11、T21、T12、T22)都截止。第二节点P2的电压由第二电容C2保持为低电平，从而保持第二驱动晶体管T23导通。来自第二电压信号端VDD的高电平信号通过第二驱动晶体管T23输出到有机发光二极管的阳极，保持驱动有机发光二极管发光。而第一节点P1的电压由第一电容C1保持为高电平，因此，第一驱动晶体管T13截止，并处于恢复状态。
也就是说，在第一和第二阶段，有机发光二极管的驱动电流仅由第二驱动晶体管T23控制。
在第三阶段，Gate1＝0，Gate2＝1，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1输入低电平信号，从而使第一晶体管T11和第四晶体管T22截止。向第二扫描线Gate2输入高电平信号，从而使第二晶体管T21和第三晶体管T12导通。
由于第一晶体管T11截止，从数据线Data输入的数据信号(高电平)无法通过第一晶体管T11输出到第一节点P1。同时由于第三晶体管T12导通，从第一电压信号端VSS输出的低电平信号使第一节点P1的电压降低。当第一节点P1的电压的下降至第一驱动晶体管T13的阈值电压Vth时，第一驱动晶体管T13导通。来自第二电压信号端VDD的高电平信号通过第一驱动晶体管T13输出到有机发光二极管的阳极，驱动有机发光二极管发光。
然而，由于第二晶体管T21导通，从数据线Data输入的数据信号(高电平)通过第二晶体管T21输出到第二节点P2。同时由于第四晶体管T22截止，从第一电压信号端VSS输出的低电平信号不会影响第二节点P2的电压。因此从数据线Data输入的数据信号使第二节点P2的电压升为高电平，从而使第二驱动晶体管T23截止，并处于恢复状态。
在第四阶段，Gate1＝0，Gate2＝0，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1和第二扫描线Gate2输入低电平信号，第一至第四晶体管(T11、T21、T12、T22)都截止。第一节点P1的电压由第一电容C1保持为低电平，从而保持第一驱动晶体管T13导通。来自第二电压 信号端VDD的高电平信号通过第一驱动晶体管T13输出到有机发光二极管的阳极，保持驱动有机发光二极管发光。而第二节点P2的电压由第二电容C2保持为高电平，因此，第二驱动晶体管T23截止，并处于恢复状态。
也就是说，在第三和第四阶段，有机发光二极管的驱动电流仅由第一驱动晶体管T13控制。
然后像素电路100重复上述四个阶段的工作状态。
或者在本实施例的再一替代实施例中，在如图2所示的像素电路100中，驱动控制模块111中的晶体管都为P型晶体管而第一驱动模块112和第二驱动模块113中的驱动晶体管都为N型晶体管。以下是对这种情况下的像素电路100的工作过程的详细描述，其中，第一电压信号端VSS输出低电平信号，第二电压信号端VDD输出高电平信号。
在第一阶段，Gate1＝0，Gate2＝1，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1输入低电平信号，从而使第一晶体管T11和第四晶体管T22导通。向第二扫描线Gate2输入高电平信号，从而使第二晶体管T21和第三晶体管T12截止。
由于第一晶体管T11导通，从数据线Data输入的数据信号(高电平)通过第一晶体管T11输出到第一节点P1。同时由于第三晶体管T12截止，从第一电压信号端VSS输出的低电平信号不会影响第一节点P1的电压。因此从数据线Data输入的数据信号使第一节点P1的电压升高。当第一节点P1的电压上升至第一驱动晶体管T13的阈值电压Vth时，第一驱动晶体管T13导通。来自第二电压信号端VDD的高电平信号通过第一驱动晶体管T13输出到有机发光二极管的阳极，驱动有机发光二极管发光。
然而，由于第二晶体管T21截止，从数据线Data输入的数据信号(高电平)无法通过第二晶体管T21输出到第二节点P2。同时由于第四晶体管T22导通，从第一电压信号端VSS输出的低电平信号使第二节点P2的电压降为低电平。因此，第二驱动晶体管T23截止，并处于恢复状态。
在第二阶段，Gate1＝1，Gate2＝1，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1和第二扫描线Gate2输入高电平信号，第一至第 四晶体管(T11、T21、T12、T22)都截止。第一节点P1的电压由第一电容C1保持为高电平，从而保持第一驱动晶体管T13导通。来自第二电压信号端VDD的高电平信号通过第一驱动晶体管T13输出到有机发光二极管的阳极，保持驱动有机发光二极管发光。而第二节点P2的电压由第二电容C2保持为低电平，因此，第二驱动晶体管T23截止，并处于恢复状态。
也就是说，在第一和第二阶段，有机发光二极管的驱动电流仅由第一驱动晶体管T13控制。
在第三阶段，Gate1＝1，Gate2＝0，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1输入高电平信号，从而使第一晶体管T11和第四晶体管T22截止。向第二扫描线Gate2输入低电平信号，从而使第二晶体管T21和第三晶体管T12导通。
由于第二晶体管T21导通，从数据线Data输入的数据信号(高电平)通过第二晶体管T21输出到第二节点P2。同时由于第四晶体管T22截止，从第一电压信号端VSS输出的低电平信号不会影响第二节点P2的电压。因此从数据线Data输入的数据信号使第二节点P2的电压升高。当第二节点P2的电压上升至第二驱动晶体管T23的阈值电压Vth时，第二驱动晶体管T23导通。来自第二电压信号端VDD的高电平信号通过第二驱动晶体管T23输出到有机发光二极管的阳极，驱动有机发光二极管发光。
然而，由于第一晶体管T11截止，从数据线Data输入的数据信号(高电平)无法通过第一晶体管T11输出到第一节点P1。同时由于第三晶体管T12导通，从第一电压信号端VSS输出的低电平信号使第一节点P1的电压降为低电平。因此，第一驱动晶体管T13截止，并处于恢复状态。
在第四阶段，Gate1＝1，Gate2＝1，Data＝1，VDD＝1，VSS＝0。
向第一扫描线Gate1和第二扫描线Gate2输入高电平信号，第一至第四晶体管(T11、T21、T12、T22)都截止。第二节点P2的电压由第二电容C2保持为高电平，从而保持第二驱动晶体管T23导通。来自第二电压信号端VDD的高电平信号通过第二驱动晶体管T23输出到有机发光二极管的阳极，保持驱动有机发光二极管发光。而第一节点P1的电压由第一电 容C1保持为低电平，因此，第一驱动晶体管T13截止，并处于恢复状态。
也就是说，在第三和第四阶段，有机发光二极管的驱动电流仅由第二驱动晶体管T23控制。
然后像素电路100重复上述四个阶段的工作状态。
图8是根据本公开的实施例的驱动如图1所示的像素电路100的驱动方法的示意性流程图。
在步骤S802，在第一阶段，向第一扫描线输入有效电压信号，向第二扫描线输入非有效电压信号，以使得驱动控制模块控制第一驱动模块和第二驱动模块中的一者开启。
接着，在步骤S804，在第二阶段，向第一扫描线和第二扫描线输入非有效电压信号，并维持第一驱动模块和第二驱动模块中的一者开启，驱动发光模块发光。
然后，在步骤S806，在第三阶段，向第二扫描线输入有效电压信号，向第一扫描线输入非有效电压信号，以使得驱动控制模块控制第一驱动模块和第二驱动模块中的另一者开启。
最后，在步骤S808，在第四阶段，向第一扫描线和第二扫描线输入非有效电压信号，并维持第一驱动模块和第二驱动模块中的另一者开启，驱动发光模块发光。
在本实施例的一个示例中，驱动控制模块中的晶体管都为N型晶体管，第一驱动模块和第二驱动模块中的晶体管都为N型晶体管，并且有效电压信号为高电平信号，非有效电压信号为低电平信号。可进一步对像素驱动方法进行如下详细描述。
在步骤S802，在第一阶段，向第一扫描线输入高电平信号，向第二扫描线输入低电平信号，以使得驱动控制模块控制仅第一驱动模块开启。
接着，在步骤S804，在第二阶段，向第一扫描线和第二扫描线输入低电平信号，并维持仅第一驱动模块开启，驱动发光模块发光。
然后，在步骤S806，在第三阶段，向第一扫描线输入低电平信号，向第二扫描线输入高电平信号，以使得驱动控制模块控制仅第二驱动模块开 启。
最后，在步骤S808，在第四阶段，向第一扫描线和第二扫描线输入低电平信号，并维持仅第二驱动模块开启，驱动发光模块发光。
在本实施例的一个示例中，驱动控制模块中的晶体管都为P型晶体管，第一驱动模块和第二驱动模块中的晶体管都为P型晶体管，并且有效电压信号为低电平信号，非有效电压信号为高电平信号。可进一步对像素驱动方法进行如下详细描述。
在步骤S802，在第一阶段，向第一扫描线输入低电平信号，向第二扫描线输入高电平信号，以使得驱动控制模块控制仅第二驱动模块开启。
接着，在步骤S804，在第二阶段，向第一扫描线和第二扫描线输入高电平信号，并维持仅第二驱动模块开启，驱动发光模块发光。
然后，在步骤S806，在第三阶段，向第一扫描线输入高电平信号，向第二扫描线输入低电平信号，以使得驱动控制模块控制仅第一驱动模块开启。
最后，在步骤S808，在第四阶段，向第一扫描线和第二扫描线输入高电平信号，并维持仅第一驱动模块开启，驱动发光模块发光。
在本实施例的一个示例中，驱动控制模块中的晶体管都为N型晶体管，第一驱动模块和第二驱动模块中的晶体管都为P型晶体管，并且有效电压信号为高电平信号，以及非有效电压信号为低电平信号。可进一步对像素驱动方法进行如下详细描述。
在步骤S802，在第一阶段，向第一扫描线输入高电平信号，向第二扫描线输入低电平信号，以使得驱动控制模块控制仅第二驱动模块开启。
接着，在步骤S804，在第二阶段，向第一扫描线和第二扫描线输入低电平信号，并维持仅第二驱动模块开启，驱动发光模块发光。
然后，在步骤S806，在第三阶段，向第一扫描线输入低电平信号，向第二扫描线输入高电平信号，以使得驱动控制模块控制仅第一驱动模块开启。
最后，在步骤S808，在第四阶段，向第一扫描线和第二扫描线输入低 电平信号，并维持仅第一驱动模块开启，驱动发光模块发光。
在本实施例的一个示例中，驱动控制模块中的晶体管都为P型晶体管，第一驱动模块和第二驱动模块中的晶体管都为N型晶体管，并且有效电压信号为低电平信号，非有效电压信号为高电平信号。可进一步对像素驱动方法进行如下详细描述。
在步骤S802，在第一阶段，向第一扫描线输入低电平信号，向第二扫描线输入高电平信号，以使得驱动控制模块控制仅第一驱动模块开启。
接着，在步骤S804，在第二阶段，向第一扫描线和第二扫描线输入高电平信号，并维持仅第一驱动模块开启，驱动发光模块发光。
然后，在步骤S806，在第三阶段，向第一扫描线输入高电平信号，向第二扫描线输入低电平信号，以使得驱动控制模块控制仅第二驱动模块开启。
最后，在步骤S808，在第四阶段，向第一扫描线和第二扫描线输入高电平信号，并维持仅第二驱动模块开启，驱动发光模块发光。
从以上描述可以看出，根据本公开实施例的像素电路及其驱动方法，阵列基板以及显示面板，通过利用第一扫描线Gate1和第二扫描线Gate2交替输出有效电压信号，使得第一驱动模块112和第二驱动模块113中的驱动晶体管交替地导通或截止，从而使得第一驱动模块112和第二驱动模块113交替地驱动发光模块120发光。换句话说，在第一驱动模块112驱动发光模块120发光期间，第二驱动模块113处于恢复状态，以及在第二驱动模块113驱动发光模块120发光期间，第一驱动模块112处于恢复状态。第一驱动模块112和第二驱动模块113中的驱动晶体管均可以在工作一段时间后进入恢复期，由此可以减少第一驱动模块112和第二驱动模块113中的驱动晶体管的阈值电压Vth和迁移率随时间推移的变化，维持驱动晶体管的初始特性，从而可以延长显示面板的使用寿命。
本公开实施例提供的显示装置可以应用于任何具有显示功能的产品，例如，电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框或导航仪等。
除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中明确禁止这样的解释。在本文中使用术语“示例”之处，特别是当其位于一组术语之后时，所述“示例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其它方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
以上对本公开的若干实施例进行了详细描述，但显然，本领域技术人员可以在不脱离本公开的精神和范围的情况下对本公开的实施例进行各种修改和变型。本公开的保护范围由所附的权利要求限定。

Claims (10)

  1. 一种像素驱动电路，包括驱动控制模块、第一驱动模块以及第二驱动模块，
    其中，所述驱动控制模块连接到数据线、第一扫描线、第二扫描线、第一电压信号端，并经由第一节点连接到所述第一驱动模块，经由第二节点连接到所述第二驱动模块，并被配置为当所述第一扫描线输出有效电压信号时，控制所述第一驱动模块和所述第二驱动模块中的一者开启，以及当所述第二扫描线输出有效电压信号时，控制所述第一驱动模块和所述第二驱动模块中的另一者开启；
    所述第一驱动模块连接到所述驱动控制模块、第二电压信号端和发光模块，并被配置为在所述驱动控制模块的控制下驱动所述发光模块发光；
    所述第二驱动模块连接到所述驱动控制模块、所述第二电压信号端和所述发光模块，并被配置为在所述驱动控制模块的控制下驱动所述发光模块发光。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一扫描线和所述第二扫描线交替地输出有效电压信号。
  3. 根据权利要求1或2所述的像素驱动电路，其中，所述驱动控制模块包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电容和第二电容，
    其中，所述第一晶体管的控制极耦接到所述第一扫描线，所述第一晶体管的第一极耦接到所述数据线，所述第一晶体管的第二极耦接到所述第一节点；
    所述第二晶体管的控制极耦接到所述第二扫描线，所述第二晶体管的第一极耦接到所述数据线，所述第二晶体管的第二极耦接到所述第二节点；
    所述第三晶体管的控制极耦接到所述第二扫描线，所述第三晶体管的第一极耦接到所述第一电压信号端，所述第三晶体管的第二极耦接到所述第一节点；
    所述第四晶体管的控制极耦接到所述第一扫描线，所述第四晶体管的 第一极耦接到所述第一电压信号端，所述第四晶体管的第二极耦接到所述第二节点；
    所述第一电容的第一端耦接到所述第一节点，所述第一电容的第二端耦接到所述第二电容的第二端；
    所述第二电容的第一端耦接到所述第二节点，所述第二电容的第二端耦接到所述第一电容的第二端。
  4. 根据权利要求1所述的像素驱动电路，其中，所述第一驱动模块包括第一驱动晶体管，所述第一驱动晶体管的栅极耦接到所述第一节点，所述第一驱动晶体管的第一极耦接到所述第二电压信号端，所述第一驱动晶体管的第二极耦接到所述发光模块。
  5. 根据权利要求1所述的像素驱动电路，其中，所述第二驱动模块包括第二驱动晶体管，所述第二驱动晶体管的栅极耦接到所述第二节点，所述第二驱动晶体管的第一极耦接到所述第二电压信号端，所述第二驱动晶体管的第二极耦接到所述发光模块。
  6. 一种像素电路，包括：如权利要求1至5中任一项所述的像素驱动电路和发光模块，其中，所述像素驱动电路与所述发光模块连接，并被配置为驱动所述发光模块发光。
  7. 根据权利要求6所述的像素电路，其中，所述发光模块包括有机发光二极管。
  8. 一种阵列基板，包括如权利要求6或7所述的像素电路。
  9. 一种显示装置，包括如权利要求8所述的阵列基板。
  10. 一种用于驱动如权利要求6或7所述的像素电路的驱动方法，包括：
    在第一阶段，向所述第一扫描线输入有效电压信号，向所述第二扫描线输入非有效电压信号，以使得所述驱动控制模块控制所述第一驱动模块和所述第二驱动模块中的一者开启；
    在第二阶段，向所述第一扫描线和所述第二扫描线输入非有效电压信号，并由所述驱动控制模块维持所述第一驱动模块和所述第二驱动模块中 的所述一者开启，驱动所述发光模块发光；
    在第三阶段，向所述第二扫描线输入有效电压信号，向所述第一扫描线输入非有效电压信号，以使得所述驱动控制模块控制所述第一驱动模块和所述第二驱动模块中的另一者开启；
    在第四阶段，向所述第一扫描线和所述第二扫描线输入非有效电压信号，并由所述驱动控制模块维持所述第一驱动模块和所述第二驱动模块中的所述另一者开启，驱动所述发光模块发光。
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106782331B (zh) * 2016-12-27 2023-07-18 京东方科技集团股份有限公司 一种像素电路、其驱动方法、显示面板及显示装置
KR102347796B1 (ko) * 2017-05-31 2022-01-07 엘지디스플레이 주식회사 전계 발광 표시장치
CN111402782B (zh) * 2018-12-14 2021-09-03 成都辰显光电有限公司 一种数字驱动像素电路及数字驱动像素的方法
CN110047435B (zh) * 2019-04-23 2020-12-04 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板和显示装置
CN110189691B (zh) * 2019-05-14 2021-03-16 深圳市华星光电半导体显示技术有限公司 像素驱动电路及显示面板
CN110459164B (zh) * 2019-07-26 2020-12-08 深圳市华星光电半导体显示技术有限公司 像素驱动电路及显示装置
TWI735338B (zh) * 2020-09-16 2021-08-01 友達光電股份有限公司 畫素驅動電路
CN113851072B (zh) * 2020-10-12 2024-05-10 友达光电股份有限公司 驱动电路
CN112331150A (zh) * 2020-11-05 2021-02-05 Tcl华星光电技术有限公司 显示装置及发光面板
CN112542144A (zh) * 2020-12-02 2021-03-23 Tcl华星光电技术有限公司 面板驱动电路和显示面板
CN112785961A (zh) * 2021-03-11 2021-05-11 深圳市华星光电半导体显示技术有限公司 像素驱动电路及显示面板
CN113674677B (zh) * 2021-08-09 2023-12-19 Tcl华星光电技术有限公司 显示面板及显示装置
CN114387926B (zh) * 2022-02-24 2024-04-09 合肥京东方显示技术有限公司 像素电路及其驱动方法、显示装置
CN115331619B (zh) * 2022-10-12 2023-01-31 惠科股份有限公司 像素驱动电路、显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101231822A (zh) * 2007-01-26 2008-07-30 Lg.菲利浦Lcd株式会社 有机发光二极管显示器件及其驱动方法
US20090079725A1 (en) * 2007-09-25 2009-03-26 Kabushiki Kaisha Toshiba Display device and method for driving the same
US20090096725A1 (en) * 2006-04-28 2009-04-16 Thales Organic electroluminescent display
CN101937647A (zh) * 2010-09-02 2011-01-05 上海交通大学 互补驱动式像素电路
CN102054436A (zh) * 2010-12-28 2011-05-11 友达光电股份有限公司 有源矩阵有机发光二极管显示器的像素电路
CN104021763A (zh) * 2014-06-11 2014-09-03 合肥鑫晟光电科技有限公司 像素电路、显示装置和像素电路的驱动方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3613253B2 (ja) * 2002-03-14 2005-01-26 日本電気株式会社 電流制御素子の駆動回路及び画像表示装置
KR100568597B1 (ko) * 2004-03-25 2006-04-07 엘지.필립스 엘시디 주식회사 일렉트로-루미네센스 표시장치와 그의 구동방법
KR101066414B1 (ko) * 2004-05-19 2011-09-21 재단법인서울대학교산학협력재단 유기발광소자의 구동소자 및 구동방법과, 이를 갖는표시패널 및 표시장치
KR101245218B1 (ko) * 2006-06-22 2013-03-19 엘지디스플레이 주식회사 유기발광다이오드 표시소자
CN102446489B (zh) * 2011-12-23 2013-08-21 深圳丹邦投资集团有限公司 一种像素电路及其驱动方法
CN203250518U (zh) * 2013-05-31 2013-10-23 京东方科技集团股份有限公司 像素电路、有机发光显示面板及显示装置
CN104252845B (zh) * 2014-09-25 2017-02-15 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置
CN104464638B (zh) * 2014-12-29 2017-05-10 合肥鑫晟光电科技有限公司 像素驱动电路、驱动方法、阵列基板和显示设备
CN104732929A (zh) * 2015-04-16 2015-06-24 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN105609047B (zh) * 2016-01-04 2018-05-18 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090096725A1 (en) * 2006-04-28 2009-04-16 Thales Organic electroluminescent display
CN101231822A (zh) * 2007-01-26 2008-07-30 Lg.菲利浦Lcd株式会社 有机发光二极管显示器件及其驱动方法
US20090079725A1 (en) * 2007-09-25 2009-03-26 Kabushiki Kaisha Toshiba Display device and method for driving the same
CN101937647A (zh) * 2010-09-02 2011-01-05 上海交通大学 互补驱动式像素电路
CN102054436A (zh) * 2010-12-28 2011-05-11 友达光电股份有限公司 有源矩阵有机发光二极管显示器的像素电路
CN104021763A (zh) * 2014-06-11 2014-09-03 合肥鑫晟光电科技有限公司 像素电路、显示装置和像素电路的驱动方法

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