WO2017118055A1 - 像素驱动电路、像素驱动方法、显示面板和显示装置 - Google Patents

像素驱动电路、像素驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2017118055A1
WO2017118055A1 PCT/CN2016/097184 CN2016097184W WO2017118055A1 WO 2017118055 A1 WO2017118055 A1 WO 2017118055A1 CN 2016097184 W CN2016097184 W CN 2016097184W WO 2017118055 A1 WO2017118055 A1 WO 2017118055A1
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Prior art keywords
transistor
phase
storage capacitor
pole
compensation
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PCT/CN2016/097184
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English (en)
French (fr)
Inventor
马占洁
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京东方科技集团股份有限公司
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Priority to US15/519,961 priority Critical patent/US10262594B2/en
Publication of WO2017118055A1 publication Critical patent/WO2017118055A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
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    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/145—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen
    • G09G2360/147—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen the originated light output being determined for each pixel
    • G09G2360/148—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen the originated light output being determined for each pixel the light being detected by light detection means within each pixel

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a pixel driving method, a display panel, and a display device.
  • AMOLED active-matrix organic light emitting diode
  • OLED Organic Light-Emitting Diode
  • the Vth Shift threshold voltage drift
  • the drift of the TFT characteristics caused by the long-time bias voltage are applied, and the AMOLED compensation circuit design is performed.
  • the signal line load is increased, resulting in voltage attenuation on the power signal line, thereby affecting the uniformity of current in the display area.
  • the existing OLED compensation circuit As the efficiency of the light-emitting device increases, the required driving data voltage range will be reduced, which will exceed the driving capability of the driving IC (Integrated Circuit).
  • the existing pixel driving circuit cannot achieve different compression ratios of data, and the data driving range of the driving IC cannot be improved.
  • a main object of the present disclosure is to provide a pixel driving circuit, a method, a display panel, and a display device to solve the problem that different compression ratios of data cannot be realized in the prior art, thereby improving the data driving range of the driving IC.
  • the present disclosure provides a pixel driving circuit including a driving transistor, a first storage capacitor, a second storage capacitor, a threshold compensation unit, a data writing unit, and a lighting control sheet.
  • a gate of the driving transistor is connected to a first end of the first storage capacitor, and a first pole of the driving transistor is connected to a second end of the first storage capacitor;
  • the first end of the second storage capacitor is connected to the first power supply voltage, and the second end of the second storage capacitor is connected to the second end of the first storage capacitor;
  • the threshold compensation unit is configured to control a gate of the driving transistor to access a reference voltage during a threshold compensation phase of each display period, and a second electrode of the driving transistor is connected to a reset voltage line, thereby causing a driving transistor to be turned on Discharging the reset voltage line until the drive transistor is turned off;
  • the data writing unit is configured to control a data voltage to be written into a gate of the driving transistor during a data writing phase of each display period;
  • the illumination control unit is configured to control a first power voltage to access a first pole of the driving transistor during a lighting phase of each display period, and control a second pole of the driving transistor to be connected to the light emitting component to control the driving transistor Passing to drive the light emitting element to emit light;
  • the total amount of charge of the first storage capacitor and the total amount of charge of the second storage capacitor are equal in the threshold compensation phase and the data writing phase;
  • the amount of charge of the first storage capacitor in the data writing phase is equal to the amount of charge of the first storage capacitor in the light emission control phase.
  • the threshold compensation phase further includes a reset phase during each display period
  • the threshold compensation unit is further configured to control a gate of the driving transistor to access a reference voltage in the reset phase and a second pole of the driving transistor to be connected to a reset voltage;
  • the illumination control unit is further configured to control, in the resetting phase, the first pole of the driving transistor to be connected to the first power voltage, and control the second pole of the driving transistor to be connected to the light emitting component;
  • the drive transistor is in an amplified state or a saturated state during the reset phase.
  • the light emitting element comprises an organic light emitting diode
  • the anode of the organic light emitting diode is connected to the second pole of the driving transistor through the light emitting control unit, and the cathode of the organic light emitting diode is connected to the second power voltage;
  • a voltage difference between a reset voltage output by the reset voltage line and the second power voltage is less than an turn-on threshold voltage of the organic light emitting diode.
  • the threshold compensation unit includes a first compensation transistor and a second compensation transistor, in,
  • a gate of the first compensation transistor is connected to a reset control signal, a first pole of the first compensation transistor is connected to a second pole of the driving transistor, and a second pole of the first compensation transistor is coupled to the reset Voltage line connection
  • a gate of the second compensation transistor is connected to the reset control signal, a first pole of the second compensation transistor is connected to a gate of the driving transistor, and a second pole of the second compensation transistor is connected to The reference voltage is described.
  • the data write unit includes a data write transistor
  • the gate of the data write transistor is connected to the scan signal, the first pole of the data write transistor is connected to the gate of the drive transistor, and the second pole of the data write transistor is connected to the data voltage.
  • the illumination control unit includes a first illumination control transistor and a second illumination control transistor, wherein
  • a gate of the first illumination control transistor is coupled to the illumination control signal, a first pole of the first illumination control transistor is coupled to the first supply voltage, and a second pole of the first illumination control transistor is Driving the first pole of the transistor;
  • a gate of the second light emission control transistor is connected to the light emission control signal, a first electrode of the second light emission control transistor is connected to a second electrode of the driving transistor, and a second electrode of the second light emission control transistor The pole is connected to the light emitting element.
  • the first compensation transistor and the second compensation transistor are P-type transistors.
  • the write transistor is a P-type transistor.
  • the first illumination control transistor and the second illumination control transistor are P-type transistors.
  • the present disclosure also provides a pixel driving method, which is applied to the above pixel driving circuit, and the pixel driving method includes:
  • the threshold compensation unit controls the gate of the driving transistor to access the reference voltage and the second electrode of the driving transistor is connected to the reset voltage line, thereby causing the driving transistor to be turned on to discharge to the initial voltage line. Until the drive transistor is turned off;
  • the data write unit controls the data voltage write drive during the data write phase of each display cycle
  • the gate of the transistor
  • the light emission control unit controls the first pole of the first power voltage driving transistor, and controls the second pole of the driving transistor to be connected with the light emitting element to control the driving transistor to be turned on to drive the light emitting element to emit light;
  • the total amount of charge of the first storage capacitor and the second storage capacitor is equal in the threshold compensation phase and the data writing phase;
  • the amount of charge of the first storage capacitor in the data writing phase is equal to the amount of charge of the first storage capacitor in the light emitting phase.
  • each display period further includes a reset phase in the threshold compensation phase time; the pixel driving method further includes:
  • a threshold compensation unit controls a gate of the driving transistor to access a reference voltage
  • a second electrode of the driving transistor is connected to a reset voltage line
  • an emission control unit controls the first of the driving transistor
  • the pole is connected to the first power voltage
  • the second pole of the driving transistor is controlled to be connected to the light emitting element
  • the drive transistor is in an amplified state or a saturated state during the reset phase.
  • the present disclosure also provides a pixel driving method, which is applied to the above pixel driving circuit, and the pixel driving method includes:
  • the illumination control signal and the scan signal are both off signals
  • the reset control signal is an on signal
  • the reset voltage line outputs a low potential reset voltage
  • the first illumination control transistor and the second illumination control transistor Shutdown, both the first compensation transistor and the second compensation transistor are turned on, and the charge held at the first storage capacitor and the second storage capacitor connection node is discharged to the reset voltage line through the driving transistor and the first compensation transistor until The source potential of the driving transistor is low enough to turn off the driving transistor;
  • the illumination control signal and the reset control signal are both off signals
  • the scan signal is an on signal
  • the first illumination control transistor and the second illumination control transistor are both turned off
  • the first compensation transistor and The second compensation transistor is turned off
  • the data write transistor is turned on, the data voltage is written to the gate of the drive transistor
  • the connection node of the first storage capacitor and the second storage capacitor is in a floating state, the first storage capacitor and the The total amount of charge of the second storage capacitor is equal to the threshold compensation phase and the data writing phase;
  • the scan signal and the reset control signal are both off signals, so that the first compensation transistor, the second compensation transistor and the data write transistor are both turned off, and the illumination control signal is an on signal, so that the first The light-emitting control transistor and the second light-emitting control transistor are both turned on, such that the light-emitting element is connected to the second pole of the driving transistor, and the first power-supply voltage is written to the junction of the first pole of the driving transistor and the first storage capacitor and the second storage capacitor
  • the first end of the second storage capacitor is connected to the first power supply voltage, the connection node of the first storage capacitor and the gate of the driving transistor is in a floating state, and the amount of charge of the first storage capacitor in the data writing phase
  • the amount of charge of the first storage capacitor in the light emission control phase is equal, such that a current flowing through the driving transistor in the light emitting phase is only related to the data voltage, a capacitance value of the first storage capacitor, and the second The capacitance value of the storage capacitor is related
  • each display period further includes a reset phase in the threshold compensation phase time; the pixel driving method further includes:
  • the illumination control signal and the reset control signal are both on signals
  • the scan signal is a shutdown signal
  • the first illumination control transistor and the second illumination control transistor are both turned on
  • the first compensation transistor and the second compensation The transistor is also turned on
  • the data writing transistor is turned off
  • the light emitting element is connected to the second electrode of the driving transistor
  • the reset voltage is written to the second electrode of the driving transistor, and the driving transistor is in an amplified state or a saturated state.
  • the light emitting element comprises an organic light emitting diode
  • an anode of the organic light emitting diode is connected to a second pole of the driving transistor through the light emitting control unit, and a cathode of the organic light emitting diode is connected to a second power voltage
  • a voltage difference between a reset voltage output by the reset voltage line and the second power voltage is less than an turn-on threshold voltage of the organic light emitting diode.
  • the present disclosure also provides a display panel including the above pixel driving circuit.
  • the present disclosure also provides a display device including the above display panel.
  • the pixel driving circuit, the method, the display panel and the display device of the present disclosure can realize driving by controlling the amount of charge of the first storage capacitor and the second storage capacitor in the threshold compensation phase and the lighting phase.
  • the current of the transistor driving the light emitting element in the light emitting phase is independent of the threshold voltage and the power supply voltage of the driving transistor, and is only related to the data voltage, the reference voltage, the capacitance value of the first storage capacitor, and the capacitance value of the second storage capacitor, and thus the data voltage and The same reference voltage
  • different current outputs can be realized, and different compression ratios of the data are realized, thereby improving the data driving range of the driving IC.
  • FIG. 1 is a structural diagram of a pixel driving circuit according to at least one embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a pixel driving circuit according to at least one embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a pixel driving circuit according to at least one embodiment of the present disclosure.
  • 4A is a detailed structural diagram of the pixel driving circuit shown in FIG. 3 when the threshold compensation unit includes the first compensation transistor and the second compensation transistor;
  • 4B is a detailed structural diagram of the pixel driving circuit shown in FIG. 3 when the data writing unit includes a data writing transistor;
  • 4C is a detailed structural diagram of the pixel driving circuit shown in FIG. 3 when the light emission control unit includes the first light emission control transistor and the second light emission control transistor;
  • FIG. 5 is a circuit diagram of a specific embodiment of a pixel driving circuit of the present disclosure.
  • FIG. 6 is a timing chart showing the operation of a specific embodiment of the pixel driving circuit shown in FIG. 5 of the present disclosure
  • FIG. 7 is a flowchart of a pixel driving method according to at least one embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a pixel driving method according to at least one embodiment of the present disclosure.
  • the pixel driving circuit of the embodiment of the present disclosure includes a driving transistor MDT, a first storage capacitor C1, a second storage capacitor C2, a threshold compensation unit 11, a data writing unit 12, and a lighting control unit 13, wherein ,
  • a gate of the driving transistor MDT is connected to a first end of the first storage capacitor C1, and a first pole of the driving transistor MDT is connected to a second end of the first storage capacitor C1;
  • the first end of the second storage capacitor C2 is connected to the first power voltage V1, and the second storage battery The second end of the capacitor C2 is connected to the second end of the first storage capacitor C1;
  • the threshold compensation unit 11 is configured to control the gate of the driving transistor MDT to access the reference voltage Vref during a threshold compensation phase of each display period such that the second pole of the driving transistor MDT and the reset voltage of the output reset voltage Vini Connecting the wires such that the driving transistor MDT is turned on to discharge the reset voltage line until the driving transistor MDT is turned off;
  • the data writing unit 12 is configured to control the data voltage SD to be written into the gate of the driving transistor MDT during the data writing phase of each display period;
  • the illumination control unit 13 is configured to control the first power supply voltage V1 to enter the first pole of the driving transistor MDT during the lighting phase of each display period, and control the second pole of the driving transistor MDT to be connected to the light emitting element LE. Controlling the driving transistor MDT to be turned on to drive the light emitting element LE to emit light;
  • the total amount of charge of the first storage capacitor C1 and the total amount of charge of the second storage capacitor C2 are equal in the threshold compensation phase and the data writing phase;
  • the amount of charge of the first storage capacitor C1 in the data writing phase is equal to the amount of charge of the first storage capacitor C1 in the light emitting phase.
  • the driving transistor MDT is a p-type transistor, at this time, the first extreme source of the driving transistor MDT, and the second extreme drain of the driving transistor MDT;
  • the driving transistor MDT may also be an n-type transistor.
  • the pixel driving circuit of the embodiment of the present disclosure can control the current of the driving transistor in the light emitting phase and the driving transistor by controlling the amount of charge of the first storage capacitor and the second storage capacitor in the threshold compensation phase and the light emitting phase.
  • the threshold voltage is independent of the power supply voltage and is only related to the data voltage, the reference voltage, the capacitance value of the first storage capacitor, and the capacitance value of the second storage capacitor, so by changing the first storage capacitor when the data voltage and the reference voltage are the same.
  • the capacitance value and the capacitance value of the second storage capacitor can realize different current outputs, realize different compression ratios of data, thereby improving the data driving range of the driving IC.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • one of the poles is referred to as a source and the other pole is referred to as a drain.
  • the transistor can be classified into an n-type transistor or a p-type transistor according to the characteristics of the transistor.
  • All of the transistors are described by taking a p-type transistor as an example. It is conceivable that when implemented by an n-type transistor, those skilled in the art can easily think of it without creative work, and thus are also implemented in the present disclosure. Within the scope of protection.
  • the threshold compensation phase further includes a reset phase during each display period
  • the threshold compensation unit is further configured to control a gate of the driving transistor to access a reference voltage in the reset phase to connect a second electrode of the driving transistor to a reset voltage line;
  • the illumination control unit is further configured to control, in the resetting phase, the first pole of the driving transistor to be connected to the first power voltage, and control the second pole of the driving transistor to be connected to the light emitting component;
  • the drive transistor is in an amplified state or a saturated state during the reset phase.
  • the driving transistor is in an amplified state or a saturated state in the reset phase to ensure that a large current flows through the driving transistor to eliminate or reduce a small current for the display panel from being used for a long time. Displaying a low-brightness transition to a characteristic drift caused by a stress (stress) of a driving transistor at a small current when a high-current is displayed, thereby eliminating or reducing a luminance tailing phenomenon when a black picture is converted to a white picture due to characteristic drift .
  • the threshold compensation unit in the reset phase, is further configured to control a gate of the driving transistor (ie, the first storage capacitor) in the reset phase a first end) accessing a reference voltage such that a second pole of the drive transistor (ie, a second end of the first storage capacitor) is coupled to a reset voltage line to initialize a potential across the first storage capacitor, So that the writing of the frame signal is not affected by the upper frame signal.
  • the driving transistor operates in a saturation region in a reset phase (ie, the driving transistor is in a saturated state in a reset phase), and at this time, a current flowing through the driving transistor can be maximized.
  • the threshold compensation unit 11 is connected to the reset control signal Reset, the data writing unit 12 is connected to the scan signal Gate, and the illumination control unit 13 is connected to the illumination control signal EM;
  • the threshold compensation unit 11 controls the reference voltage Vref to enter the gate of the driving transistor MDT during the reset phase and the threshold compensation phase of each display period under the control of the reset control signal Reset, and controls the reset voltage Vini to access the driving transistor MDT.
  • the data writing unit 12 has data in each display period under the control of the scan signal Gate Writing phase control data voltage SD is written to the gate of the driving transistor MDT;
  • the illumination control unit 13 controls the first power supply voltage V1 to access the first pole of the drive transistor MDT and the second control of the drive transistor MDT during the illumination phase of each display period under the control of the illumination control signal EM.
  • the pole is connected to the light-emitting element LE.
  • the light emitting element may include an organic light emitting diode D1, and an anode of the organic light emitting diode D1 passes through the light emitting control unit. 13 is connected to the second pole of the driving transistor MDT, and the cathode of the organic light emitting diode D1 is connected to the second power voltage V2.
  • the voltage difference between the reset voltage Vini outputted by the reset voltage line and the second power voltage V2 is smaller than the turn-on threshold voltage of the organic light emitting diode D1, so as to ensure that the D1 is not illuminated during the reset phase.
  • the turn-on threshold voltage of the organic light emitting diode D1 In order to improve the brightness quality of the displayed dark state and improve the contrast.
  • the threshold compensation unit includes a first compensation transistor and a second compensation transistor, where
  • a gate of the first compensation transistor is connected to a reset control signal, a first pole of the first compensation transistor is connected to a second pole of the driving transistor, and a second pole of the first compensation transistor is coupled to the reset Voltage line connection
  • a gate of the second compensation transistor is connected to the reset control signal, a first pole of the second compensation transistor is connected to a gate of the driving transistor, and a second pole of the second compensation transistor is connected to The reference voltage is described.
  • the data writing unit includes a data writing transistor
  • the gate of the data write transistor is connected to the scan signal, the first pole of the data write transistor is connected to the gate of the drive transistor, and the second pole of the data write transistor is connected to the data voltage.
  • the light emission control unit includes a first light emission control transistor and a second light emission control transistor, wherein
  • a gate of the first illumination control transistor is coupled to the illumination control signal, a first pole of the first illumination control transistor is coupled to the first supply voltage, and a second pole of the first illumination control transistor is Driving the first pole of the transistor;
  • a gate of the second illuminating control transistor is connected to the illuminating control signal, and the second illuminating A first pole of the control transistor is coupled to the second pole of the drive transistor, and a second pole of the second illumination control transistor is coupled to the light emitting element.
  • the threshold compensation unit 11 includes a first compensation transistor M1 and a second compensation transistor M2, wherein
  • the first compensation transistor M1 and the second compensation transistor M2 are both p-type transistors
  • a gate of the first compensation transistor M1 is connected to a reset control signal Reset, a source of the first compensation transistor M1 is connected to a drain of the driving transistor MDT, and a drain and an output of the first compensation transistor M1 Reset voltage line connection of reset voltage Vini;
  • a gate of the second compensation transistor M2 is connected to the reset control signal Reset, a source of the second compensation transistor M2 is connected to a gate of the driving transistor MDT, and a drain of the second compensation transistor M2
  • the reference voltage Vref is accessed.
  • the data writing unit 12 includes a data writing transistor M3;
  • the data write transistor M3 is a p-type transistor
  • the gate of the data writing transistor M3 is connected to the scan signal Gate, the source of the data writing transistor M3 is connected to the gate of the driving transistor MDT, and the drain of the data writing transistor M3 is connected to the data. Voltage SD.
  • the light emission control unit includes a first light emission control transistor M4 and a second light emission control transistor M5, wherein
  • the gate of the first illuminating control transistor M4 is connected to the illuminating control signal EM, the source of the first illuminating control transistor M4 is connected to the first power voltage V1, and the drain of the first illuminating control transistor M4 Connected to a source of the driving transistor MDT;
  • the gate of the second illuminating control transistor M5 is connected to the illuminating control signal EM, the source of the second illuminating control transistor M5 is connected to the drain of the driving transistor MDT, and the second illuminating control transistor M5 The drain is connected to the anode of the organic light emitting diode D1.
  • the pixel driving circuit of the present disclosure will be described below by way of a specific embodiment.
  • a specific embodiment of the pixel driving circuit of the present disclosure includes a driving transistor MDT, a first storage capacitor C1, a second storage capacitor C2, a threshold compensation unit, and a data write list. Yuan and lighting control unit, wherein
  • a gate of the driving transistor MDT is connected to a first end of the first storage capacitor C1, and a source of the driving transistor MDT is connected to a second end of the first storage capacitor C1;
  • the first end of the second storage capacitor C2 is connected to the high voltage VDD, and the second end of the second storage capacitor C2 is connected to the second end of the first storage capacitor C1;
  • the threshold compensation unit includes a first compensation transistor M1 and a second compensation transistor M2, wherein
  • a gate of the first compensation transistor M1 is connected to a reset control signal Reset, a source of the first compensation transistor M1 is connected to a drain of the driving transistor MDT, and a drain and an output of the first compensation transistor M1 Reset voltage line connection of reset voltage Vini;
  • a gate of the second compensation transistor M2 is connected to the reset control signal Reset, a source of the second compensation transistor M2 is connected to a gate of the driving transistor MDT, and a drain of the second compensation transistor M2 Accessing a reference voltage Vref;
  • the data writing unit includes a data writing transistor M3;
  • the gate of the data writing transistor M3 is connected to the scan signal Gate, the source of the data writing transistor M3 is connected to the gate of the driving transistor MDT, and the drain of the data writing transistor M3 is connected to the data. Voltage SD;
  • the light emission control unit includes a first light emission control transistor M4 and a second light emission control transistor M5, wherein
  • the gate of the first illuminating control transistor M4 is connected to the illuminating control signal EM, the source of the first illuminating control transistor M4 is connected to the high voltage VDD, the drain of the first illuminating control transistor M4 and the driving a source connection of the transistor MDT;
  • the gate of the second illuminating control transistor M5 is connected to the illuminating control signal EM, the source of the second illuminating control transistor M5 is connected to the drain of the driving transistor MDT, and the second illuminating control transistor M5 The drain is connected to the anode of the organic light emitting diode D1;
  • the cathode of the organic light emitting diode D1 is connected to a low voltage VSS;
  • connection node of the first storage capacitor C1 and the second storage capacitor C2 is node A.
  • all of the transistors are p-type transistors, and in actual operation, the transistors may be replaced with n-type transistors.
  • the specific embodiment of the pixel driving circuit shown in FIG. 5 of the present disclosure is in operation.
  • EM is the low voltage turn-on signal
  • Reset is the low voltage turn-on signal
  • Gate is the high voltage turn-off signal
  • EM controlled M4 and M5 are both on
  • Reset control M1 and M2 are also open
  • D1 anode and MDT leakage The pole is connected, the Vini is written to the drain of the MDT and the anode of the D1, and the potential of the anode of D1 is reset to Vini; and the potential difference between Vini and VSS is optimally smaller than the turn-on threshold voltage of D1, thus ensuring the time D1 is not illuminated, in order to improve the brightness quality of the displayed dark state, improve the contrast;
  • VDD is written to the source of the MDT
  • Vref is written to the gate of the MDT, where the potential difference between Vref and VDD is the Vgs of the MDT, To ensure that MDT has a large current flowing, thereby eliminating or reducing the low brightness of the display panel with a small current for a long time, and transition
  • the MDT can work in the amplification area or the saturation area, theoretically the most The MDT is a state in the saturation region, the current flowing at this time can be maximized in the MDT;
  • EM and Gate are both high voltage shutdown signals, Reset is low voltage on signal, M4 and M5 controlled by EM are all turned off; M1 and M2 controlled by Reset continue to be turned on, thus maintaining connection between C1 and C2
  • the charge of the node ie, node A in Figure 3
  • EM and Reset are high voltage shutdown signals, Gate is low voltage on signal, EM controlled M4 and M5 are all turned off, Reset controlled M1 and M2 are also turned off; M3 controlled by Gate is in In the on state, SD is written to the gate of the MDT, that is, the gate connection of C1 and MDT; in the series circuit composed of C1 and C2, the voltage at the junction of C1 and C2 is in a floating state, and C1 and C2 are in The total amount of charge in the data writing phase T3 is kept consistent with the total amount of charge of C1 and C2 in the threshold compensation phase T2; assuming that the voltage of the connecting node C1 and C2 is X at this time, the principle is based on the principle that the amount of charge before and after the change of capacitance does not change. ,details as follows:
  • Gate and Reset are both high voltage shutdown signals, so that M1, M2 and M3 are all in the off state; EM is the low voltage on signal, so that both M4 and M5 are turned on, wherein the opening of M5 will be the anode of D1 and the MDT The drain is connected.
  • the turn-on of M3 writes VDD to the source of MDT and the junction of C1 and C2. Because the first end of C2 is connected to VDD, the potential change at the junction of C1 and C2 will not affect its capacitance.
  • the gate connection of C1 and MDT is in a floating state, and the potential at the gate connection of C1 and MDT changes with the potential at the junction of C1 and C2 through C1, and the charge held by C1 before and after the change
  • the amount is constant (ie, the amount of charge held by C1 in the data writing phase T3 and the amount of charge held by C1 in the lighting phase T4 are equal);
  • Ids is the drain-source current when MDT operates in the saturation region
  • K is the current parameter
  • C2/(C2-C1) is a capacitance value, which can also be regarded as a constant
  • the data size SD and the reference voltage Vref are determined only for the size of the Ids, and Vref is a DC voltage signal. Therefore, only the data voltage SD is determined for the size of the Ids. Therefore, the circuit of the specific embodiment of the pixel driving circuit shown in FIG. 3 is disclosed in the present disclosure.
  • the structure can compensate for the threshold voltage difference of the driving transistor MDT, and can also compensate the IR Drop (IR voltage drop) on the power signal VDD, and can also be realized according to the ratio of C2/(C2-C1) under the same data voltage. Under the same data voltage, different current outputs, that is, the compression ratio effect of the data is achieved.
  • the pixel driving method according to the embodiment of the present disclosure is applied to the pixel driving method described above, and includes:
  • Threshold compensation step S1 threshold compensation unit control during the threshold compensation phase of each display period
  • the gate of the driving transistor is connected to the reference voltage and the second electrode of the driving transistor is connected to the reset voltage line, so that the driving transistor is turned on to discharge to the starting voltage line until the driving transistor is turned off;
  • Data writing step S2 in the data writing phase of each display period, the data writing unit controls the data voltage to be written to the gate of the driving transistor;
  • Light-emitting step S3 in the light-emitting stage of each display period, the light-emitting control unit controls the first pole of the first power voltage driving transistor, and controls the second pole of the driving transistor to be connected with the light-emitting element to control the driving transistor to be turned on to drive the light-emitting element Illuminate
  • the total amount of charge of the first storage capacitor and the second storage capacitor is equal in the threshold compensation phase and the data writing phase;
  • the amount of charge of the first storage capacitor in the data writing phase is equal to the amount of charge of the first storage capacitor in the light emitting phase.
  • the pixel driving method can control the current of the driving transistor to drive the light emitting element in the light emitting phase and the driving transistor by controlling the amount of charge of the first storage capacitor and the second storage capacitor in the threshold compensation phase and the light emitting phase.
  • the threshold voltage is independent of the power supply voltage and is only related to the data voltage, the reference voltage, the capacitance value of the first storage capacitor, and the capacitance value of the second storage capacitor, so by changing the first storage capacitor when the data voltage and the reference voltage are the same.
  • the capacitance value and the capacitance value of the second storage capacitor can realize different current outputs and achieve different compression ratios of the data.
  • each display period further includes a reset phase in the threshold compensation phase time; as shown in FIG. 8, the pixel driving method further includes:
  • Reset step S0 in the reset phase of each display period, the threshold compensation unit controls the gate of the drive transistor to access the reference voltage and the second electrode of the drive transistor is connected to the reset voltage line, and the illumination control unit controls the drive A first pole of the transistor is coupled to the first supply voltage, and a second pole of the drive transistor is controlled to be coupled to the light emitting element; the drive transistor is in an amplified state or a saturated state during the reset phase.
  • the driving transistor is in an amplified state or a saturated state in the reset phase to ensure that a large current flows through the driving transistor to eliminate or reduce a small current for the display panel from being used for a long time. Shows a low-brightness transition to the characteristic drift of the drive transistor at a small current due to stress at high current, thereby eliminating or reducing the black caused by it The brightness tailing when the color picture is changed to a white screen.
  • the threshold compensation unit in the reset phase, is further configured to control the gate of the driving transistor (ie, the first storage) in the reset phase a first end of the capacitor is coupled to the reference voltage and a second pole of the driving transistor (ie, the second end of the first storage capacitor) is coupled to the reset voltage line to initialize a potential across the first storage capacitor, So that the writing of the frame signal is not affected by the upper frame signal.
  • the illumination control signal and the scan signal are both off signals
  • the reset control signal is an on signal
  • the reset voltage line outputs a low potential reset voltage
  • the first illumination control transistor and the second illumination control transistor Shutdown, both the first compensation transistor and the second compensation transistor are turned on, and the charge held at the first storage capacitor and the second storage capacitor connection node is discharged to the reset voltage line through the driving transistor and the first compensation transistor until The source potential of the driving transistor is low enough to turn off the driving transistor;
  • the illumination control signal and the reset control signal are both off signals
  • the scan signal is an on signal
  • the first illumination control transistor and the second illumination control transistor are both turned off
  • the first compensation transistor and The second compensation transistor is turned off
  • the data write transistor is turned on, the data voltage is written to the gate of the drive transistor
  • the connection node of the first storage capacitor and the second storage capacitor is in a floating state, the first storage capacitor and the The total amount of charge of the second storage capacitor is equal to the threshold compensation phase and the data writing phase;
  • the scan signal and the reset control signal are both off signals, so that the first compensation transistor, the second compensation transistor and the data write transistor are both turned off, and the illumination control signal is an on signal, so that the first The light-emitting control transistor and the second light-emitting control transistor are both turned on, such that the light-emitting element is connected to the second pole of the driving transistor, and the first power-supply voltage is written to the junction of the first pole of the driving transistor and the first storage capacitor and the second storage capacitor
  • the first end of the second storage capacitor is connected to the first power supply voltage, the connection node of the first storage capacitor and the gate of the driving transistor is in a floating state, and the amount of charge of the first storage capacitor in the data writing phase
  • the amount of charge of the first storage capacitor in the light emission control phase is equal, such that a current flowing through the driving transistor in the light emitting phase is only related to the data voltage, a capacitance value of the first storage capacitor, and the second The capacitance value of the storage capacitor is related
  • each display period further includes a reset phase in the threshold compensation phase time; the pixel driving method further includes:
  • the illumination control signal and the reset control signal are both on signals
  • the scan signal is a shutdown signal
  • the first illumination control transistor and the second illumination control transistor are both turned on
  • the first compensation transistor and the second compensation The transistor is also turned on
  • the data writing transistor is turned off
  • the light emitting element is connected to the second electrode of the driving transistor
  • the reset voltage is written to the second electrode of the driving transistor
  • the driving transistor is in an amplified state or a saturated state to ensure the driving transistor.
  • the threshold compensation unit in the reset phase, is further configured to control the gate of the driving transistor (ie, the first storage) in the reset phase a first end of the capacitor is coupled to the reference voltage and a second pole of the driving transistor (ie, the second end of the first storage capacitor) is coupled to the reset voltage line to initialize a potential across the first storage capacitor, So that the writing of the frame signal is not affected by the upper frame signal.
  • the light emitting element comprises an organic light emitting diode
  • an anode of the organic light emitting diode is connected to the second pole of the driving transistor through the light emitting control unit, and when a cathode of the organic light emitting diode is connected to the second power voltage
  • a voltage difference between the reset voltage outputted by the reset voltage line and the second power voltage is less than an turn-on threshold voltage of the organic light emitting diode to ensure that the organic light emitting diode does not emit light during the reset phase.
  • the display panel according to an embodiment of the present disclosure includes the above-described pixel driving circuit.
  • the display device includes the above display panel.

Abstract

像素驱动电路包括驱动晶体管（MDT）、第一存储电容（C1）、第二存储电容（C2）、阈值补偿单元（11）、数据写入单元（12）和发光控制单元（13）；所述阈值补偿单元（11）在阈值补偿阶段控制驱动晶体管（MDT）导通而向复位电压线（Vini）放电，直至所述驱动晶体管（MDT）关断；所述数据写入单元（12）在每数据写入阶段控制数据电压（SD）写入驱动晶体管的栅极；所述发光控制单元（13）在发光阶段控制驱动晶体管（MDT）导通以驱动发光元件（LE）发光；第一存储电容（C1）的电荷总量和第二存储电容（C2）的电荷总量在阈值补偿阶段和数据写入阶段相等；第一存储电容（C1）在数据写入阶段的电荷量与第一存储电容（C1）在发光控制阶段的电荷量相等。

Description

像素驱动电路、像素驱动方法、显示面板和显示装置
相关申请的交叉引用
本申请主张在2016年1月4日在中国提交的中国专利申请号No.201610003695.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路、像素驱动方法、显示面板和显示装置。
背景技术
目前在AMOLED(Active-matrix organic light emitting diode，有源矩阵有机发光二极管)显示领域中，尤其是大尺寸基板设计中，由于背板TFT特性在工艺过程中的不均匀性，以及稳定性问题，造成流经OLED(Organic Light-Emitting Diode，有机发光二极管)电流的不均匀性。为了弥补由于背板生产过程中造成的TFT不均匀性，所导致Vth Shift(阈值电压漂移)，以及长时间开启偏压造成的TFT特性的漂移，而进行了AMOLED补偿电路设计。针对AMOLED尺寸大型化的趋势，会使信号线负载加大，导致在电源信号线上出现电压衰减，从而影响显示区电流的均匀性。
在现有的OLED补偿电路中，随着发光器件的效率提升，所需要的驱动数据电压范围将降低，将会超出驱动IC(Integrated Circuit，集成电路)的驱动能力。而现有的像素驱动电路不能实现数据的不同压缩比，无法提高驱动IC的数据驱动范围。
发明内容
本公开的主要目的在于提供一种像素驱动电路、方法、显示面板和显示装置，以解决现有技术中不能实现数据的不同压缩比的问题，从而能够提高驱动IC的数据驱动范围。
为了达到上述目的，本公开提供了一种像素驱动电路，包括驱动晶体管、第一存储电容、第二存储电容、阈值补偿单元、数据写入单元和发光控制单 元；
所述驱动晶体管的栅极与所述第一存储电容的第一端连接，所述驱动晶体管的第一极与所述第一存储电容的第二端连接；
所述第二存储电容的第一端接入第一电源电压，所述第二存储电容的第二端与所述第一存储电容的第二端连接；
所述阈值补偿单元用于在每一显示周期的阈值补偿阶段控制所述驱动晶体管的栅极接入参考电压而所述驱动晶体管的第二极与复位电压线连接，从而使得驱动晶体管导通而向所述复位电压线放电，直至所述驱动晶体管关断；
所述数据写入单元用于在每一显示周期的数据写入阶段控制数据电压写入所述驱动晶体管的栅极；
所述发光控制单元用于在每一显示周期的发光阶段控制第一电源电压接入所述驱动晶体管的第一极，控制所述驱动晶体管的第二极与发光元件连接，以控制驱动晶体管导通以驱动发光元件发光；
所述第一存储电容的电荷总量和所述第二存储电容的电荷总量在所述阈值补偿阶段和所述数据写入阶段相等；
所述第一存储电容在所述数据写入阶段的电荷量与所述第一存储电容在所述发光控制阶段的电荷量相等。
实施时，在每一显示周期，所述阈值补偿阶段还包括复位阶段；
所述阈值补偿单元还用于在所述复位阶段控制所述驱动晶体管的栅极接入参考电压而所述驱动晶体管的第二极接入复位电压；
所述发光控制单元还用于在所述复位阶段控制所述驱动晶体管的第一极接入所述第一电源电压，控制所述驱动晶体管的第二极与所述发光元件连接；
所述驱动晶体管在所述复位阶段处于放大状态或饱和状态。
实施时，所述发光元件包括有机发光二极管；
所述有机发光二极管的阳极通过所述发光控制单元与所述驱动晶体管的第二极连接，所述有机发光二极管的阴极接入第二电源电压；
在复位阶段，所述复位电压线输出的复位电压与所述第二电源电压之间的电压差小于所述有机发光二极管的开启阈值电压。
实施时，所述阈值补偿单元包括第一补偿晶体管和第二补偿晶体管，其 中，
所述第一补偿晶体管的栅极接入复位控制信号，所述第一补偿晶体管的第一极与所述驱动晶体管的第二极连接，所述第一补偿晶体管的第二极与所述复位电压线连接；
所述第二补偿晶体管的栅极接入所述复位控制信号，所述第二补偿晶体管的第一极与所述驱动晶体管的栅极连接，所述第二补偿晶体管的第二极接入所述参考电压。
实施时，所述数据写入单元包括数据写入晶体管；，
所述数据写入晶体管的栅极接入扫描信号，所述数据写入晶体管的第一极与所述驱动晶体管的栅极连接，所述数据写入晶体管的第二极接入数据电压。
实施时，所述发光控制单元包括第一发光控制晶体管和第二发光控制晶体管，其中，
所述第一发光控制晶体管的栅极接入发光控制信号，所述第一发光控制晶体管的第一极接入所述第一电源电压，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极连接；以及，
所述第二发光控制晶体管的栅极接入所述发光控制信号，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极连接，所述第二发光控制晶体管的第二极与所述发光元件连接。
实施时，所述第一补偿晶体管和所述第二补偿晶体管为P型晶体管。
实施时，所述写入晶体管为P型晶体管。
实施时，所述第一发光控制晶体管和所述第二发光控制晶体管为P型晶体管。
本公开还提供了一种像素驱动方法，应用于上述的像素驱动电路，所述像素驱动方法包括：
在每一显示周期的阈值补偿阶段，阈值补偿单元控制驱动晶体管的栅极接入参考电压而驱动晶体管的第二极与复位电压线连接，从而使得驱动晶体管导通而向起始电压线放电，直至驱动晶体管关断；
在每一显示周期的数据写入阶段，数据写入单元控制数据电压写入驱动 晶体管的栅极；
在每一显示周期的发光阶段，发光控制单元控制第一电源电压驱动晶体管的第一极，控制驱动晶体管的第二极与发光元件连接，以控制驱动晶体管导通以驱动发光元件发光；
第一存储电容和第二存储电容的电荷总量在阈值补偿阶段和数据写入阶段相等；
第一存储电容在数据写入阶段的电荷量与第一存储电容在发光阶段的电荷量相等。
实施时，每一显示周期在所述阈值补偿阶段时间还包括复位阶段；所述像素驱动方法还包括：
在每一显示周期的复位阶段，阈值补偿单元控制所述驱动晶体管的栅极接入参考电压而所述驱动晶体管的第二极与复位电压线连接，发光控制单元控制所述驱动晶体管的第一极接入所述第一电源电压，控制所述驱动晶体管的第二极与所述发光元件连接；
所述驱动晶体管在所述复位阶段处于放大状态或饱和状态。
本公开还提供了一种像素驱动方法，应用于上述的像素驱动电路，所述像素驱动方法包括：
在每一显示周期的阈值补偿阶段：发光控制信号和扫描信号都为关断信号，复位控制信号为开启信号，复位电压线输出低电位的复位电压，第一发光控制晶体管和第二发光控制晶体管都关断，第一补偿晶体管和第二补偿晶体管都开启，保持在第一存储电容和第二存储电容连接节点处的电荷通过驱动晶体管和第一补偿晶体管向所述复位电压线进行放电，直到驱动晶体管的源极电位低至使驱动晶体管关断；
在每一显示周期的数据写入阶段：发光控制信号和复位控制信号都为关断信号，扫描信号为开启信号，第一发光控制晶体管和第二发光控制晶体管都关断，第一补偿晶体管和第二补偿晶体管都关断；数据写入晶体管开启，数据电压写入驱动晶体管的栅极；第一存储电容和第二存储电容的连接节点处于浮空状态，所述第一存储电容和所述第二存储电容的电荷总量在所述阈值补偿阶段和所述数据写入阶段相等；
在每一显示周期的发光阶段：扫描信号和复位控制信号都为关断信号，使得第一补偿晶体管、第二补偿晶体管和数据写入晶体管都关断，发光控制信号是开启信号，使得第一发光控制晶体管和第二发光控制晶体管都打开，使得发光元件与驱动晶体管的第二极相连接，第一电源电压写入驱动晶体管的第一极与第一存储电容和第二存储电容的连接处，第二存储电容的第一端接入第一电源电压，第一存储电容和驱动晶体管的栅极的连接节点处于浮空状态，所述第一存储电容在所述数据写入阶段的电荷量与所述第一存储电容在所述发光控制阶段的电荷量相等，以使得在发光阶段流过驱动晶体管的电流仅与所述数据电压、所述第一存储电容的电容值和所述第二存储电容的电容值有关。
实施时，每一显示周期在所述阈值补偿阶段时间还包括复位阶段；所述像素驱动方法还包括：
在每一显示周期的复位阶段，发光控制信号和复位控制信号都是开启信号，扫描信号为关断信号，第一发光控制晶体管和第二发光控制晶体管都打开，第一补偿晶体管和第二补偿晶体管也都打开，数据写入晶体管关断，发光元件与驱动晶体管的第二极相连接，复位电压写入驱动晶体管的第二极，所述驱动晶体管处于放大状态或饱和状态。
实施时，当所述发光元件包括有机发光二极管，有机发光二极管的阳极通过所述发光控制单元与所述驱动晶体管的第二极连接，有机发光二极管的阴极接入第二电源电压时，在所述复位阶段，所述复位电压线输出的复位电压与所述第二电源电压之间的电压差小于所述有机发光二极管的开启阈值电压。
本公开还提供了一种显示面板，包括上述的像素驱动电路。
本公开还提供了一种显示装置，包括上述的显示面板。
与现有技术相比，本公开所述的像素驱动电路、方法、显示面板和显示装置通过在阈值补偿阶段和发光阶段对第一存储电容和第二存储电容的电荷量的控制，可以实现驱动晶体管在发光阶段驱动发光元件的电流与驱动晶体管的阈值电压和电源电压无关，仅与数据电压、参考电压、第一存储电容的电容值和第二存储电容的电容值有关，因此在数据电压和参考电压相同的情 况下通过改变第一存储电容的电容值和第二存储电容的电容值即可实现不同的电流输出，实现数据的不同压缩比，从而提高驱动IC的数据驱动范围。
附图说明
图1是本公开至少一个实施例所述的像素驱动电路的结构图；
图2是本公开至少一个实施例所述的像素驱动电路的结构图；
图3是本公开至少一个实施例所述的像素驱动电路的结构图；
图4A是图3所示的像素驱动电路在阈值补偿单元包括第一补偿晶体管和第二补偿晶体管时的具体结构图；
图4B是图3所示的像素驱动电路在数据写入单元包括数据写入晶体管时的具体结构图；
图4C是图3所示的像素驱动电路在发光控制单元包括第一发光控制晶体管和第二发光控制晶体管时的具体结构图；
图5是本公开所述的像素驱动电路的一具体实施例的电路图；
图6是本公开如图5所示的像素驱动电路的具体实施例的工作时序图；
图7是本公开至少一个实施例所述的像素驱动方法的流程图；
图8是本公开至少一个实施例所述的像素驱动方法的流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，本公开实施例所述的像素驱动电路包括驱动晶体管MDT、第一存储电容C1、第二存储电容C2、阈值补偿单元11、数据写入单元12和发光控制单元13，其中，
所述驱动晶体管MDT的栅极与所述第一存储电容C1的第一端连接，所述驱动晶体管MDT的第一极与所述第一存储电容C1的第二端连接；
所述第二存储电容C2的第一端接入第一电源电压V1，所述第二存储电 容C2的第二端与所述第一存储电容C1的第二端连接；
所述阈值补偿单元11用于在每一显示周期的阈值补偿阶段控制所述驱动晶体管MDT的栅极接入参考电压Vref而使得所述驱动晶体管MDT的第二极与输出复位电压Vini的复位电压线连接，从而使得驱动晶体管MDT导通而向所述复位电压线放电，直至所述驱动晶体管MDT关断；
所述数据写入单元12用于在每一显示周期的数据写入阶段控制数据电压SD写入所述驱动晶体管MDT的栅极；
所述发光控制单元13用于在每一显示周期的发光阶段控制第一电源电压V1接入所述驱动晶体管MDT的第一极，控制所述驱动晶体管MDT的第二极与发光元件LE连接，以控制驱动晶体管MDT导通以驱动发光元件LE发光；
所述第一存储电容C1的电荷总量和所述第二存储电容C2的电荷总量在所述阈值补偿阶段和所述数据写入阶段相等；
所述第一存储电容C1在所述数据写入阶段的电荷量与所述第一存储电容C1在所述发光阶段的电荷量相等。
在如图1所示的实施例中，驱动晶体管MDT为p型晶体管，此时，所述驱动晶体管MDT的第一极为源极，所述驱动晶体管MDT的第二极为漏极；在具体实施时，所述驱动晶体管MDT也可以为n型晶体管。
本公开实施例所述的像素驱动电路通过在阈值补偿阶段和发光阶段对第一存储电容和第二存储电容的电荷量的控制，可以实现驱动晶体管在发光阶段驱动发光元件的电流与驱动晶体管的阈值电压和电源电压无关，仅与数据电压、参考电压、第一存储电容的电容值和第二存储电容的电容值有关，因此在数据电压和参考电压相同的情况下通过改变第一存储电容的电容值和第二存储电容的电容值即可实现不同的电流输出，实现数据的不同压缩比，从而提高驱动IC的数据驱动范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。此外，按照晶体管的特性区分可以将晶体管分为n型晶体管或p型晶体管。在本公开实施例提供的驱动电路中， 所有晶体管均是以p型晶体管为例进行的说明，可以想到的是在采用n型晶体管实现时是本领域技术人员可在没有做出创造性劳动前提下轻易想到的，因此也是在本公开的实施例保护范围内的。
在本公开所述的像素驱动电路的一可选的实施例中，在每一显示周期内，所述阈值补偿阶段还包括复位阶段；
所述阈值补偿单元还用于在所述复位阶段控制所述驱动晶体管的栅极接入参考电压而使得所述驱动晶体管的第二极与复位电压线连接；
所述发光控制单元还用于在所述复位阶段控制所述驱动晶体管的第一极接入所述第一电源电压，控制所述驱动晶体管的第二极与所述发光元件连接；
所述驱动晶体管在所述复位阶段处于放大状态或饱和状态。
在本公开所述的像素驱动电路的可选实施例中，驱动晶体管在复位阶段处于放大状态或饱和状态，以保证驱动晶体管有大电流流过，来消除或降低显示面板由长时间用小电流显示低亮度过渡到用大电流显示高亮度时驱动晶体管在小电流下的由于stress(应力)引起的特性漂移，从而消除或减弱特性漂移所导致的黑色画面变换到白色画面时的亮度拖尾现象。
并且，在本公开所述的像素驱动电路的可选实施例中，在复位阶段，阈值补偿单元，还用于在所述复位阶段控制所述驱动晶体管的栅极(即所述第一存储电容的第一端)接入参考电压而使得所述驱动晶体管的第二极(即所述第一存储电容的第二端)与复位电压线连接，以对第一存储电容两端电位进行初始化，以使得本帧信号的写入不受上帧信号的影响。
可选的，所述驱动晶体管在复位阶段工作在饱和区(即所述驱动晶体管在复位阶段处于饱和状态)，此时可以最大化流经驱动晶体管的电流。
具体的，如图2所示，在本公开至少一个实施例所述的像素电路中，
所述阈值补偿单元11接入复位控制信号Reset，所述数据写入单元12接入扫描信号Gate，所述发光控制单元13接入发光控制信号EM；
所述阈值补偿单元11在复位控制信号Reset的控制下在每一显示周期的复位阶段和阈值补偿阶段控制参考电压Vref接入驱动晶体管MDT的栅极，控制复位电压Vini接入驱动晶体管MDT的第二极；
所述数据写入单元12在扫描信号Gate的控制下在每一显示周期的数据 写入阶段控制数据电压SD写入驱动晶体管MDT的栅极；
所述发光控制单元13在发光控制信号EM的控制下在每一显示周期的发光阶段控制控制第一电源电压V1接入所述驱动晶体管MDT的第一极，控制所述驱动晶体管MDT的第二极与发光元件LE连接。
具体的，如图3所示，在如图2所示的像素电路的实施例的基础上，所述发光元件可以包括有机发光二极管D1，所述有机发光二极管D1的阳极通过所述发光控制单元13与所述驱动晶体管MDT的第二极连接，所述有机发光二极管D1的阴极接入第二电源电压V2。
在复位阶段，所述复位电压线输出的复位电压Vini与所述第二电源电压V2之间的电压差小于所述有机发光二极管D1的开启阈值电压，这样来保证在复位阶段D1是不发光的，以便提升显示的暗态亮度品质，提升对比度。
具体的，所述阈值补偿单元包括第一补偿晶体管和第二补偿晶体管，其中，
所述第一补偿晶体管的栅极接入复位控制信号，所述第一补偿晶体管的第一极与所述驱动晶体管的第二极连接，所述第一补偿晶体管的第二极与所述复位电压线连接；
所述第二补偿晶体管的栅极接入所述复位控制信号，所述第二补偿晶体管的第一极与所述驱动晶体管的栅极连接，所述第二补偿晶体管的第二极接入所述参考电压。
具体的，所述数据写入单元包括数据写入晶体管；
所述数据写入晶体管的栅极接入扫描信号，所述数据写入晶体管的第一极与所述驱动晶体管的栅极连接，所述数据写入晶体管的第二极接入数据电压。
具体的，所述发光控制单元包括第一发光控制晶体管和第二发光控制晶体管，其中，
所述第一发光控制晶体管的栅极接入发光控制信号，所述第一发光控制晶体管的第一极接入所述第一电源电压，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极连接；以及，
所述第二发光控制晶体管的栅极接入所述发光控制信号，所述第二发光 控制晶体管的第一极与所述驱动晶体管的第二极连接，所述第二发光控制晶体管的第二极与所述发光元件连接。
如图4A所示，在本公开如图3所示的像素驱动电路的实施例的基础上，所述阈值补偿单元11包括第一补偿晶体管M1和第二补偿晶体管M2，其中，
所述第一补偿晶体管M1和所述第二补偿晶体管M2都为p型晶体管；
所述第一补偿晶体管M1的栅极接入复位控制信号Reset，所述第一补偿晶体管M1的源极与所述驱动晶体管MDT的漏极连接，所述第一补偿晶体管M1的漏极与输出复位电压Vini的复位电压线连接；
所述第二补偿晶体管M2的栅极接入所述复位控制信号Reset，所述第二补偿晶体管M2的源极与所述驱动晶体管MDT的栅极连接，所述第二补偿晶体管M2的漏极接入所述参考电压Vref。
如图4B所示，在本公开如图3所示的像素驱动电路的实施例的基础上，所述数据写入单元12包括数据写入晶体管M3；
所述数据写入晶体管M3为p型晶体管；
所述数据写入晶体管M3的栅极接入扫描信号Gate，所述数据写入晶体管M3的源极与所述驱动晶体管MDT的栅极连接，所述数据写入晶体管M3的漏极接入数据电压SD。
如图4C所示，在本公开如图3所示的像素驱动电路的实施例的基础上，所述发光控制单元包括第一发光控制晶体管M4和第二发光控制晶体管M5，其中，
所述第一发光控制晶体管M4的栅极接入发光控制信号EM，所述第一发光控制晶体管M4的源极接入所述第一电源电压V1，所述第一发光控制晶体管M4的漏极与所述驱动晶体管MDT的源极连接；
所述第二发光控制晶体管M5的栅极接入所述发光控制信号EM，所述第二发光控制晶体管M5的源极与所述驱动晶体管MDT的漏极连接，所述第二发光控制晶体管M5的漏极与所述有机发光二极管D1的阳极连接。
下面通过一具体实施例来说明本公开所述的像素驱动电路。
如图5所示，本公开所述的像素驱动电路的一具体实施例包括驱动晶体管MDT、第一存储电容C1、第二存储电容C2、阈值补偿单元、数据写入单 元和发光控制单元，其中，
所述驱动晶体管MDT的栅极与所述第一存储电容C1的第一端连接，所述驱动晶体管MDT的源极与所述第一存储电容C1的第二端连接；
所述第二存储电容C2的第一端接入高电压VDD，所述第二存储电容C2的第二端与所述第一存储电容C1的第二端连接；
所述阈值补偿单元包括第一补偿晶体管M1和第二补偿晶体管M2，其中，
所述第一补偿晶体管M1的栅极接入复位控制信号Reset，所述第一补偿晶体管M1的源极与所述驱动晶体管MDT的漏极连接，所述第一补偿晶体管M1的漏极与输出复位电压Vini的复位电压线连接；
所述第二补偿晶体管M2的栅极接入所述复位控制信号Reset，所述第二补偿晶体管M2的源极与所述驱动晶体管MDT的栅极连接，所述第二补偿晶体管M2的漏极接入参考电压Vref；
所述数据写入单元包括数据写入晶体管M3；
所述数据写入晶体管M3的栅极接入扫描信号Gate，所述数据写入晶体管M3的源极与所述驱动晶体管MDT的栅极连接，所述数据写入晶体管M3的漏极接入数据电压SD；
所述发光控制单元包括第一发光控制晶体管M4和第二发光控制晶体管M5，其中，
所述第一发光控制晶体管M4的栅极接入发光控制信号EM，所述第一发光控制晶体管M4的源极接入高电压VDD，所述第一发光控制晶体管M4的漏极与所述驱动晶体管MDT的源极连接；
所述第二发光控制晶体管M5的栅极接入所述发光控制信号EM，所述第二发光控制晶体管M5的源极与所述驱动晶体管MDT的漏极连接，所述第二发光控制晶体管M5的漏极与有机发光二极管D1的阳极连接；
有机发光二极管D1的阴极接入低电压VSS；
在图5中，第一存储电容C1和第二存储电容C2的连接节点为节点A。
在图5所示的具体实施例中，所有的晶体管都为p型晶体管，在实际操作时，上述晶体管也可以被替换为n型晶体管。
如图6所示，本公开如图5所示的像素驱动电路的具体实施例在工作时，
在复位阶段T1，EM是低压开启信号，Reset是低压开启信号，Gate为高压关断信号，EM控制的M4和M5都打开，Reset控制的M1和M2也都打开，D1的阳极与MDT的漏极相连接，Vini写入MDT的漏极和D1的阳极，将D1的阳极的电位复位成Vini；同时Vini和VSS之间的电位差最优为小于D1的开启阈值电压，这样来保证此时D1是不发光的，以便提升显示的暗态亮度品质，提升对比度；VDD写入MDT的源极，同时Vref写入到MDT的栅极，其中Vref和VDD的电位差，即是MDT的Vgs，来保证MDT有大电流流过，依此来消除或者降低显示面板在长时间用小电流显示低亮度，过渡到大电流显示高亮度时，MDT在小电流下的由于应力引起的特性漂移，消除或者减弱其所导致的黑色画面变换到白色画面时的亮度拖尾现象；其中，该阶段MDT的大电流根据不同的Vref和Vini电压情况，MDT可以工作在放大区或饱和区，理论上最好的状态是MDT工作在饱和区，此时可以最大化流经MDT的电流；
在该复位阶段T1，对C1两端电位进行复位，使本帧信号的写入不受上帧信号的影响；
在阈值补偿阶段T2：EM和Gate都为高压关断信号，Reset为低压开启信号，由EM控制的M4和M5都关断；由Reset控制的M1和M2继续开启，这样保持在C1和C2连接节点(即图3中的节点A)的电荷，便会通过MDT和M1向输出低电位的Vini的复位电压线进行放电，直到MDT的源极电位低至使MDT关断，此时MDT的Vgs-Vth＝0，因为Vg＝Vref，所以Vs＝Vg-Vth＝Vref-Vth，这样C1两端的电位差就是MDT的阈值电压Vth；
在数据写入阶段T3：EM和Reset都为高压关断信号，Gate为低压开启信号，EM控制的M4和M5都关断，Reset控制的M1和M2也都关断；由Gate控制的M3处于开启状态，SD便写入到MDT的栅极，即C1与MDT的栅极连接处；在由C1和C2构成的串联电路中，C1和C2连接处的电压处于浮空状态，C1和C2在数据写入阶段T3的电荷总量保持与C1和C2在阈值补偿阶段T2的电荷总量一致；假设此时C1和C2连接节点电压为X，那么根据电容变化前后电荷量不变的原则来推导，具体如下：
变化前C1和C2电荷总量为：(Vref-Vth-Vref)×C1+[VDD-(Vref-Vth)] ×C2；
变化后C1和C2电荷总量是：(X-SD)×C1+(VDD-X)×C2；
根据变化前后电荷量保持不变原理，可以推导出X＝(Vref×C2-SD×C1)/(C2-C1)-Vth；
在发光阶段T4：Gate和Reset都为高压关断信号，使得M1、M2和M3都处于关闭状态；EM是低压开启信号，使得M4和M5都打开，其中M5的开启将D1的阳极与MDT的漏极相连接，M3的开启将VDD写入到MDT的源极和C1和C2的连接处，因为C2的第一端接入VDD，此时C1和C2连接处的电位变化不会影响其电容变化，此时C1和MDT的栅极连接处处于浮空状态，C1和MDT的栅极连接处的电位会通过C1来跟随C1和C2的连接处的电位而变化，并且变化前后C1保持的电荷量不变(即C1在数据写入阶段T3保持的电荷量和C1在发光阶段T4保持的电荷量相等)；
C1变化前的电荷量是：(X-Vref)×C1＝[(Vref×C2-SD×C1)/(C2-C1)-Vth-Vref]×C1，C1变化后的电荷量是(假设变化后MDT栅极电位是Y)：(VDD-Y)×C1；根据电荷守恒原理，推导出Y＝VDD+Vth+C2×(SD-Vref)/(C2-C1)；由于MDT处于饱和区，根据晶体管饱和区电流公式可知：
Ids＝1/2×K×(Vgs-Vth)2＝1/2×K×(VDD+Vth+C2×(SD-Vref)/(C2-C1)-VDD-Vth)2＝1/2×K×(C2×(SD-Vref)/(C2-C1))2；
其中，Ids为MDT工作在饱和区时的漏源电流，K为电流参数，K的数值相对稳定，可以算为常量；C2/(C2-C1)是电容值，也可以看作是常量，这样决定Ids大小的就只有数据电压SD和参考电压Vref，而Vref是一个直流电压信号，因此决定Ids大小的只有数据电压SD，因此本公开如图3所示的像素驱动电路的具体实施例的电路结构既可以补偿驱动晶体管MDT的阈值电压差异性，也可以补偿电源信号VDD上的IR Drop(IR压降)，同时还可以在相同数据电压下，根据C2/(C2-C1)的比例，实现相同数据电压下，不同的电流输出，即实现数据的压缩比效果。
如图7所示，本公开实施例所述的像素驱动方法，应用于上述的像素驱动方法，包括：
阈值补偿步骤S1：在每一显示周期的阈值补偿阶段，阈值补偿单元控制 驱动晶体管的栅极接入参考电压而驱动晶体管的第二极与复位电压线连接，从而使得驱动晶体管导通而向起始电压线放电，直至驱动晶体管关断；
数据写入步骤S2：在每一显示周期的数据写入阶段，数据写入单元控制数据电压写入驱动晶体管的栅极；
发光步骤S3：在每一显示周期的发光阶段，发光控制单元控制第一电源电压驱动晶体管的第一极，控制驱动晶体管的第二极与发光元件连接，以控制驱动晶体管导通以驱动发光元件发光；
第一存储电容和第二存储电容的电荷总量在阈值补偿阶段和数据写入阶段相等；
第一存储电容在数据写入阶段的电荷量与第一存储电容在发光阶段的电荷量相等。
本公开实施例所述的像素驱动方法通过在阈值补偿阶段和发光阶段对第一存储电容和第二存储电容的电荷量的控制，可以实现驱动晶体管在发光阶段驱动发光元件的电流与驱动晶体管的阈值电压和电源电压无关，仅与数据电压、参考电压、第一存储电容的电容值和第二存储电容的电容值有关，因此在数据电压和参考电压相同的情况下通过改变第一存储电容的电容值和第二存储电容的电容值即可实现不同的电流输出，实现数据的不同压缩比。
在本公开所述的像素驱动方法的一可选的实施例中，每一显示周期在所述阈值补偿阶段时间还包括复位阶段；如图8所示，所述像素驱动方法还包括：
复位步骤S0：在每一显示周期的复位阶段，阈值补偿单元控制所述驱动晶体管的栅极接入参考电压而所述驱动晶体管的第二极与复位电压线连接，发光控制单元控制所述驱动晶体管的第一极接入所述第一电源电压，控制所述驱动晶体管的第二极与所述发光元件连接；所述驱动晶体管在所述复位阶段处于放大状态或饱和状态。
在本公开所述的像素驱动方法的可选实施例中，驱动晶体管在复位阶段处于放大状态或饱和状态，以保证驱动晶体管有大电流流过，来消除或降低显示面板由长时间用小电流显示低亮度过渡到用大电流显示高亮度时驱动晶体管在小电流下的由于应力引起的特性漂移，从而消除或减弱其所导致的黑 色画面变换到白色画面时的亮度拖尾现象。
并且，在本公开所述的像素驱动方法的该可选实施例中，在复位阶段，阈值补偿单元，还用于在所述复位阶段控制所述驱动晶体管的栅极(即所述第一存储电容的第一端)接入参考电压而所述驱动晶体管的第二极(即所述第一存储电容的第二端)与复位电压线连接，以对第一存储电容两端电位进行初始化，以使得本帧信号的写入不受上帧信号的影响。
本公开另一实施例所述的像素驱动方法包括：
在每一显示周期的阈值补偿阶段：发光控制信号和扫描信号都为关断信号，复位控制信号为开启信号，复位电压线输出低电位的复位电压，第一发光控制晶体管和第二发光控制晶体管都关断，第一补偿晶体管和第二补偿晶体管都开启，保持在第一存储电容和第二存储电容连接节点处的电荷通过驱动晶体管和第一补偿晶体管向所述复位电压线进行放电，直到驱动晶体管的源极电位低至使驱动晶体管关断；
在每一显示周期的数据写入阶段：发光控制信号和复位控制信号都为关断信号，扫描信号为开启信号，第一发光控制晶体管和第二发光控制晶体管都关断，第一补偿晶体管和第二补偿晶体管都关断；数据写入晶体管开启，数据电压写入驱动晶体管的栅极；第一存储电容和第二存储电容的连接节点处于浮空状态，所述第一存储电容和所述第二存储电容的电荷总量在所述阈值补偿阶段和所述数据写入阶段相等；
在每一显示周期的发光阶段：扫描信号和复位控制信号都为关断信号，使得第一补偿晶体管、第二补偿晶体管和数据写入晶体管都关断，发光控制信号是开启信号，使得第一发光控制晶体管和第二发光控制晶体管都打开，使得发光元件与驱动晶体管的第二极相连接，第一电源电压写入驱动晶体管的第一极与第一存储电容和第二存储电容的连接处，第二存储电容的第一端接入第一电源电压，第一存储电容和驱动晶体管的栅极的连接节点处于浮空状态，所述第一存储电容在所述数据写入阶段的电荷量与所述第一存储电容在所述发光控制阶段的电荷量相等，以使得在发光阶段流过驱动晶体管的电流仅与所述数据电压、所述第一存储电容的电容值和所述第二存储电容的电容值有关。
在本公开所述的像素驱动方法的一可选的实施例中，每一显示周期在所述阈值补偿阶段时间还包括复位阶段；所述像素驱动方法还包括：
在每一显示周期的复位阶段，发光控制信号和复位控制信号都是开启信号，扫描信号为关断信号，第一发光控制晶体管和第二发光控制晶体管都打开，第一补偿晶体管和第二补偿晶体管也都打开，数据写入晶体管关断，发光元件与驱动晶体管的第二极相连接，复位电压写入驱动晶体管的第二极，所述驱动晶体管处于放大状态或饱和状态，以保证驱动晶体管有大电流流过，来消除或降低显示面板由长时间用小电流显示低亮度过渡到用大电流显示高亮度时驱动晶体管在小电流下的由于应力引起的特性漂移，从而消除或减弱其所导致的黑色画面变换到白色画面时的亮度拖尾现象。
并且，在本公开所述的像素驱动方法的该可选实施例中，在复位阶段，阈值补偿单元，还用于在所述复位阶段控制所述驱动晶体管的栅极(即所述第一存储电容的第一端)接入参考电压而所述驱动晶体管的第二极(即所述第一存储电容的第二端)与复位电压线连接，以对第一存储电容两端电位进行初始化，以使得本帧信号的写入不受上帧信号的影响。
可选的，当所述发光元件包括有机发光二极管，有机发光二极管的阳极通过所述发光控制单元与所述驱动晶体管的第二极连接，有机发光二极管的阴极接入第二电源电压时，在所述复位阶段，所述复位电压线输出的复位电压与所述第二电源电压之间的电压差小于所述有机发光二极管的开启阈值电压，以保证有机发光二极管在复位阶段不发光。
本公开实施例所述的显示面板包括上述的像素驱动电路。
本公开实施例所述的显示装置包括上述的显示面板。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (19)

  1. 一种像素驱动电路，包括驱动晶体管、第一存储电容、第二存储电容、阈值补偿单元、数据写入单元和发光控制单元，其中，
    所述驱动晶体管的栅极与所述第一存储电容的第一端连接，所述驱动晶体管的第一极与所述第一存储电容的第二端连接；
    所述第二存储电容的第一端接入第一电源电压，所述第二存储电容的第二端与所述第一存储电容的第二端连接；
    所述阈值补偿单元用于在每一显示周期的阈值补偿阶段控制所述驱动晶体管的栅极接入参考电压而使得所述驱动晶体管的第二极与复位电压线连接，从而使得驱动晶体管导通而向所述复位电压线放电，直至所述驱动晶体管关断；
    所述数据写入单元用于在每一显示周期的数据写入阶段控制数据电压写入所述驱动晶体管的栅极；
    所述发光控制单元用于在每一显示周期的发光阶段控制第一电源电压接入所述驱动晶体管的第一极，控制所述驱动晶体管的第二极与发光元件连接，以控制驱动晶体管导通以驱动发光元件发光；
    所述第一存储电容的电荷总量和所述第二存储电容的电荷总量在所述阈值补偿阶段和所述数据写入阶段相等；
    所述第一存储电容在所述数据写入阶段的电荷量与所述第一存储电容在所述发光控制阶段的电荷量相等。
  2. 如权利要求1所述的像素驱动电路，其中，每一显示周期内，所述阈值补偿阶段还包括复位阶段；
    所述阈值补偿单元还用于在所述复位阶段控制所述驱动晶体管的栅极接入参考电压而所述驱动晶体管的第二极接入复位电压；
    所述发光控制单元还用于在所述复位阶段控制所述驱动晶体管的第一极接入所述第一电源电压，控制所述驱动晶体管的第二极与所述发光元件连接；
    所述驱动晶体管在所述复位阶段处于放大状态或饱和状态。
  3. 如权利要求2所述像素驱动电路，其中，所述发光元件包括有机发光 二极管；
    所述有机发光二极管的阳极通过所述发光控制单元与所述驱动晶体管的第二极连接，所述有机发光二极管的阴极接入第二电源电压；
    在复位阶段，所述复位电压线输出的复位电压与所述第二电源电压之间的电压差小于所述有机发光二极管的开启阈值电压。
  4. 如权利要求1所述的像素驱动电路，其中，所述阈值补偿单元包括第一补偿晶体管和第二补偿晶体管，其中，
    所述第一补偿晶体管的栅极接入复位控制信号，所述第一补偿晶体管的第一极与所述驱动晶体管的第二极连接，所述第一补偿晶体管的第二极与所述复位电压线连接；
    所述第二补偿晶体管的栅极接入所述复位控制信号，所述第二补偿晶体管的第一极与所述驱动晶体管的栅极连接，所述第二补偿晶体管的第二极接入所述参考电压。
  5. 如权利要求3所述的像素驱动电路，其中，所述阈值补偿单元包括第一补偿晶体管和第二补偿晶体管，其中，
    所述第一补偿晶体管的栅极接入复位控制信号，所述第一补偿晶体管的第一极与所述驱动晶体管的第二极连接，所述第一补偿晶体管的第二极与所述复位电压线连接；
    所述第二补偿晶体管的栅极接入所述复位控制信号，所述第二补偿晶体管的第一极与所述驱动晶体管的栅极连接，所述第二补偿晶体管的第二极接入所述参考电压。
  6. 如权利要求4所述的像素驱动电路，所述第一补偿晶体管和所述第二补偿晶体管为P型晶体管。
  7. 如权利要求1所述的像素驱动电路，其中，所述数据写入单元包括数据写入晶体管，
    所述数据写入晶体管的栅极接入扫描信号，所述数据写入晶体管的第一极与所述驱动晶体管的栅极连接，所述数据写入晶体管的第二极接入数据电压。
  8. 如权利要求7所述的像素驱动电路，所述写入晶体管为P型晶体管。
  9. 如权利要求5所述的像素驱动电路，其中，所述数据写入单元包括数据写入晶体管，
    所述数据写入晶体管的栅极接入扫描信号，所述数据写入晶体管的第一极与所述驱动晶体管的栅极连接，所述数据写入晶体管的第二极接入数据电压。
  10. 如权利要求1所述的像素驱动电路，其中，所述发光控制单元包括第一发光控制晶体管和第二发光控制晶体管，其中，
    所述第一发光控制晶体管的栅极接入发光控制信号，所述第一发光控制晶体管的第一极接入所述第一电源电压，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极连接；以及，
    所述第二发光控制晶体管的栅极接入所述发光控制信号，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极连接，所述第二发光控制晶体管的第二极与所述发光元件连接。
  11. 如权利要求10所述的像素驱动电路，其中，所述第一发光控制晶体管和所述第二发光控制晶体管为P型晶体管。
  12. 如权利要求9所述的像素驱动电路，其中，所述发光控制单元包括第一发光控制晶体管和第二发光控制晶体管，其中，
    所述第一发光控制晶体管的栅极接入发光控制信号，所述第一发光控制晶体管的第一极接入所述第一电源电压，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极连接；以及，
    所述第二发光控制晶体管的栅极接入所述发光控制信号，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极连接，所述第二发光控制晶体管的第二极与所述发光元件连接。
  13. 一种像素驱动方法，应用于如权利要求1所述的像素驱动电路，其中，所述像素驱动方法包括：
    在每一显示周期的阈值补偿阶段，阈值补偿单元控制驱动晶体管的栅极接入参考电压而驱动晶体管的第二极与复位电压线连接，从而使得驱动晶体管导通而向起始电压线放电，直至驱动晶体管关断；
    在每一显示周期的数据写入阶段，数据写入单元控制数据电压写入驱动 晶体管的栅极；
    在每一显示周期的发光阶段，发光控制单元控制第一电源电压驱动晶体管的第一极，控制驱动晶体管的第二极与发光元件连接，以控制驱动晶体管导通以驱动发光元件发光；
    第一存储电容和第二存储电容的电荷总量在阈值补偿阶段和数据写入阶段相等；
    第一存储电容在数据写入阶段的电荷量与第一存储电容在发光阶段的电荷量相等。
  14. 如权利要求13所述的像素驱动方法，其中，在每一显示周期，所述阈值补偿阶段还包括复位阶段；所述像素驱动方法还包括：
    在每一显示周期的复位阶段，阈值补偿单元控制所述驱动晶体管的栅极接入参考电压而所述驱动晶体管的第二极与复位电压线连接，发光控制单元控制所述驱动晶体管的第一极接入所述第一电源电压，控制所述驱动晶体管的第二极与所述发光元件连接；
    所述驱动晶体管在所述复位阶段处于放大状态或饱和状态。
  15. 一种像素驱动方法，应用于如权利要求12所述的像素驱动电路，其中，所述像素驱动方法包括：
    在每一显示周期的阈值补偿阶段：发光控制信号和扫描信号都为关断信号，复位控制信号为开启信号，复位电压线输出低电位的复位电压，第一发光控制晶体管和第二发光控制晶体管都关断，第一补偿晶体管和第二补偿晶体管都开启，保持在第一存储电容和第二存储电容连接节点处的电荷通过驱动晶体管和第一补偿晶体管向所述复位电压线进行放电，直到驱动晶体管的源极电位低至使驱动晶体管关断；
    在每一显示周期的数据写入阶段：发光控制信号和复位控制信号都为关断信号，扫描信号为开启信号，第一发光控制晶体管和第二发光控制晶体管都关断，第一补偿晶体管和第二补偿晶体管都关断；数据写入晶体管开启，数据电压写入驱动晶体管的栅极；第一存储电容和第二存储电容的连接节点处于浮空状态，所述第一存储电容和所述第二存储电容的电荷总量在所述阈值补偿阶段和所述数据写入阶段相等；
    在每一显示周期的发光阶段：扫描信号和复位控制信号都为关断信号，使得第一补偿晶体管、第二补偿晶体管和数据写入晶体管都关断，发光控制信号是开启信号，使得第一发光控制晶体管和第二发光控制晶体管都打开，使得发光元件与驱动晶体管的第二极相连接，第一电源电压写入驱动晶体管的第一极与第一存储电容和第二存储电容的连接处，第二存储电容的第一端接入第一电源电压，第一存储电容和驱动晶体管的栅极的连接节点处于浮空状态，所述第一存储电容在所述数据写入阶段的电荷量与所述第一存储电容在所述发光控制阶段的电荷量相等，以使得在发光阶段流过驱动晶体管的电流仅与所述数据电压、所述第一存储电容的电容值和所述第二存储电容的电容值有关。
  16. 如权利要求15所述的像素驱动方法，其中，在每一显示周期，所述阈值补偿阶段还包括复位阶段；所述像素驱动方法还包括：
    在每一显示周期的复位阶段，发光控制信号和复位控制信号都是开启信号，扫描信号为关断信号，第一发光控制晶体管和第二发光控制晶体管都打开，第一补偿晶体管和第二补偿晶体管也都打开，数据写入晶体管关断，发光元件与驱动晶体管的第二极相连接，复位电压写入驱动晶体管的第二极，所述驱动晶体管处于放大状态或饱和状态。
  17. 如权利要求16所述的像素驱动方法，其中，所述发光元件包括有机发光二极管，所述有机发光二极管的阳极通过所述发光控制单元与所述驱动晶体管的第二极连接，所述有机发光二极管的阴极接入第二电源电压时，在所述复位阶段，所述复位电压线输出的复位电压与所述第二电源电压之间的电压差小于所述有机发光二极管的开启阈值电压。
  18. 一种显示面板，包括如权利要求1所述的像素驱动电路。
  19. 一种显示装置，包括如权利要求18所述的显示面板。
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