WO2022156078A1 - 一种μLED单元电路、其发光控制方法和像素装置 - Google Patents

一种μLED单元电路、其发光控制方法和像素装置 Download PDF

Info

Publication number
WO2022156078A1
WO2022156078A1 PCT/CN2021/087633 CN2021087633W WO2022156078A1 WO 2022156078 A1 WO2022156078 A1 WO 2022156078A1 CN 2021087633 W CN2021087633 W CN 2021087633W WO 2022156078 A1 WO2022156078 A1 WO 2022156078A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
μled
signal
voltage
gate
Prior art date
Application number
PCT/CN2021/087633
Other languages
English (en)
French (fr)
Inventor
耿玓
苏悦
李泠
卢年端
刘明
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Publication of WO2022156078A1 publication Critical patent/WO2022156078A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present application relates to the technical field of semiconductors, and in particular, to a ⁇ LED unit circuit, a light emission control method thereof, and a pixel device.
  • TFT oxide thin film transistor
  • a-IGZO amorphous indium gallium zinc oxide
  • Mass transfer technology of ⁇ LED In order to reduce costs and maximize the advantages of ⁇ LEDs, the mass transfer technology of ⁇ LEDs is critical.
  • PWM digital pulse width modulation
  • the active ⁇ LED display technology based on miniature silicon-based CMOS driving is expensive, and the use of PAM driving means that the driving circuit needs an extremely fast clock signal to meet extremely high voltage resolution.
  • the use of CMOS driving has adverse effects on the flexibility, transparency and thickness of the panel.
  • the drive control signal can be generated by using the on-plane drive circuit (GOA).
  • the PWM scheme divides the display time of each frame into n subframes in equal proportions. Each pixel unit needs to be turned on once in each subframe. The data voltage input by the IC each time determines whether the ⁇ LED emits light at the corresponding time of the subframe.
  • This method can achieve higher gray scales, but the driving speed of the GOA circuit is limited. When the resolution is high, multiple turn-on will result in a long part of the time that cannot be used for light emission, thus limiting the improvement of the gray scale number.
  • the embodiments of the present application aim to provide a ⁇ LED unit circuit, a light-emitting control method and a pixel device to solve the problem that the driving speed of the existing GOA circuit is limited. A part of the time cannot be used for lighting, thus limiting the problem of increasing the number of gray levels.
  • an embodiment of the present application provides a ⁇ LED unit circuit including: a PWM signal generation circuit, a lighting control circuit, and a ⁇ LED, wherein the PWM signal generation circuit is configured to receive a lighting control signal and a comparison reference signal and based on the The lighting control signal and the comparison reference signal generate PWM signals with different pulse widths, wherein the comparison reference signal is a linearly decreasing ramp signal; the lighting control circuit includes a driving transistor for generating from the PWM signal a circuit that receives the PWM signals of different pulse widths and controls on-times of the drive transistors based on the PWM signals of different pulse widths to provide a drive current; and the ⁇ LED for receiving the PWM signals from the lighting control circuit driving current and controlling the light-emitting time of the ⁇ LED based on the driving current.
  • the beneficial effects of the above technical solutions are as follows: in the ⁇ LED unit circuit provided by the embodiments of the present application, through the circuit structure and operating mode of the present application, the combination of the PAM and PWM drive modes in the pixel can be realized, which is compatible with the traditional drive mode, It also satisfies the digital control of high grayscale.
  • the modulated light-emitting time of the present application can reach more than 75% of the entire refresh time, and 12bit grayscale can be achieved.
  • the PWM signal generation circuit includes a reset circuit, a compensation circuit and an inverter, wherein the reset circuit is used to receive a reset signal and initialize the ⁇ LED unit circuit; the inverter an inverter, connected to the output terminal of the reset circuit, and used to control the conduction of the transistors in the inverter based on the comparison between the input terminal voltage of the inverter and the power supply input terminal voltage, so as to generate different a PWM signal of pulse width; and the compensation circuit for compensating the input terminal voltage of the inverter and the power supply input terminal voltage.
  • the reset circuit includes a first transistor, wherein a gate of the first transistor receives the reset signal, a source of the first transistor is connected to a reference power supply voltage, and the first transistor receives the reset signal.
  • the drain of a transistor is connected to the input of the inverter.
  • the inverter includes a fourth transistor, a fifth transistor and a sixth transistor connected as inverters, and the ⁇ LED unit circuit further includes a first capacitor, wherein the fourth transistor is The gate receives the light-emitting control signal, the source of the fourth transistor is connected to the first power supply voltage, and the drain of the fourth transistor is the power input terminal and is connected to the source of the sixth transistor;
  • the gate of the sixth transistor is the input terminal of the inverter and receives the comparison reference signal through the first capacitor, and the drain of the sixth transistor is the output terminal of the inverter and is connected with the a source of a fifth transistor is connected; and a gate of the fifth transistor receives the light-emitting control signal, and a drain of the fifth transistor is connected to the reference power supply voltage, wherein the first power supply voltage is less than the the reference supply voltage.
  • the compensation circuit includes a second transistor and a third transistor, wherein the gate of the second transistor is used to receive a row scan signal, and the source of the second transistor is connected to the sixth transistor.
  • the gate of the transistor is connected, and the drain of the second transistor is connected with the output terminal of the inverter; and the gate of the third transistor is used for receiving the row scan signal, and the third transistor has The source is connected to the drain of the fourth transistor and the source of the sixth transistor, and the drain of the third transistor receives a PWMD signal, wherein the PWMD signal is changed according to the luminance of the ⁇ LED Voltage value.
  • the lighting control circuit includes an edge improvement circuit and a driving circuit, wherein the edge correction circuit is used for receiving the PWM signals of different pulse widths and the lighting control signal and correcting the different edge steepness of the pulse width PWM signal; and the driving circuit for controlling the on-time of the driving transistor to provide the driving current based on the corrected PWM signals of different pulse widths.
  • the edge correction circuit includes a seventh transistor, an eighth transistor and a second capacitor, wherein the gate of the seventh transistor is connected to the output terminal of the inverter and is two capacitors receive a second supply voltage, the source of the seventh transistor is connected to the drain of the eighth transistor, and the drain of the seventh transistor is connected to the drain of the ninth transistor; and the The gate of the eighth transistor receives the light emission control signal, and the source of the eighth transistor receives the second power supply voltage.
  • the drive circuit includes the ninth transistor, a tenth transistor and a third capacitor, the tenth transistor is the drive transistor, wherein the gate of the ninth transistor receives the Line scan signal, the source of the ninth transistor receives the PAMD signal, and the PAMD signal is the voltage value when the light-emitting brightness is the highest; the source of the tenth transistor is connected to the second power supply voltage, the tenth The gate of the transistor is connected to the drain of the seventh transistor and the drain of the ninth transistor; and one end of the third capacitor is connected to the second power supply voltage, and the other end of the third capacitor is connected to The drain of the seventh transistor is connected to the drain of the ninth transistor, wherein the second power supply voltage is greater than the first power supply voltage and greater than the reference power supply voltage.
  • the cathode of the ⁇ LED is connected to the drain of the driving transistor and the anode of the ⁇ LED is used to receive the light-emitting control signal; or the anode of the ⁇ LED is connected to the drain of the driving transistor The connection and the cathode of the ⁇ LED are used to receive a third supply voltage.
  • the first to the tenth transistors are N-type TFT transistors.
  • an embodiment of the present application provides a pixel device including m ⁇ n ⁇ LED unit circuits according to the above embodiments.
  • an embodiment of the present application provides a ⁇ LED light emission control method, which is characterized by comprising a step of comparing light emission, wherein the step of comparing light emission includes: generating pulses with different pulse widths based on the light emission control signal EM1 and the comparison reference signal SWEEP The PWM signal, wherein, the comparison reference signal SWEEP is a linearly decreasing ramp signal; receiving the PWM signals of different pulse widths and controlling the on-time of the driving transistor based on the PWM signals of different pulse widths to provide a driving current; and receiving the driving current from the light emission control circuit and controlling the light emission time of the ⁇ LED based on the driving current.
  • the drive current is:
  • the PAMD is the voltage value when the light-emitting brightness is the highest
  • VLED is the voltage of the ⁇ LED
  • V th10 is the driving Threshold voltage of the transistor.
  • the initialization step initializes the ⁇ LED unit circuit of the pixel device based on the reset signal RESET; and the row scanning step, After the initialization step, the ⁇ LED unit circuits of the pixel device are scanned row by row based on the row scan signal SN.
  • the initialization step includes: providing the reset signal RESET to the gate of the first transistor T1, and the first transistor T1 is turned on, so that the source of the first transistor T1 is connected to the reference
  • the power supply voltage REF is connected to set the drain of the first transistor T1 to the reference power supply voltage REF, wherein the reset signal is low level.
  • the row scanning step includes: providing the row scanning signal SN to the gates of the second transistor T2 and the third transistor T3, the second transistor T2, the third transistor T3, The sixth transistor T6 is turned on, so that the source of the sixth transistor T6 is connected to the PWMD signal by turning on the third transistor T3 and set to PWMD, and the drain of the sixth transistor T6 is connected to the PWMD signal through the third transistor T3.
  • the second transistor T2 is connected to the gate of the sixth transistor T6, so that the drain voltage of the sixth transistor T6 and the gate voltage of the sixth transistor T6 are PWMD-
  • the PWMD signal is a voltage value that changes according to the luminance of the ⁇ LED;
  • the row scan signal SN is provided to the gate of the ninth transistor T9, so that the ninth transistor T9 is turned on, so that the ninth transistor T9 is turned on.
  • the gate of the driving transistor is set to PAMD, wherein the PAMD is the voltage value when the luminous brightness of the ⁇ LED is the highest, and the row scanning signal SN is at a low level.
  • the step of comparing light emission further includes: providing the light emission control signal EM1 to the gates of the fourth transistor T4 and the fifth transistor T5 and providing the comparison reference signal SWEEP to the sixth transistor via a capacitor
  • the gate of the transistor T6 turns on the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 and is connected as an inverter, so that the source of the sixth transistor T6 is the source of the inverter
  • the power supply input terminal is connected to the first power supply voltage VGL via the fourth transistor T4, so that the voltage of the power supply input terminal of the inverter is the first power supply voltage VGL;
  • the gate of the sixth transistor T6 is the inverter
  • the input terminal of the inverter and the voltage of the power input terminal of the inverter is PWMD+V th6 - ⁇ SWEEP; the drain of the sixth transistor T6 is the output terminal of the inverter and is connected to the inverter through the fifth transistor T5.
  • the reference power supply voltage REF is connected, so that the voltage of the output terminal of the inverter is high and the seventh transistor T7 is kept off, wherein the size of the sixth transistor T6 is larger than that of the fifth transistor T5, and all
  • the light emission control signal EM1 is a pulse signal.
  • the step of comparing light emission further includes: turning on the driving transistor T10, so that the gate voltage of the driving transistor T10 maintains the PAMD signal, and the source of the driving transistor T10 is the same as the first power supply voltage VDD is connected to provide the drive current so that the ⁇ LED starts to emit light.
  • the step of comparing light emission further includes: when the comparison reference signal SWEEP increases linearly so that the voltage PWMD+V th6 - ⁇ SWEEP of the power input terminal of the inverter is greater than VGH+V th6 , the The sixth transistor T6 is turned off to raise the voltage of the output terminal of the inverter to REF, so that the seventh transistor T7 is turned on to transmit the first power supply voltage VDD to the gate of the driving transistor T10 or to The gate of the driving transistor T10 is set to the first power supply voltage VDD, and the driving transistor T10 is turned off so that the ⁇ LED stops emitting light.
  • the light-emitting control signal EM2 is provided to the eighth transistor T8, and the eighth transistor T8 and the driving transistor T10 are turned on, so that the gate voltage of the driving transistor T10 maintains the PAMD signal, the source of the driving transistor T10 is connected to the first power supply voltage VDD to provide the driving current so that the ⁇ LED starts to emit light, wherein the light-emitting control signal EM2 and the light-emitting control signal EM1 are pulse signals, and The rising edge of the lighting control signal EM2 lags behind the rising edge of the lighting control signal EM1.
  • the present application can achieve at least one of the following beneficial effects:
  • the combination of pulse amplitude modulation PAM (Pulse amplitude modulation) and PWM drive mode in the pixel can be realized, which is not only compatible with the traditional drive mode, but also satisfies the digital control of high gray scale.
  • PAM Pulse amplitude modulation
  • the modulated light-emitting time of the present application can reach more than 75% of the entire refresh time, and 12bit grayscale can be achieved.
  • connection mode of T3, T2 and T6 constitutes a diode connection structure.
  • the T6 source voltage is fixed, and the gate is discharged through T6, the threshold voltage of T6 can be detected, and the threshold voltage of T6 can be compared between the light-emitting stage and the T6 threshold voltage. It doesn't matter. It avoids the effect of positive bias stress (PBS, Positive bias stress) caused by the positive bias voltage on the T6 threshold voltage to cause the comparison result to drift.
  • PBS Positive bias stress
  • the on-time of T6 can be controlled, and the on-time of T6 can control the level of point B, thereby controlling the starting time of T7, and then the on-time of T10, and finally realizing the light-emitting time of ⁇ LED control, realize PWM control of luminous brightness.
  • Figure 1 shows the ⁇ LED current-voltage transfer curve obtained by the traditional analog voltage driving circuit.
  • FIG. 2 shows the active ⁇ LED display of the existing miniature silicon-based CMOS.
  • Fig. 3 is the PWM driving scheme of the existing ⁇ LED high gray scale display.
  • FIG. 4 is a circuit structure diagram and a timing diagram of a ⁇ LED unit circuit according to an embodiment of the present application.
  • FIG. 5 is a circuit structure diagram of an initialization stage of a ⁇ LED unit circuit according to an embodiment of the present application.
  • FIG. 6 is a circuit structure diagram of a row scanning stage (also known as a data input compensation stage) of a ⁇ LED unit circuit according to an embodiment of the present application.
  • FIG. 7 is a circuit structure diagram of a comparative light-emitting stage of a ⁇ LED unit circuit according to an embodiment of the present application.
  • FIG. 8 is a timing diagram of different lighting control signals of a ⁇ LED unit circuit according to an embodiment of the present application.
  • FIG. 9 is a PAM and PWM step-by-step input circuit diagram and a timing diagram of a ⁇ LED unit circuit according to an embodiment of the present application.
  • FIG. 10 is a circuit structure diagram and a timing diagram of a ⁇ LED unit circuit according to an optional embodiment of the present application.
  • a specific embodiment of the present application discloses a ⁇ LED unit circuit, including a PWM signal generation circuit, a lighting control circuit and a ⁇ LED.
  • a ⁇ LED unit circuit including a PWM signal generation circuit, a lighting control circuit and a ⁇ LED.
  • the ⁇ LED unit circuit will be described in detail with reference to FIG. 4 .
  • the PWM signal generating circuit is used for receiving the lighting control signal EM and the comparison reference signal SWEEP and generating PWM signals with different pulse widths based on the lighting control signal EM and the comparison reference signal SWEEP, wherein the comparison reference signal SWEEP is linearly decreasing. ramp signal.
  • the PWM signal generation circuit includes a reset circuit, a compensation circuit and an inverter, wherein, with reference to FIG. 4 and FIG. 5 , the reset circuit is used to receive the reset signal RESET and initialize the ⁇ LED unit circuit; with reference to FIG. 4 and FIG.
  • the inverter is connected to the output of the reset circuit and is used to control the conduction of the transistors in the inverter based on the comparison of the voltage at the input of the inverter (ie, point A) with the voltage at the input of the power supply (ie, point D). to generate PWM signals with different pulse widths; and with reference to Figures 4 and 6, a compensation circuit for compensating the input terminal voltage of the inverter (ie, point A) and the power supply input terminal voltage (ie, point D) .
  • the reset circuit includes a first transistor T1, wherein the gate of the first transistor T1 receives the reset signal RESET, the source of the first transistor T1 is connected to the reference supply voltage REF, and the drain of the first transistor T1 ( That is, point A) is connected to the input of the inverter.
  • the inverter includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6 connected as inverters, and the ⁇ LED unit circuit further includes a first capacitor C1, wherein the gate of the fourth transistor T4 receives the lighting control signal EM, The source of the fourth transistor T4 is connected to the first power supply voltage VGL, and the drain of the fourth transistor T4 is a power input terminal (ie, point D) and is connected to the source of the sixth transistor T6; the gate of the sixth transistor T6 is The input terminal (ie, point A) of the inverter receives the comparison reference signal SWEEP via the first capacitor C1, and the drain of the sixth transistor T6 is the output terminal (ie, point B) of the inverter and is connected with the output terminal of the fifth transistor T5.
  • the compensation circuit includes a second transistor T2 and a third transistor T3, wherein the gate of the second transistor T2 is used to receive the row scan signal SN, the source of the second transistor T2 is connected to the gate of the sixth transistor T6, and the second transistor T2 is used for receiving the row scan signal SN.
  • the drain of the transistor T2 is connected with the output terminal (ie, point B) of the inverter; and the gate of the third transistor T3 is used for receiving the row scan signal SN, and the source of the third transistor T3 is connected with the drain of the fourth transistor T4
  • the pole is connected to the source of the sixth transistor T6, and the drain of the third transistor T3 receives a PWMD signal, wherein the PWMD signal is a voltage value that changes according to the luminance of the ⁇ LED.
  • the first to sixth transistors T1 to T6 are N-type TFT transistors.
  • the lighting control circuit includes a driving transistor, namely, a tenth transistor T10 for receiving PWM signals of different pulse widths from the PWM signal generating circuit and controlling the on-time of the driving transistors based on the PWM signals of different pulse widths to provide driving. current.
  • the lighting control circuit includes an edge improvement circuit and a driving circuit, wherein the edge correction circuit is used to receive the PWM signals of different pulse widths and the lighting control signal EM and correct the edge steepness of the PWM signals of different pulse widths (refer to the timing diagram of FIG. 4 ).
  • the edge correction circuit includes a seventh transistor T7, an eighth transistor T8, and a second capacitor C2, wherein the gate of the seventh transistor T7 is connected to the output terminal (ie, point B) of the inverter and receives the second capacitor C2 via the second capacitor C2.
  • the driving circuit includes a ninth transistor T9, a tenth transistor T10 and a third capacitor C3.
  • the tenth transistor T10 is a driving transistor, wherein the gate of the ninth transistor T9 receives the row scan signal SN, and the drain of the ninth transistor T9 (ie, , point C) is connected to the drain of the seventh transistor T7, the source of the ninth transistor T9 receives the PAMD signal, and the PAMD signal is the voltage value when the light-emitting brightness is the highest; the source of the tenth transistor T10 is connected to the second power supply voltage VDD , the gate of the tenth transistor T10 is connected to the drain of the seventh transistor T7 and the drain of the ninth transistor T9 (ie, point C); and one end of the third capacitor C3 is connected to the second power supply voltage VDD, and the third capacitor The other end of C3 is connected to the drain of the seventh transistor T7 and the drain of the ninth transistor T9, wherein the second power supply voltage VDD is greater than the first power supply voltage VGL and greater than the reference power supply voltage REF.
  • the seventh transistor T7 to the tenth transistor T10 are
  • the ⁇ LED is used to receive a driving current from a lighting control circuit and control the lighting time of the ⁇ LED based on the driving current.
  • the cathode of the ⁇ LED is connected to the drain of the driving transistor and the anode of the ⁇ LED is used to receive the light emission control signal EM.
  • the anode of the ⁇ LED is connected to the drain of the driving transistor T10 and the cathode of the ⁇ LED is used to receive the third supply voltage VSS.
  • the driving transistor is an N-type TFT transistor.
  • the combination of pulse amplitude modulation PAM (Pulse amplitude modulation) and PWM driving mode in the pixel can be realized, which is compatible with both the
  • the traditional driving mode also satisfies the digital control of high gray scale.
  • the modulated light-emitting time of the present application can reach more than 75% of the entire refresh time, and 12bit grayscale can be achieved.
  • Another specific embodiment of the present application discloses a pixel device including m ⁇ n ⁇ LED unit circuits described in the above embodiments.
  • a ⁇ LED light emission control method which includes an initialization step, a line scanning step and a comparative light emission step.
  • the ⁇ LED light emission control method will be described in detail with reference to FIGS. 5 to 7 .
  • the ⁇ LED unit circuit of the pixel device is initialized based on the reset signal RESET.
  • the initialization step includes: providing a reset signal RESET to the gate of the first transistor T1, the first transistor T1 is turned on, so that the source of the first transistor T1 is connected to the reference power supply voltage REF to connect the first transistor T1 The drain of is set to the reference power supply voltage REF, wherein the reset signal RESET is low level.
  • the row scanning step includes: providing the row scanning signal SN to the gates of the second transistor T2 and the third transistor T3, the second transistor T2, the third transistor T3, and the sixth transistor T6 are turned on, so that the sixth transistor T2, the third transistor T3, and the sixth transistor T6 are turned on.
  • the source of the transistor T6 is connected to the PWMD signal via turning on the third transistor T3 and set to PWMD, and the drain of the sixth transistor T6 is connected to the gate of the sixth transistor T6 via the second transistor T2, so that the sixth transistor T6
  • the drain voltage of T6 and the gate voltage of the sixth transistor T6 are PWMD-
  • the row scan signal SN is provided to the ninth transistor T9 the gate, so that the ninth transistor T9 is turned on, so that the gate of the driving transistor is set to PAMD via the ninth transistor T9, wherein PAMD is the voltage value when the luminous brightness of the ⁇ LED is the highest, and the row scanning signal SN is low level .
  • the step of comparing light emission includes: generating PWM signals with different pulse widths based on the light emission control signal EM1 and the comparison reference signal SWEEP, wherein the comparison reference signal SWEEP is a linearly decreasing ramp signal; receiving PWM signals with different pulse widths and based on PWM signals of different pulse widths control the on-time of the driving transistor to provide the driving current; and receive the driving current from the light-emitting control circuit and control the light-emitting time of the ⁇ LED based on the driving current.
  • the drive current is:
  • PAMD is the voltage value when the luminous brightness is the highest
  • VLED is the voltage of the ⁇ LED
  • V th10 is the threshold voltage of the driving transistor T10.
  • the comparing light emission step further includes: supplying the light emission control signal EM1 to the gates of the fourth transistor T4 and the fifth transistor T5 and supplying the comparison reference signal SWEEP to the gate of the sixth transistor T6 via a capacitor,
  • the transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned on and connected as an inverter, so that the source of the sixth transistor T6 is the power supply input terminal (ie, point A) of the inverter and is connected to the first through the fourth transistor T4.
  • a power supply voltage VGL is connected so that the voltage of the power input terminal of the inverter is the first power supply voltage VGL; the gate of the sixth transistor T6 is the input terminal of the inverter and makes the power input terminal of the inverter (ie, point D) The voltage of PWMD+V th6 - ⁇ SWEEP; the drain of the sixth transistor T6 is the output terminal of the inverter (ie, point B) and is connected to the reference power supply voltage REF via the fifth transistor T5, so that the voltage of the output terminal of the inverter is The seventh transistor T7 is kept off at a high level, wherein the size of the sixth transistor T6 is larger than that of the fifth transistor T5, and the light emission control signal EM1 is a pulse signal.
  • the step of comparing light emission further includes: the driving transistor T10 is turned on, so that the gate voltage of the driving transistor T10 maintains the PAMD signal, and the source of the driving transistor T10 is connected to the first power supply voltage VDD to provide a driving current, so that the ⁇ LED starts to emit light.
  • the step of comparing light emission further includes: when the comparison reference signal SWEEP linearly increases so that the voltage PWMD+V th6 - ⁇ SWEEP of the power input terminal of the inverter is greater than VGH+V th6 , the sixth transistor T6 is turned off to increase the voltage of the output terminal of the inverter to REF, so that the seventh transistor T7 is turned on to transmit the first power supply voltage VDD to the gate of the driving transistor T10 or set the gate of the driving transistor T10 to the first power supply voltage VDD, the driving transistor T10 is turned off so that the ⁇ LED stops emitting light .
  • the light-emitting control signal EM2 is provided to the eighth transistor T8, and the eighth transistor T8 and the driving transistor T10 are turned on, so that the gate voltage of the driving transistor T10 maintains the PAMD signal, and the source of the driving transistor T10 is connected to the first.
  • a power supply voltage VDD is connected to provide a driving current to make the ⁇ LED start to emit light, wherein the light-emitting control signal EM2 and the light-emitting control signal EM1 are pulse signals, and the rising edge of the light-emitting control signal EM2 lags that of the light-emitting control signal EM1.
  • the pixel device includes a plurality of rows of ⁇ LED unit circuits.
  • the initialization step (1) in the timing diagram simultaneously initializes multiple rows of ⁇ LED unit circuits.
  • the line scanning step (2) in the timing diagram includes scanning the pixel device line by line.
  • the line scanning signal SN is provided to the first line to scan the first line
  • the line scanning signal SN+ 1 is supplied to the second row to line scan the second row, etc.
  • the line scanning step includes performing progressive scanning (2), eg, line scanning the signal.
  • the comparative light emission step (3) in the timing chart controls the light emission of the pixel device.
  • the initialization step (1) in FIG. 9 is exactly the same as the initialization step (1) in FIGS. 4 and 5 .
  • the comparative light-emitting step (4) in FIG. 9 is exactly the same as the comparative light-emitting step (3) in FIGS. 4 and 7 .
  • the row scan step of Figure 9 includes the PWAD input stage (2) in Figure 9 to set point D as PWAD and the PAMD input stage (3) to set point C to PAMD for each row of ⁇ LED cell circuits.
  • the time delay of SN relative to SNN is related to the number of scanning lines, and the specific time is SN scanning pulse width * scanning line number.
  • the time delay of SN+1 relative to SNN+1 is the same as the time delay of SN relative to SNN. Compared with the timing diagram in FIG.
  • the timing diagram in FIG. 9 sets point C to PAMD through additional line scan signals SNN, SNN+1 . . .
  • SNN line scan signals
  • SNN+1 and SNN+1 are used for row scanning of the first row of ⁇ LED unit circuits.
  • the anode of the ⁇ LED is connected to the drain of the driving transistor T10 and the cathode of the ⁇ LED is used to receive the third supply voltage VSS.
  • the light emission control signal EM is an inverted signal of the third power supply voltage VSS.
  • This application provides a new type of pixel circuit suitable for high grayscale ⁇ LED display.
  • the circuit combines PAM and PWM drive to convert analog voltage to digital pulse width inside the pixel.
  • the IC is compatible with traditional analog voltage drive circuit design, and it is complex The degree is lower, which greatly reduces the cost.
  • the scanning signal can be realized by the GOA circuit, and it only needs to be turned on once in each frame time, so that as much time as possible is used for light emission control. Compared with the prior art, the performance of the active ⁇ LED display circuit is further improved, and a high grayscale display is further realized.
  • the circuit of the present application consists of three capacitors (C1, C2 and C3) and ten TFTs, wherein T10 is a driving TFT to control the luminous brightness of the ⁇ LED.
  • the control signals are reset signal RESET, row scanning signal SN, lighting control signal EM and comparison reference signal SWEEP, wherein EM and SWEEP signals are global signals, RESET and SN are reusable signals, that is, the current stage SN signal can act as the next stage. RESET signal.
  • the high level of the control signal is VGH, and the low level is VGL.
  • the power supply VDD VGH>VDD>VGL
  • the reference voltage REF VGH>REF>PWMD
  • the data signals PAMD and PWMD are required. The way of working can be divided into three stages:
  • RESET is at a high level to turn on T1; SN is at a low level to turn off T2, T3 and T9; EM is at a low level to turn off T4, T5 and T8, and turn off the ⁇ LED at the same time to prevent flickering; the SWEEP signal remains at a high level, the circuit
  • the status is shown in Figure 5.
  • the voltage at point A (VA) is set to REF.
  • RESET changes to low level to close T1; SN changes to high level to open T2, T3 and T9, the voltage at point D (VD) is set to PWMD, T2 and T6 form a diode connection mode, VA discharges until T6 is closed, and finally VA and the voltage at point B (VB) is stabilized at PWMD-V th6 ; T9 is turned on and the voltage at point C (VC) is set to PAMD.
  • EM maintains a low level to turn off T4, T5 and T8, and turns off the ⁇ LED at the same time to prevent flickering; the SWEEP signal remains at a high level, as shown in Figure 6.
  • the compensation process at this stage can ensure that the drift of the threshold voltage of T6 will not affect the switching state of T6 in the next comparative light-emitting stage.
  • the source voltage of T6 is VGL (VGL ⁇ PWMD+V th ), VA is greater than VGL at the beginning of the comparative light-emitting phase, T6 is turned on, and the size of T6 is greater than T5, so that VB is low, T7 is kept off, and the ⁇ LED current is kept at the above level .
  • VA is gradually smaller than VGL+V th , that is, PWMD- ⁇ SWEEP ⁇ VGL
  • B gradually rises to REF, thereby turning on T7, transferring VDD to point C, turning off T10, and the ⁇ LED stops emitting light.
  • the above comparison node has nothing to do with the T6 threshold voltage, only the PWMD size and the SWEEP slope.
  • the turn-on time of T6 can be controlled, and the turn-on time of T6 can control the level of point B, so as to control the start time of T7, and then control the turn-on time of T10.
  • the control of the light-emitting time of the ⁇ LED realizes the purpose of PWM controlling the light-emitting brightness. For example, the larger the PWMD, the longer the on time of T6, the longer the time that the B point remains low, the shorter the on time of T7, the longer the on time of T10, and the longer the light-emitting time. Therefore, the pixel circuit successfully combines PAM and PWM to realize the expansion of gray scales.
  • One end of C2 is connected to B, the other end can be connected to VDD, or to any other DC power supply; one end of C3 is connected to C, the other end can be connected to VDD, or to any other DC power supply.
  • T8 Due to the influence of parasitic effects, the rising edge of the gate signal EM of T5 may affect the voltage rise of point B and cause T7 to be turned on by mistake. In order to avoid the influence of point C, the above circuit uses T8 for protection. If the parasitic capacitance of the transistor is small and the panel parasitic effect is not obvious, T8 can be removed, and the source of T7 can be directly connected to VDD.
  • the rising edge of the gate signal EM of T5 may affect the voltage of point B due to the influence of parasitic effects, thereby causing the false turn-on of T7, so T8 is required for protection.
  • the gate of T8 can use the EM signal directly, or use the EM2 signal with a longer low-level pulse width than the EM signal, completely avoiding the influence of the voltage change at point B under the influence of the rising edge of EM on point C, and achieving better protective effect.
  • the relationship between the two signals is shown in Figure 8.
  • PAMD and PWMD can be input simultaneously through two data signal lines according to the above working process, or can be input successively with one data signal line (DATA). Input the corresponding circuit diagram and timing diagram successively as shown in Figure 9.
  • the ⁇ LED can also adopt the structure in which the anode is connected to T10, and the cathode is controlled by VSS to prevent the occurrence of flicker.
  • the circuit structure and timing diagram are shown in Figure 10.
  • the RESET signal that controls initialization can also be used as a global signal to control all pixels to be initialized at the same time and then perform data input compensation line by line.
  • the present application is also applicable to other n-type TFT devices.
  • the N-type TFT transistor due to the manufacturing process of the N-type TFT transistor, no crystallization step and thus no manufacturing equipment for the high-cost crystallization process is required, resulting in a low cost of the N-type TFT transistor, and the N-type TFT transistor is suitable for small screens, for example, tablet computers and displays, etc.
  • the present application can achieve at least one of the following beneficial effects:
  • the combination of pulse amplitude modulation PAM (Pulse amplitude modulation) and PWM drive mode in the pixel can be realized, which is not only compatible with the traditional drive mode, but also satisfies the digital control of high gray scale.
  • PAM Pulse amplitude modulation
  • the modulated light-emitting time of the present application can reach more than 75% of the entire refresh time, and 12bit grayscale can be achieved.
  • connection mode of T3, T2 and T6 constitutes a diode connection structure.
  • the T6 source voltage is fixed, and the gate is discharged through T6, the threshold voltage of T6 can be detected, and the threshold voltage of T6 can be compared between the light-emitting stage and the T6 threshold voltage. It doesn't matter. It avoids the effect of positive bias stress (PBS, Positive bias stress) caused by the positive bias voltage on the T6 threshold voltage to cause the comparison result to drift.
  • PBS Positive bias stress
  • the on-time of T6 can be controlled, and the on-time of T6 can control the level of point B, thereby controlling the starting time of T7, and then the on-time of T10, and finally realizing the light-emitting time of ⁇ LED control, realize PWM control of luminous brightness.
  • the process of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium.
  • the computer-readable storage medium is a magnetic disk, an optical disk, a read-only storage memory, or a random-access storage memory, or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Led Devices (AREA)

Abstract

一种μLED单元电路、其发光控制方法和像素电路，属于半导体技术领域，μLED单元电路包括：PWM信号生成电路、发光控制电路和μLED，PWM信号生成电路基于发光控制信号和比较参考信号生成具有不同脉冲宽度的PWM信号，比较参考信号为线性降低的斜坡信号；发光控制电路包括驱动晶体管，基于不同脉冲宽度的PWM信号控制驱动晶体管的导通时间以提供驱动电流；以及μLED基于驱动电流控制μLED的发光时间。该μLED单元电路、其发光控制方法和像素电路实现了像素内PAM和PWM驱动模式的结合，既兼容了传统驱动模式又满足高灰阶的数字调控。

Description

一种μLED单元电路、其发光控制方法和像素装置 技术领域
本申请涉及半导体技术领域，尤其涉及一种μLED单元电路、其发光控制方法和像素装置。
背景技术
近年来，由于μLED具有比AMOLED(Active-matrix organic light emitting diode，有源矩阵有机发光二极管)更小的器件尺寸，更快的反应速度，更高的发光效率，更强的稳定性以及更长的使用寿命等优势，基于μLED的显示应用领域得到了迅速发展，吸引着越来越多的目光。在这一领域中，以非晶铟镓锌氧化物(a-IGZO)为代表的氧化物薄膜晶体管(TFT，Thin Film Transistor)材料由于其透明、可弯曲、制作温度低，成本低等优势已经成为大尺寸有源μLED显示的重要材料。目前针对有源μLED显示技术，有两个最关键的问题亟待解决：
1.μLED的大量转移技术。为了降低成本，将μLED的优势发挥到最大，μLED的大量转移技术十分关键。
2.μLED的灰阶展开设计方案。由于μLED的IV特性曲线十分陡峭，即μLED从低灰阶电流到高灰阶电流对应的两极电压变化量极小，如图1所示，导致灰阶很难通过传统的模拟电压驱动(PAM)的方式展开。
在基于n型a-IGZO薄膜晶体管的μLED显示电路中，现有技术大多采用传统2T1C像素电路配合微型硅基CMOS驱动实现高灰阶显示(参考图2)。除此以外，数字脉宽调制(PWM)驱动方式也得到了广泛关注。PWM驱动即通过控制μLED发光的时间来控制人眼感应到的亮度。相同驱动电流相同刷新频率的条件下，μLED发光时间占总刷新时间的比例越大，人眼感应到的亮度就越高。通过这种方法，可以实现对灰阶亮度的精确控制(参考图3)。
上述现有技术存在如下技术缺陷：基于微型硅基CMOS驱动的有源μLED显示技术成本较高，沿用PAM驱动的方式意味着驱动电路需要极快速的时钟信号去满足极高的电压分辨率。同时，采用CMOS驱动对面板的柔性、透明度、厚度都产生了不利影响。采用PWM方案，可以利用面上驱动电路(GOA)产生驱动控制信号。PWM方案将每帧显示时间分成等比例的n个子帧，每个像素单元需要在每个子帧时间内开启一次，每次IC输入的数据电压决定该子帧对应的时间μLED是否发光。该方法可以实现较高的灰阶，但是GOA电路驱动速度有限，当分辨率较高时，多次开启导致较长的 一部分时间无法用于发光，从而限制了灰阶数的提升。
发明内容
鉴于上述的分析，本申请实施例旨在提供一种μLED单元电路、其发光控制方法和像素装置，用以解决现有GOA电路驱动速度有限，当分辨率较高时，多次开启导致较长的一部分时间无法用于发光，从而限制了灰阶数的提升问题。
一方面，本申请实施例提供了一种μLED单元电路包括：PWM信号生成电路、发光控制电路和μLED，其中，所述PWM信号生成电路，用于接收发光控制信号和比较参考信号并基于所述发光控制信号和所述比较参考信号生成具有不同脉冲宽度的PWM信号，其中，所述比较参考信号为线性降低的斜坡信号；所述发光控制电路，包括驱动晶体管，用于从所述PWM信号生成电路接收所述不同脉冲宽度的PWM信号并基于所述不同脉冲宽度的PWM信号控制所述驱动晶体管的导通时间以提供驱动电流；以及所述μLED，用于从所述发光控制电路接收所述驱动电流并基于所述驱动电流控制所述μLED的发光时间。。
上述技术方案的有益效果如下：根据本申请实施例所提供的μLED单元电路中，通过本申请的电路结构和工作模式，可以实现像素内PAM和PWM驱动模式的结合，既兼容了传统驱动模式，又满足高灰阶的数字调控。对于60Hz 2k分辨率的显示应用，本申请可调制的发光时间可达到整个刷新时间的75％以上，可实现12bit灰阶。
基于上述电路的进一步改进，所述PWM信号生成电路包括复位电路、补偿电路和反相器，其中，所述复位电路，用于接收复位信号，并对所述μLED单元电路进行初始化；所述反相器，与所述复位电路的输出端连接，并用于基于所述反相器的输入端电压与电源输入端电压进行比较，控制所述反相器中的晶体管的导通，以生成具有不同脉冲宽度的PWM信号；以及所述补偿电路，用于补偿所述反相器的输入端电压和电源输入端电压。
基于上述电路的进一步改进，所述复位电路包括第一晶体管，其中，所述第一晶体管的栅极接收所述复位信号，所述第一晶体管的源极与参考电源电压连接，以及所述第一晶体管的漏极与所述反相器的输入端连接。
基于上述电路的进一步改进，所述反相器包括连接为反相器的第四晶体管、第五晶体管和第六晶体管，所述μLED单元电路还包括第一电容器，其中，所述第四晶体管的栅极接收所述发光控制信号，所述第四晶体管的源极与第一电源电压连接，以及所述第四晶体管的漏极为所述电源输入端并与所述第六晶体管的源极连接；所述第六晶体管的栅极为所述反相器的输入端并经由所述第一电容器接收所述比较参考信号，所述第六晶体管的漏极为所述反相器的输出端并与所述第五晶体管的源极连接；以及所述第五晶体管的栅极接收所述发光控制信号，所述第五晶体管的漏极与所述参考电 源电压连接，其中，所述第一电源电压小于所述参考电源电压。
基于上述电路的进一步改进，所述补偿电路包括第二晶体管和第三晶体管，其中，所述第二晶体管的栅极用于接收行扫描信号，所述第二晶体管的源极与所述第六晶体管的栅极连接，以及所述第二晶体管的漏极与所述反相器的输出端连接；以及所述第三晶体管的栅极用于接收所述行扫描信号，所述第三晶体管的源极与所述第四晶体管的漏极和所述第六晶体管的源极连接，以及所述第三晶体管的漏极接收PWMD信号，其中，所述PWMD信号为根据μLED的发光亮度而改变的电压值。
基于上述电路的进一步改进，所述发光控制电路包括边沿改善电路和驱动电路，其中，所述边沿校正电路，用于接收所述不同脉冲宽度的PWM信号和所述发光控制信号并校正所述不同脉冲宽度的PWM信号的边沿陡峭度；以及所述驱动电路，用于基于校正的不同脉冲宽度的PWM信号控制驱动晶体管的导通时间以提供所述驱动电流。
基于上述电路的进一步改进，所述边沿校正电路包括第七晶体管、第八晶体管和第二电容器，其中，所述第七晶体管的栅极与所述反相器的输出端连接并经由所述第二电容器接收第二电源电压，所述第七晶体管的源极与所述第八晶体管的漏极连接，以及所述第七晶体管的漏极与所述第九晶体管的漏极连接；以及所述第八晶体管的栅极接收所述发光控制信号，所述第八晶体管的源极接收所述第二电源电压。
基于上述电路的进一步改进，所述驱动电路包括所述第九晶体管、第十晶体管和第三电容器，所述第十晶体管为所述驱动晶体管，其中，所述第九晶体管的栅极接收所述行扫描信号，所述第九晶体管的源极接收PAMD信号，所述PAMD信号为发光亮度最高时的电压值；所述第十晶体管的源极与所述第二电源电压连接，所述第十晶体管的栅极与所述第七晶体管的漏极和所述第九晶体管的漏极连接；以及所述第三电容器的一端连接所述第二电源电压，以及所述第三电容器的另一端与所述第七晶体管的漏极和所述第九晶体管的漏极连接，其中，所述第二电源电压大于所述第一电源电压并且大于所述参考电源电压。
基于上述电路的进一步改进，所述μLED的阴极与所述驱动晶体管的漏极连接以及所述μLED的阳极用于接收所述发光控制信号；或者所述μLED的阳极与所述驱动晶体管的漏极连接以及所述μLED的阴极用于接收第三电源电压。
基于上述电路的进一步改进，所述第一晶体管至所述第十晶体管为N型TFT晶体管。
另一方面，本申请实施例提供了一种像素装置，包括m×n个根据以上实施例所述的μLED单元电路。
又一方面，本申请实施例提供了一种μLED发光控制方法，其特征在于，包括比较发光步骤，其中，所述比较发光步骤包括：基于发光控制信号EM1和比较参考信号SWEEP生成具有不同脉冲宽度的PWM信号，其中，所述比较参考信号SWEEP为线性降 低的斜坡信号；接收所述不同脉冲宽度的PWM信号并基于所述不同脉冲宽度的PWM信号控制驱动晶体管的导通时间以提供驱动电流；以及从所述发光控制电路接收所述驱动电流并基于所述驱动电流控制所述μLED的发光时间。
基于上述方法的进一步改进，所述驱动电流为：
Figure PCTCN2021087633-appb-000001
其中，所述μ、C ox和
Figure PCTCN2021087633-appb-000002
分别表示所述驱动晶体管的迁移率、单位面积栅介质电容和沟道宽长比，所述PAMD为发光亮度最高时的电压值，V LED为所述μLED的电压，以及V th10为所述驱动晶体管的阈值电压。
基于上述方法的进一步改进，在所述比较发光步骤之前，还包括初始化步骤和行扫描步骤，所述初始化步骤，基于复位信号RESET对像素装置的μLED单元电路进行初始化；以及所述行扫描步骤，在所述初始化步骤之后，基于行扫描信号SN对所述像素装置的μLED单元电路进行逐行扫描。
基于上述方法的进一步改进，所述初始化步骤包括：将所述复位信号RESET提供给第一晶体管T1的栅极，所述第一晶体管T1导通，使得所述第一晶体管T1的源极与参考电源电压REF连接以将所述第一晶体管T1的漏极置位到参考电源电压REF，其中，所述复位信号为低电平。
基于上述方法的进一步改进，所述行扫描步骤包括：将所述行扫描信号SN提供给第二晶体管T2和第三晶体管T3的栅极，所述第二晶体管T2、所述第三晶体管T3、所述第六晶体管T6导通，使得所述第六晶体管T6的源极经由导通所述第三晶体管T3与PWMD信号连接并置位为PWMD，以及所述第六晶体管T6的漏极经由所述第二晶体管T2与所述第六晶体管T6的栅极连接，以使所述第六晶体管T6的漏极电压与所述第六晶体管T6的栅极电压为PWMD-|V th6|，其中，所述PWMD信号为根据μLED的发光亮度而改变的电压值；将行扫描信号SN提供给第九晶体管T9的栅极，使得所述第九晶体管T9导通，以经由所述第九晶体管T9将驱动晶体管的栅极置位为PAMD，其中，所述PAMD为所述μLED的发光亮度最高时的电压值，所述行扫描信号SN为低电平。
基于上述方法的进一步改进，所述比较发光步骤进一步包括：将所述发光控制信号EM1提供给第四晶体管T4和第五晶体管T5的栅极并将比较参考信号SWEEP经由电容器提供给所述第六晶体管T6的栅极，将所述第四晶体管T4、所述第五晶体管T5和所述第六晶体管T6导通并连接为反相器，使得第六晶体管T6的源极为所述反相器的电源输入端并且经由所述第四晶体管T4与第一电源电压VGL连接，使得所述反相器的电源输入端的电压为第一电源电压VGL；所述第六晶体管T6的栅极为所述反相器的输入端并且使得所述反相器的电源输入端的电压为PWMD+V th6-ΔSWEEP；所述第六 晶体管T6的漏极为所述反相器的输出端并经由所述第五晶体管T5与参考电源电压REF连接，使得所述反相器的输出端的电压为高电平而第七晶体管T7保持截止，其中，所述第六晶体管T6的尺寸大于所述第五晶体管T5的尺寸，以及所述发光控制信号EM1为脉冲信号。
基于上述方法的进一步改进，所述比较发光步骤进一步包括：驱动晶体管T10导通，使得所述驱动晶体管T10的栅极电压保持所述PAMD信号，所述驱动晶体管T10的源极与第一电源电压VDD连接，以提供所述驱动电流，使得所述μLED开始发光。
基于上述方法的进一步改进，所述比较发光步骤进一步包括：当所述比较参考信号SWEEP线性提高使得所述反相器的电源输入端的电压PWMD+V th6-ΔSWEEP大于VGH+V th6时，所述第六晶体管T6截止以将所述反相器的输出端的电压上升至REF，使得所述第七晶体管T7导通以将所述第一电源电压VDD传输至所述驱动晶体管T10的栅极或者将所述驱动晶体管T10的栅极置位为所述第一电源电压VDD，所述驱动晶体管T10截止使得所述μLED停止发光。
基于上述方法的进一步改进，将所述发光控制信号EM2提供给第八晶体管T8，所述第八晶体管T8和驱动晶体管T10导通，使得所述驱动晶体管T10的栅极电压保持所述PAMD信号，所述驱动晶体管T10的源极与第一电源电压VDD连接，以提供所述驱动电流，使得所述μLED开始发光，其中，所述发光控制信号EM2和所述发光控制信号EM1为脉冲信号，以及所述发光控制信号EM2的上升沿滞后于所述发光控制信号EM1的上升沿。
与现有技术相比，本申请至少可实现如下有益效果之一：
1、通过本申请的电路结构和工作模式，可以实现像素内脉冲幅度调制PAM(Pulse amplitude modulation)和PWM驱动模式的结合，既兼容了传统驱动模式，又满足高灰阶的数字调控。对于60Hz 2k分辨率的显示应用，本申请可调制的发光时间可达到整个刷新时间的75％以上，可实现12bit灰阶。
2、T3、T2和T6的连接方式构成了二极管连接结构，在Vth补偿阶段固定T6源极电压，通过T6对栅极进行放电，可以检测到T6的阈值电压，保证比较发光阶段与T6阈值电压无关。避免了正偏压对T6阈值电压造成的正偏置压力(PBS，Positive bias stress)影响使比较结果出现漂移。
3、在比较发光阶段，将T4、T5和T6连接为反相器，通过反相器的输入端(A点)和电源输入端(D点)之间的电压比较，能够在反相器的输出端(B点)处生成不同脉冲宽度的PWM信号。
4、通过控制PWMD模拟电压值的大小可以控制T6开启的时间，T6开启时间可以控制B点的电平高低，从而控制T7的开始时间，进而控制T10的开启时间，最终实现对μLED的发光时间的控制，实现PWM控制发光亮度。
本申请中，上述各技术方案之间还可以相互组合，以实现更多的优选组合方案。 本申请的其他特征和优点将在随后的说明书中阐述，并且，部分优点可从说明书中变得显而易见，或者通过实施本申请而了解。本申请的目的和其他优点可通过说明书以及附图中所特别指出的内容中来实现和获得。
附图说明
附图仅用于示出具体实施例的目的，而并不认为是对本申请的限制，在整个附图中，相同的参考符号表示相同的部件。
图1为传统模拟电压驱动电路获得的μLED电流电压转移曲线。
图2为现有微型硅基CMOS的有源μLED显示。
图3为现有的μLED高灰阶显示的PWM驱动方案。
图4为根据本申请实施例的μLED单元电路的电路结构图及其时序图。
图5为根据本申请实施例的μLED单元电路的初始化阶段的电路结构图。
图6为根据本申请实施例的μLED单元电路的行扫描阶段(又称数据输入补偿阶段)的电路结构图。
图7为根据本申请实施例的μLED单元电路的比较发光阶段的电路结构图。
图8为根据本申请实施例的μLED单元电路的不同发光控制信号的时序图。
图9为根据本申请实施例的μLED单元电路的PAM与PWM分步输入电路图及其时序图。
图10为根据本申请可选实施例的μLED单元电路的电路结构图及其时序图。
具体实施方式
下面结合附图来具体描述本申请的优选实施例，其中，附图构成本申请一部分，并与本申请的实施例一起用于阐释本申请的原理，并非用于限定本申请的范围。
本申请的一个具体实施例，公开了一种μLED单元电路，包括PWM信号生成电路、发光控制电路和μLED。下文中，将参考图4，对μLED单元电路进行详细描述。
参考图4，PWM信号生成电路用于接收发光控制信号EM和比较参考信号SWEEP并基于发光控制信号EM和比较参考信号SWEEP生成具有不同脉冲宽度的PWM信号，其中，比较参考信号SWEEP为线性降低的斜坡信号。PWM信号生成电路包括复位电路、补偿电路和反相器，其中，参考图4和图5，复位电路，用于接收复位信号RESET，并对μLED单元电路进行初始化；参考图4和图7，反相器，与复位电路的输出端连接，并用于基于反相器的输入端电压(即，A点)与电源输入端电压(即，D点)进行比较，控制反相器中的晶体管的导通，以生成具有不同脉冲宽度的PWM信号；以及参考图4和图6，补偿电路，用于补偿反相器的输入端电压(即，A点)和电源输入 端电压(即，D点)。在实施例中，复位电路包括第一晶体管T1，其中，第一晶体管T1的栅极接收复位信号RESET，第一晶体管T1的源极与参考电源电压REF连接，以及第一晶体管T1的漏极(即，A点)与反相器的输入端连接。反相器包括连接为反相器的第四晶体管T4、第五晶体管T5和第六晶体管T6，μLED单元电路还包括第一电容器C1，其中，第四晶体管T4的栅极接收发光控制信号EM，第四晶体管T4的源极与第一电源电压VGL连接，以及第四晶体管T4的漏极为电源输入端(即，D点)并与第六晶体管T6的源极连接；第六晶体管T6的栅极为反相器的输入端(即，A点)并经由第一电容器C1接收比较参考信号SWEEP，第六晶体管T6的漏极为反相器的输出端(即，B点)并与第五晶体管T5的源极连接；以及第五晶体管T5的栅极接收发光控制信号EM，第五晶体管T5的漏极与参考电源电压REF连接，其中，第一电源电压VGL小于参考电源电压REF。补偿电路包括第二晶体管T2和第三晶体管T3，其中，第二晶体管T2的栅极用于接收行扫描信号SN，第二晶体管T2的源极与第六晶体管T6的栅极连接，以及第二晶体管T2的漏极与反相器的输出端(即，B点)连接；以及第三晶体管T3的栅极用于接收行扫描信号SN，第三晶体管T3的源极与第四晶体管T4的漏极和第六晶体管T6的源极连接，以及第三晶体管T3的漏极接收PWMD信号，其中，PWMD信号为根据μLED的发光亮度而改变的电压值。例如，第一晶体管T1至第六晶体管T6为N型TFT晶体管。
参考图4，发光控制电路包括驱动晶体管，即，第十晶体管T10，用于从PWM信号生成电路接收不同脉冲宽度的PWM信号并基于不同脉冲宽度的PWM信号控制驱动晶体管的导通时间以提供驱动电流。发光控制电路包括边沿改善电路和驱动电路，其中，边沿校正电路，用于接收不同脉冲宽度的PWM信号和发光控制信号EM并校正不同脉冲宽度的PWM信号的边沿陡峭度(参考图4的时序图，C点电压)以改善或提高PWM信号的边沿陡峭度，进而能够准确地控制驱动晶体管T10，例如导通或截止；以及驱动电路，用于基于校正的不同脉冲宽度的PWM信号控制驱动晶体管的导通时间以提供驱动电流。边沿校正电路包括第七晶体管T7、第八晶体管T8和第二电容器C2，其中，第七晶体管T7的栅极与反相器的输出端(即，B点)连接并经由第二电容器C2接收第二电源电压VDD，第七晶体管T7的源极与第八晶体管T8的漏极连接，以及第七晶体管T7的漏极与第九晶体管T9的漏极(即，C点)连接；以及第八晶体管T8的栅极接收发光控制信号EM，第八晶体管T8的源极接收第二电源电压VDD。驱动电路包括第九晶体管T9、第十晶体管T10和第三电容器C3，第十晶体管T10为驱动晶体管，其中，第九晶体管T9的栅极接收行扫描信号SN，第九晶体管T9的漏极(即，C点)与第七晶体管T7的漏极连接，第九晶体管T9的源极接收PAMD信号，PAMD信号为发光亮度最高时的电压值；第十晶体管T10的源极与第二电源电压VDD连接，第十晶体管T10的栅极与第七晶体管T7的漏极和第九晶体管T9的漏极(即，C点)连接；以及第三电容器C3的一端连接第二电源电压VDD，以及第三电容器C3的另一端与第七 晶体管T7的漏极和第九晶体管T9的漏极连接，其中，第二电源电压VDD大于第一电源电压VGL并且大于参考电源电压REF。例如，第七晶体管T7至第十晶体管T10为N型TFT晶体管。
参考图4，μLED用于从发光控制电路接收驱动电流并基于驱动电流控制μLED的发光时间。在实施例中，参考图4，μLED的阴极与驱动晶体管的漏极连接以及μLED的阳极用于接收发光控制信号EM。在可选实施例中，参考图10，μLED的阳极与驱动晶体管T10的漏极连接以及μLED的阴极用于接收第三电源电压VSS。例如，驱动晶体管为N型TFT晶体管。
与现有技术相比，本实施例提供的μLED单元电路中，通过本申请的电路结构和工作模式，可以实现像素内脉冲幅度调制PAM(Pulse amplitude modulation)和PWM驱动模式的结合，既兼容了传统驱动模式，又满足高灰阶的数字调控。对于60Hz 2k分辨率的显示应用，本申请可调制的发光时间可达到整个刷新时间的75％以上，可实现12bit灰阶。
本申请的另一个具体实施例，公开了一种像素装置，包括m×n个根据以上实施例描述的μLED单元电路。
本申请的又一个具体实施例，公开了一种μLED发光控制方法包括初始化步骤、行扫描步骤和比较发光步骤。下文中，将图5至图7对μLED发光控制方法进行详细描述。
参考图5，初始化步骤，基于复位信号RESET对像素装置的μLED单元电路进行初始化。在实施例中，初始化步骤包括：将复位信号RESET提供给第一晶体管T1的栅极，第一晶体管T1导通，使得第一晶体管T1的源极与参考电源电压REF连接以将第一晶体管T1的漏极置位到参考电源电压REF，其中，复位信号RESET为低电平。
参考图6，行扫描步骤，在初始化步骤之后，基于行扫描信号SN对像素装置的μLED单元电路进行逐行扫描。在实施例中，行扫描步骤包括：将行扫描信号SN提供给第二晶体管T2和第三晶体管T3的栅极，第二晶体管T2、第三晶体管T3、第六晶体管T6导通，使得第六晶体管T6的源极经由导通第三晶体管T3与PWMD信号连接并置位为PWMD，以及第六晶体管T6的漏极经由第二晶体管T2与第六晶体管T6的栅极连接，以使第六晶体管T6的漏极电压与第六晶体管T6的栅极电压为PWMD-|V th6|，其中，PWMD信号为根据μLED的发光亮度而改变的电压值；将行扫描信号SN提供给第九晶体管T9的栅极，使得第九晶体管T9导通，以经由第九晶体管T9将驱动晶体管的栅极置位为PAMD，其中，PAMD为μLED的发光亮度最高时的电压值，行扫描信号SN为低电平。
参考图7，比较发光步骤包括：基于发光控制信号EM1和比较参考信号SWEEP生成具有不同脉冲宽度的PWM信号，其中，比较参考信号SWEEP为线性降低的斜坡信号； 接收不同脉冲宽度的PWM信号并基于不同脉冲宽度的PWM信号控制驱动晶体管的导通时间以提供驱动电流；以及从发光控制电路接收驱动电流并基于驱动电流控制μLED的发光时间。驱动电流为：
Figure PCTCN2021087633-appb-000003
其中，μ、C ox和
Figure PCTCN2021087633-appb-000004
分别表示驱动晶体管的迁移率、单位面积栅介质电容和沟道宽长比，PAMD为发光亮度最高时的电压值，V LED为μLED的电压，以及V th10为驱动晶体管T10的阈值电压。
参考图8，比较发光步骤进一步包括：将发光控制信号EM1提供给第四晶体管T4和第五晶体管T5的栅极并将比较参考信号SWEEP经由电容器提供给第六晶体管T6的栅极，将第四晶体管T4、第五晶体管T5和第六晶体管T6导通并连接为反相器，使得第六晶体管T6的源极为反相器的电源输入端(即，A点)并且经由第四晶体管T4与第一电源电压VGL连接，使得反相器的电源输入端的电压为第一电源电压VGL；第六晶体管T6的栅极为反相器的输入端并且使得反相器的电源输入端(即，D点)的电压为PWMD+V th6-ΔSWEEP；第六晶体管T6的漏极为反相器的输出端(即，B点)并经由第五晶体管T5与参考电源电压REF连接，使得反相器的输出端的电压为高电平而第七晶体管T7保持截止，其中，第六晶体管T6的尺寸大于第五晶体管T5的尺寸，以及发光控制信号EM1为脉冲信号。比较发光步骤进一步包括：驱动晶体管T10导通，使得驱动晶体管T10的栅极电压保持PAMD信号，驱动晶体管T10的源极与第一电源电压VDD连接，以提供驱动电流，使得μLED开始发光。比较发光步骤进一步包括：当比较参考信号SWEEP线性提高使得反相器的电源输入端的电压PWMD+V th6-ΔSWEEP大于VGH+V th6时，第六晶体管T6截止以将反相器的输出端的电压上升至REF，使得第七晶体管T7导通以将第一电源电压VDD传输至驱动晶体管T10的栅极或者将驱动晶体管T10的栅极置位为第一电源电压VDD，驱动晶体管T10截止使得μLED停止发光。
参考图7和图8，将发光控制信号EM2提供给第八晶体管T8，第八晶体管T8和驱动晶体管T10导通，使得驱动晶体管T10的栅极电压保持PAMD信号，驱动晶体管T10的源极与第一电源电压VDD连接，以提供驱动电流，使得μLED开始发光，其中，发光控制信号EM2和发光控制信号EM1为脉冲信号，以及发光控制信号EM2的上升沿滞后于发光控制信号EM1的上升沿。
参考图4，像素装置包括多行μLED单元电路。参考图4和图5，时序图中的初始化步骤(1)同时对多行μLED单元电路进行初始化。参考图4和图6，时序图中的行扫描步骤(2)包括对像素装置进行逐行扫描，例如，行扫描信号SN提供给第一行以对第一行进行扫描，行扫描信号SN+1提供给第二行以对第二行进行行扫描等。 行扫描步骤包括进行逐行扫描(2)，例如，行扫描信号。参考图4和图7，时序图中的比较发光步骤(3)控制像素装置的进行发光。
图9的初始化步骤(1)与图4和图5中的初始化步骤(1)完全相同。图9中的比较发光步骤(4)与图4和图7中的比较发光步骤(3)完全相同。图9的行扫描步骤对于每行μLED单元电路，包括图9中的PWAD输入阶段(2)以将D点置位为PWAD和PAMD输入阶段(3)以将C点置位为PAMD。此外，SN相对SNN的时间延迟与扫描行数相关，具体时间为SN扫描脉宽*扫描行数。SN+1相对于SNN+1的时间延迟与SN相对SNN的时间延迟相同。相比于图4中的时序图，图9中的时序图通过额外的行扫描信号SNN、SNN+1…将C点置位为PAMD。例如，将SN和SNN用于第一行μLED单元电路的行扫描。将SN+1和SNN+1用于第一行μLED单元电路的行扫描。
参考图10，在可选实施例中，μLED的阳极与驱动晶体管T10的漏极连接以及μLED的阴极用于接收第三电源电压VSS。参考图10，发光控制信号EM是第三电源电压VSS的反相信号。
下文中，将参考图4至图10，以具体实例的方式对μLED发光控制方法进行详细描述。
本申请提供了一种适用于高灰阶μLED显示的新型像素电路，该电路将PAM与PWM驱动结合，在像素内部进行模拟电压到数字脉宽的转换，IC兼容传统模拟电压驱动电路设计，复杂度较低，大大降低了成本。扫描信号可通过GOA电路实现，在每帧时间内仅需开启一次，将时间尽可能多得用于发光控制。与现有技术相比，进一步提高了有源μLED显示电路的性能，近一步实现了高灰阶显示。
参考图4，本申请电路由三个电容(C1，C2和C3)和十个TFT组成，其中T10为驱动TFT，控制μLED的发光亮度。控制信号为复位信号RESET、行扫描信号SN、发光控制信号EM和比较参考信号SWEEP，其中EM和SWEEP信号为全局信号，RESET和SN为可复用信号，即当前级SN信号可充当下一级RESET信号。控制信号高电平为VGH，低电平为VGL。另外需要电源VDD(VGH>VDD>VGL)，参考电压REF(VGH>REF>PWMD)，数据信号PAMD和PWMD。工作方式可以分为三个阶段：
初始化阶段
RESET处于高电平打开T1；SN处于低电平关闭T2，T3和T9；EM处于低电平关闭T4，T5和T8，同时关断μLED，防止闪烁；SWEEP信号保持高电平不变，电路状态如图5。A点电压(VA)置位到REF。
数据输入补偿阶段
RESET变为低电平关闭T1；SN变为高电平打开T2，T3和T9，D点电压(VD)置位到PWMD，T2和T6组成了二极管连接方式，VA放电至T6关闭，最终VA和B点电压(VB)稳定在PWMD-V th6；T9开启，C点电压(VC)被置为PAMD。EM维持低电平关闭T4，T5和T8，同时关断μLED，防止闪烁；SWEEP信号保持高电平不变，如图6。 本阶段补偿过程可保证在接下来的比较发光阶段，T6阈值电压的漂移不会影响T6的开关状态。
比较发光阶段
RESET变为低电平关闭T1；SN处于低电平关闭T2，T3和T9；EM变为高电平打开T4，T5和T8，同时EM将μLED阳极置高，如图7。由于存储电容C3的作用，VC一直保持PAMD，PAMD的大小控制T10的驱动电流，即控制μLED的亮度。根据晶体管饱和电流公式：
Figure PCTCN2021087633-appb-000005
可得到此阶段I OLED为电流大小为：
Figure PCTCN2021087633-appb-000006
其中，μ、C ox和
Figure PCTCN2021087633-appb-000007
分别表示T10的迁移率、单位面积栅介质电容和沟道宽长比。SWEEP信号开始由高至低线性变化，通过C1电容耦合效应，VA逐渐线性变小(VA＝PWMD+V th-ΔSWEEP)。T6源极电压为VGL(VGL<PWMD+V th)，在比较发光阶段刚开始时VA大于VGL，T6开启，T6尺寸大于T5，使得VB为低电平，T7保持关闭，μLED电流保持上述大小。随着SWEEP信号进一步变小，VA逐渐小于VGL+V th，即PWMD-ΔSWEEP<VGL，B逐渐上升至REF，从而打开T7，将VDD传输至C点，关闭T10，μLED停止发光。上述比较节点与T6阈值电压无关，仅与PWMD大小和SWEEP斜率相关。
通过上述工作过程可知，通过控制PWMD模拟电压值的大小可以控制T6开启的时间，T6开启时间可以控制B点的电平高低，从而控制T7的开始时间，进而控制T10的开启时间，最终实现对μLED的发光时间的控制，实现PWM控制发光亮度的目的。例如，PWMD越大，T6开启时间越长，B点保持低电平时间越长，T7开启时间越短，T10开启时间越长，发光时间越长。所以，该像素电路成功的将PAM与PWM结合，实现了灰阶的展开。
此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方法。在可选实施例中，
1、C2的一端与B相连，另一端可与VDD相连，也可与其他任意直流电源相连；C3一端与C相连，另一端可与VDD相连，也可与其他任意直流电源相连。
2、T5栅极信号EM的上升沿由于寄生效应的影响可能会影响B点电压升高从而造成T7的错误开启，为了避免C点受到影响，上述电路使用T8进行防护。如果晶体管寄生电容小，面板寄生效应不明显，可以将T8去除，直接将T7的源极与VDD相连。
3、T5栅极信号EM的上升沿由于寄生效应的影响可能会影响B点电压从而造成T7的错误开启，所以需要T8进行保护。T8的栅极可直接使用EM信号，也可以使用 比EM信号低电平脉宽更长的EM2信号，彻底避免B点在EM上升沿影响下的电压变化对C点造成影响，实现更好的保护效果。二者信号关系如图8所示。
4、PAMD与PWMD可按照上述工作过程通过两条数据信号线同时输入，也可用一条数据信号线(DATA)先后输入。先后输入对应的电路图与时序图如图9所示。
5、μLED也可采用阳极与T10相连的结构，阴极引入VSS控制，防止闪烁的出现，电路结构及时序图如图10所示。
6、控制初始化的RESET信号也可以作为全局信号，控制所有像素同时进行初始化后再逐行进行数据输入补偿。
7、本申请同样适用于其他n型TFT器件。
另外，由于N型TFT晶体管的制造过程，不需要晶化步骤进而不需要高成本的晶化工艺的制造设备，导致N型TFT晶体管成本低，N型TFT晶体管适用于小屏幕，例如，平板电脑和显示器等。
与现有技术相比，本申请至少可实现如下有益效果之一：
1、通过本申请的电路结构和工作模式，可以实现像素内脉冲幅度调制PAM(Pulse amplitude modulation)和PWM驱动模式的结合，既兼容了传统驱动模式，又满足高灰阶的数字调控。对于60Hz 2k分辨率的显示应用，本申请可调制的发光时间可达到整个刷新时间的75％以上，可实现12bit灰阶。
2、T3、T2和T6的连接方式构成了二极管连接结构，在Vth补偿阶段固定T6源极电压，通过T6对栅极进行放电，可以检测到T6的阈值电压，保证比较发光阶段与T6阈值电压无关。避免了正偏压对T6阈值电压造成的正偏置压力(PBS，Positive bias stress)影响使比较结果出现漂移。
3、在比较发光阶段，将T4、T5和T6连接为反相器，通过反相器的输入端(A点)和电源输入端(D点)之间的电压比较，能够在反相器的输出端(B点)处生成不同脉冲宽度的PWM信号。
4、通过控制PWMD模拟电压值的大小可以控制T6开启的时间，T6开启时间可以控制B点的电平高低，从而控制T7的开始时间，进而控制T10的开启时间，最终实现对μLED的发光时间的控制，实现PWM控制发光亮度。
本领域技术人员可以理解，实现上述实施例方法的全部或部分流程，可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于计算机可读存储介质中。其中，所述计算机可读存储介质为磁盘、光盘、只读存储记忆体或随机存储记忆体等。
以上所述，仅为本申请较佳的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。

Claims (20)

  1. 一种μLED单元电路，其特征在于，包括：PWM信号生成电路、发光控制电路和μLED，其中，
    所述PWM信号生成电路，用于接收发光控制信号和比较参考信号并基于所述发光控制信号和所述比较参考信号生成具有不同脉冲宽度的PWM信号，其中，所述比较参考信号为线性降低的斜坡信号；
    所述发光控制电路，包括驱动晶体管，用于从所述PWM信号生成电路接收所述不同脉冲宽度的PWM信号并基于所述不同脉冲宽度的PWM信号控制所述驱动晶体管的导通时间以提供驱动电流；以及
    所述μLED，用于从所述发光控制电路接收所述驱动电流并基于所述驱动电流控制所述μLED的发光时间。
  2. 根据权利要求1所述的μLED单元电路，其特征在于，所述PWM信号生成电路包括复位电路、补偿电路和反相器，其中，
    所述复位电路，用于接收复位信号，并对所述μLED单元电路进行初始化；
    所述反相器，与所述复位电路的输出端连接，并用于基于所述反相器的输入端电压与电源输入端电压进行比较，控制所述反相器中的晶体管的导通，以生成具有不同脉冲宽度的PWM信号；以及
    所述补偿电路，用于补偿所述反相器的输入端电压和电源输入端电压。
  3. 根据权利要求2所述的μLED单元电路，其特征在于，所述复位电路包括第一晶体管，其中，
    所述第一晶体管的栅极接收所述复位信号，所述第一晶体管的源极与参考电源电压连接，以及所述第一晶体管的漏极与所述反相器的输入端连接。
  4. 根据权利要求2所述的μLED单元电路，其特征在于，所述反相器包括连接为反相器的第四晶体管、第五晶体管和第六晶体管，所述μLED单元电路还包括第一电容器，其中，
    所述第四晶体管的栅极接收所述发光控制信号，所述第四晶体管的源极与第一电源电压连接，以及所述第四晶体管的漏极为所述电源输入端并与所述第六晶体管的源极连接；
    所述第六晶体管的栅极为所述反相器的输入端并经由所述第一电容器接收所述比较参考信号，所述第六晶体管的漏极为所述反相器的输出端并与所述第五晶体管的源极连接；以及
    所述第五晶体管的栅极接收所述发光控制信号，所述第五晶体管的漏极与所述参考电源电压连接，其中，所述第一电源电压小于所述参考电源电压。
  5. 根据权利要求2所述的μLED单元电路，其特征在于，所述补偿电路包括第二晶体管和第三晶体管，其中，
    所述第二晶体管的栅极用于接收行扫描信号SN，所述第二晶体管的源极与所述第六晶体管的栅极连接，以及所述第二晶体管的漏极与所述反相器的输出端连接；以及
    所述第三晶体管的栅极用于接收所述行扫描信号SN，所述第三晶体管的源极与所述第四晶体管的漏极和所述第六晶体管的源极连接，以及所述第三晶体管的漏极接收PWMD信号，其中，所述PWMD信号为根据μLED的发光亮度而改变的电压值。
  6. 根据权利要求2所述的μLED单元电路，其特征在于，所述发光控制电路包括边沿改善电路和驱动电路，其中，
    所述边沿校正电路，用于接收所述不同脉冲宽度的PWM信号和所述发光控制信号并校正所述不同脉冲宽度的PWM信号的边沿陡峭度；以及
    所述驱动电路，用于基于校正的不同脉冲宽度的PWM信号控制驱动晶体管的导通时间以提供所述驱动电流。
  7. 根据权利要求6所述的μLED单元电路，其特征在于，所述边沿校正电路包括第七晶体管、第八晶体管和第二电容器，其中，
    所述第七晶体管的栅极与所述反相器的输出端连接并经由所述第二电容器接收第二电源电压，所述第七晶体管的源极与所述第八晶体管的漏极连接，以及所述第七晶体管的漏极与所述第九晶体管的漏极连接；以及
    所述第八晶体管的栅极接收所述发光控制信号，所述第八晶体管的源极接收所述第二电源电压。
  8. 根据权利要求7所述的μLED单元电路，其特征在于，所述驱动电路包括所述第九晶体管、第十晶体管和第三电容器，所述第十晶体管为所述驱动晶体管，其中，
    所述第九晶体管的栅极接收所述行扫描信号SN，所述第九晶体管的源极接收PAMD信号，所述PAMD信号为发光亮度最高时的电压值；
    所述第十晶体管的源极与所述第二电源电压连接，所述第十晶体管的栅极与所述第七晶体管的漏极和所述第九晶体管的漏极连接；以及
    所述第三电容器的一端连接所述第二电源电压，以及所述第三电容器的另一端与所述第七晶体管的漏极和所述第九晶体管的漏极连接，其中，所述第二电源电压大于所述第一电源电压并且大于所述参考电源电压。
  9. 根据权利要求1至8中的任一项所述的μLED单元电路，其特征在于，所述μLED的阴极与所述驱动晶体管的漏极连接以及所述μLED的阳极用于接收所述发光控制信号；或者
    所述μLED的阳极与所述驱动晶体管的漏极连接以及所述μLED的阴极用于接收第三电源电压。
  10. 根据权利要求1至8中的任一项所述的μLED单元电路，其特征在于，所述第一晶体管至所述第十晶体管为N型TFT晶体管。
  11. 一种像素装置，其特征在于，包括m×n个根据权利要求1至9中的任一项所述的μLED单元电路。
  12. 一种μLED发光控制方法，其特征在于，包括比较发光步骤，其中，所述比较发光步骤包括：
    基于发光控制信号EM1和比较参考信号SWEEP生成具有不同脉冲宽度的PWM信号，其中，所述比较参考信号SWEEP为线性降低的斜坡信号；
    接收所述不同脉冲宽度的PWM信号并基于所述不同脉冲宽度的PWM信号控制驱动晶体管的导通时间以提供驱动电流；以及
    从所述发光控制电路接收所述驱动电流并基于所述驱动电流控制所述μLED的发光时间。
  13. 根据权利要求12所述的μLED发光控制方法，其特征在于，所述驱动电流为：
    Figure PCTCN2021087633-appb-100001
    其中，所述μ、C ox和
    Figure PCTCN2021087633-appb-100002
    分别表示所述驱动晶体管的迁移率、单位面积栅介质电容和沟道宽长比，所述PAMD为发光亮度最高时的电压值，V LED为所述μLED的电压，以及V th10为所述驱动晶体管的阈值电压。
  14. 根据权利要求12所述的μLED发光控制方法，其特征在于，在所述比较发光步骤之前，还包括初始化步骤和行扫描步骤，
    所述初始化步骤，基于复位信号RESET对像素装置的μLED单元电路进行初始化；以及
    所述行扫描步骤，在所述初始化步骤之后，基于行扫描信号SN对所述像素装置的μLED单元电路进行逐行扫描。
  15. 根据权利要求14所述的μLED发光控制方法，其特征在于，所述初始化步骤包括：
    将所述复位信号RESET提供给第一晶体管T1的栅极，所述第一晶体管T1导通，使得所述第一晶体管T1的源极与参考电源电压REF连接以将所述第一晶体管T1的漏极置位到参考电源电压REF，其中，所述复位信号为低电平。
  16. 根据权利要求15所述的μLED发光控制方法，其特征在于，所述行扫描步骤包括：
    将所述行扫描信号SN提供给第二晶体管T2和第三晶体管T3的栅极，所述第二 晶体管T2、所述第三晶体管T3、所述第六晶体管T6导通，使得所述第六晶体管T6的源极经由导通所述第三晶体管T3与PWMD信号连接并置位为PWMD，以及所述第六晶体管T6的漏极经由所述第二晶体管T2与所述第六晶体管T6的栅极连接，以使所述第六晶体管T6的漏极电压与所述第六晶体管T6的栅极电压为PWMD-|V th6|，其中，所述PWMD信号为根据μLED的发光亮度而改变的电压值；
    将行扫描信号SN提供给第九晶体管T9的栅极，使得所述第九晶体管T9导通，以经由所述第九晶体管T9将驱动晶体管的栅极置位为PAMD，其中，所述PAMD为所述μLED的发光亮度最高时的电压值，所述行扫描信号SN为低电平。
  17. 根据权利要求16所述的μLED发光控制方法，其特征在于，所述比较发光步骤进一步包括：
    将所述发光控制信号EM1提供给第四晶体管T4和第五晶体管T5的栅极并将比较参考信号SWEEP经由电容器提供给所述第六晶体管T6的栅极，将所述第四晶体管T4、所述第五晶体管T5和所述第六晶体管T6导通并连接为反相器，使得第六晶体管T6的源极为所述反相器的电源输入端并且经由所述第四晶体管T4与第一电源电压VGL连接，使得所述反相器的电源输入端的电压为第一电源电压VGL；所述第六晶体管T6的栅极为所述反相器的输入端并且使得所述反相器的电源输入端的电压为PWMD+V th6-ΔSWEEP；所述第六晶体管T6的漏极为所述反相器的输出端并经由所述第五晶体管T5与参考电源电压REF连接，使得所述反相器的输出端的电压为高电平而第七晶体管T7保持截止，其中，所述第六晶体管T6的尺寸大于所述第五晶体管T5的尺寸，以及所述发光控制信号EM1为脉冲信号。
  18. 根据权利要求17所述的μLED发光控制方法，其特征在于，所述比较发光步骤进一步包括：
    驱动晶体管T10导通，使得所述驱动晶体管T10的栅极电压保持所述PAMD信号，所述驱动晶体管T10的源极与第一电源电压VDD连接，以提供所述驱动电流，使得所述μLED开始发光。
  19. 根据权利要求18所述的μLED发光控制方法，其特征在于，所述比较发光步骤进一步包括：
    当所述比较参考信号SWEEP线性提高使得所述反相器的电源输入端的电压PWMD+V th6-ΔSWEEP大于VGH+V th6时，所述第六晶体管T6截止以将所述反相器的输出端的电压上升至REF，使得所述第七晶体管T7导通以将所述第一电源电压VDD传输至所述驱动晶体管T10的栅极或者将所述驱动晶体管T10的栅极置位为所述第一电源电压VDD，所述驱动晶体管T10截止使得所述μLED停止发光。
  20. 根据权利要求17所述的μLED发光控制方法，其特征在于，
    将所述发光控制信号EM2提供给第八晶体管T8，所述第八晶体管T8和驱动晶体管T10导通，使得所述驱动晶体管T10的栅极电压保持所述PAMD信号，所述驱动晶 体管T10的源极与第一电源电压VDD连接，以提供所述驱动电流，使得所述μLED开始发光，其中，所述发光控制信号EM2和所述发光控制信号EM1为脉冲信号，以及所述发光控制信号EM2的上升沿滞后于所述发光控制信号EM1的上升沿。
PCT/CN2021/087633 2021-01-22 2021-04-16 一种μLED单元电路、其发光控制方法和像素装置 WO2022156078A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110089400.4 2021-01-22
CN202110089400.4A CN114783352A (zh) 2021-01-22 2021-01-22 一种μLED单元电路、其发光控制方法和像素装置

Publications (1)

Publication Number Publication Date
WO2022156078A1 true WO2022156078A1 (zh) 2022-07-28

Family

ID=82407770

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/087633 WO2022156078A1 (zh) 2021-01-22 2021-04-16 一种μLED单元电路、其发光控制方法和像素装置

Country Status (2)

Country Link
CN (1) CN114783352A (zh)
WO (1) WO2022156078A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115294923B (zh) * 2022-08-29 2023-11-21 惠科股份有限公司 稳压电路及显示面板
TWI834473B (zh) * 2023-01-13 2024-03-01 友達光電股份有限公司 顯示面板
CN116543691B (zh) * 2023-05-19 2024-04-02 华南理工大学 一种栅极驱动电路、有源电致发光显示器及驱动方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007108568A (ja) * 2005-10-17 2007-04-26 Sony Corp 表示装置及びその駆動方法
US20140125246A1 (en) * 2012-10-29 2014-05-08 Rohm Co., Ltd. Control circuit for light emitting apparatus
CN108694908A (zh) * 2017-04-11 2018-10-23 三星电子株式会社 显示面板的像素电路和显示设备
CN110322829A (zh) * 2018-03-30 2019-10-11 脸谱科技有限责任公司 发光二极管的脉宽调制控制
CN111028776A (zh) * 2019-12-27 2020-04-17 厦门天马微电子有限公司 像素驱动电路、显示面板以及显示设备和像素驱动方法
CN111341252A (zh) * 2019-10-22 2020-06-26 友达光电股份有限公司 像素电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101466187B (zh) * 2009-01-05 2012-06-27 西安理工大学 一种pfm/pwm双模式切换调光的led驱动电路
CN106231737B (zh) * 2016-09-12 2023-10-13 Tcl华瑞照明科技（惠州）有限公司 Pwm隔离调光电路及led调光驱动电源
EP3389039A1 (en) * 2017-04-13 2018-10-17 Samsung Electronics Co., Ltd. Display panel and driving method of display panel
CN110634433B (zh) * 2018-06-01 2024-07-09 三星电子株式会社 显示面板
CN111477165A (zh) * 2020-05-13 2020-07-31 深圳市华星光电半导体显示技术有限公司 显示装置及其驱动方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007108568A (ja) * 2005-10-17 2007-04-26 Sony Corp 表示装置及びその駆動方法
US20140125246A1 (en) * 2012-10-29 2014-05-08 Rohm Co., Ltd. Control circuit for light emitting apparatus
CN108694908A (zh) * 2017-04-11 2018-10-23 三星电子株式会社 显示面板的像素电路和显示设备
CN110322829A (zh) * 2018-03-30 2019-10-11 脸谱科技有限责任公司 发光二极管的脉宽调制控制
CN111341252A (zh) * 2019-10-22 2020-06-26 友达光电股份有限公司 像素电路
CN111028776A (zh) * 2019-12-27 2020-04-17 厦门天马微电子有限公司 像素驱动电路、显示面板以及显示设备和像素驱动方法

Also Published As

Publication number Publication date
CN114783352A (zh) 2022-07-22

Similar Documents

Publication Publication Date Title
CN113838421B (zh) 像素电路及其驱动方法、显示面板
US10861394B2 (en) Gate driving circuit and light emitting display apparatus including the same
WO2022156079A1 (zh) 一种μLED单元发光电路、其发光控制方法和显示装置
WO2022062747A1 (zh) 像素电路、像素驱动方法、显示面板和显示装置
WO2022156078A1 (zh) 一种μLED单元电路、其发光控制方法和像素装置
WO2020233491A1 (zh) 像素电路及其驱动方法、阵列基板及显示装置
WO2019233120A1 (zh) 像素电路及其驱动方法、显示面板
CN111613180A (zh) Amoled像素补偿驱动电路、方法及显示面板
WO2020151657A1 (zh) 像素电路、像素驱动方法和显示装置
WO2016146053A1 (zh) 显示装置及其像素电路和驱动方法
WO2018133144A1 (zh) Amoled像素驱动系统及amoled像素驱动方法
US20200211464A1 (en) Pixel circuit and driving method thereof, and display panel
CN109979384B (zh) 像素驱动电路、像素电路、显示装置及像素驱动方法
US11551606B2 (en) LED driving circuit, display panel, and pixel driving device
WO2020143234A1 (zh) 像素驱动电路、像素驱动方法和显示装置
CN108777131B (zh) Amoled像素驱动电路及驱动方法
US10424249B2 (en) Pixel driving circuit and driving method thereof, array substrate, and display device
US11922881B2 (en) Pixel circuit and driving method thereof, array substrate and display apparatus
CN114566115A (zh) 像素驱动电路及显示面板
US20220230586A1 (en) Pixels, display device comprising pixels, and driving method therefor
WO2024098778A1 (zh) 一种像素驱动电路及其驱动方法、显示装置
CN113971932A (zh) 像素电路及其驱动方法、显示面板、显示装置和终端
CN115148144A (zh) 像素电路及显示面板
WO2024124902A1 (zh) 像素驱动电路、方法和显示面板
WO2019000518A1 (zh) 像素补偿电路及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21920465

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21920465

Country of ref document: EP

Kind code of ref document: A1