WO2022193685A1 - 驱动电路、驱动方法和显示装置 - Google Patents

驱动电路、驱动方法和显示装置 Download PDF

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Publication number
WO2022193685A1
WO2022193685A1 PCT/CN2021/129599 CN2021129599W WO2022193685A1 WO 2022193685 A1 WO2022193685 A1 WO 2022193685A1 CN 2021129599 W CN2021129599 W CN 2021129599W WO 2022193685 A1 WO2022193685 A1 WO 2022193685A1
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Prior art keywords
output
electrically connected
circuit
control
signal terminal
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PCT/CN2021/129599
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English (en)
French (fr)
Inventor
于子阳
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/912,629 priority Critical patent/US20240203339A1/en
Publication of WO2022193685A1 publication Critical patent/WO2022193685A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving circuit, a driving method and a display device.
  • LTPO Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide
  • pixel circuit can use LTPS (low temperature polycrystalline silicon) P-type TFT (thin film transistor) and IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide) N-type
  • the TFT is constructed by using a low-level active driving signal to control the P-type TFT, using a high-level active driving signal to control the N-type TFT, plus the light-emitting control signal, three sets of signal generation circuits are required.
  • the number of transistors used is large, which needs to occupy a large frame.
  • an embodiment of the present disclosure provides a driving circuit, comprising: a first control circuit, a second control circuit, a tank circuit, a first output circuit, and a second output circuit, wherein,
  • the first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the output driving signal terminal, and the energy storage circuit is used for storing electrical energy;
  • the first control circuit is electrically connected to the input driving signal terminal and the first node respectively, and is used for controlling the potential of the first node according to the input driving signal provided by the input driving signal terminal;
  • the second control circuit is respectively electrically connected to the control clock signal terminal, the first voltage terminal and the first node, and is used for controlling the first node under the control of the control clock signal provided by the control clock signal terminal communicated with the first voltage terminal;
  • the first output circuit is electrically connected to the first node, the first clock signal terminal and the output driving signal terminal, respectively, and is used for controlling the output driving signal terminal and the first node under the control of the potential of the first node. Connected between a clock signal terminal;
  • the second output circuit is electrically connected to the first clock signal terminal and the output driving signal terminal respectively, and is used for controlling the output driving signal terminal to provide a first clock signal according to the first clock signal provided by the first clock signal terminal. Output drive signal.
  • the first control circuit is further electrically connected to the second clock signal terminal, and is specifically configured to control the input driving signal terminal to be connected to the second clock signal terminal under the control of the second clock signal provided by the second clock signal terminal. communication between the first nodes.
  • the second output circuit is further electrically connected to the second voltage terminal, and is configured to control the connection between the output driving signal terminal and the second voltage terminal under the control of the first clock signal.
  • the drive circuit according to at least one embodiment of the present invention further includes a third output circuit
  • the third output circuit is respectively electrically connected to the input driving signal terminal, the first voltage terminal and the output driving signal terminal, and is used for controlling the output driving signal terminal under the control of the input driving signal communicated with the first voltage terminal.
  • the first control circuit includes a first transistor
  • control electrode of the first transistor and the first electrode of the first transistor are both electrically connected to the input driving signal terminal, and the second electrode of the first transistor is electrically connected to the first node.
  • the first control circuit includes a first transistor
  • the control pole of the first transistor is electrically connected to the second clock signal terminal, the first pole of the first transistor is electrically connected to the input driving signal terminal, and the second pole of the first transistor is electrically connected to the input driving signal terminal.
  • the first node is electrically connected.
  • the second control circuit includes a second transistor
  • the control pole of the second transistor is electrically connected to the control clock signal terminal, the first pole of the second transistor is electrically connected to the first voltage terminal, and the second pole of the second transistor is electrically connected to the first node electrical connection.
  • the energy storage circuit includes a storage capacitor, and the first output circuit includes a first output transistor;
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the output driving signal terminal;
  • the control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the output driving signal terminal, and the second electrode of the first output transistor is electrically connected to the output drive signal terminal.
  • the first clock signal terminal is electrically connected.
  • the second output circuit includes a second output transistor
  • control electrode of the second output transistor and the first electrode of the second output transistor are both electrically connected to the first clock signal terminal, and the second electrode of the second output transistor is electrically connected to the output driving signal terminal. connect.
  • the second output circuit includes a second output transistor
  • the control electrode of the second output transistor is electrically connected to the first clock signal terminal, the first electrode of the second output transistor is electrically connected to the second voltage terminal, and the second electrode of the second output transistor is electrically connected is electrically connected to the output driving signal terminal.
  • the third output circuit includes a third output transistor
  • the control electrode of the third output transistor is electrically connected to the input drive signal terminal, the first electrode of the third output transistor is electrically connected to the first voltage terminal, and the second electrode of the third output transistor is electrically connected to the first voltage terminal.
  • the output driving signal terminals are electrically connected.
  • an embodiment of the present invention further provides a driving method, which is applied to the above-mentioned driving circuit, and the driving cycle includes a first stage, a second stage and a third stage set in sequence; the driving method includes:
  • the first control circuit controls the potential of the first node according to the input drive signal provided by the input drive signal terminal, so that the first output circuit controls the output drive under the control of the potential of the first node
  • the signal terminal is connected with the first clock signal terminal
  • the energy storage circuit controls to change the potential of the first node, and the first output circuit continues to control the communication between the output drive signal terminal and the first clock signal terminal under the control of the potential of the first node;
  • the second control circuit controls the communication between the first node and the first voltage terminal, so as to control the potential of the first output circuit at the first node
  • the control output driving signal terminal is disconnected from the first clock signal terminal.
  • the driving cycle further includes a fourth stage disposed after the third stage, and the driving method further includes:
  • the second output circuit controls the output driving signal provided by the output driving signal terminal to be an invalid voltage signal according to the first clock signal.
  • the drive circuit further includes a third output circuit; the drive method further includes:
  • the third output circuit controls the connection between the output driving signal terminal and the first voltage terminal.
  • ⁇ t1 is greater than the fall time t1 of the first clock signal, the sum of the fall time t01 of the control clock signal and the first interval time m1, and ⁇ t1 is less than w1-t2-t02-m2;
  • ⁇ t1 is the time difference between the falling edge of the first clock signal and the falling edge of the control clock signal
  • w1 is the time during which the potential of the first clock signal remains at a low voltage
  • t2 is the first clock signal.
  • t02 is the rise time of the control clock signal
  • m2 is the second interval time.
  • an embodiment of the present invention further provides a display device, including the above-mentioned driving circuit.
  • FIG. 1 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 2 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 4 is a structural diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 5 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 6 is a working timing diagram of at least one embodiment of the driving circuit shown in FIG. 5;
  • FIG. 7 is a simulation timing diagram of at least one embodiment of the driving circuit shown in FIG. 5;
  • FIG. 8 is a simulation timing diagram of at least one embodiment of the drive circuit shown in FIG. 5 operating at a low frequency
  • FIG. 9 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 10 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 11 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 12 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 13 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • FIG. 14 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • 15 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention.
  • 16 is a circuit diagram of at least one embodiment of a signal generation circuit for generating a low voltage active drive signal
  • 17 is at least one embodiment of a related LTPO (Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide) pixel circuit;
  • LTPO Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide
  • FIG. 18 is an operation timing diagram of at least one embodiment of the LTPO pixel circuit shown in FIG. 17;
  • FIG. 19 is a timing chart of each clock signal.
  • the transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • control electrode when the transistor is a triode, the control electrode may be the base electrode, the first electrode may be the collector electrode, and the second electrode may be the emitter electrode; or the control electrode may be the base electrode electrode, the first electrode can be an emitter electrode, and the second electrode can be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode;
  • the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the drive circuit includes a first control circuit 11 , a second control circuit 12 , an energy storage circuit 13 , a first output circuit 14 and a second output circuit 15 , wherein,
  • the first end of the energy storage circuit 13 is electrically connected to the first node N1, the second end of the energy storage circuit 13 is electrically connected to the output driving signal terminal G1, and the energy storage circuit 13 is used for storing electrical energy;
  • the first control circuit 11 is electrically connected to the input driving signal terminal G0 and the first node N1 respectively, and is used for controlling the potential of the first node N1 according to the input driving signal provided by the input driving signal terminal G0;
  • the second control circuit 12 is respectively electrically connected to the control clock signal terminal K0, the first voltage terminal V1 and the first node N1, and is used for controlling the control clock signal provided by the control clock signal terminal K0 under the control of the control clock signal terminal K0. Connecting between the first node N1 and the first voltage terminal V1;
  • the first output circuit 14 is electrically connected to the first node N1, the first clock signal terminal K1 and the output driving signal terminal G1 respectively, and is used for controlling the output driving signal under the control of the potential of the first node N1
  • the terminal G1 is communicated with the first clock signal terminal K1;
  • the second output circuit 15 is electrically connected to the first clock signal terminal K1 and the output driving signal terminal G1 respectively, and is used for controlling the output according to the first clock signal provided by the first clock signal terminal K1
  • the driving signal terminal G1 provides an output driving signal.
  • the first voltage terminal V1 may be a high voltage terminal, but is not limited thereto.
  • the drive circuit according to the embodiment of the present invention can convert an input drive signal into an output drive signal, wherein the input drive signal is a gate drive signal with active low level, and the output drive signal is a gate drive signal with active high level gate drive signal; using the drive circuit described in the embodiment of the present invention can reduce the number of transistors used in the circuit for generating an active high gate drive signal, which is beneficial to achieve narrow borders, reduce costs, and simplify control timing.
  • the embodiment of the present invention is based on the original gate driving circuit for generating an active low-level driving signal, and the driving circuit described in the embodiment of the present invention is added to realize the output of the active-high driving signal.
  • the driving cycle may include the first stage, the second stage, the third stage and the fourth stage which are set in sequence;
  • the first control circuit 11 controls the potential of the first node N1 according to the input drive signal provided by the input drive signal terminal G0, so that the first output circuit 14 controls the potential of the first node N1 Next, control the communication between the output drive signal terminal G1 and the first clock signal terminal K1;
  • the tank circuit 13 controls to change the potential of the first node N1
  • the first output circuit 14 continues to control the output drive signal terminal G1 and the first clock signal terminal K1 under the control of the potential of the first node N1.
  • the second control circuit 12 controls the connection between the first node N1 and the first voltage terminal V1, so that the first output circuit 14 is in the Under the control of the potential of the first node N1, the output drive signal terminal G1 is controlled to be disconnected from the first clock signal terminal K1;
  • the second output circuit 15 controls the output driving signal provided by the output driving signal terminal G1 to be an invalid voltage signal according to the first clock signal.
  • the invalid voltage signal may be a low voltage signal.
  • the N-type transistor When the control electrode of the N-type transistor is connected to the invalid voltage signal, the N-type transistor is turned off; but not limited thereto.
  • the first control circuit may also be electrically connected to the second clock signal terminal, and is specifically configured to control the input drive signal terminal to be connected to the second clock signal terminal under the control of the second clock signal provided by the second clock signal terminal.
  • the first nodes communicate with each other.
  • the first control circuit 11 is also electrically connected to the second clock signal terminal K2. Under the control of the second clock signal provided by K2, the input driving signal terminal G0 is controlled to communicate with the first node N1.
  • the second output circuit may also be electrically connected to a second voltage terminal, for controlling the output driving signal terminal and the second voltage terminal under the control of the first clock signal connected between the voltage terminals.
  • the second output circuit 15 may also be electrically connected to the second voltage terminal V2 for Under the control of the first clock signal, the connection between the output driving signal terminal G1 and the second voltage terminal V2 is controlled.
  • the second voltage terminal V2 may be a low voltage terminal.
  • the driving circuit may further include a third output circuit 30 ;
  • the third output circuit 30 is respectively electrically connected to the input driving signal terminal G0, the first voltage terminal V1 and the output driving signal terminal G1, and is used for controlling the input driving signal under the control of the input driving signal.
  • the output driving signal terminal G1 is communicated with the first voltage terminal V1.
  • the first voltage terminal V1 may be a high voltage terminal.
  • At least one embodiment of the driving circuit shown in FIG. 4 of the present invention adopts the third output circuit 30, which can control the output driving signal terminal G1 and the first voltage terminal V1 when the potential of the input driving signal is a low voltage. It is connected to each other to ensure that the potential of the output driving signal provided by G1 is a high voltage at this time.
  • the first control circuit includes a first transistor
  • control electrode of the first transistor and the first electrode of the first transistor are both electrically connected to the input driving signal terminal, and the second electrode of the first transistor is electrically connected to the first node.
  • the first control circuit includes a first transistor
  • the control pole of the first transistor is electrically connected to the second clock signal terminal, the first pole of the first transistor is electrically connected to the input driving signal terminal, and the second pole of the first transistor is electrically connected to the input driving signal terminal.
  • the first node is electrically connected.
  • the second control circuit may include a second transistor
  • the control pole of the second transistor is electrically connected to the control clock signal terminal, the first pole of the second transistor is electrically connected to the first voltage terminal, and the second pole of the second transistor is electrically connected to the first node electrical connection.
  • the energy storage circuit may include a storage capacitor, and the first output circuit may include a first output transistor;
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the output driving signal terminal;
  • the control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the output driving signal terminal, and the second electrode of the first output transistor is electrically connected to the output drive signal terminal.
  • the first clock signal terminal is electrically connected.
  • the second output circuit includes a second output transistor
  • control electrode of the second output transistor and the first electrode of the second output transistor are both electrically connected to the first clock signal terminal, and the second electrode of the second output transistor is electrically connected to the output driving signal terminal. connect.
  • the second output circuit includes a second output transistor
  • the control electrode of the second output transistor is electrically connected to the first clock signal terminal, the first electrode of the second output transistor is electrically connected to the second voltage terminal, and the second electrode of the second output transistor is electrically connected is electrically connected to the output driving signal terminal.
  • the third output circuit includes a third output transistor
  • the control electrode of the third output transistor is electrically connected to the input drive signal terminal, the first electrode of the third output transistor is electrically connected to the first voltage terminal, and the second electrode of the third output transistor is electrically connected to the first voltage terminal.
  • the output driving signal terminals are electrically connected.
  • the driving circuit may include a first control circuit 11 , a second control circuit 12 , an energy storage circuit 13 , a first output circuit 14 and a second output circuit 15 , wherein,
  • the first control circuit 11 includes a first transistor T1;
  • the gate of T1 is electrically connected to the second clock signal terminal K2, the source of T1 is electrically connected to the input driving signal terminal G0, and the drain of T1 is electrically connected to the first node N1;
  • the second control circuit 12 includes a second transistor T2;
  • the gate of T2 is electrically connected to the control clock signal terminal K0, the source of T2 is electrically connected to the high-voltage terminal V01, and the drain of T2 is electrically connected to the first node N1;
  • the energy storage circuit 13 includes a storage capacitor C3, and the first output circuit 14 includes a first output transistor T01;
  • the first end of the storage capacitor C3 is electrically connected to the first node N1, and the second end of the storage capacitor C3 is electrically connected to the output driving signal terminal G1;
  • the gate of the first output transistor T01 is electrically connected to the first node N1, the source of the first output transistor T01 is electrically connected to the output driving signal terminal G1, and the drain of the first output transistor T01 is electrically connected
  • the pole is electrically connected to the first clock signal terminal K1;
  • the second output circuit 15 includes a second output transistor T02;
  • the gate of the second output transistor T02 is electrically connected to the first clock signal terminal K1
  • the source of the second output transistor T02 is electrically connected to the low voltage terminal V02
  • the drain of the second output transistor T02 It is electrically connected to the output driving signal terminal G1.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the driving cycle when at least one embodiment of the driving circuit shown in FIG. 5 is in operation, the driving cycle includes a first stage S1 , a second stage S2 , a third stage S3 and a fourth stage S4 arranged in sequence;
  • the potential of the second clock signal provided by K2 is low voltage
  • the potential of the control clock signal provided by K0 is high voltage
  • T2 is turned off
  • T1 is turned on
  • the potential of the input driving signal provided by G0 is low voltage
  • the potential of N1 is a low voltage
  • T01 is turned on
  • the potential of the first clock signal provided by K1 is a high voltage
  • T02 is turned off
  • G1 outputs a high voltage signal
  • the potential of the first clock signal provided by K1 is pulled down from a high voltage to a low voltage, T01 is turned on, G1 outputs a low voltage signal, and through the bootstrapping effect of C3, the potential of N1 is further pulled down, T01 Fully turned on, the potential of the output drive signal provided by G1 can be maintained at a very low level; the potential of the second clock signal provided by K2 is a high voltage, and T1 is turned off;
  • the potential of the control clock signal provided by K0 is pulled down from a high voltage to a low voltage, T2 is turned on, the potential of N1 is pulled up, T01 is turned off, and the jump of the potential of the first clock signal provided by K1 cannot affect The voltage of the output drive signal provided by G1, and G1 maintains the output low voltage signal;
  • the potential of the first clock signal provided by K1 is a low voltage.
  • the output driving signal provided by G1 generates ripple (noise) due to factors such as coupling or leakage, due to the existence of noise It will cause T02 to turn on when the potential of the first clock signal provided by K1 is low voltage, and release the noise, so that G1 can maintain the output low voltage signal;
  • the potential of the first clock signal provided by K1 is a low voltage.
  • G1 keeps outputting a low voltage signal, and T02 is turned off.
  • the time difference ⁇ t1 between the falling edge of the first clock signal provided by K1 and the falling edge of the control clock signal provided by K0 needs to meet the following requirements:
  • ⁇ t1 is greater than the fall time t1 of the first clock signal, the sum of the fall time t01 of the control clock signal and the first interval time m1, and ⁇ t1 is less than w1-t2-t02-m2;
  • w1 is the time when the potential of the first clock signal continues to be a low voltage
  • t2 is the rise time of the first clock signal
  • t02 is the rise time of the control clock signal
  • m2 is the second interval time; m1 and m2 can be based on the display product performance tuning.
  • the potential of the control clock signal can be lowered from a high voltage to a low voltage only after the potential of the first clock signal completely drops to a low voltage.
  • FIG. 7 is a simulation timing diagram of at least one embodiment of the driving circuit shown in FIG. 5 .
  • the label G1-1 is the output driving signal terminal of the next stage adjacent to G1
  • G1-2 is the output driving signal terminal of the next stage adjacent to G1-1.
  • FIG. 8 is a simulation timing diagram of at least one embodiment of the driving circuit shown in FIG. 5 operating at a low frequency. It can be seen from FIG. 8 that at a low frequency, at least one embodiment of the driving circuit shown in FIG. 5 can maintain a stable output drive signal.
  • the driving circuit may include a first control circuit 11 , a second control circuit 12 , an energy storage circuit 13 , a first output circuit 14 and a second output circuit 15 , wherein,
  • the first control circuit 11 includes a first transistor T1;
  • the gate of T1 is electrically connected to the second clock signal terminal K2, the source of T1 is electrically connected to the input driving signal terminal G0, and the drain of T1 is electrically connected to the first node N1;
  • the second control circuit 12 includes a second transistor T2;
  • the gate of T2 is electrically connected to the control clock signal terminal K0, the source of T2 is electrically connected to the high-voltage terminal V01, and the drain of T2 is electrically connected to the first node N1;
  • the energy storage circuit 13 includes a storage capacitor C3, and the first output circuit 14 includes a first output transistor T01;
  • the first end of the storage capacitor C3 is electrically connected to the first node N1, and the second end of the storage capacitor C3 is electrically connected to the output driving signal terminal G1;
  • the gate of the first output transistor T01 is electrically connected to the first node N1, the source of the first output transistor T01 is electrically connected to the output driving signal terminal G1, and the drain of the first output transistor T01 is electrically connected
  • the pole is electrically connected to the first clock signal terminal K1;
  • the second output circuit 15 includes a second output transistor T02;
  • the gate of the second output transistor T02 and the source of the second output transistor T02 are both electrically connected to the first clock signal terminal K1, and the drain of the second output transistor T02 is connected to the output driving signal
  • the terminal G1 is electrically connected.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the driving cycle includes the first stage S1, the second stage S2, the third stage S3 and the fourth stage S4 which are set in sequence;
  • the potential of the second clock signal provided by K2 is low voltage
  • the potential of the control clock signal provided by K0 is high voltage
  • T2 is turned off
  • T1 is turned on
  • the potential of the input driving signal provided by G0 is low voltage
  • the potential of N1 is a low voltage
  • T01 is turned on
  • the potential of the first clock signal provided by K1 is a high voltage
  • G1 outputs a high voltage signal
  • the potential of the first clock signal provided by K1 is pulled down from a high voltage to a low voltage, T01 is turned on, G1 outputs a low voltage signal, and through the bootstrapping effect of C3, the potential of N1 is further pulled down, T01 Fully turned on, the potential of the output drive signal provided by G1 can be maintained at a very low level; the potential of the second clock signal provided by K2 is a high voltage, and T1 is turned off;
  • the potential of the control clock signal provided by K0 is pulled down from a high voltage to a low voltage, T2 is turned on, the potential of N1 is pulled up, T01 is turned off, and the jump of the potential of the first clock signal provided by K1 cannot affect The voltage of the output drive signal provided by G1, and G1 maintains the output low voltage signal;
  • the potential of the first clock signal provided by K1 is a low voltage.
  • the output driving signal provided by G1 generates ripple (noise) due to factors such as coupling or leakage, due to the existence of noise It will cause T02 to turn on when the potential of the first clock signal provided by K1 is low voltage, and release the noise, so that G1 can maintain the output low voltage signal;
  • the potential of the first clock signal provided by K1 is a low voltage.
  • G1 keeps outputting a low voltage signal, and T02 is turned off.
  • the driving circuit may include a first control circuit 11 , a second control circuit 12 , an energy storage circuit 13 , a first output circuit 14 and a second output circuit 15 , wherein,
  • the first control circuit 11 includes a first transistor T1;
  • the gate of T1 and the source of T1 are both electrically connected to the input driving signal terminal G1, and the drain of T1 is electrically connected to the first node N1;
  • the second control circuit 12 includes a second transistor T2;
  • the gate of T2 is electrically connected to the control clock signal terminal K0, the source of T2 is electrically connected to the high-voltage terminal V01, and the drain of T2 is electrically connected to the first node N1;
  • the energy storage circuit 13 includes a storage capacitor C3, and the first output circuit 14 includes a first output transistor T01;
  • the first end of the storage capacitor C3 is electrically connected to the first node N1, and the second end of the storage capacitor C3 is electrically connected to the output drive signal terminal G1;
  • the gate of the first output transistor T01 is electrically connected to the first node N1, the source of the first output transistor T01 is electrically connected to the output driving signal terminal G1, and the drain of the first output transistor T01 is electrically connected
  • the pole is electrically connected to the first clock signal terminal K1;
  • the second output circuit 15 includes a second output transistor T02;
  • the gate of the second output transistor T02 is electrically connected to the first clock signal terminal K1
  • the source of the second output transistor T02 is electrically connected to the low voltage terminal V02
  • the drain of the second output transistor T02 It is electrically connected to the output driving signal terminal G1.
  • all the transistors are p-type thin film transistors, but not limited thereto.
  • the driving cycle includes the first stage S1, the second stage S2, the third stage S3 and the fourth stage S4 which are set in sequence;
  • the potential of the control clock signal provided by K0 is high voltage
  • T2 is turned off
  • the potential of the input driving signal provided by G0 is low voltage
  • T1 is turned on.
  • the potential of N1 is low voltage
  • T01 is turned on
  • K1 The potential of the provided first clock signal is a high voltage
  • T02 is turned off
  • G1 outputs a high voltage signal
  • the potential of the first clock signal provided by K1 is pulled down from a high voltage to a low voltage, T01 is turned on, G1 outputs a low voltage signal, and through the bootstrapping effect of C3, the potential of N1 is further pulled down, T01 Fully open, the potential of the output drive signal provided by G1 can be maintained at a very low level; the potential of the input drive signal provided by G0 is a high voltage, and T1 is turned off;
  • the potential of the control clock signal provided by K0 is pulled down from a high voltage to a low voltage, T2 is turned on, the potential of N1 is pulled up, T01 is turned off, and the jump of the potential of the first clock signal provided by K1 cannot affect The voltage of the output drive signal provided by G1, and G1 maintains the output low voltage signal;
  • the potential of the first clock signal provided by K1 is a low voltage.
  • the output driving signal provided by G1 generates ripple (noise) due to factors such as coupling or leakage, due to the existence of noise It will cause T02 to turn on when the potential of the first clock signal provided by K1 is low voltage, and release the noise, so that G1 can maintain the output low voltage signal;
  • the potential of the first clock signal provided by K1 is a low voltage.
  • G1 keeps outputting a low voltage signal, and T02 is turned off.
  • the driving circuit may include a first control circuit 11 , a second control circuit 12 , an energy storage circuit 13 , a first output circuit 14 and a second output circuit 15 , wherein,
  • the first control circuit 11 includes a first transistor T1;
  • the gate of T1 and the source of T1 are both electrically connected to the input driving signal terminal G0, and the drain of T1 is electrically connected to the first node N1;
  • the second control circuit 12 includes a second transistor T2;
  • the gate of T2 is electrically connected to the control clock signal terminal K0, the source of T2 is electrically connected to the high-voltage terminal V01, and the drain of T2 is electrically connected to the first node N1;
  • the energy storage circuit 13 includes a storage capacitor C3, and the first output circuit 14 includes a first output transistor T01;
  • the first end of the storage capacitor C3 is electrically connected to the first node N1, and the second end of the storage capacitor C3 is electrically connected to the output driving signal terminal G1;
  • the gate of the first output transistor T01 is electrically connected to the first node N1, the source of the first output transistor T01 is electrically connected to the output driving signal terminal G1, and the drain of the first output transistor T01 is electrically connected
  • the pole is electrically connected to the first clock signal terminal K1;
  • the second output circuit 15 includes a second output transistor T02;
  • the gate of the second output transistor T02 and the source of the second output transistor T02 are both electrically connected to the first clock signal terminal K1, and the drain of the second output transistor T02 is connected to the output driving signal
  • the terminal G1 is electrically connected.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the driving cycle includes the first stage S1 , the second stage S2 , the third stage S3 and the fourth stage S4 arranged in sequence;
  • the potential of the control clock signal provided by K0 is high voltage
  • T2 is turned off
  • the potential of the input driving signal provided by G0 is low voltage
  • T1 is turned on.
  • the potential of N1 is low voltage
  • T01 is turned on
  • K1 The potential of the provided first clock signal is a high voltage
  • G1 outputs a high voltage signal
  • the potential of the first clock signal provided by K1 is pulled down from a high voltage to a low voltage, T01 is turned on, G1 outputs a low voltage signal, and through the bootstrapping effect of C3, the potential of N1 is further pulled down, T01 Fully open, the potential of the output drive signal provided by G1 can be maintained at a very low level; the potential of the input drive signal provided by G0 is a high voltage, and T1 is turned off;
  • the potential of the control clock signal provided by K0 is pulled down from a high voltage to a low voltage, T2 is turned on, the potential of N1 is pulled up, T01 is turned off, and the jump of the potential of the first clock signal provided by K1 cannot affect The voltage of the output drive signal provided by G1, and G1 maintains the output low voltage signal;
  • the potential of the first clock signal provided by K1 is a low voltage.
  • the output driving signal provided by G1 generates ripple (noise) due to factors such as coupling or leakage, due to the existence of noise It will cause T02 to turn on when the potential of the first clock signal provided by K1 is low voltage, and release the noise, so that G1 can maintain the output low voltage signal;
  • the potential of the first clock signal provided by K1 is a low voltage.
  • G1 keeps outputting a low voltage signal, and T02 is turned off.
  • the driving circuit may include a first control circuit 11 , a second control circuit 12 , a tank circuit 13 , a first output circuit 14 , a second output circuit 15 and a third output circuit 30, wherein,
  • the first control circuit 11 includes a first transistor T1;
  • the gate of T1 is electrically connected to the second clock signal terminal K2, the source of T1 is electrically connected to the input driving signal terminal G0, and the drain of T1 is electrically connected to the first node N1;
  • the second control circuit 12 includes a second transistor T2;
  • the gate of T2 is electrically connected to the control clock signal terminal K0, the source of T2 is electrically connected to the high-voltage terminal V01, and the drain of T2 is electrically connected to the first node N1;
  • the energy storage circuit 13 includes a storage capacitor C3, and the first output circuit 14 includes a first output transistor T01;
  • the first end of the storage capacitor C3 is electrically connected to the first node N1, and the second end of the storage capacitor C3 is electrically connected to the output driving signal terminal G1;
  • the gate of the first output transistor T01 is electrically connected to the first node N1, the source of the first output transistor T01 is electrically connected to the output driving signal terminal G1, and the drain of the first output transistor T01 is electrically connected
  • the pole is electrically connected to the first clock signal terminal K1;
  • the second output circuit 15 includes a second output transistor T02;
  • the gate of the second output transistor T02 is electrically connected to the first clock signal terminal K1, the source of the second output transistor T02 is electrically connected to the low voltage terminal V02, and the drain of the second output transistor T02 is electrically connected to the output drive signal terminal G1;
  • the third output circuit 30 includes a third output transistor T03;
  • the gate of the third output transistor T03 is electrically connected to the input driving signal terminal G0, the source of the third output transistor T03 is electrically connected to the high voltage terminal V01, and the drain of the third output transistor T03 is electrically connected to the high-voltage terminal V01.
  • the output driving signal terminal G1 is electrically connected.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 12 and at least one embodiment of the driving circuit shown in FIG. 5 is that T03 is added.
  • T03 when at least one embodiment of the drive circuit shown in FIG. 12 is working, when the potential of the input drive signal provided by G0 is a low voltage, T03 is turned on, so that G1 and V01 are connected; when the potential of the input drive signal provided by G0 is at a low voltage When the voltage is high, T03 is turned off.
  • the driving circuit may include a first control circuit 11 , a second control circuit 12 , a tank circuit 13 , a first output circuit 14 , a second output circuit 15 and a third output circuit 30, wherein,
  • the first control circuit 11 includes a first transistor T1;
  • the gate of T1 is electrically connected to the second clock signal terminal K2, the source of T1 is electrically connected to the input driving signal terminal G0, and the drain of T1 is electrically connected to the first node N1;
  • the second control circuit 12 includes a second transistor T2;
  • the gate of T2 is electrically connected to the control clock signal terminal K0, the source of T2 is electrically connected to the high-voltage terminal V01, and the drain of T2 is electrically connected to the first node N1;
  • the energy storage circuit 13 includes a storage capacitor C3, and the first output circuit 14 includes a first output transistor T01;
  • the first end of the storage capacitor C3 is electrically connected to the first node N1, and the second end of the storage capacitor C3 is electrically connected to the output driving signal terminal G1;
  • the gate of the first output transistor T01 is electrically connected to the first node N1, the source of the first output transistor T01 is electrically connected to the output driving signal terminal G1, and the drain of the first output transistor T01 is electrically connected
  • the pole is electrically connected to the first clock signal terminal K1;
  • the second output circuit 15 includes a second output transistor T02;
  • the gate of the second output transistor T02 and the source of the second output transistor T02 are both electrically connected to the first clock signal terminal K1, and the drain of the second output transistor T02 is connected to the output driving signal Terminal G1 is electrically connected;
  • the third output circuit 30 includes a third output transistor T03;
  • the gate of the third output transistor T03 is electrically connected to the input driving signal terminal G0, the source of the third output transistor T03 is electrically connected to the high voltage terminal V01, and the drain of the third output transistor T03 is electrically connected to the high-voltage terminal V01.
  • the output driving signal terminal G1 is electrically connected.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 13 and at least one embodiment of the driving circuit shown in FIG. 9 is that T03 is added.
  • T03 When at least one embodiment of the drive circuit shown in FIG. 13 is in operation, when the potential of the input drive signal provided by G0 is a low voltage, T03 is turned on, so that G1 and V01 are connected; when the potential of the input drive signal provided by G0 is at a low voltage When the voltage is high, T03 is turned off.
  • the driving circuit may include a first control circuit 11 , a second control circuit 12 , a tank circuit 13 , a first output circuit 14 , a second output circuit 15 and a third output circuit 30, wherein,
  • the first control circuit 11 includes a first transistor T1;
  • the gate of T1 and the source of T1 are both electrically connected to the input driving signal terminal G1, and the drain of T1 is electrically connected to the first node N1;
  • the second control circuit 12 includes a second transistor T2;
  • the gate of T2 is electrically connected to the control clock signal terminal K0, the source of T2 is electrically connected to the high-voltage terminal V01, and the drain of T2 is electrically connected to the first node N1;
  • the energy storage circuit 13 includes a storage capacitor C3, and the first output circuit 14 includes a first output transistor T01;
  • the first end of the storage capacitor C3 is electrically connected to the first node N1, and the second end of the storage capacitor C3 is electrically connected to the output drive signal terminal G1;
  • the gate of the first output transistor T01 is electrically connected to the first node N1, the source of the first output transistor T01 is electrically connected to the output driving signal terminal G1, and the drain of the first output transistor T01 is electrically connected
  • the pole is electrically connected to the first clock signal terminal K1;
  • the second output circuit 15 includes a second output transistor T02;
  • the gate of the second output transistor T02 is electrically connected to the first clock signal terminal K1, the source of the second output transistor T02 is electrically connected to the low voltage terminal V02, and the drain of the second output transistor T02 is electrically connected to the output drive signal terminal G1;
  • the third output circuit 30 includes a third output transistor T03;
  • the gate of the third output transistor T03 is electrically connected to the input driving signal terminal G0, the source of the third output transistor T03 is electrically connected to the high voltage terminal V01, and the drain of the third output transistor T03 is electrically connected to the high-voltage terminal V01.
  • the output driving signal terminal G1 is electrically connected.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 14 and at least one embodiment of the driving circuit shown in FIG. 10 is that T03 is added.
  • T03 When at least one embodiment of the drive circuit shown in FIG. 14 is in operation, when the potential of the input drive signal provided by G0 is a low voltage, T03 is turned on, so that G1 and V01 are connected; when the potential of the input drive signal provided by G0 is at a low voltage When the voltage is high, T03 is turned off.
  • the driving circuit may include a first control circuit 11 , a second control circuit 12 , a tank circuit 13 , a first output circuit 14 , a second output circuit 15 and a third output circuit 30, wherein,
  • the first control circuit 11 includes a first transistor T1;
  • the gate of T1 and the source of T1 are both electrically connected to the input driving signal terminal G0, and the drain of T1 is electrically connected to the first node N1;
  • the second control circuit 12 includes a second transistor T2;
  • the gate of T2 is electrically connected to the control clock signal terminal K0, the source of T2 is electrically connected to the high-voltage terminal V01, and the drain of T2 is electrically connected to the first node N1;
  • Described energy storage circuit 13 includes storage capacitor C3, described first output circuit 14 includes first output transistor T01;
  • the first end of the storage capacitor C3 is electrically connected to the first node N1, and the second end of the storage capacitor C3 is electrically connected to the output driving signal terminal G1;
  • the gate of the first output transistor T01 is electrically connected to the first node N1, the source of the first output transistor T01 is electrically connected to the output driving signal terminal G1, and the drain of the first output transistor T01 is electrically connected
  • the pole is electrically connected to the first clock signal terminal K1;
  • the second output circuit 15 includes a second output transistor T02;
  • the gate of the second output transistor T02 and the source of the second output transistor T02 are both electrically connected to the first clock signal terminal K1, and the drain of the second output transistor T02 is connected to the output driving signal Terminal G1 is electrically connected;
  • the third output circuit 30 includes a third output transistor T03;
  • the gate of the third output transistor T03 is electrically connected to the input driving signal terminal G0, the source of the third output transistor T03 is electrically connected to the high voltage terminal V01, and the drain of the third output transistor T03 is electrically connected to the high-voltage terminal V01.
  • the output driving signal terminal G1 is electrically connected.
  • all the transistors are p-type thin film transistors, but not limited thereto.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 15 and at least one embodiment of the driving circuit shown in FIG. 11 is that T03 is added.
  • T03 when at least one embodiment of the driving circuit shown in FIG. 15 is working, when the potential of the input driving signal provided by G0 is a low voltage, T03 is turned on, so that G1 and V01 are connected; when the potential of the input driving signal provided by G0 is at a low voltage When the voltage is high, T03 is turned off.
  • a signal generating circuit for generating a low-voltage active driving signal includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the first capacitor C1 and the second capacitor C2, wherein,
  • the gate of T9 is electrically connected to the first clock signal terminal K1, the source of T9 is electrically connected to the input terminal I1, and the drain of T9 is electrically connected to the second node N2;
  • the gate of T10 is electrically connected to the second node N2, the source of T10 is electrically connected to the first clock signal terminal K1, and the drain of T10 is electrically connected to the third node N3;
  • the gate of T3 is electrically connected to the first clock signal terminal K1, the source of T3 is electrically connected to the low voltage terminal V02, and the drain of T3 is electrically connected to the third node N3;
  • the gate of T4 is electrically connected to the third node N3, the source of T4 is electrically connected to the high voltage terminal V01, and the drain of T4 is electrically connected to the input drive signal terminal G0;
  • the gate of T5 is electrically connected to the fourth node N4, the source of T5 is electrically connected to the second clock signal terminal K2, and the drain of T5 is electrically connected to the input drive signal terminal G0;
  • the gate of T6 is electrically connected to the third node N3, the source of T6 is electrically connected to the high voltage terminal V01, and the drain of T6 is electrically connected to the source of T7;
  • the gate of T7 is electrically connected to the second clock signal terminal K2, and the drain of T7 is electrically connected to the second node N2;
  • the gate of T8 is electrically connected to the low voltage terminal V02, the source of T8 is electrically connected to the second node N2, and the drain of T8 is electrically connected to the fourth node N4;
  • the first end of C1 is electrically connected to the fourth node N4, and the second end of C1 is electrically connected to the input driving signal end G0;
  • the first terminal of C2 is electrically connected to the third node N3, and the second terminal of C2 is electrically connected to the high voltage terminal V02.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • At least one embodiment of the related LTPO pixel circuit may include an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a tenth transistor Six transistors T16, seventeenth transistor T17, capacitor C0 and organic light emitting diode O1;
  • the gate of T11 is electrically connected to the initial control terminal I0, the source of T11 is electrically connected to the initialization voltage terminal V0, and the drain of T11 is electrically connected to the gate of T13;
  • the gate of T12 is electrically connected to the output drive signal terminal G1, the source of T12 is electrically connected to the gate of T13, and the drain of T12 is electrically connected to the drain of T13;
  • the gate of T14 is electrically connected to the input drive signal terminal G0, the source of T14 is electrically connected to the data line D1, and the drain of T14 is electrically connected to the source of T13;
  • the gate of T15 is electrically connected to the light-emitting control signal terminal E1, the source of T15 is electrically connected to the power supply voltage terminal E0, and the drain of T15 is electrically connected to the source of T13;
  • the gate of T16 is electrically connected to the light-emitting control signal terminal E1, the source of T16 is electrically connected to the drain of T13, the drain of T16 is electrically connected to the anode of O1; the cathode of O1 is connected to the low-voltage signal V3;
  • the gate of T17 is electrically connected to the input drive signal terminal G0, the source of T17 is electrically connected to the initialization voltage terminal V0, and the drain of T17 is electrically connected to the anode of O1;
  • the first terminal of C0 is electrically connected to the power supply voltage terminal E0, and the second terminal of C0 is electrically connected to the gate of T13.
  • T11 and T12 are all n-type thin film transistors
  • T13 , T14 , T15 , T16 and T17 are all p-type thin film transistors.
  • I0 is electrically connected to the output driving signal terminal of the adjacent previous stage, the input driving signal is a gate driving signal with active low level, and the output driving signal is A gate driving signal with active high level, the light-emitting control signal terminal E1 is used to provide a light-emitting control signal.
  • FIG. 18 is an operation timing diagram of at least one embodiment of the LTPO pixel circuit shown in FIG. 17 .
  • the driving method according to the embodiment of the present invention is applied to the above-mentioned driving circuit, and the driving period includes the first stage, the second stage and the third stage which are set in sequence; the driving method includes:
  • the first control circuit controls the potential of the first node according to the input drive signal provided by the input drive signal terminal, so that the first output circuit controls the output drive under the control of the potential of the first node
  • the signal terminal is connected with the first clock signal terminal
  • the energy storage circuit controls to change the potential of the first node, and the first output circuit continues to control the communication between the output drive signal terminal and the first clock signal terminal under the control of the potential of the first node;
  • the second control circuit controls the communication between the first node and the first voltage terminal, so as to control the potential of the first output circuit at the first node
  • the control output driving signal terminal is disconnected from the first clock signal terminal.
  • the drive circuit according to the embodiment of the present invention can convert an input drive signal into an output drive signal, wherein the input drive signal is a gate drive signal with active low level, and the output drive signal is a gate drive signal with active high level pole drive signal.
  • the driving cycle further includes a fourth stage disposed after the third stage, and the driving method further includes:
  • the second output circuit controls the output driving signal provided by the output driving signal terminal to be an invalid voltage signal according to the first clock signal.
  • the driving circuit further includes a third output circuit; and the driving method according to at least one embodiment of the present invention further includes:
  • the third output circuit controls the connection between the output driving signal terminal and the first voltage terminal.
  • the first voltage terminal is a high voltage terminal.
  • At least one embodiment of the present invention adopts a third output circuit, which can control the connection between the output driving signal terminal and the first voltage terminal when the potential of the input driving signal is a low voltage, so as to ensure that the potential of the output driving signal is high at this time Voltage.
  • ⁇ t1 is greater than the fall time t1 of the first clock signal, the sum of the fall time t01 of the control clock signal and the first interval time m1, and ⁇ t1 is less than w1-t2-t02-m2, so that the first clock signal After the potential of the control clock signal completely drops to a low voltage, the potential of the control clock signal begins to drop from a high voltage to a low voltage;
  • ⁇ t1 is the time difference between the falling edge of the first clock signal and the falling edge of the control clock signal
  • w1 is the time during which the potential of the first clock signal remains at a low voltage
  • t2 is the first clock signal.
  • t02 is the rise time of the control clock signal
  • m2 is the second interval time.
  • the display device includes the above-mentioned driving circuit.
  • the control clock signal terminal of the driving circuit that provides the output driving signal for the odd row pixel circuits when the control clock signal terminal of the driving circuit that provides the output driving signal for the odd row pixel circuits is electrically connected to the third clock signal terminal, the control clock signal terminal that provides the output driving signal for the even row pixel circuits is electrically connected.
  • the control clock signal terminal of the driving circuit is electrically connected to the fourth clock signal terminal.
  • FIG 19 shows the first clock signal provided by the first clock signal terminal K1, the second clock signal provided by the second clock signal terminal K2, the third clock signal provided by the third clock signal terminal K3, and the fourth clock signal provided by the terminal K4. Timing diagram of the fourth clock signal.
  • the time difference between the falling edge of the first clock signal provided by K1 and the falling edge of the third clock signal provided by K3 is ⁇ t1
  • the falling edge of the second clock signal provided by K2 and the first clock signal provided by K4 are ⁇ t1.
  • the time difference between the falling edges of the four clock signals is ⁇ t2;
  • ⁇ t2 needs to meet the following requirements:
  • ⁇ t2 is greater than the sum of the fall time t3 of the second clock signal, the fall time t03 of the fourth clock signal and the first interval time m1, and ⁇ t2 is less than w2-t4-t04-m2;
  • w2 is the time during which the potential of the second clock signal continues to be a low voltage
  • t4 is the rise time of the second clock signal
  • t04 is the rise time of the fourth clock signal
  • m2 is the second interval time; m1 and m2 can be based on the display Adjust product performance.
  • the potential of the fourth clock signal starts to drop from a high voltage to a low voltage only after the potential of the second clock signal completely drops to a low voltage.
  • the display device provided by the embodiment of the present invention may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

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  • Shift Register Type Memory (AREA)

Abstract

本公开提供一种驱动电路、驱动方法和显示装置。所述驱动电路，包括第一控制电路、第二控制电路、储能电路、第一输出电路和第二输出电路；第一控制电路根据输入驱动信号端提供的输入驱动信号，控制第一节点的电位；第二控制电路在控制时钟信号的控制下，控制第一节点与第一电压端之间连通；第一输出电路在第一节点的电位的控制下，控制输出驱动信号端与第一时钟信号端之间连通；第二输出电路根据第一时钟信号，控制输出驱动信号端提供输出驱动信号。本发明解决现有的驱动电路采用的晶体管的个数多，不利于实现窄边框的问题。

Description

驱动电路、驱动方法和显示装置
相关申请的交叉引用
本申请主张在2021年3月15日在中国提交的中国专利申请号No.202110275825.4的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、驱动方法和显示装置。
背景技术
在相关技术中，LTPO(Low Temperature Polycrystalline Oxide，低温多晶氧化物)像素电路可以采用LTPS(低温多晶硅)P型TFT(薄膜晶体管)和IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)N型TFT构建而成，需要采用低电平有效的驱动信号来控制P型TFT，采用高电平有效的驱动信号来控制N型TFT，再加上发光控制信号，则需要采用三组信号生成电路，采用的晶体管的数目多，需要占用较大边框。
发明内容
在一个方面中，本公开实施例提供了一种驱动电路，包括：第一控制电路、第二控制电路、储能电路、第一输出电路和第二输出电路，其中，
所述储能电路的第一端与第一节点电连接，所述储能电路的第二端与输出驱动信号端电连接，所述储能电路用于储存电能；
所述第一控制电路分别与输入驱动信号端和第一节点电连接，用于根据所述输入驱动信号端提供的输入驱动信号，控制第一节点的电位；
所述第二控制电路分别与控制时钟信号端、第一电压端和所述第一节点电连接，用于在所述控制时钟信号端提供的控制时钟信号的控制下，控制所述第一节点与所述第一电压端之间连通；
所述第一输出电路分别与所述第一节点、第一时钟信号端和输出驱动信 号端电连接，用于在第一节点的电位的控制下，控制所述输出驱动信号端与所述第一时钟信号端之间连通；
所述第二输出电路分别与所述第一时钟信号端与所述输出驱动信号端电连接，用于根据所述第一时钟信号端提供的第一时钟信号，控制所述输出驱动信号端提供输出驱动信号。
可选的，所述第一控制电路还与第二时钟信号端电连接，具体用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述输入驱动信号端与所述第一节点之间连通。
可选的，所述第二输出电路还与第二电压端电连接，用于在所述第一时钟信号的控制下，控制所述输出驱动信号端与所述第二电压端之间连通。
可选的，本发明至少一实施例所述的驱动电路还包括第三输出电路；
所述第三输出电路分别与所述输入驱动信号端、所述第一电压端和所述输出驱动信号端电连接，用于在所述输入驱动信号的控制下，控制所述输出驱动信号端与所述第一电压端之间连通。
可选的，所述第一控制电路包括第一晶体管；
所述第一晶体管的控制极与所述第一晶体管的第一极都与所述输入驱动信号端电连接，所述第一晶体管的第二极与所述第一节点电连接。
可选的，所述第一控制电路包括第一晶体管；
所述第一晶体管的控制极与所述第二时钟信号端电连接，所述第一晶体管的第一极与所述输入驱动信号端电连接，所述第一晶体管的第二极与所述第一节点电连接。
可选的，所述第二控制电路包括第二晶体管；
所述第二晶体管的控制极与所述控制时钟信号端电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与第一节点电连接。
可选的，所述储能电路包括存储电容，所述第一输出电路包括第一输出晶体管；
所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述输出驱动信号端电连接；
所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与所述输出驱动信号端电连接，所述第一输出晶体管的第二极与所述第一时钟信号端电连接。
可选的，所述第二输出电路包括第二输出晶体管；
所述第二输出晶体管的控制极与所述第二输出晶体管的第一极都与所述第一时钟信号端电连接，所述第二输出晶体管的第二极与所述输出驱动信号端电连接。
可选的，所述第二输出电路包括第二输出晶体管；
所述第二输出晶体管的控制极与所述第一时钟信号端电连接，所述第二输出晶体管的第一极与所述第二电压端电连接，所述第二输出晶体管的第二极与所述输出驱动信号端电连接。
可选的，所述第三输出电路包括第三输出晶体管；
所述第三输出晶体管的控制极与所述输入驱动信号端电连接，所述第三输出晶体管的第一极与所述第一电压端电连接，所述第三输出晶体管的第二极与所述输出驱动信号端电连接。
在第二个方面中，本发明实施例还提供了一种驱动方法，应用于上述的驱动电路，驱动周期包括依次设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
在第一阶段，第一控制电路根据所述输入驱动信号端提供的输入驱动信号，控制第一节点的电位，以使得第一输出电路在所述第一节点的电位的控制下，控制输出驱动信号端与第一时钟信号端之间连通；
在第二阶段，储能电路控制改变第一节点的电位，第一输出电路继续在所述第一节点的电位的控制下，控制输出驱动信号端与第一时钟信号端之间连通；
在第三阶段，第二控制电路在控制时钟信号的控制下，控制所述第一节点与所述第一电压端之间连通，以使得第一输出电路在所述第一节点的电位的控制下，控制输出驱动信号端与第一时钟信号端之间断开。
可选的，驱动周期还包括设置于所述第三阶段之后的第四阶段，所述驱动方法还包括：
在第四阶段包括的至少部分时间段，所述第二输出电路根据第一时钟信号，控制所述输出驱动信号端提供的输出驱动信号为无效电压信号。
可选的，所述驱动电路还包括第三输出电路；所述驱动方法还包括：
在第一阶段，第三输出电路在所述输入驱动信号的控制下，控制所述输出驱动信号端与第一电压端之间连通。
可选的，Δt1大于第一时钟信号的下降时间t1、控制时钟信号的下降时间t01与第一间隔时间m1的和值，并且，Δt1小于w1-t2-t02-m2；
其中，Δt1为所述第一时钟信号的下降沿与所述控制时钟信号的下降沿之间的时间差，w1为所述第一时钟信号的电位持续为低电压的时间，t2为所述第一时钟信号的上升时间，t02为所述控制时钟信号的上升时间，m2为第二间隔时间。
在第三个方面中，本发明实施例还提供了一种显示装置，包括上述的驱动电路。
附图说明
图1是本发明至少一实施例所述的驱动电路的结构图；
图2是本发明至少一实施例所述的驱动电路的结构图；
图3是本发明至少一实施例所述的驱动电路的结构图；
图4是本发明至少一实施例所述的驱动电路的结构图；
图5是本发明至少一实施例所述的驱动电路的电路图；
图6是图5所示的驱动电路的至少一实施例的工作时序图；
图7是图5所示的驱动电路的至少一实施例的仿真时序图；
图8是图5所示的驱动电路的至少一实施例在低频下工作的仿真时序图；
图9是本发明至少一实施例所述的驱动电路的电路图；
图10是本发明至少一实施例所述的驱动电路的电路图；
图11是本发明至少一实施例所述的驱动电路的电路图；
图12是本发明至少一实施例所述的驱动电路的电路图；
图13是本发明至少一实施例所述的驱动电路的电路图；
图14是本发明至少一实施例所述的驱动电路的电路图；
图15是本发明至少一实施例所述的驱动电路的电路图；
图16是用于生成低电压有效的驱动信号的信号生成电路的至少一实施例的电路图；
图17是相关的LTPO(Low Temperature Polycrystalline Oxide，低温多晶氧化物)像素电路的至少一实施例；
图18是图17所示的LTPO像素电路的至少一实施例的工作时序图；
图19是各时钟信号的时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本发明实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本发明至少一实施例所述的驱动电路包括第一控制电路11、第二控制电路12、储能电路13、第一输出电路14和第二输出电路15，其中，
所述储能电路13的第一端与第一节点N1电连接，所述储能电路13的第二端与输出驱动信号端G1电连接，所述储能电路13用于储存电能；
所述第一控制电路11分别与输入驱动信号端G0和第一节点N1电连接，用于根据所述输入驱动信号端G0提供的输入驱动信号，控制第一节点N1的电位；
所述第二控制电路12分别与控制时钟信号端K0、第一电压端V1和所述第一节点N1电连接，用于在所述控制时钟信号端K0提供的控制时钟信号的控制下，控制所述第一节点N1与所述第一电压端V1之间连通；
所述第一输出电路14分别与所述第一节点N1、第一时钟信号端K1和输出驱动信号端G1电连接，用于在第一节点N1的电位的控制下，控制所述输出驱动信号端G1与所述第一时钟信号端K1之间连通；
所述第二输出电路15分别与所述第一时钟信号端K1与所述输出驱动信号端G1电连接，用于根据所述第一时钟信号端K1提供的第一时钟信号，控制所述输出驱动信号端G1提供输出驱动信号。
在本发明至少一实施例中，所述第一电压端V1可以为高电压端，但不以此为限。
本发明实施例所述的驱动电路可以将输入驱动信号转换为输出驱动信号，其中，所述输入驱动信号为低电平有效的栅极驱动信号，所述输出驱动信号为高电平有效的栅极驱动信号；采用本发明实施例所述的驱动电路，可以减少生成高电平有效的栅极驱动信号的电路采用的晶体管的个数，利于实现窄边框和降低成本，并使得控制时序简单。
本发明实施例基于原有的生成低电平有效的驱动信号的栅极驱动电路，增加本发明实施例所述的驱动电路，即可实现高电平有效的驱动信号的输出。
本发明实施例所述的驱动电路在工作时，驱动周期可以包括依次设置的第一阶段、第二阶段、第三阶段和第四阶段；
在第一阶段，第一控制电路11根据所述输入驱动信号端G0提供的输入驱动信号，控制第一节点N1的电位，以使得第一输出电路14在所述第一节点N1的电位的控制下，控制输出驱动信号端G1与第一时钟信号端K1之间连通；
在第二阶段，储能电路13控制改变第一节点N1的电位，第一输出电路14继续在所述第一节点N1的电位的控制下，控制输出驱动信号端G1与第一时钟信号端K1之间连通；
在第三阶段，第二控制电路12在K0提供的控制时钟信号的控制下，控制所述第一节点N1与所述第一电压端V1之间连通，以使得第一输出电路14 在所述第一节点N1的电位的控制下，控制输出驱动信号端G1与第一时钟信号端K1之间断开；
在第四阶段包括的至少部分时间段，所述第二输出电路15根据第一时钟信号，控制所述输出驱动信号端G1提供的输出驱动信号为无效电压信号。
在本发明至少一实施例中，所述无效电压信号可以为低电压信号，当N型晶体管的控制极接入所述无效电压信号时，N型晶体管关闭；但不以此为限。
可选的，所述第一控制电路还可以与第二时钟信号端电连接，具体用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述输入驱动信号端与所述第一节点之间连通。
如图2所示，在本发明至少一实施例中，在图1所示的驱动电路的实施例的基础上，所述第一控制电路11还与第二时钟信号端K2电连接，具体用于在K2提供的第二时钟信号的控制下，控制所述输入驱动信号端G0与第一节点N1之间连通。
在本发明至少一实施例中，所述第二输出电路还可以与第二电压端电连接，用于在所述第一时钟信号的控制下，控制所述输出驱动信号端与所述第二电压端之间连通。
如图3所示，在本发明至少一实施例中，在图1所示的驱动电路的实施例的基础上，所述第二输出电路15还可以与第二电压端V2电连接，用于在所述第一时钟信号的控制下，控制所述输出驱动信号端G1与所述第二电压端V2之间连通。
可选的，所述第二电压端V2可以为低电压端。
如图4所示，在图1所示的驱动电路的实施例的基础上，本发明至少一实施例所述的驱动电路还可以包括第三输出电路30；
所述第三输出电路30分别与所述输入驱动信号端G0、所述第一电压端V1和所述输出驱动信号端G1电连接，用于在所述输入驱动信号的控制下，控制所述输出驱动信号端G1与所述第一电压端V1之间连通。
可选的，所述第一电压端V1可以为高电压端。
本发明如图4所示的驱动电路的至少一实施例采用了第三输出电路30， 能够在所述输入驱动信号的电位为低电压时，控制输出驱动信号端G1与第一电压端V1之间连通，保证此时G1提供的输出驱动信号的电位为高电压。
可选的，所述第一控制电路包括第一晶体管；
所述第一晶体管的控制极与所述第一晶体管的第一极都与所述输入驱动信号端电连接，所述第一晶体管的第二极与所述第一节点电连接。
可选的，所述第一控制电路包括第一晶体管；
所述第一晶体管的控制极与所述第二时钟信号端电连接，所述第一晶体管的第一极与所述输入驱动信号端电连接，所述第一晶体管的第二极与所述第一节点电连接。
在本发明至少一实施例中，所述第二控制电路可以包括第二晶体管；
所述第二晶体管的控制极与所述控制时钟信号端电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与第一节点电连接。
可选的，所述储能电路可以包括存储电容，所述第一输出电路可以包括第一输出晶体管；
所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述输出驱动信号端电连接；
所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与所述输出驱动信号端电连接，所述第一输出晶体管的第二极与所述第一时钟信号端电连接。
可选的，所述第二输出电路包括第二输出晶体管；
所述第二输出晶体管的控制极与所述第二输出晶体管的第一极都与所述第一时钟信号端电连接，所述第二输出晶体管的第二极与所述输出驱动信号端电连接。
可选的，所述第二输出电路包括第二输出晶体管；
所述第二输出晶体管的控制极与所述第一时钟信号端电连接，所述第二输出晶体管的第一极与所述第二电压端电连接，所述第二输出晶体管的第二极与所述输出驱动信号端电连接。
在本发明至少一实施例中，所述第三输出电路包括第三输出晶体管；
所述第三输出晶体管的控制极与所述输入驱动信号端电连接，所述第三输出晶体管的第一极与所述第一电压端电连接，所述第三输出晶体管的第二极与所述输出驱动信号端电连接。
如图5所示，本发明至少一实施例所述的驱动电路可以包括第一控制电路11、第二控制电路12、储能电路13、第一输出电路14和第二输出电路15，其中，
所述第一控制电路11包括第一晶体管T1；
T1的栅极与第二时钟信号端K2电连接，T1的源极与所述输入驱动信号端G0电连接，T1的漏极与第一节点N1电连接；
所述第二控制电路12包括第二晶体管T2；
T2的栅极与所述控制时钟信号端K0电连接，T2的源极与高电压端V01电连接，T2的漏极与第一节点N1电连接；
所述储能电路13包括存储电容C3，所述第一输出电路14包括第一输出晶体管T01；
所述存储电容C3的第一端与所述第一节点N1电连接，所述存储电容C3的第二端与所述输出驱动信号端G1电连接；
所述第一输出晶体管T01的栅极与所述第一节点N1电连接，所述第一输出晶体管T01的源极与所述输出驱动信号端G1电连接，所述第一输出晶体管T01的漏极与所述第一时钟信号端K1电连接；
所述第二输出电路15包括第二输出晶体管T02；
所述第二输出晶体管T02的栅极与所述第一时钟信号端K1电连接，所述第二输出晶体管T02的源极与低电压端V02电连接，所述第二输出晶体管T02的漏极与所述输出驱动信号端G1电连接。
在图5所示的驱动电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
如图6所示，如图5所示的驱动电路的至少一实施例在工作时，驱动周期包括依次设置的第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4；
在第一阶段S1，K2提供的第二时钟信号的电位为低电压，K0提供的控制时钟信号的电位为高电压，T2关断，T1打开，G0提供的输入驱动信号的 电位为低电压，此时N1的电位为低电压，T01打开，K1提供的第一时钟信号的电位为高电压，T02关断，G1输出高电压信号；
在第二阶段S2，K1提供的第一时钟信号的电位由高电压被拉低为低电压，T01打开，G1输出低电压信号，通过C3的自举作用，N1的电位进一步被拉低，T01充分打开，G1提供的输出驱动信号的电位可以维持在非常低的水平；K2提供的第二时钟信号的电位为高电压，T1关断；
在第三阶段S3，K0提供的控制时钟信号的电位由高电压拉低为低电压，打开T2，将N1的电位拉高，T01关闭，K1提供的第一时钟信号的电位的跳变无法影响G1提供的输出驱动信号的电压，G1维持输出低电压信号；
在第四阶段S4包括的至少部分时间段，K1提供的第一时钟信号的电位为低电压，当G1提供的输出驱动信号因为耦合或漏电等因素产生ripple(杂讯)，由于杂讯的存在会导致K1提供的第一时钟信号的电位为低电压时T02打开，并释放掉杂讯，使得G1能够维持输出低电压信号；
在第四阶段S4包括的至少部分时间段，K1提供的第一时钟信号的电位为低电压，当G1提供的输出驱动信号不存在杂讯时，G1维持输出低电压信号，T02关断。
如图6所示，K1提供的第一时钟信号的下降沿与K0提供的控制时钟信号的下降沿之间的时间差Δt1需要满足以下要求：
Δt1大于第一时钟信号的下降时间t1、控制时钟信号的下降时间t01与第一间隔时间m1的和值，并且，Δt1小于w1-t2-t02-m2；
其中，w1为第一时钟信号的电位持续为低电压的时间，t2为第一时钟信号的上升时间，t02为控制时钟信号的上升时间，m2为第二间隔时间；m1和m2可以基于显示产品性能进行调整。
通过以上Δt1的限定，能够使得第一时钟信号的电位完全下降为低电压之后，控制时钟信号的电位才开始由高电压下降为低电压。
图7是图5所示的驱动电路的至少一实施例的仿真时序图。
在图7中，标号为G1-1的为与G1相邻的下一级输出驱动信号端，G1-2为与G1-1相邻的下一级输出驱动信号端。
由图7可知，各级输出驱动信号端可以依次移位输出，满足像素电路驱 动要求。
图8是图5所示的驱动电路的至少一实施例在低频下工作的仿真时序图，由图8可知，在低频下，图5所示的驱动电路的至少一实施例能维持稳定提供输出驱动信号。
如图9所示，本发明至少一实施例所述的驱动电路可以包括第一控制电路11、第二控制电路12、储能电路13、第一输出电路14和第二输出电路15，其中，
所述第一控制电路11包括第一晶体管T1；
T1的栅极与第二时钟信号端K2电连接，T1的源极与所述输入驱动信号端G0电连接，T1的漏极与第一节点N1电连接；
所述第二控制电路12包括第二晶体管T2；
T2的栅极与所述控制时钟信号端K0电连接，T2的源极与高电压端V01电连接，T2的漏极与第一节点N1电连接；
所述储能电路13包括存储电容C3，所述第一输出电路14包括第一输出晶体管T01；
所述存储电容C3的第一端与所述第一节点N1电连接，所述存储电容C3的第二端与所述输出驱动信号端G1电连接；
所述第一输出晶体管T01的栅极与所述第一节点N1电连接，所述第一输出晶体管T01的源极与所述输出驱动信号端G1电连接，所述第一输出晶体管T01的漏极与所述第一时钟信号端K1电连接；
所述第二输出电路15包括第二输出晶体管T02；
所述第二输出晶体管T02的栅极和所述第二输出晶体管T02的源极都与所述第一时钟信号端K1电连接，所述第二输出晶体管T02的漏极与所述输出驱动信号端G1电连接。
在图9所示的驱动电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
如图6所示，如图9所示的驱动电路的至少一实施例在工作时，驱动周期包括依次设置的第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4；
在第一阶段S1，K2提供的第二时钟信号的电位为低电压，K0提供的控 制时钟信号的电位为高电压，T2关断，T1打开，G0提供的输入驱动信号的电位为低电压，此时N1的电位为低电压，T01打开，K1提供的第一时钟信号的电位为高电压，G1输出高电压信号；
在第二阶段S2，K1提供的第一时钟信号的电位由高电压被拉低为低电压，T01打开，G1输出低电压信号，通过C3的自举作用，N1的电位进一步被拉低，T01充分打开，G1提供的输出驱动信号的电位可以维持在非常低的水平；K2提供的第二时钟信号的电位为高电压，T1关断；
在第三阶段S3，K0提供的控制时钟信号的电位由高电压拉低为低电压，打开T2，将N1的电位拉高，T01关闭，K1提供的第一时钟信号的电位的跳变无法影响G1提供的输出驱动信号的电压，G1维持输出低电压信号；
在第四阶段S4包括的至少部分时间段，K1提供的第一时钟信号的电位为低电压，当G1提供的输出驱动信号因为耦合或漏电等因素产生ripple(杂讯)，由于杂讯的存在会导致K1提供的第一时钟信号的电位为低电压时T02打开，并释放掉杂讯，使得G1能够维持输出低电压信号；
在第四阶段S4包括的至少部分时间段，K1提供的第一时钟信号的电位为低电压，当G1提供的输出驱动信号不存在杂讯时，G1维持输出低电压信号，T02关断。
如图10所示，本发明至少一实施例所述的驱动电路可以包括第一控制电路11、第二控制电路12、储能电路13、第一输出电路14和第二输出电路15，其中，
所述第一控制电路11包括第一晶体管T1；
T1的栅极和T1的源极都与输入驱动信号端G1电连接，T1的漏极与第一节点N1电连接；
所述第二控制电路12包括第二晶体管T2；
T2的栅极与所述控制时钟信号端K0电连接，T2的源极与高电压端V01电连接，T2的漏极与第一节点N1电连接；
所述储能电路13包括存储电容C3，所述第一输出电路14包括第一输出晶体管T01；
所述存储电容C3的第一端与所述第一节点N1电连接，所述存储电容 C3的第二端与所述输出驱动信号端G1电连接；
所述第一输出晶体管T01的栅极与所述第一节点N1电连接，所述第一输出晶体管T01的源极与所述输出驱动信号端G1电连接，所述第一输出晶体管T01的漏极与所述第一时钟信号端K1电连接；
所述第二输出电路15包括第二输出晶体管T02；
所述第二输出晶体管T02的栅极与所述第一时钟信号端K1电连接，所述第二输出晶体管T02的源极与低电压端V02电连接，所述第二输出晶体管T02的漏极与所述输出驱动信号端G1电连接。
在图10所示的驱动电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
如图6所示，如图10所示的驱动电路的至少一实施例在工作时，驱动周期包括依次设置的第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4；
在第一阶段S1，K0提供的控制时钟信号的电位为高电压，T2关断，G0提供的输入驱动信号的电位为低电压，T1打开，此时N1的电位为低电压，T01打开，K1提供的第一时钟信号的电位为高电压，T02关断，G1输出高电压信号；
在第二阶段S2，K1提供的第一时钟信号的电位由高电压被拉低为低电压，T01打开，G1输出低电压信号，通过C3的自举作用，N1的电位进一步被拉低，T01充分打开，G1提供的输出驱动信号的电位可以维持在非常低的水平；G0提供的输入驱动信号的电位为高电压，T1关断；
在第三阶段S3，K0提供的控制时钟信号的电位由高电压拉低为低电压，打开T2，将N1的电位拉高，T01关闭，K1提供的第一时钟信号的电位的跳变无法影响G1提供的输出驱动信号的电压，G1维持输出低电压信号；
在第四阶段S4包括的至少部分时间段，K1提供的第一时钟信号的电位为低电压，当G1提供的输出驱动信号因为耦合或漏电等因素产生ripple(杂讯)，由于杂讯的存在会导致K1提供的第一时钟信号的电位为低电压时T02打开，并释放掉杂讯，使得G1能够维持输出低电压信号；
在第四阶段S4包括的至少部分时间段，K1提供的第一时钟信号的电位为低电压，当G1提供的输出驱动信号不存在杂讯时，G1维持输出低电压信 号，T02关断。
如图11所示，本发明至少一实施例所述的驱动电路可以包括第一控制电路11、第二控制电路12、储能电路13、第一输出电路14和第二输出电路15，其中，
所述第一控制电路11包括第一晶体管T1；
T1的栅极和T1的源极都与所述输入驱动信号端G0电连接，T1的漏极与第一节点N1电连接；
所述第二控制电路12包括第二晶体管T2；
T2的栅极与所述控制时钟信号端K0电连接，T2的源极与高电压端V01电连接，T2的漏极与第一节点N1电连接；
所述储能电路13包括存储电容C3，所述第一输出电路14包括第一输出晶体管T01；
所述存储电容C3的第一端与所述第一节点N1电连接，所述存储电容C3的第二端与所述输出驱动信号端G1电连接；
所述第一输出晶体管T01的栅极与所述第一节点N1电连接，所述第一输出晶体管T01的源极与所述输出驱动信号端G1电连接，所述第一输出晶体管T01的漏极与所述第一时钟信号端K1电连接；
所述第二输出电路15包括第二输出晶体管T02；
所述第二输出晶体管T02的栅极和所述第二输出晶体管T02的源极都与所述第一时钟信号端K1电连接，所述第二输出晶体管T02的漏极与所述输出驱动信号端G1电连接。
在图11所示的驱动电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
如图6所示，如图11所示的驱动电路的至少一实施例在工作时，驱动周期包括依次设置的第一阶段S1、第二阶段S2、第三阶段S3和第四阶段S4；
在第一阶段S1，K0提供的控制时钟信号的电位为高电压，T2关断，G0提供的输入驱动信号的电位为低电压，T1打开，此时N1的电位为低电压，T01打开，K1提供的第一时钟信号的电位为高电压，G1输出高电压信号；
在第二阶段S2，K1提供的第一时钟信号的电位由高电压被拉低为低电 压，T01打开，G1输出低电压信号，通过C3的自举作用，N1的电位进一步被拉低，T01充分打开，G1提供的输出驱动信号的电位可以维持在非常低的水平；G0提供的输入驱动信号的电位为高电压，T1关断；
在第三阶段S3，K0提供的控制时钟信号的电位由高电压拉低为低电压，打开T2，将N1的电位拉高，T01关闭，K1提供的第一时钟信号的电位的跳变无法影响G1提供的输出驱动信号的电压，G1维持输出低电压信号；
在第四阶段S4包括的至少部分时间段，K1提供的第一时钟信号的电位为低电压，当G1提供的输出驱动信号因为耦合或漏电等因素产生ripple(杂讯)，由于杂讯的存在会导致K1提供的第一时钟信号的电位为低电压时T02打开，并释放掉杂讯，使得G1能够维持输出低电压信号；
在第四阶段S4包括的至少部分时间段，K1提供的第一时钟信号的电位为低电压，当G1提供的输出驱动信号不存在杂讯时，G1维持输出低电压信号，T02关断。
如图12所示，本发明至少一实施例所述的驱动电路可以包括第一控制电路11、第二控制电路12、储能电路13、第一输出电路14、第二输出电路15和第三输出电路30，其中，
所述第一控制电路11包括第一晶体管T1；
T1的栅极与第二时钟信号端K2电连接，T1的源极与所述输入驱动信号端G0电连接，T1的漏极与第一节点N1电连接；
所述第二控制电路12包括第二晶体管T2；
T2的栅极与所述控制时钟信号端K0电连接，T2的源极与高电压端V01电连接，T2的漏极与第一节点N1电连接；
所述储能电路13包括存储电容C3，所述第一输出电路14包括第一输出晶体管T01；
所述存储电容C3的第一端与所述第一节点N1电连接，所述存储电容C3的第二端与所述输出驱动信号端G1电连接；
所述第一输出晶体管T01的栅极与所述第一节点N1电连接，所述第一输出晶体管T01的源极与所述输出驱动信号端G1电连接，所述第一输出晶体管T01的漏极与所述第一时钟信号端K1电连接；
所述第二输出电路15包括第二输出晶体管T02；
所述第二输出晶体管T02的栅极与所述第一时钟信号端K1电连接，所述第二输出晶体管T02的源极与低电压端V02电连接，所述第二输出晶体管T02的漏极与所述输出驱动信号端G1电连接；
所述第三输出电路30包括第三输出晶体管T03；
所述第三输出晶体管T03的栅极与所述输入驱动信号端G0电连接，所述第三输出晶体管T03的源极与高电压端V01电连接，所述第三输出晶体管T03的漏极与所述输出驱动信号端G1电连接。
在图12所示的驱动电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
图12所示的驱动电路的至少一实施例与图5所示的驱动电路的至少一实施例的区别在于：增加了T03。
图12所示的驱动电路的至少一实施例在工作时，当G0提供的输入驱动信号的电位为低电压时，T03打开，使得G1与V01之间连通；当G0提供的输入驱动信号的电位为高电压时，T03关断。
如图13所示，本发明至少一实施例所述的驱动电路可以包括第一控制电路11、第二控制电路12、储能电路13、第一输出电路14、第二输出电路15和第三输出电路30，其中，
所述第一控制电路11包括第一晶体管T1；
T1的栅极与第二时钟信号端K2电连接，T1的源极与所述输入驱动信号端G0电连接，T1的漏极与第一节点N1电连接；
所述第二控制电路12包括第二晶体管T2；
T2的栅极与所述控制时钟信号端K0电连接，T2的源极与高电压端V01电连接，T2的漏极与第一节点N1电连接；
所述储能电路13包括存储电容C3，所述第一输出电路14包括第一输出晶体管T01；
所述存储电容C3的第一端与所述第一节点N1电连接，所述存储电容C3的第二端与所述输出驱动信号端G1电连接；
所述第一输出晶体管T01的栅极与所述第一节点N1电连接，所述第一 输出晶体管T01的源极与所述输出驱动信号端G1电连接，所述第一输出晶体管T01的漏极与所述第一时钟信号端K1电连接；
所述第二输出电路15包括第二输出晶体管T02；
所述第二输出晶体管T02的栅极和所述第二输出晶体管T02的源极都与所述第一时钟信号端K1电连接，所述第二输出晶体管T02的漏极与所述输出驱动信号端G1电连接；
所述第三输出电路30包括第三输出晶体管T03；
所述第三输出晶体管T03的栅极与所述输入驱动信号端G0电连接，所述第三输出晶体管T03的源极与高电压端V01电连接，所述第三输出晶体管T03的漏极与所述输出驱动信号端G1电连接。
在图13所示的驱动电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
图13所示的驱动电路的至少一实施例与图9所示的驱动电路的至少一实施例的区别在于：增加了T03。
图13所示的驱动电路的至少一实施例在工作时，当G0提供的输入驱动信号的电位为低电压时，T03打开，使得G1与V01之间连通；当G0提供的输入驱动信号的电位为高电压时，T03关断。
如图14所示，本发明至少一实施例所述的驱动电路可以包括第一控制电路11、第二控制电路12、储能电路13、第一输出电路14、第二输出电路15和第三输出电路30，其中，
所述第一控制电路11包括第一晶体管T1；
T1的栅极和T1的源极都与输入驱动信号端G1电连接，T1的漏极与第一节点N1电连接；
所述第二控制电路12包括第二晶体管T2；
T2的栅极与所述控制时钟信号端K0电连接，T2的源极与高电压端V01电连接，T2的漏极与第一节点N1电连接；
所述储能电路13包括存储电容C3，所述第一输出电路14包括第一输出晶体管T01；
所述存储电容C3的第一端与所述第一节点N1电连接，所述存储电容 C3的第二端与所述输出驱动信号端G1电连接；
所述第一输出晶体管T01的栅极与所述第一节点N1电连接，所述第一输出晶体管T01的源极与所述输出驱动信号端G1电连接，所述第一输出晶体管T01的漏极与所述第一时钟信号端K1电连接；
所述第二输出电路15包括第二输出晶体管T02；
所述第二输出晶体管T02的栅极与所述第一时钟信号端K1电连接，所述第二输出晶体管T02的源极与低电压端V02电连接，所述第二输出晶体管T02的漏极与所述输出驱动信号端G1电连接；
所述第三输出电路30包括第三输出晶体管T03；
所述第三输出晶体管T03的栅极与所述输入驱动信号端G0电连接，所述第三输出晶体管T03的源极与高电压端V01电连接，所述第三输出晶体管T03的漏极与所述输出驱动信号端G1电连接。
在图14所示的驱动电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
图14所示的驱动电路的至少一实施例与图10所示的驱动电路的至少一实施例的区别在于：增加了T03。
图14所示的驱动电路的至少一实施例在工作时，当G0提供的输入驱动信号的电位为低电压时，T03打开，使得G1与V01之间连通；当G0提供的输入驱动信号的电位为高电压时，T03关断。
如图15所示，本发明至少一实施例所述的驱动电路可以包括第一控制电路11、第二控制电路12、储能电路13、第一输出电路14、第二输出电路15和第三输出电路30，其中，
所述第一控制电路11包括第一晶体管T1；
T1的栅极和T1的源极都与所述输入驱动信号端G0电连接，T1的漏极与第一节点N1电连接；
所述第二控制电路12包括第二晶体管T2；
T2的栅极与所述控制时钟信号端K0电连接，T2的源极与高电压端V01电连接，T2的漏极与第一节点N1电连接；
所述储能电路13包括存储电容C3，所述第一输出电路14包括第一输出 晶体管T01；
所述存储电容C3的第一端与所述第一节点N1电连接，所述存储电容C3的第二端与所述输出驱动信号端G1电连接；
所述第一输出晶体管T01的栅极与所述第一节点N1电连接，所述第一输出晶体管T01的源极与所述输出驱动信号端G1电连接，所述第一输出晶体管T01的漏极与所述第一时钟信号端K1电连接；
所述第二输出电路15包括第二输出晶体管T02；
所述第二输出晶体管T02的栅极和所述第二输出晶体管T02的源极都与所述第一时钟信号端K1电连接，所述第二输出晶体管T02的漏极与所述输出驱动信号端G1电连接；
所述第三输出电路30包括第三输出晶体管T03；
所述第三输出晶体管T03的栅极与所述输入驱动信号端G0电连接，所述第三输出晶体管T03的源极与高电压端V01电连接，所述第三输出晶体管T03的漏极与所述输出驱动信号端G1电连接。
在图15所示的驱动电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
图15所示的驱动电路的至少一实施例与图11所示的驱动电路的至少一实施例的区别在于：增加了T03。
图15所示的驱动电路的至少一实施例在工作时，当G0提供的输入驱动信号的电位为低电压时，T03打开，使得G1与V01之间连通；当G0提供的输入驱动信号的电位为高电压时，T03关断。
如图16所示，用于生成低电压有效的驱动信号的信号生成电路的至少一实施例包括第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第一电容C1和第二电容C2，其中，
T9的栅极与第一时钟信号端K1电连接，T9的源极与输入端I1电连接，T9的漏极与第二节点N2电连接；
T10的栅极与第二节点N2电连接，T10的源极与第一时钟信号端K1电连接，T10的漏极与第三节点N3电连接；
T3的栅极与第一时钟信号端K1电连接，T3的源极与低电压端V02电连接，T3的漏极与第三节点N3电连接；
T4的栅极与第三节点N3电连接，T4的源极与高电压端V01电连接，T4的漏极与输入驱动信号端G0电连接；
T5的栅极与第四节点N4电连接，T5的源极与第二时钟信号端K2电连接，T5的漏极与所述输入驱动信号端G0电连接；
T6的栅极与所述第三节点N3电连接，T6的源极与高电压端V01电连接，T6的漏极与T7的源极电连接；
T7的栅极与第二时钟信号端K2电连接，T7的漏极与所述第二节点N2电连接；
T8的栅极与低电压端V02电连接，T8的源极与第二节点N2电连接，T8的漏极与第四节点N4电连接；
C1的第一端与第四节点N4电连接，C1的第二端与所述输入驱动信号端G0电连接；
C2的第一端与所述第三节点N3电连接，C2的第二端与高电压端V02电连接。
在图16所示的信号生成电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
如图17所示，相关的LTPO像素电路的至少一实施例可以包括第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17、电容C0和有机发光二极管O1；
T11的栅极与初始控制端I0电连接，T11的源极与初始化电压端V0电连接，T11的漏极与T13的栅极电连接；
T12的栅极与输出驱动信号端G1电连接，T12的源极与T13的栅极电连接，T12的漏极与T13的漏极电连接；
T14的栅极与输入驱动信号端G0电连接，T14的源极与数据线D1电连接，T14的漏极与T13的源极电连接；
T15的栅极与发光控制信号端E1电连接，T15的源极与电源电压端E0 电连接，T15的漏极与T13的源极电连接；
T16的栅极与所述发光控制信号端E1电连接，T16的源极与T13的漏极电连接，T16的漏极与O1的阳极电连接；O1的阴极接入低电压信号V3；
T17的栅极与输入驱动信号端G0电连接，T17的源极与所述初始化电压端V0电连接，T17的漏极与O1的阳极电连接；
C0的第一端与所述电源电压端E0电连接，C0的第二端与T13的栅极电连接。
在图17所示的LTPO像素电路的至少一实施例中，T11和T12都为n型薄膜晶体管，T13、T14、T15、T16和T17都为p型薄膜晶体管。
在图17所示的LTPO像素电路的至少一实施例中，I0与相邻前一级输出驱动信号端电连接，所述输入驱动信号为低电平有效的栅极驱动信号，输出驱动信号为高电平有效的栅极驱动信号，所述发光控制信号端E1用于提供发光控制信号。
图18是图17所示的LTPO像素电路的至少一实施例的工作时序图。
本发明实施例所述的驱动方法，应用于上述的驱动电路，驱动周期包括依次设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
在第一阶段，第一控制电路根据所述输入驱动信号端提供的输入驱动信号，控制第一节点的电位，以使得第一输出电路在所述第一节点的电位的控制下，控制输出驱动信号端与第一时钟信号端之间连通；
在第二阶段，储能电路控制改变第一节点的电位，第一输出电路继续在所述第一节点的电位的控制下，控制输出驱动信号端与第一时钟信号端之间连通；
在第三阶段，第二控制电路在控制时钟信号的控制下，控制所述第一节点与所述第一电压端之间连通，以使得第一输出电路在所述第一节点的电位的控制下，控制输出驱动信号端与第一时钟信号端之间断开。
本发明实施例所述的驱动电路可以将输入驱动信号转换为输出驱动信号，其中，所述输入驱动信号为低电平有效的栅极驱动信号，所述输出驱动信号为高电平有效的栅极驱动信号。
在本发明至少一实施例中，驱动周期还包括设置于所述第三阶段之后的 第四阶段，所述驱动方法还包括：
在第四阶段包括的至少部分时间段，所述第二输出电路根据第一时钟信号，控制所述输出驱动信号端提供的输出驱动信号为无效电压信号。
可选的，所述驱动电路还包括第三输出电路；本发明至少一实施例所述的驱动方法还包括：
在第一阶段，第三输出电路在所述输入驱动信号的控制下，控制所述输出驱动信号端与第一电压端之间连通。
可选的，所述第一电压端为高电压端。
本发明至少一实施例采用第三输出电路，能够在所述输入驱动信号的电位为低电压时，控制输出驱动信号端与第一电压端之间连通，保证此时输出驱动信号的电位为高电压。
可选的，Δt1大于第一时钟信号的下降时间t1、控制时钟信号的下降时间t01与第一间隔时间m1的和值，并且，Δt1小于w1-t2-t02-m2，以使得第一时钟信号的电位完全下降为低电压之后，控制时钟信号的电位才开始由高电压下降为低电压；
其中，Δt1为所述第一时钟信号的下降沿与所述控制时钟信号的下降沿之间的时间差，w1为所述第一时钟信号的电位持续为低电压的时间，t2为所述第一时钟信号的上升时间，t02为所述控制时钟信号的上升时间，m2为第二间隔时间。
本发明实施例所述的显示装置包括上述的驱动电路。
在本发明实施例所述的显示装置中，当为奇数行像素电路提供输出驱动信号的驱动电路的控制时钟信号端与第三时钟信号端电连接时，为偶数行像素电路提供输出驱动信号的驱动电路的控制时钟信号端与第四时钟信号端电连接。
图19是第一时钟信号端K1提供的第一时钟信号、第二时钟信号端K2提供的第二时钟信号、第三时钟信号端K3提供的第三时钟信号和第四时钟信号端K4提供的第四时钟信号的时序图。
如图19所示，K1提供的第一时钟信号的下降沿与K3提供的第三时钟信号的下降沿之间的时间差为Δt1，K2提供的第二时钟信号的下降沿和与K4 提供的第四时钟信号的下降沿之间的时间差为Δt2；
Δt2需要满足以下要求：
Δt2大于第二时钟信号的下降时间t3、第四时钟信号的下降时间t03与第一间隔时间m1的和值，并且，Δt2小于w2-t4-t04-m2；
其中，w2为第二时钟信号的电位持续为低电压的时间，t4为第二时钟信号的上升时间，t04为第四时钟信号的上升时间，m2为第二间隔时间；m1和m2可以基于显示产品性能进行调整。
通过以上Δt2的限定，能够使得第二时钟信号的电位完全下降为低电压之后，第四时钟信号的电位才开始由高电压下降为低电压。
本发明实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (16)

  1. 一种驱动电路，包括：第一控制电路、第二控制电路、储能电路、第一输出电路和第二输出电路，其中，
    所述储能电路的第一端与第一节点电连接，所述储能电路的第二端与输出驱动信号端电连接，所述储能电路用于储存电能；
    所述第一控制电路分别与输入驱动信号端和第一节点电连接，用于根据所述输入驱动信号端提供的输入驱动信号，控制第一节点的电位；
    所述第二控制电路分别与控制时钟信号端、第一电压端和所述第一节点电连接，用于在所述控制时钟信号端提供的控制时钟信号的控制下，控制所述第一节点与所述第一电压端之间连通；
    所述第一输出电路分别与所述第一节点、第一时钟信号端和输出驱动信号端电连接，用于在第一节点的电位的控制下，控制所述输出驱动信号端与所述第一时钟信号端之间连通；
    所述第二输出电路分别与所述第一时钟信号端与所述输出驱动信号端电连接，用于根据所述第一时钟信号端提供的第一时钟信号，控制所述输出驱动信号端提供输出驱动信号。
  2. 如权利要求1所述的驱动电路，其中，所述第一控制电路还与第二时钟信号端电连接，具体用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述输入驱动信号端与所述第一节点之间连通。
  3. 如权利要求1所述的驱动电路，其中，所述第二输出电路还与第二电压端电连接，用于在所述第一时钟信号的控制下，控制所述输出驱动信号端与所述第二电压端之间连通。
  4. 如权利要求1所述的驱动电路，其中，还包括第三输出电路；
    所述第三输出电路分别与所述输入驱动信号端、所述第一电压端和所述输出驱动信号端电连接，用于在所述输入驱动信号的控制下，控制所述输出驱动信号端与所述第一电压端之间连通。
  5. 如权利要求1所述的驱动电路，其中，所述第一控制电路包括第一晶体管；
    所述第一晶体管的控制极与所述第一晶体管的第一极都与所述输入驱动信号端电连接，所述第一晶体管的第二极与所述第一节点电连接。
  6. 如权利要求2所述的驱动电路，其中，所述第一控制电路包括第一晶体管；
    所述第一晶体管的控制极与所述第二时钟信号端电连接，所述第一晶体管的第一极与所述输入驱动信号端电连接，所述第一晶体管的第二极与所述第一节点电连接。
  7. 如权利要求1至6中任一权利要求所述的驱动电路，其中，所述第二控制电路包括第二晶体管；
    所述第二晶体管的控制极与所述控制时钟信号端电连接，所述第二晶体管的第一极与所述第一电压端电连接，所述第二晶体管的第二极与第一节点电连接。
  8. 如权利要求1至6中任一权利要求所述的驱动电路，其中，所述储能电路包括存储电容，所述第一输出电路包括第一输出晶体管；
    所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与所述输出驱动信号端电连接；
    所述第一输出晶体管的控制极与所述第一节点电连接，所述第一输出晶体管的第一极与所述输出驱动信号端电连接，所述第一输出晶体管的第二极与所述第一时钟信号端电连接。
  9. 如权利要求1所述的驱动电路，其中，所述第二输出电路包括第二输出晶体管；
    所述第二输出晶体管的控制极与所述第二输出晶体管的第一极都与所述第一时钟信号端电连接，所述第二输出晶体管的第二极与所述输出驱动信号端电连接。
  10. 如权利要求3所述的驱动电路，其中，所述第二输出电路包括第二输出晶体管；
    所述第二输出晶体管的控制极与所述第一时钟信号端电连接，所述第二输出晶体管的第一极与所述第二电压端电连接，所述第二输出晶体管的第二极与所述输出驱动信号端电连接。
  11. 如权利要求4所述的驱动电路，其中，所述第三输出电路包括第三输出晶体管；
    所述第三输出晶体管的控制极与所述输入驱动信号端电连接，所述第三输出晶体管的第一极与所述第一电压端电连接，所述第三输出晶体管的第二极与所述输出驱动信号端电连接。
  12. 一种驱动方法，应用于如权利要求1至11中任一权利要求所述的驱动电路，驱动周期包括依次设置的第一阶段、第二阶段和第三阶段；所述驱动方法包括：
    在第一阶段，第一控制电路根据所述输入驱动信号端提供的输入驱动信号，控制第一节点的电位，以使得第一输出电路在所述第一节点的电位的控制下，控制输出驱动信号端与第一时钟信号端之间连通；
    在第二阶段，储能电路控制改变第一节点的电位，第一输出电路继续在所述第一节点的电位的控制下，控制输出驱动信号端与第一时钟信号端之间连通；
    在第三阶段，第二控制电路在控制时钟信号的控制下，控制所述第一节点与所述第一电压端之间连通，以使得第一输出电路在所述第一节点的电位的控制下，控制输出驱动信号端与第一时钟信号端之间断开。
  13. 如权利要求12所述的驱动方法，其中，驱动周期还包括设置于所述第三阶段之后的第四阶段，所述驱动方法还包括：
    在第四阶段包括的至少部分时间段，所述第二输出电路根据第一时钟信号，控制所述输出驱动信号端提供的输出驱动信号为无效电压信号。
  14. 如权利要求12或13所述的驱动方法，其中，所述驱动电路还包括第三输出电路；所述驱动方法还包括：
    在第一阶段，第三输出电路在所述输入驱动信号的控制下，控制所述输出驱动信号端与第一电压端之间连通。
  15. 如权利要求12或13所述的驱动方法，其中，Δt1大于第一时钟信号的下降时间t1、控制时钟信号的下降时间t01与第一间隔时间m1的和值，并且，Δt1小于w1-t2-t02-m2；
    其中，Δt1为所述第一时钟信号的下降沿与所述控制时钟信号的下降沿 之间的时间差，w1为所述第一时钟信号的电位持续为低电压的时间，t2为所述第一时钟信号的上升时间，t02为所述控制时钟信号的上升时间，m2为第二间隔时间。
  16. 一种显示装置，包括如权利要求1至11中任一权利要求所述的驱动电路。
PCT/CN2021/129599 2021-03-15 2021-11-09 驱动电路、驱动方法和显示装置 WO2022193685A1 (zh)

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