WO2023092304A1 - 驱动电路、驱动模组、驱动方法和显示装置 - Google Patents

驱动电路、驱动模组、驱动方法和显示装置 Download PDF

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Publication number
WO2023092304A1
WO2023092304A1 PCT/CN2021/132572 CN2021132572W WO2023092304A1 WO 2023092304 A1 WO2023092304 A1 WO 2023092304A1 CN 2021132572 W CN2021132572 W CN 2021132572W WO 2023092304 A1 WO2023092304 A1 WO 2023092304A1
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Prior art keywords
terminal
control
output
transistor
electrically connected
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PCT/CN2021/132572
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English (en)
French (fr)
Inventor
范龙飞
卢鹏程
Original Assignee
京东方科技集团股份有限公司
云南创视界光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 云南创视界光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180003538.6A priority Critical patent/CN116982103A/zh
Priority to PCT/CN2021/132572 priority patent/WO2023092304A1/zh
Priority to US17/926,959 priority patent/US20240242649A1/en
Publication of WO2023092304A1 publication Critical patent/WO2023092304A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving module, a driving method and a display device.
  • an embodiment of the present disclosure provides a driving circuit, including a driving signal output terminal, a first node control circuit, an on-off control circuit, and a first output circuit;
  • the first node control circuit is respectively electrically connected to the first control terminal, the first voltage terminal, the first node, the second output control terminal and the first clock signal terminal, for Under the control of the first control signal provided, control the disconnection or connection between the first node and the first voltage terminal, and under the control of the first clock signal provided by the first clock signal terminal, control the The first node is connected or disconnected from the first voltage terminal; the first control terminal is different from the first clock signal terminal;
  • the on-off control circuit is electrically connected to the second voltage terminal, the first node and the first output control terminal, and is used to control the first voltage signal under the control of the second voltage signal provided by the second voltage terminal.
  • a node is connected or disconnected from the first output control terminal;
  • the first output circuit is electrically connected to the first output control terminal, the first clock signal terminal and the drive signal output terminal, and is used to control the output of the drive signal under the control of the potential of the first output control terminal.
  • the terminal is connected or disconnected from the first clock signal terminal.
  • the transistors included in the first node control circuit are all p-type transistors; or, the transistors included in the first node control circuit are all n-type transistors;
  • the first control signal and the first clock signal are opposite to each other.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second output control terminal control circuit and a second output circuit;
  • the second output control terminal control circuit is electrically connected to the first node, the second output control terminal, the second clock signal terminal and the second voltage terminal, and is used for controlling the potential of the first node control the connection or disconnection between the second output control terminal and the second clock signal terminal, and control the second output control terminal under the control of the second clock signal provided by the second clock signal terminal. connected or disconnected between the terminal and the second voltage terminal;
  • the second output circuit is electrically connected to the second output control terminal, the first voltage terminal and the drive signal output terminal respectively, and is used to control the drive signal output terminal under the control of the potential of the second output control terminal. connected to or disconnected from the first voltage terminal.
  • the first node control circuit is also electrically connected to the second output control terminal, the second clock signal terminal and the input terminal, and is used to control the second output control terminal under the control of the potential of the second output control terminal.
  • a node is connected or disconnected from the first voltage terminal, and is used to control the connection between the first node and the input terminal under the control of the second clock signal provided by the second clock signal terminal or disconnect.
  • the first node control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor;
  • the control pole of the first transistor is electrically connected to the second clock signal terminal, the first pole of the first transistor is electrically connected to the input terminal, and the second pole of the first transistor is electrically connected to the first node electrical connection;
  • the control electrode of the second transistor is electrically connected to the first clock signal terminal, and the first electrode of the second transistor is electrically connected to the first node;
  • the control pole of the third transistor is electrically connected to the second output control terminal, the first pole of the third transistor is electrically connected to the second pole of the second transistor, and the second pole of the third transistor electrically connected to the first voltage terminal;
  • the first voltage terminal is electrically connected to the second pole of the third transistor through the fourth transistor; or, the first pole of the third transistor is connected to the first pole of the second transistor through the fourth transistor.
  • the two poles are electrically connected; or, the first pole of the second transistor is electrically connected to the first node through the fourth transistor;
  • the control electrode of the fourth transistor is electrically connected to the first control terminal.
  • the first node control circuit is also electrically connected to the second output control terminal, the second clock signal terminal and the input terminal, and is used to control the second output control terminal under the control of the potential of the second output control terminal.
  • a node is connected or disconnected from the first voltage terminal, and is used to control the connection between the first node and the second clock signal under the control of the first control signal and the second clock signal provided by the second clock signal terminal. The input ends are connected or disconnected.
  • the first node control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor;
  • the control pole of the first transistor is electrically connected to the second clock signal terminal, the first pole of the first transistor is electrically connected to the input terminal, and the second pole of the first transistor is electrically connected to the second clock signal terminal. node electrical connection;
  • the control electrode of the second transistor is electrically connected to the first clock signal terminal, and the first electrode of the second transistor is electrically connected to the second node;
  • the control pole of the third transistor is electrically connected to the second output control terminal, the first pole of the third transistor is electrically connected to the second pole of the second transistor, and the second pole of the third transistor electrically connected to the first voltage terminal;
  • the control pole of the fourth transistor is electrically connected to the first control terminal, the first pole of the fourth transistor is electrically connected to the second node, and the second pole of the fourth transistor is electrically connected to the first node.
  • the nodes are electrically connected.
  • the fourth transistor is a double-gate transistor.
  • the aspect ratio of the fourth transistor is equal to the aspect ratio of the second transistor.
  • the drive circuit described in at least one embodiment of the present disclosure further includes a first energy storage circuit and a second energy storage circuit;
  • the first energy storage circuit is electrically connected to the first output control terminal for storing electric energy
  • the second energy storage circuit is electrically connected to the second output control terminal for storing electric energy.
  • the first energy storage circuit includes a first capacitor
  • the second energy storage circuit includes a second capacitor
  • the first terminal of the second capacitor is electrically connected to the second output control terminal, and the second terminal of the second capacitor is electrically connected to the first voltage terminal;
  • a first end of the first capacitor is electrically connected to the first output control end, and a second end of the first capacitor is electrically connected to the driving signal output end.
  • the second output control terminal control circuit includes a fifth transistor and a sixth transistor;
  • the control pole of the fifth transistor is electrically connected to the second clock signal terminal, the first pole of the fifth transistor is electrically connected to the second voltage terminal, and the second pole of the fifth transistor is electrically connected to the The second output control terminal is electrically connected;
  • the control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the first node.
  • the two output control terminals are electrically connected.
  • the on-off control circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the second voltage terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the first node.
  • the output control terminal is electrically connected.
  • the first output circuit includes a first output transistor
  • the second output circuit includes a second output transistor
  • the control pole of the first output transistor is electrically connected to the first output control terminal, the first pole of the first output transistor is electrically connected to the first clock signal terminal, and the second The pole is electrically connected to the drive signal output end;
  • the control pole of the second output transistor is electrically connected to the second output control terminal, the first pole of the second output transistor is electrically connected to the first voltage terminal, and the second pole of the second output transistor It is electrically connected with the driving signal output end.
  • the aspect ratio of the first output transistor is greater than the aspect ratio of the second output transistor.
  • an embodiment of the present disclosure further provides a driving module, including multiple stages of the above-mentioned driving circuits.
  • the embodiment of the present disclosure also provides a driving method, which is applied to the above-mentioned driving circuit, and the display cycle includes an output phase;
  • the driving method includes: in the output stage, the first node control circuit controls the disconnection between the first node and the first voltage terminal under the control of the first control signal, and the on-off control circuit controls the second voltage signal, Controlling the communication between the first node and the first output control terminal, the first output circuit controls the communication between the driving signal output terminal and the first clock signal terminal under the control of the potential of the first output control terminal.
  • the driving circuit further includes a second output control terminal control circuit and a second output circuit; the display period also includes an input phase set before the output phase; the driving method further includes:
  • the second output control terminal control circuit controls the connection between the second output control terminal and the second voltage terminal under the control of the second clock signal, so that the potential of the second output circuit at the second output control terminal Under the control of the control, the connection between the driving signal output terminal and the first voltage terminal is controlled;
  • the second output control terminal control circuit controls the connection between the second output control terminal and the second clock signal terminal under the control of the potential of the first node, so that the first The second output circuit controls the disconnection between the driving signal output terminal and the first voltage terminal under the control of the potential of the second output control terminal.
  • the first node control circuit is also electrically connected to the second clock signal terminal and the input terminal respectively;
  • the driving circuit further includes a first energy storage circuit and a second energy storage circuit;
  • the driving method further includes:
  • the input terminal provides an input signal
  • the first node control circuit controls the input terminal to provide the input signal to the first node under the control of the second clock signal
  • the on-off control circuit operates on the second Under the control of the second voltage signal provided by the voltage terminal, the communication between the first node and the first output control terminal is controlled to charge the first energy storage circuit, and the first output circuit is connected to the first output control terminal. Under the control of the potential, the communication between the drive signal output end and the first clock signal end is controlled.
  • the display period further includes a reset phase set after the output phase;
  • the reset phase includes a first reset time period and a second reset time period;
  • the driving method further includes:
  • the input terminal provides the first voltage signal, and the potential of the second clock signal provided by the second clock signal terminal is the second voltage; the first node control circuit controls the The first node is connected to the input terminal, so that the potential of the first node is a first voltage, and the on-off control circuit controls the second voltage signal provided by the second voltage terminal.
  • the first node communicates with the first output control terminal to charge the first energy storage circuit, so that the potential of the first output control terminal is a first voltage; Under the control of the potential of an output control terminal, control the disconnection between the drive signal output terminal and the first clock signal terminal; the second output control terminal control circuit controls the second output control terminal under the control of the second clock signal It is connected with the second voltage terminal to charge the second energy storage circuit, so that the potential of the second output control terminal is the second voltage, and the second output circuit is under the control of the potential of the second output control terminal , controlling the connection between the drive signal output terminal and the first voltage terminal;
  • the second energy storage circuit maintains the potential of the second output control terminal, and the second output circuit controls the drive signal output terminal and the first output terminal under the control of the potential of the second output control terminal.
  • One voltage terminal is connected; the first energy storage circuit maintains the potential of the first output control terminal, and the first output circuit controls the drive signal output terminal and the first clock signal terminal under the control of the first output control terminal disconnected between.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned pixel circuit.
  • FIG. 1 is a structural diagram of a driving circuit described in an embodiment of the present disclosure
  • Fig. 2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure
  • Fig. 3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Fig. 4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Fig. 5 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 6 is a working timing diagram of the driving circuit described in at least one embodiment of the present disclosure.
  • Fig. 7 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Fig. 8 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • Fig. 9 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 10 is a working sequence diagram of the driving module according to at least one embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the first pole when the transistor is a thin film transistor or a field effect transistor, the first pole may be a drain, and the second pole may be a source; or, the first pole may be a source, The second pole may be a drain.
  • the drive circuit described in the embodiment of the present disclosure includes a drive signal output terminal G1, a first node control circuit 11, an on-off control circuit 12, and a first output circuit 13;
  • the first node control circuit 11 is electrically connected to the first control terminal D1, the first voltage terminal V1, the first node N1 and the first clock signal terminal K1 respectively, for Under the control of the provided first control signal, control the disconnection or connection between the first node N1 and the first voltage terminal V1, and control the first clock signal provided at the first clock signal terminal K1 Next, control the connection or disconnection between the first node N1 and the first voltage terminal V1; the first control terminal D1 is different from the first clock signal terminal K1;
  • the on-off control circuit 12 is electrically connected to the second voltage terminal V2, the first node and the first output control terminal GT1 respectively, and is used for controlling the second voltage signal provided by the second voltage terminal V2, controlling the connection or disconnection between the first node N1 and the first output control terminal GT1;
  • the first output circuit 13 is electrically connected to the first output control terminal GT1, the first clock signal terminal K1, and the drive signal output terminal G1, respectively, for controlling the potential of the first output control terminal GT1, Controlling the connection or disconnection between the driving signal output terminal G1 and the first clock signal terminal K1.
  • the first voltage terminal may be a high voltage terminal
  • the second voltage terminal may be a low voltage terminal, but not limited thereto.
  • the second The first control signal provided by a control terminal D1 is different from the first clock signal provided by the first clock signal terminal K1, so that in the output stage, the first node control circuit 11 can control the first node N1 and the first node N1.
  • One voltage terminal is disconnected to prevent the potential of the first node N1 from being affected by the leakage current between the first node N1 and the first voltage terminal V1.
  • the display cycle includes an output stage
  • the first node control circuit 11 controls the disconnection between the first node N1 and the first voltage terminal
  • the on-off control circuit 12 controls the first node N1 under the control of the second voltage signal.
  • the node N1 is connected to the first output control terminal GT1
  • the first output circuit controls the communication between the driving signal output terminal G1 and the first clock signal terminal K1 under the control of the potential of the first output control terminal GT1 , so that the driving signal output terminal G1 can normally output the driving signal.
  • the driving circuit described in the embodiment of the present disclosure controls the disconnection between the first node N1 and the first voltage terminal V1 through the first node control circuit 11 in the output stage under the control of the first control signal, so as to avoid that in the output stage,
  • the potential of the first node N1 and the potential of the first output control terminal GT1 are the first voltage, so that in the output stage, the first output circuit 13 can control the
  • the driving signal output terminal G1 is connected to the first clock signal terminal K1 to normally output the driving signal.
  • the transistors included in the first node control circuit are all p-type transistors; or, the transistors included in the first node control circuit are all n-type transistors;
  • the first control signal and the first clock signal are opposite to each other.
  • the first control signal provided by the first control terminal and the first clock signal provided by the first clock signal terminal can be set to be mutually inverse, so that the gate electrode included in the first node control circuit is connected to The transistor of the first control signal and the transistor whose control electrode is connected to the first clock signal will not be turned on at the same time, so as to prevent the leakage current between the first node N1 and the first voltage terminal V1 from affecting the first Potential of node N1.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second output control terminal control circuit 21 and a second output circuit 22 ;
  • the second output control terminal control circuit 21 is electrically connected to the first node N1, the second output control terminal GT2, the second clock signal terminal K2 and the second voltage terminal V2 respectively, for Under the control of the potential of node N1, control the connection or disconnection between the second output control terminal GT2 and the second clock signal terminal K2, and control the second clock signal provided by the second clock signal terminal K2 Next, control the connection or disconnection between the second output control terminal GT2 and the second voltage terminal V2;
  • the second output circuit 22 is electrically connected to the second output control terminal GT2, the first voltage terminal V1 and the drive signal output terminal G1 respectively, and is used to control the potential of the second output control terminal GT2 under the control of the potential
  • the driving signal output terminal G1 is connected or disconnected from the first voltage terminal V1.
  • the first control terminal may be a third clock signal terminal, but not limited thereto.
  • the display cycle further includes an input phase arranged before the output phase;
  • the second output control terminal control circuit 21 controls the connection between the second output control terminal GT2 and the second voltage terminal V2 under the control of the second clock signal, so that the second output circuit 22 Under the control of the potential of the output control terminal GT2, control the connection between the driving signal output terminal G1 and the first voltage terminal V1;
  • the second output control terminal control circuit 21 controls the communication between the second output control terminal GT2 and the second clock signal terminal K2 under the control of the potential of the first node N1, so as to Under the control of the potential of the second output control terminal GT2, the second output circuit 22 controls the disconnection between the driving signal output terminal G1 and the first voltage terminal V1.
  • the second output control terminal control circuit 21 can control the communication between the second output control terminal GT2 and the second clock signal terminal K2 under the control of the potential of the first node N1, so as to control the second output circuit
  • the transistor included in 22 is turned off, so as to avoid affecting the driving signal output from the driving signal output terminal G1.
  • the first node control circuit may also be electrically connected to the second output control terminal, the second clock signal terminal and the input terminal, respectively, for controlling the potential of the second output control terminal control the connection or disconnection between the first node and the first voltage terminal, and control the connection between the first node and the first voltage terminal under the control of the second clock signal provided by the second clock signal terminal. connected or disconnected between the above-mentioned input terminals.
  • the driving circuit described in at least one embodiment of the present disclosure may further include a first energy storage circuit and a second energy storage circuit;
  • the first energy storage circuit is electrically connected to the first output control terminal for storing electric energy and maintaining the potential of the first output control terminal;
  • the second energy storage circuit is electrically connected to the second output control terminal for storing electric energy and maintaining the potential of the second output control terminal.
  • the first node control circuit 11 is also connected to the second output control terminal GT2, the second clock signal terminal K2 and the input terminal I1 is electrically connected, and is used to control the connection or disconnection between the first node N1 and the input terminal I1 under the control of the second clock signal provided by the second clock signal terminal K2, and at the second Under the control of the potential of the second output control terminal GT2, control the connection or disconnection between the first node N1 and the first voltage terminal V1;
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first energy storage circuit 41 and a second energy storage circuit 42 ;
  • the first energy storage circuit 41 is electrically connected to the first output control terminal GT1 for storing electric energy and maintaining the potential of the first output control terminal GT1;
  • the second energy storage circuit 42 is electrically connected to the second output control terminal GT2 for storing electric energy and maintaining the potential of the second output control terminal GT2.
  • the display cycle includes an input phase, an output phase, and a reset phase that are set successively;
  • the input terminal I1 provides an input signal
  • the first node control circuit 11 controls the input terminal I1 to provide the input signal to the first node N1 under the control of the second clock signal
  • the on-off control circuit 12 Under the control of the second voltage signal provided by the second voltage terminal V2
  • the connection between the first node N1 and the first output control terminal GT1 is controlled to charge the first energy storage circuit 41
  • the circuit 13 controls the connection between the drive signal output terminal G1 and the first clock signal terminal K1;
  • the input terminal I1 provides the first voltage signal
  • the potential of the second clock signal provided by the second clock signal terminal K2 is the second voltage
  • the first node control circuit 11 Under the control of the control, the connection between the first node N1 and the input terminal I1 is controlled, so that the potential of the first node N1 is the first voltage
  • the on-off control circuit 12 provides Under the control of the second voltage signal, control the connection between the first node N1 and the first output control terminal GT1 to charge the first energy storage circuit 41, so that the first output control terminal GT1
  • the potential is the first voltage
  • the first output circuit 13 controls the disconnection between the drive signal output terminal G1 and the first clock signal terminal K1 under the control of the potential of the first output control terminal GT1
  • the second Under the control of the second clock signal
  • the output control terminal control circuit 21 controls the connection between the second output control terminal GT2 and the second voltage terminal to charge the second energy storage circuit 42, so that the second The potential of the output control terminal GT2 is the second voltage
  • the second energy storage circuit 42 maintains the potential of the second output control terminal GT2, and the second output circuit 22 controls the
  • the drive signal output terminal G1 is connected to the first voltage terminal V1; the first energy storage circuit 41 maintains the potential of the first output control terminal GT1, and the first output circuit 13 is connected to the first output control terminal GT1. Under control, the drive signal output terminal G1 is controlled to be disconnected from the first clock signal terminal K1.
  • the first node control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor;
  • the control pole of the first transistor is electrically connected to the second clock signal terminal, the first pole of the first transistor is electrically connected to the input terminal, and the second pole of the first transistor is electrically connected to the first node electrical connection;
  • the control electrode of the second transistor is electrically connected to the first clock signal terminal, and the first electrode of the second transistor is electrically connected to the first node;
  • the control pole of the third transistor is electrically connected to the second output control terminal, the first pole of the third transistor is electrically connected to the second pole of the second transistor, and the second pole of the third transistor electrically connected to the first voltage terminal;
  • the first voltage terminal is electrically connected to the second pole of the third transistor through the fourth transistor; or, the first pole of the third transistor is connected to the first pole of the second transistor through the fourth transistor.
  • the two poles are electrically connected; or, the first pole of the second transistor is electrically connected to the first node through the fourth transistor;
  • the control electrode of the fourth transistor is electrically connected to the first control terminal.
  • the first node control circuit may also be electrically connected to the second output control terminal, the second clock signal terminal and the input terminal, respectively, for controlling the potential of the second output control terminal control the connection or disconnection between the first node and the first voltage terminal, and for controlling the first control signal and the second clock signal provided by the second clock signal terminal.
  • the first node is connected or disconnected from the input end.
  • the first node control circuit 11 is also connected to the second output control terminal GT2, the second clock signal terminal K2 and the input terminal I1 is electrically connected to control the connection or disconnection between the first node N1 and the first voltage terminal V1 under the control of the potential of the second output control terminal GT2, and is used to control the connection or disconnection between the first node N1 and the first voltage terminal V1, and is used to Under the control of the control signal and the second clock signal provided by the second clock signal terminal K2, control the connection or disconnection between the first node N1 and the input terminal I1;
  • the first node control circuit 11 may also be electrically connected to the second node N2, and the first node control circuit 11 is configured to be controlled by the second clock signal , to control the connection or disconnection between the input terminal I1 and the second node N2, and for controlling the connection between the second node N2 and the first node N1 under the control of the first control signal connected or disconnected;
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first energy storage circuit 41 and a second energy storage circuit 42 ;
  • the first energy storage circuit 41 is electrically connected to the first output control terminal GT1 for storing electric energy and maintaining the potential of the first output control terminal GT1;
  • the second energy storage circuit 42 is electrically connected to the second output control terminal GT2 for storing electric energy and maintaining the potential of the second output control terminal GT2.
  • the display cycle includes an input phase, an output phase, and a reset phase that are set successively;
  • the input terminal I1 provides an input signal
  • the first node control circuit 11 controls the input terminal I1 to provide the input signal to the second node N2 under the control of the second clock signal, and the first node
  • the control circuit 11 controls the communication between the second node N2 and the first node N1 under the control of the first control signal, so as to write the input signal into the first node N1
  • the on-off control circuit 12 Under the control of the second voltage signal provided by the second voltage terminal V2, the connection between the first node N1 and the first output control terminal GT1 is controlled to charge the first energy storage circuit 41, and the first output Under the control of the potential of the first output control terminal GT1, the circuit 13 controls the connection between the drive signal output terminal G1 and the first clock signal terminal K1;
  • the input terminal I1 provides the first voltage signal
  • the potential of the second clock signal provided by the second clock signal terminal K2 is the second voltage
  • the first node control circuit 11 Under the control of the second node N2 is controlled to communicate with the input terminal I1, and under the control of the first control signal, the second node N2 is controlled to be communicated with the first node N1, so that Make the potential of the first node N1 be the first voltage
  • the on-off control circuit 12 controls the first node N1 and the first output voltage under the control of the second voltage signal provided by the second voltage terminal V2.
  • the control terminals GT1 are connected to charge the first energy storage circuit 41, so that the potential of the first output control terminal GT1 is the first voltage; the first output circuit 13 is connected to the first output control terminal. Under the control of the potential of GT1, control the disconnection between the drive signal output terminal G1 and the first clock signal terminal K1; the second output control terminal control circuit 21 controls the second output control terminal under the control of the second clock signal.
  • Terminal GT2 is connected with the second voltage terminal to charge the second energy storage circuit 42, so that the potential of the second output control terminal GT2 is the second voltage, and the second output circuit 22 is at the second output Under the control of the potential of the control terminal GT2, control the connection between the drive signal output terminal G1 and the first voltage terminal V1;
  • the second energy storage circuit 42 maintains the potential of the second output control terminal GT2, and the second output circuit 22 controls the
  • the drive signal output terminal G1 is connected to the first voltage terminal V1; the first energy storage circuit 41 maintains the potential of the first output control terminal GT1, and the first output circuit 13 is connected to the first output control terminal GT1. Under control, the drive signal output terminal G1 is controlled to be disconnected from the first clock signal terminal K1.
  • the first node control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor;
  • the control pole of the first transistor is electrically connected to the second clock signal terminal, the first pole of the first transistor is electrically connected to the input terminal, and the second pole of the first transistor is electrically connected to the second clock signal terminal. node electrical connection;
  • the control electrode of the second transistor is electrically connected to the first clock signal terminal, and the first electrode of the second transistor is electrically connected to the second node;
  • the control pole of the third transistor is electrically connected to the second output control terminal, the first pole of the third transistor is electrically connected to the second pole of the second transistor, and the second pole of the third transistor electrically connected to the first voltage terminal;
  • the control pole of the fourth transistor is electrically connected to the first control terminal, the first pole of the fourth transistor is electrically connected to the second node, and the second pole of the fourth transistor is electrically connected to the first node.
  • the nodes are electrically connected.
  • the fourth transistor may be a double-gate transistor to further reduce leakage current.
  • the width-to-length ratio of the fourth transistor may be equal to the width-to-length ratio of the second transistor.
  • both the fourth transistor and the second transistor are switch transistors, and the width-to-length ratio of the fourth transistor and the width-to-length ratio of the second transistor may be equal to facilitate design.
  • the width-to-length ratio of the fourth transistor may not be equal to the width-to-length ratio of the second transistor.
  • the first energy storage circuit includes a first capacitor
  • the second energy storage circuit includes a second capacitor
  • the first terminal of the second capacitor is electrically connected to the second output control terminal, and the second terminal of the second capacitor is electrically connected to the first voltage terminal;
  • a first end of the first capacitor is electrically connected to the first output control end, and a second end of the first capacitor is electrically connected to the driving signal output end.
  • the second output control terminal control circuit includes a fifth transistor and a sixth transistor;
  • the control pole of the fifth transistor is electrically connected to the second clock signal terminal, the first pole of the fifth transistor is electrically connected to the second voltage terminal, and the second pole of the fifth transistor is electrically connected to the The second output control terminal is electrically connected;
  • the control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the first node.
  • the two output control terminals are electrically connected.
  • the on-off control circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the second voltage terminal, the first electrode of the seventh transistor is electrically connected to the first node, and the second electrode of the seventh transistor is electrically connected to the first node.
  • the output control terminal is electrically connected.
  • the first output circuit includes a first output transistor
  • the second output circuit includes a second output transistor
  • the control pole of the first output transistor is electrically connected to the first output control terminal, the first pole of the first output transistor is electrically connected to the first clock signal terminal, and the second The pole is electrically connected to the drive signal output end;
  • the control pole of the second output transistor is electrically connected to the second output control terminal, the first pole of the second output transistor is electrically connected to the first voltage terminal, and the second pole of the second output transistor It is electrically connected with the driving signal output end.
  • the aspect ratio of the first output transistor is greater than the aspect ratio of the second output transistor.
  • the first output transistor and the second output transistor are used to control the output driving signal.
  • the aspect ratio of the first output transistor and the second output transistor The width-to-length ratio of the transistors is very large. Since the first output transistor is used to output low-voltage signals, and it is more difficult to output low-voltage signals, the width-to-length ratio of the first output transistor can be greater than that of the second output transistor. The width-to-length ratio of the output transistors to ensure drive capability.
  • the first node control circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;
  • the gate of the first transistor M1 is electrically connected to the second clock signal terminal K2, the source of the first transistor M1 is electrically connected to the input terminal I1, and the drain of the first transistor M1 is electrically connected to the second clock signal terminal K2.
  • the first node N1 is electrically connected;
  • the gate of the second transistor M2 is electrically connected to the first clock signal terminal K1, the source of the second transistor M2 is electrically connected to the first node N1; the drain of the second transistor M2 is electrically connected to the first node N1.
  • the source of the fourth transistor M4 is electrically connected;
  • the gate of the fourth transistor M4 is electrically connected to the third clock signal terminal K3, and the drain of the fourth transistor M4 is electrically connected to the source of the third transistor M3;
  • the gate of the third transistor M3 is electrically connected to the second output control terminal GT2, and the drain of the third transistor M3 is electrically connected to a high voltage terminal; the high voltage terminal is used to provide a high voltage signal V01;
  • the first energy storage circuit 41 includes a first capacitor C1, and the second energy storage circuit 42 includes a second capacitor C2;
  • the first terminal of the second capacitor C2 is electrically connected to the second output control terminal GT2, and the second terminal of the second capacitor C2 is electrically connected to the high voltage terminal;
  • the first terminal of the first capacitor C1 is electrically connected to the first output control terminal GT1, and the second terminal of the first capacitor C1 is electrically connected to the driving signal output terminal G1;
  • the second output control terminal control circuit 21 includes a fifth transistor M5 and a sixth transistor M6;
  • the gate of the fifth transistor M5 is electrically connected to the second clock signal terminal K2, the source of the fifth transistor M5 is electrically connected to the low voltage end, and the drain of the fifth transistor M5 is electrically connected to the first clock signal terminal K2.
  • the two output control terminals GT2 are electrically connected; the low voltage terminal is used to provide a low voltage signal V02;
  • the gate of the sixth transistor M6 is electrically connected to the first node N1, the source of the sixth transistor M6 is electrically connected to the second clock signal terminal K2, and the drain of the sixth transistor M6 is electrically connected to the second clock signal terminal K2.
  • the second output control terminal GT2 is electrically connected;
  • the on-off control circuit 12 includes a seventh transistor M7;
  • the gate of the seventh transistor M7 is electrically connected to the low voltage terminal, the drain of the seventh transistor M7 is electrically connected to the first node N1, and the source of the seventh transistor M7 is electrically connected to the first node N1.
  • An output control terminal GT1 is electrically connected;
  • the first output circuit 13 includes a first output transistor M01, and the second output circuit 22 includes a second output transistor M02;
  • the gate of the first output transistor M01 is electrically connected to the first output control terminal GT1
  • the source of the first output transistor M01 is electrically connected to the first clock signal terminal K1
  • the first output transistor M01 The drain of M01 is electrically connected to the drive signal output terminal G1;
  • the gate of the second output transistor M02 is electrically connected to the second output control terminal GT2, the drain of the second output transistor M02 is electrically connected to the high voltage end, and the source of the second output transistor M02 The pole is electrically connected to the driving signal output terminal G1.
  • all transistors are p-type transistors, for example, the transistors may be PMOS transistors (P-type metal-oxide-semiconductor transistors), but not as a limit.
  • the transistors included in the drive circuit may also be n-type transistors, and it is sufficient to change the control signals accordingly.
  • the transistors included in the driving circuit described in at least one embodiment of the present disclosure may all be p-type transistors, or all may be n-type transistors, but not limited thereto.
  • the first control terminal is the third clock signal terminal K3, but not limited thereto.
  • the third clock signal provided by the third clock signal terminal K3 is opposite to the first clock signal provided by the first clock signal terminal K1, so that during the display period, M2 or M4 Turn off, control the disconnection between the first node N1 and the first voltage terminal V1, and prevent leakage current from affecting the potential of the first node N1; but not limited thereto.
  • the display cycle may include successively set input phase S1, output phase S2, and reset phase, and the reset phase includes successively set The first reset time period S31 and the second reset time period S32;
  • K1 provides a high voltage signal
  • K2 provides a low voltage signal
  • K3 provides a high voltage signal
  • I1 provides a low voltage signal
  • M1 is turned on, the potential of N1 is low voltage
  • M2 is turned off
  • I1 provides a low voltage signal
  • M6 is turned on, the low voltage signal provided by K2 is written into the gate of M02
  • M02 is turned on, G1 is connected to the high voltage terminal
  • M7 is turned on, the low voltage signal provided by I1
  • the voltage signal is written into the gate of M01 through M1 and M7 to charge C1 and turn on M01.
  • the high voltage signal provided by K1 is written into G1, and G1 outputs a high voltage signal
  • G1 outputs a high voltage signal
  • the potential of GT1 and the potential of GT2 are both low voltage
  • K3 provides a low voltage signal, and M4 is turned on;
  • I1 provides a high-voltage signal
  • K1 provides a low-voltage signal
  • K2 provides a high-voltage signal
  • K3 provides a high-voltage signal
  • M4 is disconnected to disconnect the path between the high-voltage terminal and N1, and C1 maintains GT1
  • the potential is low voltage
  • M01 is turned on
  • G1 outputs a low voltage signal
  • M7 is turned on
  • the potential of N1 is low voltage
  • M6 is turned on
  • the high voltage signal provided by K2 is written into GT2, and C2 is charged, making the potential of GT1 high voltage, M02 off;
  • I1 provides a high-voltage signal
  • K1 provides a high-voltage signal
  • K2 provides a low-voltage signal
  • K3 provides a low-voltage signal
  • M1 and M5 are turned on
  • the low-voltage signal V02 charges C2 through M5, so that The potential of GT2 is low voltage, and M3 and M02 are turned on, G1 outputs a high voltage signal
  • M2 is turned off
  • M1 is turned on to write the high voltage signal provided by I1 into N1
  • M7 is turned on to pass the high voltage provided by I1
  • the signal charges C1, the potential of GT1 is high voltage, and M01 is turned off;
  • I1 provides a high voltage signal
  • K1 provides a low voltage signal
  • K2 provides a high voltage signal
  • K3 provides a high voltage signal
  • M2 is turned on
  • C2 maintains the potential of GT2 at a low voltage
  • M3 and M02 are turned on
  • G1 outputs a high voltage signal
  • M4 is turned off
  • C1 maintains the potential of GT1 at a high voltage
  • M6, M01, M1 and M5 are turned off.
  • the first node control circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;
  • the gate of the first transistor M1 is electrically connected to the second clock signal terminal K2, the source of the first transistor M1 is electrically connected to the input terminal I1, and the drain of the first transistor M1 is electrically connected to the second clock signal terminal K2.
  • the first node N1 is electrically connected;
  • the gate of the second transistor M2 is electrically connected to the first clock signal terminal K1, the source of the second transistor M2 is electrically connected to the first node N1; the drain of the second transistor M2 is electrically connected to the first node N1.
  • the source of the third transistor M3 is electrically connected;
  • the gate of the third transistor M3 is electrically connected to the second output control terminal GT2, and the drain of the third transistor M3 is electrically connected to the source of the fourth transistor M4;
  • the gate of the fourth transistor M4 is electrically connected to the third clock signal terminal K3, and the drain of the fourth transistor M4 is electrically connected to a high voltage terminal; the high voltage terminal is used to provide a high voltage signal V01;
  • the first energy storage circuit 41 includes a first capacitor C1, and the second energy storage circuit 42 includes a second capacitor C2;
  • the first terminal of the second capacitor C2 is electrically connected to the second output control terminal GT2, and the second terminal of the second capacitor C2 is electrically connected to the high voltage terminal;
  • the first terminal of the first capacitor C1 is electrically connected to the first output control terminal GT1, and the second terminal of the first capacitor C1 is electrically connected to the driving signal output terminal G1;
  • the second output control terminal control circuit 21 includes a fifth transistor M5 and a sixth transistor M6;
  • the gate of the fifth transistor M5 is electrically connected to the second clock signal terminal K2, the source of the fifth transistor M5 is electrically connected to the low voltage end, and the drain of the fifth transistor M5 is electrically connected to the first clock signal terminal K2.
  • the two output control terminals GT2 are electrically connected; the low voltage terminal is used to provide a low voltage signal V02;
  • the gate of the sixth transistor M6 is electrically connected to the first node N1, the source of the sixth transistor M6 is electrically connected to the second clock signal terminal K2, and the drain of the sixth transistor M6 is electrically connected to the second clock signal terminal K2.
  • the second output control terminal GT2 is electrically connected;
  • the on-off control circuit 12 includes a seventh transistor M7;
  • the gate of the seventh transistor M7 is electrically connected to the low voltage terminal, the drain of the seventh transistor M7 is electrically connected to the first node N1, and the source of the seventh transistor M7 is electrically connected to the first node N1.
  • An output control terminal GT1 is electrically connected;
  • the first output circuit 13 includes a first output transistor M01, and the second output circuit 22 includes a second output transistor M02;
  • the gate of the first output transistor M01 is electrically connected to the first output control terminal GT1
  • the source of the first output transistor M01 is electrically connected to the first clock signal terminal K1
  • the first output transistor M01 The drain of M01 is electrically connected to the drive signal output terminal G1;
  • the gate of the second output transistor M02 is electrically connected to the second output control terminal GT2, the drain of the second output transistor M02 is electrically connected to the high voltage end, and the source of the second output transistor M02 The pole is electrically connected to the driving signal output terminal G1.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the first control terminal is the third clock signal terminal K3, but not limited thereto.
  • the display cycle may include an input phase S1, an output phase S2, and a reset phase that are set successively.
  • the reset phase includes successively set The first reset time period S31 and the second reset time period S32;
  • K1 provides a high voltage signal
  • K2 provides a low voltage signal
  • K3 provides a high voltage signal
  • I1 provides a low voltage signal
  • M1 is turned on, the potential of N1 is low voltage
  • M2 is turned off
  • I1 provides a low voltage signal
  • M6 is turned on, the low voltage signal provided by K2 is written into the gate of M02
  • M02 is turned on, G1 is connected to the high voltage terminal
  • M7 is turned on, the low voltage signal provided by I1
  • the voltage signal is written into the gate of M01 through M1 and M7 to charge C1 and turn on M01.
  • the high voltage signal provided by K1 is written into G1, and G1 outputs a high voltage signal
  • G1 outputs a high voltage signal
  • the potential of GT1 and the potential of GT2 are both low voltage
  • K3 provides a low voltage signal, and M4 is turned on;
  • I1 provides a high-voltage signal
  • K1 provides a low-voltage signal
  • K2 provides a high-voltage signal
  • K3 provides a high-voltage signal
  • M4 is disconnected to disconnect the path between the high-voltage terminal and N1, and C1 maintains GT1
  • the potential is low voltage
  • M01 is turned on
  • G1 outputs a low voltage signal
  • M7 is turned on
  • the potential of N1 is low voltage
  • M6 is turned on
  • the high voltage signal provided by K2 is written into GT2, and C2 is charged, making the potential of GT1 high voltage, M02 off;
  • I1 provides a high-voltage signal
  • K1 provides a high-voltage signal
  • K2 provides a low-voltage signal
  • K3 provides a low-voltage signal
  • M1 and M5 are turned on
  • the low-voltage signal V02 charges C2 through M5, so that The potential of GT2 is low voltage, and M3 and M02 are turned on, G1 outputs a high voltage signal
  • M2 is turned off
  • M1 is turned on to write the high voltage signal provided by I1 into N1
  • M7 is turned on to pass the high voltage provided by I1
  • the signal charges C1, the potential of GT1 is high voltage, and M01 is turned off;
  • I1 provides a high voltage signal
  • K1 provides a low voltage signal
  • K2 provides a high voltage signal
  • K3 provides a high voltage signal
  • M2 is turned on
  • C2 maintains the potential of GT2 at a low voltage
  • M3 and M02 are turned on
  • G1 outputs a high voltage signal
  • M4 is turned off
  • C1 maintains the potential of GT1 at a high voltage
  • M6, M01, M1 and M5 are turned off.
  • the first node control circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;
  • the gate of the first transistor M1 is electrically connected to the second clock signal terminal K2, the source of the first transistor M1 is electrically connected to the input terminal I1, and the drain of the first transistor M1 is electrically connected to the second clock signal terminal K2.
  • the first node N1 is electrically connected;
  • the gate of the fourth transistor M4 is electrically connected to the third clock signal terminal K3, the source of the fourth transistor M4 is electrically connected to the first node N1, and the drain of the fourth transistor M4 is electrically connected to the The source of the second transistor M2 is electrically connected;
  • the gate of the second transistor M2 is electrically connected to the first clock signal terminal K1, and the drain of the second transistor M2 is electrically connected to the source of the third transistor M3;
  • the gate of the third transistor M3 is electrically connected to the second output control terminal GT2, and the drain of the third transistor M3 is electrically connected to the high voltage terminal; the high voltage terminal is used to provide a high voltage signal V01;
  • the first energy storage circuit 41 includes a first capacitor C1, and the second energy storage circuit 42 includes a second capacitor C2;
  • the first terminal of the second capacitor C2 is electrically connected to the second output control terminal GT2, and the second terminal of the second capacitor C2 is electrically connected to the high voltage terminal;
  • the first terminal of the first capacitor C1 is electrically connected to the first output control terminal GT1, and the second terminal of the first capacitor C1 is electrically connected to the driving signal output terminal G1;
  • the second output control terminal control circuit 21 includes a fifth transistor M5 and a sixth transistor M6;
  • the gate of the fifth transistor M5 is electrically connected to the second clock signal terminal K2, the source of the fifth transistor M5 is electrically connected to the low voltage end, and the drain of the fifth transistor M5 is electrically connected to the first clock signal terminal K2.
  • the two output control terminals GT2 are electrically connected; the low voltage terminal is used to provide a low voltage signal V02;
  • the gate of the sixth transistor M6 is electrically connected to the first node N1, the source of the sixth transistor M6 is electrically connected to the second clock signal terminal K2, and the drain of the sixth transistor M6 is electrically connected to the second clock signal terminal K2.
  • the second output control terminal GT2 is electrically connected;
  • the on-off control circuit 12 includes a seventh transistor M7;
  • the gate of the seventh transistor M7 is electrically connected to the low voltage terminal, the drain of the seventh transistor M7 is electrically connected to the first node N1, and the source of the seventh transistor M7 is electrically connected to the first node N1.
  • An output control terminal GT1 is electrically connected;
  • the first output circuit 13 includes a first output transistor M01, and the second output circuit 22 includes a second output transistor M02;
  • the gate of the first output transistor M01 is electrically connected to the first output control terminal GT1
  • the source of the first output transistor M01 is electrically connected to the first clock signal terminal K1
  • the first output transistor M01 The drain of M01 is electrically connected to the drive signal output terminal G1;
  • the gate of the second output transistor M02 is electrically connected to the second output control terminal GT2, the drain of the second output transistor M02 is electrically connected to the high voltage end, and the source of the second output transistor M02 The pole is electrically connected to the driving signal output terminal G1.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the first control terminal is the third clock signal terminal K3, but not limited thereto.
  • K1 provides a high voltage signal
  • K2 provides a low voltage signal
  • K3 provides a high voltage signal
  • I1 provides a low voltage signal
  • M1 is turned on, the potential of N1 is low voltage
  • M2 is turned off
  • I1 provides a low voltage signal
  • M6 is turned on, the low voltage signal provided by K2 is written into the gate of M02
  • M02 is turned on, G1 is connected to the high voltage terminal
  • M7 is turned on, the low voltage signal provided by I1
  • the voltage signal is written into the gate of M01 through M1 and M7 to charge C1 and turn on M01.
  • the high voltage signal provided by K1 is written into G1, and G1 outputs a high voltage signal
  • G1 outputs a high voltage signal
  • the potential of GT1 and the potential of GT2 are both low voltage
  • K3 provides a low voltage signal, and M4 is turned on;
  • I1 provides a high-voltage signal
  • K1 provides a low-voltage signal
  • K2 provides a high-voltage signal
  • K3 provides a high-voltage signal
  • M4 is disconnected to disconnect the path between the high-voltage terminal and N1, and C1 maintains GT1
  • the potential is low voltage
  • M01 is turned on
  • G1 outputs a low voltage signal
  • M7 is turned on
  • the potential of N1 is low voltage
  • M6 is turned on
  • the high voltage signal provided by K2 is written into GT2, and C2 is charged, making the potential of GT1 high voltage, M02 off;
  • I1 provides a high-voltage signal
  • K1 provides a high-voltage signal
  • K2 provides a low-voltage signal
  • K3 provides a low-voltage signal
  • M1 and M5 are turned on
  • the low-voltage signal V02 charges C2 through M5, so that The potential of GT2 is low voltage, and M3 and M02 are turned on, G1 outputs a high voltage signal
  • M2 is turned off
  • M1 is turned on to write the high voltage signal provided by I1 into N1
  • M7 is turned on to pass the high voltage provided by I1
  • the signal charges C1, the potential of GT1 is high voltage, and M01 is turned off;
  • I1 provides a high voltage signal
  • K1 provides a low voltage signal
  • K2 provides a high voltage signal
  • K3 provides a high voltage signal
  • M2 is turned on
  • C2 maintains the potential of GT2 at a low voltage
  • M3 and M02 are turned on
  • G1 outputs a high voltage signal
  • M4 is turned off
  • C1 maintains the potential of GT1 at a high voltage
  • M6, M01, M1 and M5 are turned off.
  • the first node control circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;
  • the gate of the first transistor M1 is electrically connected to the second clock signal terminal K2, the source of the first transistor M1 is electrically connected to the input terminal I1, and the drain of the first transistor M1 is electrically connected to the second clock signal terminal K2.
  • the two nodes N2 are electrically connected;
  • the gate of the fourth transistor M4 is electrically connected to the third clock signal terminal K3, the source of the fourth transistor M4 is electrically connected to the second node N2, and the drain of the fourth transistor is electrically connected to the first A node N1 is electrically connected;
  • the gate of the second transistor M2 is electrically connected to the first clock signal terminal K1, the source of the second transistor M2 is electrically connected to the second node N2, and the drain of the second transistor M2 is electrically connected to the second node N2.
  • the source of the third transistor M3 is electrically connected;
  • the gate of the third transistor M3 is electrically connected to the second output control terminal GT2, and the drain of the third transistor M3 is electrically connected to the high voltage terminal; the high voltage terminal is used to provide a high voltage signal V01;
  • the first energy storage circuit 41 includes a first capacitor C1, and the second energy storage circuit 42 includes a second capacitor C2;
  • the first terminal of the second capacitor C2 is electrically connected to the second output control terminal GT2, and the second terminal of the second capacitor C2 is electrically connected to the high voltage terminal;
  • the first terminal of the first capacitor C1 is electrically connected to the first output control terminal GT1, and the second terminal of the first capacitor C1 is electrically connected to the driving signal output terminal G1;
  • the second output control terminal control circuit 21 includes a fifth transistor M5 and a sixth transistor M6;
  • the gate of the fifth transistor M5 is electrically connected to the second clock signal terminal K2, the source of the fifth transistor M5 is electrically connected to the low voltage end, and the drain of the fifth transistor M5 is electrically connected to the first clock signal terminal K2.
  • the two output control terminals GT2 are electrically connected; the low voltage terminal is used to provide a low voltage signal V02;
  • the gate of the sixth transistor M6 is electrically connected to the first node N1, the source of the sixth transistor M6 is electrically connected to the second clock signal terminal K2, and the drain of the sixth transistor M6 is electrically connected to the second clock signal terminal K2.
  • the second output control terminal GT2 is electrically connected;
  • the on-off control circuit 12 includes a seventh transistor M7;
  • the gate of the seventh transistor M7 is electrically connected to the low voltage terminal, the drain of the seventh transistor M7 is electrically connected to the first node N1, and the source of the seventh transistor M7 is electrically connected to the first node N1.
  • An output control terminal GT1 is electrically connected;
  • the first output circuit 13 includes a first output transistor M01, and the second output circuit 22 includes a second output transistor M02;
  • the gate of the first output transistor M01 is electrically connected to the first output control terminal GT1
  • the source of the first output transistor M01 is electrically connected to the first clock signal terminal K1
  • the first output transistor M01 The drain of M01 is electrically connected to the drive signal output terminal G1;
  • the gate of the second output transistor M02 is electrically connected to the second output control terminal GT2, the drain of the second output transistor M02 is electrically connected to the high voltage end, and the source of the second output transistor M02 The pole is electrically connected to the driving signal output terminal G1.
  • all transistors are p-type thin film transistors, but not limited thereto.
  • the first control terminal is the third clock signal terminal K3, but not limited thereto.
  • K1 provides a high voltage signal
  • K2 provides a low voltage signal
  • K3 provides a high voltage signal
  • I1 provides a low voltage signal
  • M1 is turned on
  • M2 is turned off
  • the low voltage signal provided by I1 is written into the gate of M6 and Charge C2
  • M6 is turned on
  • the low voltage signal provided by K2 is written into the gate of M02
  • M02 is turned on
  • G1 is connected to the high voltage terminal
  • M7 is turned on, and the low voltage signal provided by I1 is written through M1 and M7 Enter the gate of M01, charge C1 and turn on M01, at this time, the high voltage signal provided by K1 is written into G1, and G1 outputs a high voltage signal
  • M1 is turned on
  • M2 is turned off
  • the low voltage signal provided by I1 is written into the gate of M6 and Charge C2
  • M6 is turned on
  • the low voltage signal provided by K2 is written into the gate of M02
  • M02 is turned on
  • the potential of GT1 and the potential of GT2 are both low voltage
  • K3 provides a low voltage signal
  • M4 is turned on
  • the potential of N1 is a low voltage
  • I1 provides a high-voltage signal
  • K1 provides a low-voltage signal
  • K2 provides a high-voltage signal
  • K3 provides a high-voltage signal
  • M4 is disconnected to disconnect the path between the high-voltage terminal and N1, and C1 maintains GT1
  • the potential is low voltage
  • M01 is turned on
  • G1 outputs a low voltage signal
  • M7 is turned on
  • the potential of N1 is low voltage
  • M6 is turned on
  • the high voltage signal provided by K2 is written into GT2, and C2 is charged, making the potential of GT1 high voltage, M02 off;
  • I1 provides a high-voltage signal
  • K1 provides a high-voltage signal
  • K2 provides a low-voltage signal
  • K3 provides a low-voltage signal
  • M1 and M5 are turned on
  • the low-voltage signal V02 charges C2 through M5, so that The potential of GT2 is low voltage, and M3 and M02 are turned on, G1 outputs a high voltage signal
  • M2 is turned off
  • M1 is turned on to write the high voltage signal provided by I1 into N1
  • M7 is turned on to pass the high voltage provided by I1
  • the signal charges C1, the potential of GT1 is high voltage, and M01 is turned off;
  • I1 provides a high voltage signal
  • K1 provides a low voltage signal
  • K2 provides a high voltage signal
  • K3 provides a high voltage signal
  • M2 is turned on
  • C2 maintains the potential of GT2 at a low voltage
  • M3 and M02 are turned on
  • G1 outputs a high voltage signal
  • M4 is turned off
  • C1 maintains the potential of GT1 at a high voltage
  • M6, M01, M1 and M5 are turned off.
  • the driving module described in the embodiment of the present disclosure includes multiple stages of the above-mentioned driving circuits.
  • the driving module described in the embodiments of the present disclosure may include a first-level driving circuit and a second-level driving circuit;
  • the first clock signal end of the first-level drive circuit is electrically connected to the first clock signal line SK1
  • the second clock signal end of the first-level drive circuit is electrically connected to the second clock signal line SK2
  • the first The third clock signal end of the stage drive circuit is electrically connected to the third clock signal line SK3;
  • the first clock signal end of the second-level drive circuit is electrically connected to the second clock signal line SK2
  • the second clock signal end of the first-level drive circuit is electrically connected to the first clock signal line SK2
  • the first The third clock signal end of the stage drive circuit is electrically connected to the third clock signal line SK4;
  • Fig. 10 the waveform diagram of the clock signal provided by the first clock signal line SK1, the waveform diagram of the clock signal provided by the second clock signal line SK2, the waveform diagram of the clock signal provided by the third clock signal line SK3, and the waveform diagram of the clock signal provided by the third clock signal line SK3 are shown.
  • the waveform diagram of the clock signal provided by the four clock signal line SK4 the waveform diagram of the input signal provided by the input terminal I1 electrically connected to the first-level driving circuit, the waveform diagram of the driving signal G11 output by the first-level driving circuit, and the second Waveform diagram of the drive signal G12 output by the stage drive circuit.
  • the clock signal provided by the first clock signal line SK1 and the clock signal provided by the third clock signal line SK3 may be opposite to each other, but not limited thereto.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the display cycle includes an output stage;
  • the driving method includes: in the output stage, the first node control circuit controls the disconnection between the first node and the first voltage terminal under the control of the first control signal, and the on-off control circuit controls the second voltage signal, Controlling the communication between the first node and the first output control terminal, the first output circuit controls the communication between the driving signal output terminal and the first clock signal terminal under the control of the potential of the first output control terminal.
  • the first node control circuit controls the disconnection between the first node and the first voltage terminal in the output stage under the control of the first control signal, thereby avoiding that in the output stage, the first node
  • the potential of the first output control terminal and the potential of the first output control terminal are controlled to be the first voltage, so that in the output stage, the first output circuit can control the drive signal output terminal and the The first clock signal terminals are connected to output the drive signal normally.
  • the driving circuit further includes a second output control terminal control circuit and a second output circuit;
  • the display cycle further includes an input phase set before the output phase;
  • the driving method further includes:
  • the second output control terminal control circuit controls the connection between the second output control terminal and the second voltage terminal under the control of the second clock signal, so that the potential of the second output circuit at the second output control terminal Under the control of the control, the connection between the driving signal output terminal and the first voltage terminal is controlled;
  • the second output control terminal control circuit controls the connection between the second output control terminal and the second clock signal terminal under the control of the potential of the first node, so that the first The second output circuit controls the disconnection between the driving signal output terminal and the first voltage terminal under the control of the potential of the second output control terminal.
  • the drive circuit also includes a second output control terminal control circuit and a second output circuit, the second output control terminal control circuit controls the potential of the second output control terminal, and the potential of the second output circuit at the second output control terminal Under the control of the control, the connection or disconnection between the driving signal output terminal and the first voltage terminal is controlled.
  • the first node control circuit is also electrically connected to the second clock signal terminal and the input terminal respectively;
  • the driving circuit also includes a first energy storage circuit and a second energy storage circuit; the driving method further includes:
  • the input terminal provides an input signal
  • the first node control circuit controls the input terminal to provide the input signal to the first node under the control of the second clock signal
  • the on-off control circuit operates on the second Under the control of the second voltage signal provided by the voltage terminal, the communication between the first node and the first output control terminal is controlled to charge the first energy storage circuit, and the first output circuit is connected to the first output control terminal. Under the control of the potential, the communication between the drive signal output end and the first clock signal end is controlled.
  • the first node control circuit can control the input signal to be written into the first node during the input stage, and the on-off control circuit controls the connection between the first node and the first output control terminal under the control of the second voltage signal.
  • the first output circuit controls the communication between the drive signal output terminal and the first clock signal terminal under the control of the potential of the first output control terminal.
  • the display cycle further includes a reset phase set after the output phase;
  • the reset phase includes a first reset time period and a second reset time period;
  • the driving method further includes:
  • the input terminal provides the first voltage signal, and the potential of the second clock signal provided by the second clock signal terminal is the second voltage; the first node control circuit controls the The first node is connected to the input terminal, so that the potential of the first node is a first voltage, and the on-off control circuit controls the second voltage signal provided by the second voltage terminal.
  • the first node communicates with the first output control terminal to charge the first energy storage circuit, so that the potential of the first output control terminal is a first voltage;
  • the second output control terminal control circuit controls the second output control terminal under the control of the second clock signal It is connected with the second voltage terminal to charge the second energy storage circuit, so that the potential of the second output control terminal is the second voltage, and the second output circuit is under the control of the potential of the second output control terminal , controlling the communication between the drive signal output terminal and the first voltage terminal, so that the drive signal output terminal outputs a first voltage signal;
  • the second energy storage circuit maintains the potential of the second output control terminal, and the second output circuit controls the drive signal output terminal and the first output terminal under the control of the potential of the second output control terminal.
  • One voltage terminal is connected; the first energy storage circuit maintains the potential of the first output control terminal, and the first output circuit controls the drive signal output terminal and the first clock signal terminal under the control of the first output control terminal disconnected between.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned driving module.
  • the display device described in at least one embodiment of the present disclosure may be a silicon-based OLED (Organic Light Emitting Diode) display device, but is not limited thereto.
  • OLED Organic Light Emitting Diode
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

一种驱动电路、驱动模组、驱动方法和显示装置，驱动电路包括驱动信号输出端（G1），第一节点控制电路（11）、通断控制电路（12）和第一输出电路（13）；第一节点控制电路（11）在第一控制信号的控制下，控制第一节点（N1）与第一电压端（V1）之间断开或连通，在第一时钟信号的控制下，控制第一节点（N1）与第一电压端（V1）之间连通或断开；第一控制端（D1）与第一时钟信号端（K1）不相同；通断控制电路（12）在第二电压信号的控制下，控制第一节点（N1）与第一输出控制端（GT1）之间连通或断开；第一输出电路（13）在第一输出控制端（GT1）的电位的控制下，控制驱动信号输出端（G1）与第一时钟信号端（K1）之间连通或断开。解决了驱动电路不能在输出阶段（S2）正常输出驱动信号的问题。

Description

驱动电路、驱动模组、驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、驱动模组、驱动方法和显示装置。
背景技术
相关的应用于硅基OLED(有机发光二极管)显示装置的驱动电路只采用N型晶体管或P型晶体管。相关的所述驱动电路在工作时，在输出阶段，会出现驱动电路不能正常输出驱动信号的情况发生。
发明内容
在一个方面中，本公开实施例提供了一种驱动电路，包括驱动信号输出端，第一节点控制电路、通断控制电路和第一输出电路；
所述第一节点控制电路分别与第一控制端、所述第一电压端、所述第一节点、第二输出控制端和第一时钟信号端电连接，用于在所述第一控制端提供的第一控制信号的控制下，控制所述第一节点与所述第一电压端之间断开或连通，并在所述第一时钟信号端提供的第一时钟信号的控制下，控制所述第一节点与所述第一电压端之间连通或断开；所述第一控制端与所述第一时钟信号端不相同；
所述通断控制电路分别与第二电压端、所述第一节点和第一输出控制端电连接，用于在所述第二电压端提供的第二电压信号的控制下，控制所述第一节点与所述第一输出控制端之间连通或断开；
所述第一输出电路分别与第一输出控制端、第一时钟信号端和所述驱动信号输出端电连接，用于在所述第一输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一时钟信号端之间连通或断开。
可选的，所述第一节点控制电路包括的晶体管都为p型晶体管；或者，所述第一节点控制电路包括的晶体管都为n型晶体管；
所述第一控制信号与所述第一时钟信号相互反相。
可选的，本公开至少一实施例所述的驱动电路还包括第二输出控制端控制电路和第二输出电路；
所述第二输出控制端控制电路分别与所述第一节点、所述第二输出控制端、第二时钟信号端和第二电压端电连接，用于在所述第一节点的电位的控制下，控制所述第二输出控制端与所述第二时钟信号端之间连通或断开，在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第二输出控制端与所述第二电压端之间连通或断开；
所述第二输出电路分别与第二输出控制端、第一电压端和所述驱动信号输出端电连接，用于在所述第二输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一电压端之间连通或断开。
可选的，所述第一节点控制电路还分别与第二输出控制端、第二时钟信号端和输入端电连接，用于在所述第二输出控制端的电位的控制下，控制所述第一节点与所述第一电压端之间连通或断开，并用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通或断开。
可选的，所述第一节点控制电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
所述第一晶体管的控制极与所述第二时钟信号端电连接，所述第一晶体管的第一极与所述输入端电连接，所述第一晶体管的第二极与所述第一节点电连接；
所述第二晶体管的控制极与所述第一时钟信号端电连接，所述第二晶体管的第一极与所述第一节点电连接；
所述第三晶体管的控制极与所述第二输出控制端电连接，所述第三晶体管的第一极与所述第二晶体管的第二极电连接，所述第三晶体管的第二极与所述第一电压端电连接；
所述第一电压端通过所述第四晶体管与所述第三晶体管的第二极电连接；或者，所述第三晶体管的第一极通过所述第四晶体管与所述第二晶体管的第二极电连接；或者，所述第二晶体管的第一极通过所述第四晶体管与所述第一节点电连接；
所述第四晶体管的控制极与所述第一控制端电连接。
可选的，所述第一节点控制电路还分别与第二输出控制端、第二时钟信号端和输入端电连接，用于在所述第二输出控制端的电位的控制下，控制所述第一节点与所述第一电压端之间连通或断开，并用于在所述第一控制信号和所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通或断开。
可选的，所述第一节点控制电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
所述第一晶体管的控制极与所述第二时钟信号端电连接，所述第一晶体管的第一极与所述输入端电连接，所述第一晶体管的第二极与所述第二节点电连接；
所述第二晶体管的控制极与所述第一时钟信号端电连接，所述第二晶体管的第一极与所述第二节点电连接；
所述第三晶体管的控制极与所述第二输出控制端电连接，所述第三晶体管的第一极与所述第二晶体管的第二极电连接，所述第三晶体管的第二极与所述第一电压端电连接；
所述第四晶体管的控制极与所述第一控制端电连接，所述第四晶体管的第一极与所述第二节点电连接，所述第四晶体管的第二极与所述第一节点电连接。
可选的，所述第四晶体管为双栅晶体管。
可选的，所述第四晶体管的宽长比等于所述第二晶体管的宽长比。
可选的，本公开至少一实施例所述的驱动电路还包括第一储能电路和第二储能电路；
所述第一储能电路与所述第一输出控制端电连接，用于储存电能；
所述第二储能电路与所述第二输出控制端电连接，用于储存电能。
可选的，所述第一储能电路包括第一电容，所述第二储能电路包括第二电容；
所述第二电容的第一端与所述第二输出控制端电连接，所述第二电容的第二端与所述第一电压端电连接；
所述第一电容的第一端与所述第一输出控制端电连接，所述第一电容的第二端与所述驱动信号输出端电连接。
可选的，所述第二输出控制端控制电路包括第五晶体管和第六晶体管；
所述第五晶体管的控制极与所述第二时钟信号端电连接，所述第五晶体管的第一极与所述第二电压端电连接，所述第五晶体管的第二极与所述第二输出控制端电连接；
所述第六晶体管的控制极与所述第一节点电连接，所述第六晶体管的第一极与所述第二时钟信号端电连接，所述第六晶体管的第二极与所述第二输出控制端电连接。
可选的，所述通断控制电路包括第七晶体管；
所述第七晶体管的控制极与所述第二电压端电连接，所述第七晶体管的第一极与所述第一节点电连接，所述第七晶体管的第二极与所述第一输出控制端电连接。
可选的，所述第一输出电路包括第一输出晶体管，所述第二输出电路包括第二输出晶体管；
所述第一输出晶体管的控制极与所述第一输出控制端电连接，所述第一输出晶体管的第一极与所述第一时钟信号端电连接，所述第一输出晶体管的第二极与所述驱动信号输出端电连接；
所述第二输出晶体管的控制极与所述第二输出控制端电连接，所述第二输出晶体管的第一极与所述第一电压端电连接，所述第二输出晶体管的第二极与所述驱动信号输出端电连接。
可选的，所述第一输出晶体管的宽长比大于所述第二输出晶体管的宽长比。
在第二个方面中，本公开实施例还提供了一种驱动模组，包括多级上述的驱动电路。
在第三个方面中，本公开实施例还提供了一种驱动方法，应用于上述的驱动电路，显示周期包括输出阶段；
所述驱动方法包括：在输出阶段，第一节点控制电路在第一控制信号的控制下，控制第一节点与第一电压端之间断开，通断控制电路在第二电压信 号的控制下，控制第一节点与第一输出控制端之间连通，第一输出电路在第一输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一时钟信号端之间连通。
可选的，所述驱动电路还包括第二输出控制端控制电路和第二输出电路；显示周期还包括设置于所述输出阶段之前的输入阶段；所述驱动方法还包括：
在输入阶段，第二输出控制端控制电路在第二时钟信号的控制下，控制第二输出控制端与第二电压端之间连通，以使得第二输出电路在所述第二输出控制端的电位的控制下，控制驱动信号输出端与所述第一电压端之间连通；
在输出阶段，所述第二输出控制端控制电路在所述第一节点的电位的控制下，控制所述第二输出控制端与所述第二时钟信号端之间连通，以使得所述第二输出电路在所述第二输出控制端的电位的控制下，控制驱动信号输出端与所述第一电压端之间断开。
可选的，所述第一节点控制电路还分别与第二时钟信号端和输入端电连接；所述驱动电路还包括第一储能电路和第二储能电路；所述驱动方法还包括：
在输入阶段，输入端提供输入信号，所述第一节点控制电路在第二时钟信号的控制下，控制输入端提供所述输入信号至所述第一节点；通断控制电路在所述第二电压端提供的第二电压信号的控制下，控制所述第一节点与所述第一输出控制端之间连通，以为第一储能电路充电，第一输出电路在所述第一输出控制端的电位的控制下，控制所述驱动信号输出端与第一时钟信号端之间连通。
可选的，显示周期还包括设置于所述输出阶段之后的复位阶段；所述复位阶段包括第一复位时间段和第二复位时间段；所述驱动方法还包括：
在第一复位时间段，输入端提供第一电压信号，第二时钟信号端提供的第二时钟信号的电位为第二电压；第一节点控制电路在第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通，以使得所述第一节点的电位为第一电压，通断控制电路在所述第二电压端提供的第二电压信号的控制下，控制所述第一节点与所述第一输出控制端之间连通，为所述第一储能电路充电，以使得所述第一输出控制端的电位为第一电压；所述第一输出电路在所 述第一输出控制端的电位的控制下，控制所述驱动信号输出端与第一时钟信号端之间断开；第二输出控制端控制电路在第二时钟信号的控制下，控制所述第二输出控制端与第二电压端之间连通，为所述第二储能电路充电，以使得所述第二输出控制端的电位为第二电压，第二输出电路在所述第二输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一电压端之间连通；
在第二复位时间段，第二储能电路维持所述第二输出控制端的电位，第二输出电路在所述第二输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一电压端之间连通；第一储能电路维持所述第一输出控制端的电位，第一输出电路在第一输出控制端的控制下，控制所述驱动信号输出端与所述第一时钟信号端之间断开。
在第四个方面中，本公开实施例还提供了一种显示装置，包括上述的像素电路。
附图说明
图1是本公开实施例所述的驱动电路的结构图；
图2是本公开至少一实施例所述的驱动电路的结构图；
图3是本公开至少一实施例所述的驱动电路的结构图；
图4是本公开至少一实施例所述的驱动电路的结构图；
图5是本公开至少一实施例所述的驱动电路的电路图；
图6是本公开至少一实施例所述的驱动电路的工作时序图；
图7是本公开至少一实施例所述的驱动电路的电路图；
图8是本公开至少一实施例所述的驱动电路的电路图；
图9是本公开至少一实施例所述的驱动电路的电路图；
图10是本公开至少一实施例所述的驱动模组的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做 出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的驱动电路包括驱动信号输出端G1、第一节点控制电路11、通断控制电路12和第一输出电路13；
所述第一节点控制电路11分别与第一控制端D1、所述第一电压端V1、所述第一节点N1和第一时钟信号端K1电连接，用于在所述第一控制端D1提供的第一控制信号的控制下，控制所述第一节点N1与所述第一电压端V1之间断开或连通，并用于在所述第一时钟信号端K1提供的第一时钟信号的控制下，控制所述第一节点N1与所述第一电压端V1之间连通或断开；所述第一控制端D1与所述第一时钟信号端K1不相同；
所述通断控制电路12分别与第二电压端V2、所述第一节点和第一输出控制端GT1电连接，用于在所述第二电压端V2提供的第二电压信号的控制下，控制所述第一节点N1与所述第一输出控制端GT1之间连通或断开；
所述第一输出电路13分别与第一输出控制端GT1、第一时钟信号端K1和所述驱动信号输出端G1电连接，用于在所述第一输出控制端GT1的电位的控制下，控制所述驱动信号输出端G1与所述第一时钟信号端K1之间连通或断开。
在本公开至少一实施例中，所述第一电压端可以为高电压端，所述第二电压端可以为低电压端，但不以此为限。
在本公开至少一实施例中，当所述第一节点控制电路11包括的晶体管都为p型晶体管，或者，所述第一节点控制电路11包括的晶体管都为n型晶体管时，所述第一控制端D1提供的第一控制信号和所述第一时钟信号端K1提供的第一时钟信号不相同，以使得在输出阶段，所述第一节点控制电路11能够控制第一节点N1与第一电压端之间断开，防止由于第一节点N1与第一电 压端V1之间的漏电流而影响第一节点N1的电位。
本公开如图1所示的驱动电路的实施例在工作时，显示周期包括输出阶段；
在输出阶段，第一节点控制电路11在第一控制信号的控制下，控制第一节点N1与第一电压端之间断开，通断控制电路12在第二电压信号的控制下，控制第一节点N1与第一输出控制端GT1之间连通，第一输出电路在第一输出控制端GT1的电位的控制下，控制所述驱动信号输出端G1与所述第一时钟信号端K1之间连通，以使得所述驱动信号输出端G1能够正常输出驱动信号。
本公开实施例所述的驱动电路通过第一节点控制电路11在输出阶段，在第一控制信号的控制下，控制第一节点N1与第一电压端V1之间断开，从而避免在输出阶段，第一节点N1的电位和第一输出控制端GT1的电位为第一电压，进而使得在输出阶段，第一输出电路13能够在所述第一输出控制端GT1的电位的控制下，控制所述驱动信号输出端G1与所述第一时钟信号端K1之间连通，以正常输出驱动信号。
在本公开至少一实施例中，所述第一节点控制电路包括的晶体管都为p型晶体管；或者，所述第一节点控制电路包括的晶体管都为n型晶体管；
所述第一控制信号与所述第一时钟信号相互反相。
在具体实施时，可以将第一控制端提供的第一控制信号与第一时钟信号端提供的第一时钟信号设置为相互反相，以使得所述第一节点控制电路包括的控制极接入所述第一控制信号的晶体管，以及，控制极接入所述第一时钟信号的晶体管不会同时打开，从而防止由于第一节点N1与第一电压端V1之间的漏电流而影响第一节点N1的电位。
如图2所示，在图1所示的驱动电路的实施例的基础上，本公开至少一实施例所述的驱动电路还包括第二输出控制端控制电路21和第二输出电路22；
所述第二输出控制端控制电路21分别与所述第一节点N1、所述第二输出控制端GT2、第二时钟信号端K2和第二电压端V2电连接，用于在所述第一节点N1的电位的控制下，控制所述第二输出控制端GT2与所述第二时钟 信号端K2之间连通或断开，在所述第二时钟信号端K2提供的第二时钟信号的控制下，控制所述第二输出控制端GT2与所述第二电压端V2之间连通或断开；
所述第二输出电路22分别与第二输出控制端GT2、第一电压端V1和所述驱动信号输出端G1电连接，用于在所述第二输出控制端GT2的电位的控制下，控制所述驱动信号输出端G1与所述第一电压端V1之间连通或断开。
在本公开至少一实施例中，所述第一控制端可以为第三时钟信号端，但不以此为限。
本公开如图2所示的驱动电路的至少一实施例在工作时，显示周期还包括设置于所述输出阶段之前的输入阶段；
在输入阶段，第二输出控制端控制电路21在第二时钟信号的控制下，控制第二输出控制端GT2与第二电压端V2之间连通，以使得第二输出电路22在所述第二输出控制端GT2的电位的控制下，控制驱动信号输出端G1与所述第一电压端V1之间连通；
在输出阶段，所述第二输出控制端控制电路21在所述第一节点N1的电位的控制下，控制所述第二输出控制端GT2与所述第二时钟信号端K2之间连通，以使得所述第二输出电路22在所述第二输出控制端GT2的电位的控制下，控制驱动信号输出端G1与所述第一电压端V1之间断开。
在本公开如图2所示的驱动电路的至少一实施例工作时，在输出阶段，由于第一节点控制电路11控制避免第一节点N1的电位被第一电压信号拉升，进而使得在输出阶段，第二输出控制端控制电路21能够在第一节点N1的电位的控制下，控制第二输出控制端GT2与所述第二时钟信号端K2之间连通，以控制所述第二输出电路22包括的晶体管关断，避免影响所述驱动信号输出端G1输出驱动信号。
在本公开至少一实施例中，所述第一节点控制电路还可以分别与第二输出控制端、第二时钟信号端和输入端电连接，用于在所述第二输出控制端的电位的控制下，控制所述第一节点与所述第一电压端之间连通或断开，并用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通或断开。
本公开至少一实施例所述的驱动电路还可以包括第一储能电路和第二储能电路；
所述第一储能电路与所述第一输出控制端电连接，用于储存电能，维持所述第一输出控制端的电位；
所述第二储能电路与所述第二输出控制端电连接，用于储存电能，维持所述第二输出控制端的电位。
如图3所示，在图2所示的驱动电路的至少一实施例的基础上，所述第一节点控制电路11还分别与第二输出控制端GT2、第二时钟信号端K2和输入端I1电连接，用于在所述第二时钟信号端K2提供的第二时钟信号的控制下，控制所述第一节点N1与所述输入端I1之间连通或断开，并在所述第二输出控制端GT2的电位的控制下，控制所述第一节点N1与所述第一电压端V1之间连通或断开；
如图3所示，本公开至少一实施例所述的驱动电路还包括第一储能电路41和第二储能电路42；
所述第一储能电路41与所述第一输出控制端GT1电连接，用于储存电能，维持所述第一输出控制端GT1的电位；
所述第二储能电路42与所述第二输出控制端GT2电连接，用于储存电能，维持所述第二输出控制端GT2的电位。
本公开如图3所示的驱动电路的至少一实施例在工作时，显示周期包括先后设置的输入阶段、输出阶段和复位阶段；
在输入阶段，输入端I1提供输入信号，所述第一节点控制电路11在第二时钟信号的控制下，控制输入端I1提供所述输入信号至所述第一节点N1；通断控制电路12在所述第二电压端V2提供的第二电压信号的控制下，控制所述第一节点N1与所述第一输出控制端GT1之间连通，以为第一储能电路41充电，第一输出电路13在所述第一输出控制端GT1的电位的控制下，控制所述驱动信号输出端G1与第一时钟信号端K1之间连通；
在复位阶段包括的第一复位时间段，输入端I1提供第一电压信号，第二时钟信号端K2提供的第二时钟信号的电位为第二电压；第一节点控制电路11在第二时钟信号的控制下，控制所述第一节点N1与所述输入端I1之间连 通，以使得所述第一节点N1的电位为第一电压，通断控制电路12在所述第二电压端V2提供的第二电压信号的控制下，控制所述第一节点N1与所述第一输出控制端GT1之间连通，为所述第一储能电路41充电，以使得所述第一输出控制端GT1的电位为第一电压；所述第一输出电路13在所述第一输出控制端GT1的电位的控制下，控制所述驱动信号输出端G1与第一时钟信号端K1之间断开；第二输出控制端控制电路21在第二时钟信号的控制下，控制所述第二输出控制端GT2与第二电压端之间连通，为所述第二储能电路42充电，以使得所述第二输出控制端GT2的电位为第二电压，第二输出电路22在所述第二输出控制端GT2的电位的控制下，控制所述驱动信号输出端G1与所述第一电压端V1之间连通；
在复位阶段包括的第二复位时间段，第二储能电路42维持所述第二输出控制端GT2的电位，第二输出电路22在所述第二输出控制端GT2的电位的控制下，控制所述驱动信号输出端G1与所述第一电压端V1之间连通；第一储能电路41维持所述第一输出控制端GT1的电位，第一输出电路13在第一输出控制端GT1的控制下，控制所述驱动信号输出端G1与所述第一时钟信号端K1之间断开。
可选的，所述第一节点控制电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
所述第一晶体管的控制极与所述第二时钟信号端电连接，所述第一晶体管的第一极与所述输入端电连接，所述第一晶体管的第二极与所述第一节点电连接；
所述第二晶体管的控制极与所述第一时钟信号端电连接，所述第二晶体管的第一极与所述第一节点电连接；
所述第三晶体管的控制极与所述第二输出控制端电连接，所述第三晶体管的第一极与所述第二晶体管的第二极电连接，所述第三晶体管的第二极与所述第一电压端电连接；
所述第一电压端通过所述第四晶体管与所述第三晶体管的第二极电连接；或者，所述第三晶体管的第一极通过所述第四晶体管与所述第二晶体管的第二极电连接；或者，所述第二晶体管的第一极通过所述第四晶体管与所述第 一节点电连接；
所述第四晶体管的控制极与所述第一控制端电连接。
在本公开至少一实施例中，所述第一节点控制电路还可以分别与第二输出控制端、第二时钟信号端和输入端电连接，用于在所述第二输出控制端的电位的控制下，控制所述第一节点与所述第一电压端之间连通或断开，并用于在所述第一控制信号和所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通或断开。
如图4所示，在图2所示的驱动电路的至少一实施例的基础上，所述第一节点控制电路11还分别与第二输出控制端GT2、第二时钟信号端K2和输入端I1电连接，用于在所述第二输出控制端GT2的电位的控制下，控制所述第一节点N1与所述第一电压端V1之间连通或断开，并用于在所述第一控制信号和所述第二时钟信号端K2提供的第二时钟信号的控制下，控制所述第一节点N1与所述输入端I1之间连通或断开；
在图4所示的至少一实施例中，所述第一节点控制电路11还可以与第二节点N2电连接，所述第一节点控制电路11用于在所述第二时钟信号的控制下，控制所述输入端I1与所述第二节点N2之间连通或断开，并用于在所述第一控制信号的控制下，控制所述第二节点N2与所述第一节点N1之间连通或断开；
如图4所示，本公开至少一实施例所述的驱动电路还包括第一储能电路41和第二储能电路42；
所述第一储能电路41与所述第一输出控制端GT1电连接，用于储存电能，维持所述第一输出控制端GT1的电位；
所述第二储能电路42与所述第二输出控制端GT2电连接，用于储存电能，维持所述第二输出控制端GT2的电位。
本公开如图4所示的驱动电路的至少一实施例在工作时，显示周期包括先后设置的输入阶段、输出阶段和复位阶段；
在输入阶段，输入端I1提供输入信号，所述第一节点控制电路11在第二时钟信号的控制下，控制输入端I1提供所述输入信号至所述第二节点N2，所述第一节点控制电路11在第一控制信号的控制下，控制所述第二节点N2 与所述第一节点N1之间连通，以将所述输入信号写入所述第一节点N1；通断控制电路12在所述第二电压端V2提供的第二电压信号的控制下，控制所述第一节点N1与所述第一输出控制端GT1之间连通，以为第一储能电路41充电，第一输出电路13在所述第一输出控制端GT1的电位的控制下，控制所述驱动信号输出端G1与第一时钟信号端K1之间连通；
在复位阶段包括的第一复位时间段，输入端I1提供第一电压信号，第二时钟信号端K2提供的第二时钟信号的电位为第二电压；第一节点控制电路11在第二时钟信号的控制下，控制所述第二节点N2与所述输入端I1之间连通，并在第一控制信号的控制下，控制所述第二节点N2与所述第一节点N1之间连通，以使得所述第一节点N1的电位为第一电压，通断控制电路12在所述第二电压端V2提供的第二电压信号的控制下，控制所述第一节点N1与所述第一输出控制端GT1之间连通，为所述第一储能电路41充电，以使得所述第一输出控制端GT1的电位为第一电压；所述第一输出电路13在所述第一输出控制端GT1的电位的控制下，控制所述驱动信号输出端G1与第一时钟信号端K1之间断开；第二输出控制端控制电路21在第二时钟信号的控制下，控制所述第二输出控制端GT2与第二电压端之间连通，为所述第二储能电路42充电，以使得所述第二输出控制端GT2的电位为第二电压，第二输出电路22在所述第二输出控制端GT2的电位的控制下，控制所述驱动信号输出端G1与所述第一电压端V1之间连通；
在复位阶段包括的第二复位时间段，第二储能电路42维持所述第二输出控制端GT2的电位，第二输出电路22在所述第二输出控制端GT2的电位的控制下，控制所述驱动信号输出端G1与所述第一电压端V1之间连通；第一储能电路41维持所述第一输出控制端GT1的电位，第一输出电路13在第一输出控制端GT1的控制下，控制所述驱动信号输出端G1与所述第一时钟信号端K1之间断开。
可选的，所述第一节点控制电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
所述第一晶体管的控制极与所述第二时钟信号端电连接，所述第一晶体管的第一极与所述输入端电连接，所述第一晶体管的第二极与所述第二节点 电连接；
所述第二晶体管的控制极与所述第一时钟信号端电连接，所述第二晶体管的第一极与所述第二节点电连接；
所述第三晶体管的控制极与所述第二输出控制端电连接，所述第三晶体管的第一极与所述第二晶体管的第二极电连接，所述第三晶体管的第二极与所述第一电压端电连接；
所述第四晶体管的控制极与所述第一控制端电连接，所述第四晶体管的第一极与所述第二节点电连接，所述第四晶体管的第二极与所述第一节点电连接。
在本公开至少一实施例中，所述第四晶体管可以为双栅晶体管，以进一步减小漏电流。
可选的，所述第四晶体管的宽长比和所述第二晶体管的宽长比可以相等。
在具体实施时，所述第四晶体管和所述第二晶体管都为开关晶体管，所述第四晶体管的宽长比和所述第二晶体管的宽长比可以相等，以方便设计。但是在本公开至少一实施例中，所述第四晶体管的宽长比和所述第二晶体管的宽长比也可以不相等。
可选的，所述第一储能电路包括第一电容，所述第二储能电路包括第二电容；
所述第二电容的第一端与所述第二输出控制端电连接，所述第二电容的第二端与所述第一电压端电连接；
所述第一电容的第一端与所述第一输出控制端电连接，所述第一电容的第二端与所述驱动信号输出端电连接。
可选的，所述第二输出控制端控制电路包括第五晶体管和第六晶体管；
所述第五晶体管的控制极与所述第二时钟信号端电连接，所述第五晶体管的第一极与所述第二电压端电连接，所述第五晶体管的第二极与所述第二输出控制端电连接；
所述第六晶体管的控制极与所述第一节点电连接，所述第六晶体管的第一极与所述第二时钟信号端电连接，所述第六晶体管的第二极与所述第二输出控制端电连接。
可选的，所述通断控制电路包括第七晶体管；
所述第七晶体管的控制极与所述第二电压端电连接，所述第七晶体管的第一极与所述第一节点电连接，所述第七晶体管的第二极与所述第一输出控制端电连接。
可选的，所述第一输出电路包括第一输出晶体管，所述第二输出电路包括第二输出晶体管；
所述第一输出晶体管的控制极与所述第一输出控制端电连接，所述第一输出晶体管的第一极与所述第一时钟信号端电连接，所述第一输出晶体管的第二极与所述驱动信号输出端电连接；
所述第二输出晶体管的控制极与所述第二输出控制端电连接，所述第二输出晶体管的第一极与所述第一电压端电连接，所述第二输出晶体管的第二极与所述驱动信号输出端电连接。
可选的，所述第一输出晶体管的宽长比大于所述第二输出晶体管的宽长比。
在本公开至少一实施例中，所述第一输出晶体管和所述第二输出晶体管用于控制输出驱动信号，为了提升驱动能力，所述第一输出晶体管的宽长比和所述第二输出晶体管的宽长比都很大，由于所述第一输出晶体管用于输出低电压信号，而输出低电压信号更为困难，因此可以将所述第一输出晶体管的宽长比大于所述第二输出晶体管的宽长比，以保证驱动能力。
如图5所示，在图3所示的驱动电路的至少一实施例的基础上，所述第一节点控制电路11包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4；
所述第一晶体管M1的栅极与所述第二时钟信号端K2电连接，所述第一晶体管M1的源极与所述输入端I1电连接，所述第一晶体管M1的漏极与所述第一节点N1电连接；
所述第二晶体管M2的栅极与所述第一时钟信号端K1电连接，所述第二晶体管M2的源极与所述第一节点N1电连接；所述第二晶体管M2的漏极与所述第四晶体管M4的源极电连接；
所述第四晶体管M4的栅极与第三时钟信号端K3电连接，所述第四晶体 管M4的漏极与所述第三晶体管M3的源极电连接；
所述第三晶体管M3的栅极与所述第二输出控制端GT2电连接，所述第三晶体管M3的漏极与高电压端电连接；所述高电压端用于提供高电压信号V01；
所述第一储能电路41包括第一电容C1，所述第二储能电路42包括第二电容C2；
所述第二电容C2的第一端与所述第二输出控制端GT2电连接，所述第二电容C2的第二端与所述高电压端电连接；
所述第一电容C1的第一端与所述第一输出控制端GT1电连接，所述第一电容C1的第二端与所述驱动信号输出端G1电连接；
所述第二输出控制端控制电路21包括第五晶体管M5和第六晶体管M6；
所述第五晶体管M5的栅极与所述第二时钟信号端K2电连接，所述第五晶体管M5的源极与低电压端电连接，所述第五晶体管M5的漏极与所述第二输出控制端GT2电连接；所述低电压端用于提供低电压信号V02；
所述第六晶体管M6的栅极与所述第一节点N1电连接，所述第六晶体管M6的源极与所述第二时钟信号端K2电连接，所述第六晶体管M6的漏极与所述第二输出控制端GT2电连接；
所述通断控制电路12包括第七晶体管M7；
所述第七晶体管M7的栅极与所述低电压端电连接，所述第七晶体管M7的漏极与所述第一节点N1电连接，所述第七晶体管M7的源极与所述第一输出控制端GT1电连接；
所述第一输出电路13包括第一输出晶体管M01，所述第二输出电路22包括第二输出晶体管M02；
所述第一输出晶体管M01的栅极与所述第一输出控制端GT1电连接，所述第一输出晶体管M01的源极与所述第一时钟信号端K1电连接，所述第一输出晶体管M01的漏极与所述驱动信号输出端G1电连接；
所述第二输出晶体管M02的栅极与所述第二输出控制端GT2电连接，所述第二输出晶体管M02的漏极与所述高电压端电连接，所述第二输出晶体管M02的源极与所述驱动信号输出端G1电连接。
在图5所示的驱动电路的至少一实施例中，所有的晶体管都为p型晶体管，例如，所述晶体管可以为PMOS管(P型金属-氧化物-半导体晶体管)，但不以此为限。
在本公开至少一实施例中，所述驱动电路包括的晶体管也可以为n型晶体管，相应改变各控制信号即可。
可选的，本公开至少一实施例所述的驱动电路包括的晶体管可以都为p型晶体管，也可以都为n型晶体管，但不以此为限。
在图5所示的驱动电路的至少一实施例中，所述第一控制端为第三时钟信号端K3，但不以此为限。
在本公开至少一实施例中，所述第三时钟信号端K3提供的第三时钟信号与所述第一时钟信号端K1提供的第一时钟信号反相，以使得在显示周期，M2或M4关断，控制第一节点N1与第一电压端V1之间断开，防止漏电流影响第一节点N1的电位；但不以此为限。
如图6所示，本公开如图5所示的驱动电路的至少一实施例在工作时，显示周期可以包括先后设置的输入阶段S1、输出阶段S2和复位阶段，所述复位阶段包括先后设置的第一复位时间段S31和第二复位时间段S32；
在输入阶段S1，K1提供高电压信号，K2提供低电压信号，K3提供高电压信号，I1提供低电压信号，M1导通，N1的电位为低电压，M2关断，I1提供的低电压信号写入M6的栅极并为C2充电，M6导通，K2提供的低电压信号写入M02的栅极，M02打开，G1与所述高电压端之间连通；M7导通，I1提供的低电压信号经过M1和M7写入M01的栅极，为C1充电并打开M01，此时K1提供的高电压信号写入G1，G1输出高电压信号；
在输入阶段S1，GT1的电位和GT2的电位都为低电压；
在输入阶段S1，K3提供低电压信号，M4导通；
在输出阶段S2，I1提供高电压信号，K1提供低电压信号，K2提供高电压信号，K3提供高电压信号，M4断开，以断开高电压端与N1之间的通路，C1维持GT1的电位为低电压，M01导通，G1输出低电压信号；M7导通，N1的电位为低电压，M6打开，K2提供的高电压信号写入GT2，并为C2充电，使得GT1的电位为高电压，M02关断；
在第一复位时间段S31，I1提供高电压信号，K1提供高电压信号，K2提供低电压信号，K3提供低电压信号，M1和M5导通，低电压信号V02通过M5为C2充电，以使得GT2的电位为低电压，并打开M3和M02，G1输出高电压信号；M2关断，M1导通，以将I1提供的高电压信号写入N1，M7导通，以通过I1提供的高电压信号为C1充电，GT1的电位为高电压，M01关断；
在第二复位时间段S31，I1提供高电压信号，K1提供低电压信号，K2提供高电压信号，K3提供高电压信号，M2打开，C2维持GT2的电位为低电压，M3和M02导通，G1输出高电压信号，M4关断，C1维持GT1的电位为高电压，M6、M01、M1和M5关断。
如图7所示，在图3所示的驱动电路的至少一实施例的基础上，所述第一节点控制电路11包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4；
所述第一晶体管M1的栅极与所述第二时钟信号端K2电连接，所述第一晶体管M1的源极与所述输入端I1电连接，所述第一晶体管M1的漏极与所述第一节点N1电连接；
所述第二晶体管M2的栅极与所述第一时钟信号端K1电连接，所述第二晶体管M2的源极与所述第一节点N1电连接；所述第二晶体管M2的漏极与所述第三晶体管M3的源极电连接；
所述第三晶体管M3的栅极与所述第二输出控制端GT2电连接，所述第三晶体管M3的漏极与所述第四晶体管M4的源极电连接；
所述第四晶体管M4的栅极与第三时钟信号端K3电连接，所述第四晶体管M4的漏极与高电压端电连接；所述高电压端用于提供高电压信号V01；
所述第一储能电路41包括第一电容C1，所述第二储能电路42包括第二电容C2；
所述第二电容C2的第一端与所述第二输出控制端GT2电连接，所述第二电容C2的第二端与所述高电压端电连接；
所述第一电容C1的第一端与所述第一输出控制端GT1电连接，所述第一电容C1的第二端与所述驱动信号输出端G1电连接；
所述第二输出控制端控制电路21包括第五晶体管M5和第六晶体管M6；
所述第五晶体管M5的栅极与所述第二时钟信号端K2电连接，所述第五晶体管M5的源极与低电压端电连接，所述第五晶体管M5的漏极与所述第二输出控制端GT2电连接；所述低电压端用于提供低电压信号V02；
所述第六晶体管M6的栅极与所述第一节点N1电连接，所述第六晶体管M6的源极与所述第二时钟信号端K2电连接，所述第六晶体管M6的漏极与所述第二输出控制端GT2电连接；
所述通断控制电路12包括第七晶体管M7；
所述第七晶体管M7的栅极与所述低电压端电连接，所述第七晶体管M7的漏极与所述第一节点N1电连接，所述第七晶体管M7的源极与所述第一输出控制端GT1电连接；
所述第一输出电路13包括第一输出晶体管M01，所述第二输出电路22包括第二输出晶体管M02；
所述第一输出晶体管M01的栅极与所述第一输出控制端GT1电连接，所述第一输出晶体管M01的源极与所述第一时钟信号端K1电连接，所述第一输出晶体管M01的漏极与所述驱动信号输出端G1电连接；
所述第二输出晶体管M02的栅极与所述第二输出控制端GT2电连接，所述第二输出晶体管M02的漏极与所述高电压端电连接，所述第二输出晶体管M02的源极与所述驱动信号输出端G1电连接。
在图7所示的驱动电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在图7所示的驱动电路的至少一实施例中，所述第一控制端为第三时钟信号端K3，但不以此为限。
如图6所示，本公开如图7所示的驱动电路的至少一实施例在工作时，显示周期可以包括先后设置的输入阶段S1、输出阶段S2和复位阶段，所述复位阶段包括先后设置的第一复位时间段S31和第二复位时间段S32；
在输入阶段S1，K1提供高电压信号，K2提供低电压信号，K3提供高电压信号，I1提供低电压信号，M1导通，N1的电位为低电压，M2关断，I1提供的低电压信号写入M6的栅极并为C2充电，M6导通，K2提供的低电压 信号写入M02的栅极，M02打开，G1与所述高电压端之间连通；M7导通，I1提供的低电压信号经过M1和M7写入M01的栅极，为C1充电并打开M01，此时K1提供的高电压信号写入G1，G1输出高电压信号；
在输入阶段S1，GT1的电位和GT2的电位都为低电压；
在输入阶段S1，K3提供低电压信号，M4导通；
在输出阶段S2，I1提供高电压信号，K1提供低电压信号，K2提供高电压信号，K3提供高电压信号，M4断开，以断开高电压端与N1之间的通路，C1维持GT1的电位为低电压，M01导通，G1输出低电压信号；M7导通，N1的电位为低电压，M6打开，K2提供的高电压信号写入GT2，并为C2充电，使得GT1的电位为高电压，M02关断；
在第一复位时间段S31，I1提供高电压信号，K1提供高电压信号，K2提供低电压信号，K3提供低电压信号，M1和M5导通，低电压信号V02通过M5为C2充电，以使得GT2的电位为低电压，并打开M3和M02，G1输出高电压信号；M2关断，M1导通，以将I1提供的高电压信号写入N1，M7导通，以通过I1提供的高电压信号为C1充电，GT1的电位为高电压，M01关断；
在第二复位时间段S31，I1提供高电压信号，K1提供低电压信号，K2提供高电压信号，K3提供高电压信号，M2打开，C2维持GT2的电位为低电压，M3和M02导通，G1输出高电压信号，M4关断，C1维持GT1的电位为高电压，M6、M01、M1和M5关断。
如图8所示，在图3所示的驱动电路的至少一实施例的基础上，所述第一节点控制电路11包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4；
所述第一晶体管M1的栅极与所述第二时钟信号端K2电连接，所述第一晶体管M1的源极与所述输入端I1电连接，所述第一晶体管M1的漏极与所述第一节点N1电连接；
所述第四晶体管M4的栅极与第三时钟信号端K3电连接，所述第四晶体管M4的源极与所述第一节点N1电连接，所述第四晶体管M4的漏极与所述第二晶体管M2的源极电连接；
所述第二晶体管M2的栅极与所述第一时钟信号端K1电连接，所述第二晶体管M2的漏极与所述第三晶体管M3的源极电连接；
所述第三晶体管M3的栅极与所述第二输出控制端GT2电连接，所述第三晶体管M3的漏极与所述高电压端电连接；所述高电压端用于提供高电压信号V01；
所述第一储能电路41包括第一电容C1，所述第二储能电路42包括第二电容C2；
所述第二电容C2的第一端与所述第二输出控制端GT2电连接，所述第二电容C2的第二端与所述高电压端电连接；
所述第一电容C1的第一端与所述第一输出控制端GT1电连接，所述第一电容C1的第二端与所述驱动信号输出端G1电连接；
所述第二输出控制端控制电路21包括第五晶体管M5和第六晶体管M6；
所述第五晶体管M5的栅极与所述第二时钟信号端K2电连接，所述第五晶体管M5的源极与低电压端电连接，所述第五晶体管M5的漏极与所述第二输出控制端GT2电连接；所述低电压端用于提供低电压信号V02；
所述第六晶体管M6的栅极与所述第一节点N1电连接，所述第六晶体管M6的源极与所述第二时钟信号端K2电连接，所述第六晶体管M6的漏极与所述第二输出控制端GT2电连接；
所述通断控制电路12包括第七晶体管M7；
所述第七晶体管M7的栅极与所述低电压端电连接，所述第七晶体管M7的漏极与所述第一节点N1电连接，所述第七晶体管M7的源极与所述第一输出控制端GT1电连接；
所述第一输出电路13包括第一输出晶体管M01，所述第二输出电路22包括第二输出晶体管M02；
所述第一输出晶体管M01的栅极与所述第一输出控制端GT1电连接，所述第一输出晶体管M01的源极与所述第一时钟信号端K1电连接，所述第一输出晶体管M01的漏极与所述驱动信号输出端G1电连接；
所述第二输出晶体管M02的栅极与所述第二输出控制端GT2电连接，所述第二输出晶体管M02的漏极与所述高电压端电连接，所述第二输出晶体 管M02的源极与所述驱动信号输出端G1电连接。
在图8所示的驱动电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在图8所示的驱动电路的至少一实施例中，所述第一控制端为第三时钟信号端K3，但不以此为限。
如图6所示，本公开如图8所示的驱动电路的至少一实施例在工作时，显示周期可以包括先后设置的输入阶段S1、输出阶段S2和复位阶段，所述复位阶段包括先后设置的第一复位时间段S31和第二复位时间段S32；
在输入阶段S1，K1提供高电压信号，K2提供低电压信号，K3提供高电压信号，I1提供低电压信号，M1导通，N1的电位为低电压，M2关断，I1提供的低电压信号写入M6的栅极并为C2充电，M6导通，K2提供的低电压信号写入M02的栅极，M02打开，G1与所述高电压端之间连通；M7导通，I1提供的低电压信号经过M1和M7写入M01的栅极，为C1充电并打开M01，此时K1提供的高电压信号写入G1，G1输出高电压信号；
在输入阶段S1，GT1的电位和GT2的电位都为低电压；
在输入阶段S1，K3提供低电压信号，M4导通；
在输出阶段S2，I1提供高电压信号，K1提供低电压信号，K2提供高电压信号，K3提供高电压信号，M4断开，以断开高电压端与N1之间的通路，C1维持GT1的电位为低电压，M01导通，G1输出低电压信号；M7导通，N1的电位为低电压，M6打开，K2提供的高电压信号写入GT2，并为C2充电，使得GT1的电位为高电压，M02关断；
在第一复位时间段S31，I1提供高电压信号，K1提供高电压信号，K2提供低电压信号，K3提供低电压信号，M1和M5导通，低电压信号V02通过M5为C2充电，以使得GT2的电位为低电压，并打开M3和M02，G1输出高电压信号；M2关断，M1导通，以将I1提供的高电压信号写入N1，M7导通，以通过I1提供的高电压信号为C1充电，GT1的电位为高电压，M01关断；
在第二复位时间段S31，I1提供高电压信号，K1提供低电压信号，K2提供高电压信号，K3提供高电压信号，M2打开，C2维持GT2的电位为低 电压，M3和M02导通，G1输出高电压信号，M4关断，C1维持GT1的电位为高电压，M6、M01、M1和M5关断。
如图9所示，在图4所示的驱动电路的至少一实施例的基础上，所述第一节点控制电路11包括第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4；
所述第一晶体管M1的栅极与所述第二时钟信号端K2电连接，所述第一晶体管M1的源极与所述输入端I1电连接，所述第一晶体管M1的漏极与第二节点N2电连接；
所述第四晶体管M4的栅极与第三时钟信号端K3电连接，所述第四晶体管M4的源极与所述第二节点N2电连接，所述第四晶体管的漏极与所述第一节点N1电连接；
所述第二晶体管M2的栅极与所述第一时钟信号端K1电连接，所述第二晶体管M2的源极与所述第二节点N2电连接，所述第二晶体管M2的漏极与所述第三晶体管M3的源极电连接；
所述第三晶体管M3的栅极与所述第二输出控制端GT2电连接，所述第三晶体管M3的漏极与所述高电压端电连接；所述高电压端用于提供高电压信号V01；
所述第一储能电路41包括第一电容C1，所述第二储能电路42包括第二电容C2；
所述第二电容C2的第一端与所述第二输出控制端GT2电连接，所述第二电容C2的第二端与所述高电压端电连接；
所述第一电容C1的第一端与所述第一输出控制端GT1电连接，所述第一电容C1的第二端与所述驱动信号输出端G1电连接；
所述第二输出控制端控制电路21包括第五晶体管M5和第六晶体管M6；
所述第五晶体管M5的栅极与所述第二时钟信号端K2电连接，所述第五晶体管M5的源极与低电压端电连接，所述第五晶体管M5的漏极与所述第二输出控制端GT2电连接；所述低电压端用于提供低电压信号V02；
所述第六晶体管M6的栅极与所述第一节点N1电连接，所述第六晶体管M6的源极与所述第二时钟信号端K2电连接，所述第六晶体管M6的漏极与 所述第二输出控制端GT2电连接；
所述通断控制电路12包括第七晶体管M7；
所述第七晶体管M7的栅极与所述低电压端电连接，所述第七晶体管M7的漏极与所述第一节点N1电连接，所述第七晶体管M7的源极与所述第一输出控制端GT1电连接；
所述第一输出电路13包括第一输出晶体管M01，所述第二输出电路22包括第二输出晶体管M02；
所述第一输出晶体管M01的栅极与所述第一输出控制端GT1电连接，所述第一输出晶体管M01的源极与所述第一时钟信号端K1电连接，所述第一输出晶体管M01的漏极与所述驱动信号输出端G1电连接；
所述第二输出晶体管M02的栅极与所述第二输出控制端GT2电连接，所述第二输出晶体管M02的漏极与所述高电压端电连接，所述第二输出晶体管M02的源极与所述驱动信号输出端G1电连接。
在图9所示的驱动电路的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在图9所示的驱动电路的至少一实施例中，所述第一控制端为第三时钟信号端K3，但不以此为限。
如图6所示，本公开如图9所示的驱动电路的至少一实施例在工作时，显示周期可以包括先后设置的输入阶段S1、输出阶段S2和复位阶段，所述复位阶段包括先后设置的第一复位时间段S31和第二复位时间段S32；
在输入阶段S1，K1提供高电压信号，K2提供低电压信号，K3提供高电压信号，I1提供低电压信号，M1导通，M2关断，I1提供的低电压信号写入M6的栅极并为C2充电，M6导通，K2提供的低电压信号写入M02的栅极，M02打开，G1与所述高电压端之间连通；M7导通，I1提供的低电压信号经过M1和M7写入M01的栅极，为C1充电并打开M01，此时K1提供的高电压信号写入G1，G1输出高电压信号；
在输入阶段S1，GT1的电位和GT2的电位都为低电压；
在输入阶段S1，K3提供低电压信号，M4导通，N1的电位为低电压；
在输出阶段S2，I1提供高电压信号，K1提供低电压信号，K2提供高电 压信号，K3提供高电压信号，M4断开，以断开高电压端与N1之间的通路，C1维持GT1的电位为低电压，M01导通，G1输出低电压信号；M7导通，N1的电位为低电压，M6打开，K2提供的高电压信号写入GT2，并为C2充电，使得GT1的电位为高电压，M02关断；
在第一复位时间段S31，I1提供高电压信号，K1提供高电压信号，K2提供低电压信号，K3提供低电压信号，M1和M5导通，低电压信号V02通过M5为C2充电，以使得GT2的电位为低电压，并打开M3和M02，G1输出高电压信号；M2关断，M1导通，以将I1提供的高电压信号写入N1，M7导通，以通过I1提供的高电压信号为C1充电，GT1的电位为高电压，M01关断；
在第二复位时间段S31，I1提供高电压信号，K1提供低电压信号，K2提供高电压信号，K3提供高电压信号，M2打开，C2维持GT2的电位为低电压，M3和M02导通，G1输出高电压信号，M4关断，C1维持GT1的电位为高电压，M6、M01、M1和M5关断。
本公开实施例所述的驱动模组包括多级上述的驱动电路。
本公开实施例所述的驱动模组可以包括第一级驱动电路和第二级驱动电路；
所述第一级驱动电路的第一时钟信号端与第一时钟信号线SK1电连接，所述第一级驱动电路的第二时钟信号端与第二时钟信号线SK2电连接，所述第一级驱动电路的第三时钟信号端与第三时钟信号线SK3电连接；
所述第二级驱动电路的第一时钟信号端与第二时钟信号线SK2电连接，所述第一级驱动电路的第二时钟信号端与第一时钟信号线SK2电连接，所述第一级驱动电路的第三时钟信号端与第三时钟信号线SK4电连接；
图10中，示出了第一时钟信号线SK1提供的时钟信号的波形图、第二时钟信号线SK2提供的时钟信号的波形图、第三时钟信号线SK3提供的时钟信号的波形图、第四时钟信号线SK4提供的时钟信号的波形图、第一级驱动电路电连接的输入端I1提供的输入信号的波形图、第一级驱动电路输出的驱动信号G11的波形图，以及，第二级驱动电路输出的驱动信号G12的波形图。
在本公开至少一实施例中，所述第一时钟信号线SK1提供的时钟信号， 与所述第三时钟信号线SK3提供的时钟信号可以相互反相，但不以此为限。
本公开实施例所述的驱动方法应用于上述的驱动电路，显示周期包括输出阶段；
所述驱动方法包括：在输出阶段，第一节点控制电路在第一控制信号的控制下，控制第一节点与第一电压端之间断开，通断控制电路在第二电压信号的控制下，控制第一节点与第一输出控制端之间连通，第一输出电路在第一输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一时钟信号端之间连通。
本公开实施例所述的驱动方法通过第一节点控制电路在输出阶段，在第一控制信号的控制下，控制第一节点与第一电压端之间断开，从而避免在输出阶段，第一节点的电位和第一输出控制端的电位被控制为第一电压，进而使得在输出阶段，第一输出电路能够在所述第一输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一时钟信号端之间连通，以正常输出驱动信号。
在本公开至少一实施例中，所述驱动电路还包括第二输出控制端控制电路和第二输出电路；显示周期还包括设置于所述输出阶段之前的输入阶段；所述驱动方法还包括：
在输入阶段，第二输出控制端控制电路在第二时钟信号的控制下，控制第二输出控制端与第二电压端之间连通，以使得第二输出电路在所述第二输出控制端的电位的控制下，控制驱动信号输出端与所述第一电压端之间连通；
在输出阶段，所述第二输出控制端控制电路在所述第一节点的电位的控制下，控制所述第二输出控制端与所述第二时钟信号端之间连通，以使得所述第二输出电路在所述第二输出控制端的电位的控制下，控制驱动信号输出端与所述第一电压端之间断开。
在具体实施时，所述驱动电路还包括第二输出控制端控制电路和第二输出电路，第二输出控制端控制电路控制第二输出控制端的电位，第二输出电路在第二输出控制端的电位的控制下，控制驱动信号输出端与第一电压端之间连通或断开。
可选的，所述第一节点控制电路还分别与第二时钟信号端和输入端电连 接；所述驱动电路还包括第一储能电路和第二储能电路；所述驱动方法还包括：
在输入阶段，输入端提供输入信号，所述第一节点控制电路在第二时钟信号的控制下，控制输入端提供所述输入信号至所述第一节点；通断控制电路在所述第二电压端提供的第二电压信号的控制下，控制所述第一节点与所述第一输出控制端之间连通，以为第一储能电路充电，第一输出电路在所述第一输出控制端的电位的控制下，控制所述驱动信号输出端与第一时钟信号端之间连通。
在具体实施时，第一节点控制电路能够在输入阶段，控制将输入信号写入第一节点，通断控制电路在第二电压信号的控制下，控制第一节点与第一输出控制端之间连通，在输入阶段，第一输出电路在第一输出控制端的电位的控制下，控制所述驱动信号输出端与第一时钟信号端之间连通。
在本公开至少一实施例中，显示周期还包括设置于所述输出阶段之后的复位阶段；所述复位阶段包括第一复位时间段和第二复位时间段；所述驱动方法还包括：
在第一复位时间段，输入端提供第一电压信号，第二时钟信号端提供的第二时钟信号的电位为第二电压；第一节点控制电路在第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通，以使得所述第一节点的电位为第一电压，通断控制电路在所述第二电压端提供的第二电压信号的控制下，控制所述第一节点与所述第一输出控制端之间连通，为所述第一储能电路充电，以使得所述第一输出控制端的电位为第一电压；所述第一输出电路在所述第一输出控制端的电位的控制下，控制所述驱动信号输出端与第一时钟信号端之间断开；第二输出控制端控制电路在第二时钟信号的控制下，控制所述第二输出控制端与第二电压端之间连通，为所述第二储能电路充电，以使得所述第二输出控制端的电位为第二电压，第二输出电路在所述第二输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一电压端之间连通，以使得所述驱动信号输出端输出第一电压信号；
在第二复位时间段，第二储能电路维持所述第二输出控制端的电位，第二输出电路在所述第二输出控制端的电位的控制下，控制所述驱动信号输出 端与所述第一电压端之间连通；第一储能电路维持所述第一输出控制端的电位，第一输出电路在第一输出控制端的控制下，控制所述驱动信号输出端与所述第一时钟信号端之间断开。
本公开实施例所述的显示装置包括上述的驱动模组。
本公开至少一实施例所述的显示装置可以为硅基OLED(有机发光二极管)显示装置，但不以此为限。
本公开至少一实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (21)

  1. 一种驱动电路，包括驱动信号输出端，第一节点控制电路、通断控制电路和第一输出电路；
    所述第一节点控制电路分别与第一控制端、所述第一电压端、所述第一节点、第二输出控制端和第一时钟信号端电连接，用于在所述第一控制端提供的第一控制信号的控制下，控制所述第一节点与所述第一电压端之间断开或连通，并在所述第一时钟信号端提供的第一时钟信号的控制下，控制所述第一节点与所述第一电压端之间连通或断开；所述第一控制端与所述第一时钟信号端不相同；
    所述通断控制电路分别与第二电压端、所述第一节点和第一输出控制端电连接，用于在所述第二电压端提供的第二电压信号的控制下，控制所述第一节点与所述第一输出控制端之间连通或断开；
    所述第一输出电路分别与第一输出控制端、第一时钟信号端和所述驱动信号输出端电连接，用于在所述第一输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一时钟信号端之间连通或断开。
  2. 如权利要求1所述的驱动电路，其中，所述第一节点控制电路包括的晶体管都为p型晶体管；或者，所述第一节点控制电路包括的晶体管都为n型晶体管；
    所述第一控制信号与所述第一时钟信号相互反相。
  3. 如权利要求1所述的驱动电路，其中，还包括第二输出控制端控制电路和第二输出电路；
    所述第二输出控制端控制电路分别与所述第一节点、所述第二输出控制端、第二时钟信号端和第二电压端电连接，用于在所述第一节点的电位的控制下，控制所述第二输出控制端与所述第二时钟信号端之间连通或断开，在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第二输出控制端与所述第二电压端之间连通或断开；
    所述第二输出电路分别与第二输出控制端、第一电压端和所述驱动信号输出端电连接，用于在所述第二输出控制端的电位的控制下，控制所述驱动 信号输出端与所述第一电压端之间连通或断开。
  4. 如权利要求1所述的驱动电路，其中，所述第一节点控制电路还分别与第二输出控制端、第二时钟信号端和输入端电连接，用于在所述第二输出控制端的电位的控制下，控制所述第一节点与所述第一电压端之间连通或断开，并用于在所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通或断开。
  5. 如权利要求4所述的驱动电路，其中，所述第一节点控制电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
    所述第一晶体管的控制极与所述第二时钟信号端电连接，所述第一晶体管的第一极与所述输入端电连接，所述第一晶体管的第二极与所述第一节点电连接；
    所述第二晶体管的控制极与所述第一时钟信号端电连接，所述第二晶体管的第一极与所述第一节点电连接；
    所述第三晶体管的控制极与所述第二输出控制端电连接，所述第三晶体管的第一极与所述第二晶体管的第二极电连接，所述第三晶体管的第二极与所述第一电压端电连接；
    所述第一电压端通过所述第四晶体管与所述第三晶体管的第二极电连接；或者，所述第三晶体管的第一极通过所述第四晶体管与所述第二晶体管的第二极电连接；或者，所述第二晶体管的第一极通过所述第四晶体管与所述第一节点电连接；
    所述第四晶体管的控制极与所述第一控制端电连接。
  6. 如权利要求1所述的驱动电路，其中，所述第一节点控制电路还分别与第二输出控制端、第二时钟信号端和输入端电连接，用于在所述第二输出控制端的电位的控制下，控制所述第一节点与所述第一电压端之间连通或断开，并用于在所述第一控制信号和所述第二时钟信号端提供的第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通或断开。
  7. 如权利要求6所述的驱动电路，其中，所述第一节点控制电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
    所述第一晶体管的控制极与所述第二时钟信号端电连接，所述第一晶体 管的第一极与所述输入端电连接，所述第一晶体管的第二极与所述第二节点电连接；
    所述第二晶体管的控制极与所述第一时钟信号端电连接，所述第二晶体管的第一极与所述第二节点电连接；
    所述第三晶体管的控制极与所述第二输出控制端电连接，所述第三晶体管的第一极与所述第二晶体管的第二极电连接，所述第三晶体管的第二极与所述第一电压端电连接；
    所述第四晶体管的控制极与所述第一控制端电连接，所述第四晶体管的第一极与所述第二节点电连接，所述第四晶体管的第二极与所述第一节点电连接。
  8. 如权利要求5或7所述的驱动电路，其中，所述第四晶体管为双栅晶体管。
  9. 如权利要求8所述的驱动电路，其中，所述第四晶体管的宽长比等于所述第二晶体管的宽长比。
  10. 如权利要求1至7中任一权利要求所述的驱动电路，其中，还包括第一储能电路和第二储能电路；
    所述第一储能电路与所述第一输出控制端电连接，用于储存电能；
    所述第二储能电路与所述第二输出控制端电连接，用于储存电能。
  11. 如权利要求10所述的驱动电路，其中，所述第一储能电路包括第一电容，所述第二储能电路包括第二电容；
    所述第二电容的第一端与所述第二输出控制端电连接，所述第二电容的第二端与所述第一电压端电连接；
    所述第一电容的第一端与所述第一输出控制端电连接，所述第一电容的第二端与所述驱动信号输出端电连接。
  12. 如权利要求3所述的驱动电路，其中，所述第二输出控制端控制电路包括第五晶体管和第六晶体管；
    所述第五晶体管的控制极与所述第二时钟信号端电连接，所述第五晶体管的第一极与所述第二电压端电连接，所述第五晶体管的第二极与所述第二输出控制端电连接；
    所述第六晶体管的控制极与所述第一节点电连接，所述第六晶体管的第一极与所述第二时钟信号端电连接，所述第六晶体管的第二极与所述第二输出控制端电连接。
  13. 如权利要求1所述的驱动电路，其中，所述通断控制电路包括第七晶体管；
    所述第七晶体管的控制极与所述第二电压端电连接，所述第七晶体管的第一极与所述第一节点电连接，所述第七晶体管的第二极与所述第一输出控制端电连接。
  14. 如权利要求3所述的驱动电路，其中，所述第一输出电路包括第一输出晶体管，所述第二输出电路包括第二输出晶体管；
    所述第一输出晶体管的控制极与所述第一输出控制端电连接，所述第一输出晶体管的第一极与所述第一时钟信号端电连接，所述第一输出晶体管的第二极与所述驱动信号输出端电连接；
    所述第二输出晶体管的控制极与所述第二输出控制端电连接，所述第二输出晶体管的第一极与所述第一电压端电连接，所述第二输出晶体管的第二极与所述驱动信号输出端电连接。
  15. 如权利要求14所述的驱动电路，其中，所述第一输出晶体管的宽长比大于所述第二输出晶体管的宽长比。
  16. 一种驱动模组，包括多级如权利要求1至15中任一权利要求所述的驱动电路。
  17. 一种驱动方法，应用于如权利要求1至15中任一权利要求所述的驱动电路，显示周期包括输出阶段；
    所述驱动方法包括：在输出阶段，第一节点控制电路在第一控制信号的控制下，控制第一节点与第一电压端之间断开，通断控制电路在第二电压信号的控制下，控制第一节点与第一输出控制端之间连通，第一输出电路在第一输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一时钟信号端之间连通。
  18. 如权利要求17所述的驱动方法，其中，所述驱动电路还包括第二输出控制端控制电路和第二输出电路；显示周期还包括设置于所述输出阶段之 前的输入阶段；所述驱动方法还包括：
    在输入阶段，第二输出控制端控制电路在第二时钟信号的控制下，控制第二输出控制端与第二电压端之间连通，以使得第二输出电路在所述第二输出控制端的电位的控制下，控制驱动信号输出端与所述第一电压端之间连通；
    在输出阶段，所述第二输出控制端控制电路在所述第一节点的电位的控制下，控制所述第二输出控制端与所述第二时钟信号端之间连通，以使得所述第二输出电路在所述第二输出控制端的电位的控制下，控制驱动信号输出端与所述第一电压端之间断开。
  19. 如权利要求18所述的驱动方法，其中，所述第一节点控制电路还分别与第二时钟信号端和输入端电连接；所述驱动电路还包括第一储能电路和第二储能电路；所述驱动方法还包括：
    在输入阶段，输入端提供输入信号，所述第一节点控制电路在第二时钟信号的控制下，控制输入端提供所述输入信号至所述第一节点；通断控制电路在所述第二电压端提供的第二电压信号的控制下，控制所述第一节点与所述第一输出控制端之间连通，以为第一储能电路充电，第一输出电路在所述第一输出控制端的电位的控制下，控制所述驱动信号输出端与第一时钟信号端之间连通。
  20. 如权利要求19所述的驱动方法，其中，显示周期还包括设置于所述输出阶段之后的复位阶段；所述复位阶段包括第一复位时间段和第二复位时间段；所述驱动方法还包括：
    在第一复位时间段，输入端提供第一电压信号，第二时钟信号端提供的第二时钟信号的电位为第二电压；第一节点控制电路在第二时钟信号的控制下，控制所述第一节点与所述输入端之间连通，以使得所述第一节点的电位为第一电压，通断控制电路在所述第二电压端提供的第二电压信号的控制下，控制所述第一节点与所述第一输出控制端之间连通，为所述第一储能电路充电，以使得所述第一输出控制端的电位为第一电压；所述第一输出电路在所述第一输出控制端的电位的控制下，控制所述驱动信号输出端与第一时钟信号端之间断开；第二输出控制端控制电路在第二时钟信号的控制下，控制所述第二输出控制端与第二电压端之间连通，为所述第二储能电路充电，以使 得所述第二输出控制端的电位为第二电压，第二输出电路在所述第二输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一电压端之间连通；
    在第二复位时间段，第二储能电路维持所述第二输出控制端的电位，第二输出电路在所述第二输出控制端的电位的控制下，控制所述驱动信号输出端与所述第一电压端之间连通；第一储能电路维持所述第一输出控制端的电位，第一输出电路在第一输出控制端的控制下，控制所述驱动信号输出端与所述第一时钟信号端之间断开。
  21. 一种显示装置，包括如权利要求16所述的驱动模组。
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CN113362766A (zh) * 2021-07-02 2021-09-07 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置

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