WO2022068385A1 - 显示面板、其驱动方法及显示装置 - Google Patents

显示面板、其驱动方法及显示装置 Download PDF

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Publication number
WO2022068385A1
WO2022068385A1 PCT/CN2021/110674 CN2021110674W WO2022068385A1 WO 2022068385 A1 WO2022068385 A1 WO 2022068385A1 CN 2021110674 W CN2021110674 W CN 2021110674W WO 2022068385 A1 WO2022068385 A1 WO 2022068385A1
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Prior art keywords
transistor
pole
switch transistor
circuit
driving
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PCT/CN2021/110674
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English (en)
French (fr)
Inventor
邱远游
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/786,158 priority Critical patent/US11869429B2/en
Publication of WO2022068385A1 publication Critical patent/WO2022068385A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present application relates to the field of display technology, and more particularly, to a display panel, a driving method thereof, and a display device.
  • the display screen with high refresh rate has become the mainstream development trend of the current display screen, and the scheme design to achieve high refresh rate is still relatively limited.
  • the odd-even design of the gate drive circuit is one of them, but the corresponding need to use dual data lines Therefore, the number of film layers in the display panel is increased, the number of mask (MASK) processes is increased, and the cost is increased.
  • a display panel provided by an embodiment of the present application includes: a plurality of pixel circuits arranged in a matrix, a plurality of data lines, a plurality of write control lines, a plurality of compensation control lines, and a third line connected to the plurality of compensation control lines a drive circuit, and a second drive circuit connected to the plurality of write control lines;
  • Each column of the pixel circuits corresponds to one of the data lines, and each row of the pixel circuits corresponds to one of the write control lines and one of the compensation control lines;
  • the pixel circuit includes: a driving transistor, a first switching transistor, a second switching transistor, a first capacitor and a second capacitor; wherein: the first switching transistor is used to make all the The gate of the drive transistor is short-circuited with the second pole of the drive transistor; the second switch transistor is used to write the signal of the corresponding data line under the control of the corresponding write control line the first pole of the drive transistor; the first capacitor is connected between the gate of the drive transistor and the first power supply voltage terminal, and the second capacitor is connected between the first pole of the drive transistor and the between the first power supply voltage terminals;
  • the first driving circuit is used for sequentially outputting compensation control signals to the pixel circuits in each row through the plurality of compensation control lines
  • the second driving circuit is used for sequentially outputting the compensation control signals to the pixel circuits in each row through the plurality of write control lines.
  • the pixel circuit outputs a write control signal
  • the pulse width of the compensation control signal is equal to N times the pulse width of the write control signal, the write control signals on two adjacent write control lines do not overlap, and the adjacent two write control signals do not overlap.
  • the overlapping time of the compensation control signal on the compensation control line is equal to (N ⁇ 1)/N of the pulse width of the compensation control signal, where N is an integer greater than 1.
  • N is equal to 2.
  • the ratio of the capacitance value of the second capacitor to the capacitance value of the first capacitor is greater than or equal to 0.5 and less than or equal to 1.5.
  • the first pole of the first switching transistor is connected to the gate of the driving transistor, and the second pole of the first switching transistor is connected to the first pole of the driving transistor.
  • the diodes are connected, and the gate of the first switching transistor is connected to the compensation control line;
  • the first pole of the second switch transistor is connected to the data line
  • the second pole of the second switch transistor is connected to the first pole of the driving transistor
  • the gate of the second switch transistor is connected to the Write control line connection.
  • the display panel further includes a plurality of light-emitting control lines and a third driving circuit connected to the plurality of light-emitting control lines;
  • Each of the light-emitting control lines corresponds to a row of the pixel circuit, and the pixel circuit further includes a third switch transistor and a fourth switch transistor;
  • the first pole of the third switch transistor is connected to the first power supply voltage terminal, the second pole of the third switch transistor is connected to the first pole of the driving transistor, and the gate of the third switch transistor connected with the light-emitting control line;
  • the first pole of the fourth switch transistor is connected to the second pole of the driving transistor, the second pole of the fourth switch transistor is connected to the anode of the light emitting device, and the gate of the fourth switch transistor is connected to the Lighting control line connection;
  • the third driving circuit is used for sequentially outputting light-emitting control signals to the pixel circuits in each row through the plurality of light-emitting control lines.
  • the display panel further includes a plurality of light-emitting control lines and a third driving circuit connected to the plurality of light-emitting control lines;
  • Each of the light-emitting control lines corresponds to a row of the pixel circuit, and the pixel circuit further includes a third switch transistor and a fourth switch transistor;
  • the first pole of the third switching transistor is connected to the first power supply voltage terminal, the second pole of the third switching transistor is connected to the second pole of the driving transistor, and the gate of the third switching transistor is connected connected with the light-emitting control line;
  • the first pole of the fourth switch transistor is connected to the first pole of the driving transistor, the second pole of the fourth switch transistor is connected to the anode of the light emitting device, and the gate of the fourth switch transistor is connected to the Lighting control line connection;
  • the third driving circuit is used for sequentially outputting light-emitting control signals to the pixel circuits in each row through the plurality of light-emitting control lines.
  • the pixel circuit further includes a fifth switch transistor
  • the first pole of the fifth switch transistor is connected to the first reset signal terminal
  • the second pole of the fifth switch transistor is connected to the gate of the driving transistor
  • the gate of the fifth switch transistor is connected to the first reset signal terminal. reset the control terminal connection
  • the first reset control terminal of the pixel circuit of the nth row is connected to the write control line corresponding to the pixel circuit of the n-1th row.
  • the pixel circuit further includes a sixth switch transistor
  • the first pole of the sixth switch transistor is connected to the second reset signal terminal, the second pole of the sixth switch transistor is connected to the anode of the light emitting device, and the gate of the sixth switch transistor is connected to the second reset signal terminal control terminal connection;
  • the second reset control terminal of the pixel circuit of the nth row is connected to the write control line corresponding to the pixel circuit of the n-1th row, or the second reset control terminal of the pixel circuit of the nth row is connected to the write control line corresponding to the pixel circuit of the n-1th row.
  • the write control lines corresponding to the pixel circuits in the nth row are connected.
  • the first driving circuit includes a first driving sub-circuit and a second driving sub-circuit; wherein,
  • the first driving sub-circuit is connected to the odd-numbered compensation control line
  • the second driving sub-circuit is connected to the even-numbered compensation control lines.
  • the embodiments of the present application also provide a driving method applied to any of the above-mentioned display panels, including:
  • the second driving circuit progressively supplies the pixel circuits in the nth row to the n+N ⁇ 1th row row by row.
  • the write control signal is provided.
  • the embodiments of the present application also provide a display device, including a control circuit and any display panel provided by the embodiments of the present application;
  • the control circuit is connected to the display panel for controlling the display panel to display.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 3 is a circuit timing diagram corresponding to the pixel circuit provided by the embodiment of the present application.
  • FIG. 4 is another circuit timing diagram corresponding to the pixel circuit provided by the embodiment of the present application.
  • FIG. 5 is another schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 6 is another schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 7 is another circuit timing diagram corresponding to the pixel circuit provided by the embodiment of the present application.
  • FIG. 8 is another schematic structural diagram of a display panel according to an embodiment of the present application.
  • a display panel provided by an embodiment of the present application includes: a plurality of pixel circuits pix arranged in a matrix, a plurality of data lines D(m), a plurality of write control lines S(n), a plurality of a compensation control line G(n), a first drive circuit 10 connected to a plurality of compensation control lines G(n), and a second drive circuit 20 connected to a plurality of write control lines S(n);
  • Each column of pixel circuits pix corresponds to a data line D(m), and each row of pixel circuits pix corresponds to a write control line S(n) and a compensation control line G(n);
  • the pixel circuit pix includes: a driving transistor T0, a first switching transistor T1, a second switching transistor T2, a first capacitor C1 and a second capacitor C2; wherein: the first switching transistor T1 is used in the corresponding Under the control of the compensation control line G(n), the gate of the drive transistor T0 is short-circuited with the second pole N2 of the drive transistor T0; the second switch transistor T2 is used to be under the control of the corresponding write control line S(n) Write the signal of the corresponding data line D(m) into the first pole N1 of the driving transistor T0; the first capacitor C1 is connected between the gate N1 of the driving transistor T0 and the first power supply voltage terminal VDD, and the second capacitor C2 is connected between the first pole N1 of the driving transistor T0 and the first power supply voltage terminal VDD;
  • the first driving circuit 10 is used for sequentially outputting compensation control signals to each row of pixel circuits pix through a plurality of compensation control lines G(n), and the second driving circuit 20 is used for sequentially outputting compensation control signals to each row of pixels through a plurality of write control lines S(n).
  • the circuit pix outputs the write control signal;
  • the pulse width of the compensation control signal on the compensation control line G(n) is equal to N times the pulse width of the write control signal on the write control line S(n).
  • the compensation control line is used to control the first switch transistor, and the second capacitor and the compensation control signals on the two adjacent compensation control lines have an overlapping time to ensure that the N3 node of the pixel circuit is sufficiently charged. high refresh rate.
  • the pulse width of the compensation control signal used to control the first switch transistor is equal to the write control signal used to control the second switch transistor.
  • the on-time of the first switch transistor in each pixel circuit is longer than the on-time of the second switch transistor, when the second switch transistor is on, the second capacitor can be used for charging, and when When the second switch transistor is turned off, the second capacitor is used to continue to charge the N3 node through the turned-on first switch transistor, so as to ensure that the N3 node is sufficiently charged.
  • the voltage of the N1 node is used to charge the N3 node, and the voltage of the N1 node is provided by the second switch transistor.
  • the second switch transistor is turned off, the N1 node is turned off.
  • the voltage of the second capacitor is maintained by the second capacitor, so the capacitance value of the second capacitor cannot be too small, or the potential of the N3 node cannot be maintained before the first switching transistor is turned off.
  • the capacitance value of the second capacitor cannot be too large, or Before the first switching transistor is turned off, the potential of the N3 node cannot reach an ideal value.
  • the ratio of the capacitance value of the second capacitor to the capacitance value of the first capacitor is greater than or equal to 0.5 and less than or equal to 1.5, for example, the capacitance value of the second capacitor and the capacitance of the first capacitor value is about the same.
  • the second capacitor is charged to the N3 node, and when the second capacitor is discharged to the voltage of the N2 node lower than the N3 node voltage, the second capacitor is discharged to the N3 node.
  • the capacitor cannot continue to charge the N3 node, so the time for the second capacitor to charge the N3 node is limited.
  • the difference between the pulse width of the compensation control signal and the pulse width of the write control signal should not be too large.
  • the turn-on time of the second switch transistors in the pixel circuits of two adjacent rows needs to be separated by a period of time, that is, as shown in FIG.
  • the incoming control signals do not overlap to avoid misalignment of data signal transmission on the data line D(m).
  • the first pole of the first switching transistor T1 is connected to the gate of the driving transistor T0, and the second pole of the first switching transistor T1 is connected to the driving transistor The second pole of T0 is connected, and the gate of the first switching transistor T1 is connected to the compensation control line G(n);
  • the first pole of the second switch transistor T2 is connected to the data line
  • the second pole of the second switch transistor T2 is connected to the first pole of the driving transistor T0
  • the gate of the second switch transistor T2 is connected to the write control line S(n) connect.
  • the present application is applicable to any display panel having the pixel circuit structure shown in FIG. 4 .
  • other devices are generally included in the pixel circuit.
  • the display panel provided by the present application further includes a plurality of light-emitting control lines and a third driving circuit connected to the plurality of light-emitting control lines; each light-emitting control line corresponds to a row of pixel circuits, and the third driving circuit uses The light-emitting control signals are sequentially output to the pixel circuits of each row through the plurality of light-emitting control lines EM(n).
  • the pixel circuit further includes a third switch transistor T3 and a fourth switch transistor T4;
  • the first pole of the third switching transistor T3 is connected to the first power supply voltage terminal VDD
  • the second pole of the third switching transistor T3 is connected to the first pole N1 of the driving transistor T0
  • the The gate is connected to the light-emitting control line EM(n)
  • the first pole of the fourth switching transistor T4 is connected to the second pole N2 of the driving transistor T0
  • the second pole of the fourth switching transistor T4 is connected to the anode of the light-emitting device oled
  • the first pole of the fourth switching transistor T4 is connected to the anode of the light-emitting device oled.
  • the gate of the four-switch transistor T4 is connected to the light emission control line EM(n).
  • the first pole of the third switch transistor T3 is connected to the first power supply voltage terminal VDD
  • the second pole of the third switch transistor T3 is connected to the second pole N2 of the driving transistor T0
  • the third switch transistor The gate of T3 is connected to the light-emitting control line EM(n)
  • the first pole of the fourth switching transistor T4 is connected to the first pole N1 of the driving transistor T0
  • the second pole of the fourth switching transistor T4 is connected to the anode of the light-emitting device oled
  • the gate of the fourth switching transistor T4 is connected to the light-emitting control line EM(n).
  • the pixel circuit further includes a fifth switch transistor T5;
  • the first pole of the fifth switch transistor T5 is connected to the first reset signal terminal Vinit1, the second pole of the fifth switch transistor T5 is connected to the gate of the driving transistor T0, and the gate of the fifth switch transistor T5 is connected to the first reset control terminal connect;
  • the first reset control terminal of the pixel circuit in the nth row is connected to the write control line S(n-1) corresponding to the pixel circuit in the n-1th row.
  • the pixel circuit further includes a sixth switch transistor T6; the first pole of the sixth switch transistor T6 is connected to the second reset signal terminal Vinit2, The second pole of the sixth switch transistor T6 is connected to the anode of the light-emitting device oled, and the gate of the sixth switch transistor T6 is connected to the second reset control terminal; as shown in FIG. 5 , the second reset control terminal of the pixel circuit in the nth row is connected to the write control line S(n-1) corresponding to the pixel circuit of the n-1th row; or, as shown in FIG. The input control line S(n) is connected.
  • the corresponding timing diagram is shown in FIG. 7 , in the t1 stage, the fifth switching transistor T5 is turned on, and the potential of the N3 node is Vinit1 .
  • the sixth switch transistor is turned on, and the potential Vinit2 of the anode of the light-emitting device oled is turned on.
  • stage t2 the first switching transistor T1, the second switching transistor T2 and the driving transistor T0 are turned on, the potential of the N2 node is VData(n), and VData(n) is written to N3 through the driving transistor T0 and the first switching transistor T1 node, and VData(n) charges the second capacitor C2.
  • the sixth switch transistor is turned on, and the potential Vinit2 of the anode of the light-emitting device oled is turned on.
  • the second capacitor C2 is turned off until the potential of the N3 node becomes Vdata+Vth, and the driving transistor T0 is turned off, where Vth is the threshold voltage of the driving transistor T0.
  • the second capacitor C2 discharges quickly, and the charging time of the N3 node is short. If the capacitance value of the second capacitor C2 is too large, the second capacitor C2 discharges slowly, and the potential of the N3 node cannot be charged to Vdata+Vth.
  • the third switching transistor T3 and the fourth switching transistor T4 are turned on, the potential of the N3 node is still Vdata+Vth, and the driving transistor T0 is in a saturated state.
  • the display panel includes a display area AA and a frame area BB, wherein the first driving circuit 10 and the second driving circuit 20 are both located in the frame area.
  • the first driving circuit includes a first driving sub-circuit 101 and a second driving sub-circuit 102;
  • the compensation control line G(n) is connected;
  • the second driving sub-circuit 102 is connected with the even-numbered compensation control line G(n).
  • the first driving sub-circuit 101 and the second driving sub-circuit 102 are respectively located on both sides of the compensation control line G(n).
  • an embodiment of the present application also provides a driving method applied to any of the above-mentioned display panels, including:
  • the second driving circuit provides the write control signal to the pixel circuits of the nth row to the n+N-1th row row by row.
  • the embodiments of the present application also provide a display device, including a control circuit and any of the above-mentioned display panels provided by the embodiments of the present application; the control circuit is connected to the display panel for controlling the display panel to display.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the compensation control line is used to control the first switching transistor, and the pixel circuit can be guaranteed by the second capacitor and the compensation control signals on the adjacent two compensation control lines having an overlap time.
  • the N3 node has a high refresh rate on a fully charged basis.
  • the pulse width of the compensation control signal used to control the first switch transistor is equal to the write control signal used to control the second switch transistor.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请公开了一种显示面板、其驱动方法及显示装置，其中显示面板包括：矩阵排列的多个像素电路，多条数据线、多条写入控制线、多条补偿控制线、与多条补偿控制线连接的第一驱动电路、与多条写入控制线连接的第二驱动电路；每一列像素电路对应一条数据线，每一行像素电路对应一条写入控制线和一条补偿控制线；第一驱动电路通过多条补偿控制线依次向各行像素电路输出补偿控制信号，第二驱动电路通过多条写入控制线依次向各行像素电路输出写入控制信号；补偿控制信号的脉宽等于写入控制信号的脉宽的N倍，相邻两条写入控制线上的写入控制信号不交叠，相邻两条补偿控制线上的补偿控制信号的交叠时间等于补偿控制信号脉宽的(N-1)/N。

Description

显示面板、其驱动方法及显示装置
相关申请的交叉引用
本申请要求在2020年9月30日提交中国专利局、申请号为202011060095.8、发明名称为“显示面板、其驱动方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤指一种显示面板、其驱动方法及显示装置。
背景技术
高刷新频率的显示屏成为当前显示屏的主流发展趋势，而实现高刷新频率的方案设计还比较有限，其中，栅极驱动电路采用奇偶设计就是其中一种，但是对应的就需要采用双数据线的设计，从而导致显示面板中膜层数增加，掩膜(MASK)工艺次数增加，进而成本增加。
发明内容
本申请实施例提供的一种显示面板、其驱动方法及显示装置，具体方案如下：
本申请实施例提供的一种显示面板，包括：矩阵排列的多个像素电路，多条数据线、多条写入控制线、多条补偿控制线、与所述多条补偿控制线连接的第一驱动电路、与所述多条写入控制线连接的第二驱动电路；
每一列所述像素电路对应一条所述数据线，每一行所述像素电路对应一条所述写入控制线和一条所述补偿控制线；
所述像素电路包括：驱动晶体管、第一开关晶体管、第二开关晶体管、第一电容和第二电容；其中：所述第一开关晶体管用于在对应的所述补偿控制线的控制下使所述驱动晶体管的栅极与所述驱动晶体管的第二极短接；所 述第二开关晶体管用于在对应的所述写入控制线的控制下将其对应的所述数据线的信号写入所述驱动晶体管的第一极；所述第一电容连接于所述驱动晶体管的栅极与第一电源电压端之间，所述第二电容连接于所述驱动晶体管的第一极与所述第一电源电压端之间；
所述第一驱动电路用于通过所述多条补偿控制线依次向各行所述像素电路输出补偿控制信号，所述第二驱动电路用于通过所述多条写入控制线依次向各行所述像素电路输出写入控制信号；
所述补偿控制信号的脉宽等于所述写入控制信号的脉宽的N倍，相邻两条所述写入控制线上的所述写入控制信号不交叠，相邻两条所述补偿控制线上的所述补偿控制信号的交叠时间等于所述补偿控制信号脉宽的(N-1)/N，N为大于1的整数。
可选地，在本申请提供的显示面板中，N等于2。
可选地，在本申请提供的显示面板中，所述第二电容的电容值与所述第一电容的电容值的比值大于或等于0.5，且小于或等于1.5。
可选地，在本申请提供的显示面板中，所述第一开关晶体管的第一极与所述驱动晶体管的栅极连接，所述第一开关晶体管的第二极与所述驱动晶体管的第二极连接，所述第一开关晶体管的栅极与所述补偿控制线连接；
所述第二开关晶体管的第一极与所述数据线连接，所述第二开关晶体管的第二极与所述驱动晶体管的第一极连接，所述第二开关晶体管的栅极与所述写入控制线连接。
可选地，在本申请提供的显示面板中，所述显示面板还包括多条发光控制线和与所述多条发光控制线连接的第三驱动电路；
每一条所述发光控制线对应一行所述像素电路，所述像素电路中还包括第三开关晶体管和第四开关晶体管；
所述第三开关晶体管的第一极与所述第一电源电压端连接，所述第三开关晶体管的第二极与所述驱动晶体管的第一极连接，所述第三开关晶体管的栅极与所述发光控制线连接；
所述第四开关晶体管的第一极与所述驱动晶体管的第二极连接，所述第四开关晶体管的第二极与发光器件的阳极连接，所述第四开关晶体管的栅极与所述发光控制线连接；
所述第三驱动电路用于通过所述多条发光控制线依次向各行所述像素电路输出发光控制信号。
可选地，在本申请提供的显示面板中，所述显示面板还包括多条发光控制线和与所述多条发光控制线连接的第三驱动电路；
每一条所述发光控制线对应一行所述像素电路，所述像素电路中还包括第三开关晶体管和第四开关晶体管；
所述第三开关晶体管的第一极与所述第一电源电压端连接，所述第三开关晶体管的第二极与所述驱动晶体管的第二极连接，所述第三开关晶体管的栅极与所述发光控制线连接；
所述第四开关晶体管的第一极与所述驱动晶体管的第一极连接，所述第四开关晶体管的第二极与发光器件的阳极连接，所述第四开关晶体管的栅极与所述发光控制线连接；
所述第三驱动电路用于通过所述多条发光控制线依次向各行所述像素电路输出发光控制信号。
可选地，在本申请提供的显示面板中，所述像素电路还包括第五开关晶体管；
所述第五开关晶体管的第一极与第一复位信号端连接，所述第五开关晶体管的第二极与所述驱动晶体管的栅极连接，所述第五开关晶体管的栅极与第一复位控制端连接；
所述第n行像素电路的第一复位控制端与所述第n-1行像素电路对应的所述写入控制线连接。
可选地，在本申请提供的显示面板中，所述像素电路还包括第六开关晶体管；
所述第六开关晶体管的第一极与第二复位信号端连接，所述第六开关晶 体管的第二极与所述发光器件的阳极连接，所述第六开关晶体管的栅极与第二复位控制端连接；
所述第n行像素电路的第二复位控制端与所述第n-1行像素电路对应的所述写入控制线连接，或者，所述第n行像素电路的第二复位控制端与所述第n行像素电路对应的所述写入控制线连接。
可选地，在本申请提供的显示面板中，所述第一驱动电路包括第一驱动子电路和第二驱动子电路；其中，
所述第一驱动子电路与第奇数条所述补偿控制线连接；
所述第二驱动子电路与第偶数条所述补偿控制线连接。
相应地，本申请实施例还提供了一种应用于上述任一种显示面板的驱动方法，包括：
所述第一驱动电路在向第n行所述像素电路提供所述补偿控制信号的时间段内，所述第二驱动电路逐行向第n行至第n+N-1行所述像素电路提供所述写入控制信号。
相应地，本申请实施例还提供了一种显示装置，包括控制电路以及本申请实施例提供的任一种显示面板；
所述控制电路与所述显示面板连接，用于控制所述显示面板进行显示。
附图说明
图1为本申请实施例提供的显示面板的一种结构示意图；
图2为本申请实施例提供的像素电路的一种结构示意图；
图3为本申请实施例提供的像素电路对应的一种电路时序图；
图4为本申请实施例提供的像素电路对应的另一种电路时序图；
图5为本申请实施例提供的像素电路的另一种结构示意图；
图6为本申请实施例提供的像素电路的又一种结构示意图；
图7为本申请实施例提供的像素电路对应的又一种电路时序图；
图8为本申请实施例提供的显示面板的另一种结构示意图。
具体实施方式
为使本申请的上述目的、特征和优点能够更为明显易懂，下面将结合附图和实施例对本申请做进一步说明。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本申请更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。
需要说明的是，在以下描述中阐述了具体细节以便于充分理解本申请。但是本申请能够以多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广。因此本申请不受下面公开的具体实施方式的限制。说明书后续描述为实施本申请的较佳实施方式，然所述描述乃以说明本申请的一般原则为目的，并非用以限定本申请的范围。本申请的保护范围当视所附权利要求所界定者为准。
下面结合附图，对本申请实施例提供的显示面板、其驱动方法及显示装置进行具体说明。
本申请实施例提供的一种显示面板，如图1所示，包括：矩阵排列的多个像素电路pix，多条数据线D(m)、多条写入控制线S(n)、多条补偿控制线G(n)、与多条补偿控制线G(n)连接的第一驱动电路10、与多条写入控制线S(n)连接的第二驱动电路20；
每一列像素电路pix对应一条数据线D(m)，每一行像素电路pix对应一条写入控制线S(n)和一条补偿控制线G(n)；
如图2所示，该像素电路pix包括：驱动晶体管T0、第一开关晶体管T1、第二开关晶体管T2、第一电容C1和第二电容C2；其中：第一开关晶体管T1用于在对应的补偿控制线G(n)的控制下使驱动晶体管T0的栅极与驱动晶体管T0的第二极N2短接；第二开关晶体管T2用于在对应的写入控制线S(n)的 控制下将其对应的数据线D(m)的信号写入驱动晶体管T0的第一极N1；第一电容C1连接于驱动晶体管T0的栅极N1与第一电源电压端VDD之间，第二电容C2连接于驱动晶体管T0的第一极N1与第一电源电压端VDD之间；
第一驱动电路10用于通过多条补偿控制线G(n)依次向各行像素电路pix输出补偿控制信号，第二驱动电路20用于通过多条写入控制线S(n)依次向各行像素电路pix输出写入控制信号；
如图3所示，补偿控制线G(n)上的补偿控制信号的脉宽等于写入控制线S(n)上写入控制信号的脉宽的N倍，相邻两条写入控制线S(n)上的写入控制信号不交叠，相邻两条补偿控制线G(n)上的补偿控制信号的交叠时间等于补偿控制信号脉宽的(N-1)/N，N为大于1的整数，图3以N＝3为例进行说明。
在本申请中，补偿控制线用于控制第一开关晶体管，通过第二电容以及相邻两条补偿控制线上的补偿控制信号有交叠时间可以保证像素电路的N3节点充电充足的基础上有高的刷新频率。为了避免相邻两行像素电路在N3节点的充电交叠时间时出现数据写入错位，使用于控制第一开关晶体管的补偿控制信号的脉宽等于用于控制第二开关晶体管的写入控制信号的脉宽的N倍，且相邻两条写入控制线上的写入控制信号不交叠，即虽然相邻两行像素电路的第一开关晶体管的打开时间有交叠，但是相邻两行像素电路的第二开关晶体管的打开时间是不交叠的，从而每一列像素电路仅需对应一条数据线，不用增加显示面板中膜层数量和MASK工艺数量，可以节约成本。
在具体实施时，在本申请中，虽然每一像素电路中第一开关晶体管的打开时间大于第二开关晶体管的打开时间，但是在第二开关晶体管打开时，可以利用第二电容进行充电，当第二开关晶体管截止时，利用第二电容通过导通的第一开关晶体管继续对N3节点进行充电，从而保证N3节点充电充足。
在具体实施时，当像素电路中第一开关晶体管打开时，利用N1节点的电压对N3节点进行充电，N1节点的电压时由第二开关晶体管提供的，当第二开关晶体管截止时，N1节点的电压由第二电容来维持，因此第二电容的电容值不能太小，要不在第一开关晶体管截止之前，不能维持N3节点的电位，当 然，第二电容的电容值不能太大，要不在第一开关晶体管截止之前，N3节点的电位不能达到理想值。
因此，可选地，在本申请中，第二电容的电容值与第一电容的电容值的比值大于或等于0.5，且小于或等于1.5，例如第二电容的电容值与第一电容的电容值约相同。
在本申请提供的显示面板中，当像素电路中的第二开关晶体管截止后，由第二电容向N3节点进行充电，当第二电容放电至N2节点的电压低于N3节点电压时，第二电容不能继续对N3节点进行充电，因此第二电容向N3节点进行充电的时间是有限的。为了避免在第一开关晶体管截止之前，第二电容就放电结束，补偿控制信号的脉宽与写入控制信号的脉宽的差距不能太大，可选地，如图4所示，N＝2，即补偿控制信号的脉宽等于写入控制信号的脉宽的2倍。
进一步地，在本申请中，相邻两行像素电路中的第二开关晶体管的打开时间需要间隔一段时间，即如图4所示，相邻两条写入控制线S(n)上的写入控制信号不交叠，以避免数据线D(m)上的数据信号发送错位。
在具体实施时，在本申请提供的显示面板中，如图2所示，第一开关晶体管T1的第一极与驱动晶体管T0的栅极连接，第一开关晶体管T1的第二极与驱动晶体管T0的第二极连接，第一开关晶体管T1的栅极与补偿控制线G(n)连接；
第二开关晶体管T2的第一极与数据线连接，第二开关晶体管T2的第二极与驱动晶体管T0的第一极连接，第二开关晶体管T2的栅极与写入控制线S(n)连接。
需要说明的是，本申请适应于具有如4所示的像素电路结构的任何显示面板。在具体实施时，为了优化显示面板的品质，像素电路中一般还包括其它器件。
在具体实施时，在本申请提供的显示面板中，还包括多条发光控制线和与多条发光控制线连接的第三驱动电路；每一条发光控制线对应一行像素电 路，第三驱动电路用于通过多条发光控制线EM(n)依次向各行像素电路输出发光控制信号。如图5和图6所示，像素电路中还包括第三开关晶体管T3和第四开关晶体管T4；
如图5所示，第三开关晶体管T3的第一极与第一电源电压端VDD连接，第三开关晶体管T3的第二极与驱动晶体管T0的第一极N1连接，第三开关晶体管T3的栅极与发光控制线EM(n)连接；第四开关晶体管T4的第一极与驱动晶体管T0的第二极N2连接，第四开关晶体管T4的第二极与发光器件oled的阳极连接，第四开关晶体管T4的栅极与发光控制线EM(n)连接。
或者，如图6所示，第三开关晶体管T3的第一极与第一电源电压端VDD连接，第三开关晶体管T3的第二极与驱动晶体管T0的第二极N2连接，第三开关晶体管T3的栅极与发光控制线EM(n)连接；第四开关晶体管T4的第一极与驱动晶体管T0的第一极N1连接，第四开关晶体管T4的第二极与发光器件oled的阳极连接，第四开关晶体管T4的栅极与发光控制线EM(n)连接。
可选地，在本申请提供的显示面板中，如图5和图6所示，像素电路还包括第五开关晶体管T5；
第五开关晶体管T5的第一极与第一复位信号端Vinit1连接，第五开关晶体管T5的第二极与驱动晶体管T0的栅极连接，第五开关晶体管T5的栅极与第一复位控制端连接；
第n行像素电路的第一复位控制端与第n-1行像素电路对应的写入控制线S(n-1)连接。
可选地，在本申请提供的显示面板中，如图5和图6所示，像素电路还包括第六开关晶体管T6；第六开关晶体管T6的第一极与第二复位信号端Vinit2连接，第六开关晶体管T6的第二极与发光器件oled的阳极连接，第六开关晶体管T6的栅极与第二复位控制端连接；如图5所示，第n行像素电路的第二复位控制端与第n-1行像素电路对应的写入控制线S(n-1)连接；或者，如图6所示，第n行像素电路的第二复位控制端与第n行像素电路对应的写入控制线S(n)连接。
具体地，以图5和图6所示的像素电路为例，其对应的时序图如图7所示，在t1阶段，第五开关晶体管T5导通，N3节点的电位为Vinit1。图5所示像素电路中第六开关晶体管导通，发光器件oled阳极的电位Vinit2。在t2阶段，第一开关晶体管T1、第二开关晶体管T2和驱动晶体管T0导通，N2节点的电位为VData(n)，VData(n)通过驱动晶体管T0和第一开关晶体管T1写入至N3节点，并且VData(n)对第二电容C2进行充电。图6所示像素电路中第六开关晶体管导通，发光器件oled阳极的电位Vinit2。在t3阶段，第二电容C2直到N3节点的电位变为Vdata+Vth，驱动晶体管T0截止，其中，Vth为驱动晶体管T0的阈值电压，在该阶段中，如果第二电容C2的电容值太小，第二电容C2快速放电，N3节点充电时间较短，如果第二电容C2的电容值太大，第二电容C2放电较慢，N3节点的电位不能充电至Vdata+Vth。在t4阶段，第三开关晶体管T3和第四开关晶体管T4导通，N3节点的电位仍为Vdata+Vth，驱动晶体管T0工作处于饱和状态，根据饱和状态电流特性可知，流过驱动晶体管T0且用于驱动发光器件oled发光的工作电流I oled满足公式：I oled＝K(V gs–Vth) 2＝K[VData(n)+Vth-VDD–Vth] 2＝K(VData(n)-VDD) 2，其中K为结构参数，相同结构中此数值相对稳定，可以算作常量。
在具体实施时，在本申请中，如图1所示，显示面板包括显示区域AA和边框区域BB，其中第一驱动电路10和第二驱动电路20均位于边框区域。
可选地，在本申请提供的显示面板中，如图8所示，第一驱动电路包括第一驱动子电路101和第二驱动子电路102；其中，第一驱动子电路101与第奇数条补偿控制线G(n)连接；第二驱动子电路102与第偶数条补偿控制线G(n)连接。第一驱动子电路101和第二驱动子电路102分别位于补偿控制线G(n)的两侧。
基于同一发明构思，本申请实施例还提供了一种应用于上述任一种显示面板的驱动方法，包括：
第一驱动电路在向第n行像素电路提供补偿控制信号的时间段内，第二驱动电路逐行向第n行至第n+N-1行像素电路提供写入控制信号。
基于同一发明构思，本申请实施例还提供了一种显示装置，包括控制电路以及本申请实施例提供的上述任一种显示面板；控制电路与显示面板连接，用于控制显示面板进行显示。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本申请提供的显示面板、其驱动方法及显示装置，补偿控制线用于控制第一开关晶体管，通过第二电容以及相邻两条补偿控制线上的补偿控制信号有交叠时间可以保证像素电路的N3节点充电充足的基础上有高的刷新频率。为了避免相邻两行像素电路在N3节点的充电交叠时间时出现数据写入错位，使用于控制第一开关晶体管的补偿控制信号的脉宽等于用于控制第二开关晶体管的写入控制信号的脉宽的N倍，且相邻两条写入控制线上的写入控制信号不交叠，即虽然相邻两行像素电路的第一开关晶体管的打开时间有交叠，但是相邻两行像素电路的第二开关晶体管的打开时间是不交叠的，从而每一列像素电路仅需对应一条数据线，不用增加显示面板中膜层数量和MASK工艺数量，可以节约成本。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (11)

  1. 一种显示面板，其中，包括：矩阵排列的多个像素电路，多条数据线、多条写入控制线、多条补偿控制线、与所述多条补偿控制线连接的第一驱动电路、与所述多条写入控制线连接的第二驱动电路；
    每一列所述像素电路对应一条所述数据线，每一行所述像素电路对应一条所述写入控制线和一条所述补偿控制线；
    所述像素电路包括：驱动晶体管、第一开关晶体管、第二开关晶体管、第一电容和第二电容；其中：所述第一开关晶体管用于在对应的所述补偿控制线的控制下使所述驱动晶体管的栅极与所述驱动晶体管的第二极短接；所述第二开关晶体管用于在对应的所述写入控制线的控制下将其对应的所述数据线的信号写入所述驱动晶体管的第一极；所述第一电容连接于所述驱动晶体管的栅极与第一电源电压端之间，所述第二电容连接于所述驱动晶体管的第一极与所述第一电源电压端之间；
    所述第一驱动电路用于通过所述多条补偿控制线依次向各行所述像素电路输出补偿控制信号，所述第二驱动电路用于通过所述多条写入控制线依次向各行所述像素电路输出写入控制信号；
    所述补偿控制信号的脉宽等于所述写入控制信号的脉宽的N倍，相邻两条所述写入控制线上的所述写入控制信号不交叠，相邻两条所述补偿控制线上的所述补偿控制信号的交叠时间等于所述补偿控制信号脉宽的(N-1)/N，N为大于1的整数。
  2. 如权利要求1所述的显示面板，其中，N等于2。
  3. 如权利要求1所述的显示面板，其中，所述第二电容的电容值与所述第一电容的电容值的比值大于或等于0.5，且小于或等于1.5。
  4. 如权利要求1所述的显示面板，其中，所述第一开关晶体管的第一极与所述驱动晶体管的栅极连接，所述第一开关晶体管的第二极与所述驱动晶体管的第二极连接，所述第一开关晶体管的栅极与所述补偿控制线连接；
    所述第二开关晶体管的第一极与所述数据线连接，所述第二开关晶体管的第二极与所述驱动晶体管的第一极连接，所述第二开关晶体管的栅极与所述写入控制线连接。
  5. 如权利要求1所述的显示面板，其中，所述显示面板还包括多条发光控制线和与所述多条发光控制线连接的第三驱动电路；
    每一条所述发光控制线对应一行所述像素电路，所述像素电路中还包括第三开关晶体管和第四开关晶体管；
    所述第三开关晶体管的第一极与所述第一电源电压端连接，所述第三开关晶体管的第二极与所述驱动晶体管的第一极连接，所述第三开关晶体管的栅极与所述发光控制线连接；
    所述第四开关晶体管的第一极与所述驱动晶体管的第二极连接，所述第四开关晶体管的第二极与发光器件的阳极连接，所述第四开关晶体管的栅极与所述发光控制线连接；
    所述第三驱动电路用于通过所述多条发光控制线依次向各行所述像素电路输出发光控制信号。
  6. 如权利要求1所述的显示面板，其中，所述显示面板还包括多条发光控制线和与所述多条发光控制线连接的第三驱动电路；
    每一条所述发光控制线对应一行所述像素电路，所述像素电路中还包括第三开关晶体管和第四开关晶体管；
    所述第三开关晶体管的第一极与所述第一电源电压端连接，所述第三开关晶体管的第二极与所述驱动晶体管的第二极连接，所述第三开关晶体管的栅极与所述发光控制线连接；
    所述第四开关晶体管的第一极与所述驱动晶体管的第一极连接，所述第四开关晶体管的第二极与发光器件的阳极连接，所述第四开关晶体管的栅极与所述发光控制线连接；
    所述第三驱动电路用于通过所述多条发光控制线依次向各行所述像素电路输出发光控制信号。
  7. 如权利要求5或6所述的显示面板，其中，所述像素电路还包括第五开关晶体管；
    所述第五开关晶体管的第一极与第一复位信号端连接，所述第五开关晶体管的第二极与所述驱动晶体管的栅极连接，所述第五开关晶体管的栅极与第一复位控制端连接；
    所述第n行像素电路的第一复位控制端与所述第n-1行像素电路对应的所述写入控制线连接。
  8. 如权利要求5或6所述的显示面板，其中，所述像素电路还包括第六开关晶体管；
    所述第六开关晶体管的第一极与第二复位信号端连接，所述第六开关晶体管的第二极与所述发光器件的阳极连接，所述第六开关晶体管的栅极与第二复位控制端连接；
    所述第n行像素电路的第二复位控制端与所述第n-1行像素电路对应的所述写入控制线连接，或者，所述第n行像素电路的第二复位控制端与所述第n行像素电路对应的所述写入控制线连接。
  9. 如权利要求1-6任一项所述的显示面板，其中，所述第一驱动电路包括第一驱动子电路和第二驱动子电路；其中，
    所述第一驱动子电路与第奇数条所述补偿控制线连接；
    所述第二驱动子电路与第偶数条所述补偿控制线连接。
  10. 一种应用于如权利要求1-9任一项所述的显示面板的驱动方法，其中，包括：
    所述第一驱动电路在向第n行所述像素电路提供所述补偿控制信号的时间段内，所述第二驱动电路逐行向第n行至第n+N-1行所述像素电路提供所述写入控制信号。
  11. 一种显示装置，其中，包括控制电路以及如权利要求1-9任一项所述的显示面板；
    所述控制电路与所述显示面板连接，用于控制所述显示面板进行显示。
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