WO2022017024A1 - 显示面板及其驱动方法 - Google Patents

显示面板及其驱动方法 Download PDF

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Publication number
WO2022017024A1
WO2022017024A1 PCT/CN2021/098854 CN2021098854W WO2022017024A1 WO 2022017024 A1 WO2022017024 A1 WO 2022017024A1 CN 2021098854 W CN2021098854 W CN 2021098854W WO 2022017024 A1 WO2022017024 A1 WO 2022017024A1
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Prior art keywords
signal
data signal
level period
clock control
control signal
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PCT/CN2021/098854
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English (en)
French (fr)
Inventor
冯雷
吕水明
胡维博
吴国强
郑中基
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/921,320 priority Critical patent/US12033576B2/en
Publication of WO2022017024A1 publication Critical patent/WO2022017024A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a driving method thereof.
  • OLED Organic Light Emitting Diode
  • the OLED display screen is controlled to light up by scanning and writing data signals line by line.
  • the difference between the data signals stored in the adjacent two lines in the display screen is large, the potential of the power supply signal will change, which will cause the data signal to change due to the influence of the power supply signal during the writing process, resulting in brightness differences. display effect.
  • Embodiments of the present disclosure provide a method for driving a display panel, the display panel comprising:
  • a plurality of pixel circuits for controlling the pixels to emit light for display
  • a gate driving circuit located at one side of the pixel circuit, for outputting a gate scanning signal to the pixel circuit
  • the driving method includes:
  • the control clock signal terminal inputs a clock control signal to the gate driving circuit, so that the gate driving circuit outputs the gate scanning signal and controls the data signal
  • the data signal output from the terminal is written into the pixel circuit of the row;
  • the valid level period of the clock control signal falls within the valid level period of the data signal
  • the start time of the valid level period of the data signal is at least earlier than the valid level period of the clock control signal
  • the start time is 1 ⁇ s-2 ⁇ s.
  • the duty cycle of the active level period of the data signal in the pixel scanning period of the row is greater than 50%.
  • the duty cycle of the active level period of the clock control signal in the pixel scanning period of the row is less than 50%.
  • the duration of the active level period of the clock control signal is less than or equal to half of the duration of the active level period of the data signal.
  • the end time of the active level period of the clock control signal is earlier than the end time of the active level period of the data signal.
  • the end time of the active level period of the clock control signal is at least 1 ⁇ s-2 ⁇ s earlier than the end time of the active level period of the data signal.
  • the duration of the active level period of the data signal is 4 ⁇ s-6 ⁇ s.
  • the duration of the active level period of the clock control signal is 2 ⁇ s-3 ⁇ s.
  • the start time of the active level period of the data signal is at least 1 ⁇ s later than the start time of the pixel scanning period of the row.
  • the end time of the active level period of the data signal is at least 1 ⁇ s earlier than the end time of the pixel scanning period of the row.
  • Embodiments of the present disclosure provide a display panel, including:
  • a plurality of pixel circuits for controlling the pixels to emit light for display
  • a gate driving circuit located at one side of the pixel circuit, for outputting a gate scanning signal to the pixel circuit
  • a driving chip connected to the gate driving circuit and the pixel circuit respectively, and used for outputting control signals to the gate driving circuit and the pixel circuit;
  • the driving chip controls a clock signal terminal to input a clock control signal to the gate driving circuit, so that the gate driving circuit outputs a gate scanning signal, and control the data signal output from the data signal terminal to be written into the pixel circuit of the row;
  • the valid level period of the clock control signal falls within the valid level period of the data signal
  • the start time of the valid level period of the data signal is at least earlier than the valid level period of the clock control signal
  • the start time is 1 ⁇ s-2 ⁇ s.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of a shift register provided by an embodiment of the present disclosure
  • Fig. 3 is the timing diagram of the shift register shown in Fig. 2;
  • FIG. 4 is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 5 is a timing diagram of the pixel circuit shown in FIG. 4;
  • FIG. 7 is a sequence diagram provided by an embodiment of the present disclosure.
  • FIG. 8 is one of the simulation timing diagrams of the related art
  • FIG. 9 is one of the simulation sequence diagrams provided by the embodiment of the present disclosure.
  • FIG. 10 is one of the simulation timing diagrams of the related art
  • FIG. 11 is the second simulation sequence diagram provided by the embodiment of the present disclosure.
  • OLED display panel is a display panel with organic light-emitting diodes as light-emitting devices.
  • OLED is a new generation of display technology. Compared with liquid crystal display panels (Liquid Crystal Display, LCD for short), the thickness of OLED panels can be controlled within 1mm. Thinner and lighter in weight.
  • the OLED screen also has a wide viewing angle that LCD does not have, which can achieve a large viewing range without distortion of the picture. Its response speed is one thousandth of that of an LCD screen.
  • the OLED screen is resistant to low temperature and can display content normally at -40°C. It has the advantages of thinness, high brightness, low power consumption, fast response, high definition, good flexibility, and high luminous efficiency. It occupies an increasingly important role in the display field. Location.
  • An OLED device includes an anode, a light-emitting layer, and a cathode.
  • the anode, the light-emitting layer and the cathode form a sandwich structure. After an electric field is generated between the anode and the anode, the electrons and holes will move to the light-emitting layer and recombine into excitons in the light-emitting layer. The excitons excite the light-emitting molecules and finally generate visible light.
  • Embodiments of the present disclosure provide a display panel, which is an OLED display panel, and may specifically be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display panel which is an OLED display panel, and may specifically be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • a display panel provided by an embodiment of the present disclosure includes: a plurality of pixels not shown in the figure, a gate driving circuit 100 , a pixel circuit 200 and a driving chip 300 .
  • each pixel is connected to a pixel circuit, and the pixel circuit 200 drives the pixel to emit light.
  • the pixels in the OLED display panel are organic light emitting diode devices.
  • the OLED devices may include red OLED devices, green OLED devices, and blue OLED devices, which can be driven by signal control of the gate driving circuit 100 and the pixel circuit 200
  • the corresponding pixels are displayed in full color.
  • a white OLED device with a color filter can also be used to achieve full-color display, which is not limited here.
  • the pixels in the OLED display panel are distributed in the display area, each pixel is connected to a pixel circuit 200 correspondingly, and a gate driving circuit 100 is provided in the non-display area on one side of the display area.
  • the gate driving circuit 100 is used for outputting a gate scanning signal to the pixel circuit 200, and writing a data signal into the pixel circuit 200 under the control of the gate scanning signal.
  • the gate driving circuit includes mutually cascaded shift registers, the input signal of the shift register of the first pole is provided by the driving chip, and in addition, the shift register of each stage is provided by the driving chip.
  • the output signal is used as the output signal of the next stage shift register.
  • the output end of each stage of the shift register is connected to a gate signal line 11 , and the gate signal line 11 is used for transmitting the gate scanning signal for controlling the pixels of the row.
  • FIG. 2 is an equivalent circuit diagram of a shift register provided by an embodiment of the present disclosure
  • FIG. 3 is a timing diagram of the shift register shown in FIG. 2 .
  • the shift register provided by the embodiment of the present disclosure includes 8 transistors and 2 capacitors.
  • the 8 transistors are p-type transistors, and the low level signal is the active level.
  • the specific working principle is as follows:
  • the first clock control signal provided on the first clock signal terminal CB is a low level signal
  • the second clock control signal provided on the second clock signal terminal CK is a high level signal
  • the input voltage signal terminal STV The input signal Vin provided above is a low level signal, for example, the input signal Vin is equal to the first power supply signal VL.
  • the second transistor T2 Since the first clock control signal is a low level signal, the second transistor T2 is turned on, and the input signal is transmitted to the third node N3 through the second transistor T2. Since the second transistor T2 transmits a low level signal with threshold loss, the voltage of the third node N3 is Vin-Vth2, ie VL-Vth2, where Vth2 represents the threshold voltage of the second transistor T2. Since the gate of the sixth transistor T6 receives the first power supply signal VL, the sixth transistor T6 is in an on state, whereby the voltage VL-Vth2 is transmitted to the first node N1 via the sixth transistor T6. For example, the threshold voltage of the sixth transistor T6 is represented as Vth6.
  • the voltage of the first node N1 is VL-VthN1, where VthN1 is the higher of Vth2 and Vth6. small one.
  • the voltage of the first node N1 can control the eighth transistor T8 to be turned on, and the second clock control signal is written to the output terminal G(n) through the eighth transistor T8 as an output signal, that is, in the input stage t1, the output signal is high.
  • a flat second clock control signal that is, the second power supply signal VH.
  • the first transistor T1 is turned on, and the first power signal VL is transmitted to the second node N2 through the first transistor T1. Since the voltage of the third node N3 is VL -Vth2, the seventh transistor T7 is turned on, and the low-level first clock control signal is transmitted to the second node N2 through the seventh transistor T7.
  • the threshold voltage of the seventh transistor T7 is represented as Vth7
  • the threshold voltage of the first transistor T1 is represented as Vth1.
  • the first clock control signal provided on the first clock signal terminal CB is a high-level signal
  • the second clock control signal provided on the second clock signal terminal CK is a low-level signal
  • the input voltage signal terminal STV The input signal Vin provided above is a high level signal.
  • the eighth transistor T8 is turned on, and the second clock control signal is written to the output terminal G(n) via the eighth transistor T8 as an output signal.
  • the voltage at one end of the second capacitor C2 connected to the output terminal G(n) is the second power supply signal VH
  • the voltage at the end of the second capacitor C2 connected to the first node N1 is VL-VthN1
  • the voltage at the end of the second capacitor C2 connected to the output terminal G(n) becomes VL
  • the voltage at the end of the second capacitor C2 connected to the first node N1 becomes 2VL -VthN1-VH, that is, the voltage of the first node N1 becomes 2VL-VthN1-VH
  • the sixth transistor T6 is turned off
  • the eighth transistor T8 can be better turned on
  • the output signal is the first power supply signal VL.
  • the first clock control signal is a high level signal, so that both the second transistor T2 and the first transistor T1 are turned off.
  • the voltage of the third node N3 is still VL-VthN1
  • the seventh transistor T7 is turned on, and the high-level first clock control signal is transmitted to the second node N2 through the seventh transistor T7, that is, the voltage of the second node N2 is the second The power supply signal VH, whereby the third transistor T3 and the fourth transistor T4 are both turned off. Since the second clock control signal is a low level signal, the fifth transistor T5 is turned on.
  • the first clock control signal provided on the first clock signal terminal CB and the second clock control signal provided on the second clock signal terminal CK are both high-level signals, and the input voltage provided on the signal terminal STV is input.
  • the signal Vin is a high level signal.
  • the eighth transistor T8 is turned on, and the second clock control signal is written to the output terminal G(n) through the eighth transistor T8 as an output signal.
  • the output signal is a high-level second clock control signal, namely the second clock control signal.
  • Power supply signal VH Due to the bootstrap effect of the second capacitor C2, the voltage of the first node N1 becomes VL-VthN1.
  • the first clock control signal is a high level signal, so that both the second transistor T2 and the first transistor T1 are turned off.
  • the voltage of the first node N1 becomes VL-VthN1, at this time, the sixth transistor T6 is turned on, the voltage of the third node N3 is also VL-VthN1, the seventh transistor T7 is turned on, and the high-level first clock control signal
  • the voltage transmitted to the second node N2 via the seventh transistor T7 that is, the voltage of the second node N2 is the second power supply signal VH, so that both the third transistor T3 and the fourth transistor T4 are turned off. Since the second clock control signal is a high level signal, the fifth transistor T5 is turned off.
  • the first clock control signal provided on the first clock signal terminal CB is a low level signal
  • the second clock control signal provided on the second clock signal terminal CK is a high level signal
  • the input signal Vin provided on the input voltage signal terminal STV is a high-level signal, for example, the input signal Vin is equal to the second power signal VH. Since the first clock control signal is a low-level signal, the second transistor T2 is turned on, and the input signal Vin is transmitted to the third node N3 through the second transistor T2. Since the second transistor T2 transmits a high-level signal without threshold loss, the third The voltage of the node N3 is Vin (ie, the second power signal VH), and the seventh transistor T7 is turned off.
  • the sixth transistor T6 Since the sixth transistor T6 is in an on state, the voltage of the first node N1 is the same as that of the third node N3, that is, the voltage of the first node N1 is VH, and the eighth transistor T8 is turned off. Since the first clock control signal is a low level signal, the first transistor T1 is turned on, the voltage of the second node N2 is VL-Vth1, the third transistor T3 and the fourth transistor T4 are both turned on, and the second power signal VH passes through the The three transistors T3 are transmitted to the output terminal G(n), that is, the output signal is the second power supply signal VH.
  • the first clock control signal provided on the first clock signal terminal CB is a high level signal
  • the second clock control signal provided on the second clock signal terminal CK is a low level signal signal
  • the input signal Vin provided on the input voltage signal terminal STV is a high level signal.
  • the voltages of the first node N1 and the third node N3 are Vin (ie, the second power supply signal VH), and both the eighth transistor T8 and the seventh transistor T7 are turned off.
  • the first clock control signal is a high-level signal, so both the second transistor T2 and the first transistor T1 are turned off.
  • the voltage of the second node N2 is still VL-Vth1
  • the third transistor T3 and The fourth transistors T4 are all turned on, the second power signal VH is transmitted to the output terminal G(n) through the third transistor T3, and the output signal is the second power signal VH.
  • the fifth transistor T5 is turned on, so that the second power signal VH is transmitted to the third node N3 via the fourth transistor T4 and the fifth transistor T5 and the first node N1, so that the voltage of the first node N1 and the voltage of the third node N3 are kept at a high level.
  • the first clock control signal provided on the first clock signal terminal CB and the second clock control signal provided on the second clock signal terminal CK are both high-level signals, and the input voltage
  • the input signal Vin provided on the signal terminal STV is a high level signal.
  • the voltages of the first node N1 and the third node N3 are VH, and the eighth transistor T8 and the seventh transistor T7 are turned off.
  • the first clock control signal is a high level signal, so both the second transistor T2 and the first transistor T1 are turned off, the voltage of the second node N2 is still VL-Vth1, and the third transistor T3 and the fourth transistor T4 are both turned on.
  • the second power supply signal VH is transmitted to the output terminal G(n) through the third transistor T3, and the output signal is the second power supply signal VH.
  • the output terminal G(n) of the above-mentioned shift register is connected to the gate signal line 11 corresponding to the pixel in this row, and the signal output by the output terminal G(n) is the gate scanning signal.
  • the gate scan signal is input into the pixel circuit 200 of the corresponding row of pixels, the data signal of each column of data signal lines can be written into the corresponding pixel circuit.
  • FIG. 4 is an equivalent circuit of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 5 is a timing diagram of the pixel circuit shown in FIG. 4 .
  • the pixel driving circuit provided by the embodiments of the present disclosure includes a driving transistor M1, a first switching transistor M3, a second switching transistor M6, a first control transistor M2, a second control transistor M4, and a third control transistor M5 , the fourth control transistor M7 and the storage capacitor Cst.
  • the source of the first switching transistor M3 is electrically connected to the gate of the driving transistor M1, and the drain of the first switching transistor M3 is electrically connected to the drain of the driving transistor M1.
  • the gate of the first switching transistor M3 is electrically connected to the gate signal line G(n) of the nth row.
  • the gate of the second switching transistor M6 is electrically connected to the nth row reset line Re(n), the drain of the second switching transistor M6 is electrically connected to the gate of the driving transistor M1, and the source of the second switching transistor M6 is electrically connected to the initial voltage
  • the signal line Vint is electrically connected.
  • the gate of the first control transistor M2 is electrically connected to the gate signal line G(n) of the nth row, the source of the first control transistor M2 is electrically connected to the data signal line Da(m) of the mth column, and the first control transistor M2 The drain is electrically connected to the source of the driving transistor M1.
  • the gate of the second control transistor M4 is electrically connected to the n-th row light-emitting control line EM(n), the source of the second control transistor M4 is electrically connected to the power signal line ELVDD, and the drain of the second control transistor M4 is electrically connected to the driving transistor M1 source electrical connection.
  • the gate of the third control transistor M5 is electrically connected to the n-th row light-emitting control line EM(n), the source of the third control transistor M5 is electrically connected to the drain of the driving transistor M1, and the drain of the third control transistor M5 is electrically connected to the organic
  • the anode of the light emitting diode OLED is electrically connected; the cathode of the organic light emitting diode OLED is electrically connected with the low voltage signal line ELVSS.
  • the gate of the fourth control transistor M7 is electrically connected to the n+1th row reset signal line Re(n+1), the drain of the fourth control transistor M7 is electrically connected to the anode of the organic light emitting diode OLED, and the The source electrode is electrically connected to the initial voltage signal line Vint.
  • the first plate d1 of the storage capacitor Cst is electrically connected to the power signal line ELVDD, and the gate of the driving transistor M1 can be multiplexed as the second plate d2 of the storage capacitor Cst.
  • n is a positive integer
  • m is a positive integer.
  • the transistors in the pixel circuit provided by the embodiments of the present disclosure are p-type thin film transistors, and a low level is an active level.
  • the driving of the pixel circuit is divided into three stages, namely the reset stage, the data writing stage and the light-emitting stage.
  • Re(n) is input low, G(n) is high, EM(n) is high, M6 is turned on, and the potential of the gate of M1 is reset to initial voltage.
  • Re(n) is input high, G(n) is low, Da(m) is data voltage Vd, and EM(n) is high level, M6 is turned off, M4 and M5 are turned off, M2, M3, M1 and M7 are turned on, Vd charges Cst through M2, M1, and M3 to increase the potential of the gate of M1 until the potential of the gate of M1 becomes Vd
  • +Vth Vth is the threshold voltage of M1
  • M3 is turned off
  • the potential of N1 is stored by Cst
  • M7 is turned on at the same time to reset the potential of the anode of the OLED to the initial voltage.
  • Re(n) input high level, G(n) input high level, EM(n) input low level, M2, M3, M6 and M7 are off, M1, M4
  • M5 When M5 is turned on, the OLED emits light, and the driving current I that M1 drives the OLED to emit light is equal to K(Vd-Vdd) 2 /2, where K is the current coefficient, and Vdd is the voltage value of the power signal input by ELVDD.
  • the distance between the data signal line 21 and the power signal line 22 is relatively short, so when the signal on the data signal line jumps, due to the coupling effect between the two signal lines, the power signal The voltage transmitted on line 22 produces a transition. It can be seen from FIG. 4 that the power signal line 22 is input to one plate d1 of the storage capacitor Cst, and the data signal will be written to the other plate d2 of the storage capacitor Cst during the data writing stage. If the power signal transmitted by the power signal line ELVDD jumps, the data signal of the other plate d2 of Cst will be unstable, which may eventually cause a difference in display brightness.
  • the second clock signal terminal CK in FIG. 2 controls the output of the gate scan signal G(n), and the output gate scan signal G(n) and the second clock signal terminal CK output
  • the clock control signal is the same, and the data signal is written into the pixel circuit according to the gate scan signal.
  • FIG. 6 is a timing diagram of the related art.
  • the data signal Vd output from the data signal line is written into the storage capacitor of the pixel circuit.
  • the data signal line is outputting data signals to pixels of different rows, if the data signal output by the data signal line jumps, for example, in FIG. 6, the data signal Vd changes from high level to low level and from low level
  • the power signal ELVDD transmitted by the power signal line will change with the change of the data signal, and can recover to the fixed potential of the power signal ELVDD after a period of time.
  • the data writing stage that is, the period during which the clock control signal output by the second clock signal terminal CK is kept at a low level, and the period during which the power supply signal ELVDD is unstable, there is an overlap area, which will cause the data signal written into the pixel circuit to be inconsistent. precise.
  • an embodiment of the present disclosure provides a driving method for a display panel.
  • the clock signal terminal ie the second clock signal terminal in FIG. 2
  • the drive circuit inputs a clock control signal (ie, the second clock control signal), so that the gate drive circuit outputs a gate scan signal, and controls the data signal output from the data signal terminal to be written into the row of pixel circuits.
  • FIG. 7 is a timing diagram of an embodiment of the present disclosure.
  • the effective level of the clock control signal (CK) is low level, and the gate scan output by the gate driving circuit
  • the signal is controlled and output by the clock control signal (CK), and the period of the gate scanning signal and the duty ratio of the active level period are the same as the clock control signal (CK).
  • the pixel circuit of each row of pixels writes the data signal (Vd) transmitted by the data line connected to the row of pixels into the corresponding pixel circuit when the gate signal line connected to the pixel circuit outputs the active level of the gate scan signal. Therefore, the data writing time of each row of pixels is controlled by the clock control signal (CK).
  • the active level period of the clock control signal (CK) refers to the period during which the active level is output in one cycle, that is, the period H during which a row of pixels is scanned
  • the active level period of the data signal (Vd) refers to the period of A period in which the active level is output within the period H in which one row of pixels is scanned.
  • the clock control signal (CK) includes a plurality of active level periods of low level, and one of the active level periods corresponds to the data writing period of a row of pixels.
  • An active level period of the clock control signal can be controlled to fall within the active level period of the data signal (Vd) of the corresponding pixel row, and the start time of the active level period of the data signal (Vd) is at least earlier than the clock control signal.
  • the start time of the active level period of (CK) is 1 ⁇ s-2 ⁇ s.
  • the above-mentioned driving method provided by the embodiment of the present disclosure encodes the driving chip, controls the start time and the end time of the data signal (Vd) output by the data signal terminal, and controls the start of the clock control signal (CK) output by the clock signal terminal.
  • the active level period of the signal (CK) and the fluctuation period of the power supply signal (ELVDD) do not overlap or overlap very little, that is, during the period in which the data signal (Vd) is written to the pixel circuit and the fluctuation period of the power supply signal (ELVDD)
  • the fluctuation period does not overlap or overlaps in a very small part, thereby avoiding the influence of power signal fluctuation on data signal writing, and avoiding brightness differences in the row of pixels.
  • the start time of the valid level period of the data signal is set at least 1 ⁇ s-2 ⁇ s earlier than the start time of the valid level period of the clock control signal, which can ensure that when the clock control signal enters the valid level period, the power signal has been restored
  • the power supply signal remains at a fixed potential during the valid period of the clock control signal, that is, the period during which data is written to the pixel circuit, and will not affect the writing of the data signal.
  • the active level periods of the clock control signal (CK) and the data signal (Vd) are basically the same, and occupy about half of the scanning period H of a row of pixels.
  • the embodiments of the present disclosure shorten the effective level period of the clock control signal (CK) on the premise of ensuring the normal display of the display image, so as to provide a period of time for the fluctuation of the power supply signal (ELVDD) and reduce the power supply signal The overlapping time of the fluctuation period of (ELVDD) and the active level period of the clock control signal (CK).
  • the embodiment of the present disclosure shortens the active level period of the clock control signal (CK), so that in the scanning period H of the pixel row of one row, the active level period of the clock control signal (CK) is The duty cycle is less than 50%.
  • the embodiment of the present disclosure also increases the valid level period of the data signal (Vd), so that the start time of the valid level period of the data signal (Vd) is closer to the start time of the pixel scanning period of the row, so that the The end time of the active level period of the data signal (Vd) is closer to the end time of the pixel scanning period of the row.
  • the time difference between the start time of the active level period of the data signal (Vd) and the start time of the active level period of the clock control signal (CK) can be increased, thereby causing the fluctuation of the power supply signal (ELVDD) in advance, and is
  • the recovery of the power supply signal (ELVDD) provides sufficient time to ensure that the fluctuation period of the power supply signal (ELVDD) does not overlap with the active level period of the clock control signal (CK).
  • the embodiment of the present disclosure increases the active level period of the data signal (Vd), so that the duty of the active level period of the data signal (Vd) in the scanning period H for one pixel row of one row than 50%.
  • the duration of the active level period of the clock control signal (CK) can be less than or equal to half of the duration of the active level period of the data signal (Vd).
  • the fluctuation period of the power signal (ELVDD) can be prevented from overlapping with the writing period of the data signal (Vd), thereby preventing the fluctuation of the power signal (ELVDD) from affecting the written data signal (Vd).
  • the data signal (Vd) not only causes fluctuations in the power supply signal (ELVDD) when the data signal (Vd) transitions from a high level to a low level, but also causes fluctuations in the power supply signal (ELVDD) when the data signal (Vd) transitions from a low level to a high level.
  • the power supply signal (ELVDD) also fluctuates when the level is changed.
  • the embodiment of the present disclosure sets the end time of the active level period of the clock control signal (CK) earlier than the data signal (Vd) The end time of the active level period of the clock control signal (Vd), so that even if the data signal (Vd) has an impact on the power signal (ELVDD), the impact period does not overlap with the active level period of the clock control signal (CK), that is, it will not The writing of the data signal is affected, thereby further avoiding the influence of the power signal (ELVDD) on the writing of the data signal (Vd).
  • the end time of the active level period of the clock control signal (CK) is set to be at least 1 ⁇ s-2 ⁇ s earlier than the end time of the active level period of the data signal (Vd).
  • the power signal (ELVDD) fluctuates, it takes about 1 ⁇ s-2 ⁇ s to recover to a fixed potential.
  • the above settings can ensure that the power signal (ELVDD) fluctuation will not affect the writing of the data signal (Vd).
  • the scanning duration of a row of pixels is about 7 ⁇ s
  • the start time of the active level period of the data signal (Vd) needs to be at least 1 ⁇ s later than the start time of the scanning period of the row of pixels
  • the active level of the data signal (Vd) is at least 1 ⁇ s
  • the end time of the segment needs to be at least 1 ⁇ s earlier than the end time of the pixel scanning period of the row.
  • the duration of the active level period of the data signal (Vd) may be set to be 4 ⁇ s-6 ⁇ s.
  • the start time of the active level period of the data signal (Vd) needs to be 1 ⁇ s-2 ⁇ s earlier than the start time of the active level period of the clock control signal (CK), therefore, the effective level period of the clock control signal (CK) can be set
  • the duration is 2 ⁇ s-3 ⁇ s.
  • FIG. 8 and FIG. 9 are comparison diagrams before and after the adjustment of the effective level period of each signal when the display image is converted from a white image to a black image.
  • the data signal (Vd) jumps from the low level corresponding to the white picture to the high level corresponding to the black picture
  • the power supply signal (ELVDD) fluctuates, and the time when the power supply signal (ELVDD) fluctuates overlaps with the effective level period of the clock control signal (CK)
  • the fluctuation of the power supply signal (ELVDD) will affect the data signal (
  • the writing of Vd) has an effect, which ultimately affects the display brightness.
  • the data signal (Vd) is advanced by the corresponding value of the white screen.
  • the power supply signal (ELVDD) fluctuates in advance, so that the time when the power supply signal (ELVDD) fluctuates is equal to the effective level of the clock control signal (CK).
  • the segments do not overlap, and the fluctuation of the power signal (ELVDD) will not affect the writing of the data signal (Vd) at this time, and will not affect the display brightness.
  • FIG. 10 and FIG. 11 are comparison diagrams before and after the adjustment of the effective level period of each signal when the display image is converted from a black image to a white image.
  • the data signal (Vd) jumps from the high level corresponding to the black picture to the low level corresponding to the white picture
  • the power supply signal (ELVDD) fluctuates, and the time when the power supply signal (ELVDD) fluctuates overlaps with the effective level period of the clock control signal (CK)
  • the fluctuation of the power supply signal (ELVDD) will affect the data signal (
  • the writing of Vd) has an effect, which ultimately affects the display brightness.
  • the data signal (Vd) is advanced by the corresponding value of the black screen.
  • the power supply signal (ELVDD) fluctuates in advance, so that the time when the power supply signal (ELVDD) fluctuates is equal to the effective level of the clock control signal (CK).
  • the segments do not overlap, and the fluctuation of the power signal (ELVDD) will not affect the writing of the data signal (Vd) at this time, and will not affect the display brightness.
  • an embodiment of the present disclosure further provides a display panel, the structure of which is referred to FIG. 1 .
  • the display panel provided by the embodiment of the present disclosure includes: a plurality of pixels not shown in the figure, a gate driving circuit 100 , a pixel circuit 200 and the driver chip 300.
  • the pixels in the display panel are distributed in the display area, each pixel is connected to a pixel circuit 200 correspondingly, and a gate driving circuit 100 is provided in the non-display area on one side of the display area.
  • the gate driving circuit 100 is used for outputting a gate scanning signal to the pixel circuit 200, and writing a data signal into the pixel circuit 200 under the control of the gate scanning signal.
  • the data signal line 21, the power signal line 22 connected to the pixel circuit 200, and the initial signal input terminal of the gate driving circuit 100 are all connected to the driving chip 300, and the driving chip 300 provides the initial signal and clock control signal of the gate driving circuit , and provide data signals and power signals.
  • the start time and the end time of the effective levels of the above-mentioned signals can be realized by the coding of the driving chip 300 .
  • the driving chip 300 controls the clock signal terminal to input the clock control signal to the gate driving circuit 100, so that the gate driving circuit 100 outputs the gate scanning signal , and control the data signal output from the data signal terminal to be written into the pixel circuit 200 of the row.
  • the active level period of the clock control signal falls within the active level period of the data signal, and the starting time of the active level period of the data signal is at least 1 ⁇ s-2 ⁇ s earlier than the starting time of the active level period of the clock control signal.
  • the period in which the data signal is written to the pixel circuit does not overlap or overlaps very little with the fluctuation period of the power signal, thereby avoiding the influence of the fluctuation of the power signal on the writing of the data signal, avoiding the row Pixels produce differences in brightness.

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Abstract

一种显示面板及其驱动方法，在栅极驱动电路（100）逐行对像素进行扫描时，驱动芯片（300）控制时钟信号端向栅极驱动电路（100）输入时钟控制信号（CK），使栅极驱动电路（100）输出栅极扫描信号（G(n)），并控制数据信号端输出的数据信号（Vd）写入相应行像素电路（200）中。其中，时钟控制信号（CK）的有效电平时段落入数据信号（Vd）的有效电平时段之内，数据信号（Vd）的有效电平时段的开始时刻至少早于时钟控制信号（CK）的有效电平时段的开始时刻1μs-2μs。数据信号（Vd）写入到像素电路（200）的时段与电源信号（ELVDD）的波动时段不重叠或极小部分重叠，由此避免电源信号（ELVDD）波动对数据信号（Vd）写入的影响，避免相应行像素产生亮度差异。

Description

显示面板及其驱动方法
相关申请的交叉引用
本申请要求在2020年07月23日提交中国专利局、申请号为202010716277.X、申请名称为“显示面板及其驱动方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其驱动方法。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)显示技术具有能耗低、响应速度快、视角宽、更轻薄且具有柔韧性等优点，是一种极具潜力的显示技术。
OLED显示屏采用逐行扫描写入数据信号的方式控制点亮，显示屏中存在大量信号线，因此不可避免地存在串扰问题。当显示屏中相邻两行存储的数据信号差异较大时，会引起电源信号的电位变化，这将导致数据信号在写入的过程中受到电源信号的影响产生变化，从而出现亮度差异，影响显示效果。
发明内容
本公开实施例提供一种显示面板的驱动方法，所述显示面板包括：
多个像素，用于图像显示；
多个像素电路，用于控制所述像素进行发光显示；
栅极驱动电路，位于所述像素电路的一侧，用于向所述像素电路输出栅极扫描信号；
所述驱动方法包括：
在所述栅极驱动电路逐行对所述像素进行扫描时，控制时钟信号端向所 述栅极驱动电路输入时钟控制信号，使所述栅极驱动电路输出栅极扫描信号，并控制数据信号端输出的数据信号写入该行所述像素电路中；
其中，所述时钟控制信号的有效电平时段落入所述数据信号的有效电平时段之内，所述数据信号的有效电平时段的开始时刻至少早于所述时钟控制信号的有效电平时段的开始时刻1μs-2μs。
本公开一些实施例中，所述数据信号的有效电平时段在该行像素扫描时段的占空比大于50％。
本公开一些实施例中，所述时钟控制信号的有效电平时段在该行像素扫描时段的占空比小于50％。
本公开一些实施例中，所述时钟控制信号的有效电平时段的时长小于或等于所述数据信号的有效电平时段的时长的一半。
本公开一些实施例中，所述时钟控制信号的有效电平时段的结束时刻早于所述数据信号的有效电平时段的结束时刻。
本公开一些实施例中，所述时钟控制信号的有效电平时段的结束时刻至少早于所述数据信号的有效电平时段的结束时刻1μs-2μs。
本公开一些实施例中，所述数据信号的有效电平时段的时长为4μs-6μs。
本公开一些实施例中，所述时钟控制信号的有效电平时段的时长为2μs-3μs。
本公开一些实施例中，所述数据信号的有效电平时段的开始时刻至少晚于该行像素扫描时段的开始时刻1μs。
本公开一些实施例中，所述数据信号的有效电平时段的结束时刻至少早于该行像素扫描时段的结束时刻1μs。
本公开实施例提供一种显示面板，包括：
多个像素，用于图像显示；
多个像素电路，用于控制所述像素进行发光显示；
栅极驱动电路，位于所述像素电路的一侧，用于向所述像素电路输出栅极扫描信号；
驱动芯片，分别与所述栅极驱动电路和所述像素电路连接，用于向所述栅极驱动电路和所述像素电路输出控制信号；
在所述栅极驱动电路逐行对所述像素进行扫描时，所述驱动芯片控制时钟信号端向所述栅极驱动电路输入时钟控制信号，使所述栅极驱动电路输出栅极扫描信号，并控制数据信号端输出的数据信号写入该行所述像素电路中；
其中，所述时钟控制信号的有效电平时段落入所述数据信号的有效电平时段之内，所述数据信号的有效电平时段的开始时刻至少早于所述时钟控制信号的有效电平时段的开始时刻1μs-2μs。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例中所需要使用的附图作简单地介绍，显而易见地，下面所介绍的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的显示面板的结构示意图；
图2为本公开实施例提供的移位寄存器的等效电路图；
图3为图2所示移位寄存器的时序图；
图4为本公开实施例提供的像素电路的等效电路图；
图5为图4所示像素电路的时序图；
图6为相关技术的时序图；
图7为本公开实施例提供的时序图；
图8为相关技术的仿真时序图之一；
图9为本公开实施例提供的仿真时序图之一；
图10为相关技术的仿真时序图之一；
图11为本公开实施例提供的仿真时序图之二。
具体实施方式
为使本公开的上述目的、特征和优点能够更为明显易懂，下面将结合附图和实施例对本公开做进一步说明。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本公开中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本公开保护范围内。本公开的附图仅用于示意相对位置关系不代表真实比例。
OLED显示面板是一种以有机发光二极管作为发光器件的显示面板，OLED作为新一代显示技术，相较于液晶显示面板(Liquid Crystal Display，简称LCD)，OLED面板厚度可以控制在1mm以内，整机更轻薄，重量更加轻盈。OLED屏幕还具有LCD不具备的广视角，可以实现超大可视范围，画面不会失真。其响应速度是LCD屏幕的千分之一。OLED屏幕耐低温，可以在-40℃环境下正常显示内容，具有轻薄、亮度高、功耗低、响应快、清晰度高、柔性好、发光效率高等优势，在显示领域占据越来越重要的位置。
OLED器件包括阳极、发光层和阴极。阳极、发光层和阴极构成三明治结构，在阳极和阳极之间产生电场之后，电子和空穴会向发光层移动，并在发光层中复合成激子，激子激发发光分子最终产生可见光。
本公开实施例提供一种显示面板，该显示面板为OLED显示面板，具体可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图1为本公开实施例提供的显示面板的结构示意图。
参照图1，本公开实施例提供的显示面板包括：图中未示出的多个像素，栅极驱动电路100、像素电路200以及驱动芯片300。
其中，每个像素均与一个像素电路相连，通过像素电路200驱动像素发光。OLED显示面板中的像素为有机发光二极管器件，在具体实施时，OLED 器件可以包括红色OLED器件、绿色OLED器件以及蓝色OLED器件，通过对栅极驱动电路100和像素电路200的信号控制可以驱动相应的像素进行全彩显示。除此之外，也可以采用白色OLED器件配合彩膜来实现全彩显示，在此不做限定。
OLED显示面板中的像素会分布于显示区内，每个像素对应连接一个像素电路200，在显示区一侧的非显示区内设置有栅极驱动电路100。栅极驱动电路100用于向像素电路200输出栅极扫描信号，在栅极扫描信号的控制下将数据信号写入到像素电路200中，该数据信号为控制像素发光亮度灰阶的信号，通过对像素对应的像素电路200写入不同的数据信号，可以实现各像素的灰阶控制。
在本公开实施例提供的上述显示面板中，栅极驱动电路包括相互级联的移位寄存器，第一极的移位寄存器的输入信号由驱动芯片提供，除此之外，每级移位寄存器的输出信号作为下一级移位寄存器的输出信号。每级移位寄存器的输出端连接一条栅极信号线11，该栅极信号线11用于传输控制本行像素的栅极扫描信号。
图2为本公开实施例提供的移位寄存器的等效电路图，图3为图2所示移位寄存器的时序图。
参照图2和图3，本公开实施例提供的移位寄存器包括8个晶体管和2个电容。8个晶体管采用p型晶体管，低电平信号为有效电平。具体工作原理如下：
在输入阶段t1，第一时钟信号端CB上提供的第一时钟控制信号为低电平信号，第二时钟信号端CK上提供的第二时钟控制信号为高电平信号，输入电压信号端STV上提供的输入信号Vin为低电平信号，例如输入信号Vin与第一电源信号VL相等。
由于第一时钟控制信号为低电平信号，第二晶体管T2导通，输入信号经由第二晶体管T2传输至第三节点N3。由于第二晶体管T2传递低电平信号具有阈值损失，从而第三节点N3的电压为Vin-Vth2，即VL-Vth2，其中，Vth2 表示第二晶体管T2的阈值电压。由于第六晶体管T6的栅极接收第一电源信号VL，从而第六晶体管T6处于开启状态，由此，电压VL-Vth2经由第六晶体管T6传输至第一节点N1。例如，第六晶体管T6的阈值电压表示为Vth6，同理，由于第六晶体管T6传递低电平信号具有阈值损失，第一节点N1的电压为VL-VthN1，其中，VthN1为Vth2和Vth6中较小的一个。第一节点N1的电压可以控制第八晶体管T8导通，第二时钟控制信号经由第八晶体管T8被写入输出端G(n)以作为输出信号，即在输入阶段t1，输出信号为高电平的第二时钟控制信号，即第二电源信号VH。
在输入阶段t1，由于第一时钟控制信号为低电平信号，第一晶体管T1导通，第一电源信号VL经由第一晶体管T1传输至第二节点N2，由于第三节点N3的电压为VL-Vth2，第七晶体管T7导通，低电平的第一时钟控制信号经由第七晶体管T7传输至第二节点N2。例如，第七晶体管T7的阈值电压表示为Vth7，第一晶体管T1的阈值电压表示为Vth1，当Vth1<Vth7+Vth2时，则第二节点N2的电压为VL-Vth7-Vth2；而当Vth1>Vth7+Vth2时，则第二节点N2的电压为VL-Vth1。此时，第三晶体管T3和第四晶体管T4均导通。由于第二时钟控制信号为高电平信号，第五晶体管T5截止。
在输出阶段t2，第一时钟信号端CB上提供的第一时钟控制信号为高电平信号，第二时钟信号端CK上提供的第二时钟控制信号为低电平信号，输入电压信号端STV上提供的输入信号Vin为高电平信号。第八晶体管T8导通，第二时钟控制信号经由第八晶体管T8被写入输出端G(n)以作为输出信号。在输入阶段t1，第二电容C2的连接输出端G(n)的一端的电压为第二电源信号VH，第二电容C2的连接第一节点N1的一端的电压为VL-VthN1，而在输出阶段t2，第二电容C2的连接输出端G(n)的一端的电压变为VL，由于第二电容C2的自举作用，第二电容C2的连接第一节点N1的一端的电压变为2VL-VthN1-VH，即第一节点N1的电压变为2VL-VthN1-VH，此时，第六晶体管T6截止，第八晶体管T8可以更好地打开，输出信号为第一电源信号VL。
在输出阶段t2，第一时钟控制信号为高电平信号，从而第二晶体管T2和 第一晶体管T1均截止。第三节点N3的电压仍为VL-VthN1，第七晶体管T7导通，高电平的第一时钟控制信号经由第七晶体管T7传输至第二节点N2，即第二节点N2的电压为第二电源信号VH，由此，第三晶体管T3和第四晶体管T4均截止。由于第二时钟控制信号为低电平信号，第五晶体管T5导通。
在缓冲阶段t3，第一时钟信号端CB上提供的第一时钟控制信号和第二时钟信号端CK上提供的第二时钟控制信号均为高电平信号，输入电压信号端STV上提供的输入信号Vin为高电平信号。第八晶体管T8导通，第二时钟控制信号经由第八晶体管T8被写入输出端G(n)以作为输出信号，此时，输出信号为高电平的第二时钟控制信号，即第二电源信号VH。由于第二电容C2的自举作用，第一节点N1的电压变为VL-VthN1。
在缓冲阶段t3，第一时钟控制信号为高电平信号，从而第二晶体管T2和第一晶体管T1均截止。第一节点N1的电压变为VL-VthN1，此时，第六晶体管T6导通，第三节点N3的电压也为VL-VthN1，第七晶体管T7导通，高电平的第一时钟控制信号经由第七晶体管T7传输至第二节点N2，即第二节点N2的电压为第二电源信号VH，由此，第三晶体管T3和第四晶体管T4均截止。由于第二时钟控制信号为高电平信号，第五晶体管T5截止。
在稳定阶段t4的第一子阶段t41中，第一时钟信号端CB上提供的第一时钟控制信号为低电平信号，第二时钟信号端CK上提供的第二时钟控制信号为高电平信号，输入电压信号端STV上提供的输入信号Vin为高电平信号，例如输入信号Vin与第二电源信号VH相等。由于第一时钟控制信号为低电平信号，第二晶体管T2导通，输入信号Vin经由第二晶体管T2传输至第三节点N3，由于第二晶体管T2传递高电平信号无阈值损失，第三节点N3的电压为Vin(即，第二电源信号VH)，第七晶体管T7截止。由于第六晶体管T6处于开启状态，第一节点N1的电压与第三节点N3相同，也就是说，第一节点N1的电压为VH，第八晶体管T8截止。由于第一时钟控制信号为低电平信号，第一晶体管T1导通，第二节点N2的电压为VL-Vth1，第三晶体管T3和第四晶体管T4均导通，第二电源信号VH经由第三晶体管T3传输至输出端G(n)， 即输出信号为第二电源信号VH。
在稳定阶段t4的第二子阶段t42中，第一时钟信号端CB上提供的第一时钟控制信号为高电平信号，第二时钟信号端CK上提供的第二时钟控制信号为低电平信号，输入电压信号端STV上提供的输入信号Vin为高电平信号。第一节点N1和第三节点N3的电压为Vin(即，第二电源信号VH)，第八晶体管T8和第七晶体管T7均截止。第一时钟控制信号为高电平信号，从而第二晶体管T2和第一晶体管T1均截止，由于第一电容C1的保持作用，第二节点N2的电压仍为VL-Vth1，第三晶体管T3和第四晶体管T4均导通，第二电源信号VH经由第三晶体管T3传输至输出端G(n)，输出信号为第二电源信号VH。
在第二子阶段t42中，由于第二时钟控制信号为低电平信号，第五晶体管T5导通，从而第二电源信号VH经由第四晶体管T4和第五晶体管T5被传输至第三节点N3和第一节点N1，以使第一节点N1的电压和第三节点N3的电压保持为高电平。
在稳定阶段t4的第三子阶段t43中，第一时钟信号端CB上提供的第一时钟控制信号和第二时钟信号端CK上提供的第二时钟控制信号均为高电平信号，输入电压信号端STV上提供的输入信号Vin为高电平信号。第一节点N1和第三节点N3的电压为VH，第八晶体管T8和第七晶体管T7截止。第一时钟控制信号为高电平信号，从而第二晶体管T2和第一晶体管T1均截止，第二节点N2的电压仍为VL-Vth1，第三晶体管T3和第四晶体管T4均导通。第二电源信号VH经由第三晶体管T3传输至输出端G(n)，输出信号为第二电源信号VH。
上述移位寄存器的输出端G(n)连接本行像素对应的栅极信号线11，输出端G(n)输出的信号即为栅极扫描信号。当栅极扫描信号输入到对应行像素的像素电路200中时，各列数据信号线的数据信号可以写入到对应的像素电路中。
图4为本公开实施例提供的像素电路的等效电路，图5为图4所示像素 电路的时序图。
参照图4和图5，本公开实施例提供的像素驱动电路包括驱动晶体管M1、第一开关晶体管M3、第二开关晶体管M6、第一控制晶体管M2、第二控制晶体管M4、第三控制晶体管M5、第四控制晶体管M7和存储电容Cst。
第一开关晶体管M3的源极与驱动晶体管M1的栅极电连接，第一开关晶体管M3的漏极与驱动晶体管M1的漏极电连接。
第一开关晶体管M3的栅极与第n行栅极信号线G(n)电连接。
第二开关晶体管M6的栅极与第n行复位线Re(n)电连接，第二开关晶体管M6的漏极与驱动晶体管M1的栅极电连接，第二开关晶体管M6的源极与初始电压信号线Vint电连接。
第一控制晶体管M2的栅极与第n行栅极信号线G(n)电连接，第一控制晶体管M2的源极与第m列数据信号线Da(m)电连接，第一控制晶体管M2的漏极与驱动晶体管M1的源极电连接。
第二控制晶体管M4的栅极与第n行发光控制线EM(n)电连接，第二控制晶体管M4的源极与电源信号线ELVDD电连接，第二控制晶体管M4的漏极与驱动晶体管M1的源极电连接。
第三控制晶体管M5的栅极与第n行发光控制线EM(n)电连接，第三控制晶体管M5的源极与驱动晶体管M1的漏极电连接，第三控制晶体管M5的漏极与有机发光二极管OLED的阳极电连接；有机发光二极管OLED的阴极与低电压信号线ELVSS电连接。
第四控制晶体管M7的栅极与第n+1行复位信号线Re(n+1)电连接，第四控制晶体管M7的漏极与有机发光二极管OLED的阳极电连接，第四控制晶体管M7的源极与初始电压信号线Vint电连接。
存储电容Cst的第一极板d1与电源信号线ELVDD电连接，驱动晶体管M1的栅极可以复用为存储电容Cst的第二极板d2。
其中，n为正整数，m为正整数。本公开实施例提供的像素电路中的晶体管为p型薄膜晶体管，低电平为有效电平。
像素电路的驱动分为三个阶段，分别为复位阶段、数据写入阶段和发光阶段。
在第一阶段t1’(复位阶段)，Re(n)输入低电平，G(n)输入高电平，EM(n)输入高电平，M6打开，M1的栅极的电位被复位为初始电压。
在第二阶段t2’(数据写入和阈值电压补偿阶段)，Re(n)输入高电平，G(n)输入低电平，Da(m)输入数据电压Vd，EM(n)输入高电平，M6截止，M4和M5截止，M2、M3、M1和M7开启，Vd通过M2、M1、M3为Cst充电，以提升M1的栅极的电位，直至M1的栅极的电位变为Vd+Vth(Vth为M1的阈值电压)时，M3关闭，N1的电位被Cst存储，同时M7打开，以将OLED的阳极的电位复位为初始电压。
在第三阶段t3’(发光阶段)，Re(n)输入高电平，G(n)输入高电平，EM(n)输入低电平，M2、M3、M6和M7截止，M1、M4和M5导通，OLED发光，M1驱动OLED发光的驱动电流I等于K(Vd-Vdd) 2/2，其中，K为电流系数，Vdd为ELVDD输入的电源信号的电压值。
在显示面板的制作过程中，数据信号线21与电源信号线22的距离较近，因此当数据信号线上的信号出现跳变时，由于两条信号线之间的耦合作用，会使电源信号线22上传输的电压产生跳变。由图4可以看出，电源信号线22输入到存储电容Cst的一个极板d1上，而在数据写入阶段数据信号会写入到存储电容Cst的另一极板d2上，由于存储电容Cst的自举作用，如果电源信号线ELVDD传输的电源信号产生跳变，则会使Cst的另一极板d2的数据信号不稳定，最终可能造成显示亮度的差异。
由上述的分析可知，图2中的第二时钟信号端CK控制栅极扫描信号G(n)的输出，且输出的栅极扫描信号G(n)与第二时钟信号端CK输出的第二时钟控制信号相同，而数据信号是根据栅极扫描信号写入到像素电路中的。
图6为相关技术的时序图。参照图6，当第二时钟信号端CK输入有效电平(低电平)时，数据信号线上输出的数据信号Vd写入到像素电路的存储电容。而当数据信号线在对不同行的像素输出数据信号时，如果数据信号线输 出的数据信号发生跳变，例如在图6中数据信号Vd由高电平变为低电平以及由低电平变为高电平的时刻，电源信号线传输的电源信号ELVDD会随着数据信号的变化而产生变化，且经过一段时间才能恢复到电源信号ELVDD的固定电位。那么在数据写入阶段，即第二时钟信号端CK输出的时钟控制信号保持低电平的时段与电源信号ELVDD不稳定的时段有重合区域，这将导致写入到像素电路中的数据信号不准确。
为了克服上述问题，本公开实施例提供一种显示面板的驱动方法，在栅极驱动电路逐行对像素进行扫描时，控制时钟信号端(即图2中的第二时钟信号端)向栅极驱动电路输入时钟控制信号(即上述第二时钟控制信号)，使栅极驱动电路输出栅极扫描信号，并控制数据信号端输出的数据信号写入该行像素电路中。
图7为本公开实施例提的时序图，参照图7，本公开实施例提供的驱动方法中，时钟控制信号(CK)的有效电平为低电平，栅极驱动电路输出的栅极扫描信号由时钟控制信号(CK)控制输出，栅极扫描信号的周期以及有效电平时段的占空比均与时钟控制信号(CK)相同。每行像素的像素电路在其连接的栅极信号线输出栅极扫描信号的有效电平时，将该行像素连接的数据线所传输的数据信号(Vd)写入到对应的像素电路中。因此各行像素的数据写入的时间由时钟控制信号(CK)来控制。
时钟控制信号(CK)的有效电平时段是指在一个周期内，即对一行像素进行扫描的时段H内，输出有效电平的时段，数据信号(Vd)的有效电平时段是指在对一行像素进行扫描的时段H内输出有效电平的时段。由图7可以看出，时钟控制信号(CK)包括多个低电平的有效电平时段，其中一个有效电平时段均对应着一行像素的数据写入时段，那么在本发明实施例中，可以控制时钟控制信号的一个有效电平时段落入对应的像素行的数据信号(Vd)的有效电平时段之内，且数据信号(Vd)的有效电平时段的开始时刻至少早于时钟控制信号(CK)的有效电平时段的开始时刻1μs-2μs。
本公开实施例提供的上述驱动方法，对驱动芯片进行编码，控制数据信 号端输出数据信号(Vd)的起始时刻和终止时刻，以及控制时钟信号端输出的时钟控制信号(CK)的起始时刻和终止时刻，使得在对一行像素进行扫描的时段H内将数据信号(Vd)的有效电平时段的起始时刻提前，从而提前引起电源信号(ELVDD)的波动，这就使在时钟控制信号(CK)的有效电平时段与电源信号(ELVDD)的波动时段不重叠或极小部分重叠，也就是说，在数据信号(Vd)写入到像素电路的时段与电源信号(ELVDD)的波动时段不重叠或极小部分重叠，由此避免电源信号波动对数据信号写入的影响，避免该行像素产生亮度差异。
通过实测可以确定当数据信号线传输的数据信号产生跳变而引起电源信号线传输的电源信号产生波动时，该波动大约经历1μs-2μs可以恢复到其固定电位。因此本公开实施例设置数据信号的有效电平时段的开始时刻至少早于时钟控制信号的有效电平时段的开始时刻1μs-2μs，可以保证时钟控制信号进入有效电平时段时，电源信号已恢复到其设定值，那么在时钟控制信号的有效时段，即数据写入到像素电路的时段电源信号保持在固定电位，不会影响数据信号的写入。
对比图6和图7可以看出，在相关技术中时钟控制信号(CK)和数据信号(Vd)的有效电平时段基本相同，且占据一行像素的扫描时段H的一半左右。本公开实施例为了实现上述效果，在保证显示图像正常显示的前提下，将时钟控制信号(CK)的有效电平时段缩短，这样可以为电源信号(ELVDD)的波动提供一段时间，缩小电源信号(ELVDD)的波动时段与时钟控制信号(CK)的有效电平时段的重叠时间。
如图7所示，本公开实施例将时钟控制信号(CK)的有效电平时段缩短，以使在对一行的像素行的扫描时段H内，时钟控制信号(CK)的有效电平时段的占空比小于50％。
与此同时，本公开实施例还增长了数据信号(Vd)的有效电平时段，以使数据信号(Vd)的有效电平时段的开始时刻更靠近该行像素扫描时段的起始时刻，使数据信号(Vd)的有效电平时段的结束时刻更靠近该行像素扫描 时段的终止时刻。这样可以增长数据信号(Vd)的有效电平时段的开始时刻与时钟控制信号(CK)的有效电平时段的起始时刻之间的时间差，从而提前引起电源信号(ELVDD)的波动，且为电源信号(ELVDD)的恢复提供充足的时间，以保证电源信号(ELVDD)的波动时段与时钟控制信号(CK)的有效电平时段不重叠。
如图7所示，本公开实施例将数据信号(Vd)的有效电平时段增长，以使在对一行的像素行的扫描时段H内，数据信号(Vd)的有效电平时段的占空比大于50％。
经过上述设置可以使时钟控制信号(CK)的有效电平时段的时长小于或等于数据信号(Vd)的有效电平时段的时长的一半。由此可以避免电源信号(ELVDD)的波动时段与数据信号(Vd)的写入时段重叠，从而避免电源信号(ELVDD)的波动对写入的数据信号(Vd)产生影响。
如图6和图7所示，数据信号(Vd)不仅在由高电平跳变到低电平时会造成电源信号(ELVDD)的波动，在数据信号(Vd)由低电平跳变到高电平时也会造成电源信号(ELVDD)的波动。
如图7所示，本公开实施例为了改善电源信号(ELVDD)对数据信号(Vd)写入的影响，设置时钟控制信号(CK)的有效电平时段的结束时刻早于数据信号(Vd)的有效电平时段的结束时刻，这样即使数据信号(Vd)对电源信号(ELVDD)会产生影响，但产生影响的时段与时钟控制信号(CK)的有效电平时段并不重叠，即不会影响数据信号的写入，由此进一步避免电源信号(ELVDD)对数据信号(Vd)写入的影响。
在本公开实施例中，设置时钟控制信号(CK)的有效电平时段的结束时刻至少早于数据信号(Vd)的有效电平时段的结束时刻1μs-2μs。电源信号(ELVDD)产生波动后大约需要1μs-2μs可以恢复到固定电位，采用上述设置可以保证电源信号(ELVDD)的波动不会对数据信号(Vd)的写入产生影响。
在具体实施时，一行像素的扫描时长大约为7μs，数据信号(Vd)的有效 电平时段的开始时刻至少需要晚于该行像素扫描时段的开始时刻1μs，数据信号(Vd)的有效电平时段的结束时刻至少需要早于该行像素扫描时段的结束时刻1μs。
在本公开实施例中，可以设置数据信号(Vd)的有效电平时段的时长为4μs-6μs。而数据信号(Vd)的有效电平时段的开始时刻需要早于时钟控制信号(CK)的有效电平时段的开始时刻1μs-2μs，因此，可以设置时钟控制信号(CK)的有效电平时段的时长为2μs-3μs。
图8和图9为显示图像由白画面转换成黑画面时对各信号有效电平时段调整前后的对比图。
如图8所示，在对时钟控制信号(CK)以及数据信号(Vd)的有效电平时段进行调整之前，数据信号(Vd)由白画面对应的低电平跳变成黑画面对应的高电平时，电源信号(ELVDD)产生波动，且电源信号(ELVDD)产生波动的时间与时钟控制信号(CK)的有效电平时段有重叠，此时电源信号(ELVDD)的波动会对数据信号(Vd)的写入产生影响，最终影响显示亮度。
如图9所示，在采用本公开实施例提供的上述驱动方法对时钟控制信号(CK)以及数据信号(Vd)的有效电平时段进行调整之后，提前数据信号(Vd)由白画面对应的低电平跳变成黑画面对应的高电平的时间，从而使电源信号(ELVDD)提前产生波动，由此使得电源信号(ELVDD)产生波动的时间与时钟控制信号(CK)的有效电平时段不重叠，此时电源信号(ELVDD)的波动不会对数据信号(Vd)的写入产生影响，也就不会影响显示亮度。
图10和图11为显示图像由黑画面转换成白画面时对各信号有效电平时段调整前后的对比图。
如图10所示，在对时钟控制信号(CK)以及数据信号(Vd)的有效电平时段进行调整之前，数据信号(Vd)由黑画面对应的高电平跳变成白画面对应的低电平时，电源信号(ELVDD)产生波动，且电源信号(ELVDD)产生波动的时间与时钟控制信号(CK)的有效电平时段有重叠，此时电源信号(ELVDD)的波动会对数据信号(Vd)的写入产生影响，最终影响显示亮度。
如图11所示，在采用本公开实施例提供的上述驱动方法对时钟控制信号(CK)以及数据信号(Vd)的有效电平时段进行调整之后，提前数据信号(Vd)由黑画面对应的高电平跳变成白画面对应的低电平的时间，从而使电源信号(ELVDD)提前产生波动，由此使得电源信号(ELVDD)产生波动的时间与时钟控制信号(CK)的有效电平时段不重叠，此时电源信号(ELVDD)的波动不会对数据信号(Vd)的写入产生影响，也就不会影响显示亮度。
基于同一发明构思，本公开实施例还提供一种显示面板，其结构参照图1，本公开实施例提供的显示面板包括：图中未示出的多个像素，栅极驱动电路100、像素电路200以及驱动芯片300。
显示面板中的像素会分布于显示区内，每个像素对应连接一个像素电路200，在显示区一侧的非显示区内设置有栅极驱动电路100。栅极驱动电路100用于向像素电路200输出栅极扫描信号，在栅极扫描信号的控制下将数据信号写入到像素电路200中，该数据信号为控制像素发光亮度灰阶的信号，通过对像素对应的像素电路200写入不同的数据信号，可以实现各像素的灰阶控制。
像素电路200所连接的数据信号线21、电源信号线22，以及栅极驱动电路100的初始信号输入端均与驱动芯片300连接，由驱动芯片300提供栅极驱动电路的初始信号、时钟控制信号，以及提供数据信号、电源信号。而上述各信号的有效电平的起始时间和终止时间，可以通过驱动芯片300的编码实现。
在本公开实施例中，在栅极驱动电路100逐行对像素进行扫描时，驱动芯片300控制时钟信号端向栅极驱动电路100输入时钟控制信号，使栅极驱动电路100输出栅极扫描信号，并控制数据信号端输出的数据信号写入该行像素电路200中。
其中，时钟控制信号的有效电平时段落入数据信号的有效电平时段之内，数据信号的有效电平时段的开始时刻至少早于时钟控制信号的有效电平时段的开始时刻1μs-2μs。
本公开实施例提供的上述显示面板，数据信号写入到像素电路的时段与电源信号的波动时段不重叠或极小部分重叠，由此避免电源信号波动对数据信号写入的影响，避免该行像素产生亮度差异。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (11)

  1. 一种显示面板的驱动方法，其中，所述显示面板包括：
    多个像素，用于图像显示；
    多个像素电路，用于控制所述像素进行发光显示；
    栅极驱动电路，位于所述像素电路的一侧，用于向所述像素电路输出栅极扫描信号；
    所述驱动方法包括：
    在所述栅极驱动电路逐行对所述像素进行扫描时，控制时钟信号端向所述栅极驱动电路输入时钟控制信号，使所述栅极驱动电路输出栅极扫描信号，并控制数据信号端输出的数据信号写入该行所述像素电路中；
    其中，所述时钟控制信号的有效电平时段落入所述数据信号的有效电平时段之内，所述数据信号的有效电平时段的开始时刻至少早于所述时钟控制信号的有效电平时段的开始时刻1μs-2μs。
  2. 如权利要求1所述的驱动方法，其中，所述数据信号的有效电平时段在该行像素扫描时段的占空比大于50％。
  3. 如权利要求2所述的驱动方法，其中，所述时钟控制信号的有效电平时段在该行像素扫描时段的占空比小于50％。
  4. 如权利要求3所述的驱动方法，其中，所述时钟控制信号的有效电平时段的时长小于或等于所述数据信号的有效电平时段的时长的一半。
  5. 如权利要求1所述的驱动方法，其中，所述时钟控制信号的有效电平时段的结束时刻早于所述数据信号的有效电平时段的结束时刻。
  6. 如权利要求5所述的驱动方法，其中，所述时钟控制信号的有效电平时段的结束时刻至少早于所述数据信号的有效电平时段的结束时刻1μs-2μs。
  7. 如权利要求1-6任一项所述的驱动方法，其中，所述数据信号的有效电平时段的时长为4μs-6μs。
  8. 如权利要求7所述的驱动方法，其中，所述时钟控制信号的有效电平 时段的时长为2μs-3μs。
  9. 如权利要求1-6任一项所述的驱动方法，其中，所述数据信号的有效电平时段的开始时刻至少晚于该行像素扫描时段的开始时刻1μs。
  10. 如权利要求9所述的驱动方法，其中，所述数据信号的有效电平时段的结束时刻至少早于该行像素扫描时段的结束时刻1μs。
  11. 一种显示面板，其中，包括：
    多个像素，用于图像显示；
    多个像素电路，用于控制所述像素进行发光显示；
    栅极驱动电路，位于所述像素电路的一侧，用于向所述像素电路输出栅极扫描信号；
    驱动芯片，分别与所述栅极驱动电路和所述像素电路连接，用于向所述栅极驱动电路和所述像素电路输出控制信号；
    在所述栅极驱动电路逐行对所述像素进行扫描时，所述驱动芯片控制时钟信号端向所述栅极驱动电路输入时钟控制信号，使所述栅极驱动电路输出栅极扫描信号，并控制数据信号端输出的数据信号写入该行所述像素电路中；
    其中，所述时钟控制信号的有效电平时段落入所述数据信号的有效电平时段之内，所述数据信号的有效电平时段的开始时刻至少早于所述时钟控制信号的有效电平时段的开始时刻1μs-2μs。
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