WO2023205964A1 - 像素电路、其驱动方法、显示面板及显示装置 - Google Patents

像素电路、其驱动方法、显示面板及显示装置 Download PDF

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Publication number
WO2023205964A1
WO2023205964A1 PCT/CN2022/088832 CN2022088832W WO2023205964A1 WO 2023205964 A1 WO2023205964 A1 WO 2023205964A1 CN 2022088832 W CN2022088832 W CN 2022088832W WO 2023205964 A1 WO2023205964 A1 WO 2023205964A1
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Prior art keywords
control signal
coupled
transistor
control
electrode
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PCT/CN2022/088832
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English (en)
French (fr)
Inventor
邱远游
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京东方科技集团股份有限公司
重庆京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000857.6A priority Critical patent/CN117296091A/zh
Priority to PCT/CN2022/088832 priority patent/WO2023205964A1/zh
Priority to US18/022,486 priority patent/US20240265866A1/en
Publication of WO2023205964A1 publication Critical patent/WO2023205964A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects

Definitions

  • the present disclosure relates to the field of display technology, and in particular to pixel circuits, driving methods thereof, display panels and display devices.
  • Electroluminescent diodes such as organic light emitting diodes (OLED), quantum dot light emitting diodes (QLED), micro light emitting diodes (Micro Light Emitting Diode, Micro LED) have the characteristics of self-luminescence and low energy consumption. Advantages, it is one of the hot spots in the field of electroluminescent display device application research today. Generally, pixel circuits are used in electroluminescent display devices to drive electroluminescent diodes to emit light.
  • a driving transistor configured to generate a driving current for driving the light-emitting device to emit light according to the data voltage
  • a data writing circuit coupled to the driving transistor; wherein the data writing circuit is configured to input the data voltage in response to a loaded signal;
  • a voltage control circuit coupled to the driving transistor; wherein the voltage control circuit is configured to respond to a loaded signal and, before inputting the data voltage, control the control electrode, the first electrode and the third electrode of the driving transistor.
  • the two poles are reset.
  • the voltage control circuit is further configured to provide the first initialization signal loaded on the first initialization signal terminal to the control electrode of the driving transistor in response to the first control signal loaded on the first control signal terminal. , resetting the control electrode of the driving transistor; and, in response to the second control signal loaded on the second control signal terminal, resetting the first electrode and the second electrode of the driving transistor.
  • the voltage control circuit includes: a first transistor, a second transistor, and a storage capacitor;
  • the control electrode of the first transistor is coupled to the first control signal terminal, the first electrode of the first transistor is coupled to the first initialization signal terminal, and the second electrode of the first transistor is coupled to the first initialization signal terminal.
  • the control electrode of the driving transistor is coupled;
  • the control electrode of the second transistor is coupled to the second control signal terminal, the first electrode of the second transistor is coupled to the control electrode of the driving transistor, and the second electrode of the second transistor is coupled to the control signal terminal.
  • the first electrode plate of the storage capacitor is coupled to the control electrode of the driving transistor, and the second electrode plate of the storage capacitor is coupled to the first electrode of the drive.
  • the voltage control circuit is further configured to compensate the threshold voltage of the driving transistor in response to the second control signal loaded on the second control signal terminal when the data voltage is input. .
  • the pixel circuit further includes a threshold compensation circuit
  • the threshold compensation circuit is coupled to the drive transistor, wherein the threshold compensation circuit is configured to, when the data voltage is input, respond to a third control signal loaded on a third control signal terminal, to the drive transistor. threshold voltage to compensate.
  • the threshold compensation circuit includes: a third transistor
  • the control electrode of the third transistor is coupled to the third control signal terminal, the first electrode of the third transistor is coupled to the control electrode of the driving transistor, and the second electrode of the third transistor is coupled to the control signal terminal.
  • the second pole of the driving transistor is coupled.
  • the data writing circuit is further configured to input the data voltage loaded at the data signal terminal into the first pole of the driving transistor in response to a fourth control signal loaded at the fourth control signal terminal.
  • the data writing circuit includes a fourth transistor
  • the control electrode of the fourth transistor is coupled to the fourth control signal terminal, the first electrode of the fourth transistor is coupled to the data signal terminal, and the second electrode of the fourth transistor is coupled to the driving The first terminal of the transistor is coupled.
  • the maintenance time of the effective level of the fourth control signal is not greater than the maintenance time of the effective level of the first control signal.
  • the data writing circuit is further configured to write the data loaded on the data signal terminal in response to a fifth control signal loaded on the fifth control signal terminal and a sixth control signal loaded on the sixth control signal terminal.
  • the voltage is input to the first pole of the driving transistor;
  • the effective level of the fifth control signal and the effective level of the sixth control signal have a second overlapping duration, and the starting time of the effective level of the fifth control signal is at the effective level of the sixth control signal. before the start time of the level.
  • the data writing circuit includes: a fifth transistor and a sixth transistor;
  • the control electrode of the fifth transistor is coupled to the fifth control signal terminal, the first electrode of the fifth transistor is coupled to the first electrode of the driving transistor, and the second electrode of the fifth transistor is coupled to The first pole of the sixth transistor is coupled;
  • the control electrode of the sixth transistor is coupled to the sixth control signal terminal, and the second electrode of the sixth transistor is coupled to the data signal terminal.
  • the maintenance time of the effective level of at least one of the fifth control signal and the sixth control signal is substantially the same as the maintenance time of the effective level of the second control signal.
  • the starting time of the effective level of the fifth control signal is before the starting time of the effective level of the second control signal
  • the starting time of the effective level of the second control signal is before the starting time of the effective level of the second control signal.
  • the start time of the effective level of the sixth control signal is before the start time of the effective level of the sixth control signal.
  • the fifth control signal terminal and the second control signal terminal are the same signal terminal.
  • the pixel circuit further includes:
  • the pixel circuit further includes:
  • a device reset circuit coupled to the light-emitting device; wherein the device reset circuit is configured to provide a second initialization signal of a second initialization signal terminal to the light-emitting device in response to a seventh control signal of a seventh control signal terminal .
  • the seventh control signal terminal is the same signal terminal as one of the first to fourth control signal terminals.
  • An embodiment of the present disclosure provides a display panel including the above-mentioned pixel circuit.
  • the display panel includes:
  • a plurality of sub-pixels wherein at least one sub-pixel among the plurality of sub-pixels includes the above-mentioned pixel circuit;
  • control signal lines wherein at least one of the plurality of control signal lines is coupled to a pixel circuit in a row of sub-pixels;
  • a drive control circuit wherein the drive control circuit is coupled to the plurality of control signal lines respectively.
  • the plurality of control signal lines include a plurality of first control signal lines, a plurality of second control signal lines, a plurality of fifth control signal lines, and a plurality of sixth control signal lines; wherein, one of the plurality of control signal lines A first control signal line is coupled to a first control signal terminal of a pixel circuit in a row of sub-pixels, a second control signal line is coupled to a second control signal terminal of a pixel circuit in a row of sub-pixels, and a second control signal line is coupled to a first control signal terminal of a pixel circuit in a row of sub-pixels.
  • the fifth control signal line is coupled to the fifth control signal terminal of the pixel circuit in one row of sub-pixels, and one of the sixth control signal lines is coupled to the sixth control signal terminal of the pixel circuit in one row of sub-pixels;
  • the drive control circuit includes: a first drive control circuit; wherein the first drive control circuit includes a plurality of first drive shift register units arranged in sequence; with each adjacent plurality of first drive shift register units is a first unit group, and one row of sub-pixels corresponds to one first unit group; and, in the first unit group, the first first driving shift register unit is coupled to the corresponding row of sub-pixels.
  • the first control signal line is coupled
  • the third first drive shift register unit is coupled to the fifth control signal line coupled to the corresponding row sub-pixel
  • the fourth first drive shift register unit is coupled to the corresponding row sub-pixel.
  • the second control signal line to which the pixel is coupled is coupled
  • the fifth first driving shift register unit is coupled to the sixth control signal line to which the corresponding row of sub-pixels is coupled.
  • the plurality of control signal lines include a plurality of first control signal lines, a plurality of second control signal lines, and a plurality of sixth control signal lines; wherein one of the first control signal lines and a row of sub The first control signal terminal of the pixel circuit in the pixel is coupled, one of the second control signal lines is coupled to the second control signal terminal and the fifth control signal terminal of the pixel circuit in a row of sub-pixels, and one of the sixth control signal lines The control signal line is coupled to the sixth control signal terminal of the pixel circuit in one row of sub-pixels;
  • the drive control circuit includes: a second drive control circuit; wherein the second drive control circuit includes a plurality of second drive shift register units arranged in sequence; with each adjacent plurality of second drive shift register units is a second unit group, and one row of sub-pixels corresponds to one second unit group; and, in the second unit group, the first second driving shift register unit is coupled to the corresponding row of sub-pixels.
  • the first control signal line is coupled
  • the third second drive shift register unit is coupled to the second control signal line coupled to the corresponding row sub-pixel
  • the fifth second drive shift register unit is coupled to the corresponding row sub-pixel.
  • the sixth control signal line to which the pixel is coupled is coupled.
  • the plurality of control signal lines include a plurality of first control signal lines, a plurality of second control signal lines, and a plurality of fourth control signal lines; wherein one of the first control signal lines and a row of sub-line
  • the first control signal terminal of the pixel circuit in the pixel is coupled, one of the second control signal lines is coupled to the second control signal terminal of the pixel circuit in a row of sub-pixels, and one of the fourth control signal lines is coupled to a row of sub-pixels.
  • the fourth control signal terminal of the pixel circuit in the pixel is coupled;
  • the drive control circuit includes: a third drive control circuit and a fourth drive control circuit;
  • the third drive control circuit includes a plurality of third drive shift register units arranged in sequence; each adjacent plurality of third drive shift register units is a third unit group, and one row of sub-pixels corresponds to one of the third drive shift register units.
  • the bit register unit is coupled to the second control signal line coupled to the corresponding row of sub-pixels;
  • the fourth driving control circuit includes a plurality of fourth driving shift register units arranged in sequence; one row of sub-pixels corresponds to one fourth driving shift register unit; and the fourth driving shift register unit and the corresponding row of sub-pixels
  • the coupled fourth control signal line is coupled.
  • a display device provided by an embodiment of the present disclosure includes the above-mentioned display panel.
  • the voltage control circuit responds to the loaded signal and resets the control electrode, the first electrode and the second electrode of the drive transistor before inputting the data voltage;
  • the data writing circuit is configured to input the data voltage in response to the loaded signal
  • the driving transistor In the light-emitting stage, the driving transistor generates a driving current to drive the light-emitting device to emit light according to the data voltage, thereby driving the light-emitting device to emit light.
  • Figure 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure
  • Figure 2 is another structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 3 is a schematic diagram of some specific structures of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 4a is some signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 4b is some signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 5 is some flowcharts of driving methods for pixel circuits provided by embodiments of the present disclosure.
  • Figure 6 is another specific structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 7 is another signal timing diagram provided by an embodiment of the present disclosure.
  • Figure 8 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 9 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 10 is a schematic diagram of some further specific structures of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 11 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 12 is a schematic diagram of some further specific structures of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 13a is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 13b is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 14 is a schematic diagram of some further specific structures of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 15 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 16 is a schematic diagram of some further specific structures of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 17 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 18 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • Figure 19 is another structural schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • Figure 20 is another structural schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • Figure 21 is another structural schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 22 is another structural schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • the display device may include a display panel.
  • the display panel may include a substrate substrate.
  • the base substrate may include a display area and a non-display area (ie, the area in the base substrate except the area surrounding the display area).
  • the display area may include multiple pixel units arranged in an array.
  • each pixel unit includes sub-pixels of the same color or sub-pixels of multiple different colors.
  • the pixel unit may include red sub-pixels, green sub-pixels and blue sub-pixels, so that red, green and blue colors can be mixed to achieve color display.
  • the pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, so that the colors of red, green, blue and white can be mixed to achieve color display.
  • the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here. The following description takes the pixel unit including red sub-pixels, green sub-pixels and blue sub-pixels as an example.
  • each sub-pixel may include a pixel circuit
  • the pixel circuit may include a driving transistor M0 and a light-emitting device L to control the light-emitting device L to emit light, thereby enabling the display panel to achieve the function of displaying a picture.
  • the threshold voltage Vth of the driving transistor M0 will drift, which will affect the generated driving current, and the hysteresis effect when switching between high and low gray scales will also cause the problem of image retention.
  • embodiments of the present disclosure provide some pixel circuits, as shown in FIG. 1 , which may include: a driving transistor M0, a data writing circuit 10, and a light-emitting device L.
  • the data writing circuit 10 is coupled to the driving transistor M0
  • the voltage control circuit 20 is coupled to the driving transistor M0.
  • the driving transistor M0 may be configured to generate a current that drives the light emitting device L to emit light according to the data voltage.
  • the data writing circuit 10 may be configured to input a data voltage in response to the loaded signal.
  • the voltage control circuit 20 may be configured to respond to the loaded signal and reset the control electrode, the first electrode and the second electrode of the driving transistor M0 before inputting the data voltage.
  • the control electrode, the first electrode and the second electrode of the driving transistor can be reset before inputting the data voltage.
  • the voltage of the control electrode of the driving transistor is approximately the same
  • the voltage of the first electrode of the driving transistor is approximately the same
  • the voltage of the second electrode of the driving transistor is approximately the same.
  • the voltages of the poles are roughly the same, which can improve the problem of image retention caused by the hysteresis effect when switching between high and low gray scales.
  • the voltage control circuit 20 can be connected to the first control signal terminal CS1 , the first initialization signal terminal VINIT1 , the second control signal terminal CS2 and the control electrode of the driving transistor M0 respectively.
  • the second pole is coupled.
  • the voltage control circuit 20 is further configured to provide the first initialization signal loaded at the first initialization signal terminal VINIT1 to the control electrode of the driving transistor M0 in response to the first control signal cs1 loaded on the first control signal terminal CS1, so as to The control electrode of the driving transistor M0 is reset; and, in response to the second control signal cs2 loaded on the second control signal terminal CS2, the first electrode and the second electrode of the driving transistor M0 are reset.
  • the voltage control circuit 20 is further configured to compensate the threshold voltage of the driving transistor M0 in response to the second control signal cs2 loaded on the second control signal terminal CS2 when the data voltage is input.
  • the data writing circuit 10 can be coupled to the fourth control signal terminal CS4, the data signal terminal DA and the first pole of the driving transistor M0 respectively. Moreover, the data writing circuit 10 may be further configured to input the data voltage loaded on the data signal terminal DA into the first pole of the driving transistor M0 in response to the fourth control signal cs4 loaded on the fourth control signal terminal CS4.
  • the pixel circuit may further include: a light emission control circuit 30 .
  • the light emitting control circuit 30 may be coupled to the driving transistor M0 and the light emitting device L respectively.
  • the light emission control circuit 30 may be configured to conduct the first power terminal and the first pole of the driving transistor M0 in response to the first light emission control signal em1 of the first light emission control signal terminal EM1; and in response to the second light emission control The second light-emitting control signal em2 of the signal terminal EM2 conducts the second pole of the driving transistor M0 and the light-emitting device L.
  • the light emission control circuit 30 may be coupled to the first power terminal, the first and second poles of the driving transistor M0 and the first electrode of the light emitting device L, respectively.
  • the pixel circuit may further include: a device reset circuit 40 .
  • the device reset circuit 40 is coupled to the light-emitting device L.
  • the device reset circuit 40 is configured to provide the second initialization signal of the second initialization signal terminal VINIT2 to the light emitting device L in response to the seventh control signal cs7 of the seventh control signal terminal CS7.
  • the device reset circuit 40 may be coupled to the seventh control signal terminal CS7, the second initialization signal terminal VINIT2, and the first electrode of the light emitting device L, respectively.
  • the first electrode of the light-emitting device L may be coupled with the second pole of the driving transistor M0 or the first electrode of the light-emitting device L may be coupled with the second pole of the driving transistor M0 through the light-emitting control circuit 30 .
  • the second electrode of the light emitting device L may be coupled with the second power terminal VSS.
  • the first electrode of the light-emitting device L may be its anode, and the second electrode may be its cathode.
  • the light emitting device L may be an electroluminescent diode.
  • the light-emitting device L may include: a Micro Light Emitting Diode (Micro LED), an Organic Light Emitting Diode (OLED), and a Quantum Dot Light Emitting Diode (QLED). At least one.
  • the specific structure of the light-emitting device L can be designed and determined according to the actual application environment, and is not limited here.
  • the driving transistor M0 can be configured as a P-type transistor; wherein, the first electrode of the driving transistor M0 can be its source electrode, and the second electrode of the driving transistor M0 can be Its drain, and when the driving transistor M0 is in a saturated state, current flows from the source of the driving transistor M0 to its drain.
  • the driving transistor M0 can also be configured as an N-type transistor, which is not limited here.
  • the voltage control circuit 20 may include: a first transistor M1, a second transistor M2, and a storage capacitor CST.
  • the control electrode of the first transistor M1 is coupled to the first control signal terminal CS1
  • the first electrode of the first transistor M1 is coupled to the first initialization signal terminal VINIT1
  • the second electrode of the first transistor M1 is coupled to the first terminal of the driving transistor M0.
  • the control electrode of the second transistor M2 is coupled to the second control signal terminal CS2
  • the first electrode of the second transistor M2 is coupled to the control electrode of the driving transistor M0
  • the second electrode of the second transistor M2 is coupled to the control electrode of the driving transistor M0.
  • the second pole is coupled.
  • the first electrode plate of the storage capacitor CST is coupled to the control electrode of the driving transistor M0
  • the second electrode plate of the storage capacitor CST is coupled to the first electrode of the driving transistor.
  • the first transistor M1 may be turned on under the control of the effective level of the first control signal cs1, and may be turned off under the control of the inactive level of the first control signal cs1.
  • the first transistor M1 can be set as a P-type transistor, then the effective level of the first control signal cs1 is low level, and the inactive level of the first control signal cs1 is high level.
  • the first transistor M1 can also be set as an N-type transistor, then the effective level of the first control signal cs1 is high level, and the inactive level of the first control signal cs1 is low level.
  • the second transistor M2 may be turned on under the control of the effective level of the second control signal cs2, and may be turned off under the control of the inactive level of the second control signal cs2.
  • the second transistor M2 can be set as a P-type transistor, then the effective level of the second control signal cs2 is low level, and the inactive level of the second control signal cs2 is high level.
  • the second transistor M2 can also be set as an N-type transistor, then the effective level of the second control signal cs2 is high level, and the inactive level of the second control signal cs2 is low level.
  • the data writing circuit 10 may include a fourth transistor M4.
  • the control electrode of the fourth transistor M4 is coupled to the fourth control signal terminal CS4
  • the first electrode of the fourth transistor M4 is coupled to the data signal terminal DA
  • the second electrode of the fourth transistor M4 is coupled to the first terminal of the driving transistor M0.
  • Extremely coupled the fourth transistor M4 may be turned on under the control of the effective level of the fourth control signal cs4, and may be turned off under the control of the inactive level of the fourth control signal cs4.
  • the fourth transistor M4 can be set as a P-type transistor, then the effective level of the fourth control signal cs4 is low level, and the inactive level of the fourth control signal cs4 is high level.
  • the fourth transistor M4 can also be set as an N-type transistor, then the effective level of the fourth control signal cs4 is high level, and the inactive level of the fourth control signal cs4 is low level.
  • the lighting control circuit 30 may include a seventh transistor M7 and an eighth transistor M8.
  • the control electrode of the seventh transistor M7 is coupled to the first light-emitting control signal terminal EM1
  • the first electrode of the seventh transistor M7 is coupled to the first power supply terminal
  • the second electrode of the seventh transistor M7 is coupled to the third terminal of the driving transistor M0.
  • the control electrode of the eighth transistor M8 is coupled to the second light-emitting control signal terminal EM2
  • the first electrode of the eighth transistor M8 is coupled to the second electrode of the driving transistor M0
  • the second electrode of the eighth transistor M8 is coupled to the light-emitting device. L coupling.
  • the seventh transistor M7 may be turned on under the control of the effective level of the first light-emitting control signal em1, and may be turned off under the control of the inactive level of the first light-emitting control signal em1.
  • the seventh transistor M7 can be set as a P-type transistor, then the effective level of the first light-emitting control signal em1 is low level, and the inactive level of the first light-emitting control signal em1 is high level.
  • the seventh transistor M7 may also be configured as an N-type transistor, so that the effective level of the first light-emitting control signal em1 is high level and the inactive level of the first light-emitting control signal em1 is low level.
  • the eighth transistor M8 may be turned on under the control of the effective level of the second light-emitting control signal em2, and may be turned off under the control of the inactive level of the second light-emitting control signal em2.
  • the eighth transistor M8 can be set as a P-type transistor, then the effective level of the second light-emitting control signal em2 is low level, and the inactive level of the second light-emitting control signal em2 is high level.
  • the eighth transistor M8 may also be configured as an N-type transistor, so that the effective level of the second light-emitting control signal em2 is high level and the inactive level of the second light-emitting control signal em2 is low level.
  • the device reset circuit 40 may include a ninth transistor M9.
  • the control electrode of the ninth transistor M9 is coupled to the seventh control signal terminal CS7
  • the first electrode of the ninth transistor M9 is coupled to the second initialization signal terminal VINIT2
  • the second electrode of the ninth transistor M9 is coupled to the light-emitting device L. catch.
  • the ninth transistor M9 may be turned on under the control of the effective level of the seventh light-emitting control signal, and may be turned off under the control of the inactive level of the seventh light-emitting control signal.
  • the ninth transistor M9 can be set as a P-type transistor, then the effective level of the seventh light-emitting control signal is low level, and the inactive level of the seventh light-emitting control signal is high level.
  • the ninth transistor M9 can also be configured as an N-type transistor, so that the effective level of the seventh light-emitting control signal is high level and the inactive level of the seventh light-emitting control signal is low level.
  • transistors that use Low Temperature Poly-Silicon (LTPS) material as the active layer have high mobility and can be made thinner and smaller, with lower power consumption.
  • LTPS Low Temperature Poly-Silicon
  • at least one of the above transistors has The material of the source layer can be set to low-temperature polysilicon material. In this way, the above-mentioned transistors can be set as LTPS type transistors, so that the pixel circuit can achieve high mobility and can be made thinner and smaller, with lower power consumption, etc.
  • the leakage current of transistors using metal oxide semiconductor materials as the active layer is small. Therefore, in order to reduce the leakage current, in some embodiments of the present disclosure, the material of the active layer of at least one of the transistors can also include metal oxide.
  • the semiconductor material can be, for example, IGZO (Indium Gallium Zinc Oxide). Of course, it can also be other metal oxide semiconductor materials, which are not limited here. In this way, the above-mentioned transistors can be set as oxide transistors (Oxide Thin Film Transistor) to reduce the leakage current of the pixel circuit.
  • all transistors may be configured as LTPS type transistors.
  • all transistors can be configured as oxide transistors.
  • some of the transistors may be configured as oxide transistors, and the remaining transistors may be configured as LTPS transistors.
  • the first transistor M1 and the second transistor M2 may be configured as oxide-type transistors, and the remaining transistors may be configured as LTPS-type transistors.
  • these two transistor preparation processes are combined to prepare a low-temperature polysilicon oxide LTPO pixel circuit, which can make the leakage current of the control electrode of the driving transistor M0 smaller and reduce the power consumption. Low. Therefore, when the pixel circuit is applied to a display panel, the display uniformity can be ensured when the display panel reduces the refresh frequency for display.
  • the control electrode of the transistor can be used as its gate electrode, the first electrode of the transistor can be used as its source electrode, and the second electrode can be used as its drain electrode; or, conversely, The first electrode of the transistor is used as its drain electrode, and the second electrode is used as its source electrode.
  • This can be designed and determined according to the actual application environment, and no specific distinction will be made here.
  • the first power terminal may be configured to load a constant first power voltage, and the first power voltage is generally a positive value.
  • the second power supply terminal can be loaded with a constant second power supply voltage, and the second power supply voltage can generally be a ground voltage or a negative value.
  • the specific values of the first power supply voltage and the second power supply voltage can be designed and determined according to the actual application environment, and are not limited here.
  • the signal timing diagram corresponding to the pixel circuit shown in Figure 3 is shown in Figure 4a.
  • the maintenance time tcs1 of the effective level (for example, high level) of the first control signal cs1 can be made substantially the same as the maintenance time tcs2 of the effective level (for example, high level) of the second control signal cs2.
  • the starting time kcs1 of the active level of the first control signal cs1 is before the starting time kcs2 of the active level of the second control signal cs2 (eg, high level).
  • the effective level of the first control signal cs1 (for example, high level) and the effective level of the second control signal cs2 (for example, high level) may have no overlapping duration.
  • the starting time kcs4 of the effective level (for example, high level) of the fourth control signal cs4 can be made to be the starting time of the effective level (for example, high level) of the second control signal cs2 After kcs4.
  • the interval duration tg may be less than, greater than, or equal to the duration of the data writing phase.
  • the interval length tg can be determined according to the needs of the actual application, and is not limited here.
  • the maintenance time tcs4 of the effective level (for example, high level) of the fourth control signal cs4 can be made shorter than the maintenance time of the effective level (for example, high level) of the first control signal cs1 tcs1.
  • the fourth control signal cs4 and the seventh control signal cs7 can be set to signals with substantially the same timing.
  • the first light emission control signal em1 and the second light emission control signal em2 can be set to signals with substantially the same timing sequence.
  • the driving method of a pixel circuit may include the following steps:
  • the voltage control circuit responds to the loaded signal and resets the control electrode, the first electrode and the second electrode of the drive transistor before inputting the data voltage;
  • S200 data writing stage, the data writing circuit is configured to respond to the loaded signal and input the data voltage
  • the driving transistor In the light-emitting stage, the driving transistor generates a driving current to drive the light-emitting device to emit light according to the data voltage, and drives the light-emitting device to emit light.
  • the reset phase T1 the data writing phase T2 and the light-emitting phase T3 in the signal timing diagram shown in FIG. 4a are mainly selected.
  • the reset phase T1 includes the T11 phase and the T12 phase.
  • em1 represents the first lighting control signal em1 loaded to the first lighting control signal terminal EM1.
  • em2 represents the second lighting control signal em2 loaded to the second lighting control signal terminal EM2.
  • cs1 represents the first control signal cs1 loaded to the first control signal terminal CS1.
  • cs2 represents the second control signal cs2 loaded to the second control signal terminal CS2.
  • cs4 represents the fourth control signal cs4 loaded to the fourth control signal terminal CS4.
  • cs7 represents the seventh control signal cs7 loaded to the seventh control signal terminal CS7.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the fourth transistor M4 is turned off under the control of the high level of the signal cs4.
  • the seventh transistor M7 is turned off under the control of the high level of the signal em1.
  • the eighth transistor M8 is turned off under the control of the high level of the signal em2.
  • the ninth transistor M9 is turned off under the control of the high level of the signal cs7.
  • the first transistor M1 is turned on under the control of the low level of the signal cs1 to provide the first initialization voltage vinit1 loaded on the first initialization signal terminal VINIT1 to the control electrode of the driving transistor M0 to reset the control electrode of the driving transistor M0 , and maintains the voltage of the control electrode of the driving transistor M0 through the storage capacitor CST.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the fourth transistor M4 is turned off under the control of the high level of the signal cs4.
  • the seventh transistor M7 is turned off under the control of the high level of the signal em1.
  • the eighth transistor M8 is turned off under the control of the high level of the signal em2.
  • the ninth transistor M9 is turned off under the control of the high level of the signal cs7.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2 to connect the control electrode of the driving transistor M0 with the second electrode, so that the driving transistor M0 forms a diode connection.
  • the storage capacitor CST maintains the voltage of the control electrode of the driving transistor M0 as the first initialization voltage vinit1
  • the voltage of the second electrode of the driving transistor M0 can also be changed to the first initialization voltage vinit1
  • the first electrode of the driving transistor M0 can be changed.
  • Vth represents the threshold voltage of the driving transistor M0.
  • the voltage of the control electrode of the driving transistor M0 is the first initialization voltage vinit1
  • the voltage of the second electrode also changes to the first initialization voltage vinit1
  • the voltage of the first electrode becomes vinit1-Vth
  • the voltages of the control electrodes of the driving transistor M0 are approximately the same
  • the voltages of the first electrodes of the driving transistor M0 are approximately the same
  • the voltages of the second electrodes of the driving transistor M0 are approximately the same.
  • the voltages of the poles are roughly the same, which can improve the problem of image retention caused by the hysteresis effect when switching between high and low gray scales.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the seventh transistor M7 is turned off under the control of the high level of the signal em1.
  • the eighth transistor M8 is turned off under the control of the high level of the signal em2.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2 to connect the control electrode of the driving transistor M0 with the second electrode, so that the driving transistor M0 forms a diode connection.
  • the fourth transistor M4 is turned on under the control of the low level of the signal cs4 to input the data voltage Vda loaded to the data signal terminal DA into the first pole of the driving transistor M0, and to the driving transistor through the turned-on second transistor M2
  • the control electrode of M0 is charged, so that the control electrode voltage of the driving transistor M0 becomes Vda+Vth.
  • the ninth transistor M9 is turned on under the control of the low level of the signal cs7 to input the second initialization voltage loaded to the second initialization signal terminal VINIT2 into the first electrode of the light-emitting device L to initialize the light-emitting device L.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the fourth transistor M4 is turned off under the control of the high level of the signal cs4.
  • the ninth transistor M9 is turned off under the control of the high level of the signal cs7.
  • the seventh transistor M7 is turned on under the control of the low level of the signal em1 to provide the first power supply voltage of the first power terminal VDD to the first pole of the driving transistor M0, so that the voltage of the first pole of the driving transistor M0 is Vdd.
  • the turned-on eighth transistor M8 connects the second electrode of the driving transistor M0 to the first electrode of the light-emitting device L, thereby providing the driving current IL to the light-emitting device L to drive the light-emitting device L to emit light.
  • K is a structural constant of the driving transistor M0.
  • the control electrode, the first electrode and the second electrode of the driving transistor M0 can be reset before the data voltage is written. Moreover, since after the reset, the voltage of the control electrode of the driving transistor M0 is the first initialization voltage vinit1, the voltage of the second electrode also changes to the first initialization voltage vinit1, and the voltage of the first electrode becomes vinit1-Vth, therefore,
  • the voltage of the control electrode of the driving transistor M0 is approximately the same, the voltage of the first electrode of the driving transistor M0 is approximately the same, and the voltage of the second electrode of the driving transistor M0 is approximately the same.
  • the voltages of the poles are roughly the same, which can improve the problem of image retention caused by the hysteresis effect when switching between high and low gray scales.
  • the driving current IL that drives the light-emitting device L to emit light is the same as the driving current IL.
  • the threshold voltage of the transistor M0 is independent, so that the influence of the threshold voltage drift of the driving transistor M0 on the light emission of the light-emitting device L can be avoided, and the light-emitting stability can be further improved.
  • the first control signal cs1, the second control signal cs2 and the fourth control signal cs4 may be cascade signals.
  • the pixel circuit in the embodiment of the present disclosure can be applied to a display panel that switches between high and low frequencies.
  • the data voltage Vda can be refreshed only in the refresh frame, but the frame is maintained without writing the data voltage Vda.
  • the first control signal cs1, the second control signal cs2, and the fourth control signal cs4 all need to be refreshed at a low frequency to control the first transistor M1, the second transistor M2, and the fourth transistor M4 to be refreshed at a low frequency.
  • the first electrode of the light-emitting device needs to be reset at a high frequency, so at this time, the control electrode of the ninth transistor M9 needs to be refreshed at a high frequency.
  • the signal cs7 needs to be controlled by a separate circuit and not cascaded with the signals cs1 and cs2. Based on this, the seventh control signal terminal is not set to the same signal terminal as the fourth control signal terminal.
  • Embodiments of the present disclosure provide other signal timing diagrams of the pixel circuit, as shown in Figure 4b, which are modified from the implementation in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and their general similarities will not be described again.
  • the maintenance time tcs4 of the effective level (for example, high level) of the fourth control signal cs4 can be equal to the maintenance time of the effective level (for example, high level) of the first control signal cs1 tcs1 is about the same.
  • the fourth control signal cs4 and the seventh control signal cs7 can be set to signals with substantially the same timing.
  • the effective level of the first control signal cs1 (eg, high level) and the effective level of the second control signal cs2 (eg, high level) have a first overlapping duration td1.
  • the effective level (eg, high level) of the second control signal cs2 and the effective level (eg, high level) of the fourth control signal cs4 also have a first overlapping duration td1.
  • the effective level (for example, high level) of the second control signal cs2 and the effective level (for example, high level) of the seventh control signal cs7 also have a first overlapping duration td1.
  • the first overlap duration td1 can be approximately the same as the duration of the input data voltage (ie, the duration of the data writing phase T2).
  • the signal timing diagram corresponding to the pixel circuit shown in Figure 3 can also be shown in Figure 4b.
  • the first transistor M1 is turned on under the control of the low level of the signal cs1, thereby providing the first initialization voltage loaded to the first initialization signal terminal VINIT1 to the control electrode of the driving transistor M0.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2 to connect the control electrode of the driving transistor M0 with the second electrode, so that the driving transistor M0 forms a diode connection.
  • the control electrode, the first electrode and the second electrode of the driving transistor M0 can be reset before the data voltage is written.
  • other processes in which the pixel circuit shown in FIG. 3 operates in conjunction with the signal timing sequence shown in FIG. 4b can be basically the same as the process in which the pixel circuit shown in FIG. 3 operates in conjunction with the signal timing sequence shown in FIG. 4a.
  • No further details will be given.
  • the first control signal cs1, the second control signal cs2 and the fourth control signal cs4 may be cascade signals.
  • the pixel circuit in the embodiment of the present disclosure can be applied to a display panel that switches between high and low frequencies.
  • the data voltage Vda can be refreshed only in the refresh frame, but the frame is maintained without writing the data voltage Vda.
  • the first control signal cs1, the second control signal cs2, and the fourth control signal cs4 all need to be refreshed at a low frequency to control the first transistor M1, the second transistor M2, and the fourth transistor M4 to be refreshed at a low frequency.
  • the first electrode of the light-emitting device needs to be reset at a high frequency, so at this time the control electrode of the ninth transistor M9 needs to be refreshed at a high frequency.
  • the signal cs7 needs to be controlled by a separate circuit and not cascaded with the signals cs1 and cs2. Based on this, the seventh control signal terminal is not set to the same signal terminal as the fourth control signal terminal.
  • Embodiments of the present disclosure provide other structural schematic diagrams of pixel circuits, as shown in FIG. 6 , which are modified from the implementation in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and their general similarities will not be described again.
  • the first lighting control signal terminal and the second lighting control signal terminal can be set to the same signal terminal. This can reduce the number of signal traces and reduce the difficulty of wiring.
  • the control electrode of the seventh transistor M7 and the control electrode of the eighth transistor M8 may both be coupled to the first light-emitting control signal terminal EM1.
  • the control electrode of the seventh transistor M7 and the control electrode of the eighth transistor M8 may both be coupled to the second light emitting control signal terminal EM2.
  • the seventh control signal terminal and the fourth control signal terminal may be set to the same signal terminal. This can reduce the number of signal traces and reduce the difficulty of wiring.
  • the control electrode of the fourth transistor M4 and the control electrode of the ninth transistor M9 may both be coupled to the fourth control signal terminal CS4.
  • the control electrode of the fourth transistor M4 and the control electrode of the ninth transistor M9 may both be coupled to the seventh control signal terminal CS7.
  • the signal timing diagram corresponding to the pixel circuit shown in Figure 6 can be shown in Figure 7 .
  • the maintenance time tcs4 of the effective level (eg, high level) of the fourth control signal cs4 can be made shorter than the maintenance time tcs1 of the effective level (eg, high level) of the first control signal cs1.
  • the process of the pixel circuit shown in FIG. 6 operating in combination with the signal timing shown in FIG. 7 can be basically the same as the process of the pixel circuit shown in FIG. 3 operating in conjunction with the signal timing shown in FIG. 4a, and will not be described here. Repeat.
  • the signal timing diagram corresponding to the pixel circuit shown in Figure 6 can also be shown in Figure 8 .
  • the duration tcs4 of the active level (eg, high level) of the fourth control signal cs4 can be equal to the duration tcs1 of the active level (eg, high level) of the first control signal cs1.
  • the process of the pixel circuit shown in FIG. 6 operating in combination with the signal timing shown in FIG. 8 can be basically the same as the process of the pixel circuit shown in FIG. 3 operating in conjunction with the signal timing shown in FIG. 4a, and will not be described here. Repeat.
  • the duration tcs4 of the active level (eg, high level) of the fourth control signal cs4 can be equal to the duration tcs1 of the active level (eg, high level) of the first control signal cs1.
  • the effective level of the first control signal cs1 (for example, high level) and the effective level of the second control signal cs2 (for example, high level) have a first overlapping duration td1.
  • the first overlap duration td1 can be approximately the same as the duration of the input data voltage (ie, the duration of the data writing phase T2).
  • the first transistor M1 is turned on under the control of the low level of the signal cs1, thereby providing the first initialization voltage loaded to the first initialization signal terminal VINIT1 to the control electrode of the driving transistor M0.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2 to connect the control electrode of the driving transistor M0 with the second electrode, so that the driving transistor M0 forms a diode connection.
  • the control electrode, the first electrode and the second electrode of the driving transistor M0 can be reset before the data voltage is written.
  • other processes in which the pixel circuit shown in FIG. 6 operates in conjunction with the signal timing sequence shown in FIG. 8 can be basically the same as the process in which the pixel circuit shown in FIG. 3 operates in conjunction with the signal timing sequence shown in FIG. 4a.
  • No further details will be given.
  • the seventh control signal terminal CS7 and the first control signal terminal CS1 can also be set as the same signal terminal.
  • the seventh control signal terminal CS7 and the second control signal terminal CS2 can also be set as the same signal terminal.
  • the seventh control signal terminal CS7 can be set according to the requirements of the actual application, which is not limited here.
  • Embodiments of the present disclosure provide further structural schematic diagrams of pixel circuits, as shown in FIG. 10 , which are modified from the implementation in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and their general similarities will not be described again.
  • the seventh control signal terminal CS7 and the second control signal terminal CS2 can be set to the same signal terminal. This can reduce the number of signal traces and reduce the difficulty of wiring.
  • the control electrode of the fourth transistor M4 and the control electrode of the ninth transistor M9 may both be coupled to the second control signal terminal CS2.
  • the control electrode of the fourth transistor M4 and the control electrode of the ninth transistor M9 may both be coupled to the seventh control signal terminal CS7.
  • the data writing circuit 10 may be further configured to respond to the fifth control signal cs5 loaded by the fifth control signal terminal CS5 and the sixth loaded by the sixth control signal terminal CS6.
  • the control signal cs6 inputs the data voltage loaded on the data signal terminal DA into the first pole of the driving transistor M0.
  • the data writing circuit 10 may include a fifth transistor M5 and a sixth transistor M6. Among them, the control electrode of the fifth transistor M5 is coupled to the fifth control signal terminal CS5, the first electrode of the fifth transistor M5 is coupled to the first electrode of the driving transistor M0, and the second electrode of the fifth transistor M5 is coupled to the sixth transistor M5. The first pole of M6 is coupled.
  • the control electrode of the sixth transistor M6 is coupled to the sixth control signal terminal CS6, and the second electrode of the sixth transistor M6 is coupled to the data signal terminal DA.
  • the fifth transistor M5 may be turned on under the control of the effective level of the fifth control signal cs5 and turned off under the control of the inactive level of the fifth control signal cs5.
  • the fifth transistor M5 is a P-type transistor
  • the effective level of the fifth control signal cs5 is low level
  • the inactive level of the fifth control signal cs5 is high level.
  • the fifth transistor M5 is an N-type transistor
  • the effective level of the fifth control signal cs5 is high level
  • the inactive level of the fifth control signal cs5 is low level.
  • the sixth transistor M6 may be turned on under the control of the effective level of the sixth control signal cs6 and turned off under the control of the inactive level of the sixth control signal cs6.
  • the sixth transistor M6 is a P-type transistor, the effective level of the sixth control signal cs6 is low level, and the inactive level of the sixth control signal cs6 is high level.
  • the sixth transistor M6 is an N-type transistor, the effective level of the sixth control signal cs6 is high level, and the inactive level of the sixth control signal cs6 is low level.
  • the maintenance time of the effective level of at least one of the fifth control signal cs5 and the sixth control signal cs6 is substantially the same as the maintenance time of the effective level of the second control signal cs2.
  • the maintenance duration of the effective level (for example, high level) of the first control signal cs1 can be tcs1
  • the maintenance duration of the effective level (for example, high level) of the second control signal cs2 can be tcs1 .
  • the maintenance time tcs5 of the active level (eg high level) of the fifth control signal cs5 and the active level (eg high level) of the sixth control signal cs6 are substantially the same.
  • the effective level of the first control signal cs1 (for example, high level) and the effective level of the second control signal cs2 (for example, high level) may not overlap. duration.
  • the effective level of the fifth control signal cs5 and the effective level of the sixth control signal cs6 have a second overlapping duration td2.
  • the starting time kcs1 of the effective level (for example, high level) of the first control signal cs1 can be at the effective level of the fifth control signal cs5 (for example, high level).
  • the starting time kcs5 of the effective level of the fifth control signal cs5 is before the starting time kcs2 of the effective level of the second control signal cs2 (for example, high level).
  • the starting time kcs5 of the effective level (for example, high level) of the fifth control signal cs5 is before the starting time kcs6 of the effective level (for example, high level) of the sixth control signal cs6.
  • the start time kcs2 of the effective level of the second control signal cs2 is before the start time kcs6 of the effective level of the sixth control signal cs6 (for example, high level).
  • the timing of the second control signal cs2 and the seventh control signal cs7 can be made approximately the same.
  • the reset phase T1 the data writing phase T2 and the light-emitting phase T3 in the signal timing diagram shown in FIG. 11 are mainly selected.
  • the reset phase T1 includes the T11 phase and the T12 phase.
  • em1 represents the first lighting control signal em1 loaded to the first lighting control signal terminal EM1.
  • em2 represents the second lighting control signal em2 loaded to the second lighting control signal terminal EM2.
  • cs1 represents the first control signal cs1 loaded to the first control signal terminal CS1.
  • cs2 represents the second control signal cs2 loaded to the second control signal terminal CS2.
  • cs5 represents the fourth control signal cs4 loaded to the fifth control signal terminal CS5.
  • cs6 represents the fourth control signal cs4 loaded to the sixth control signal terminal CS6.
  • the second transistor M2 and the ninth transistor M9 are turned off under the control of the high level of the signal cs2.
  • the sixth transistor M6 is turned off under the control of the high level of the signal cs6.
  • the seventh transistor M7 is turned off under the control of the high level of the signal em1.
  • the eighth transistor M8 is turned off under the control of the high level of the signal em2.
  • the first transistor M1 is turned on under the control of the low level of the signal cs1 to provide the first initialization voltage vinit1 loaded on the first initialization signal terminal VINIT1 to the control electrode of the driving transistor M0 to reset the control electrode of the driving transistor M0 , and maintains the voltage of the control electrode of the driving transistor M0 through the storage capacitor CST.
  • the fifth transistor M5 is turned on under the control of the low level of the signal cs5
  • the sixth transistor M6 is turned off. Therefore, the working process of the pixel circuit is not affected.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the sixth transistor M6 is turned off under the control of the high level of the signal cs6.
  • the seventh transistor M7 is turned off under the control of the high level of the signal em1.
  • the eighth transistor M8 is turned off under the control of the high level of the signal em2.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2 to connect the control electrode of the driving transistor M0 with the second electrode, so that the driving transistor M0 forms a diode connection.
  • the storage capacitor CST maintains the voltage of the control electrode of the driving transistor M0 as the first initialization voltage vinit1
  • the voltage of the second electrode of the driving transistor M0 can also be changed to the first initialization voltage vinit1
  • the first electrode of the driving transistor M0 can be changed.
  • Vth represents the threshold voltage of the driving transistor M0.
  • the voltage of the control electrode of the driving transistor M0 is the first initialization voltage vinit1
  • the voltage of the second electrode also changes to the first initialization voltage vinit1
  • the voltage of the first electrode becomes vinit1-Vth
  • the voltages of the control electrodes of the driving transistor M0 are approximately the same
  • the voltages of the first electrodes of the driving transistor M0 are approximately the same
  • the voltages of the second electrodes of the driving transistor M0 are approximately the same.
  • the voltages of the poles are roughly the same, which can improve the problem of image retention caused by the hysteresis effect when switching between high and low gray scales.
  • the ninth transistor M9 is turned on under the control of the low level of the signal cs2 to input the second initialization voltage loaded to the second initialization signal terminal VINIT2 into the first electrode of the light-emitting device L to initialize the light-emitting device L.
  • the fifth transistor M5 is turned on under the control of the low level of the signal cs5, but the sixth transistor M6 is turned off. Therefore, the working process of the pixel circuit is not affected.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the seventh transistor M7 is turned off under the control of the high level of the signal em1.
  • the eighth transistor M8 is turned off under the control of the high level of the signal em2.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2 to connect the control electrode of the driving transistor M0 with the second electrode, so that the driving transistor M0 forms a diode connection.
  • the fifth transistor M5 is turned on under the control of the low level of the signal cs5, and the sixth transistor M6 is turned on under the control of the low level of the signal cs6 to input the data voltage Vda loaded to the data signal terminal DA into the driving transistor.
  • the first electrode of M0 is charged to the control electrode of the driving transistor M0 through the turned-on second transistor M2, so that the control electrode voltage of the driving transistor M0 becomes Vda+Vth.
  • the ninth transistor M9 is turned on under the control of the low level of the signal cs2 to input the second initialization voltage loaded to the second initialization signal terminal VINIT2 into the first electrode of the light-emitting device L to initialize the light-emitting device L.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the second transistor M2 and the ninth transistor M9 are turned off under the control of the high level of the signal cs2.
  • the fifth transistor M5 is turned off under the control of the high level of the signal cs5.
  • the sixth transistor M6 is turned off under the control of the high level of the signal cs6.
  • the seventh transistor M7 is turned on under the control of the low level of the signal em1 to provide the first power supply voltage of the first power terminal VDD to the first pole of the driving transistor M0, so that the voltage of the first pole of the driving transistor M0 is Vdd.
  • the turned-on eighth transistor M8 connects the second electrode of the driving transistor M0 to the first electrode of the light-emitting device L, thereby providing the driving current IL to the light-emitting device L to drive the light-emitting device L to emit light.
  • K is a structural constant of the driving transistor M0.
  • the control electrode, the first electrode and the second electrode of the driving transistor M0 can be reset before the data voltage is written. Moreover, since after the reset, the voltage of the control electrode of the driving transistor M0 is the first initialization voltage vinit1, the voltage of the second electrode also changes to the first initialization voltage vinit1, and the voltage of the first electrode becomes vinit1-Vth, therefore,
  • the voltage of the control electrode of the driving transistor M0 is approximately the same, the voltage of the first electrode of the driving transistor M0 is approximately the same, and the voltage of the second electrode of the driving transistor M0 is approximately the same.
  • the voltages of the poles are roughly the same, which can improve the problem of image retention caused by the hysteresis effect when switching between high and low gray scales.
  • the driving current IL that drives the light-emitting device L to emit light is the same as the driving current IL.
  • the threshold voltage of the transistor M0 is independent, so that the influence of the threshold voltage drift of the driving transistor M0 on the light emission of the light-emitting device L can be avoided, and the light-emitting stability can be further improved.
  • buffer stage T4 between the data writing stage T2 and the light-emitting stage T3.
  • the voltage Vda+Vth of the driving transistor M0 can be further stabilized before entering the light-emitting stage T3.
  • Embodiments of the present disclosure provide further structural schematic diagrams of pixel circuits, as shown in FIG. 12 , which are modified from the implementation in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and their general similarities will not be described again.
  • the first lighting control signal terminal and the second lighting control signal terminal may be set to the same signal terminal. This can reduce the number of signal traces and reduce the difficulty of wiring.
  • the control electrode of the seventh transistor M7 and the control electrode of the eighth transistor M8 may both be coupled to the first light-emitting control signal terminal EM1.
  • the control electrode of the seventh transistor M7 and the control electrode of the eighth transistor M8 may both be coupled to the second light emitting control signal terminal EM2.
  • the signal timing diagram corresponding to the pixel circuit shown in Figure 12 can be as shown in Figure 13a.
  • the process of the pixel circuit shown in FIG. 12 operating in combination with the signal timing shown in FIG. 13a can be basically the same as the process of the pixel circuit shown in FIG. 10 operating in conjunction with the signal timing shown in FIG. 11, and will not be described here. Repeat.
  • the signal timing diagram corresponding to the pixel circuit shown in Figure 12 can also be shown in Figure 13b.
  • the process of the pixel circuit shown in FIG. 12 operating in combination with the signal timing shown in FIG. 13b can be basically the same as the process of the pixel circuit shown in FIG. 10 operating in conjunction with the signal timing shown in FIG. 11, and will not be described here. Repeat.
  • Embodiments of the present disclosure provide further structural schematic diagrams of pixel circuits, as shown in FIG. 14 , which are modified from the implementation in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and their general similarities will not be described again.
  • the fifth control signal terminal and the second control signal terminal may be set to the same signal terminal.
  • the seventh control signal terminal CS7 and the second control signal terminal CS2 are set to the same signal terminal.
  • the first lighting control signal terminal EM1 and the second lighting control signal terminal EM2 are set to the same signal terminal. This can reduce the number of signal traces and reduce the difficulty of wiring.
  • the control electrode of the seventh transistor M7 and the control electrode of the eighth transistor M8 may both be coupled to the first light-emitting control signal terminal EM1.
  • the control electrode of the second transistor M2, the control electrode of the fifth transistor M5, and the control electrode of the ninth transistor M9 may all be coupled to the second control signal terminal CS2.
  • the maintenance duration tcs1 of the effective level (for example, high level) of the first control signal cs1, the effective level (for example, high level) of the second control signal cs2 can be ) and the maintenance time tcs6 of the effective level (for example, high level) of the sixth control signal cs6 are substantially the same.
  • the start time of the maintenance duration tcs1 of the active level (eg high level) of the first control signal cs1 is before the start time of the maintenance duration tcs2 of the active level (eg high level) of the second control signal cs2.
  • the start time of the maintenance duration tcs2 of the active level (eg high level) of the second control signal cs2 is before the start time of the maintenance duration tcs6 of the active level (eg high level) of the sixth control signal cs6.
  • the reset phase T1 the data writing phase T2 and the light-emitting phase T3 in the signal timing diagram shown in FIG. 15 are mainly selected.
  • the reset phase T1 includes the T11 phase and the T12 phase.
  • em1 represents the first lighting control signal em1 loaded to the first lighting control signal terminal EM1.
  • em2 represents the second lighting control signal em2 loaded to the second lighting control signal terminal EM2.
  • cs1 represents the first control signal cs1 loaded to the first control signal terminal CS1.
  • cs2 represents the second control signal cs2 loaded to the second control signal terminal CS2.
  • cs6 represents the fourth control signal cs4 loaded to the sixth control signal terminal CS6.
  • cs7 represents the seventh control signal cs7 loaded to the seventh control signal terminal CS7.
  • the second transistor M2, the fifth transistor M5, and the ninth transistor M9 are turned off under the control of the high level of the signal cs2.
  • the sixth transistor M6 is turned off under the control of the high level of the signal cs6.
  • the seventh transistor M7 and the eighth transistor M8 are turned off under the control of the high level of the signal em1.
  • the ninth transistor M9 is turned off under the control of the high level of the signal cs7.
  • the first transistor M1 is turned on under the control of the low level of the signal cs1 to provide the first initialization voltage vinit1 loaded on the first initialization signal terminal VINIT1 to the control electrode of the driving transistor M0 to reset the control electrode of the driving transistor M0 , and maintains the voltage of the control electrode of the driving transistor M0 through the storage capacitor CST.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the sixth transistor M6 is turned off under the control of the high level of the signal cs6.
  • the seventh transistor M7 and the eighth transistor M8 are turned off under the control of the high level of the signal em1.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2 to connect the control electrode of the driving transistor M0 with the second electrode, so that the driving transistor M0 forms a diode connection.
  • the storage capacitor CST maintains the voltage of the control electrode of the driving transistor M0 as the first initialization voltage vinit1
  • the voltage of the second electrode of the driving transistor M0 can also be changed to the first initialization voltage vinit1
  • the first electrode of the driving transistor M0 can be changed.
  • Vth represents the threshold voltage of the driving transistor M0.
  • the voltage of the control electrode of the driving transistor M0 is the first initialization voltage vinit1
  • the voltage of the second electrode also changes to the first initialization voltage vinit1
  • the voltage of the first electrode becomes vinit1-Vth
  • the voltages of the control electrodes of the driving transistor M0 are approximately the same
  • the voltages of the first electrodes of the driving transistor M0 are approximately the same
  • the voltages of the second electrodes of the driving transistor M0 are approximately the same.
  • the voltages of the poles are roughly the same, which can improve the problem of image retention caused by the hysteresis effect when switching between high and low gray scales.
  • the ninth transistor M9 is turned on under the control of the low level of the signal cs2 to input the second initialization voltage loaded to the second initialization signal terminal VINIT2 into the first electrode of the light-emitting device L to initialize the light-emitting device L.
  • the fifth transistor M5 is turned on under the control of the low level of the signal cs2, but the sixth transistor M6 is turned off. Therefore, the working process of the pixel circuit is not affected.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the seventh transistor M7 and the eighth transistor M8 are turned off under the control of the high level of the signal em1.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2 to connect the control electrode of the driving transistor M0 with the second electrode, so that the driving transistor M0 forms a diode connection.
  • the fifth transistor M5 is turned on under the control of the low level of the signal cs2, and the sixth transistor M6 is turned on under the control of the low level of the signal cs6 to input the data voltage Vda loaded to the data signal terminal DA into the driving transistor.
  • the first electrode of M0 is charged to the control electrode of the driving transistor M0 through the turned-on second transistor M2, so that the control electrode voltage of the driving transistor M0 becomes Vda+Vth.
  • the ninth transistor M9 is turned on under the control of the low level of the signal cs2 to input the second initialization voltage loaded to the second initialization signal terminal VINIT2 into the first electrode of the light-emitting device L to initialize the light-emitting device L.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the second transistor M2, the fifth transistor M5, and the ninth transistor M9 are turned off under the control of the high level of the signal cs2.
  • the sixth transistor M6 is turned off under the control of the high level of the signal cs6.
  • the seventh transistor M7 is turned on under the control of the low level of the signal em1 to provide the first power supply voltage of the first power terminal VDD to the first pole of the driving transistor M0, so that the voltage of the first pole of the driving transistor M0 is Vdd.
  • the turned-on eighth transistor M8 connects the second electrode of the driving transistor M0 to the first electrode of the light-emitting device L, thereby providing the driving current IL to the light-emitting device L to drive the light-emitting device L to emit light.
  • K is a structural constant of the driving transistor M0.
  • the control electrode, the first electrode and the second electrode of the driving transistor M0 can be reset before the data voltage is written. Moreover, since after the reset, the voltage of the control electrode of the driving transistor M0 is the first initialization voltage vinit1, the voltage of the second electrode also changes to the first initialization voltage vinit1, and the voltage of the first electrode becomes vinit1-Vth, therefore,
  • the voltage of the control electrode of the driving transistor M0 is approximately the same, the voltage of the first electrode of the driving transistor M0 is approximately the same, and the voltage of the second electrode of the driving transistor M0 is approximately the same.
  • the voltages of the poles are roughly the same, which can improve the problem of image retention caused by the hysteresis effect when switching between high and low gray scales.
  • the driving current IL that drives the light-emitting device L to emit light is the same as the driving current IL.
  • the threshold voltage of the transistor M0 is independent, so that the influence of the threshold voltage drift of the driving transistor M0 on the light emission of the light-emitting device L can be avoided, and the light-emitting stability can be further improved.
  • buffer stage T4 between the data writing stage T2 and the light-emitting stage T3.
  • the voltage Vda+Vth of the driving transistor M0 can be further stabilized before entering the light-emitting stage T3.
  • Embodiments of the present disclosure provide further structural schematic diagrams of pixel circuits, as shown in FIG. 16 , which are modified from the implementation in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and their general similarities will not be described again.
  • the pixel circuit may further include a threshold compensation circuit 50 .
  • the threshold compensation circuit 50 is coupled to the driving transistor M0, wherein the threshold compensation circuit 50 is configured to, when the data voltage is input, respond to the third control signal cs3 loaded at the third control signal terminal CS3, to adjust the threshold of the driving transistor M0. voltage to compensate.
  • the threshold compensation circuit 50 may include: a third transistor M3. Among them, the control electrode of the third transistor M3 is coupled to the third control signal terminal CS3, the first electrode of the third transistor M3 is coupled to the control electrode of the driving transistor M0, and the second electrode of the third transistor M3 is coupled to the control electrode of the driving transistor M0. The second pole is coupled.
  • the third transistor M3 is turned on under the control of the effective level of the third control signal cs3 and turned off under the control of the inactive level of the third control signal cs3.
  • the third transistor M3 can be set as a P-type transistor, then the effective level of the third control signal cs3 is low level and the inactive level is high level.
  • the third transistor M3 can be set as an N-type transistor, then the effective level of the third control signal cs3 is high level and the inactive level is low level.
  • the signal timing diagram corresponding to the pixel circuit shown in Figure 16 can be as shown in Figure 17 .
  • the process of the pixel circuit shown in FIG. 16 operating in combination with the signal timing shown in FIG. 17 can be basically the same as the process of the pixel circuit shown in FIG. 14 operating in conjunction with the signal timing shown in FIG. 15, and will not be described here. Repeat.
  • At least one sub-pixel (such as each sub-pixel) in the display panel provided by the embodiment of the present disclosure may include any of the above-mentioned pixel circuits provided by the embodiment of the present disclosure.
  • the display panel may also include a plurality of control signal lines and drive control circuits. Wherein, at least one control signal line among the plurality of control signal lines is coupled to the pixel circuit in a row of sub-pixels, and the drive control circuit is coupled to the plurality of control signal lines respectively.
  • the plurality of control signal lines include a plurality of first light-emitting control signal lines, a plurality of second light-emitting control signal lines, a plurality of first control signal lines, a plurality of second control signal lines, a plurality of fifth control signal lines and a plurality of sixth control signal lines; wherein, a first control signal line is coupled to the first control signal terminal CS1 of the pixel circuit in a row of sub-pixels, and a second control signal line is coupled to the first control signal terminal CS1 of the pixel circuit in a row of sub-pixels.
  • the second control signal terminal CS2 of the pixel circuit is coupled, a fifth control signal line is coupled to the fifth control signal terminal CS5 of the pixel circuit in one row of sub-pixels, and a sixth control signal line is coupled to the pixel circuit in one row of sub-pixels.
  • the sixth control signal terminal CS6 is coupled, a first light-emitting control signal line is coupled to the first light-emitting control signal terminal EM1 of the pixel circuit in a row of sub-pixels, and a second light-emitting control signal line is coupled to the pixels in a row of sub-pixels.
  • the second lighting control signal terminal EM2 of the circuit is coupled.
  • the drive control circuit may be disposed in the non-display area, and the drive control circuit may include: a first lighting control circuit 210 , a second lighting control circuit 220 and a first driving control circuit. 310.
  • the first light emission control circuit 210 includes a plurality of first light emission control shift register units arranged in sequence; wherein one first light emission control shift register unit is coupled to a first light emission control signal line coupled to a row of sub-pixels.
  • the second light emission control circuit 220 includes a plurality of second light emission control shift register units arranged in sequence; wherein, one second light emission control shift register unit is coupled to a second light emission control signal line coupled to a row of sub-pixels.
  • the first drive control circuit 310 includes a plurality of first drive shift register units arranged in sequence; each adjacent plurality of first drive shift register units is a first unit group, and one row of sub-pixels corresponds to one first unit. group; and, in the first unit group, the first first driving shift register unit is coupled to the first control signal line coupled to the corresponding row sub-pixel, and the third first driving shift register unit is coupled to the corresponding row sub-pixel.
  • the fifth control signal line coupled to the pixel is coupled, the fourth first driving shift register unit is coupled to the second control signal line coupled to the corresponding row of sub-pixels, and the fifth first driving shift register unit is coupled to the corresponding row sub-pixel.
  • the row sub-pixels are coupled to a sixth control signal line.
  • Driving shift register unit N-2 first driving shift register unit SRGA2 (N-2) ⁇ N+2 first driving shift register unit SRGA2 (N+2), first light emitting control circuit 210
  • N-th first light-emitting control shift register unit SREM1 (N) in the second light-emitting control circuit 220 and an N-th second light-emitting control shift register unit SREM2 (N) in the second light-emitting control circuit 220 An N-th first light-emitting control shift register unit SREM1 (N) in the second light-emitting control circuit 220 and an N-th second light-emitting control shift register unit SREM2 (N) in the second light-emitting control circuit 220 .
  • the Nth first emission control shift register unit SREM1(N) in the first emission control circuit 210 is coupled to the first emission control signal line EM1L(N) corresponding to the Nth row of sub-pixels.
  • the Nth second emission control shift register unit SREM2(N) in the second emission control circuit 220 is coupled to the second emission control signal line EM2L(N) corresponding to the Nth row of sub-pixels.
  • the N-2th first driving shift register unit SRGA2(N-2) in the first driving control circuit 310 is coupled to the first control signal line CS1L(N) corresponding to the Nth row sub-pixel.
  • the Nth first driving shift register unit SRGA2(N) in the first driving control circuit 310 is coupled to the fifth control signal line CS5L(N) corresponding to the Nth row sub-pixel.
  • the N+1th first driving shift register unit SRGA2(N+1) in the first driving control circuit 310 is coupled to the second control signal line CS2L(N) corresponding to the Nth row sub-pixel.
  • the N+2th first driving shift register unit SRGA2(N+2) in the first driving control circuit 310 is coupled to the sixth control signal line CS6L(N) corresponding to the Nth row sub-pixel.
  • the number of first driving shift register units in the first unit group may be set to 6, 7 or more.
  • the number of the first driving shift register units in the first unit group can be determined by the actual application, and the corresponding relationship between the first driving shift register units in the first unit group and the control signal lines of the corresponding rows , as long as the relationship in the above timing diagram is satisfied.
  • Embodiments of the present disclosure provide further structural schematic diagrams of a display panel, as shown in FIG. 19 , which are modified from the implementation in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and their general similarities will not be described again.
  • the plurality of control signal lines may include a plurality of third light-emitting control signal lines; wherein, a third light-emitting control signal line is connected to the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM1 of the pixel circuit in a row of sub-pixels.
  • the signal terminal EM2 is coupled.
  • the drive control circuit includes: a third light-emitting control circuit 230; wherein the third light-emitting control circuit 230 includes a plurality of third light-emitting control shift register units arranged in sequence; wherein one third light-emitting control shift register unit and one row The sub-pixel is coupled to a third light emitting control signal line.
  • Driving shift register unit N-2 first driving shift register unit SRGA1 (N-2) ⁇ N+2 first driving shift register unit SRGA1 (N+2), and the third light emitting control circuit
  • the 1 Nth third lighting control shift register unit SREM3(N) in 230 is coupled to the third lighting control signal line EM3L(N) corresponding to the Nth row sub-pixel.
  • the N-2th first driving shift register unit SRGA1(N-2) in the first driving control circuit 310 is coupled to the first control signal line CS1L(N) corresponding to the Nth row sub-pixel.
  • the Nth first driving shift register unit SRGA1(N) in the first driving control circuit 310 is coupled to the fifth control signal line CS5L(N) corresponding to the Nth row sub-pixel.
  • the N+1th first driving shift register unit SRGA1(N+1) in the first driving control circuit 310 is coupled to the second control signal line CS2L(N) corresponding to the Nth row sub-pixel.
  • the N+2th first driving shift register unit SRGA1(N+2) in the first driving control circuit 310 is coupled to the sixth control signal line CS6L(N) corresponding to the Nth row sub-pixel.
  • the number of first driving shift register units in the first unit group may be set to 6, 7 or more.
  • the number of the first driving shift register units in the first unit group can be determined by the actual application, and the corresponding relationship between the first driving shift register units in the first unit group and the control signal lines of the corresponding rows , as long as the relationship in the above timing diagram is satisfied.
  • Embodiments of the present disclosure provide further structural schematic diagrams of a display panel, as shown in FIG. 20 , which are modified from the implementation in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and their general similarities will not be described again.
  • the plurality of control signal lines may include a plurality of third light-emitting control signal lines, a plurality of first control signal lines, a plurality of second control signal lines and a plurality of sixth control signal lines; wherein, one third light-emitting control signal line
  • the control signal line is coupled to the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 of the pixel circuit in one row of sub-pixels, and a first control signal line is coupled to the first control signal terminal of the pixel circuit in one row of sub-pixels.
  • a second control signal line is coupled to the second control signal terminal CS2 and the fifth control signal terminal CS5 of the pixel circuit in a row of sub-pixels
  • a sixth control signal line is coupled to the pixel circuit of a row of sub-pixels.
  • the sixth control signal terminal CS6 is coupled.
  • the driving control circuit includes: a third lighting control circuit 230 and a second driving control circuit 320; wherein the third lighting control circuit 230 includes a plurality of third lighting circuits arranged in sequence.
  • a shift register unit is controlled; and a third light-emitting control shift register unit is coupled to a third light-emitting control signal line coupled to a row of sub-pixels.
  • the second drive control circuit 320 includes a plurality of second drive shift register units arranged in sequence; each adjacent plurality of second drive shift register units is a second unit group, and one row of sub-pixels corresponds to a second unit group.
  • the first second driving shift register unit is coupled to the first control signal line coupled to the corresponding row of sub-pixels
  • the third second driving shift register unit is coupled to the corresponding row of sub-pixels.
  • the second control signal line of the row sub-pixel coupling is coupled
  • the fifth second driving shift register unit is coupled to the sixth control signal line of the corresponding row sub-pixel coupling.
  • Driving shift register unit N-2nd second driving shift register unit SRGA2 (N-2) ⁇ N+2nd second driving shift register unit SRGA2 (N+2), and the third light emitting control circuit
  • the 1 Nth third lighting control shift register unit SREM3(N) in 230 is coupled to the third lighting control signal line EM3L(N) corresponding to the Nth row sub-pixel.
  • the N-2 second drive shift register unit SRGA2(N-2) in the second drive control circuit 320 is coupled to the first control signal line CS1L(N) corresponding to the N-th row sub-pixel.
  • the Nth second driving shift register unit SRGA2(N) in the second driving control circuit 320 is coupled to the second control signal line CS2L(N) corresponding to the Nth row sub-pixel.
  • the N+2 second driving shift register unit SRGA2(N+2) in the second driving control circuit 320 is coupled to the sixth control signal line CS6L(N) corresponding to the Nth row sub-pixel.
  • the number of second driving shift register units in the second unit group may be set to 6, 7 or more.
  • the number of the second driving shift register units in the second unit group can be determined by the actual application, and the corresponding relationship between the second driving shift register units in the second unit group and the control signal lines of the corresponding rows , as long as the relationship in the above timing diagram is satisfied.
  • Embodiments of the present disclosure provide further structural schematic diagrams of a display panel, as shown in FIG. 21 , which are modified from the implementation in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and their general similarities will not be described again.
  • the plurality of control signal lines may include a plurality of third light-emitting control signal lines, a plurality of first control signal lines, a plurality of second control signal lines and a plurality of fourth control signal lines; wherein, one third light-emitting control signal line
  • the control signal line is coupled to the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 of the pixel circuit in one row of sub-pixels, and a first control signal line is coupled to the first control signal terminal of the pixel circuit in one row of sub-pixels.
  • CS1 is coupled, a second control signal line is coupled to the second control signal terminal CS2 of the pixel circuit in a row of sub-pixels, and a fourth control signal line is coupled to the fourth control signal terminal CS4 of the pixel circuit in a row of sub-pixels. catch.
  • the driving control circuit includes: a third lighting control circuit 230, a third driving control circuit 330 and a fourth driving control circuit 340; wherein the third lighting control circuit 230 includes in sequence A plurality of third light-emitting control shift register units are provided; and a third light-emitting control shift register unit is coupled to a third light-emitting control signal line coupled to a row of sub-pixels.
  • the third drive control circuit 330 includes a plurality of third drive shift register units arranged in sequence; each adjacent plurality of third drive shift register units is a third unit group, and one row of sub-pixels corresponds to a third drive shift register unit.
  • the first third driving shift register unit is coupled to the first control signal line coupled to the corresponding row of sub-pixels
  • the fifth third driving shift register unit is coupled to the corresponding row of sub-pixels.
  • the second control signal line to which the row sub-pixels are coupled is coupled;
  • the fourth drive control circuit 340 includes a plurality of fourth drive shift register units arranged in sequence; one row of sub-pixels corresponds to one fourth drive shift register unit; and,
  • the four-driving shift register unit is coupled to a fourth control signal line coupled to a corresponding row of sub-pixels.
  • Driving shift register unit N-4th third driving shift register unit SRGA3 (N-4) ⁇ N+1th third driving shift register unit SRGA3 (N+1), fourth driving control circuit 340
  • the Nth third lighting control shift register unit SREM3(N) in the third lighting control circuit 230 is coupled to the third lighting control signal line EM3L(N) corresponding to the Nth row of sub-pixels.
  • the Nth fourth drive control shift register unit SRGA4(N) in the fourth drive control circuit 340 is coupled to the fourth control signal line CS4L(N) corresponding to the Nth row sub-pixel.
  • the N-4th third driving shift register unit SRGA3(N-4) in the third driving control circuit 330 is coupled to the first control signal line CS1L(N) corresponding to the Nth row sub-pixel.
  • the Nth third driving shift register unit SRGA3(N) in the third driving control circuit 330 is coupled to the second control signal line CS2L(N) corresponding to the Nth row sub-pixel.
  • the N-1th third lighting control shift register unit SREM3(N-1) in the third lighting control circuit 230 and the third lighting control signal line EM3L(N-1) corresponding to the N-1th row sub-pixel ) coupling is coupled to the third lighting control signal line EM3L(N) corresponding to the Nth row sub-pixel.
  • the N-1th fourth drive control shift register unit SRGA4(N-1) in the fourth drive control circuit 340 is coupled to the fourth control signal line CS4L(N-1) corresponding to the N-1th row sub-pixel. .
  • the Nth fourth drive control shift register unit SRGA4(N) in the fourth drive control circuit 340 is coupled to the fourth control signal line CS4L(N) corresponding to the Nth row sub-pixel.
  • the N-5th third drive shift register unit SRGA3(N-5) is coupled to the first control signal line CS1L(N-1) corresponding to the N-1th row sub-pixel.
  • the N-1 third driving shift register unit SRGA3(N-1) is coupled to the second control signal line CS2L(N-1) corresponding to the N-1 row sub-pixel.
  • the N-4 third driving shift register unit SRGA3(N-4) is coupled to the first control signal line CS1L(N) corresponding to the N-th row sub-pixel.
  • the Nth third drive shift register unit SRGA3(N) is coupled to the second control signal line CS2L(N) corresponding to the Nth row sub-pixel.
  • the number of third driving shift register units in the third unit group may be set to 7, 8 or more.
  • the number of the third driving shift register unit in the third unit group can be determined by the actual application, and the corresponding relationship between the third driving shift register unit in the third unit group and the control signal line of the corresponding row , as long as the relationship in the above timing diagram is satisfied.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • Other essential components of the display device are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.

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Abstract

本公开实施例提供的像素电路、其驱动方法、显示面板及显示装置，包括：发光器件；驱动晶体管，被配置为根据数据电压产生驱动发光器件发光的驱动电流；数据写入电路，与驱动晶体管耦接；其中，数据写入电路被配置为响应于加载的信号，输入数据电压；电压控制电路，与驱动晶体管耦接；其中，电压控制电路被配置为响应于加载的信号，在输入数据电压之前，对驱动晶体管的控制极、第一极以及第二极进行复位。

Description

像素电路、其驱动方法、显示面板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及像素电路、其驱动方法、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)等电致发光二极管具有自发光、低能耗等优点，是当今电致发光显示装置应用研究领域的热点之一。一般电致发光显示装置中采用像素电路来驱动电致发光二极管发光。
发明内容
本公开实施例提供的像素电路，包括：
发光器件；
驱动晶体管，被配置为根据数据电压产生驱动所述发光器件发光的驱动电流；
数据写入电路，与所述驱动晶体管耦接；其中，所述数据写入电路被配置为响应于加载的信号，输入所述数据电压；
电压控制电路，与所述驱动晶体管耦接；其中，所述电压控制电路被配置为响应于加载的信号，在输入所述数据电压之前，对所述驱动晶体管的控制极、第一极以及第二极进行复位。
在一些示例中，所述电压控制电路进一步被配置为响应于第一控制信号端加载的第一控制信号，将第一初始化信号端加载的第一初始化信号，提供给所述驱动晶体管的控制极，对所述驱动晶体管的控制极进行复位；以及，响应于第二控制信号端加载的第二控制信号，对所述驱动晶体管的第一极和 第二极进行复位。
在一些示例中，所述电压控制电路包括：第一晶体管、第二晶体管以及存储电容；
所述第一晶体管的控制极与所述第一控制信号端耦接，所述第一晶体管的第一极与所述第一初始化信号端耦接，所述第一晶体管的第二极与所述驱动晶体管的控制极耦接；
所述第二晶体管的控制极与所述第二控制信号端耦接，所述第二晶体管的第一极与所述驱动晶体管的控制极耦接，所述第二晶体管的第二极与所述驱动晶体管的第二极耦接；
所述存储电容的第一电极板与所述驱动晶体管的控制极耦接，所述存储电容的第二电极板与所述驱动的第一极耦接。
在一些示例中，所述电压控制电路还被配置为在输入所述数据电压时，响应于所述第二控制信号端加载的所述第二控制信号，对所述驱动晶体管的阈值电压进行补偿。
在一些示例中，所述像素电路还包括阈值补偿电路；
所述阈值补偿电路与所述驱动晶体管耦接，其中，所述阈值补偿电路被配置为在输入所述数据电压时，响应于第三控制信号端加载的第三控制信号，对所述驱动晶体管的阈值电压进行补偿。
在一些示例中，所述阈值补偿电路包括：第三晶体管；
所述第三晶体管的控制极与所述第三控制信号端耦接，所述第三晶体管的第一极与所述驱动晶体管的控制极耦接，所述第三晶体管的第二极与所述驱动晶体管的第二极耦接。
在一些示例中，所述数据写入电路进一步被配置为响应于第四控制信号端加载的第四控制信号，将数据信号端加载的所述数据电压输入所述驱动晶体管的第一极。
在一些示例中，所述数据写入电路包括第四晶体管；
所述第四晶体管的控制极与所述第四控制信号端耦接，所述第四晶体管 的第一极与所述数据信号端耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接。
在一些示例中，其中，所述第四控制信号的有效电平的维持时长不大于第一控制信号的有效电平的维持时长。
在一些示例中，所述数据写入电路进一步被配置为响应于第五控制信号端加载的第五控制信号和第六控制信号端加载的第六控制信号，将数据信号端加载的所述数据电压输入所述驱动晶体管的第一极；
所述第五控制信号的有效电平和所述第六控制信号的有效电平具有第二交叠时长，并且所述第五控制信号的有效电平的开始时刻在所述第六控制信号的有效电平的开始时刻之前。
在一些示例中，所述数据写入电路包括：第五晶体管和第六晶体管；
所述第五晶体管的控制极与所述第五控制信号端耦接，所述第五晶体管的第一极与所述驱动晶体管的第一极耦接，所述第五晶体管的第二极与所述第六晶体管的第一极耦接；
所述第六晶体管的控制极与所述第六控制信号端耦接，所述第六晶体管的第二极与所述数据信号端耦接。
在一些示例中，所述第五控制信号和所述第六控制信号中的至少一个的有效电平的维持时长与第二控制信号的有效电平的维持时长大致相同。
在一些示例中，所述第五控制信号的有效电平的开始时刻在所述第二控制信号的有效电平的开始时刻之前，所述第二控制信号的有效电平的开始时刻在所述第六控制信号的有效电平的开始时刻之前。
在一些示例中，所述第五控制信号端和第二控制信号端为同一信号端。
在一些示例中，所述像素电路还包括：
在一些示例中，所述像素电路还包括：
器件复位电路，与所述发光器件耦接；其中，所述器件复位电路被配置为响应于第七控制信号端的第七控制信号，将第二初始化信号端的第二初始化信号提供给所述发光器件。
在一些示例中，所述第七控制信号端与第一控制信号端至第四控制信号端中的一个为同一信号端。
本公开实施例提供返显示面板，包括上述的像素电路。
在一些示例中，所述显示面板包括：
多个子像素；其中，所述多个子像素中的至少一个子像素包括上述的像素电路；
多条控制信号线；其中，所述多条控制信号线中的至少一条控制信号线与一行子像素中的像素电路耦接；
驱动控制电路；其中，所述驱动控制电路分别与所述多条控制信号线耦接。
在一些示例中，所述多条控制信号线包括多条第一控制信号线、多条第二控制信号线、多条第五控制信号线以及多条第六控制信号线；其中，一条所述第一控制信号线与一行子像素中的像素电路的第一控制信号端耦接，一条所述第二控制信号线与一行子像素中的像素电路的第二控制信号端耦接，一条所述第五控制信号线与一行子像素中的像素电路的第五控制信号端耦接，一条所述第六控制信号线与一行子像素中的像素电路的第六控制信号端耦接；
所述驱动控制电路包括：第一驱动控制电路；其中，所述第一驱动控制电路包括依次设置的多个第一驱动移位寄存器单元；以每相邻的多个第一驱动移位寄存器单元为一个第一单元组，且一行子像素对应一个所述第一单元组；并且，所述第一单元组中，第一个第一驱动移位寄存器单元与对应行子像素耦接的所述第一控制信号线耦接，第三个第一驱动移位寄存器单元与对应行子像素耦接的所述第五控制信号线耦接，第四个第一驱动移位寄存器单元与对应行子像素耦接的所述第二控制信号线耦接，第五个第一驱动移位寄存器单元与对应行子像素耦接的所述第六控制信号线耦接。
在一些示例中，所述多条控制信号线包括多条第一控制信号线、多条第二控制信号线以及多条第六控制信号线；其中，一条所述第一控制信号线与一行子像素中的像素电路的第一控制信号端耦接，一条所述第二控制信号线 与一行子像素中的像素电路的第二控制信号端和第五控制信号端耦接，一条所述第六控制信号线与一行子像素中的像素电路的第六控制信号端耦接；
所述驱动控制电路包括：第二驱动控制电路；其中，所述第二驱动控制电路包括依次设置的多个第二驱动移位寄存器单元；以每相邻的多个第二驱动移位寄存器单元为一个第二单元组，且一行子像素对应一个所述第二单元组；并且，所述第二单元组中，第一个第二驱动移位寄存器单元与对应行子像素耦接的所述第一控制信号线耦接，第三个第二驱动移位寄存器单元与对应行子像素耦接的所述第二控制信号线耦接，第五个第二驱动移位寄存器单元与对应行子像素耦接的所述第六控制信号线耦接。
在一些示例中，所述多条控制信号线包括多条第一控制信号线、多条第二控制信号线以及多条第四控制信号线；其中，一条所述第一控制信号线与一行子像素中的像素电路的第一控制信号端耦接，一条所述第二控制信号线与一行子像素中的像素电路的第二控制信号端耦接，一条所述第四控制信号线与一行子像素中的像素电路的第四控制信号端耦接；
所述驱动控制电路包括：第三驱动控制电路和第四驱动控制电路；
所述第三驱动控制电路包括依次设置的多个第三驱动移位寄存器单元；以每相邻的多个第三驱动移位寄存器单元为一个第三单元组，且一行子像素对应一个所述第三单元组；并且，所述第三单元组中，第一个第三驱动移位寄存器单元与对应行子像素耦接的所述第一控制信号线耦接，第五个第三驱动移位寄存器单元与对应行子像素耦接的所述第二控制信号线耦接；
所述第四驱动控制电路包括依次设置的多个第四驱动移位寄存器单元；一行子像素对应一个第四驱动移位寄存器单元；并且，所述第四驱动移位寄存器单元与对应行子像素耦接的所述第四控制信号线耦接。
本公开实施例提供的显示装置，包括上述的显示面板。
本公开实施例提供的用于上述的像素电路的驱动方法，包括：
复位阶段，所述电压控制电路响应于加载的信号，在输入所述数据电压之前，对所述驱动晶体管的控制极、第一极以及第二极进行复位；
数据写入阶段，所述数据写入电路被配置为响应于加载的信号，输入所述数据电压；
发光阶段，所述驱动晶体管根据数据电压产生驱动所述发光器件发光的驱动电流，驱动所述发光器件发光。
附图说明
图1为本公开实施例提供的像素电路的一些结构示意图；
图2为本公开实施例提供的像素电路的另一些结构示意图；
图3为本公开实施例提供的像素电路的一些具体结构示意图；
图4a为本公开实施例提供的一些信号时序图；
图4b为本公开实施例提供的一些信号时序图；
图5为本公开实施例提供的像素电路的驱动方法的一些流程图；
图6为本公开实施例提供的像素电路的另一些具体结构示意图；
图7为本公开实施例提供的另一些信号时序图；
图8为本公开实施例提供的又一些信号时序图；
图9为本公开实施例提供的又一些信号时序图；
图10为本公开实施例提供的像素电路的又一些具体结构示意图；
图11为本公开实施例提供的又一些信号时序图；
图12为本公开实施例提供的像素电路的又一些具体结构示意图；
图13a为本公开实施例提供的又一些信号时序图；
图13b为本公开实施例提供的又一些信号时序图；
图14为本公开实施例提供的像素电路的又一些具体结构示意图；
图15为本公开实施例提供的又一些信号时序图；
图16为本公开实施例提供的像素电路的又一些具体结构示意图；
图17为本公开实施例提供的又一些信号时序图；
图18为本公开实施例提供的显示面板的一些结构示意图；
图19为本公开实施例提供的显示面板的另一些结构示意图；
图20为本公开实施例提供的显示面板的又一些结构示意图；
图21为本公开实施例提供的显示面板的又一些结构示意图；
图22为本公开实施例提供的显示面板的又一些结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，本公开中提到的相同并不能完全相同，可能会有一些测量误差，因此本公开实施例中的相同关系，可以允许有20％内的波动，均属于本发明的保护范围。
在本公开一些实施例中，本公开实施例提供的显示装置可以包括显示面板。显示面板可以包括衬底基板。其中，衬底基板可以包括显示区域和非显示区域(即衬底基板中除显示区域包围区域之外的区域)。其中，显示区域可 以包括多个阵列排布的像素单元。示例性地，每个像素单元包括同一种颜色的子像素或多种不同颜色的子像素。例如，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。下面以像素单元包括红色子像素，绿色子像素以及蓝色子像素为例进行说明。
在本公开一些实施例中，各子像素中可以包括像素电路，像素电路可以包括驱动晶体管M0和发光器件L，以控制发光器件L发光，从而使显示面板实现画面显示的功能。但是由于工艺、老化等原因会造成驱动晶体管M0的阈值电压Vth漂移，对产生的驱动电流造成影响，并且在高低灰阶切换时的迟滞效应，还会造成残影的问题。
为了解决上述问题，本公开实施例提供了一些像素电路，如图1所示，可以包括：驱动晶体管M0，数据写入电路10，以及发光器件L。其中，数据写入电路10与驱动晶体管M0耦接，电压控制电路20与驱动晶体管M0耦接。并且，驱动晶体管M0可以被配置为根据数据电压产生驱动发光器件L发光的电流。数据写入电路10可以被配置为响应于加载的信号，输入数据电压。以及，电压控制电路20可以被配置为响应于加载的信号，在输入数据电压之前，对驱动晶体管M0的控制极、第一极以及第二极进行复位。
本公开实施例提供的像素电路，通过设置电压控制电路，可以在输入数据电压之前，对驱动晶体管的控制极、第一极以及第二极进行复位。这样可以使像素电路在每一个显示帧中工作时，在输入数据电压之前，使驱动晶体管的控制极的电压大致相同，使驱动晶体管的第一极的电压大致相同，以及使驱动晶体管的第二极的电压大致相同，从而可以改善高低灰阶切换时的迟滞效应造成的残影的问题。
在本公开一些实施例中，如图2所示，可以使电压控制电路20分别与第 一控制信号端CS1、第一初始化信号端VINIT1、第二控制信号端CS2以及驱动晶体管M0的控制极和第二极耦接。并且，电压控制电路20进一步被配置为响应于第一控制信号端CS1加载的第一控制信号cs1，将第一初始化信号端VINIT1加载的第一初始化信号，提供给驱动晶体管M0的控制极，对驱动晶体管M0的控制极进行复位；以及，响应于第二控制信号端CS2加载的第二控制信号cs2，对驱动晶体管M0的第一极和第二极进行复位。进一步地，电压控制电路20还被配置为在输入数据电压时，响应于第二控制信号端CS2加载的第二控制信号cs2，对驱动晶体管M0的阈值电压进行补偿。
在本公开一些实施例中，如图2所示，可以使数据写入电路10分别与第四控制信号端CS4、数据信号端DA以及驱动晶体管M0的第一极耦接。并且，数据写入电路10进一步可以被配置为响应于第四控制信号端CS4加载的第四控制信号cs4，将数据信号端DA加载的数据电压输入驱动晶体管M0的第一极。
在本公开一些实施例中，如图2所示，像素电路还可以包括：发光控制电路30。其中，发光控制电路30可以分别与驱动晶体管M0和发光器件L耦接。并且，发光控制电路30可以被配置为响应于第一发光控制信号端EM1的第一发光控制信号em1，将第一电源端与驱动晶体管M0的第一极导通；以及响应于第二发光控制信号端EM2的第二发光控制信号em2，将驱动晶体管M0的第二极与发光器件L导通。示例性地，发光控制电路30可以分别与第一电源端、驱动晶体管M0的第一极和第二极以及发光器件L的第一电极耦接。
在本公开一些实施例中，如图2所示，像素电路还可以包括：器件复位电路40。其中，器件复位电路40与发光器件L耦接。并且，器件复位电路40被配置为响应于第七控制信号端CS7的第七控制信号cs7，将第二初始化信号端VINIT2的第二初始化信号提供给发光器件L。示例性地，器件复位电路40可以分别与第七控制信号端CS7、第二初始化信号端VINIT2以及发光器件L的第一电极耦接。
在本公开一些实施例中，发光器件L的第一电极可以与驱动晶体管M0的第二极耦接或发光器件L的第一电极可以通过发光控制电路30与驱动晶体管M0的第二极耦接。发光器件L的第二电极可以与第二电源端VSS耦接。并且，发光器件L的第一电极可以为其阳极，第二电极为其阴极。示例性地，发光器件L可以为电致发光二极管。例如，发光器件L可以包括：微型发光二极管(Micro Light Emitting Diode，Micro LED)、有机电致发光二极管(Organic Light Emitting Diode，OLED)以及量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)中的至少一种。在实际应用中，可以根据实际应用环境来设计确定发光器件L的具体结构，在此不作限定。
在本公开一些实施例中，如图1与图2所示，驱动晶体管M0可以设置为P型晶体管；其中，驱动晶体管M0的第一极可以为其源极，驱动晶体管M0的第二极可以为其漏极，并且该驱动晶体管M0处于饱和状态时，电流由驱动晶体管M0的源极流向其漏极。当然，驱动晶体管M0也可以设置为N型晶体管，在此不作限定。
在本公开一些实施例中，如图3所示，电压控制电路20可以包括：第一晶体管M1、第二晶体管M2以及存储电容CST。其中，第一晶体管M1的控制极与第一控制信号端CS1耦接，第一晶体管M1的第一极与第一初始化信号端VINIT1耦接，第一晶体管M1的第二极与驱动晶体管M0的控制极耦接。以及，第二晶体管M2的控制极与第二控制信号端CS2耦接，第二晶体管M2的第一极与驱动晶体管M0的控制极耦接，第二晶体管M2的第二极与驱动晶体管M0的第二极耦接。以及，存储电容CST的第一电极板与驱动晶体管M0的控制极耦接，存储电容CST的第二电极板与驱动的第一极耦接。
示例性地，第一晶体管M1可以在第一控制信号cs1的有效电平的控制下导通，可以在第一控制信号cs1的无效电平的控制下截止。例如，第一晶体管M1可以设置为P型晶体管，则第一控制信号cs1的有效电平为低电平，第一控制信号cs1的无效电平为高电平。或者，第一晶体管M1也可以设置为N型晶体管，则第一控制信号cs1的有效电平为高电平，第一控制信号cs1的无 效电平为低电平。
示例性地，第二晶体管M2可以在第二控制信号cs2的有效电平的控制下导通，可以在第二控制信号cs2的无效电平的控制下截止。例如，第二晶体管M2可以设置为P型晶体管，则第二控制信号cs2的有效电平为低电平，第二控制信号cs2的无效电平为高电平。或者，第二晶体管M2也可以设置为N型晶体管，则第二控制信号cs2的有效电平为高电平，第二控制信号cs2的无效电平为低电平。
在本公开一些实施例中，如图3所示，数据写入电路10可以包括第四晶体管M4。其中，第四晶体管M4的控制极与第四控制信号端CS4耦接，第四晶体管M4的第一极与数据信号端DA耦接，第四晶体管M4的第二极与驱动晶体管M0的第一极耦接。示例性地，第四晶体管M4可以在第四控制信号cs4的有效电平的控制下导通，可以在第四控制信号cs4的无效电平的控制下截止。例如，第四晶体管M4可以设置为P型晶体管，则第四控制信号cs4的有效电平为低电平，第四控制信号cs4的无效电平为高电平。或者，第四晶体管M4也可以设置为N型晶体管，则第四控制信号cs4的有效电平为高电平，第四控制信号cs4的无效电平为低电平。
需要说明的是，本公开实施例中，优选地可以使数据写入电路10中设置一个晶体管，这样可以使像素电路的晶体管的数量较少，其在显示面板中占用的空间也较少。
在本公开一些实施例中，如图3所示，发光控制电路30可以包括第七晶体管M7和第八晶体管M8。其中，第七晶体管M7的控制极与第一发光控制信号端EM1耦接，第七晶体管M7的第一极与第一电源端耦接，第七晶体管M7的第二极与驱动晶体管M0的第一极耦接。以及，第八晶体管M8的控制极与第二发光控制信号端EM2耦接，第八晶体管M8的第一极与驱动晶体管M0的第二极耦接，第八晶体管M8的第二极与发光器件L耦接。
示例性地，第七晶体管M7可以在第一发光控制信号em1的有效电平的控制下导通，可以在第一发光控制信号em1的无效电平的控制下截止。例如， 第七晶体管M7可以设置为P型晶体管，则第一发光控制信号em1的有效电平为低电平，第一发光控制信号em1的无效电平为高电平。或者，第七晶体管M7也可以设置为N型晶体管，则第一发光控制信号em1的有效电平为高电平，第一发光控制信号em1的无效电平为低电平。
示例性地，第八晶体管M8可以在第二发光控制信号em2的有效电平的控制下导通，可以在第二发光控制信号em2的无效电平的控制下截止。例如，第八晶体管M8可以设置为P型晶体管，则第二发光控制信号em2的有效电平为低电平，第二发光控制信号em2的无效电平为高电平。或者，第八晶体管M8也可以设置为N型晶体管，则第二发光控制信号em2的有效电平为高电平，第二发光控制信号em2的无效电平为低电平。
在本公开一些实施例中，如图3所示，器件复位电路40可以包括第九晶体管M9。其中，第九晶体管M9的控制极与第七控制信号端CS7耦接，第九晶体管M9的第一极与第二初始化信号端VINIT2耦接，第九晶体管M9的第二极与发光器件L耦接。示例性地，第九晶体管M9可以在第七发光控制信号的有效电平的控制下导通，可以在第七发光控制信号的无效电平的控制下截止。例如，第九晶体管M9可以设置为P型晶体管，则第七发光控制信号的有效电平为低电平，第七发光控制信号的无效电平为高电平。或者，第九晶体管M9也可以设置为N型晶体管，则第七发光控制信号的有效电平为高电平，第七发光控制信号的无效电平为低电平。
一般采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)材料作为有源层的晶体管的迁移率高且可以做得更薄更小、功耗更低等，在具体实施时，上述至少一个晶体管的有源层的材料可以设置为低温多晶硅材料。这样可以将上述晶体管设置为LTPS型晶体管，以使像素电路实现迁移率高且可以做得更薄更小、功耗更低等。
一般采用金属氧化物半导体材料作为有源层的晶体管的漏电流较小，因此为了降低漏电流，在本公开一些实施例中，也可以使上述至少一个晶体管的有源层的材料包括金属氧化物半导体材料，例如可以为IGZO(Indium  Gallium Zinc Oxide，铟镓锌氧化物)，当然，也可以为其他金属氧化物半导体材料，在此不作限定。这样可以将上述晶体管设置为氧化物型晶体管(Oxide Thin Film Transistor)，以使像素电路的漏电流减小。
示例性地，可以将所有晶体管均设置为LTPS型晶体管。或者，可以将所有晶体管均设置为氧化物型晶体管。或者，也可以使部分晶体管设置为氧化物型晶体管，其余晶体管设置为LTPS型晶体管。例如，可以将第一晶体管M1和第二晶体管M2设置为氧化物型晶体管，将其余晶体管设置为LTPS型晶体管。这样通过将LTPS型晶体管与氧化物型晶体管，这两种制备晶体管的工艺进行结合制备低温多晶硅氧化物的LTPO像素电路，可以使驱动晶体管M0的控制极的漏电流较小，以及使功耗较低。从而将该像素电路应用于显示面板中，在显示面板降低刷新频率进行显示时，可以保证显示的均一性。
在具体实施中，可以根据晶体管的类型以及其控制极的信号，将晶体管的控制极作为其栅极，将晶体管的第一极作为其源极，第二极作为其漏极；或者，反之，将晶体管的第一极作为其漏极，第二极作为其源极，这可以根据实际应用环境来设计确定，具体在此不做具体区分。
以上仅是举例说明本公开实施例提供的像素电路中的各电路的具体结构，在具体实施时，上述电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，这些均在本公开的保护范围之内，具体在此不作限定。
在本公开一些实施例中，第一电源端可以被配置为加载恒定的第一电源电压，并且第一电源电压一般为正值。以及，第二电源端可以加载恒定的第二电源电压，并且第二电源电压一般可以为接地电压或为负值。在实际应用中，第一电源电压和第二电源电压的具体数值可以根据实际应用环境来设计确定，在此不作限定。
以上仅是举例说明本公开实施例提供的像素电路中的各电路的具体结构，在具体实施时，上述电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，这些均在本公开的保护范围之内， 具体在此不作限定。
下面以上述各晶体管为P型为例进行说明。示例性地，图3所示的像素电路对应的信号时序图，如图4a所示。可以使第一控制信号cs1的有效电平(例如高电平)的维持时长tcs1与第二控制信号cs2的有效电平(例如高电平)的维持时长tcs2大致相同。并且，第一控制信号cs1的有效电平(例如高电平)的开始时刻kcs1在第二控制信号cs2(例如高电平)的有效电平的开始时刻kcs2之前。
示例性地，如图4a所示，可以使第一控制信号cs1的有效电平(例如高电平)与第二控制信号cs2的有效电平(例如高电平)无交叠时长。
示例性地，如图4a所示，可以使第四控制信号cs4的有效电平(例如高电平)的开始时刻kcs4在第二控制信号cs2的有效电平(例如高电平)的开始时刻kcs4之后。并且，开始时刻kcs4和开始时刻kcs2之间可以具有间隔时长tg。示例性地，间隔时长tg可以小于或大于或等于数据写入阶段的时长。在实际应用中，间隔时长tg可以根据实际应用的需求进行确定，在此不作限定。
示例性地，如图4a所示，可以使第四控制信号cs4的有效电平(例如高电平)的维持时长tcs4小于第一控制信号cs1的有效电平(例如高电平)的维持时长tcs1。
示例性地，如图4a所示，可以使第四控制信号cs4和第七控制信号cs7设置为大致相同时序的信号。
示例性地，如图4a所示，可以使第一发光控制信号em1和第二发光控制信号em2设置为大致相同时序的信号。
如图5所示，本公开实施例提供的像素电路的驱动方法，可以包括如下步骤：
S100、复位阶段，电压控制电路响应于加载的信号，在输入数据电压之前，对驱动晶体管的控制极、第一极以及第二极进行复位；
S200、数据写入阶段，数据写入电路被配置为响应于加载的信号，输入 数据电压；
S300、发光阶段，驱动晶体管根据数据电压产生驱动发光器件发光的驱动电流，驱动发光器件发光。
下面以图3所示的像素电路的结构为例，结合图4a所示的信号时序图，对本公开实施例提供的像素电路在一个显示帧内的工作过程作以描述。其中，主要选取图4a所示的信号时序图中的复位阶段T1、数据写入阶段T2以及发光阶段T3。其中，复位阶段T1包括T11阶段和T12阶段。并且，em1代表加载到第一发光控制信号端EM1的第一发光控制信号em1。em2代表加载到第二发光控制信号端EM2的第二发光控制信号em2。cs1代表加载到第一控制信号端CS1的第一控制信号cs1。cs2代表加载到第二控制信号端CS2的第二控制信号cs2。cs4代表加载到第四控制信号端CS4的第四控制信号cs4。cs7代表加载到第七控制信号端CS7的第七控制信号cs7。
在复位阶段T1中的T11阶段，第二晶体管M2在信号cs2的高电平的控制下截止。第四晶体管M4在信号cs4的高电平的控制下截止。第七晶体管M7在信号em1的高电平的控制下截止。第八晶体管M8在信号em2的高电平的控制下截止。第九晶体管M9在信号cs7的高电平的控制下截止。第一晶体管M1在信号cs1的低电平的控制下导通，以将第一初始化信号端VINIT1加载的第一初始化电压vinit1提供给驱动晶体管M0的控制极，对驱动晶体管M0的控制极进行复位，并通过存储电容CST保持驱动晶体管M0的控制极的电压。
在复位阶段T1中的T12阶段，第一晶体管M1在信号cs1的高电平的控制下截止。第四晶体管M4在信号cs4的高电平的控制下截止。第七晶体管M7在信号em1的高电平的控制下截止。第八晶体管M8在信号em2的高电平的控制下截止。第九晶体管M9在信号cs7的高电平的控制下截止。第二晶体管M2在信号cs2的低电平的控制下导通，以将驱动晶体管M0的控制极与第二极导通，从而使驱动晶体管M0形成二极管连接方式。由于存储电容CST保持驱动晶体管M0的控制极的电压为第一初始化电压vinit1，从而可以将驱动晶体管M0的第二极 的电压也变化为第一初始化电压vinit1，以及将驱动晶体管M0的第一极的电压变为vinit1-Vth。其中，Vth代表驱动晶体管M0的阈值电压。这样可以使驱动晶体管M0的控制极、第一极以及第二极在数据电压写入之前进行重置。并且，由于重置之后，驱动晶体管M0的控制极的电压为第一初始化电压vinit1，第二极的电压也变化为第一初始化电压vinit1，以及第一极的电压变为vinit1-Vth，因此，在像素电路每一个显示帧中工作时，在输入数据电压之前，使驱动晶体管M0的控制极的电压大致相同，使驱动晶体管M0的第一极的电压大致相同，以及使驱动晶体管M0的第二极的电压大致相同，从而可以改善高低灰阶切换时的迟滞效应造成的残影的问题。
在数据写入阶段T2，第一晶体管M1在信号cs1的高电平的控制下截止。第七晶体管M7在信号em1的高电平的控制下截止。第八晶体管M8在信号em2的高电平的控制下截止。第二晶体管M2在信号cs2的低电平的控制下导通，以将驱动晶体管M0的控制极与第二极导通，从而使驱动晶体管M0形成二极管连接方式。第四晶体管M4在信号cs4的低电平的控制下导通，以将加载到数据信号端DA的数据电压Vda输入驱动晶体管M0的第一极，并通过导通的第二晶体管M2对驱动晶体管M0的控制极进行充电，从而使驱动晶体管M0的控制极电压变为Vda+Vth。以及，第九晶体管M9在信号cs7的低电平的控制下导通，以将加载到第二初始化信号端VINIT2的第二初始化电压输入发光器件L的第一电极，对发光器件L进行初始化。
在发光阶段T3，第一晶体管M1在信号cs1的高电平的控制下截止。第二晶体管M2在信号cs2的高电平的控制下截止。第四晶体管M4在信号cs4的高电平的控制下截止。第九晶体管M9在信号cs7的高电平的控制下截止。第七晶体管M7在信号em1的低电平的控制下导通，以将第一电源端VDD的第一电源电压提供给驱动晶体管M0的第一极，以使驱动晶体管M0的第一极的电压为Vdd。由于驱动晶体管M0的控制极电压为Vda+Vth，驱动晶体管M0产生的驱动电流IL为：IL＝K(Vda+Vth-Vdd-Vth) 2＝K(Vda-Vdd) 2。导通的第八晶体管M8将驱动晶体管M0的第二极与发光器件L的第一电极导通， 从而将驱动电流IL提供给发光器件L，以驱动发光器件L发光。并且，K为驱动晶体管M0的结构常数。
需要说明的是，在T12阶段中，可以使驱动晶体管M0的控制极、第一极以及第二极在数据电压写入之前进行重置。并且，由于重置之后，驱动晶体管M0的控制极的电压为第一初始化电压vinit1，第二极的电压也变化为第一初始化电压vinit1，以及第一极的电压变为vinit1-Vth，因此，像素电路在每一个显示帧中工作时，在输入数据电压之前，使驱动晶体管M0的控制极的电压大致相同，使驱动晶体管M0的第一极的电压大致相同，以及使驱动晶体管M0的第二极的电压大致相同，从而可以改善高低灰阶切换时的迟滞效应造成的残影的问题。
需要说明的是，在发光阶段T3，通过驱动电流IL的公式IL＝K(Vda+Vth-Vdd-Vth) 2＝K(Vda-Vdd) 2，可知驱动发光器件L发光的驱动电流IL与驱动晶体管M0的阈值电压无关，从而可以避免驱动晶体管M0的阈值电压漂移对发光器件L的发光影响，进一步提高发光稳定性。
需要说明的是，第一控制信号cs1和第二控制信号cs2以及第四控制信号cs4可以是级联信号。本公开实施例中的像素电路可以应用于高低频切换显示的显示面板中。在显示面板采用低频显示时，数据电压Vda可以仅在刷新帧刷新，而是保持帧不进行数据电压Vda写入。例如，第一控制信号cs1和第二控制信号cs2以及第四控制信号cs4均需要进行低频刷新，以控制第一晶体管M1、第二晶体管M2以及第四晶体管M4均低频熟悉。但是，为了降低发光器件的闪烁，发光器件的第一电极需要进行高频复位，所以此时第九晶体管M9的控制极需要进行高频刷新。此时，则需要将信号cs7进行单独的电路进行控制，不和信号cs1、cs2级联。基于此，第七控制信号端也不与第四控制信号端设置为同一信号端。
本公开实施例提供了像素电路的另一些信号时序图，如图4b所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
示例性地，如图4b所示，可以使第四控制信号cs4的有效电平(例如高电平)的维持时长tcs4与第一控制信号cs1的有效电平(例如高电平)的维持时长tcs1大致相同。以及示例性地，如图4b所示，可以使第四控制信号cs4和第七控制信号cs7设置为大致相同时序的信号。
示例性地，如图4b所示，第一控制信号cs1的有效电平(例如高电平)与第二控制信号cs2的有效电平(例如高电平)具有第一交叠时长td1。第二控制信号cs2的有效电平(例如高电平)与第四控制信号cs4的有效电平(例如高电平)也具有第一交叠时长td1。并且，第二控制信号cs2的有效电平(例如高电平)与第七控制信号cs7的有效电平(例如高电平)也具有第一交叠时长td1。且第一交叠时长td1与输入数据电压的时长(即数据写入阶段T2的时长)可以大致相同。
需要说明的是，图3所示的像素电路对应的信号时序图，也可以如图4b所示。其中，在T12阶段中，第一晶体管M1在信号cs1的低电平的控制下导通，从而将加载到第一初始化信号端VINIT1的第一初始化电压提供给驱动晶体管M0的控制极。第二晶体管M2在信号cs2的低电平的控制下导通，以将驱动晶体管M0的控制极与第二极导通，从而使驱动晶体管M0形成二极管连接方式。这样可以使驱动晶体管M0的控制极、第一极以及第二极在数据电压写入之前进行重置。并且，图3所示的像素电路结合图4b所示的信号时序进行工作的其他过程，可以与图3所示的像素电路结合图4a所示的信号时序进行工作的过程基本大致相同，在此不作赘述。
需要说明的是，第一控制信号cs1和第二控制信号cs2以及第四控制信号cs4可以是级联信号。本公开实施例中的像素电路可以应用于高低频切换显示的显示面板中。在显示面板采用低频显示时，数据电压Vda可以仅在刷新帧刷新，而是保持帧不进行数据电压Vda写入。例如，第一控制信号cs1和第二控制信号cs2以及第四控制信号cs4均需要进行低频刷新，以控制第一晶体管M1、第二晶体管M2以及第四晶体管M4均低频熟悉。但是，为了降低发光器件的闪烁，发光器件的第一电极需要进行高频复位，所以此时第九晶体 管M9的控制极需要进行高频刷新。此时，则需要将信号cs7进行单独的电路进行控制，不和信号cs1、cs2级联。基于此，第七控制信号端也不与第四控制信号端设置为同一信号端。
本公开实施例提供了像素电路的另一些结构示意图，如图6所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开一些实施例中，可以使第一发光控制信号端和第二发光控制信号端设置为同一信号端。这样可以降低信号走线的数量，降低布线难度。示例性地，如图6所示，第七晶体管M7的控制极与第八晶体管M8的控制极可以均与第一发光控制信号端EM1耦接。或者，第七晶体管M7的控制极与第八晶体管M8的控制极也可以均与第二发光控制信号端EM2耦接。
在本公开一些实施例中，可以使第七控制信号端和第四控制信号端设置为同一信号端。这样可以降低信号走线的数量，降低布线难度。示例性地，如图6所示，第四晶体管M4的控制极与第九晶体管M9的控制极可以均与第四控制信号端CS4耦接。或者，第四晶体管M4的控制极与第九晶体管M9的控制极也可以均与第七控制信号端CS7耦接。
需要说明的是，图6所示的像素电路对应的信号时序图，可以如图7所示。可以使第四控制信号cs4的有效电平(例如高电平)的维持时长tcs4小于第一控制信号cs1的有效电平(例如高电平)的维持时长tcs1。以及第一控制信号cs1的有效电平(例如高电平)与第二控制信号cs2的有效电平(例如高电平)无交叠时长。并且，图6所示的像素电路结合图7所示的信号时序进行工作的过程，可以与图3所示的像素电路结合图4a所示的信号时序进行工作的过程基本大致相同，在此不作赘述。
需要说明的是，图6所示的像素电路对应的信号时序图，也可以如图8所示。可以使第四控制信号cs4的有效电平(例如高电平)的维持时长tcs4等于第一控制信号cs1的有效电平(例如高电平)的维持时长tcs1。以及第一 控制信号cs1的有效电平(例如高电平)与第二控制信号cs2的有效电平(例如高电平)无交叠时长。并且，图6所示的像素电路结合图8所示的信号时序进行工作的过程，可以与图3所示的像素电路结合图4a所示的信号时序进行工作的过程基本大致相同，在此不作赘述。
需要说明的是，图6所示的像素电路对应的信号时序图，也可以如图9所示。可以使第四控制信号cs4的有效电平(例如高电平)的维持时长tcs4等于第一控制信号cs1的有效电平(例如高电平)的维持时长tcs1。以及第一控制信号cs1的有效电平(例如高电平)与第二控制信号cs2的有效电平(例如高电平)具有第一交叠时长td1。且第一交叠时长td1与输入数据电压的时长(即数据写入阶段T2的时长)可以大致相同。其中，在T12阶段中，第一晶体管M1在信号cs1的低电平的控制下导通，从而将加载到第一初始化信号端VINIT1的第一初始化电压提供给驱动晶体管M0的控制极。第二晶体管M2在信号cs2的低电平的控制下导通，以将驱动晶体管M0的控制极与第二极导通，从而使驱动晶体管M0形成二极管连接方式。这样可以使驱动晶体管M0的控制极、第一极以及第二极在数据电压写入之前进行重置。并且，图6所示的像素电路结合图8所示的信号时序进行工作的其他过程，可以与图3所示的像素电路结合图4a所示的信号时序进行工作的过程基本大致相同，在此不作赘述。
当然，也可以使第七控制信号端CS7与第一控制信号端CS1设置为同一信号端。或者，也可以使第七控制信号端CS7与第二控制信号端CS2设置为同一信号端。在实际应用中，可以根据实际应用的需求设置第七控制信号端CS7，在此不作限定。
本公开实施例提供了像素电路的又一些结构示意图，如图10所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开一些实施例中，可以使第七控制信号端CS7和第二控制信号端CS2设置为同一信号端。这样可以降低信号走线的数量，降低布线难度。示 例性地，如图10所示，第四晶体管M4的控制极与第九晶体管M9的控制极可以均与第二控制信号端CS2耦接。或者，第四晶体管M4的控制极与第九晶体管M9的控制极也可以均与第七控制信号端CS7耦接。
在本公开一些实施例中，如图10所示，数据写入电路10可以进一步被配置为响应于第五控制信号端CS5加载的第五控制信号cs5和第六控制信号端CS6加载的第六控制信号cs6，将数据信号端DA加载的数据电压输入驱动晶体管M0的第一极。示例性地，如图10所示，数据写入电路10可以包括：第五晶体管M5和第六晶体管M6。其中，第五晶体管M5的控制极与第五控制信号端CS5耦接，第五晶体管M5的第一极与驱动晶体管M0的第一极耦接，第五晶体管M5的第二极与第六晶体管M6的第一极耦接。第六晶体管M6的控制极与第六控制信号端CS6耦接，第六晶体管M6的第二极与数据信号端DA耦接。
示例性地，第五晶体管M5可以在第五控制信号cs5的有效电平的控制下导通，在第五控制信号cs5的无效电平的控制下截止。例如，第五晶体管M5为P型晶体管，则第五控制信号cs5的有效电平为低电平，第五控制信号cs5的无效电平为高电平。或者，第五晶体管M5为N型晶体管，则第五控制信号cs5的有效电平为高电平，第五控制信号cs5的无效电平为低电平。
示例性地，第六晶体管M6可以在第六控制信号cs6的有效电平的控制下导通，在第六控制信号cs6的无效电平的控制下截止。例如，第六晶体管M6为P型晶体管，则第六控制信号cs6的有效电平为低电平，第六控制信号cs6的无效电平为高电平。或者，第六晶体管M6为N型晶体管，则第六控制信号cs6的有效电平为高电平，第六控制信号cs6的无效电平为低电平。
在本公开一些实施例中，第五控制信号cs5和第六控制信号cs6中的至少一个的有效电平的维持时长与第二控制信号cs2的有效电平的维持时长大致相同。示例性地，如图11所示，可以使第一控制信号cs1的有效电平(例如高电平)的维持时长tcs1、第二控制信号cs2的有效电平(例如高电平)的维持时长tcs2、第五控制信号cs5的有效电平(例如高电平)的维持时长tcs5 以及第六控制信号cs6的有效电平(例如高电平)的维持时长tcs6大致相同。
在本公开一些实施例中，如图11所示，可以使第一控制信号cs1的有效电平(例如高电平)与第二控制信号cs2的有效电平(例如高电平)无交叠时长。第五控制信号cs5的有效电平和第六控制信号cs6的有效电平具有第二交叠时长td2。
在本公开一些实施例中，如图11所示，可以使第一控制信号cs1的有效电平(例如高电平)的开始时刻kcs1在第五控制信号cs5(例如高电平)的有效电平的开始时刻kcs5之前。以及使第五控制信号cs5的有效电平(例如高电平)的开始时刻kcs5在第二控制信号cs2(例如高电平)的有效电平的开始时刻kcs2之前。并且第五控制信号cs5的有效电平(例如高电平)的开始时刻kcs5在第六控制信号cs6的有效电平(例如高电平)的开始时刻kcs6之前。以及，使第二控制信号cs2的有效电平(例如高电平)的开始时刻kcs2在第六控制信号cs6(例如高电平)的有效电平的开始时刻kcs6之前。
在本公开一些实施例中，如图11所示，可以使第二控制信号cs2与第七控制信号cs7的时序大致相同。
下面以图10所示的像素电路的结构为例，结合图11所示的信号时序图，对本公开实施例提供的像素电路在一个显示帧内的工作过程作以描述。其中，主要选取图11所示的信号时序图中的复位阶段T1、数据写入阶段T2以及发光阶段T3。其中，复位阶段T1包括T11阶段和T12阶段。并且，em1代表加载到第一发光控制信号端EM1的第一发光控制信号em1。em2代表加载到第二发光控制信号端EM2的第二发光控制信号em2。cs1代表加载到第一控制信号端CS1的第一控制信号cs1。cs2代表加载到第二控制信号端CS2的第二控制信号cs2。cs5代表加载到第五控制信号端CS5的第四控制信号cs4。cs6代表加载到第六控制信号端CS6的第四控制信号cs4。
在复位阶段T1中的T11阶段，第二晶体管M2和第九晶体管M9在信号cs2的高电平的控制下截止。第六晶体管M6在信号cs6的高电平的控制下截止。第七晶体管M7在信号em1的高电平的控制下截止。第八晶体管M8在 信号em2的高电平的控制下截止。第一晶体管M1在信号cs1的低电平的控制下导通，以将第一初始化信号端VINIT1加载的第一初始化电压vinit1提供给驱动晶体管M0的控制极，对驱动晶体管M0的控制极进行复位，并通过存储电容CST保持驱动晶体管M0的控制极的电压。本阶段，虽然第五晶体管M5在信号cs5的低电平的控制下导通，但是第六晶体管M6截止，因此，不影响像素电路的工作过程。
在复位阶段T1中的T12阶段，第一晶体管M1在信号cs1的高电平的控制下截止。第六晶体管M6在信号cs6的高电平的控制下截止。第七晶体管M7在信号em1的高电平的控制下截止。第八晶体管M8在信号em2的高电平的控制下截止。第二晶体管M2在信号cs2的低电平的控制下导通，以将驱动晶体管M0的控制极与第二极导通，从而使驱动晶体管M0形成二极管连接方式。由于存储电容CST保持驱动晶体管M0的控制极的电压为第一初始化电压vinit1，从而可以将驱动晶体管M0的第二极的电压也变化为第一初始化电压vinit1，以及将驱动晶体管M0的第一极的电压变为vinit1-Vth。其中，Vth代表驱动晶体管M0的阈值电压。这样可以使驱动晶体管M0的控制极、第一极以及第二极在数据电压写入之前进行重置。并且，由于重置之后，驱动晶体管M0的控制极的电压为第一初始化电压vinit1，第二极的电压也变化为第一初始化电压vinit1，以及第一极的电压变为vinit1-Vth，因此，在像素电路每一个显示帧中工作时，在输入数据电压之前，使驱动晶体管M0的控制极的电压大致相同，使驱动晶体管M0的第一极的电压大致相同，以及使驱动晶体管M0的第二极的电压大致相同，从而可以改善高低灰阶切换时的迟滞效应造成的残影的问题。并且，第九晶体管M9在信号cs2的低电平的控制下导通，以将加载到第二初始化信号端VINIT2的第二初始化电压输入发光器件L的第一电极，对发光器件L进行初始化。以及，第五晶体管M5在信号cs5的低电平的控制下导通，但是第六晶体管M6截止，因此，不影响像素电路的工作过程。
在数据写入阶段T2，第一晶体管M1在信号cs1的高电平的控制下截止。 第七晶体管M7在信号em1的高电平的控制下截止。第八晶体管M8在信号em2的高电平的控制下截止。第二晶体管M2在信号cs2的低电平的控制下导通，以将驱动晶体管M0的控制极与第二极导通，从而使驱动晶体管M0形成二极管连接方式。第五晶体管M5在信号cs5的低电平的控制下导通，以及第六晶体管M6在信号cs6的低电平的控制下导通，以将加载到数据信号端DA的数据电压Vda输入驱动晶体管M0的第一极，并通过导通的第二晶体管M2对驱动晶体管M0的控制极进行充电，从而使驱动晶体管M0的控制极电压变为Vda+Vth。以及，第九晶体管M9在信号cs2的低电平的控制下导通，以将加载到第二初始化信号端VINIT2的第二初始化电压输入发光器件L的第一电极，对发光器件L进行初始化。
在发光阶段T3，第一晶体管M1在信号cs1的高电平的控制下截止。第二晶体管M2和第九晶体管M9在信号cs2的高电平的控制下截止。第五晶体管M5在信号cs5的高电平的控制下截止。第六晶体管M6在信号cs6的高电平的控制下截止。第七晶体管M7在信号em1的低电平的控制下导通，以将第一电源端VDD的第一电源电压提供给驱动晶体管M0的第一极，以使驱动晶体管M0的第一极的电压为Vdd。由于驱动晶体管M0的控制极电压为Vda+Vth，驱动晶体管M0产生的驱动电流IL为：IL＝K(Vda+Vth-Vdd-Vth) 2＝K(Vda-Vdd) 2。导通的第八晶体管M8将驱动晶体管M0的第二极与发光器件L的第一电极导通，从而将驱动电流IL提供给发光器件L，以驱动发光器件L发光。并且，K为驱动晶体管M0的结构常数。
需要说明的是，在T12阶段中，可以使驱动晶体管M0的控制极、第一极以及第二极在数据电压写入之前进行重置。并且，由于重置之后，驱动晶体管M0的控制极的电压为第一初始化电压vinit1，第二极的电压也变化为第一初始化电压vinit1，以及第一极的电压变为vinit1-Vth，因此，像素电路在每一个显示帧中工作时，在输入数据电压之前，使驱动晶体管M0的控制极的电压大致相同，使驱动晶体管M0的第一极的电压大致相同，以及使驱动晶体管M0的第二极的电压大致相同，从而可以改善高低灰阶切换时的迟滞效应造 成的残影的问题。
需要说明的是，在发光阶段T3，通过驱动电流IL的公式IL＝K(Vda+Vth-Vdd-Vth) 2＝K(Vda-Vdd) 2，可知驱动发光器件L发光的驱动电流IL与驱动晶体管M0的阈值电压无关，从而可以避免驱动晶体管M0的阈值电压漂移对发光器件L的发光影响，进一步提高发光稳定性。
需要说明的是，在数据写入阶段T2和发光阶段T3之间还可以具有缓冲阶段T4，在缓冲阶段T4，可以使驱动晶体管M0的电压Vda+Vth进一步稳定后，再进入发光阶段T3。
本公开实施例提供了像素电路的又一些结构示意图，如图12所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开一些实施例中，可以使第一发光控制信号端和第二发光控制信号端设置为同一信号端。这样可以降低信号走线的数量，降低布线难度。示例性地，如图12所示，第七晶体管M7的控制极与第八晶体管M8的控制极可以均与第一发光控制信号端EM1耦接。或者，第七晶体管M7的控制极与第八晶体管M8的控制极也可以均与第二发光控制信号端EM2耦接。
需要说明的是，图12所示的像素电路对应的信号时序图，可以如图13a所示。并且，图12所示的像素电路结合图13a所示的信号时序进行工作的过程，可以与图10所示的像素电路结合图11所示的信号时序进行工作的过程基本大致相同，在此不作赘述。
需要说明的是，图12所示的像素电路对应的信号时序图，也可以如图13b所示。并且，图12所示的像素电路结合图13b所示的信号时序进行工作的过程，可以与图10所示的像素电路结合图11所示的信号时序进行工作的过程基本大致相同，在此不作赘述。
本公开实施例提供了像素电路的又一些结构示意图，如图14所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开一些实施例中，可以使第五控制信号端和第二控制信号端设置为同一信号端。使第七控制信号端CS7和第二控制信号端CS2设置为同一信号端。以及使第一发光控制信号端EM1和第二发光控制信号端EM2设置为同一信号端。这样可以降低信号走线的数量，降低布线难度。示例性地，如图14所示，第七晶体管M7的控制极与第八晶体管M8的控制极可以均与第一发光控制信号端EM1耦接。第二晶体管M2的控制极、第五晶体管M5的控制极以及第九晶体管M9的控制极可以均与第二控制信号端CS2耦接。
在本公开一些实施例中，如图15所示，可以使第一控制信号cs1的有效电平(例如高电平)的维持时长tcs1、第二控制信号cs2的有效电平(例如高电平)的维持时长tcs2以及第六控制信号cs6的有效电平(例如高电平)的维持时长tcs6大致相同。并且，第一控制信号cs1的有效电平(例如高电平)的维持时长tcs1的开始时刻在第二控制信号cs2的有效电平(例如高电平)的维持时长tcs2的开始时刻之前。以及，第二控制信号cs2的有效电平(例如高电平)的维持时长tcs2的开始时刻在第六控制信号cs6的有效电平(例如高电平)的维持时长tcs6的开始时刻之前。
下面以图14所示的像素电路的结构为例，结合图15所示的信号时序图，对本公开实施例提供的像素电路在一个显示帧内的工作过程作以描述。其中，主要选取图15所示的信号时序图中的复位阶段T1、数据写入阶段T2以及发光阶段T3。其中，复位阶段T1包括T11阶段和T12阶段。并且，em1代表加载到第一发光控制信号端EM1的第一发光控制信号em1。em2代表加载到第二发光控制信号端EM2的第二发光控制信号em2。cs1代表加载到第一控制信号端CS1的第一控制信号cs1。cs2代表加载到第二控制信号端CS2的第二控制信号cs2。cs6代表加载到第六控制信号端CS6的第四控制信号cs4。cs7代表加载到第七控制信号端CS7的第七控制信号cs7。
在复位阶段T1中的T11阶段，第二晶体管M2、第五晶体管M5以及第九晶体管M9在信号cs2的高电平的控制下截止。第六晶体管M6在信号cs6的高电平的控制下截止。第七晶体管M7和第八晶体管M8在信号em1的高 电平的控制下截止。第九晶体管M9在信号cs7的高电平的控制下截止。第一晶体管M1在信号cs1的低电平的控制下导通，以将第一初始化信号端VINIT1加载的第一初始化电压vinit1提供给驱动晶体管M0的控制极，对驱动晶体管M0的控制极进行复位，并通过存储电容CST保持驱动晶体管M0的控制极的电压。
在复位阶段T1中的T12阶段，第一晶体管M1在信号cs1的高电平的控制下截止。第六晶体管M6在信号cs6的高电平的控制下截止。第七晶体管M7和第八晶体管M8在信号em1的高电平的控制下截止。第二晶体管M2在信号cs2的低电平的控制下导通，以将驱动晶体管M0的控制极与第二极导通，从而使驱动晶体管M0形成二极管连接方式。由于存储电容CST保持驱动晶体管M0的控制极的电压为第一初始化电压vinit1，从而可以将驱动晶体管M0的第二极的电压也变化为第一初始化电压vinit1，以及将驱动晶体管M0的第一极的电压变为vinit1-Vth。其中，Vth代表驱动晶体管M0的阈值电压。这样可以使驱动晶体管M0的控制极、第一极以及第二极在数据电压写入之前进行重置。并且，由于重置之后，驱动晶体管M0的控制极的电压为第一初始化电压vinit1，第二极的电压也变化为第一初始化电压vinit1，以及第一极的电压变为vinit1-Vth，因此，在像素电路每一个显示帧中工作时，在输入数据电压之前，使驱动晶体管M0的控制极的电压大致相同，使驱动晶体管M0的第一极的电压大致相同，以及使驱动晶体管M0的第二极的电压大致相同，从而可以改善高低灰阶切换时的迟滞效应造成的残影的问题。并且，第九晶体管M9在信号cs2的低电平的控制下导通，以将加载到第二初始化信号端VINIT2的第二初始化电压输入发光器件L的第一电极，对发光器件L进行初始化。以及，第五晶体管M5在信号cs2的低电平的控制下导通，但是第六晶体管M6截止，因此，不影响像素电路的工作过程。
在数据写入阶段T2，第一晶体管M1在信号cs1的高电平的控制下截止。第七晶体管M7和第八晶体管M8在信号em1的高电平的控制下截止。第二晶体管M2在信号cs2的低电平的控制下导通，以将驱动晶体管M0的控制极 与第二极导通，从而使驱动晶体管M0形成二极管连接方式。第五晶体管M5在信号cs2的低电平的控制下导通，以及第六晶体管M6在信号cs6的低电平的控制下导通，以将加载到数据信号端DA的数据电压Vda输入驱动晶体管M0的第一极，并通过导通的第二晶体管M2对驱动晶体管M0的控制极进行充电，从而使驱动晶体管M0的控制极电压变为Vda+Vth。以及，第九晶体管M9在信号cs2的低电平的控制下导通，以将加载到第二初始化信号端VINIT2的第二初始化电压输入发光器件L的第一电极，对发光器件L进行初始化。
在发光阶段T3，第一晶体管M1在信号cs1的高电平的控制下截止。第二晶体管M2、第五晶体管M5以及第九晶体管M9在信号cs2的高电平的控制下截止。第六晶体管M6在信号cs6的高电平的控制下截止。第七晶体管M7在信号em1的低电平的控制下导通，以将第一电源端VDD的第一电源电压提供给驱动晶体管M0的第一极，以使驱动晶体管M0的第一极的电压为Vdd。由于驱动晶体管M0的控制极电压为Vda+Vth，驱动晶体管M0产生的驱动电流IL为：IL＝K(Vda+Vth-Vdd-Vth) 2＝K(Vda-Vdd) 2。导通的第八晶体管M8将驱动晶体管M0的第二极与发光器件L的第一电极导通，从而将驱动电流IL提供给发光器件L，以驱动发光器件L发光。并且，K为驱动晶体管M0的结构常数。
需要说明的是，在T12阶段中，可以使驱动晶体管M0的控制极、第一极以及第二极在数据电压写入之前进行重置。并且，由于重置之后，驱动晶体管M0的控制极的电压为第一初始化电压vinit1，第二极的电压也变化为第一初始化电压vinit1，以及第一极的电压变为vinit1-Vth，因此，像素电路在每一个显示帧中工作时，在输入数据电压之前，使驱动晶体管M0的控制极的电压大致相同，使驱动晶体管M0的第一极的电压大致相同，以及使驱动晶体管M0的第二极的电压大致相同，从而可以改善高低灰阶切换时的迟滞效应造成的残影的问题。
需要说明的是，在发光阶段T3，通过驱动电流IL的公式IL＝K(Vda+Vth-Vdd-Vth) 2＝K(Vda-Vdd) 2，可知驱动发光器件L发光的驱动电 流IL与驱动晶体管M0的阈值电压无关，从而可以避免驱动晶体管M0的阈值电压漂移对发光器件L的发光影响，进一步提高发光稳定性。
需要说明的是，在数据写入阶段T2和发光阶段T3之间还可以具有缓冲阶段T4，在缓冲阶段T4，可以使驱动晶体管M0的电压Vda+Vth进一步稳定后，再进入发光阶段T3。
本公开实施例提供了像素电路的又一些结构示意图，如图16所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开一些实施例中，像素电路还可以包括阈值补偿电路50。并且，阈值补偿电路50与驱动晶体管M0耦接，其中，阈值补偿电路50被配置为在输入数据电压时，响应于第三控制信号端CS3加载的第三控制信号cs3，对驱动晶体管M0的阈值电压进行补偿。示例性地，阈值补偿电路50可以包括：第三晶体管M3。其中，第三晶体管M3的控制极与第三控制信号端CS3耦接，第三晶体管M3的第一极与驱动晶体管M0的控制极耦接，第三晶体管M3的第二极与驱动晶体管M0的第二极耦接。示例性地，第三晶体管M3在第三控制信号cs3的有效电平的控制下导通，在第三控制信号cs3的无效电平的控制下截止。例如，第三晶体管M3可以设置为P型晶体管，则第三控制信号cs3的有效电平为低电平，无效电平为高电平。或者，第三晶体管M3可以设置为N型晶体管，则第三控制信号cs3的有效电平为高电平，无效电平为低电平。
需要说明的是，图16所示的像素电路对应的信号时序图，可以如图17所示。并且，图16所示的像素电路结合图17所示的信号时序进行工作的过程，可以与图14所示的像素电路结合图15所示的信号时序进行工作的过程基本大致相同，在此不作赘述。
本公开实施例提供的显示面板中的至少一个子像素(如各子像素)可以包括本公开实施例提供的上述任一像素电路。并且，显示面板还可以包括多条控制信号线和驱动控制电路。其中，多条控制信号线中的至少一条控制信号线与一行子像素中的像素电路耦接，以及，驱动控制电路分别与多条控制 信号线耦接。
在本公开一些实施例中，在同一像素电路的第一发光控制信号端EM1和第二发光控制信号端EM2为相互独立的信号端时，在显示面板采用如图10所示的像素电路时，如图18所示，多条控制信号线包括多条第一发光控制信号线、多条第二发光控制信号线、多条第一控制信号线、多条第二控制信号线、多条第五控制信号线以及多条第六控制信号线；其中，一条第一控制信号线与一行子像素中的像素电路的第一控制信号端CS1耦接，一条第二控制信号线与一行子像素中的像素电路的第二控制信号端CS2耦接，一条第五控制信号线与一行子像素中的像素电路的第五控制信号端CS5耦接，一条第六控制信号线与一行子像素中的像素电路的第六控制信号端CS6耦接，一条第一发光控制信号线与一行子像素中的像素电路的第一发光控制信号端EM1耦接，一条第二发光控制信号线与一行子像素中的像素电路的第二发光控制信号端EM2耦接。
在本公开一些实施例中，如图18所示，驱动控制电路可以设置在非显示区域中，驱动控制电路可以包括：第一发光控制电路210、第二发光控制电路220以及第一驱动控制电路310。其中，第一发光控制电路210包括依次设置的多个第一发光控制移位寄存器单元；其中，一个第一发光控制移位寄存器单元与一行子像素耦接的第一发光控制信号线耦接。第二发光控制电路220包括依次设置的多个第二发光控制移位寄存器单元；其中，一个第二发光控制移位寄存器单元与一行子像素耦接的第二发光控制信号线耦接。第一驱动控制电路310包括依次设置的多个第一驱动移位寄存器单元；以每相邻的多个第一驱动移位寄存器单元为一个第一单元组，且一行子像素对应一个第一单元组；并且，第一单元组中，第一个第一驱动移位寄存器单元与对应行子像素耦接的第一控制信号线耦接，第三个第一驱动移位寄存器单元与对应行子像素耦接的第五控制信号线耦接，第四个第一驱动移位寄存器单元与对应行子像素耦接的第二控制信号线耦接，第五个第一驱动移位寄存器单元与对应行子像素耦接的第六控制信号线耦接。
示例性地，以每相邻的5个第一驱动移位寄存器单元为一个第一单元组为例，如图18所示，示意出了第一驱动控制电路310中相邻的5个第一驱动移位寄存器单元：第N-2个第一驱动移位寄存器单元SRGA2(N-2)～第N+2个第一驱动移位寄存器单元SRGA2(N+2)，第一发光控制电路210中的1个第N个第一发光控制移位寄存器单元SREM1(N)以及第二发光控制电路220中的1个第N个第二发光控制移位寄存器单元SREM2(N)。第一发光控制电路210中的第N个第一发光控制移位寄存器单元SREM1(N)与第N行子像素对应的第一发光控制信号线EM1L(N)耦接。第二发光控制电路220中的第N个第二发光控制移位寄存器单元SREM2(N)与第N行子像素对应的第二发光控制信号线EM2L(N)耦接。第一驱动控制电路310中的第N-2个第一驱动移位寄存器单元SRGA2(N-2)与第N行子像素对应的第一控制信号线CS1L(N)耦接。第一驱动控制电路310中的第N个第一驱动移位寄存器单元SRGA2(N)与第N行子像素对应的第五控制信号线CS5L(N)耦接。第一驱动控制电路310中的第N+1个第一驱动移位寄存器单元SRGA2(N+1)与第N行子像素对应的第二控制信号线CS2L(N)耦接。第一驱动控制电路310中的第N+2个第一驱动移位寄存器单元SRGA2(N+2)与第N行子像素对应的第六控制信号线CS6L(N)耦接。
需要说明的是，第一单元组中的第一驱动移位寄存器单元的数量可以设置为6个、7个或更多个。在实际应用中，第一单元组中的第一驱动移位寄存器单元的数量可以实际应用来确定，并且第一单元组中的第一驱动移位寄存器单元与对应行的控制信号线的对应关系，只需满足上述时序图中的关系即可。
本公开实施例提供了显示面板的又一些结构示意图，如图19所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开一些实施例中，在同一像素电路的第一发光控制信号端EM1和第二发光控制信号端EM2为同一信号端时，例如，显示面板采用图12所示 的像素电路时，如图19所示，多条控制信号线可以包括多条第三发光控制信号线；其中，一条第三发光控制信号线与一行子像素中的像素电路的第一发光控制信号端EM1和第二发光控制信号端EM2耦接。并且，驱动控制电路包括：第三发光控制电路230；其中，第三发光控制电路230包括依次设置的多个第三发光控制移位寄存器单元；其中，一个第三发光控制移位寄存器单元与一行子像素耦接的第三发光控制信号线耦接。
示例性地，以每相邻的5个第一驱动移位寄存器单元为一个第一单元组为例，如图19所示，示意出了第一驱动控制电路310中相邻的5个第一驱动移位寄存器单元：第N-2个第一驱动移位寄存器单元SRGA1(N-2)～第N+2个第一驱动移位寄存器单元SRGA1(N+2)，以及第三发光控制电路230中的1个第N个第三发光控制移位寄存器单元SREM3(N)。第三发光控制电路230中的第N个第三发光控制移位寄存器单元SREM3(N)与第N行子像素对应的第三发光控制信号线EM3L(N)耦接。第一驱动控制电路310中的第N-2个第一驱动移位寄存器单元SRGA1(N-2)与第N行子像素对应的第一控制信号线CS1L(N)耦接。第一驱动控制电路310中的第N个第一驱动移位寄存器单元SRGA1(N)与第N行子像素对应的第五控制信号线CS5L(N)耦接。第一驱动控制电路310中的第N+1个第一驱动移位寄存器单元SRGA1(N+1)与第N行子像素对应的第二控制信号线CS2L(N)耦接。第一驱动控制电路310中的第N+2个第一驱动移位寄存器单元SRGA1(N+2)与第N行子像素对应的第六控制信号线CS6L(N)耦接。
需要说明的是，第一单元组中的第一驱动移位寄存器单元的数量可以设置为6个、7个或更多个。在实际应用中，第一单元组中的第一驱动移位寄存器单元的数量可以实际应用来确定，并且第一单元组中的第一驱动移位寄存器单元与对应行的控制信号线的对应关系，只需满足上述时序图中的关系即可。
本公开实施例提供了显示面板的又一些结构示意图，如图20所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例 的区别之处，其大致相同之处在此不作赘述。
在本公开一些实施例中，在同一像素电路的第一发光控制信号端EM1和第二发光控制信号端EM2为同一信号端时，例如，显示面板采用图14所示的像素电路时，如图20所示，多条控制信号线可以包括多条第三发光控制信号线、多条第一控制信号线、多条第二控制信号线以及多条第六控制信号线；其中，一条第三发光控制信号线与一行子像素中的像素电路的第一发光控制信号端EM1和第二发光控制信号端EM2耦接，一条第一控制信号线与一行子像素中的像素电路的第一控制信号端CS1耦接，一条第二控制信号线与一行子像素中的像素电路的第二控制信号端CS2和第五控制信号端CS5耦接，一条第六控制信号线与一行子像素中的像素电路的第六控制信号端CS6耦接。
在本公开一些实施例中，如图20所示，驱动控制电路包括：第三发光控制电路230和第二驱动控制电路320；其中，第三发光控制电路230包括依次设置的多个第三发光控制移位寄存器单元；并且，一个第三发光控制移位寄存器单元与一行子像素耦接的第三发光控制信号线耦接。以及，第二驱动控制电路320包括依次设置的多个第二驱动移位寄存器单元；以每相邻的多个第二驱动移位寄存器单元为一个第二单元组，且一行子像素对应一个第二单元组；并且，第二单元组中，第一个第二驱动移位寄存器单元与对应行子像素耦接的第一控制信号线耦接，第三个第二驱动移位寄存器单元与对应行子像素耦接的第二控制信号线耦接，第五个第二驱动移位寄存器单元与对应行子像素耦接的第六控制信号线耦接。
示例性地，以每相邻的5个第二驱动移位寄存器单元为一个第二单元组为例，如图20所示，示意出了第二驱动控制电路320中相邻的5个第二驱动移位寄存器单元：第N-2个第二驱动移位寄存器单元SRGA2(N-2)～第N+2个第二驱动移位寄存器单元SRGA2(N+2)，以及第三发光控制电路230中的1个第N个第三发光控制移位寄存器单元SREM3(N)。第三发光控制电路230中的第N个第三发光控制移位寄存器单元SREM3(N)与第N行子像素对应的第三发光控制信号线EM3L(N)耦接。第二驱动控制电路320中的第N-2个第 二驱动移位寄存器单元SRGA2(N-2)与第N行子像素对应的第一控制信号线CS1L(N)耦接。第二驱动控制电路320中的第N个第二驱动移位寄存器单元SRGA2(N)与第N行子像素对应的第二控制信号线CS2L(N)耦接。第二驱动控制电路320中的第N+2个第二驱动移位寄存器单元SRGA2(N+2)与第N行子像素对应的第六控制信号线CS6L(N)耦接。
需要说明的是，第二单元组中的第二驱动移位寄存器单元的数量可以设置为6个、7个或更多个。在实际应用中，第二单元组中的第二驱动移位寄存器单元的数量可以实际应用来确定，并且第二单元组中的第二驱动移位寄存器单元与对应行的控制信号线的对应关系，只需满足上述时序图中的关系即可。
本公开实施例提供了显示面板的又一些结构示意图，如图21所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开一些实施例中，在同一像素电路的第一发光控制信号端EM1和第二发光控制信号端EM2为同一信号端时，例如，显示面板采用图7所示的像素电路时，如图21所示，多条控制信号线可以包括多条第三发光控制信号线、多条第一控制信号线、多条第二控制信号线以及多条第四控制信号线；其中，一条第三发光控制信号线与一行子像素中的像素电路的第一发光控制信号端EM1和第二发光控制信号端EM2耦接，一条第一控制信号线与一行子像素中的像素电路的第一控制信号端CS1耦接，一条第二控制信号线与一行子像素中的像素电路的第二控制信号端CS2耦接，一条第四控制信号线与一行子像素中的像素电路的第四控制信号端CS4耦接。
在本公开一些实施例中，如图21所示，驱动控制电路包括：第三发光控制电路230、第三驱动控制电路330和第四驱动控制电路340；其中，第三发光控制电路230包括依次设置的多个第三发光控制移位寄存器单元；并且，一个第三发光控制移位寄存器单元与一行子像素耦接的第三发光控制信号线耦接。以及，第三驱动控制电路330包括依次设置的多个第三驱动移位寄存 器单元；以每相邻的多个第三驱动移位寄存器单元为一个第三单元组，且一行子像素对应一个第三单元组；并且，第三单元组中，第一个第三驱动移位寄存器单元与对应行子像素耦接的第一控制信号线耦接，第五个第三驱动移位寄存器单元与对应行子像素耦接的第二控制信号线耦接；第四驱动控制电路340包括依次设置的多个第四驱动移位寄存器单元；一行子像素对应一个第四驱动移位寄存器单元；并且，第四驱动移位寄存器单元与对应行子像素耦接的第四控制信号线耦接。
示例性地，以每相邻的5个第三驱动移位寄存器单元为一个第三单元组为例，如图21所示，示意出了第三驱动控制电路330中相邻的6个第三驱动移位寄存器单元：第N-4个第三驱动移位寄存器单元SRGA3(N-4)～第N+1个第三驱动移位寄存器单元SRGA3(N+1)、第四驱动控制电路340中的1个第四驱动移位寄存器单元SRGA4(N)、以及第三发光控制电路230中的1个第N个第三发光控制移位寄存器单元SREM3(N)。其中，第三发光控制电路230中的第N个第三发光控制移位寄存器单元SREM3(N)与第N行子像素对应的第三发光控制信号线EM3L(N)耦接。第四驱动控制电路340中的第N个第四驱动控制移位寄存器单元SRGA4(N)与第N行子像素对应的第四控制信号线CS4L(N)耦接。第三驱动控制电路330中的第N-4个第三驱动移位寄存器单元SRGA3(N-4)与第N行子像素对应的第一控制信号线CS1L(N)耦接。第三驱动控制电路330中的第N个第三驱动移位寄存器单元SRGA3(N)与第N行子像素对应的第二控制信号线CS2L(N)耦接。
示例性地，如图22所示，示意出了第三驱动控制电路330中相邻的7个第三驱动移位寄存器单元：第N-3个第三驱动移位寄存器单元SRGA3(N-3)～第N+1个第三驱动移位寄存器单元SRGA3(N+1)、第四驱动控制电路340中的2个第四驱动移位寄存器单元SRGA4(N-1)～SRGA4(N)、以及第三发光控制电路230中的2个第N个第三发光控制移位寄存器单元SREM3(N-1)～SREM3(N)。其中，第三发光控制电路230中的第N-1个第三发光控制移位寄存器单元SREM3(N-1)与第N-1行子像素对应的第三发光控制信 号线EM3L(N-1)耦接。第三发光控制电路230中的第N个第三发光控制移位寄存器单元SREM3(N)与第N行子像素对应的第三发光控制信号线EM3L(N)耦接。第四驱动控制电路340中的第N-1个第四驱动控制移位寄存器单元SRGA4(N-1)与第N-1行子像素对应的第四控制信号线CS4L(N-1)耦接。第四驱动控制电路340中的第N个第四驱动控制移位寄存器单元SRGA4(N)与第N行子像素对应的第四控制信号线CS4L(N)耦接。第三驱动控制电路330中，第N-5个第三驱动移位寄存器单元SRGA3(N-5)与第N-1行子像素对应的第一控制信号线CS1L(N-1)耦接。第N-1个第三驱动移位寄存器单元SRGA3(N-1)与第N-1行子像素对应的第二控制信号线CS2L(N-1)耦接。第N-4个第三驱动移位寄存器单元SRGA3(N-4)与第N行子像素对应的第一控制信号线CS1L(N)耦接。第N个第三驱动移位寄存器单元SRGA3(N)与第N行子像素对应的第二控制信号线CS2L(N)耦接。
需要说明的是，第三单元组中的第三驱动移位寄存器单元的数量可以设置为7个、8个或更多个。在实际应用中，第三单元组中的第三驱动移位寄存器单元的数量可以实际应用来确定，并且第三单元组中的第三驱动移位寄存器单元与对应行的控制信号线的对应关系，只需满足上述时序图中的关系即可。
需要说明的是，在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变 型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (23)

  1. 一种像素电路，包括：
    发光器件；
    驱动晶体管，被配置为根据数据电压产生驱动所述发光器件发光的驱动电流；
    数据写入电路，与所述驱动晶体管耦接；其中，所述数据写入电路被配置为响应于加载的信号，输入所述数据电压；
    电压控制电路，与所述驱动晶体管耦接；其中，所述电压控制电路被配置为响应于加载的信号，在输入所述数据电压之前，对所述驱动晶体管的控制极、第一极以及第二极进行复位。
  2. 如权利要求1所述的像素电路，其中，所述电压控制电路进一步被配置为响应于第一控制信号端加载的第一控制信号，将第一初始化信号端加载的第一初始化信号，提供给所述驱动晶体管的控制极，对所述驱动晶体管的控制极进行复位；以及，响应于第二控制信号端加载的第二控制信号，对所述驱动晶体管的第一极和第二极进行复位。
  3. 如权利要求2所述的像素电路，其中，所述电压控制电路包括：第一晶体管、第二晶体管以及存储电容；
    所述第一晶体管的控制极与所述第一控制信号端耦接，所述第一晶体管的第一极与所述第一初始化信号端耦接，所述第一晶体管的第二极与所述驱动晶体管的控制极耦接；
    所述第二晶体管的控制极与所述第二控制信号端耦接，所述第二晶体管的第一极与所述驱动晶体管的控制极耦接，所述第二晶体管的第二极与所述驱动晶体管的第二极耦接；
    所述存储电容的第一电极板与所述驱动晶体管的控制极耦接，所述存储电容的第二电极板与所述驱动的第一极耦接。
  4. 如权利要求2或3所述的像素电路，其中，所述电压控制电路还被配 置为在输入所述数据电压时，响应于所述第二控制信号端加载的所述第二控制信号，对所述驱动晶体管的阈值电压进行补偿。
  5. 如权利要求2或3所述的像素电路，其中，所述像素电路还包括阈值补偿电路；
    所述阈值补偿电路与所述驱动晶体管耦接，其中，所述阈值补偿电路被配置为在输入所述数据电压时，响应于第三控制信号端加载的第三控制信号，对所述驱动晶体管的阈值电压进行补偿。
  6. 如权利要求5所述的像素电路，其中，所述阈值补偿电路包括：第三晶体管；
    所述第三晶体管的控制极与所述第三控制信号端耦接，所述第三晶体管的第一极与所述驱动晶体管的控制极耦接，所述第三晶体管的第二极与所述驱动晶体管的第二极耦接。
  7. 如权利要求1-6任一项所述的像素电路，其中，所述数据写入电路进一步被配置为响应于第四控制信号端加载的第四控制信号，将数据信号端加载的所述数据电压输入所述驱动晶体管的第一极。
  8. 如权利要求7所述的像素电路，其中，所述数据写入电路包括第四晶体管；
    所述第四晶体管的控制极与所述第四控制信号端耦接，所述第四晶体管的第一极与所述数据信号端耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接。
  9. 如权利要求8所述的像素电路，其中，所述第四控制信号的有效电平的维持时长不大于第一控制信号的有效电平的维持时长。
  10. 如权利要求1-9任一项所述的像素电路，其中，所述数据写入电路进一步被配置为响应于第五控制信号端加载的第五控制信号和第六控制信号端加载的第六控制信号，将数据信号端加载的所述数据电压输入所述驱动晶体管的第一极；
    所述第五控制信号的有效电平和所述第六控制信号的有效电平具有第二 交叠时长，并且所述第五控制信号的有效电平的开始时刻在所述第六控制信号的有效电平的开始时刻之前。
  11. 如权利要求10所述的像素电路，其中，所述数据写入电路包括：第五晶体管和第六晶体管；
    所述第五晶体管的控制极与所述第五控制信号端耦接，所述第五晶体管的第一极与所述驱动晶体管的第一极耦接，所述第五晶体管的第二极与所述第六晶体管的第一极耦接；
    所述第六晶体管的控制极与所述第六控制信号端耦接，所述第六晶体管的第二极与所述数据信号端耦接。
  12. 如权利要求11所述的像素电路，其中，所述第五控制信号和所述第六控制信号中的至少一个的有效电平的维持时长与第二控制信号的有效电平的维持时长大致相同。
  13. 如权利要求12所述的像素电路，其中，所述第五控制信号的有效电平的开始时刻在所述第二控制信号的有效电平的开始时刻之前，所述第二控制信号的有效电平的开始时刻在所述第六控制信号的有效电平的开始时刻之前。
  14. 如权利要求13所述的像素电路，其中，所述第五控制信号端和第二控制信号端为同一信号端。
  15. 如权利要求1-14任一项所述的像素电路，其中，所述像素电路还包括：
    器件复位电路，与所述发光器件耦接；其中，所述器件复位电路被配置为响应于第七控制信号端的第七控制信号，将第二初始化信号端的第二初始化信号提供给所述发光器件。
  16. 如权利要求15所述的像素电路，其中，所述第七控制信号端与第一控制信号端至第四控制信号端中的一个为同一信号端。
  17. 一种显示面板，包括如权利要求1-16任一项所述的像素电路。
  18. 如权利要求17所述的显示面板，其中，所述显示面板包括：
    多个子像素；其中，所述多个子像素中的至少一个子像素包括如权利要求1-16任一项所述的像素电路；
    多条控制信号线；其中，所述多条控制信号线中的至少一条控制信号线与一行子像素中的像素电路耦接；
    驱动控制电路；其中，所述驱动控制电路分别与所述多条控制信号线耦接。
  19. 如权利要求18所述的显示面板，其中，所述多条控制信号线包括多条第一控制信号线、多条第二控制信号线、多条第五控制信号线以及多条第六控制信号线；其中，一条所述第一控制信号线与一行子像素中的像素电路的第一控制信号端耦接，一条所述第二控制信号线与一行子像素中的像素电路的第二控制信号端耦接，一条所述第五控制信号线与一行子像素中的像素电路的第五控制信号端耦接，一条所述第六控制信号线与一行子像素中的像素电路的第六控制信号端耦接；
    所述驱动控制电路包括：第一驱动控制电路；其中，所述第一驱动控制电路包括依次设置的多个第一驱动移位寄存器单元；以每相邻的多个第一驱动移位寄存器单元为一个第一单元组，且一行子像素对应一个所述第一单元组；并且，所述第一单元组中，第一个第一驱动移位寄存器单元与对应行子像素耦接的所述第一控制信号线耦接，第三个第一驱动移位寄存器单元与对应行子像素耦接的所述第五控制信号线耦接，第四个第一驱动移位寄存器单元与对应行子像素耦接的所述第二控制信号线耦接，第五个第一驱动移位寄存器单元与对应行子像素耦接的所述第六控制信号线耦接。
  20. 如权利要求18所述的显示面板，其中，所述多条控制信号线包括多条第一控制信号线、多条第二控制信号线以及多条第六控制信号线；其中，一条所述第一控制信号线与一行子像素中的像素电路的第一控制信号端耦接，一条所述第二控制信号线与一行子像素中的像素电路的第二控制信号端和第五控制信号端耦接，一条所述第六控制信号线与一行子像素中的像素电路的第六控制信号端耦接；
    所述驱动控制电路包括：第二驱动控制电路；其中，所述第二驱动控制电路包括依次设置的多个第二驱动移位寄存器单元；以每相邻的多个第二驱动移位寄存器单元为一个第二单元组，且一行子像素对应一个所述第二单元组；并且，所述第二单元组中，第一个第二驱动移位寄存器单元与对应行子像素耦接的所述第一控制信号线耦接，第三个第二驱动移位寄存器单元与对应行子像素耦接的所述第二控制信号线耦接，第五个第二驱动移位寄存器单元与对应行子像素耦接的所述第六控制信号线耦接。
  21. 如权利要求19所述的显示面板，其中，所述多条控制信号线包括多条第一控制信号线、多条第二控制信号线以及多条第四控制信号线；其中，一条所述第一控制信号线与一行子像素中的像素电路的第一控制信号端耦接，一条所述第二控制信号线与一行子像素中的像素电路的第二控制信号端耦接，一条所述第四控制信号线与一行子像素中的像素电路的第四控制信号端耦接；
    所述驱动控制电路包括：第三驱动控制电路和第四驱动控制电路；
    所述第三驱动控制电路包括依次设置的多个第三驱动移位寄存器单元；以每相邻的多个第三驱动移位寄存器单元为一个第三单元组，且一行子像素对应一个所述第三单元组；并且，所述第三单元组中，第一个第三驱动移位寄存器单元与对应行子像素耦接的所述第一控制信号线耦接，第五个第三驱动移位寄存器单元与对应行子像素耦接的所述第二控制信号线耦接；
    所述第四驱动控制电路包括依次设置的多个第四驱动移位寄存器单元；一行子像素对应一个第四驱动移位寄存器单元；并且，所述第四驱动移位寄存器单元与对应行子像素耦接的所述第四控制信号线耦接。
  22. 一种显示装置，包括如权利要求17-21任一项所述的显示面板。
  23. 一种用于如权利要求1-16任一项所述的像素电路的驱动方法，包括：
    复位阶段，所述电压控制电路响应于加载的信号，在输入所述数据电压之前，对所述驱动晶体管的控制极、第一极以及第二极进行复位；
    数据写入阶段，所述数据写入电路被配置为响应于加载的信号，输入所述数据电压；
    发光阶段，所述驱动晶体管根据数据电压产生驱动所述发光器件发光的驱动电流，驱动所述发光器件发光。
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