WO2022007445A1 - 三维电容制备方法 - Google Patents

三维电容制备方法 Download PDF

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Publication number
WO2022007445A1
WO2022007445A1 PCT/CN2021/084141 CN2021084141W WO2022007445A1 WO 2022007445 A1 WO2022007445 A1 WO 2022007445A1 CN 2021084141 W CN2021084141 W CN 2021084141W WO 2022007445 A1 WO2022007445 A1 WO 2022007445A1
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layer
electrode layer
hole
substrate
wall
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PCT/CN2021/084141
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English (en)
French (fr)
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张卫
刘子玉
陈琳
孙清清
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复旦大学
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Publication of WO2022007445A1 publication Critical patent/WO2022007445A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/88—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by patterning layers, e.g. by etching conductive layers

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a method for preparing a three-dimensional capacitor.
  • the purpose of the present disclosure is to provide a method for preparing a three-dimensional capacitor.
  • the three-dimensional capacitor prepared by the method has a small occupied area and can greatly improve the area utilization rate on the chip.
  • a three-dimensional capacitor fabrication method including: forming a through hole in a substrate; forming a patterned first electrode layer on an inner wall of the through hole and a surface of the substrate , the first electrode layer includes an electrode layer formed of a two-dimensional material; an insulating medium layer is formed on the first electrode layer; and a second electrode layer is formed on the insulating medium layer.
  • the forming the patterned first electrode layer on the inner wall of the through hole and the surface of the substrate includes: electroplating a mixed electrode on the inner wall of the through hole and the surface of the substrate.
  • a two-dimensional material copper electroplating solution is used to form an electroplating layer; and copper in the electroplating layer is wet-etched to obtain the patterned first electrode layer.
  • the forming the patterned first electrode layer on the inner wall of the through hole and the surface of the substrate includes: chemical vapor deposition, forming a patterned first electrode layer on the inner wall of the through hole and the surface of the substrate.
  • the patterned first electrode layer is formed on the surface.
  • the first electrode layer further includes a metal adhesion layer
  • the method further includes: prior to forming the electrode layer formed of the two-dimensional material, placing an inner wall of the through hole on the inner wall of the through hole and the substrate. A patterned metal adhesion layer is formed on the surface, wherein the electrode layer formed of the two-dimensional material is located above the metal adhesion layer.
  • the forming a patterned metal adhesion layer on the inner wall of the through hole and the surface of the substrate includes: depositing on the inner wall of the through hole and the surface of the substrate by atomic layer deposition depositing the metal adhesion layer thereon; forming the patterned metal adhesion layer by photolithography.
  • the forming a patterned metal adhesion layer on the inner wall of the through hole and the surface of the substrate includes: magnetron sputtering on the inner wall of the through hole and the surface of the substrate.
  • the metal adhesion layer is formed on the surface; the patterned metal adhesion layer is formed by photolithography.
  • the method further comprises: before forming the patterned first electrode layer on the inner wall of the through hole and the surface of the substrate, forming a patterned first electrode layer on the inner wall of the through hole and the surface of the substrate An insulating layer is formed thereon, wherein the insulating layer is located under the first electrode layer.
  • the forming an insulating layer on the inner wall of the through hole and the surface of the substrate includes: forming the insulating layer on the inner wall of the through hole and the surface of the substrate by thermal oxidation .
  • the forming an insulating layer on the inner wall of the through hole and the surface of the substrate includes: forming an insulating layer on the inner wall of the through hole and the surface of the substrate by plasma chemical vapor deposition. the insulating layer.
  • the forming an insulating medium layer on the first electrode layer includes: forming an insulating medium layer on the first electrode layer by deposition; and forming a second electrode on the insulating medium layer layer, including: forming a second electrode layer on the insulating medium layer by sputtering deposition.
  • the plate area of the three-dimensional capacitor can be increased, thereby greatly improving the capacitance value of the three-dimensional capacitor, and greatly improving the utilization rate of the area on the chip.
  • the center of the through hole can still be used as a three-dimensional interconnection, that is, an interconnection layer for three-dimensional interconnection can still be formed in the center of the through hole. The formation of three-dimensional capacitance on the inner wall of the through hole not only does not affect the interconnection function of the through hole, but also greatly improves the functional density of the through hole.
  • FIG. 1 is a schematic cross-sectional view of a three-dimensional capacitor according to an embodiment of the present disclosure.
  • FIG. 2 is another schematic cross-sectional view of a three-dimensional capacitor according to an embodiment of the present disclosure.
  • FIG. 3 is a flowchart of a method for fabricating a three-dimensional capacitor according to an embodiment of the present disclosure.
  • 4a-4i are schematic cross-sectional flowchart diagrams of a method for fabricating a three-dimensional capacitor according to an embodiment of the present disclosure.
  • 5a-5f are further schematic cross-sectional flow diagrams of a method for fabricating a three-dimensional capacitor according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic cross-sectional view of a three-dimensional capacitor according to an embodiment of the present disclosure.
  • the three-dimensional capacitor includes: a substrate 1 ; a through hole 2 located in the substrate 1 ; a patterned first electrode layer located on the inner wall of the through hole 2 and the surface of the substrate 1 , the first electrode layer
  • the electrode layer includes an electrode layer 3 a formed of a two-dimensional material; an insulating medium layer 4 on the first electrode layer; and a second electrode layer 5 on the insulating medium layer 4 .
  • a semiconductor-insulating layer-metal type three-dimensional capacitor can be formed.
  • the substrate 1 may be one of a high resistance silicon substrate 1, a glass substrate 1, an organic substrate substrate 1, or other types of substrates. That is, the present disclosure does not limit the specific type of the substrate 1 .
  • a two-dimensional material refers to a material in which electrons can move freely (planar motion) on the nanoscale in only two dimensions, such as nano-thin film materials, superlattice materials, quantum well materials, and the like.
  • the two-dimensional material can be graphene.
  • the insulating dielectric layer 4 may be formed of SiO 2 /SiN, or may be formed of a high dielectric constant insulating medium to increase the dielectric constant of the insulating dielectric layer 4 , such as HfO 2 , TiO 2 or PbZr 0.52 Ti 0.48 O 3 formed.
  • the insulating medium layer 4 and the second electrode layer 5 may have the same shape as the first electrode layer, that is, the same shape.
  • the plate area of the three-dimensional capacitor can be increased, thereby greatly improving the capacitance value of the three-dimensional capacitor, and greatly improving the utilization rate of the area on the chip.
  • the center of the through hole 2 can still be used as a three-dimensional interconnection, that is, an interconnection layer for three-dimensional interconnection can still be formed in the center of the through hole 2 Therefore, using the inner wall of the through hole 2 to form a three-dimensional capacitor not only does not affect the interconnection function of the through hole 2 , but also greatly improves the functional density of the through hole 2 .
  • FIG. 2 is another schematic cross-sectional view of a three-dimensional capacitor according to an embodiment of the present disclosure.
  • the first electrode layer may further include a metal adhesion layer 3b located under the electrode layer 3a formed of a two-dimensional material.
  • the metal adhesion layer 3b may be formed of TiN, TiW/Cu or Cr/Ni.
  • the metal adhesion layer 3b plays the role of electrode connection or lead-out of the pad;
  • the function of the electrode layer 3a formed of the two-dimensional material is to prevent the electrode layer 3a formed of the two-dimensional material from falling off due to poor adhesion to the substrate 1, thereby ensuring the stability of the electrode layer 3a formed of the two-dimensional material.
  • the three-dimensional capacitor may further include an insulating layer 6 located on the inner wall of the through hole 2 and the surface of the substrate 1, and the insulating layer 6 is located under the first electrode layer.
  • the insulating layer 6 may be formed of SiO 2 /SiN, SiO 2 or the like.
  • FIG. 3 is a flowchart of a method for fabricating a three-dimensional capacitor according to an embodiment of the present disclosure. As shown in FIG. 3, the method includes the following steps S11 to S15.
  • step S11 through holes are formed in the substrate
  • a patterned first electrode layer is formed on the inner wall of the through hole and the surface of the substrate, and the first electrode layer includes an electrode layer formed of a two-dimensional material;
  • step S13 an insulating medium layer is formed on the first electrode layer.
  • step S14 a second electrode layer is formed on the insulating medium layer.
  • the plate area of the three-dimensional capacitor can be increased, thereby greatly improving the capacitance value of the three-dimensional capacitor, and greatly improving the utilization rate of the area on the chip.
  • the center of the through hole 2 can still be used as a three-dimensional interconnection, that is, an interconnection layer for three-dimensional interconnection can still be formed in the center of the through hole, so Using the inner wall of the through hole to form a three-dimensional capacitor not only does not affect the interconnection function of the through hole, but also greatly improves the functional density of the through hole.
  • 4a-4i are schematic cross-sectional flowchart diagrams of a method for fabricating a three-dimensional capacitor according to an embodiment of the present disclosure.
  • through holes 2 are formed in the substrate 1 .
  • the through hole 2 can be formed in the substrate 1 by a deep silicon etching method, but those skilled in the art should understand that the deep silicon etching method here is only an example, and any other method capable of forming a through hole is also possible of.
  • the substrate 1 may be one of a high resistance silicon substrate 1, a glass substrate 1, an organic substrate substrate 1, or other types of substrates.
  • the size of the through hole 2 is determined according to actual needs. For example, the diameter of the through hole 2 may be 5 micrometers to 20 micrometers, and the depth may be 40 micrometers to 100 micrometers.
  • an insulating layer 6 is formed on the inner wall of the through hole 2 and the surface of the substrate 1 .
  • the insulating layer 6 may be formed of SiO 2 /SiN, SiO 2 or the like.
  • the thickness of the insulating layer 6 may be 200nm-500nm.
  • the insulating layer 6 can be formed by thermal oxidation.
  • any method capable of forming the insulating layer is feasible, such as plasma chemical vapor deposition, physical deposition and other methods are also feasible.
  • this step is optional. That is, if a semiconductor-insulating layer-metal type three-dimensional capacitor is to be formed, this step can be omitted. This step is necessary if a metal-insulating layer-metal type three-dimensional capacitor is to be formed, and the insulating layer 6 formed serves to prevent substrate leakage.
  • a patterned metal adhesion layer 3b is formed on the insulating layer 6, which metal adhesion layer 3b belongs to the first electrode layer.
  • the metal adhesion layer 3b may be formed of TiN, TiW/Cu, Cr/Ni, or the like.
  • the metal adhesion layer 3b plays the role of electrode connection or lead-out of the pad;
  • the function of the electrode layer 3a formed of the two-dimensional material is to prevent the electrode layer 3a formed of the two-dimensional material from falling off due to poor adhesion to the substrate 1, thereby ensuring the stability of the electrode layer 3a formed of the two-dimensional material.
  • This step can also be omitted, that is, an electrode layer formed of a two-dimensional material can be directly formed on the insulating layer 6 .
  • the layer of the 3D capacitor includes a window prepared as a lead-out pad, a plane part of the three-dimensional capacitor (ie, the part of the three-dimensional capacitor located on the surface of the substrate 1) and the part of the three-dimensional capacitor located on the inner wall of the through hole.
  • FIG. 4d the planar part of the three-dimensional capacitor and the part of the three-dimensional capacitor located on the inner wall of the via hole are exposed by photolithography, so as to avoid depositing two-dimensional material on the substrate insulating layer in subsequent steps.
  • reference numeral 7 denotes the photoresist remaining after photolithography.
  • a copper plating solution mixed with two-dimensional materials is used to plate a layer of two-dimensional material and copper on the plane part of the three-dimensional capacitor and the inner wall part of the through hole of the three-dimensional capacitor, wherein the electroplated two-dimensional material and copper are Commonly referred to by reference numeral 3a-1 in Figure 4e.
  • the mixing ratio of two-dimensional materials in the copper electroplating solution is set according to the required plate area of the three-dimensional capacitor. In order to obtain a large plate area, a high proportion of two-dimensional materials is usually mixed in the copper electroplating solution.
  • the copper electroplating baths here are only examples, and any type of electroplating bath that can achieve metal electroplating is possible.
  • the two-dimensional material can be, for example, a nano-thin film material, a superlattice material, a quantum well material, and the like.
  • the two-dimensional material can be graphene.
  • the two-dimensional material and the copper layer 3a-1 are wet-etched to obtain the electrode layer 3a formed of the two-dimensional material, that is, only the two-dimensional material is left in the electrode layer 3a.
  • Wet etching can be implemented using, for example, copper etching solutions or other types of metal etching solutions.
  • the copper etching solution can be, for example, a cuprammonium etching solution, a FeCl3 etching solution, and the like.
  • the electrode layer 3a formed of the two-dimensional material and the metal adhesion layer 3b together constitute the first electrode layer.
  • an insulating dielectric layer 4 is formed on the electrode layer 3a formed of a two-dimensional material.
  • the shape of the insulating medium layer 4 is the same as that of the electrode layer 3a formed of the two-dimensional material, that is, the shape is the same.
  • the insulating medium layer 4 may be formed of SiO 2 /SiN, or may be formed of a high dielectric constant insulating medium to increase the dielectric constant of the insulating medium layer 4 , such as HfO 2 , TiO 2 or PbZr 0.52 Ti 0.48 O 3 .
  • the insulating medium layer 4 can be formed by a deposition method (eg, physical vapor deposition, chemical vapor deposition, atomic layer deposition, magnetron sputtering deposition, etc.).
  • a second electrode layer 5 is formed on the insulating dielectric layer 4 .
  • the second electrode layer 5 can be formed by sputter deposition, chemical vapor deposition, physical vapor deposition, electroplating, or the like.
  • the three-dimensional capacitor has been prepared.
  • the electrode lead-out pads of the three-dimensional capacitor can be formed through a re-wiring process, or the three-dimensional capacitor can be integrated with other devices by re-wiring.
  • 5a-5f are further schematic cross-sectional flow diagrams of a method for fabricating a three-dimensional capacitor according to an embodiment of the present disclosure.
  • through holes 2 are formed in the substrate 1 .
  • the through hole 2 can be formed in the substrate 1 by a deep silicon etching method, but those skilled in the art should understand that the deep silicon etching method here is only an example, and any other method capable of forming a through hole is also possible of.
  • the substrate 1 may be one of a high resistance silicon substrate 1, a glass substrate 1, an organic substrate substrate 1, or other types of substrates.
  • the size of the through hole 2 is determined according to actual needs. For example, the diameter of the through hole 2 may be 5 micrometers to 20 micrometers, and the depth may be 40 micrometers to 100 micrometers.
  • an insulating layer 6 is formed on the inner wall of the through hole 2 and the surface of the substrate 1 by a plasma chemical vapor deposition method.
  • the purpose of growing the insulating layer 6 in this method is to reduce the two-dimensionality in the subsequent steps. Deposition of material on insulating layer 6 .
  • the insulating layer 6 may be formed of SiO 2 /SiN, SiO 2 or the like.
  • the thickness of the insulating layer 6 may be 200nm-500nm.
  • this step is optional. That is, if a semiconductor-insulating layer-metal type three-dimensional capacitor is to be formed, this step can be omitted. This step is necessary if a metal-insulating layer-metal type three-dimensional capacitor is to be formed, and the insulating layer 6 formed serves to prevent substrate leakage.
  • a metal adhesion layer 3b is formed on the insulating layer 6 by a magnetron sputtering method, and the metal adhesion layer 3b belongs to the first electrode layer.
  • the metal adhesion layer 3b may be formed of TiN, TiW/Cu, Cr/Ni, or the like.
  • the metal adhesion layer 3b plays the role of electrode connection or lead-out of the pad;
  • the function of the electrode layer 3a formed of the two-dimensional material is to prevent the electrode layer 3a formed of the two-dimensional material from falling off due to poor adhesion to the substrate 1, thereby ensuring the stability of the electrode layer 3a formed of the two-dimensional material.
  • This step can also be omitted, that is, an electrode layer formed of a two-dimensional material can be directly formed on the insulating layer 6 .
  • the metal adhesion layer 3b is patterned by photolithography, and then photolithography is performed to expose the planar part of the three-dimensional capacitor and the part of the three-dimensional capacitor located on the inner wall of the through hole
  • a layer of two-dimensional material is selectively deposited on the metal adhesion layer 3b but not on the insulating layer 6 by the chemical vapor deposition method to form the electrode layer 3a composed of the two-dimensional material and its patterning .
  • the deposition can be performed by using this method after optimizing parameters such as the substrate temperature, rotation, power, and deposition time of the chemical vapor deposition process.
  • the two-dimensional material can be, for example, a nano-thin film material, a superlattice material, a quantum well material, and the like.
  • the two-dimensional material can be graphene.
  • an insulating dielectric layer 4 is formed on the electrode layer 3 a formed of a two-dimensional material, and a second electrode layer 5 is formed on the insulating dielectric layer 4 .
  • the insulating medium layer 4 and the second electrode layer 5 have the same shape as the electrode layer 3a formed of a two-dimensional material, that is, the same shape.
  • the insulating medium layer 4 may be formed of SiO 2 /SiN, or may be formed of a high dielectric constant insulating medium to increase the dielectric constant of the insulating medium layer 4 , such as HfO 2 , TiO 2 or PbZr 0.52 Ti 0.48 O 3 .
  • the insulating medium layer 4 can be formed by a deposition method (eg, physical vapor deposition, chemical vapor deposition, atomic layer deposition, magnetron sputtering deposition, etc.).
  • the second electrode layer 5 may be formed by sputtering deposition, chemical vapor deposition, physical vapor deposition, electroplating, or the like.
  • the three-dimensional capacitor has been prepared.
  • the electrode lead-out pads of the three-dimensional capacitor can be formed through a re-wiring process, or the three-dimensional capacitor can be integrated with other devices by re-wiring.

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Abstract

一种三维电容制备方法，属于半导体技术领域，其所制备的三维电容的占用面积小，能够极大地提高芯片上面积利用率。一种三维电容制备方法，包括：在衬底（1）中形成通孔（2）；在所述通孔（2）的内壁和所述衬底（1）的表面上形成图形化的第一电极层，所述第一电极层包括由二维材料形成的电极层（3a）；在所述第一电极层上形成绝缘介质层（4）；以及在所述绝缘介质层（4）上形成第二电极层（5）。

Description

三维电容制备方法 技术领域
本公开涉及半导体技术领域，具体地，涉及一种三维电容制备方法。
背景技术
随着半导体器件特征尺寸的进一步等比例缩小，传统的半导体器件将达到尺寸的极限。三维集成已经成为集成电路重要发展方向之一，但是随着集成器件和芯片的种类和数目越来越多，三维集成系统对于芯片上面积的需求越来越大，但系统中还存在很多占用面积较大的元素，因此，如何减小这些元素的占用面积是亟需解决的问题。
发明内容
本公开的目的是提供一种三维电容制备方法，其所制备的三维电容的占用面积小，能够极大地提高芯片上面积利用率。
根据本公开的第一实施例，提供一种三维电容制备方法，包括：在衬底中形成通孔；在所述通孔的内壁和所述衬底的表面上形成图形化的第一电极层，所述第一电极层包括由二维材料形成的电极层；在所述第一电极层上形成绝缘介质层；以及在所述绝缘介质层上形成第二电极层。
可选地，所述在所述通孔的内壁和所述衬底的表面上形成图形化的第一电极层，包括：在所述通孔的内壁和所述衬底的表面上电镀混合了二维材料的铜电镀液，形成电镀层；对所述电镀层中的铜进行湿法刻蚀，得到图形化的所述第一电极层。
可选地，所述在所述通孔的内壁和所述衬底的表面上形成图形化的第一电极层，包括：通过化学气相沉积，在所述通孔的内壁和所述衬底的表 面上形成图形化的所述第一电极层。
可选地，所述第一电极层还包括金属粘附层，所述方法还包括：在形成由所述二维材料形成的电极层之前，在所述通孔的内壁和所述衬底的表面上形成图形化的金属粘附层，其中，所述由所述二维材料形成的电极层位于所述金属粘附层的上方。
可选地，所述在所述通孔的内壁和所述衬底的表面上形成图形化的金属粘附层，包括：通过原子层沉积在所述通孔的内壁和所述衬底的表面上沉积所述金属粘附层；通过光刻刻蚀形成图形化的所述金属粘附层。
可选地，所述在所述通孔的内壁和所述衬底的表面上形成图形化的金属粘附层，包括：通过磁控溅射在所述通孔的内壁和所述衬底的表面上形成所述金属粘附层；通过光刻刻蚀形成图形化的所述金属粘附层。
可选地，所述方法还包括：在在所述通孔的内壁和所述衬底的表面上形成图形化的第一电极层之前，在所述通孔的内壁和所述衬底的表面上形成绝缘层，其中，所述绝缘层位于所述第一电极层的下方。
可选地，所述在所述通孔的内壁和所述衬底的表面上形成绝缘层，包括：通过热氧化在所述通孔的内壁和所述衬底的表面上形成所述绝缘层。
可选地，所述在所述通孔的内壁和所述衬底的表面上形成绝缘层，包括：通过等离子体化学气相沉积在所述通孔的内壁和所述衬底的表面上形成所述绝缘层。
可选地，所述在所述第一电极层上形成绝缘介质层，包括：通过沉积在所述第一电极层上形成绝缘介质层；以及所述在所述绝缘介质层上形成第二电极层，包括：通过溅射沉积在所述绝缘介质层上形成第二电极层。
通过采用上述技术方案，由于二维材料具有极大的比表面积，所以能够增大三维电容的极板面积，从而极大地提高三维电容的电容值，极大地提高了芯片上面积利用率。另外，由于是借助通孔的内壁形成三维电容， 而通孔的中心仍然可以被用作三维互连，也即，通孔的中心中仍然可以形成有用于三维互连的互连层，因此利用通孔的内壁形成三维电容不仅不影响通孔的互连功能，而且还极大地提高了通孔的功能密度。
本公开的其他特征和优点将在随后的具体实施方式部分予以详细说明。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是根据本公开一种实施例的三维电容的剖面示意图。
图2是根据本公开一种实施例的三维电容的又一剖面示意图。
图3是根据本公开一种实施例的三维电容制备方法的流程图。
图4a-图4i是根据本公开一种实施例的三维电容制备方法的剖面流程示意图。
图5a-图5f是根据本公开一种实施例的三维电容制备方法的又一剖面流程示意图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
图1是根据本公开一种实施例的三维电容的剖面示意图。如图1所示，该三维电容包括：衬底1；位于衬底1中的通孔2；位于通孔2的内壁和衬底1的表面上的图形化的第一电极层，该第一电极层包括由二维材料形成的 电极层3a；位于第一电极层上的绝缘介质层4；以及位于绝缘介质层4上的第二电极层5。采用图1所示的三维电容结构，可以形成半导体-绝缘层-金属类型的三维电容。
在一种实施例中，衬底1可以为高阻硅衬底1、玻璃衬底1、有机基板衬底1或者其他类型的衬底中的一者。也就是说，本公开不限制衬底1的具体类型。
在一种实施例中，二维材料指的是电子仅可在两个维度的纳米尺度上自由运动(平面运动)的材料，如纳米薄膜材料、超晶格材料、量子阱材料等。例如，二维材料可以为石墨烯。
在一种实施例中，绝缘介质层4可以由SiO 2/SiN形成，也可以由高介电常数的绝缘介质形成以提高绝缘介质层4的介电常数，例如由HfO 2、TiO 2或PbZr 0.52Ti 0.48O 3形成。
在一种实施例中，绝缘介质层4和第二电极层5可以与第一电极层同形，也即形状相同。
通过采用上述技术方案，由于二维材料具有极大的比表面积，所以能够增大三维电容的极板面积，从而极大地提高三维电容的电容值，极大地提高了芯片上面积利用率。另外，由于是借助通孔2的内壁形成三维电容，而通孔2的中心仍然可以被用作三维互连，也即，通孔2的中心中仍然可以形成有用于三维互连的互连层，因此利用通孔2的内壁形成三维电容不仅不影响通孔2的互连功能，而且还极大地提高了通孔2的功能密度。
图2是根据本公开一种实施例的三维电容的又一剖面示意图。如图2所示，第一电极层还可以包括金属粘附层3b，金属粘附层3b位于由二维材料形成的电极层3a的下方。金属粘附层3b可以由TiN、TiW/Cu或Cr/Ni形成。一方面，金属粘附层3b作为第一电极层的组成部分，起到电极连接或焊盘引出的作用；另一方面，金属粘附层3b可以作为三维电容的基底，起到粘 附由二维材料形成的电极层3a的作用，用于防止由二维材料形成的电极层3a因与衬底1粘附不好而脱落，从而保证了由二维材料形成的电极层3a的稳定性。
继续参考图2。三维电容还可以包括位于通孔2的内壁和衬底1的表面上的绝缘层6，绝缘层6位于第一电极层的下方。绝缘层6可以由SiO 2/SiN、SiO 2等形成。通过利用绝缘层6将第一电极层与衬底1隔离，能够形成金属-绝缘层-金属类型的三维电容，而且绝缘层6还能够防止衬底漏电。
图3是根据本公开一种实施例的三维电容制备方法的流程图。如图3所示，该方法包括以下步骤S11至S15。
在步骤S11中，在衬底中形成通孔；
在步骤S12中，在通孔的内壁和衬底的表面上形成图形化的第一电极层，第一电极层包括由二维材料形成的电极层；
在步骤S13中，在第一电极层上形成绝缘介质层；以及
在步骤S14中，在绝缘介质层上形成第二电极层。
通过采用上述技术方案，由于二维材料具有极大的比表面积，所以能够增大三维电容的极板面积，从而极大地提高三维电容的电容值，极大地提高了芯片上面积利用率。另外，由于是借助通孔的内壁形成三维电容，而通孔2的中心仍然可以被用作三维互连，也即，通孔的中心中仍然可以形成有用于三维互连的互连层，因此利用通孔的内壁形成三维电容不仅不影响通孔的互连功能，而且还极大地提高了通孔的功能密度。
图4a-图4i是根据本公开一种实施例的三维电容制备方法的剖面流程示意图。
首先在图4a中，在衬底1中形成通孔2。例如，可以通过深硅刻蚀方法在衬底1中形成通孔2，但是本领域技术人员应当理解的是，这里的深硅刻蚀方法仅是示例，任何其他能够形成通孔的方法也是可行的。衬底1可以为 高阻硅衬底1、玻璃衬底1、有机基板衬底1或者其他类型的衬底中的一者。通孔2的尺寸根据实际需要决定，例如，通孔2的直径可以为5微米～20微米、深度可以为40微米～100微米。
然后，在图4b中，在通孔2的内壁和衬底1的表面上形成绝缘层6。绝缘层6可以由SiO 2/SiN、SiO 2等形成。绝缘层6的厚度可以为200nm-500nm。绝缘层6可以采用热氧化的方法形成。但是本领域技术人员应当理解的是，本公开对形成绝缘层6的方法不做限制，任何能够形成绝缘层的方法都是可行的，例如等离子体化学气相沉积、物理沉积等方法也是可行的。
另外，该步骤是可选的。也即，如果要形成半导体-绝缘层-金属类型的三维电容，那么该步骤是可以省略的。如果要形成金属-绝缘层-金属类型的三维电容，那么该步骤是需要的，而且所形成的绝缘层6用于防止衬底漏电。
然后，在图4c中，在绝缘层6上形成图形化的金属粘附层3b，该金属粘附层3b属于第一电极层。金属粘附层3b可以由TiN、TiW/Cu或Cr/Ni等形成。一方面，金属粘附层3b作为第一电极层的组成部分，起到电极连接或焊盘引出的作用；另一方面，金属粘附层3b可以作为三维电容的基底，起到粘附由二维材料形成的电极层3a的作用，用于防止由二维材料形成的电极层3a因与衬底1粘附不好而脱落，从而保证了由二维材料形成的电极层3a的稳定性。
该步骤也是可以省略的，也即可以在绝缘层6上直接形成由二维材料形成的电极层。
可以采用多种实现方式来形成金属粘附层3b。一种实现方式是，首先，采用原子层沉积方法在绝缘层6上形成金属粘附层3b，然后，通过光刻及刻蚀方法对沉积形成的金属粘附层3b进行图形化，最终留下的图层包括：包括准备作为引出焊盘的开窗、三维电容的平面部分(也即三维电容的位于 衬底1的表面上的部分)和三维电容的位于通孔内壁上的部分。
然后，在图4d中，通过光刻的方式露出三维电容的平面部分和三维电容的位于通孔内壁的部分，以避免在后续步骤中在衬底绝缘层上沉积二维材料。图4d中，标号7表示光刻后剩余的光刻胶。
然后，在图4e中，采用混合了二维材料的铜电镀液，在三维电容的平面部分和三维电容的通孔内壁部分上电镀一层二维材料和铜，其中电镀的二维材料和铜在图4e中共同用标号3a-1表示。铜电镀液中二维材料的混合比例根据需求的三维电容的极板面积进行设置，为了获得极大的极板面积，通常会在铜电镀液中混合高比例的二维材料。另外，这里的铜电镀液仅是示例，任何能够实现金属电镀的电镀液类型都是可以的。
二维材料可以是例如纳米薄膜材料、超晶格材料、量子阱材料等。例如，二维材料可以为石墨烯。
然后，在图4f中，去掉光刻胶7。
然后，在图4g中，对二维材料和铜层3a-1进行湿法刻蚀，得到由二维材料形成的电极层3a，也即，在电极层3a中仅留下了二维材料。湿法刻蚀可以采用例如铜刻蚀液或者其他类型的金属刻蚀液来实现。铜刻蚀液可以为例如铜氨刻蚀液、FeCl3刻蚀液等。另外，由二维材料形成的电极层3a和金属粘附层3b共同构成了第一电极层。
然后，在图4h中，在由二维材料形成的电极层3a上形成绝缘介质层4。绝缘介质层4的形状与由二维材料形成的电极层3a同形，也即形状相同。
绝缘介质层4可以由SiO 2/SiN形成，也可以由高介电常数的绝缘介质形成以提高绝缘介质层4的介电常数，例如由HfO 2、TiO 2或PbZr 0.52Ti 0.48O 3形成。绝缘介质层4可以通过沉积(例如物理气相沉积、化学气相沉积、原子层沉积、磁控溅射沉积等)的方法形成。
然后，在图4i中，在绝缘介质层4上形成第二电极层5。例如，可以通 过溅射沉积、化学气相沉积、物理气相沉积、电镀等方法形成第二电极层5。
至此，三维电容就制备完成了。之后，就可以通过再布线工艺形成三维电容的电极引出焊盘，或者进行再布线实现三维电容与其他器件的集成。
图5a-图5f是根据本公开一种实施例的三维电容制备方法的又一剖面流程示意图。
首先在图5a中，在衬底1中形成通孔2。例如，可以通过深硅刻蚀方法在衬底1中形成通孔2，但是本领域技术人员应当理解的是，这里的深硅刻蚀方法仅是示例，任何其他能够形成通孔的方法也是可行的。衬底1可以为高阻硅衬底1、玻璃衬底1、有机基板衬底1或者其他类型的衬底中的一者。通孔2的尺寸根据实际需要决定，例如，通孔2的直径可以为5微米～20微米、深度可以为40微米～100微米。
然后，在图5b中，采用等离子体化学气相沉积方法在通孔2的内壁和衬底1的表面上形成绝缘层6，该种方法生长绝缘层6的目的是为了减小后续步骤中二维材料在绝缘层6上的沉积。绝缘层6可以由SiO 2/SiN、SiO 2等形成。绝缘层6的厚度可以为200nm-500nm。
另外，该步骤是可选的。也即，如果要形成半导体-绝缘层-金属类型的三维电容，那么该步骤是可以省略的。如果要形成金属-绝缘层-金属类型的三维电容，那么该步骤是需要的，而且所形成的绝缘层6用于防止衬底漏电。
然后，在图5c中，采用磁控溅射方法在绝缘层6上形成金属粘附层3b，该金属粘附层3b属于第一电极层。金属粘附层3b可以由TiN、TiW/Cu或Cr/Ni等形成。一方面，金属粘附层3b作为第一电极层的组成部分，起到电极连接或焊盘引出的作用；另一方面，金属粘附层3b可以作为三维电容的 基底，起到粘附由二维材料形成的电极层3a的作用，用于防止由二维材料形成的电极层3a因与衬底1粘附不好而脱落，从而保证了由二维材料形成的电极层3a的稳定性。
该步骤也是可以省略的，也即可以在绝缘层6上直接形成由二维材料形成的电极层。
然后，在图5d中，通过光刻刻蚀对金属粘附层3b进行图形化，再进行光刻露出三维电容的平面部分和三维电容的位于通孔内壁的部分
然后，在图5e中，用化学气相沉积方法有选择性地在金属粘附层3b上而不在绝缘层6上沉积一层二维材料，形成由二维材料构成的电极层3a及其图形化。这里，可以通过对化学气相沉积工艺的衬底温度、旋转、功率、沉积时间等参数进行优化后，在利用该方法进行沉积。
二维材料可以是例如纳米薄膜材料、超晶格材料、量子阱材料等。例如，二维材料可以为石墨烯。
然后，在图5f中，在由二维材料形成的电极层3a上形成绝缘介质层4，并在绝缘介质层4上形成第二电极层5。绝缘介质层4和第二电极层5的形状与由二维材料形成的电极层3a同形，也即形状相同。
绝缘介质层4可以由SiO 2/SiN形成，也可以由高介电常数的绝缘介质形成以提高绝缘介质层4的介电常数，例如由HfO 2、TiO 2或PbZr 0.52Ti 0.48O 3形成。绝缘介质层4可以通过沉积(例如物理气相沉积、化学气相沉积、原子层沉积、磁控溅射沉积等)的方法形成。
第二电极层5可以通过溅射沉积、化学气相沉积、物理气相沉积、电镀等方法形成。
至此，三维电容就制备完成了。之后，就可以通过再布线工艺形成三维电容的电极引出焊盘，或者进行再布线实现三维电容与其他器件的集成。
以上结合附图详细描述了本公开的优选实施方式，但是，本公开并不限于上述实施方式中的具体细节，在本公开的技术构思范围内，可以对本公开的技术方案进行多种简单变型，这些简单变型均属于本公开的保护范围。
另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合。为了避免不必要的重复，本公开对各种可能的组合方式不再另行说明。
此外，本公开的各种不同的实施方式之间也可以进行任意组合，只要其不违背本公开的思想，其同样应当视为本公开所公开的内容。

Claims (10)

  1. 一种三维电容制备方法，其特征在于，包括：
    在衬底中形成通孔；
    在所述通孔的内壁和所述衬底的表面上形成图形化的第一电极层，所述第一电极层包括由二维材料形成的电极层；
    在所述第一电极层上形成绝缘介质层；以及
    在所述绝缘介质层上形成第二电极层。
  2. 根据权利要求1所述的方法，其特征在于，所述在所述通孔的内壁和所述衬底的表面上形成图形化的第一电极层，包括：
    在所述通孔的内壁和所述衬底的表面上电镀混合了二维材料的铜电镀液，形成电镀层；
    对所述电镀层中的铜进行湿法刻蚀，得到图形化的所述第一电极层。
  3. 根据权利要求1所述的方法，其特征在于，所述在所述通孔的内壁和所述衬底的表面上形成图形化的第一电极层，包括：
    通过化学气相沉积，在所述通孔的内壁和所述衬底的表面上形成图形化的所述第一电极层。
  4. 根据权利要求1所述的方法，其特征在于，所述第一电极层还包括金属粘附层，所述方法还包括：
    在形成由所述二维材料形成的电极层之前，在所述通孔的内壁和所述衬底的表面上形成图形化的金属粘附层，其中，所述由所述二维材料形成的电极层位于所述金属粘附层的上方。
  5. 根据权利要求4所述的方法，其特征在于，所述在所述通孔的内壁和所述衬底的表面上形成图形化的金属粘附层，包括：
    通过原子层沉积在所述通孔的内壁和所述衬底的表面上沉积所述金属粘附层；
    通过光刻刻蚀形成图形化的所述金属粘附层。
  6. 根据权利要求4所述的方法，其特征在于，所述在所述通孔的内壁和所述衬底的表面上形成图形化的金属粘附层，包括：
    通过磁控溅射在所述通孔的内壁和所述衬底的表面上形成所述金属粘附层；
    通过光刻刻蚀形成图形化的所述金属粘附层。
  7. 根据权利要求1至6中任一权利要求所述的方法，其特征在于，所述方法还包括：
    在在所述通孔的内壁和所述衬底的表面上形成图形化的第一电极层之前，在所述通孔的内壁和所述衬底的表面上形成绝缘层，其中，所述绝缘层位于所述第一电极层的下方。
  8. 根据权利要求7所述的方法，其特征在于，所述在所述通孔的内壁和所述衬底的表面上形成绝缘层，包括：
    通过热氧化在所述通孔的内壁和所述衬底的表面上形成所述绝缘层。
  9. 根据权利要求7所述的方法，其特征在于，所述在所述通孔的内壁和所述衬底的表面上形成绝缘层，包括：
    通过等离子体化学气相沉积在所述通孔的内壁和所述衬底的表面上形 成所述绝缘层。
  10. 根据权利要求1所述的方法，其特征在于，所述在所述第一电极层上形成绝缘介质层，包括：通过沉积在所述第一电极层上形成绝缘介质层；以及
    所述在所述绝缘介质层上形成第二电极层，包括：通过溅射沉积在所述绝缘介质层上形成第二电极层。
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CN111864063A (zh) * 2020-07-09 2020-10-30 复旦大学 三维电容制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6144546A (en) * 1996-12-26 2000-11-07 Kabushiki Kaisha Toshiba Capacitor having electrodes with two-dimensional conductivity
CN103155098A (zh) * 2010-10-05 2013-06-12 国际商业机器公司 用于提高可靠性的具有浮置导电板的3d过孔电容器
CN206225212U (zh) * 2016-12-01 2017-06-06 中国建筑材料科学研究总院 石墨烯电容器
CN111864064A (zh) * 2020-07-09 2020-10-30 复旦大学 三维电容
CN111864063A (zh) * 2020-07-09 2020-10-30 复旦大学 三维电容制备方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102583354B (zh) * 2012-03-09 2015-05-20 合肥工业大学 一种电镀沉积法制备石墨烯膜的方法
CN102683318B (zh) * 2012-05-25 2014-07-02 无锡纳能科技有限公司 硅电容器内部多层电极连接结构及连接方法
US9105602B2 (en) * 2013-12-23 2015-08-11 Qualcomm Incorporated Embedded three-dimensional capacitor
CN104377191A (zh) * 2014-11-17 2015-02-25 上海集成电路研发中心有限公司 与集成电路工艺兼容的电容结构及其制备方法
CN104409442A (zh) * 2014-11-28 2015-03-11 中国科学院上海微系统与信息技术研究所 一种深槽结构电容及其制造方法
CN105714360B (zh) * 2014-12-04 2017-12-29 中国科学院宁波材料技术与工程研究所 碱性石墨烯‑镍电镀液、其制备方法及应用
CN105226046A (zh) * 2015-10-13 2016-01-06 格科微电子（上海）有限公司 金属层-绝缘层-金属层电容器及其制作方法
CN105390475A (zh) * 2015-10-20 2016-03-09 北京大学 一种衬底内部的电容集成结构及其制造方法
US10818544B2 (en) * 2017-09-27 2020-10-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method to enhance electrode adhesion stability
CN107858728B (zh) * 2017-12-20 2019-08-23 武汉新芯集成电路制造有限公司 Tsv电镀方法
CN110636693A (zh) * 2018-06-21 2019-12-31 四川聚创石墨烯科技有限公司 一种利用复杂脉冲电镀石墨烯-金属复合材料镀层的方法和一种pcb及电机
CN111199955A (zh) * 2018-11-16 2020-05-26 格科微电子（上海）有限公司 金属层-绝缘层-金属层电容器的制作方法、存储器单元
CN111199954A (zh) * 2018-11-16 2020-05-26 格科微电子（上海）有限公司 金属层-绝缘层-金属层电容器的制作方法、存储器单元
CN110752207B (zh) * 2019-09-10 2021-04-30 福建省福联集成电路有限公司 一种背面电容结构及制作方法
CN111029459B (zh) * 2019-11-29 2022-06-14 华中科技大学 一种界面型原子忆阻器及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6144546A (en) * 1996-12-26 2000-11-07 Kabushiki Kaisha Toshiba Capacitor having electrodes with two-dimensional conductivity
CN103155098A (zh) * 2010-10-05 2013-06-12 国际商业机器公司 用于提高可靠性的具有浮置导电板的3d过孔电容器
CN206225212U (zh) * 2016-12-01 2017-06-06 中国建筑材料科学研究总院 石墨烯电容器
CN111864064A (zh) * 2020-07-09 2020-10-30 复旦大学 三维电容
CN111864063A (zh) * 2020-07-09 2020-10-30 复旦大学 三维电容制备方法

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