WO2024040517A1 - 滤波器及其制备方法、电子设备 - Google Patents

滤波器及其制备方法、电子设备 Download PDF

Info

Publication number
WO2024040517A1
WO2024040517A1 PCT/CN2022/114811 CN2022114811W WO2024040517A1 WO 2024040517 A1 WO2024040517 A1 WO 2024040517A1 CN 2022114811 W CN2022114811 W CN 2022114811W WO 2024040517 A1 WO2024040517 A1 WO 2024040517A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
connection
layer
electrode
conductive
Prior art date
Application number
PCT/CN2022/114811
Other languages
English (en)
French (fr)
Inventor
刘英伟
赵仲兰
曹占锋
王珂
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/114811 priority Critical patent/WO2024040517A1/zh
Publication of WO2024040517A1 publication Critical patent/WO2024040517A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F5/00—Coils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators

Definitions

  • the present disclosure relates to but is not limited to the field of semiconductor technology, and in particular, to a filter, a manufacturing method thereof, and electronic equipment.
  • IPD Integrated Passive Device
  • RF radio frequency
  • the present disclosure provides a filter, including a first substrate, a second substrate arranged oppositely, and a connection substrate arranged between the first substrate and the second substrate.
  • the first substrate is provided with at least A first substrate electrode, at least one second substrate electrode provided on the second substrate, the connection substrate at least includes a connection substrate and at least one conductive pillar penetrating the connection substrate in the thickness direction, the conductive pillar
  • a first bump structure is provided at one end close to the first substrate, and a second bump structure is provided at one end of the conductive pillar close to the second substrate.
  • the first bump structure is in contact with the first substrate electrode.
  • the second bump structure and the second substrate electrode are connected by bonding.
  • connection substrate includes a first side surface close to the first substrate and a second side surface close to the second substrate, and the first bump structure is disposed on the connection substrate. on the first side surface of the bottom and connected to one end of the conductive pillar close to the first substrate; the second bump structure is disposed on the second side surface of the connection substrate and connected to the conductive The pillar is connected at one end close to the second substrate.
  • an orthographic projection of the first bump structure on the connection substrate includes an orthographic projection of the conductive pillar on the connection substrate, and the second bump structure is on the connection substrate.
  • the orthographic projection on the connection substrate includes the orthographic projection of the conductive pillar on the connection substrate.
  • the first bump structure includes a first connection layer disposed on a first side surface of the connection substrate and a first connection layer disposed on a side away from the connection substrate. a first bump layer, the first connection layer is connected to one end of the conductive pillar close to the first substrate, and the first bump layer is connected to the first substrate electrode by bonding;
  • the second bump structure includes a second connection layer disposed on the second side surface of the connection substrate and a second bump layer disposed on a side of the second connection layer away from the connection substrate, wherein The second connection layer is connected to one end of the conductive pillar close to the second substrate, and the second bump layer is connected to the second substrate electrode through bonding.
  • the materials of the first connection layer and the second connection layer include any one of the following: a composite layer of titanium and copper, a composite layer of molybdenum-titanium-nickel alloy and copper, molybdenum-titanium-nickel alloy, copper-nickel Composite layer of alloy and copper.
  • the material of the first bump layer and the second bump layer includes any one of the following: tin, indium tin alloy.
  • the conductive pillars include at least a first conductive pillar and a second conductive pillar
  • the first substrate electrode includes at least a first connection electrode and a second connection electrode
  • the second substrate electrode includes at least a third connection electrode.
  • Three connection electrodes the first connection electrode is connected to the first conductive column
  • the second connection electrode is connected to the second conductive column
  • the third connection electrode is connected to the first conductive column and the third conductive column respectively.
  • Two conductive pillars are connected, and the first conductive pillar, the second conductive pillar, the first connection electrode, the second connection electrode and the third connection electrode form a filter inductor of a three-dimensional spiral inductance structure.
  • the first substrate is further provided with a filter capacitor, and the filter capacitor is connected to the filter inductor.
  • the first substrate at least includes a first substrate, a first conductive layer disposed on a side of the first substrate close to the connection substrate, and a first conductive layer disposed on a side of the first conductive layer close to the connection substrate.
  • the second conductive layer on the side of the connection substrate, the third conductive layer provided on the side of the second conductive layer close to the connection substrate, the first connection electrode and the second connection electrode are provided on the third conductive layer. layer.
  • the filter capacitor includes a first plate and a second plate, and the orthographic projection of the first plate on the first substrate is the same as the orthographic projection of the second plate on the first substrate. Orthographic projections on a substrate at least partially overlap, the first electrode plate is disposed in the second conductive layer, and the second electrode plate is disposed in the third conductive layer.
  • the first conductive layer includes at least a first pad electrode, a second pad electrode, and a fourth connection electrode, and the first connection electrode is connected to the first pad electrode through a via hole.
  • the second connection electrode and the first electrode plate are respectively connected to the fourth connection electrode through a via hole, and the second electrode plate is connected to the second pad electrode through a via hole.
  • the first substrate further includes a pad conductive layer and a pad protection layer.
  • the pad protection layer is provided on a side of the first substrate away from the connection substrate.
  • a pad conductive layer is provided on a side of the pad protective layer away from the connection substrate.
  • the pad conductive layer at least includes a first pad and a second pad, and the first pad electrode is connected to the pad through a via hole. The first pad is connected, and the second pad electrode is connected to the second pad through a via hole.
  • a surface of the pad conductive layer on a side away from the connection substrate is flush with a surface of the first substrate on a side away from the connection substrate.
  • a surface of the pad protection layer on a side away from the connection substrate is flush with a surface of the first substrate on a side away from the connection substrate.
  • the conductive pillars include n conductive pillars, the first substrate electrode includes one first connection electrode and n/2 second connection electrodes, and the second substrate electrode includes n/2
  • the third connection electrode the first connection electrode 41 is connected to the first conductive column among the n conductive columns, the (n/2) second connection electrode is connected to the nth conductive column among the n conductive columns, and the others
  • the second connection electrodes are respectively connected to the i+1-th conductive column and the i+2-th conductive column among the n conductive columns, and the plurality of third connection electrodes are respectively connected to the i-th conductive column and the i+1-th conductive column among the n conductive columns.
  • Conductive pillars, n conductive pillars, first connecting electrodes, n/2 second connecting electrodes and n/2 third connecting electrodes constitute the first filter inductor of the three-dimensional spiral inductor structure, n is an even number greater than or equal to 2, i is an odd number greater than or equal to 1 and less than or equal to n-2.
  • the first substrate is further provided with a filter capacitor, a first bonding pad and a second bonding pad, the first connection electrode is connected to the first bonding pad, and the (n/2)th The second connection electrode is connected to the first plate of the filter capacitor, and the second plate of the filter capacitor is connected to the second pad.
  • the second substrate at least includes a second substrate and a fourth conductive layer disposed on a side of the second substrate close to the connection substrate, and the third connection electrode is disposed on the in the fourth conductive layer.
  • the present disclosure also provides an electronic device, including the aforementioned filter.
  • the present disclosure also provides a method for preparing a filter, including:
  • a first substrate, a second substrate and a connection substrate are respectively prepared. At least one first substrate electrode is provided on the first substrate. At least one second substrate electrode is provided on the second substrate.
  • the connection substrate at least includes a connection The substrate and at least one conductive pillar penetrating the connection substrate, one end of the conductive pillar close to the first substrate is connected to a first bump structure, and one end of the conductive pillar close to the second substrate is connected to a third Two bump structures;
  • the first substrate and the second substrate are arranged oppositely, and the connection substrate is arranged between the first substrate and the second substrate, and the first bump structure and the first substrate are connected by bonding. Electrode connection, the second bump structure and the second substrate electrode are connected.
  • preparing the connection substrate includes:
  • connection substrate forming a plurality of through holes on the connection substrate, the material of the connection substrate including glass;
  • a plurality of first bump structures are formed on the first side surface of the connection substrate, and a plurality of second bump structures are formed on the second side surface of the connection substrate;
  • the first bump structure includes a a first connection layer on the first side surface of the connection substrate and a first bump layer disposed on a side of the first connection layer away from the connection substrate, a plurality of first connection layers and a plurality of conductive The ends of the pillars located on the first side surface are connected correspondingly;
  • the second bump structure includes a second connection layer provided on the second side surface of the connection substrate and a second connection layer provided away from the second connection layer.
  • the second bump layer on one side of the connection substrate is connected to a plurality of second connection layers corresponding to the ends of the plurality of conductive pillars located on the second side surface.
  • Figure 1 is a schematic structural diagram of a filter according to an exemplary embodiment of the present disclosure
  • Figure 2 is a schematic diagram of the filter according to the embodiment of the present disclosure after forming a pad conductive layer pattern
  • Figure 3 is a schematic diagram of the filter according to the embodiment of the present disclosure after forming a pad protective layer pattern
  • Figure 4 is a schematic diagram of the first substrate pattern formed on the filter according to the embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of the filter according to the embodiment of the present disclosure after forming a first conductive layer pattern
  • Figure 6 is a schematic diagram of the second insulating layer pattern formed on the filter according to the embodiment of the present disclosure.
  • Figure 7 is a schematic diagram of the second conductive layer pattern formed on the filter according to the embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of the third insulating layer pattern formed on the filter according to the embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of the third conductive layer pattern formed on the filter according to the embodiment of the present disclosure.
  • Figure 10 is a schematic diagram of the fourth insulating layer pattern formed on the filter according to the embodiment of the present disclosure.
  • Figure 11 is a schematic diagram of the second substrate pattern formed on the filter according to the embodiment of the present disclosure.
  • Figure 12 is a schematic diagram of the fourth conductive layer pattern formed on the filter according to the embodiment of the present disclosure.
  • Figure 13 is a schematic diagram of the sixth insulating layer pattern formed on the filter according to the embodiment of the present disclosure.
  • Figure 14 is a schematic diagram after preparing the connection substrate pattern for the filter according to the embodiment of the present disclosure.
  • Figure 15 is a schematic diagram after preparing the conductive pillar pattern for the filter according to the embodiment of the present disclosure.
  • Figure 16 is a schematic diagram of the first bump structure layer pattern formed on the filter according to the embodiment of the present disclosure.
  • Figure 17 is a schematic diagram of the second bump structure layer pattern formed on the filter according to the embodiment of the present disclosure.
  • FIGS. 18 and 19 are schematic diagrams of a filter bonding process according to an embodiment of the present disclosure.
  • 10 the first substrate
  • 10A the first carrier board
  • 10B the first sacrificial layer
  • 80 through hole
  • 90 pad protective layer
  • 100 first substrate
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • TGV through glass via
  • Si silicon
  • GaAs gallium arsenide
  • Through glass hole TGV technology refers to making a through hole on a glass substrate and filling it with metal material. Through the metal material in the through hole, the functional structure located on the upper surface of the glass substrate and the functional structure located on the lower surface of the glass substrate are connected. Electrical connection. Research shows that when making corresponding functional structures on the upper and lower surfaces of a glass substrate, processes such as high-temperature annealing or high-temperature film deposition will occur. Due to the difference between the thermal expansion coefficient of the metal material filling the through hole and the thermal expansion coefficient of the glass substrate, It is easy for the metal material to protrude through the through hole, causing disconnection between the metal material and the functional structure, reducing product yield.
  • the present disclosure provides a passive filter, including a first substrate, a second substrate arranged oppositely, and a connection substrate arranged between the first substrate and the second substrate, and at least one The first substrate electrode is provided with at least one second substrate electrode on the second substrate.
  • the connection substrate at least includes a connection substrate and at least one conductive pillar penetrating the connection substrate in the thickness direction.
  • the conductive pillar is close to One end of the first substrate is provided with a first bump structure, and one end of the conductive pillar close to the second substrate is provided with a second bump structure.
  • the first bump structure is connected to the first substrate electrode,
  • the second bump structure and the second substrate electrode are connected by bonding.
  • connection substrate includes a first side surface close to the first substrate and a second side surface close to the second substrate, and the first bump structure is disposed on the connection substrate. on the first side surface of the bottom and connected to one end of the conductive pillar close to the first substrate; the second bump structure is disposed on the second side surface of the connection substrate and connected to the conductive The pillar is connected at one end close to the second substrate.
  • the first bump structure includes a first connection layer disposed on a first side surface of the connection substrate and a first connection layer disposed on a side away from the connection substrate. a first bump layer, the first connection layer is connected to one end of the conductive pillar close to the first substrate, and the first bump layer is connected to the first substrate electrode by bonding;
  • the second bump structure includes a second connection layer disposed on the second side surface of the connection substrate and a second bump layer disposed on a side of the second connection layer away from the connection substrate, wherein The second connection layer is connected to one end of the conductive pillar close to the second substrate, and the second bump layer is connected to the second substrate electrode through bonding.
  • the conductive pillars include at least a first conductive pillar and a second conductive pillar
  • the first substrate electrode includes at least a first connection electrode and a second connection electrode
  • the second substrate electrode includes at least a third connection electrode.
  • Three connection electrodes the first connection electrode is connected to the first conductive column
  • the second connection electrode is connected to the second conductive column
  • the third connection electrode is connected to the first conductive column and the third conductive column respectively.
  • Two conductive pillars are connected, and the first conductive pillar, the second conductive pillar, the first connection electrode, the second connection electrode and the third connection electrode form a filter inductor of a three-dimensional spiral inductance structure.
  • the first substrate is further provided with a filter capacitor, and the filter capacitor is connected to the filter inductor.
  • Figure 1 is a schematic structural diagram of a filter according to an exemplary embodiment of the present disclosure.
  • the main structure of the filter according to the exemplary embodiment of the present disclosure may include a first substrate 100 , a second substrate 200 arranged oppositely, and a connection substrate 300 arranged between the first substrate 100 and the second substrate 200 .
  • the first substrate 100 and the connection substrate 300 are connected by bonding
  • the second substrate 200 and the connection substrate 300 are connected by bonding, forming a passive filter including a filter inductor and a filter capacitor.
  • connection substrate 300 may include at least the connection substrate 30, first conductive pillars 71 and second conductive pillars 72 penetrating the connection substrate 30 in the thickness direction, and the first substrate 100 may include at least a first substrate. 10 and the first connection electrode 41 and the second connection electrode 42 provided on the side of the first substrate 10 close to the second substrate 200.
  • the second substrate 200 may at least include the second substrate 20 and the first connection electrode 41 and the second connection electrode 42 provided close to the second substrate 20.
  • the first conductive pillar 71 and the second conductive pillar 72 are respectively provided with a first bump structure 51 at one end close to the first substrate 100.
  • the first conductive pillar 71 and the second conductive pillar 72 are respectively provided with a first bump structure 51 at one end close to the second substrate 200.
  • the two bump structures 52 connect the two first bump structures 51 of the substrate 300 to the first connection electrode 41 and the second connection electrode 42 of the first substrate 100 respectively through bonding.
  • the two first bump structures 51 of the connection substrate 300 The bump structures 51 are respectively connected to the third connection electrodes 43 of the second substrate 200 by bonding, forming an electrical connection structure of the first substrate 100 , the connection substrate 300 and the second substrate 200 .
  • first connection electrode 41 and the second connection electrode 42 may serve as the first substrate electrode of the present disclosure
  • third connection electrode 43 may serve as the second substrate electrode of the present disclosure
  • connection substrate 30 may include a first side surface close to the first substrate 100 and a second side surface close to the second substrate 200
  • two first bump structures 51 may be disposed on the connection substrate 30 on the first side surface, and are respectively connected to one end of the first conductive pillar 71 and the second conductive pillar 72 close to the first substrate 100
  • two second bump structures 52 may be disposed on the second side surface of the connection substrate 30 on the first conductive pillar 71 and the second conductive pillar 72 respectively, and are connected to one end of the first conductive pillar 71 and the second conductive pillar 72 close to the second substrate 200 .
  • the orthographic projection of the first bump structure 51 on the connection substrate may include the orthographic projection of the first conductive pillar 71 and the second conductive pillar 72 on the connection substrate, and the second bump structure 52 is on the connection substrate.
  • the orthographic projection on the connection substrate may include the orthographic projection of the first conductive pillar 71 and the second conductive pillar 72 on the connection substrate.
  • the first bump structure 51 may include a stacked first connection layer 51-1 and a first bump layer 51-2.
  • the first connection layer 51 - 1 may be disposed on the first side surface of the connection substrate 30 and connected to one end of the first conductive pillar 71 and the second conductive pillar 72 close to the first substrate 100 respectively.
  • the first bump layer 51-2 may be disposed on a side of the first connection layer 51-1 away from the connection substrate 30, and is connected to the first connection electrode 41 and the second connection electrode 42 by bonding respectively.
  • the second bump structure 52 may include a stacked second connection layer 52-1 and a second bump layer 52-2.
  • the second connection layer 52 - 1 may be disposed on the second side surface of the connection substrate 30 , and is respectively connected to one end of the first conductive pillar 71 and the second conductive pillar 72 close to the second substrate 200 .
  • the second bump layer 52-2 can be disposed on a side of the second connection layer 52-1 close to the second substrate 200, and is respectively connected to the third connection electrode 43 through bonding.
  • the materials of the first connection layer 51-1 and the second connection layer 52-1 may include any one of the following: a composite layer of titanium and copper, a composite layer of molybdenum-titanium-nickel alloy and copper, molybdenum-titanium Composite layer of nickel alloy, copper-nickel alloy and copper.
  • the materials of the first bump layer 51-2 and the second bump layer 52-2 include any one of the following: tin, indium tin alloy.
  • the first substrate 100 may include a filter inductor with a three-dimensional spiral inductor structure and a filter capacitor with a parallel plate capacitor structure, and the filter inductor is connected to the filter capacitor.
  • the first connection electrode 41 is connected to the first conductive pillar 71 through the first bump structure 51
  • the second connection electrode 42 is connected to the second conductive pillar 72 through the first bump structure 51
  • the third connection The electrode 43 is connected to the first conductive pillar 71 and the second conductive pillar 72 respectively through the second bump structure 52
  • the first connection electrode 41, the first conductive pillar 71, the third connection electrode 43, and the second conductive pillar 72 are connected in sequence.
  • the second connection electrode 42 form a filter inductor with a three-dimensional spiral inductor structure.
  • the filter capacitor may include a first plate 61 and a second plate 62, and the orthographic projection of the first plate 61 on the first substrate 10 and the second plate 62 on the first substrate orthographic projections at least partially overlap.
  • the first substrate 100 may include at least: a first substrate 10, a first insulating layer 11 disposed on a side of the first substrate 10 close to the connection substrate 300, and a first insulating layer 11 disposed on a side close to the connection substrate 300.
  • the first conductive layer on the side of the substrate 300 is provided on the second insulating layer 12 on the side of the first conductive layer close to the connection substrate 300.
  • the second conductive layer is provided on the side of the second insulating layer 12 close to the connection substrate 300.
  • the second conductive layer is close to the third insulating layer 13 on the side of the connection substrate 300 , the third conductive layer is disposed on the side of the third insulating layer 13 close to the connection substrate 300 , and the third conductive layer is disposed on the side of the third conductive layer close to the connection substrate 300 Fourth insulation layer 14.
  • the first conductive layer may include at least the first pad electrode 31, the second pad electrode 32, and the fourth connection electrode 44
  • the second conductive layer may include at least the first plate 61
  • the third conductive layer may include at least the first pad electrode 31, the second pad electrode 32, and the fourth connection electrode 44.
  • the layer may at least include a first connection electrode 41, a second connection electrode 42 and a second plate 62.
  • the second connection electrode 42 may be connected to the fourth connection electrode 44 through a via hole
  • the first plate 61 may be connected to the fourth connection electrode 44 through a via hole.
  • the four connection electrodes 44 are connected, so that the filter inductor and the filter capacitor are connected to each other through the fourth connection electrode 44 .
  • At least two first bonding via holes are provided on the fourth insulating layer 14 , and the at least two first bonding via holes expose the first connection electrode 41 and the second connection electrode 42 respectively, and at least The two first bump structures 51 extend into the corresponding first bonding via holes and are bonded to the first connection electrode 41 and the second connection electrode 42 respectively.
  • the second substrate 200 may include at least: a second substrate 20 , a fifth insulating layer 15 disposed on a side of the second substrate 20 close to the connection substrate 300 , and a fifth insulating layer 15 disposed on a side close to the connection substrate 300 .
  • the fourth conductive layer may include at least the third connection electrode 43 .
  • the sixth insulating layer 16 is provided with at least two second bonding vias, the at least two second bonding vias respectively expose the third connection electrodes 43, and the at least two second bump structures 52 extend into corresponding The second bonding via holes are respectively bonded and connected to the third connection electrodes 43 .
  • the first substrate 100 may further include a pad conductive layer and a pad protection layer 90 .
  • the pad protection layer 90 may be disposed on a side of the first substrate 10 away from the connection substrate 300 .
  • the pad conductive layer It may be provided on the side of the pad protection layer 90 away from the connection substrate 300 .
  • a surface of the pad protection layer 90 on a side away from the connection substrate 300 and a surface of the first substrate 10 on a side away from the connection substrate 300 may be substantially flush.
  • a surface of the pad conductive layer on a side away from the connection substrate 300 and a surface of the first substrate 10 on a side away from the connection substrate 300 may be substantially flush.
  • the pad conductive layer may include at least one first pad 21 and at least one second pad 22, and the first substrate 10 and the first insulating layer 11 are provided with first via holes and second
  • the first pad electrode 31 can be connected to the first pad 21 through the first via hole
  • the second pad electrode 32 can be connected to the second pad 22 through the second via hole.
  • the first connection electrode 41 may be connected to the first pad electrode 31 through a via hole
  • the second plate 62 may be connected to the second pad electrode 32 through a via hole, thereby realizing the first pad 21 is connected to the filter inductor, and the second pad 22 is connected to the filter capacitor.
  • the number of conductive pillars and connection electrodes included in the filter inductor of the three-dimensional spiral inductor structure can be set according to parameters such as inductance (such as the number of coil turns).
  • connection substrate 300 may be provided with n through holes penetrating the connection substrate 30 in the thickness direction, and the n conductive pillars may be respectively disposed in the n through holes.
  • the n conductive pillars may be provided along the device. Orientation and regular arrangement.
  • the first substrate 100 may be provided with one first connection electrode 41 and n/2 second connection electrodes 42.
  • the second substrate 200 may be provided with n/2 third connection electrodes 43.
  • the first connection electrode 41 may be connected to The first conductive column and the (n/2) second connection electrode 42 among the n conductive columns can be connected to the nth conductive column among the n conductive columns, and the other plurality of second connection electrodes 42 can be connected to n respectively.
  • the i+1-th conductive pillar and the i+2-th conductive pillar among the conductive pillars, the plurality of third connection electrodes 43 can respectively connect the i-th conductive pillar and the i+1-th conductive pillar among the n conductive pillars, and the n conductive pillars , the first connection electrode 41, n/2 second connection electrodes 42 and n/2 third connection electrodes 43 constitute the first filter inductor of the three-dimensional spiral inductor structure, n is an even number greater than or equal to 2, i is greater than or equal to An odd number equal to 1, less than or equal to n-2.
  • the first connection electrode 41 may be connected to the first pad of the resonator, the (n/2)th second connection electrode 42 may be connected to the first plate of the filter capacitor, and the (n/2)th second connection electrode 42 may be connected to the first plate of the filter capacitor.
  • the diode plate can be connected to the second pad of the resonator.
  • the following is an exemplary description through the preparation process of the filter.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the filter.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the filter according to the exemplary embodiment of the present disclosure may include at least four parts, including preparation of the first substrate, preparation of the second substrate, preparation of the connection substrate, and bonding processing. Among them, there is no order requirement for the preparation of the connection substrate, the preparation of the first substrate and the preparation of the second substrate, and they can be carried out at the same time, while the bonding process needs to be carried out after the preparation of the connection substrate, the first substrate and the second substrate is completed.
  • the four parts of the preparation process are described below.
  • the preparation process of the first substrate may include the following operations.
  • Form the pad conductive layer pattern may include: providing a first carrier board 10A, first forming a first sacrificial layer (De-bonding Layer, DBL for short) 10B on the first carrier board 10A, and then forming a first sacrificial layer (De-bonding Layer, DBL for short) 10B on the first carrier board 10A.
  • a pad conductive film is deposited on a sacrificial layer 10B, and a patterning process is used to pattern the pad conductive film to form a pad conductive layer pattern on the first sacrificial layer 10B, as shown in FIG. 2 .
  • the pad conductive layer may include at least a first pad 21 configured as an input terminal of the filter and a second pad 22 configured as the filter.
  • the output terminal of the filter, or the first pad 21 is configured as an output terminal of the filter, and the second pad 22 is configured as an input terminal of the filter.
  • the material of the first carrier plate may be glass
  • the material of the first sacrificial layer may be an organic polymer material, which may be formed by coating a viscous liquid and then curing to form a film, and the first sacrificial layer is configured In order to separate the first substrate from the first carrier in the subsequent laser lift-off (LLO) process.
  • LLO laser lift-off
  • a lift-off process may also be used to form the pad conductive layer pattern.
  • a photoresist is first coated on the first carrier plate, exposed and developed to form a photoresist pattern, and then a pad conductive film is deposited, and then the photoresist pattern and the pad conductive film on the photoresist pattern are peeled off.
  • a pad conductive layer pattern including a first pad 21 and a second pad 22 is formed on the first carrier board.
  • forming the pad protection layer pattern may include: depositing a pad protection film on the first carrier 10A on which the foregoing pattern is formed, patterning the pad protection film using a patterning process, and forming a cover welding layer.
  • the pad protective layer 90 pattern of the pad conductive layer is as shown in Figure 3.
  • the pad protection layer 90 may be provided only in the area where the first pad 21 and the second pad 22 are located, and the pad protection layer 90 covering the first pad 21 and the second pad 22 is provided with The first transition hole and the second transition hole.
  • the pad protection film in the first transition hole is removed, exposing the surface of the first pad 21.
  • the pad protection film in the second transition hole is removed, exposing the second surface of pad 22.
  • forming the first substrate pattern may include: first coating a first substrate film on the first carrier 10A where the foregoing pattern is formed, and then curing the film to form a first insulating film, and then using patterning. The process performs patterning on the first insulating film and the first substrate film to form the first substrate 10 covering the pad conductive layer and the pad protective layer, and disposes the first substrate 10 away from the first carrier plate 10A. side of the first insulating layer 11, as shown in Figure 4.
  • the first substrate 10 covers not only the pad conductive layer and the pad protective layer 90 but also the first sacrificial layer 10B other than the pad protective layer 90 .
  • the first substrate 10 and the first insulating layer 11 are provided with a first via K1.
  • the orthographic projection of the first via K1 on the first substrate can be located at the area where the first bonding pad 21 is located.
  • the first insulating film and the first substrate film in the first via hole K1 are removed, exposing the surface of the first pad 21, and the first via hole K1 is configured In order to enable the first pad electrode formed later to be connected to the first pad 21 through the via hole.
  • the first substrate 10 and the first insulating layer 11 are provided with a second via hole K2.
  • the orthographic projection of the second via hole K2 on the first substrate can be located at the area where the second bonding pad 22 is located.
  • the first insulating film and the first substrate film in the second via hole K2 are removed, exposing the surface of the second pad 22, and the second via hole K2 is configured In order to allow the second pad electrode formed later to be connected to the second pad 22 through the via hole.
  • the orthographic projection of the first via hole K1 on the first substrate 10 may be located within the range of the orthographic projection of the first transition hole on the first substrate 10
  • the second via hole K2 is located on the first substrate 10
  • the orthographic projection on one substrate 10 may be located within the range of the orthographic projection of the second transition hole on the first substrate 10 .
  • the first substrate may be made of polyimide (PI), polyethylene terephthalate (PET), or other materials.
  • PI polyimide
  • PET polyethylene terephthalate
  • forming the first conductive layer pattern may include: on the first carrier plate 10A where the foregoing pattern is formed, using a seed layer deposition method and an additive method, forming the first insulating layer 11 away from the first carrier plate 10A.
  • a first conductive layer pattern is formed on one side, as shown in Figure 5.
  • the first conductive layer pattern may include at least spaced apart first pad electrodes 31 , second pad electrodes 32 , and fourth connection electrodes 44 .
  • the first pad electrode 31 may be connected to the first pad 21 through the first via hole K1
  • the second pad electrode 32 may be connected to the second pad 22 through the second via hole K2.
  • a pad electrode 31 is configured to be connected to a first connection electrode formed subsequently
  • a second pad electrode 32 is configured to be connected to a second electrode plate formed subsequently.
  • the fourth connection electrode 44 may be disposed between the first pad electrode 31 and the second pad electrode 32 , and the fourth connection electrode 44 is configured to communicate with the subsequently formed first connection electrode and the first pad electrode 32 .
  • the plate connection realizes the connection between the filter inductor and the filter capacitor.
  • the seed layer deposition method may adopt electrochemical deposition (ECD) or other methods
  • the additive method refers to a method of selectively depositing a conductive film to form a conductive pattern.
  • a patterning process may also be used to form the first conductive layer pattern, or a lift-off process may be used.
  • forming the second insulating layer pattern may include: depositing a second insulating film on the first carrier 10A on which the foregoing pattern is formed, patterning the second insulating film using a patterning process, and forming a pattern covering the second insulating layer.
  • a conductive layer pattern and a second insulating layer 12 pattern are shown in FIG. 6 .
  • a third via K3 is formed on the second insulating layer 12 , and the orthographic projection of the third via K3 on the first substrate may be located at the orthogonal projection of the fourth connection electrode 44 on the first substrate.
  • the second insulating film in the third via hole K3 is removed, exposing the surface of the fourth connection electrode 44.
  • the third via hole K3 is configured to allow the subsequently formed first plate to pass through the via hole. Connected to the fourth connection electrode 44 .
  • forming the second conductive layer pattern may include: depositing a second conductive film on the first carrier 10A on which the foregoing pattern is formed, patterning the second conductive film using a patterning process, and performing a patterning process on the second conductive film.
  • a second conductive layer pattern is formed on the insulating layer 12, as shown in FIG. 7 .
  • the second conductive layer pattern may include at least a first plate 61 , which is connected to the fourth connection electrode 44 through a third via K3 .
  • the first plate 61 may serve as a filter capacitor.
  • a lift-off process may also be used to form the second conductive layer pattern.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the first carrier 10A on which the foregoing pattern is formed, patterning the third insulating film using a patterning process, and forming a pattern covering the third insulating layer.
  • the second conductive layer pattern and the third insulating layer 13 pattern are as shown in FIG. 8 .
  • the fourth via hole K4 , the fifth via hole K5 and the sixth via hole K6 are formed on the third insulating layer 13 .
  • the orthographic projection of the fourth via hole K4 on the first substrate may be located within the range of the orthographic projection of the fourth connection electrode 44 on the first substrate, and the orthogonal projection of the fourth via hole K4 on the first substrate.
  • the three insulating films and the second insulating film are removed to expose the surface of the fourth connection electrode 44 , and the fourth via hole K4 is configured to allow the subsequently formed second connection electrode to be connected to the fourth connection electrode 44 through the via hole.
  • the orthographic projection of the fifth via hole K5 on the first substrate may be located within the range of the orthographic projection of the first pad electrode 3 on the first substrate.
  • the third insulating film and the second insulating film are removed, exposing the surface of the first pad electrode 31 , and the fifth via hole K5 is configured to allow the subsequently formed first connection electrode to pass through the via hole and the first pad electrode 31 connect.
  • the orthographic projection of the sixth via hole K6 on the first substrate may be located within the range of the orthographic projection of the second pad electrode 32 on the first substrate.
  • the third insulating film and the second insulating film are removed, exposing the surface of the second pad electrode 32 , and the sixth via hole K6 is configured to allow the subsequently formed second plate to pass through the via hole and the second pad electrode 32 connect.
  • forming the third conductive layer pattern may include: depositing a third conductive film on the first carrier 10A on which the foregoing pattern is formed, using a patterning process to pattern the third conductive film, and in the third A third conductive layer pattern is formed on the insulating layer 13, as shown in Figure 9.
  • the third conductive layer pattern may include at least the first connection electrode 41 , the second connection electrode 42 and the second electrode plate 62 .
  • the orthographic projection of the first connection electrode 41 on the first substrate 10 at least partially overlaps the orthographic projection of the first pad electrode 31 on the first substrate 10 , and the first connection electrode 41 passes through
  • the fifth via hole K5 is connected to the first pad electrode 31, and the first connection electrode 41 is configured to be bonded and connected to the first bump structure in the connection substrate.
  • the orthographic projection of the second connection electrode 42 on the first substrate 10 at least partially overlaps the orthographic projection of the fourth connection electrode 44 on the first substrate 10 , and the second connection electrode 42 passes through the first substrate 10 .
  • the four via holes K4 are connected to the fourth connection electrode 44, and the second connection electrode 42 is configured to be bonded and connected to the first bump structure in the connection substrate.
  • the orthographic projection of the second plate 62 on the first substrate 10 at least partially overlaps the orthographic projection of the first plate 61 and the second pad electrode 32 on the first substrate 10,
  • the second plate 62 is connected to the second pad electrode 32 through the sixth via K6.
  • the second plate 62 can be used as another plate (upper plate) of the filter capacitor.
  • the first plate 61 and the second plate 62 constitutes a filter capacitor with a planar film capacitor structure.
  • a lift-off process may also be used to form the third conductive layer pattern.
  • chemical mechanical polishing may be used to polish the surfaces of the first connection electrode 41 and the second connection electrode 42 on the side away from the first substrate, so that the first connection electrode 41 and the second connection electrode 42 are polished.
  • the surfaces of the first connection electrode 41 and the second connection electrode 42 are flush, and the surface roughness of the surfaces of the first connection electrode 41 and the second connection electrode 42 away from the first substrate may be less than or equal to 1 nm.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the first carrier 10A on which the foregoing pattern is formed, patterning the fourth insulating film using a patterning process, and forming a pattern covering the fourth insulating layer.
  • the fourth insulating layer 14 pattern of the three conductive layer patterns is as shown in FIG. 10 .
  • two first bonding vias V1 are formed on the fourth insulating layer 14 .
  • an orthographic projection of a first bonding via V1 on the first substrate 10 may be located within a range of an orthographic projection of the first connection electrode 41 on the first substrate 10 , and the first The fourth insulating film in the bonding via V1 is removed to expose the surface of the first connection electrode 41.
  • the first bonding via V1 is configured to allow a first bump structure in the connection substrate to pass through the bonding.
  • the via hole is connected to the first connection electrode 41 .
  • the orthographic projection of the other first bonding via V1 on the first substrate 10 may be located within the range of the orthographic projection of the second connection electrode 42 on the first substrate 10 .
  • the fourth insulating film in a bonding via V1 is removed to expose the surface of the second connection electrode 42.
  • the first bonding via V1 is configured to allow another first bump structure in the connection substrate to pass through the first bonding via V1.
  • the via hole is connected to the second connection electrode 42 .
  • the first substrate disposed on the first carrier is completed.
  • the first substrate may include a first substrate 10 disposed on the first sacrificial layer 10B, a first insulating layer 11 disposed on the first substrate 10 , a first insulating layer 11 disposed on the first insulating layer 11
  • the first conductive layer may include at least the first pad electrode 31 , the second pad electrode 32 and the fourth connection electrode 44 , the second conductive layer may include at least the first plate 61 , and the third conductive layer may include at least the first connection electrode.
  • the first substrate may further include a pad protection layer 90 disposed on a side of the first substrate 10 away from the first insulating layer 11 and a pad protection layer 90 disposed on a side away from the first substrate 10
  • the pad conductive layer may include at least a first pad 21 and a second pad 22 .
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may adopt silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). Any one or more, can be single layer, multi-layer or composite layer.
  • the first insulating layer may be called a first barrier layer
  • the second insulating layer may be called a second (PVX) passivation layer
  • the third insulating layer may be called a third passivation layer
  • the fourth insulating layer may be called a fourth passivation layer.
  • the preparation process of the second substrate may include the following operations.
  • preparing the second substrate pattern may include: providing a second carrier plate 20A, first forming a second sacrificial layer 20B on the second carrier plate 20A, and then coating a second sacrificial layer 20B on the second sacrificial layer 20B. After the substrate film is cured to form a film, a fifth insulating film is deposited to form the second substrate 20 and the fifth insulating layer 15 disposed on the side of the second substrate 20 away from the second carrier 20A, as shown in Figure 11 .
  • the material of the second substrate may be polyimide (PI), polyethylene terephthalate (PET), or other materials.
  • the material of the second carrier plate can be glass
  • the material of the second sacrificial layer can be an organic polymer material, which can be formed by coating a viscous liquid and then curing it to form a film.
  • the second sacrificial layer is configured In order to separate the second substrate from the second carrier in the subsequent laser lift-off process.
  • forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the second carrier 20A on which the foregoing pattern is formed, using a patterning process to pattern the fourth conductive film, and in the fifth A fourth conductive layer pattern is formed on the insulating layer 15, as shown in Figure 12.
  • the fourth conductive layer pattern may include at least a third connection electrode 43 configured to be connected to the second bump structure in the connection substrate.
  • a lift-off process may also be used to form the fourth conductive layer pattern.
  • chemical mechanical polishing may be used to polish the surface of the third connection electrode 43 on the side away from the second substrate, so that the third connection electrode 43 is away from the second substrate.
  • the surface roughness of one side may be less than or equal to 1 nm.
  • Form a sixth insulating layer pattern may include: depositing a sixth insulating film on the second carrier 20A on which the foregoing pattern is formed, patterning the sixth insulating film using a patterning process, and forming a pattern covering the sixth insulating layer.
  • the sixth insulating layer 16 pattern of the four conductive layer patterns is as shown in FIG. 13 .
  • two second bonding vias V2 are formed on the sixth insulating layer 16 .
  • the orthographic projection of the two second bonding vias V2 on the second substrate 20 may be located within the range of the orthographic projection of the third connection electrode 43 on the second substrate 20 .
  • the sixth insulating film in the second bonding via hole V2 is removed, respectively exposing the surface of the third connection electrode 43.
  • the two second bonding via holes V2 are configured to connect the two second bumps in the substrate.
  • the structure is connected to the third connection electrode 43 through the bonding via hole.
  • the second substrate disposed on the second carrier is completed.
  • the second substrate may include a second substrate 20 disposed on the second sacrificial layer 20B, a fifth insulating layer 15 disposed on the second substrate 20, and a fifth insulating layer 15 disposed on the second sacrificial layer 20B.
  • a fourth conductive layer, and a sixth insulating layer 16 disposed on the fourth conductive layer, the fourth conductive layer may at least include a third connection electrode 43 .
  • the preparation process of the connection substrate may include the following operations.
  • preparing the connection substrate may include: providing the connection substrate 30 , forming at least two through holes 80 on the connection substrate 30 , and forming the connection substrate 30 of a TGV structure, as shown in FIG. 14 .
  • the structures of the at least two through holes 80 may be substantially the same, and both are through hole structures penetrating the connection substrate 30 .
  • the shape of the through hole 80 may be circular or elliptical.
  • the cross-sectional shape of the through hole 80 may be columnar, funnel-shaped, hourglass-shaped, etc., through Holes 80 are configured to receive subsequently formed conductive posts.
  • connection substrate 30 may include a first side surface 30A and a second side surface 30B facing away from each other.
  • at least one through hole may be formed using a patterning process or a laser drilling process.
  • forming at least one through hole on the connection substrate using a patterning process may include: first coating a layer of photolithography on the first side surface 30A of the connection substrate.
  • the photoresist is exposed and developed to form an exposed area and an unexposed area.
  • the photoresist in the exposed area is removed, exposing the first side surface 30A of the connection substrate.
  • the unexposed area is still covered with photoresist.
  • the connection substrate in the exposure area is etched using a dry etching process or a wet etching process, and a plurality of first blind holes are formed on the side surface of the connection substrate.
  • the cross-sectional shape of the first blind holes may be a trapezoid shape.
  • connection substrate in the exposure area is etched using a dry etching process or a wet etching process, and a plurality of second blind holes are formed on the side surface of the connection substrate.
  • the cross-sectional shape of the second blind holes may be a trapezoid shape. It is connected with the first blind hole to form an hourglass-shaped through hole.
  • using a laser drilling process to form at least one through hole on the connection substrate may include: first using a laser to irradiate the third portion of the connection substrate with a laser beam that is vertically incident.
  • a first blind hole in the shape of an inverted truncated cone is formed on this side surface of the connection substrate, and then a laser is used to illuminate the second side surface 30B of the connection substrate in a vertically incident manner with the laser beam.
  • a second blind hole in the shape of an inverted truncated cone is formed on the side surface, and the second blind hole is connected with the first blind hole to form an hourglass-shaped through hole.
  • the higher energy laser photons ionize the atoms in the connection substrate and eject them out of the connection substrate.
  • the hole gradually deepens until the first blind hole and the second blind hole are formed. Blind hole.
  • the type of laser can be continuous laser, pulse laser, etc.
  • the laser wavelength can be about 532nm, 355nm, 266nm, 248nm, 197nm, etc.
  • the pulse width of the laser can be selected from 1fs to 100fs, 1ps to 100ps, 1ns. to 100ns etc.
  • laser drilling methods may include but are not limited to the following two methods.
  • the first method when the diameter of the laser spot is large, the relative position of the laser beam and the connection substrate is fixed, and high energy is used to directly hit the connection substrate to a preset depth.
  • the second method when the diameter of the laser spot is small, the laser beam draws a circle and scans on the connection substrate. The radius of the circle gradually decreases, the focus point of the spot continues to change, and the focus depth also changes constantly, and the connection substrate is to the preset depth.
  • the material of the connection substrate may be glass, such as silicon oxide, silicon dioxide, or photosensitive glass.
  • preparing the conductive pillar pattern may include: forming a plurality of conductive pillar patterns in a plurality of through holes 80 through a filling process on the connection substrate on which the foregoing pattern is formed, as shown in FIG. 15 .
  • the conductive pillar pattern may include at least first conductive pillars 71 and second conductive pillars 72 .
  • the first conductive pillar 71 and the second conductive pillar 72 may be respectively disposed in the two through holes 80 .
  • both the first conductive pillar 71 and the second conductive pillar 72 may include a conductive layer and a seed layer located outside the conductive layer, and the seed layer is connected to the inner wall of the through hole 80 .
  • forming the plurality of conductive pillar patterns within the plurality of through holes 80 through a filling process may include:
  • the material of the seed layer may be at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the seed layer may be approximately 0.01 ⁇ m to 0.05 ⁇ m. .
  • the thickness of the seed layer may be approximately 0.03 ⁇ m
  • an auxiliary metal layer may be formed in the through hole.
  • the material of the auxiliary metal layer includes but is not limited to nickel (Ni). , at least one of molybdenum (Mo) alloy and titanium (Ti) alloy.
  • the conductive layer may be made of copper (Cu), and the thickness of the conductive layer may be approximately 0.2 ⁇ m to 0.5 ⁇ m.
  • the conductive layer can be filled with copper in the through hole using methods such as Cu electroplating or Cu core solder ball filling. For example, put the connection substrate on the carrier of the electroplating machine, press the electrification pad, and put it into a plating tank with electrolyte. Apply electricity to make the plating liquid continue to flow rapidly on the surface of the substrate substrate. The cations in the plating liquid Electrons are obtained on the inner wall of the through hole and become atoms deposited on the inner wall. As time goes by, the thickness of the copper on the inner wall of the through hole gradually increases, and the through hole can even be completely filled.
  • forming the first bump structure layer pattern may include: on the connection substrate on which the foregoing pattern is formed, forming the first bump structure layer pattern on the first side surface of the connection substrate through a patterning process , as shown in Figure 16.
  • the first bump structure layer may include at least two first bump structures 51 , one first bump structure 51 is connected to the end of the first conductive pillar 71 located on the first side surface, and the other The first bump structure 51 is connected to the end of the second conductive pillar 72 located on the first side surface.
  • the orthographic projection of the first bump structure 51 on the connection substrate includes the orthographic projection of the first conductive pillar 71 and the second conductive pillar 72 on the connection substrate, that is, the first bump structure 51 is completely Cover the end portion of the first conductive pillar 71 located on the first side surface and completely cover the end portion of the second conductive pillar 72 located on the first side surface.
  • the first bump structure 51 may include a stacked first connection layer 51-1 and a first bump layer 51-2, and the first connection layer 51-1 may be disposed on a connection lining.
  • the first bump layer 51-2 can be disposed on the first connection layer 51-1 away from the connection substrate 30
  • the first connection layer 51-1 can serve as an interconnection bonding layer, pasting the first bump layer 51-2 and the first conductive pillar 71 and the second conductive pillar 72 together, and blocking the first bump layer
  • the atoms are diffused into the conductive pillars, and the first bump layer 51 - 2 is configured to be bonded and connected to the first connection electrode and the second connection electrode in the first substrate.
  • the first connection layer may be called an under-bump metal (UBM) layer.
  • UBM under-bump metal
  • the material of the first connection layer may adopt a multi-layer composite structure, such as a composite layer of titanium (Ti) and copper (Cu) Ti/Cu, molybdenum-titanium-nickel alloy (MTD) and copper (Cu).
  • the material of the first bump layer may be tin (Sn) or indium-tin alloy (Sn-In), etc., which not only has good stretchability but also has anti-corrosion properties.
  • forming the first bump structure layer pattern on the first side surface of the connection substrate 30 through a patterning process may include: first depositing a first connection film on the first side surface of the connection substrate 30, Then, a layer of photoresist is coated on the first connection film, and a photoresist pattern is formed through exposure and development.
  • the photoresist pattern includes an exposed area and an unexposed area. The photoresist in the exposed area is removed, exposing the first connection. film, the photoresist in the unexposed area covers the first connection film.
  • the first bump structures 51 are formed on the first side surface of the connection substrate 30 .
  • the first bump structures 51 include stacked first connection layers 51 - 1 and first bump layers 51 - 2 .
  • forming the second bump structure layer pattern may include: on the connection substrate on which the foregoing pattern is formed, forming the second bump structure layer pattern on the second side surface of the connection substrate through a patterning process. , as shown in Figure 17.
  • the second bump structure layer may include at least two second bump structures 52 , one of the second bump structures 52 is connected to the end of the first conductive pillar 71 located on the second side surface, and the other The second bump structure 52 is connected to the end of the second conductive pillar 72 located on the second side surface.
  • the orthographic projection of the second bump structure 52 on the connection substrate includes the orthographic projection of the first conductive pillar 71 and the second conductive pillar 72 on the connection substrate, that is, the second bump structure 52 is completely Cover the end portion of the first conductive pillar 71 located on the second side surface and completely cover the end portion of the second conductive pillar 72 located on the second side surface.
  • the second bump structure 52 may include a stacked second connection layer 52-1 and a second bump layer 52-2, and the second connection layer 52-1 may be disposed on the connection substrate 30 , respectively connected to the ends of the first conductive pillar 71 and the second conductive pillar 72 in the through hole, the second bump layer 52-2 can be disposed on the side of the second connection layer 52-1 away from the connection substrate 30,
  • the second connection layer 52-1 may serve as an interconnection bonding layer and may be called a UBM layer.
  • the material of the second connection layer may be substantially the same as the material of the first connection layer
  • the material of the second bump layer may be substantially the same as the material of the first bump layer
  • the preparation method and formation method of forming the second bump structure layer The first bump structure layer can be prepared in substantially the same manner.
  • connection substrate is prepared.
  • the connection substrate may include the connection substrate 30 , first conductive pillars 71 and second conductive pillars 72 penetrating the connection substrate 30 in the thickness direction, and at least two first bump structures disposed on the first side surface of the connection substrate 30 51 and at least two second bump structures 52 provided on the second side surface of the connection substrate 30 .
  • the bonding process may include the following operations: disposing the prepared first substrate 100 on one side of the first side surface of the connection substrate 300, flipping the prepared second substrate 200 and disposing it on the connection substrate 300.
  • the side of the second side surface of the substrate 300 is as shown in FIG. 18 .
  • first substrate 100, the second substrate 200 and the connection substrate 300 are aligned and bonded, the first substrate 100, the connection substrate 300 and the second substrate 200 are pressed together using a metal-to-metal diffusion bonding method to complete the connection.
  • One first bump structure 51 in the substrate 300 is connected to the first connection electrode 41 in the first substrate 100, and another first bump structure 51 in the substrate 300 is connected to the second connection electrode 42 in the first substrate 100.
  • the two second bump structures 52 in the connection substrate 300 are bonded and connected to the third connection electrode 43 in the second substrate 200 to form an electrical connection structure of the first substrate 100, the connection substrate 300 and the second substrate 200, as shown in Figure 19 shown.
  • the bonding pressure may be about 40 kN to 100 kN, and the bonding temperature may be about 350°C to 450°C.
  • the first connection electrode 41 in the first substrate 100 and the third connection electrode 43 in the second substrate 200 are connected through the first bump structure 51 in the substrate 300 , the first conductive pillar 71 and the second bump structure 52 are connected to each other, so that the second connection electrode 42 in the first substrate 100 and the third connection electrode 43 in the second substrate 200 are connected through the connection substrate 300
  • the first bump structure 51, the second conductive pillar 72 and the second bump structure 52 are connected to each other, and the first connection electrode 41, the first conductive pillar 71, the third connection electrode 43 and the second conductive pillar 72 are connected in sequence.
  • the second connection electrode 42 form a filter inductor with a three-dimensional spiral inductor structure.
  • the filter inductor and the filter capacitor are realized. They are interconnected through the fourth connection electrode 44 .
  • first carrier plate 10A and the first sacrificial layer 10B on the side of the first substrate 100 away from the connection substrate 300 are peeled off through a laser lift-off process, and the second carrier plate 20A and the second carrier plate 20A on the side of the second substrate 200 away from the connection substrate 300 are peeled off.
  • the second sacrificial layer 20B forms a filter according to an exemplary embodiment of the present disclosure, as shown in FIG. 1 .
  • the first sacrificial layer and the second sacrificial layer will decompose relatively completely when exposed to light, thereby facilitating the separation of the first substrate and the first carrier plate, and the second substrate and the second carrier plate.
  • the first substrate, the second substrate and the connection substrate are respectively prepared, and then the first substrate is bonded and connected on both sides of the connection substrate using a bonding method.
  • the substrate and the second substrate not only realize the integration of the filter inductor of the three-dimensional spiral inductor structure and the filter capacitor of the parallel plate capacitor structure on one chip, the integrated filter chip has a high degree of integration and reduces the size of the filter.
  • connection substrate uses a glass substrate, which can not only reduce filter loss, but also reduce production costs.
  • the preparation process of the present disclosure can be realized by using existing mature preparation equipment. It has little improvement to the existing process and can be well compatible with the existing preparation process. The process is simple to realize, easy to implement, has high production efficiency and low production cost. The yield rate is high.
  • connection substrate 300 may be provided with n through holes penetrating the connection substrate 30 in the thickness direction, n conductive pillars are respectively provided in the n through holes, and the n conductive pillars may be arranged along the thickness direction. Arrange according to the set direction rules.
  • the first substrate 100 may be provided with one first connection electrode 41 and n/2 second connection electrodes 42.
  • the second substrate 200 may be provided with n/2 third connection electrodes 43.
  • the first connection electrode 41 may be connected to The first conductive column and the (n/2) second connection electrode 42 among the n conductive columns can be connected to the nth conductive column among the n conductive columns, and the other plurality of second connection electrodes 42 can be connected to n respectively.
  • the i+1-th conductive pillar and the i+2-th conductive pillar among the conductive pillars, the plurality of third connection electrodes 43 can respectively connect the i-th conductive pillar and the i+1-th conductive pillar among the n conductive pillars, and the n conductive pillars , the first connection electrode 41, n/2 second connection electrodes 42 and n/2 third connection electrodes 43 constitute the first filter inductor of the three-dimensional spiral inductor structure, n is an even number greater than or equal to 2, i is greater than or equal to An odd number equal to 1, less than or equal to n-2.
  • the first connection electrode 41 can be connected to the first pad of the resonator, the (n/2)th second connection electrode 42 can be connected to the first plate of the filter capacitor, and the second plate of the filter capacitor can be connected to the resonator. of the second pad connection.
  • Exemplary embodiments of the present disclosure also provide a method of manufacturing a filter to prepare the filter of the foregoing embodiment.
  • the preparation method of the filter may include:
  • a first substrate, a second substrate and a connection substrate are respectively prepared. At least one first substrate electrode is provided on the first substrate. At least one second substrate electrode is provided on the second substrate.
  • the connection substrate at least includes a connection The substrate and at least one conductive pillar penetrating the connection substrate, one end of the conductive pillar close to the first substrate is connected to a first bump structure, and one end of the conductive pillar close to the second substrate is connected to a third Two bump structures;
  • the first substrate and the second substrate are arranged oppositely, and the connection substrate is arranged between the first substrate and the second substrate, and the first bump structure and the first substrate are connected by bonding. Electrode connection, the second bump structure and the second substrate electrode are connected.
  • preparing the connection substrate may include:
  • connection substrate forming a plurality of through holes on the connection substrate, the material of the connection substrate including glass;
  • a plurality of first bump structures are formed on the first side surface of the connection substrate, and a plurality of second bump structures are formed on the second side surface of the connection substrate;
  • the first bump structure includes a a first connection layer on the first side surface of the connection substrate and a first bump layer disposed on a side of the first connection layer away from the connection substrate, a plurality of first connection layers and a plurality of conductive The ends of the pillars located on the first side surface are connected correspondingly;
  • the second bump structure includes a second connection layer provided on the second side surface of the connection substrate and a second connection layer provided away from the second connection layer.
  • the second bump layer on one side of the connection substrate is connected to a plurality of second connection layers corresponding to the ends of the plurality of conductive pillars located on the second side surface.
  • forming a plurality of first bump structures on the first side surface of the connection substrate, and forming a plurality of second bump structures on the second side surface of the connection substrate may include:
  • a first connection film is deposited on the first side surface of the connection substrate, a layer of photoresist is coated on the first connection film, and a photoresist pattern is formed through exposure and development.
  • the photoresist pattern includes exposed areas and unexposed areas. area, the photoresist in the exposed area is removed, exposing the first connection film, and the photoresist in the unexposed area covers the first connection film; after the first bump film is formed in the exposed area, the photoresist pattern and photolithography are
  • the first bump film on the glue is used as a shield to etch the first connection film to form a plurality of first bump structures on the first side surface of the connection substrate.
  • the first bump structure includes a stacked first connection layer and a first bump layer;
  • a second connection film is deposited on the second side surface of the connection substrate, a layer of photoresist is coated on the second connection film, and a photoresist pattern is formed through exposure and development.
  • the photoresist pattern includes exposed areas and unexposed areas. area, the photoresist in the exposed area is removed, exposing the second connection film, and the photoresist in the unexposed area covers the second connection film; after forming the second bump film in the exposed area, the photoresist pattern and photolithography are
  • the second bump film on the glue is used as a shield to etch the second connection film to form a plurality of second bump structures on the second side surface of the connection substrate.
  • the second bump structure includes a stacked second connection layer and a second bump layer.
  • the present disclosure also provides an electronic device, including the filter of the foregoing embodiment.
  • Electronic equipment can be used in radio frequency front-end devices in wireless communication devices, such as radio frequency filters.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

本公开提供了一种滤波器及其制备方法、电子设备。滤波器包括相对设置的第一基板(100)、第二基板(200)以及设置在第一基板(100)和第二基板(200)之间的连接基板(300)，第一基板(100)上设置有至少一个第一基板电极，第二基板(200)上设置有至少一个第二基板电极，连接基板(300)至少包括连接衬底(30)和在厚度方向贯通连接衬底(30)的至少一个导电柱，导电柱靠近第一基板(100)的一端设置有第一凸点结构(51)，导电柱靠近第二基板(200)的一端设置有第二凸点结构(52)，第一凸点结构(51)与第一基板电极、第二凸点结构(52)与第二基板电极通过键合方式连接。

Description

滤波器及其制备方法、电子设备 技术领域
本公开涉及但不限于半导体技术领域，尤指一种滤波器及其制造方法、电子设备。
背景技术
滤波器作为通信终端中的重要组成部件，能够解决信号传输过程中的相互干扰问题，提高频谱利用率。随着移动通信技术的发展，移动通信系统要求面积小、高性能、一致性好的的滤波器，集成无源器件(Integrated Passive Device，简称IPD)因优越的独立无源元件特性，被广泛应用于无线通信设备中射频(Radio Frequency，简称RF)前端芯片中。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种滤波器，包括相对设置的第一基板、第二基板以及设置在所述第一基板和第二基板之间的连接基板，所述第一基板上设置有至少一个第一基板电极，所述第二基板上设置有至少一个第二基板电极，所述连接基板至少包括连接衬底和在厚度方向贯通所述连接衬底的至少一个导电柱，所述导电柱靠近所述第一基板的一端设置有第一凸点结构，所述导电柱靠近所述第二基板的一端设置有第二凸点结构，所述第一凸点结构与所述第一基板电极、所述第二凸点结构与所述第二基板电极通过键合方式连接。
在示例性实施方式中，所述连接衬底包括靠近所述第一基板的第一侧表面和靠近所述第二基板的第二侧表面，所述第一凸点结构设置在所述连接衬底的第一侧表面上，且与所述导电柱靠近所述第一基板的一端连接，所述第二凸点结构设置在所述连接衬底的第二侧表面上，且与所述导电柱靠近所述 第二基板的一端连接。
在示例性实施方式中，所述第一凸点结构在所述连接衬底上的正投影包含所述导电柱在所述连接衬底上的正投影，所述第二凸点结构在所述连接衬底上的正投影包含所述导电柱在所述连接衬底上的正投影。
在示例性实施方式中，所述第一凸点结构包括设置在所述连接衬底的第一侧表面上的第一连接层和设置在所述第一连接层远离所述连接衬底一侧的第一凸点层，所述第一连接层与所述导电柱靠近所述第一基板的一端连接，所述第一凸点层与所述第一基板电极通过键合方式连接；所述第二凸点结构包括设置在所述连接衬底的第二侧表面上的第二连接层和设置在所述第二连接层远离所述连接衬底一侧的第二凸点层，所述第二连接层与所述导电柱靠近所述第二基板的一端连接，所述第二凸点层与所述第二基板电极通过键合方式连接。
在示例性实施方式中，所述第一连接层和第二连接层的材料包括如下任意一种：钛和铜的复合层，钼钛镍合金和铜的复合层，钼钛镍合金、铜镍合金和铜的复合层。
在示例性实施方式中，所述第一凸点层和第二凸点层的材料包括如下任意一种：锡，铟锡合金。
在示例性实施方式中，所述导电柱至少包括第一导电柱和第二导电柱，所述第一基板电极至少包括第一连接电极和第二连接电极，所述第二基板电极至少包括第三连接电极，所述第一连接电极与所述第一导电柱连接，所述第二连接电极与所述第二导电柱连接，所述第三连接电极分别与所述第一导电柱和第二导电柱连接，所述第一导电柱、第二导电柱、第一连接电极、第二连接电极和第三连接电极构成三维螺旋电感结构的滤波电感。
在示例性实施方式中，所述第一基板还设置有滤波电容，所述滤波电容与所述滤波电感连接。
在示例性实施方式中，所述第一基板至少包括第一衬底、设置在所述第一衬底靠近所述连接基板一侧的第一导电层、设置在所述第一导电层靠近所述连接基板一侧的第二导电层、设置在所述第二导电层靠近所述连接基板一 侧的第三导电层，所述第一连接电极和第二连接电极设置在所述第三导电层中。
在示例性实施方式中，所述滤波电容包括第一极板和第二极板，所述第一极板在所述第一衬底上的正投影与所述第二极板在所述第一衬底上的正投影至少部分交叠，所述第一极板设置在所述第二导电层中，所述第二极板设置在所述第三导电层中。
在示例性实施方式中，所述第一导电层至少包括第一焊盘电极、第二焊盘电极和第四连接电极，所述第一连接电极通过过孔与所述第一焊盘电极连接，所述第二连接电极和所述第一极板分别通过过孔与所述第四连接电极连接，所述第二极板通过过孔与所述第二焊盘电极连接。
在示例性实施方式中，所述第一基板还包括焊盘导电层和焊盘保护层，所述焊盘保护层设置在所述第一衬底远离所述连接基板的一侧，所述焊盘导电层设置在所述焊盘保护层远离所述连接基板的一侧，所述焊盘导电层至少包括第一焊盘和第二焊盘，所述第一焊盘电极通过过孔与所述第一焊盘连接，所述第二焊盘电极通过过孔与所述第二焊盘连接。
在示例性实施方式中，所述焊盘导电层远离所述连接基板一侧的表面与所述第一衬底远离所述连接基板一侧的表面平齐。
在示例性实施方式中，所述焊盘保护层远离所述连接基板一侧的表面与所述第一衬底远离所述连接基板一侧的表面平齐。
在示例性实施方式中，所述导电柱包括n个导电柱，所述第一基板电极包括一个第一连接电极和n/2个第二连接电极，所述第二基板电极包括n/2个第三连接电极，所述第一连接电极41与n个导电柱中的第1导电柱连接，第(n/2)个第二连接电极与n个导电柱中的第n导电柱连接，其它的第二连接电极分别连接n个导电柱中的第i+1导电柱和第i+2导电柱，多个第三连接电极分别连接n个导电柱中的第i导电柱和第i+1导电柱，n个导电柱、第一连接电极、n/2个第二连接电极和n/2个第三连接电极构成三维螺旋电感结构的第一滤波电感，n为大于或等于2的偶数，i为大于或等于1、小于或等于n-2的奇数。
在示例性实施方式中，所述第一基板还设置有滤波电容、第一焊盘和第二焊盘，所述第一连接电极与所述第一焊盘连接，第(n/2)个第二连接电极与所述滤波电容的第一极板连接，所述滤波电容的第二极板与所述第二焊盘连接。
在示例性实施方式中，所述第二基板至少包括第二衬底、设置在所述第二衬底靠近所述连接基板一侧的第四导电层，所述第三连接电极设置在所述第四导电层中。
另一方面，本公开还提供了一种电子设备，包括前述的滤波器。
又一方面，本公开还提供了一种滤波器的制备方法，包括：
分别制备第一基板、第二基板和连接基板，所述第一基板上设置有至少一个第一基板电极，所述第二基板上设置有至少一个第二基板电极，所述连接基板至少包括连接衬底和贯通所述连接衬底的至少一个导电柱，所述导电柱靠近所述第一基板的一端连接有第一凸点结构，所述导电柱靠近所述第二基板的一端连接有第二凸点结构；
将所述第一基板和第二基板相对设置，且所述连接基板设置在所述第一基板和第二基板之间，通过键合方式将所述第一凸点结构与所述第一基板电极连接、所述第二凸点结构与所述第二基板电极连接起来。
在示例性实施方式中，制备连接基板包括：
提供连接衬底，在所述连接衬底上形成多个通孔，所述连接衬底的材料包括玻璃；
在多个通孔内形成多个导电柱；
在所述连接衬底的第一侧表面形成多个第一凸点结构，在所述连接衬底的第二侧表面形成多个第二凸点结构；所述第一凸点结构包括设置在所述连接衬底的第一侧表面上的第一连接层和设置在所述第一连接层远离所述连接衬底一侧的第一凸点层，多个第一连接层与多个导电柱位于所述第一侧表面的端部对应连接；所述第二凸点结构包括设置在所述连接衬底的第二侧表面上的第二连接层和设置在所述第二连接层远离所述连接衬底一侧的第二凸点 层，多个第二连接层与多个导电柱位于所述第二侧表面的端部对应连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开示例性实施例一种滤波器的结构示意图；
图2为本公开实施例滤波器形成焊盘导电层图案后示意图；
图3为本公开实施例滤波器形成焊盘保护层图案后示意图；
图4为本公开实施例滤波器形成第一衬底图案后示意图；
图5为本公开实施例滤波器形成第一导电层图案后示意图；
图6为本公开实施例滤波器形成第二绝缘层图案后示意图；
图7为本公开实施例滤波器形成第二导电层图案后示意图；
图8为本公开实施例滤波器形成第三绝缘层图案后示意图；
图9为本公开实施例滤波器形成第三导电层图案后示意图；
图10为本公开实施例滤波器形成第四绝缘层图案后示意图；
图11为本公开实施例滤波器形成第二衬底图案后示意图；
图12为本公开实施例滤波器形成第四导电层图案后示意图；
图13为本公开实施例滤波器形成第六绝缘层图案后示意图；
图14为本公开实施例滤波器制备连接衬底图案后示意图；
图15为本公开实施例滤波器制备导电柱图案后示意图；
图16为本公开实施例滤波器形成第一凸点结构层图案后示意图；
图17为本公开实施例滤波器形成第二凸点结构层图案后示意图；
图18和图19为本公开实施例滤波器键合处理的示意图。
附图标记说明:
10—第一衬底；          10A—第一载板；         10B—第一牺牲层；
11—第一绝缘层；        12—第二绝缘层；        13—第三绝缘层；
14—第四绝缘层；        15—第五绝缘层；        16—第六绝缘层；
20—第二衬底；          20A—第二载板；         20B—第二牺牲层；
21—第一焊盘；          22—第二焊盘；          30—连接衬底；
31—第一焊盘电极；      32—第二焊盘电极；      41—第一连接电极；
42—第二连接电极；      43—第三连接电极；      44—第四连接电极；
51—第一凸点结构；      52—第二凸点结构；      61—第一极板；
62—第二极板；          71—第一导电柱；        72—第二导电柱；
80—通孔；              90—焊盘保护层；        100—第一基板；
200—第二基板；         300—连接基板。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、 “竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
为了满足不断增长的宽频带、低成本和高集成度的需求，玻璃通孔 (Through Glass Via，简称TGV)技术逐渐成为无源滤波器(LC滤波器)设计的一种可行技术。与硅(Si)基IPD相比，基于TGV的IPD可以避免硅基绝缘性差导致器件微波损耗高的问题，可以实现更优的电性能。与砷化镓(GaAs)基IPD相比，基于TGV的IPD具有价格便宜的优点，且适合高频应用。
玻璃通孔TGV技术是指，在玻璃基底上制作通孔，并在通孔中填充金属材料，通过过孔中的金属材料将位于玻璃基底上表面的功能结构和位于玻璃基底下表面的功能结构电连接。研究表明，在玻璃基底的上表面和下表面制作相应功能结构时，会经历高温退火或者高温沉积薄膜等工艺过程，由于通孔中填充金属材料的热膨胀系数与玻璃基底的热膨胀系数存在差异，因而容易使金属材料凸出通孔，导致金属材料与功能结构之间断开连接，降低了产品良率。
本公开提供了一种无源滤波器，包括相对设置的第一基板、第二基板以及设置在所述第一基板和第二基板之间的连接基板，所述第一基板上设置有至少一个第一基板电极，所述第二基板上设置有至少一个第二基板电极，所述连接基板至少包括连接衬底和在厚度方向贯通所述连接衬底的至少一个导电柱，所述导电柱靠近所述第一基板的一端设置有第一凸点结构，所述导电柱靠近所述第二基板的一端设置有第二凸点结构，所述第一凸点结构与所述第一基板电极、所述第二凸点结构与所述第二基板电极通过键合方式连接。
在示例性实施方式中，所述连接衬底包括靠近所述第一基板的第一侧表面和靠近所述第二基板的第二侧表面，所述第一凸点结构设置在所述连接衬底的第一侧表面上，且与所述导电柱靠近所述第一基板的一端连接，所述第二凸点结构设置在所述连接衬底的第二侧表面上，且与所述导电柱靠近所述第二基板的一端连接。
在示例性实施方式中，所述第一凸点结构包括设置在所述连接衬底的第一侧表面上的第一连接层和设置在所述第一连接层远离所述连接衬底一侧的第一凸点层，所述第一连接层与所述导电柱靠近所述第一基板的一端连接，所述第一凸点层与所述第一基板电极通过键合方式连接；所述第二凸点结构包括设置在所述连接衬底的第二侧表面上的第二连接层和设置在所述第二连 接层远离所述连接衬底一侧的第二凸点层，所述第二连接层与所述导电柱靠近所述第二基板的一端连接，所述第二凸点层与所述第二基板电极通过键合方式连接。
在示例性实施方式中，所述导电柱至少包括第一导电柱和第二导电柱，所述第一基板电极至少包括第一连接电极和第二连接电极，所述第二基板电极至少包括第三连接电极，所述第一连接电极与所述第一导电柱连接，所述第二连接电极与所述第二导电柱连接，所述第三连接电极分别与所述第一导电柱和第二导电柱连接，所述第一导电柱、第二导电柱、第一连接电极、第二连接电极和第三连接电极构成三维螺旋电感结构的滤波电感。
在示例性实施方式中，所述第一基板还设置有滤波电容，所述滤波电容与所述滤波电感连接。
图1为本公开示例性实施例一种滤波器的结构示意图。如图1所示，本公开示例性实施例滤波器的主体结构可以包括相对设置的第一基板100、第二基板200和以及设置在第一基板100和第二基板200之间的连接基板300，第一基板100与连接基板300通过键合方式实现连接，第二基板200与连接基板300通过键合方式实现连接，构成包含滤波电感和滤波电容的无源滤波器。
在示例性实施方式中，连接基板300可以至少包括连接衬底30、在厚度方向贯通连接衬底30的第一导电柱71和第二导电柱72，第一基板100可以至少包括第一衬底10和设置在第一衬底10靠近第二基板200一侧的第一连接电极41和第二连接电极42，第二基板200可以至少包括第二衬底20和设置在第二衬底20靠近第一基板100一侧的第三连接电极43。第一导电柱71和第二导电柱72靠近第一基板100的一端分别设置有第一凸点结构51，第一导电柱71和第二导电柱72靠近第二基板200的一端分别设置有第二凸点结构52，连接基板300的两个第一凸点结构51分别与第一基板100的第一连接电极41和第二连接电极42通过键合方式连接，连接基板300的两个第一凸点结构51分别与第二基板200的第三连接电极43通过键合方式连接，形成第一基板100、连接基板300和第二基板200的电连接结构。
在示例性实施方式中，第一连接电极41和第二连接电极42可以作为本 公开的第一基板电极，第三连接电极43可以作为本公开的第二基板电极。
在示例性实施方式中，连接衬底30可以包括靠近第一基板100的第一侧表面和靠近第二基板200的第二侧表面，两个第一凸点结构51可以设置在连接衬底30的第一侧表面上，且分别与第一导电柱71和第二导电柱72靠近第一基板100的一端连接，两个第二凸点结构52可以设置在连接衬底30的第二侧表面上，且分别与第一导电柱71和第二导电柱72靠近第二基板200的一端连接。
在示例性实施方式中，第一凸点结构51在连接衬底上的正投影可以包含第一导电柱71和第二导电柱72在连接衬底上的正投影，第二凸点结构52在连接衬底上的正投影可以包含第一导电柱71和第二导电柱72在连接衬底上的正投影。
在示例性实施方式中，第一凸点结构51可以包括叠设的第一连接层51-1和第一凸点层51-2。第一连接层51-1可以设置在连接衬底30的第一侧表面上，分别与第一导电柱71和第二导电柱72靠近第一基板100的一端连接。第一凸点层51-2可以设置在第一连接层51-1远离连接衬底30的一侧，分别与第一连接电极41和第二连接电极42通过键合方式连接。
在示例性实施方式中，第二凸点结构52可以包括叠设的第二连接层52-1和第二凸点层52-2。第二连接层52-1可以设置在连接衬底30的第二侧表面上，分别与第一导电柱71和第二导电柱72靠近第二基板200的一端连接。第二凸点层52-2可以设置在第二连接层52-1靠近第二基板200的一侧，分别与第三连接电极43通过键合方式连接。
在示例性实施方式中，第一连接层51-1和第二连接层52-1的材料可以包括如下任意一种：钛和铜的复合层，钼钛镍合金和铜的复合层，钼钛镍合金、铜镍合金和铜的复合层。
在示例性实施方式中，第一凸点层51-2和第二凸点层52-2的材料包括如下任意一种：锡，铟锡合金。
在示例性实施方式中，第一基板100可以包括三维螺旋电感结构的滤波电感和平行板电容结构的滤波电容，滤波电感与滤波电容连接。
在示例性实施方式中，第一连接电极41通过第一凸点结构51与第一导电柱71连接，第二连接电极42通过第一凸点结构51与第二导电柱72连接，第三连接电极43通过第二凸点结构52分别与第一导电柱71和第二导电柱72连接，依次连接的第一连接电极41、第一导电柱71、第三连接电极43、第二导电柱72和第二连接电极42构成三维螺旋电感结构的滤波电感。
在示例性实施方式中，滤波电容可以包括第一极板61和第二极板62，第一极板61在第一衬底10上的正投影与第二极板62在第一衬底上的正投影至少部分交叠。
在示例性实施方式中，第一基板100可以至少包括：第一衬底10，设置在第一衬底10靠近连接基板300一侧的第一绝缘层11，设置在第一绝缘层11靠近连接基板300一侧的第一导电层，设置在第一导电层靠近连接基板300一侧的第二绝缘层12，设置在第二绝缘层12靠近连接基板300一侧的第二导电层，设置在第二导电层靠近连接基板300一侧的第三绝缘层13，设置在第三绝缘层13靠近连接基板300一侧的第三导电层，以及设置在第三导电层靠近连接基板300一侧的第四绝缘层14。
在示例性实施方式中，第一导电层可以至少包括第一焊盘电极31、第二焊盘电极32和第四连接电极44，第二导电层可以至少包括第一极板61，第三导电层可以至少包括第一连接电极41、第二连接电极42和第二极板62，第二连接电极42可以通过过孔与第四连接电极44连接，第一极板61可以通过过孔与第四连接电极44连接，因而实现了滤波电感与滤波电容通过第四连接电极44的相互连接。
在示例性实施方式中，第四绝缘层14上设置有至少两个第一键合过孔，至少两个第一键合过孔分别暴露出第一连接电极41和第二连接电极42，至少两个第一凸点结构51伸入到相应的第一键合过孔中，分别与第一连接电极41和第二连接电极42键合连接。
在示例性实施方式中，第二基板200可以至少包括：第二衬底20，设置在第二衬底20靠近连接基板300一侧的第五绝缘层15，设置在第五绝缘层15靠近连接基板300一侧的第四导电层，以及设置在第四导电层靠近连接基板300一侧的第六绝缘层16。
在示例性实施方式中，第四导电层可以至少包括第三连接电极43。第六绝缘层16上设置有至少两个第二键合过孔，至少两个第二键合过孔分别暴露出第三连接电极43，至少两个第二凸点结构52伸入到相应的第二键合过孔中，分别与第三连接电极43键合连接。
在示例性实施方式中，第一基板100还可以包括焊盘导电层和焊盘保护层90，焊盘保护层90可以设置在第一衬底10远离连接基板300的一侧，焊盘导电层可以设置在焊盘保护层90远离连接基板300的一侧。
在示例性实施方式中，焊盘保护层90远离连接基板300一侧的表面与第一衬底10远离连接基板300一侧的表面可以基本上平齐。
在示例性实施方式中，焊盘导电层远离连接基板300一侧的表面与第一衬底10远离连接基板300一侧的表面可以基本上平齐。
在示例性实施方式中，焊盘导电层可以包括至少一个第一焊盘21和至少一个第二焊盘22，第一衬底10和第一绝缘层11上设置有第一过孔和第二过孔，第一焊盘电极31可以通过第一过孔与第一焊盘21连接，第二焊盘电极32可以通过第二过孔与第二焊盘22连接。
在示例性实施方式中，第一连接电极41可以通过过孔与第一焊盘电极31连接，第二极板62可以通过过孔与第二焊盘电极32连接，因而实现了第一焊盘21与滤波电感的连接，第二焊盘22与滤波电容的连接。
在示例性实施方式中，三维螺旋电感结构的滤波电感所包括的导电柱和连接电极的数量可以根据电感量(如线圈匝数)等参数进行设置。
在示例性实施方式中，连接基板300上可以设置有在厚度方向上贯通连接衬底30的n个通孔，n个导电柱分别设置在n个通孔内，n个导电柱可以沿着设定方向规则排布。第一基板100上可以设置有一个第一连接电极41和n/2个第二连接电极42，第二基板200上可以设置有n/2个第三连接电极43，第一连接电极41可以连接n个导电柱中的第1导电柱，第(n/2)个第二连接电极42可以连接n个导电柱中的第n导电柱，其它的多个第二连接电极42可以分别连接n个导电柱中的第i+1导电柱和第i+2导电柱，多个第三连接电极43可以分别连接n个导电柱中的第i导电柱和第i+1导电柱，n个 导电柱、第一连接电极41、n/2个第二连接电极42和n/2个第三连接电极43构成三维螺旋电感结构的第一滤波电感，n为大于或等于2的偶数，i为大于或等于1、小于或等于n-2的奇数。
在示例性实施方式中，第一连接电极41可以与谐振器的第一焊盘连接，第(n/2)个第二连接电极42可以与滤波电容的第一极板连接，滤波电容的第二极板可以与谐振器的第二焊盘连接。
下面通过滤波器的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于滤波器方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
本公开示例性实施例滤波器的制备过程可以至少包括四部分，分别为第一基板的制备、第二基板的制备、连接基板的制备和键合处理。其中，连接基板的制备、第一基板的制备和第二基板的制备三者没有先后次序要求，可以同时进行，而键合处理需要在连接基板、第一基板和第二基板制备完成后进行。下面分别说明四部分的制备过程。
第一部分、第一基板的制备
在示例性实施方式中，第一基板的制备过程可以包括如下操作。
(11)形成焊盘导电层图案。在示例性实施方式中，形成焊盘导电层图案可以包括：提供第一载板10A，先在第一载板10A上形成第一牺牲层(De-bonding Layer，简称DBL)10B，然后在第一牺牲层10B上沉积焊盘导电薄膜，采用图案化工艺对焊盘导电薄膜进行图案化处理，在第一牺牲层10B上形成焊盘导电层图案，如图2所示。
在示例性实施方式中，焊盘导电层可以至少包括第一焊盘21和第二焊盘22，第一焊盘21被配置作为滤波器的输入端子，第二焊盘22被配置作为滤波器的输出端子，或者，第一焊盘21被配置作为滤波器的输出端子，第二焊盘22被配置作为滤波器的输入端子。
在示例性实施方式中，第一载板的材料可以采用玻璃，第一牺牲层的材料可以采用有机聚合物材料，可以采用涂覆粘性液体后固化成膜的方式形成，第一牺牲层被配置为在后续激光剥离(Laser Lift-Off，简称LLO)工艺中使得第一基板与第一载板分离。
在示例性实施方式中，形成焊盘导电层图案也可以采用剥离(Lift-Off)工艺。例如，先在第一载板上涂覆光刻胶，曝光显影后形成光刻胶图案，然后沉积焊盘导电薄膜，随后剥离光刻胶图案以及光刻胶图案上面的焊盘导电薄膜，在第一载板上形成包括第一焊盘21和第二焊盘22的焊盘导电层图案。
(12)形成焊盘保护层图案。在示例性实施方式中，形成焊盘保护层图案可以包括：在形成前述图案的第一载板10A，沉积焊盘保护薄膜，采用图案化工艺对焊盘保护薄膜进行图案化处理，形成覆盖焊盘导电层的焊盘保护层90图案，如图3所示。
在示例性实施方式中，焊盘保护层90可以仅设置在第一焊盘21和第二焊盘22所在区域，覆盖第一焊盘21和第二焊盘22的焊盘保护层90设置有第一过渡孔和第二过渡孔，第一过渡孔内的焊盘保护薄膜被去掉，暴露出第一焊盘21的表面，第二过渡孔内的焊盘保护薄膜被去掉，暴露出第二焊盘22的表面。
(13)形成第一衬底图案。在示例性实施方式中，形成第一衬底图案可以包括：在形成前述图案的第一载板10A，先涂覆第一衬底薄膜，固化成膜 后，沉积第一绝缘薄膜，采用图案化工艺对第一绝缘薄膜和第一衬底薄膜进行图案化处理，形成覆盖焊盘导电层和焊盘保护层的第一衬底10，以及设置在第一衬底10远离第一载板10A一侧的第一绝缘层11，如图4所示。
在示例性实施方式中，第一衬底10不仅覆盖焊盘导电层和焊盘保护层90，而且覆盖焊盘保护层90以外的第一牺牲层10B。在第一焊盘21所在区域，第一衬底10和第一绝缘层11设置有第一过孔K1，第一过孔K1在第一衬底上的正投影可以位于第一焊盘21在第一衬底上的正投影的范围之内，第一过孔K1内的第一绝缘薄膜和第一衬底薄膜被去掉，暴露出第一焊盘21的表面，第一过孔K1被配置为使后续形成的第一焊盘电极通过该过孔与第一焊盘21连接。在第二焊盘22所在区域，第一衬底10和第一绝缘层11设置有第二过孔K2，第二过孔K2在第一衬底上的正投影可以位于第二焊盘22在第一衬底上的正投影的范围之内，第二过孔K2内的第一绝缘薄膜和第一衬底薄膜被去掉，暴露出第二焊盘22的表面，第二过孔K2被配置为使后续形成的第二焊盘电极通过该过孔与第二焊盘22连接。
在示例性实施方式中，第一过孔K1在第一衬底10上的正投影可以位于第一过渡孔在第一衬底10上的正投影的范围之内，第二过孔K2在第一衬底10上的正投影可以位于第二过渡孔在第一衬底10上的正投影的范围之内。
在示例性实施方式中，第一衬底的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)等材料。
(14)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的第一载板10A，通过种子层沉积方式和加成法方式，在第一绝缘层11远离第一载板10A的一侧形成第一导电层图案，如图5所示。
在示例性实施方式中，第一导电层图案可以至少包括间隔设置的第一焊盘电极31、第二焊盘电极32和第四连接电极44。
在示例性实施方式中，第一焊盘电极31可以通过第一过孔K1与第一焊盘21连接，第二焊盘电极32可以通过第二过孔K2与第二焊盘22连接，第一焊盘电极31被配置为与后续形成的第一连接电极连接，第二焊盘电极32 被配置为与后续形成的第二极板连接。
在示例性实施方式中，第四连接电极44可以设置在第一焊盘电极31和第二焊盘电极32之间，第四连接电极44被配置为与后续形成的第一连接电极和第一极板连接，实现滤波电感与滤波电容的连接。
在示例性实施方式中，种子层沉积方式可以采用电化学沉积(ECD)等方式，加成法方式是指有选择性地沉积导电薄膜形成导电图形的方式。
在示例性实施方式中，形成第一导电层图案也可以采用图案化工艺，或者可以采用剥离工艺。
(15)形成第二绝缘层图案。在示例性实施方式中，形成第二绝缘层图案可以包括：在形成前述图案的第一载板10A，沉积第二绝缘薄膜，采用图案化工艺对第二绝缘薄膜进行图案化处理，形成覆盖第一导电层图案的第二绝缘层12图案，如图6所示。
在示例性实施方式中，第二绝缘层12上形成有第三过孔K3，第三过孔K3在第一衬底上的正投影可以位于第四连接电极44在第一衬底上的正投影的范围之内，第三过孔K3内的第二绝缘薄膜被去掉，暴露出第四连接电极44的表面，第三过孔K3被配置为使后续形成的第一极板通过该过孔与第四连接电极44连接。
(16)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的第一载板10A，沉积第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化处理，在第二绝缘层12上形成第二导电层图案，如图7所示。
在示例性实施方式中，第二导电层图案可以至少包括第一极板61，第一极板61通过第三过孔K3与第四连接电极44连接，第一极板61可以作为滤波电容的一个极板(下极板)。
在示例性实施方式中，形成第二导电层图案也可以采用剥离工艺。
(17)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成前述图案的第一载板10A，沉积第三绝缘薄膜，采用图 案化工艺对第三绝缘薄膜进行图案化处理，形成覆盖第二导电层图案的第三绝缘层13图案，如图8所示。
在示例性实施方式中，第三绝缘层13上形成有第四过孔K4、第五过孔K5和第六过孔K6。
在示例性实施方式中，第四过孔K4在第一衬底上的正投影可以位于第四连接电极44在第一衬底上的正投影的范围之内，第四过孔K4内的第三绝缘薄膜和第二绝缘薄膜被去掉，暴露出第四连接电极44的表面，第四过孔K4被配置为使后续形成的第二连接电极通过该过孔与第四连接电极44连接。
在示例性实施方式中，第五过孔K5在第一衬底上的正投影可以位于第一焊盘电极3在第一衬底上的正投影的范围之内，第五过孔K5内的第三绝缘薄膜和第二绝缘薄膜被去掉，暴露出第一焊盘电极31的表面，第五过孔K5被配置为使后续形成的第一连接电极通过该过孔与第一焊盘电极31连接。
在示例性实施方式中，第六过孔K6在第一衬底上的正投影可以位于第二焊盘电极32在第一衬底上的正投影的范围之内，第六过孔K6内的第三绝缘薄膜和第二绝缘薄膜被去掉，暴露出第二焊盘电极32的表面，第六过孔K6被配置为使后续形成的第二极板通过该过孔与第二焊盘电极32连接。
(18)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的第一载板10A，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化处理，在第三绝缘层13上形成第三导电层图案，如图9所示。
在示例性实施方式中，第三导电层图案可以至少包括第一连接电极41、第二连接电极42和第二极板62。
在示例性实施方式中，第一连接电极41在第一衬底10上的正投影与第一焊盘电极31在第一衬底10上的正投影至少部分交叠，第一连接电极41通过第五过孔K5与第一焊盘电极31连接，第一连接电极41被配置为与连接基板中的第一凸点结构键合连接。
在示例性实施方式中，第二连接电极42在第一衬底10上的正投影与第四连接电极44在第一衬底10上的正投影至少部分交叠，第二连接电极42 通过第四过孔K4与第四连接电极44连接，第二连接电极42被配置为与连接基板中的第一凸点结构键合连接。
在示例性实施方式中，第二极板62在第一衬底10上的正投影与第一极板61和第二焊盘电极32在第一衬底10上的正投影至少部分交叠，第二极板62通过第六过孔K6与第二焊盘电极32连接，第二极板62可以作为滤波电容的另一个极板(上极板)，第一极板61和第二极板62构成平面薄膜电容结构的滤波电容。
在示例性实施方式中，形成第三导电层图案也可以采用剥离工艺。
在示例性实施方式中，形成第三导电层图案后，可以采用化学机械抛光方式对第一连接电极41和第二连接电极42远离第一衬底一侧的表面进行抛光，使得第一连接电极41和第二连接电极42的表面平齐，且第一连接电极41和第二连接电极42远离第一衬底一侧的表面的表面粗糙度可以小于或等于1nm。
(19)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的第一载板10A，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化处理，形成覆盖第三导电层图案的第四绝缘层14图案，如图10所示。
在示例性实施方式中，第四绝缘层14上形成有两个第一键合过孔V1。
在示例性实施方式中，一个第一键合过孔V1在第一衬底10上的正投影可以位于第一连接电极41在第一衬底10上的正投影的范围之内，该第一键合过孔V1内的第四绝缘薄膜被去掉，暴露出第一连接电极41的表面，该第一键合过孔V1被配置为使连接基板中的一个第一凸点结构通过该键合过孔与第一连接电极41连接。
在示例性实施方式中，另一个第一键合过孔V1在第一衬底10上的正投影可以位于第二连接电极42在第一衬底10上的正投影的范围之内，该第一键合过孔V1内的第四绝缘薄膜被去掉，暴露出第二连接电极42的表面，该第一键合过孔V1被配置为使连接基板中的另一个第一凸点结构通过该过孔与第二连接电极42连接。
至此，制备完成设置在第一载板上的第一基板。在示例性实施方式中，第一基板可以包括设置在第一牺牲层10B上的第一衬底10、设置在第一衬底10上的第一绝缘层11、设置在第一绝缘层11上的第一导电层、设置在第一导电层上的第二绝缘层12、设置在第二绝缘层12上的第二导电层、设置在第二导电层上的第三绝缘层13、设置在第三绝缘层13上的第三导电层、以及设置在第三导电层上的第四绝缘层。第一导电层可以至少包括第一焊盘电极31、第二焊盘电极32和第四连接电极44，第二导电层可以至少包括第一极板61，第三导电层可以至少包括第一连接电极41、第二连接电极42和第二极板62。
在示例性实施方式中，第一基板还可以包括设置在第一衬底10远离第一绝缘层11一侧的焊盘保护层90以及设置在焊盘保护层90远离第一衬底10一侧的焊盘导电层，焊盘导电层可以至少包括第一焊盘21和第二焊盘22。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层可以称为第一阻挡层，第二绝缘层可以称为第二(PVX)钝化层，第三绝缘层可以称为第三钝化层，第四绝缘层可以称为第四钝化层。
第二部分、第二基板的制备
在示例性实施方式中，第二基板的制备过程可以包括如下操作。
(21)制备第二衬底图案。在示例性实施方式中，制备第二衬底图案可以包括：提供第二载板20A，先在第二载板20A上形成第二牺牲层20B，然后在第二牺牲层20B上涂覆第二衬底薄膜，固化成膜后，沉积第五绝缘薄膜，形成第二衬底20，以及设置在第二衬底20远离第二载板20A一侧的第五绝缘层15，如图11所示。
在示例性实施方式中，第二衬底的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)等材料。
在示例性实施方式中，第二载板的材料可以采用玻璃，第二牺牲层的材料可以采用有机聚合物材料，可以采用涂覆粘性液体后固化成膜的方式形成， 第二牺牲层被配置为在后续激光剥离工艺中使得第二基板与第二载板分离。
(22)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的第二载板20A，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化处理，在第五绝缘层15上形成第四导电层图案，如图12所示。
在示例性实施方式中，第四导电层图案可以至少包括第三连接电极43，第三连接电极43被配置为与连接基板中的第二凸点结构连接。
在示例性实施方式中，形成第四导电层图案也可以采用剥离工艺。
在示例性实施方式中，形成第四导电层图案后，可以采用化学机械抛光方式对第三连接电极43远离第二衬底一侧的表面进行抛光，使得第三连接电极43远离第二衬底一侧的表面的表面粗糙度可以小于或等于1nm。
(23)形成第六绝缘层图案。在示例性实施方式中，形成第六绝缘层图案可以包括：在形成前述图案的第二载板20A，沉积第六绝缘薄膜，采用图案化工艺对第六绝缘薄膜进行图案化处理，形成覆盖第四导电层图案的第六绝缘层16图案，如图13所示。
在示例性实施方式中，第六绝缘层16上形成有两个第二键合过孔V2。
在示例性实施方式中，两个第二键合过孔V2在第二衬底20上的正投影可以位于第三连接电极43在第二衬底20上的正投影的范围之内，两个第二键合过孔V2内的第六绝缘薄膜被去掉，分别暴露出第三连接电极43的表面，两个第二键合过孔V2被配置为使连接基板中的两个第二凸点结构通过该键合过孔与第三连接电极43连接。
至此，制备完成设置在第二载板上的第二基板。在示例性实施方式中，第二基板可以包括设置在第二牺牲层20B上的第二衬底20、设置在第二衬底20上的第五绝缘层15、设置在第五绝缘层15上的第四导电层、以及设置在第四导电层上的第六绝缘层16，第四导电层可以至少包括第三连接电极43。
第三部分、连接基板的制备
在示例性实施方式中，连接基板的制备过程可以包括如下操作。
(31)制备连接衬底。在示例性实施方式中，制备连接衬底可以包括：提供连接衬底30，在连接衬底30上形成至少二个通孔80，形成TGV结构的连接衬底30，如图14所示。
在示例性实施方式中，至少二个通孔80的结构可以基本上相同，均为贯通连接衬底30的通孔结构。在平行于连接衬底的平面上，通孔80的形状可以为圆形或者椭圆形，在垂直于连接基板的平面上，通孔80的截面形状可以为柱状、漏斗状或者沙漏状等，通孔80被配置为容置后续形成的导电柱。
在示例性实施方式中，连接衬底30可以包括相互背离的第一侧表面30A和第二侧表面30B。在示例性实施方式中，可以采用图案化工艺或者激光打孔工艺形成至少一个通孔。
在示例性实施方式中，以沙漏状通孔为例，采用图案化工艺在连接衬底上形成至少一个通孔可以包括：先在连接衬底的第一侧表面30A上涂覆一层光刻胶，对光刻胶进行曝光和显影后形成曝光区和未曝光区，曝光区的光刻胶被去除，暴露出连接衬底的第一侧表面30A，未曝光区仍覆盖有光刻胶。采用干刻工艺或者湿刻工艺刻蚀曝光区的连接衬底，在连接衬底的该侧表面上形成多个第一盲孔，第一盲孔的截面形状可以为梯形状。然后，在连接衬底的第二侧表面30B上涂覆一层光刻胶，对光刻胶进行曝光和显影后形成曝光区和未曝光区，曝光区的光刻胶被去除，暴露出连接衬底的第二侧表面30B，未曝光区仍覆盖有光刻胶。采用干刻工艺或者湿刻工艺刻蚀曝光区的连接衬底，在连接衬底的该侧表面上形成多个第二盲孔，第二盲孔的截面形状可以为梯形状，第二盲孔和第一盲孔连通，形成沙漏状的通孔。
在示例性实施方式中，以沙漏状通孔为例，采用激光打孔工艺在连接衬底上形成至少一个通孔可以包括：先使用激光器以激光束垂直入射的方式照射到连接衬底的第一侧表面30A，在连接衬底的该侧表面形成倒圆台状的第一盲孔，然后使用激光器以激光束垂直入射的方式照射到连接衬底的第二侧表面30B，在连接衬底的该侧表面形成倒圆台状的第二盲孔，第二盲孔和第一盲孔连通，形成沙漏状的通孔。在激光束与连接衬底相互作用时，能量较高的激光光子将连接衬底中的原子电离化并抛射出连接衬底，随时间增加，孔逐渐加深，直至形成第一盲孔和第二盲孔。
在示例性实施方式中，激光器的类型可选连续激光器、脉冲激光器等，激光波长可以约为532nm、355nm、266nm、248nm、197nm等，激光的脉冲宽度可选1fs至100fs、1ps至100ps、1ns至100ns等。
在示例性实施方式中，激光打孔的方式可以包括但不限于如下两种。第一种方式，当激光光斑直径较大时，激光束和连接衬底的相对位置固定，依靠高能量直接把连接衬底打到预设深度。第二种方式，当激光光斑直径较小时，激光束在连接衬底上画圈扫描，画圈的半径逐渐减小，光斑聚焦点不断变化，聚焦焦点深度也在不断变化，把连接衬底打到预设深度。
在示例性实施方式中，连接衬底的材料可以采用玻璃，例如氧化硅、二氧化硅或者光敏玻璃等。
(32)制备导电柱图案。在示例性实施方式中，制备导电柱图案可以包括：在形成前述图案的连接衬底上，通过填充工艺在多个通孔80内形成多个导电柱图案，如图15所示。
在示例性实施方式中，导电柱图案可以至少包括第一导电柱71和第二导电柱72。第一导电柱71和第二导电柱72可以分别设置在两个通孔80内。
在示例性实施方式中，第一导电柱71和第二导电柱72均可以包括导电层和位于导电层外侧的种子层，种子层与通孔80的内壁连接。
在示例性实施方式中，通过填充工艺在多个通孔80内形成多个导电柱图案可以包括：
先采用物理气相沉积或者化学气相沉积在通孔的内壁形成种子层，然后采用电镀工艺在种子层内形成导电层。
在示例性实施方式中，种子层的材料可以采用铜(Cu)、铝(Al)、钼(Mo)、银(Ag)中的至少一种，种子层的厚度可以约为0.01μm至0.05μm。例如，种子层的厚度可以约为0.03μm，
在示例性实施方式中，为了增加种子层与通孔内壁的附着力，在形成种子层之前，可以在通孔内形成一层辅助金属层，辅助金属层的材料包括但不限于镍(Ni)、钼(Mo)合金、钛(Ti)合金中的至少一种。
在示例性实施方式中，导电层的材料可以采用铜(Cu)，导电层的厚度可以约为0.2μm至0.5μm。导电层可以采用Cu电镀或者Cu芯焊锡球填充等方法，在通孔进行铜的填充。例如，将连接衬底放入电镀机台载具上，压上加电焊盘，放入具有电解液的电镀槽中，加电使电镀液在衬底基板表面持续快速流动，电镀液中的阳离子在通孔内壁上获得电子，成为原子淀积在内壁上。随时间增加，通孔内壁上铜的厚度逐渐增加，甚至可以将通孔完全填实。
(33)形成第一凸点结构层图案。在示例性实施方式中，形成第一凸点结构层图案可以包括：在形成前述图案的连接衬底上，通过图案化工艺在连接衬底的第一侧表面上形成第一凸点结构层图案，如图16所示。
在示例性实施方式中，第一凸点结构层可以至少包括两个第一凸点结构51，一个第一凸点结构51与第一导电柱71位于第一侧表面的端部连接，另一个第一凸点结构51与第二导电柱72位于第一侧表面的端部连接。
在示例性实施方式中，第一凸点结构51在连接衬底上的正投影包含第一导电柱71和第二导电柱72在连接衬底上的正投影，即第一凸点结构51完全覆盖第一导电柱71位于第一侧表面的端部和完全覆盖第二导电柱72位于第一侧表面的端部。
在示例性实施方式中，第一凸点结构51可以包括叠设的第一连接层51-1和第一凸点(Bump)层51-2，第一连接层51-1可以设置在连接衬底30上，分别与通孔中的第一导电柱71和第二导电柱72的端部连接，第一凸点层51-2可以设置在第一连接层51-1远离连接衬底30的一侧，第一连接层51-1可以作为互联的键合层，将第一凸点层51-2和第一导电柱71和第二导电柱72粘贴在一起，并阻挡第一凸点层中原子扩散至导电柱，第一凸点层51-2被配置为与第一基板中的第一连接电极和第二连接电极键合连接。在示例性实施方式中，第一连接层可以称为凸点下金属(Under Ball Metal，简称UBM)层。
在示例性实施方式中，第一连接层的材料可以采用多层复合结构，如钛(Ti)和铜(Cu)的复合层Ti/Cu、钼钛镍合金(MTD)和铜(Cu)的复合层MTD/Cu、钼钛镍合金(MTD)、铜镍合金(CuNi)和铜(Cu)的复合层MTD/CuNi/Cu等。
在示例性实施方式中，第一凸点层的材料可以采用锡(Sn)或者铟锡合金(Sn-In)等，不仅具有良好的伸展性，而且具有防腐蚀的性能。
在示例性实施方式中，通过图案化工艺在连接衬底30的第一侧表面上形成第一凸点结构层图案可以包括：先在连接衬底30的第一侧表面沉积第一连接薄膜，然后在第一连接薄膜上涂覆一层光刻胶，通过曝光显影形成光刻胶图案，光刻胶图案包括曝光区和未曝光区，曝光区的光刻胶被去掉，暴露出第一连接薄膜，未曝光区的光刻胶覆盖第一连接薄膜。通过电镀方式在曝光区形成第一凸点薄膜后，剥离光刻胶图案以及光刻胶上的第一凸点薄膜，并利用未剥离的第一凸点薄膜作为遮挡刻蚀第一连接薄膜，在连接衬底30的第一侧表面上形成两个第一凸点结构51，第一凸点结构51包括叠设的第一连接层51-1和第一凸点层51-2。
(34)形成第二凸点结构层图案。在示例性实施方式中，形成第二凸点结构层图案可以包括：在形成前述图案的连接衬底上，通过图案化工艺在连接衬底的第二侧表面上形成第二凸点结构层图案，如图17所示。
在示例性实施方式中，第二凸点结构层可以至少包括两个第二凸点结构52，一个第二凸点结构52与第一导电柱71位于第二侧表面的端部连接，另一个第二凸点结构52与第二导电柱72位于第二侧表面的端部连接。
在示例性实施方式中，第二凸点结构52在连接衬底上的正投影包含第一导电柱71和第二导电柱72在连接衬底上的正投影，即第二凸点结构52完全覆盖第一导电柱71位于第二侧表面的端部和完全覆盖第二导电柱72位于第二侧表面的端部。
在示例性实施方式中，第二凸点结构52可以包括叠设的第二连接层52-1和第二凸点层52-2，第二连接层52-1可以设置在连接衬底30上，分别与通孔中的第一导电柱71和第二导电柱72的端部连接，第二凸点层52-2可以设置在第二连接层52-1远离连接衬底30的一侧，第二连接层52-1可以作为互联的键合层，可以称为UBM层。
第二连接层的材料与第一连接层的材料可以基本上相同，第二凸点层的材料与第一凸点层的材料可以基本上相同，形成第二凸点结构层的制备方式 与形成第一凸点结构层的制备方式可以基本上相同。
至此，制备完成连接基板。连接基板可以包括连接衬底30、在厚度方向贯通连接衬底30的第一导电柱71和第二导电柱72、设置在连接衬底30第一侧表面上的至少两个第一凸点结构51以及设置在连接衬底30第二侧表面的至少两个第二凸点结构52。
第四部分、键合处理
在示例性实施方式中，键合处理可以包括如下操作：将制备完成的第一基板100设置在连接基板300中第一侧表面的一侧，将制备完成的第二基板200翻转后设置在连接基板300中第二侧表面的一侧，如图18所示。
随后，第一基板100、第二基板200和连接基板300对位贴合后，采用金属与金属扩散键合方式将第一基板100、连接基板300和第二基板200压合再一起，将连接基板300中的一个第一凸点结构51与第一基板100中的第一连接电极41、连接基板300中的另一个第一凸点结构51与第一基板100中的第二连接电极42、连接基板300中的两个第二凸点结构52与第二基板200中的第三连接电极43键合连接，形成第一基板100、连接基板300和第二基板200的电连接结构，如图19所示。
在示例性实施方式中，键合过程中，键合压力可以约为40kN至100kN，键合温度可以约为350℃至450℃。
在示例性实施方式中，通过键合处理，使得第一基板100中的第一连接电极41和第二基板200中的第三连接电极43之间通过连接基板300中的第一凸点结构51、第一导电柱71和第二凸点结构52实现了相互连接，使得第一基板100中的第二连接电极42和第二基板200中的第三连接电极43之间通过连接基板300中的第一凸点结构51、第二导电柱72和第二凸点结构52实现了相互连接，依次连接的第一连接电极41、第一导电柱71、第三连接电极43、第二导电柱72和第二连接电极42构成三维螺旋电感结构的滤波电感。
在示例性实施方式中，由于第二连接电极42通过过孔与第四连接电极44连接，而第一极板61也通过过孔与第四连接电极44连接，因而实现了滤波电感和滤波电容之间通过第四连接电极44实现了相互连接。
最后，通过激光剥离工艺剥离掉第一基板100远离连接基板300一侧的第一载板10A和第一牺牲层10B，剥离掉第二基底200远离连接基板300一侧的第二载板20A和第二牺牲层20B，形成本公开示例性实施例的滤波器，如图1所示。
在示例性实施方式中，第一牺牲层和第二牺牲层遇到光照时会分解的较彻底，因而便于实现第一基板与第一载板、第二基底与第二载板的分离。
至此，制备完成本公开示例性实施例滤波器。
通过本公开示例性实施例滤波器的结构和制备过程可以看出，本公开通过分别制备第一基板、第二基板和连接基板，然后利用键合方式在连接基板的两侧键合连接第一基板和第二基板，不仅实现了将三维螺旋电感结构的滤波电感和平行板电容结构的滤波电容集成在一个芯片上，所集成的滤波器芯片集成度高，减小了滤波器的尺寸，而且避免了连接基板因高温退火或者高温沉积薄膜等工艺导致的导电柱凸出，消除了连接基板中导电柱与第一基板和第二基板中连接电极断开连接的问题。本公开通过在连接基板上设置凸点结构，导电柱通过凸点结构与连接电极连接，进一步提高了连接基板中导电柱与第一基板和第二基板中连接电极的连接可靠性，最大限度地提高了产品良率。本公开连接基板采用玻璃衬底，不仅可以降低滤波器损耗，而且可以降低生产成本。本公开的制备工艺利用现有成熟的制备设备即可实现，对现有工艺改进较小，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开示例性实施例滤波器的结构及其制备过程仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺，本公开在此不做限定。例如，在示例性实施方式中，连接基板300上可以设置有在厚度方向上贯通连接衬底30的n个通孔，n个导电柱分别设置在n个通孔内，n个导电柱可以沿着设定方向规则排布。第一基板100上可以设置有一个第一连接电极41和n/2个第二连接电极42，第二基板200上可以设置有n/2个第三连接电极43，第一连接电极41可以连接n个导电柱中的第1导电柱，第(n/2)个第二连接电极42可以连接n个导电柱中的第n导电柱，其它的多个第二连接电极42可以分别连接n个导电柱中的第 i+1导电柱和第i+2导电柱，多个第三连接电极43可以分别连接n个导电柱中的第i导电柱和第i+1导电柱，n个导电柱、第一连接电极41、n/2个第二连接电极42和n/2个第三连接电极43构成三维螺旋电感结构的第一滤波电感，n为大于或等于2的偶数，i为大于或等于1、小于或等于n-2的奇数。第一连接电极41可以与谐振器的第一焊盘连接，第(n/2)个第二连接电极42可以与滤波电容的第一极板连接，滤波电容的第二极板可以与谐振器的第二焊盘连接。
本公开示例性实施例还提供了一种滤波器的制备方法，以制备前述实施例的滤波器。在示例性实施方式中，滤波器的制备方法可以包括：
分别制备第一基板、第二基板和连接基板，所述第一基板上设置有至少一个第一基板电极，所述第二基板上设置有至少一个第二基板电极，所述连接基板至少包括连接衬底和贯通所述连接衬底的至少一个导电柱，所述导电柱靠近所述第一基板的一端连接有第一凸点结构，所述导电柱靠近所述第二基板的一端连接有第二凸点结构；
将所述第一基板和第二基板相对设置，且所述连接基板设置在所述第一基板和第二基板之间，通过键合方式将所述第一凸点结构与所述第一基板电极连接、所述第二凸点结构与所述第二基板电极连接起来。
在示例性实施方式中，制备连接基板可以包括：
提供连接衬底，在所述连接衬底上形成多个通孔，所述连接衬底的材料包括玻璃；
在多个通孔内形成多个导电柱；
在所述连接衬底的第一侧表面形成多个第一凸点结构，在所述连接衬底的第二侧表面形成多个第二凸点结构；所述第一凸点结构包括设置在所述连接衬底的第一侧表面上的第一连接层和设置在所述第一连接层远离所述连接衬底一侧的第一凸点层，多个第一连接层与多个导电柱位于所述第一侧表面的端部对应连接；所述第二凸点结构包括设置在所述连接衬底的第二侧表面上的第二连接层和设置在所述第二连接层远离所述连接衬底一侧的第二凸点层，多个第二连接层与多个导电柱位于所述第二侧表面的端部对应连接。
在示例性实施方式中，在所述连接衬底的第一侧表面形成多个第一凸点结构，在所述连接衬底的第二侧表面形成多个第二凸点结构，可以包括：
在所述连接衬底的第一侧表面沉积第一连接薄膜，在第一连接薄膜上涂覆一层光刻胶，通过曝光显影形成光刻胶图案，光刻胶图案包括曝光区和未曝光区，曝光区的光刻胶被去掉，暴露出第一连接薄膜，未曝光区的光刻胶覆盖第一连接薄膜；在曝光区形成第一凸点薄膜后，剥离光刻胶图案以及光刻胶上的第一凸点薄膜，并利用未剥离的第一凸点薄膜作为遮挡刻蚀第一连接薄膜，在所述连接衬底的第一侧表面上形成多个第一凸点结构，所述第一凸点结构包括叠设的第一连接层和第一凸点层；
在所述连接衬底的第二侧表面沉积第二连接薄膜，在第二连接薄膜上涂覆一层光刻胶，通过曝光显影形成光刻胶图案，光刻胶图案包括曝光区和未曝光区，曝光区的光刻胶被去掉，暴露出第二连接薄膜，未曝光区的光刻胶覆盖第二连接薄膜；在曝光区形成第二凸点薄膜后，剥离光刻胶图案以及光刻胶上的第二凸点薄膜，并利用未剥离的第二凸点薄膜作为遮挡刻蚀第二连接薄膜，在所述连接衬底的第二侧表面上形成多个第二凸点结构，所述第二凸点结构包括叠设的第二连接层和第二凸点层。
本公开还提供了一种电子设备，包括前述实施例的滤波器。电子设备可以用于无线通信装置中的射频前端装置，如射频滤波器等。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种滤波器，包括相对设置的第一基板、第二基板以及设置在所述第一基板和第二基板之间的连接基板，所述第一基板上设置有至少一个第一基板电极，所述第二基板上设置有至少一个第二基板电极，所述连接基板至少包括连接衬底和在厚度方向贯通所述连接衬底的至少一个导电柱，所述导电柱靠近所述第一基板的一端设置有第一凸点结构，所述导电柱靠近所述第二基板的一端设置有第二凸点结构，所述第一凸点结构与所述第一基板电极、所述第二凸点结构与所述第二基板电极通过键合方式连接。
  2. 根据权利要求1所述的滤波器，其中，所述连接衬底包括靠近所述第一基板的第一侧表面和靠近所述第二基板的第二侧表面，所述第一凸点结构设置在所述连接衬底的第一侧表面上，且与所述导电柱靠近所述第一基板的一端连接，所述第二凸点结构设置在所述连接衬底的第二侧表面上，且与所述导电柱靠近所述第二基板的一端连接。
  3. 根据权利要求1所述的滤波器，其中，所述第一凸点结构在所述连接衬底上的正投影包含所述导电柱在所述连接衬底上的正投影，所述第二凸点结构在所述连接衬底上的正投影包含所述导电柱在所述连接衬底上的正投影。
  4. 根据权利要求1所述的滤波器，其中，所述第一凸点结构包括设置在所述连接衬底的第一侧表面上的第一连接层和设置在所述第一连接层远离所述连接衬底一侧的第一凸点层，所述第一连接层与所述导电柱靠近所述第一基板的一端连接，所述第一凸点层与所述第一基板电极通过键合方式连接；所述第二凸点结构包括设置在所述连接衬底的第二侧表面上的第二连接层和设置在所述第二连接层远离所述连接衬底一侧的第二凸点层，所述第二连接层与所述导电柱靠近所述第二基板的一端连接，所述第二凸点层与所述第二基板电极通过键合方式连接。
  5. 根据权利要求4所述的滤波器，其中，所述第一连接层和第二连接层的材料包括如下任意一种：钛和铜的复合层，钼钛镍合金和铜的复合层，钼钛镍合金、铜镍合金和铜的复合层。
  6. 根据权利要求4所述的滤波器，其中，所述第一凸点层和第二凸点层 的材料包括如下任意一种：锡，铟锡合金。
  7. 根据权利要求1至6任一项所述的滤波器，其中，所述导电柱至少包括第一导电柱和第二导电柱，所述第一基板电极至少包括第一连接电极和第二连接电极，所述第二基板电极至少包括第三连接电极，所述第一连接电极与所述第一导电柱连接，所述第二连接电极与所述第二导电柱连接，所述第三连接电极分别与所述第一导电柱和第二导电柱连接，所述第一导电柱、第二导电柱、第一连接电极、第二连接电极和第三连接电极构成三维螺旋电感结构的滤波电感。
  8. 根据权利要求7所述的滤波器，其中，所述第一基板还设置有滤波电容，所述滤波电容与所述滤波电感连接。
  9. 根据权利要求8所述的滤波器，其中，所述第一基板至少包括第一衬底、设置在所述第一衬底靠近所述连接基板一侧的第一导电层、设置在所述第一导电层靠近所述连接基板一侧的第二导电层、设置在所述第二导电层靠近所述连接基板一侧的第三导电层，所述第一连接电极和第二连接电极设置在所述第三导电层中。
  10. 根据权利要求9所述的滤波器，其中，所述滤波电容包括第一极板和第二极板，所述第一极板在所述第一衬底上的正投影与所述第二极板在所述第一衬底上的正投影至少部分交叠，所述第一极板设置在所述第二导电层中，所述第二极板设置在所述第三导电层中。
  11. 根据权利要求10所述的滤波器，其中，所述第一导电层至少包括第一焊盘电极、第二焊盘电极和第四连接电极，所述第一连接电极通过过孔与所述第一焊盘电极连接，所述第二连接电极和所述第一极板分别通过过孔与所述第四连接电极连接，所述第二极板通过过孔与所述第二焊盘电极连接。
  12. 根据权利要求11所述的滤波器，其中，所述第一基板还包括焊盘导电层和焊盘保护层，所述焊盘保护层设置在所述第一衬底远离所述连接基板的一侧，所述焊盘导电层设置在所述焊盘保护层远离所述连接基板的一侧，所述焊盘导电层至少包括第一焊盘和第二焊盘，所述第一焊盘电极通过过孔与所述第一焊盘连接，所述第二焊盘电极通过过孔与所述第二焊盘连接。
  13. 根据权利要求12所述的滤波器，其中，所述焊盘导电层远离所述连接基板一侧的表面与所述第一衬底远离所述连接基板一侧的表面平齐。
  14. 根据权利要求12所述的滤波器，其中，所述焊盘保护层远离所述连接基板一侧的表面与所述第一衬底远离所述连接基板一侧的表面平齐。
  15. 根据权利要求7所述的滤波器，其中，所述导电柱包括n个导电柱，所述第一基板电极包括一个第一连接电极和n/2个第二连接电极，所述第二基板电极包括n/2个第三连接电极，所述第一连接电极41与n个导电柱中的第1导电柱连接，第(n/2)个第二连接电极与n个导电柱中的第n导电柱连接，其它的第二连接电极分别连接n个导电柱中的第i+1导电柱和第i+2导电柱，多个第三连接电极分别连接n个导电柱中的第i导电柱和第i+1导电柱，n个导电柱、第一连接电极、n/2个第二连接电极和n/2个第三连接电极构成三维螺旋电感结构的第一滤波电感，n为大于或等于2的偶数，i为大于或等于1、小于或等于n-2的奇数。
  16. 根据权利要求15所述的滤波器，其中，所述第一基板还设置有滤波电容、第一焊盘和第二焊盘，所述第一连接电极与所述第一焊盘连接，第(n/2)个第二连接电极与所述滤波电容的第一极板连接，所述滤波电容的第二极板与所述第二焊盘连接。
  17. 根据权利要求7所述的滤波器，其中，所述第二基板至少包括第二衬底、设置在所述第二衬底靠近所述连接基板一侧的第四导电层，所述第三连接电极设置在所述第四导电层中。
  18. 一种电子设备，包括权利要求1至17任一项所述的滤波器。
  19. 一种滤波器的制备方法，包括：
    分别制备第一基板、第二基板和连接基板，所述第一基板上设置有至少一个第一基板电极，所述第二基板上设置有至少一个第二基板电极，所述连接基板至少包括连接衬底和贯通所述连接衬底的至少一个导电柱，所述导电柱靠近所述第一基板的一端连接有第一凸点结构，所述导电柱靠近所述第二基板的一端连接有第二凸点结构；
    将所述第一基板和第二基板相对设置，且所述连接基板设置在所述第一 基板和第二基板之间，通过键合方式将所述第一凸点结构与所述第一基板电极连接、所述第二凸点结构与所述第二基板电极连接起来。
  20. 根据权利要求19所述的滤波器，其中，制备连接基板包括：
    提供连接衬底，在所述连接衬底上形成多个通孔，所述连接衬底的材料包括玻璃；
    在多个通孔内形成多个导电柱；
    在所述连接衬底的第一侧表面形成多个第一凸点结构，在所述连接衬底的第二侧表面形成多个第二凸点结构；所述第一凸点结构包括设置在所述连接衬底的第一侧表面上的第一连接层和设置在所述第一连接层远离所述连接衬底一侧的第一凸点层，多个第一连接层与多个导电柱位于所述第一侧表面的端部对应连接；所述第二凸点结构包括设置在所述连接衬底的第二侧表面上的第二连接层和设置在所述第二连接层远离所述连接衬底一侧的第二凸点层，多个第二连接层与多个导电柱位于所述第二侧表面的端部对应连接。
PCT/CN2022/114811 2022-08-25 2022-08-25 滤波器及其制备方法、电子设备 WO2024040517A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/114811 WO2024040517A1 (zh) 2022-08-25 2022-08-25 滤波器及其制备方法、电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/114811 WO2024040517A1 (zh) 2022-08-25 2022-08-25 滤波器及其制备方法、电子设备

Publications (1)

Publication Number Publication Date
WO2024040517A1 true WO2024040517A1 (zh) 2024-02-29

Family

ID=90012046

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/114811 WO2024040517A1 (zh) 2022-08-25 2022-08-25 滤波器及其制备方法、电子设备

Country Status (1)

Country Link
WO (1) WO2024040517A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070268105A1 (en) * 2006-05-19 2007-11-22 Freescale Semiconductor, Inc. Electrical component having an inductor and a method of formation
CN101322201A (zh) * 2005-10-05 2008-12-10 Nxp股份有限公司 用于集成电路的多层电感元件
US20100225434A1 (en) * 2009-03-03 2010-09-09 Freescale Semiconductor, Inc. Stacked device assembly with integrated coil and method of forming same
US20150371763A1 (en) * 2014-06-20 2015-12-24 International Business Machines Corporation Nested-helical transformer
CN108476014A (zh) * 2015-12-28 2018-08-31 高通股份有限公司 使用与3d贯穿玻璃通孔滤波器集成的2d无源玻璃滤波器的多路复用器设计
CN114070222A (zh) * 2021-11-18 2022-02-18 京东方科技集团股份有限公司 一种滤波器及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101322201A (zh) * 2005-10-05 2008-12-10 Nxp股份有限公司 用于集成电路的多层电感元件
US20070268105A1 (en) * 2006-05-19 2007-11-22 Freescale Semiconductor, Inc. Electrical component having an inductor and a method of formation
US20100225434A1 (en) * 2009-03-03 2010-09-09 Freescale Semiconductor, Inc. Stacked device assembly with integrated coil and method of forming same
US20150371763A1 (en) * 2014-06-20 2015-12-24 International Business Machines Corporation Nested-helical transformer
CN108476014A (zh) * 2015-12-28 2018-08-31 高通股份有限公司 使用与3d贯穿玻璃通孔滤波器集成的2d无源玻璃滤波器的多路复用器设计
CN114070222A (zh) * 2021-11-18 2022-02-18 京东方科技集团股份有限公司 一种滤波器及其制备方法

Similar Documents

Publication Publication Date Title
US11894306B2 (en) Chip package
CN113410175B (zh) 一种tsv导电通孔结构制备方法
CN114070222A (zh) 一种滤波器及其制备方法
CN108511327A (zh) 一种无需临时键合的超薄硅转接板的制作方法
US20200411456A1 (en) Fan-out antenna package structure and packaging method
US11289435B2 (en) Fan-out antenna packaging structure and packaging method
WO2023020351A1 (zh) 传感器件及其制备方法
CN114520222A (zh) 无源滤波器及其制备方法
CN114070220A (zh) 滤波器及其制备方法、电子设备
WO2024040517A1 (zh) 滤波器及其制备方法、电子设备
CN216290855U (zh) 可调滤波器
WO2022134847A1 (zh) 集成有无源器件的基板及其制备方法
TW201712812A (zh) 玻璃基板封裝及其製造方法
US11574817B2 (en) Fabricating an interconnection using a sacrificial layer
WO2022007445A1 (zh) 三维电容制备方法
WO2022222405A1 (zh) 可调滤波器及其制备方法
WO2024044871A1 (zh) 滤波器及其制备方法、电子设备
WO2022222131A1 (zh) 集成有无源器件的基板及其制备方法
WO2022222133A1 (zh) 集成有无源器件的基板及其制备方法
WO2023245593A1 (zh) 滤波器及其制备方法
CN113009625B (zh) 一种集成光波导的多层lcp光传输模块的制造方法
WO2022222124A1 (zh) 集成有无源器件的基板及其制备方法
WO2024082210A1 (zh) 电感及其制备方法、滤波器、电子设备
WO2023070496A1 (zh) 集成有无源器件的基板及其制备方法
Lei et al. The Fabrication of Three-layer Silicon Stacked Antenna

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22956064

Country of ref document: EP

Kind code of ref document: A1