WO2023070496A1 - 集成有无源器件的基板及其制备方法 - Google Patents

集成有无源器件的基板及其制备方法 Download PDF

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Publication number
WO2023070496A1
WO2023070496A1 PCT/CN2021/127289 CN2021127289W WO2023070496A1 WO 2023070496 A1 WO2023070496 A1 WO 2023070496A1 CN 2021127289 W CN2021127289 W CN 2021127289W WO 2023070496 A1 WO2023070496 A1 WO 2023070496A1
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Prior art keywords
layer
substrate
interlayer dielectric
open
base substrate
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PCT/CN2021/127289
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English (en)
French (fr)
Inventor
刘英伟
王珂
曹占锋
姚琪
袁广才
肖月磊
李月
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京东方科技集团股份有限公司
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Priority to US18/271,117 priority Critical patent/US20240079354A1/en
Priority to PCT/CN2021/127289 priority patent/WO2023070496A1/zh
Priority to CN202180003179.4A priority patent/CN116368948A/zh
Publication of WO2023070496A1 publication Critical patent/WO2023070496A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/305—Material
    • H01L2224/30505—Layer connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3051—Function
    • H01L2224/30515—Layer connectors having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1205—Capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1206—Inductor

Definitions

  • the disclosure belongs to the technical field of radio frequency devices, and in particular relates to a substrate integrated with passive devices and a preparation method thereof.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a substrate integrated with passive devices and a preparation method thereof.
  • an embodiment of the present disclosure provides a substrate integrated with passive devices, which includes a base substrate and a passive device disposed on the base substrate, and the passive device includes at least an inductor; the inductor It includes a plurality of open-loop parts arranged in sequence along the direction away from the substrate and connected in sequence; wherein, an interlayer dielectric layer is arranged between the adjacently arranged open-loop parts, and the adjacently arranged open-loop parts Electrically connected through a first via hole penetrating through the interlayer dielectric layer; and orthographic projections of any two open loop portions on the base substrate are at least partially overlapped.
  • the interlayer dielectric layer includes a first passivation layer, a planarization layer, and a second passivation layer arranged in sequence along the direction away from the substrate;
  • the substrate includes N interlayer dielectric layers;
  • the Mth interlayer The planarization layer in the dielectric layer passes through the second passivation layer in the M-1th interlayer dielectric layer and the second via hole in the first passivation layer in the Mth interlayer dielectric layer, and the M-th 1
  • the planarization layer contacts in the interlayer dielectric layer; N ⁇ 2, 2 ⁇ M ⁇ N, and both M and N are integers.
  • the orthographic projections of at least part of the second via holes located on different layers on the base substrate at least partly overlap.
  • planarization layer in the Mth interlayer dielectric layer is in contact with the planarization layer in the M-1th interlayer dielectric layer through a plurality of second via holes.
  • the orthographic projections of at least part of the first via holes on the base substrate do not overlap.
  • the passive device further includes a capacitor, and the capacitor includes a first plate and a second plate arranged in sequence along the side away from the substrate; the first plate and the plurality of open loops One of the same layers in the department is set, and the material is the same.
  • the first electrode plate is arranged on the same layer as the first one of the plurality of open-loop portions arranged in a direction away from the substrate, and is directly electrically connected.
  • the thickness ratio of the second pole plate to the first pole plate is 1:100 ⁇ 1:30.
  • the substrate further includes a first connection portion, the first connection portion is electrically connected to the second plate, and the edge between the first connection portion and the plurality of open-loop portions is away from the substrate The last sibling setup in the substrate direction.
  • the substrate further includes a transfer portion, and the transfer portion is disposed on the same layer as any one or more of the plurality of open-loop portions located between the first and the last one.
  • an embodiment of the present disclosure provides a method for preparing a substrate integrated with passive devices, which includes: providing a base substrate, and forming passive devices on the base substrate, the passive devices including Inductance; the inductance includes a plurality of open-loop parts arranged in sequence along the direction away from the substrate and connected in sequence; wherein, the step of forming the inductance includes: sequentially forming a plurality of open-loop parts and covering on the substrate In the interlayer dielectric layer above the open-loop portion, the open-loop portions arranged adjacently are electrically connected through a first via hole penetrating through the interlayer dielectric layer; and any two open-loop portions are in the The orthographic projections on the base substrate at least partially overlap.
  • the step of forming the ring opening includes: forming a metal thin film on the base substrate as a seed layer; forming a sacrificial layer on the side of the seed layer away from the base substrate, and etching the sacrificial layer to form The groove portion corresponding to the open ring portion; electroplating the seed layer, so that the groove portion forms a metal material; removing the seed layer, and removing the metal material other than the groove portion through a patterning process, The open loop is formed.
  • the interlayer dielectric layer includes a first passivation layer, a planarization layer, and a second passivation layer arranged in sequence along a direction away from the substrate;
  • the substrate includes N interlayer dielectric layers;
  • the method further includes forming a second via hole penetrating through the second passivation layer in the M-1th interlayer dielectric layer and the first passivation layer in the Mth interlayer dielectric layer, so that the flatness in the Mth interlayer dielectric layer
  • the planarization layer is in contact with the planarization layer in the M-1th interlayer dielectric layer; N ⁇ 2, 2 ⁇ M ⁇ N, and both M and N are integers.
  • the passive device further includes a capacitor
  • the step of forming the capacitor includes: sequentially forming a first pole plate and a second pole plate along a side away from the base substrate; One of the plurality of open loops is formed in the same patterning process.
  • the first electrode plate is formed in the same patterning process as the first one of the plurality of open-loop portions arranged in a direction away from the substrate.
  • FIG. 1 is a perspective view of inductance and capacitance of a substrate integrated with passive devices according to an embodiment of the present disclosure.
  • FIG. 2 is a cross-sectional view of a substrate integrated with passive devices according to an embodiment of the present disclosure.
  • FIG. 3 is a cross-sectional view of an intermediate product formed in step S11 of the method for manufacturing a substrate integrated with passive devices according to an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of an intermediate product formed in step S12 of the method for manufacturing a substrate integrated with passive devices according to an embodiment of the present disclosure.
  • step S13 is a cross-sectional view of an intermediate product formed in step S13 in the method for manufacturing a substrate integrated with passive devices according to an embodiment of the present disclosure.
  • FIG. 6 is a cross-sectional view of an intermediate product formed in step S14 of the method for manufacturing a substrate integrated with passive devices according to an embodiment of the present disclosure.
  • step S15 is a cross-sectional view of an intermediate product formed in step S15 of the method for manufacturing a substrate integrated with passive devices according to an embodiment of the present disclosure.
  • step S16 is a cross-sectional view of an intermediate product formed in step S16 of the method for manufacturing a substrate integrated with passive devices according to an embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional view of an intermediate product formed in step S17 in the method for manufacturing a substrate integrated with passive devices according to an embodiment of the present disclosure.
  • step S18 is a cross-sectional view of an intermediate product formed in step S18 of the method for manufacturing a substrate integrated with passive devices according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a substrate integrated with passive devices and a preparation method thereof.
  • passive components such as capacitors, inductors, resistors, etc.
  • an LC oscillator circuit integrated on a substrate is taken as an example. That is, at least inductive and capacitive devices are integrated on the substrate. It should be understood that, according to the function and performance of the circuit, devices such as resistors may also be integrated on the substrate.
  • an embodiment of the present disclosure provides a substrate integrated with passive devices, which includes a base substrate 10, a passive device disposed on the base substrate 10, the passive The device includes at least an inductor 1 .
  • the inductor 1 includes a plurality of open-loop portions 11 arranged in sequence along a direction away from the base substrate 10 (that is, a direction perpendicular to the plane where the base substrate 10 is located) and connected in sequence.
  • any open-loop portion 11 includes a head end and a terminal end, and the head ends and ends of adjacent open-loop portions 11 are connected in sequence.
  • any open loop portion 11 facing away from the base substrate 10 is covered with the interlayer dielectric layer 4, and the adjacent open loop portions 11 are electrically connected through the first via hole 12 penetrating the interlayer dielectric layer 4;
  • the orthographic projections of any two open-loop portions 11 on the base substrate 10 are at least partially overlapped.
  • the area of the base substrate 10 occupied by the inductor 1 can be effectively reduced. Space, which helps to achieve high integration of substrates integrated with passive devices.
  • the orthographic projections of the open-loop portions 11 of the inductor 1 on the base substrate 10 are completely overlapped. In this way, the size of the inductor 1 can be minimized and the integration of the substrate can be improved.
  • the interlayer dielectric layer 4 includes a first passivation layer 41 , a planarization layer 42 and a second passivation layer 43 sequentially disposed on the substrate 10 away from the substrate.
  • both the first passivation layer 41 and the second passivation layer 43 can use inorganic materials, the materials of which can be the same or different, and the inorganic materials include: SiNx, SiNOx, SiOx, the first passivation layer 41 and The second passivation layer 43 can use one or more materials among SiNx, SiNOx and SiOx to form a single layer structure or a stacked layer structure.
  • the thicknesses of the first passivation layer 41 and the second passivation layer 43 are both in about.
  • the planarization layer 42 uses an organic material.
  • Organic materials include photosensitive OC materials, such as acrylic-based polymers, silicon-based polymers, and other materials.
  • the thickness of the planarization layer 42 is 2 ⁇ m-5 ⁇ m, for example, the thickness of the planarization layer 42 is 3 ⁇ m.
  • the number of interlayer dielectric layers 4 is also N, where N ⁇ 2, and N is an integer.
  • the planarization layer 42 in the Mth interlayer dielectric layer 4 passes through the second passivation layer 43 in the M-1th interlayer dielectric layer 4 and the Mth interlayer dielectric layer 4
  • the second via hole 13 of the first passivation layer 41 is in contact with the planarization layer 42 in the M-1th interlayer dielectric layer 4, 2 ⁇ M ⁇ N, and M is an integer.
  • any second via hole 13 penetrates through the second passivation layer 43 of one of the adjacently arranged interlayer dielectric layers 4 and the first passivation layer 41 of the other, so that the adjacently arranged The planarization layer 42 in the interlayer dielectric layer 4 is in contact.
  • the reason for such setting is that the planarization layer 42 is usually made of organic insulating material, and the second via hole 13 is equivalent to a ventilation channel at this time, so that water, oxygen, etc. absorbed by each planarization layer 42 can be led out of the substrate.
  • the orthographic projections of at least part of the second via holes 13 located on different layers on the base substrate 10 at least partially overlap, that is, at least the second via hole 13 communicates in a direction perpendicular to the base substrate 10 , This facilitates the derivation of water, oxygen, etc. of each planarization layer 42 .
  • the substrate includes multiple layers of second via holes 13 , and the number of second via holes 13 in each layer is multiple.
  • the second via holes 13 of any adjacent layer are arranged in one-to-one correspondence, and the orthographic projections of the plurality of second via holes 13 arranged in one-to-one correspondence on the base substrate 10 completely overlap. In this way, the water, oxygen, etc. of each planarization layer 42 can be led out to the greatest extent.
  • the orthographic projections of at least part of the first via holes 12 used to electrically connect adjacent open-loop portions 11 in the inductor 1 on the base substrate 10 do not overlap.
  • the orthographic projections of the i-th and (i+1)-th first via holes 12 on the base substrate 10 along the direction away from the base substrate 10 do not overlap, i ⁇ 1. In this way, it is possible to effectively avoid the concentrated arrangement of the first via holes 12 and reduce the risk of defective components of the inductor 1 .
  • the orthographic projections of the i-th and i+1-th first via holes 12 on the base substrate 10 in the direction away from the base substrate 10 do not overlap, and the i-th and i+2-th via holes 12
  • the orthographic projections of a via hole 12 on the base substrate 10 completely overlap.
  • the patterns of the i-th and i+2-th open-loop portions 11 along the direction away from the base substrate 10 may be the same, and their orthographic projections on the base substrate 10 may overlap.
  • the passive device in the embodiment of the present disclosure includes not only an inductor 1, but also a capacitor 2, and the capacitor 2 includes a first plate 21 and a second plate arranged in sequence along the side away from the substrate 10 22.
  • the first pole plate 21 can be set on the same layer as one of the multiple open-loop parts 11 of the inductor 1, and use the same material.
  • the first plate 21 of the capacitor 2 and the open-loop portion 11 of the inductor 1 can be formed in one patterning process, thereby reducing process steps and costs.
  • the first plate 21 of the capacitor 2 can be arranged on the same layer as the first open-loop portion 11 of the inductor 1 along the direction away from the substrate, and be directly electrically connected, that is, the first plate 21 of the capacitor 2 can be connected with the The first open-loop portion 11 of the inductor 1 along the direction away from the substrate is integrally formed.
  • a dielectric layer 23 may be provided between the second plate 22 and the first plate 21 of the capacitor 2, and the dielectric layer 23 may include one or more of SiNx, SiNOx, and SiOx
  • the material forms a single-layer structure or a laminated structure, and its thickness is in the left and right, for example
  • the thickness of the second pole plate 22 of the capacitor 2 is smaller than the thickness of the first pole plate 21, for example: the thickness ratio of the second pole plate 22 to the first pole plate 2 is 1:100-1 :30, preferably 1:60.
  • the thicknesses of the two polar plates of the capacitor 2 can also be specifically set according to product requirements.
  • the embodiment of the present disclosure also includes a first connection part 3, the first connection part 3 is used as a signal receiving terminal of the second plate 22 of the capacitor 2, which is connected to the second plate 22 of the capacitor 2,
  • the first connecting portion 3 is disposed on the same layer as the last one of the plurality of open loop portions 11 disposed along the direction away from the base substrate 10 .
  • the first connection part 3 and the second pole plate 22 are further provided with at least one transfer portion 5 , and the first connection portion 3 is electrically connected to the second pole plate 22 through the transfer portion 5 .
  • inductance 1 includes three open-loop parts 11, the first pole plate 21 of capacitor 2 is set on the same layer as the first open-loop part 11, and the second pole plate 22 of capacitor 2 is only assumed between the first pole plate 21
  • the transfer part 5 can be arranged on the same layer as the second open-loop part 11, and the first connecting part 3 can be arranged on the same layer as the third open-loop part 11.
  • the first connecting part 3 The connecting portion 5 is connected, and the connecting portion 5 is connected to the second pole plate 22 , so as to realize the electrical connection between the first connecting portion 3 and the second pole plate 22 .
  • the transition part 5 and any one or more of the plurality of open-loop parts 11 in the inductor 1 between the first and the last one are arranged in the same layer, so that no process steps are added, Process costs can also be reduced.
  • the protective layer 6 can be formed on the layer where the last open loop portion 11 and the first connecting portion 3 are located away from the substrate base, and the third via hole 71 and the fourth via hole 72 are formed in the protective layer 6, One end of the last open-loop part 11 of the inductor 1 is exposed at the position of the third via hole 71 , and the first connection part 3 is exposed at the position of the fourth via hole 72 , so as to load signals for the capacitor 2 and the inductor 1 .
  • the protective layer may include a first passivation layer 61 and a planarization layer 62, and the first passivation layer 61 and the planarization layer 62 may be made of the same materials as the above-mentioned first passivation layer 41 and the planarization layer 42 respectively, so in This will not be repeated here.
  • the base substrate 10 in the embodiment of the present disclosure can be a glass substrate, or a flexible film, and the material of the flexible film can be COP film, polyimide (PI) or polyethylene terephthalate (PET) at least one.
  • the thickness of the base substrate 10 in the embodiment of the present disclosure may be about 0.5mm-1mm, for example: the back of the base substrate 10 is 0.7mm.
  • a reverse stress layer may be formed on the base substrate 10 of the embodiment of the present disclosure to reduce glass warpage.
  • an embodiment of the present disclosure provides a method for preparing a substrate integrated with passive devices, and the method can be used for preparing the above-mentioned substrate.
  • the method may include providing a base substrate 10, and forming passive devices on the base substrate 10.
  • the passive device includes an inductor 1; Open-loop portion 11; wherein, the step of forming the inductor 1 includes: sequentially forming a plurality of open-loop portions 11 and the interlayer dielectric layer 4 covering the open-loop portion 11 on the base substrate 10, and adjacently arranged open-loop portions The portions 11 are electrically connected through the first via hole 12 penetrating the interlayer dielectric layer 4 ; and the orthographic projections of any two open-loop portions 11 on the base substrate 10 are at least partially overlapped.
  • the preparation method in the embodiment of the present disclosure takes three open-loop parts 11 of the inductor 1 as an example for illustration.
  • the following description includes not only the step of forming the inductor 1 but also the step of forming the capacitor 2 , but it should be understood that not forming the capacitor 2 in the substrate is also within the protection scope of the embodiments of the present disclosure.
  • the preparation method of the embodiment of the present disclosure may specifically include the following steps.
  • a base substrate 10 is provided, on which a pattern including the first plate 21 of the capacitor 2 and the first open loop portion 11a of the capacitor 2 is formed.
  • step S11 may specifically include:
  • the base substrate 10 can be a glass substrate, or a flexible film
  • the flexible film material can be at least one of COP film, polyimide (PI) or polyethylene terephthalate (PET).
  • the flexible COP film can be pasted on the glass substrate with transparent optical glue (OCA glue), and then the glass substrate on which the COP film is formed is cleaned.
  • OCA glue transparent optical glue
  • the material of the first sacrificial layer includes but not limited to organic materials, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, silicon oxide, etc. Alkane and other resin materials, etc.
  • the material of the first metal film includes but not limited to at least one of (Cu), aluminum (Al), molybdenum (Mo), silver (Ag), the thickness of the first metal film is about 100nm-500nm, further can be in 50nm-35 ⁇ m, such as 7 ⁇ m.
  • the material of the first metal thin film is copper as an example.
  • the first open-loop portion 11a of the inductor 1 and the first plate 21 of the capacitor 2 completed so far are mainly electroplating. It should be noted that the above only gives an exemplary method of forming the first open-loop portion 11a of the inductor 1 and the first plate 21 of the capacitor 2, and in some examples, depositing the first metal film can also be used layer, and then form the pattern of the first open-loop portion 11a of the inductor 1 and the first plate 21 of the capacitor 2 by means of exposure, development, and etching. The methods for forming the first open-loop portion 11 a of the inductor 1 and the first plate 21 of the capacitor 2 are not listed here.
  • the dielectric layer 23 can specifically be one or more materials in SiNx, SiNOx, and SiOx to form a single-layer structure or a stacked structure, and its thickness is between left and right, for example
  • the material of the second plate 22 of the capacitor 2 may be the same as that of the first plate 21 , except that the thickness of the second plate 22 is thinner than that of the first plate 21 .
  • the step of forming the second pole plate 22 including the capacitor 2 through a patterning process may specifically include: depositing a second metal film by, for example, controlled sputtering, and forming the second pole including the capacitor 2 through exposure, development, and etching processes. Graphics of board 22.
  • a first interlayer dielectric layer 4a is formed, and a first first pass through the first interlayer dielectric layer 4 is formed through a patterning process.
  • hole 12a and the first first transfer hole 44a are formed on the base substrate 10 after the above steps are completed.
  • one end of the first open-loop portion 11 of the inductor 1 is exposed at the position of the first first via hole 12a (this end is the end not connected to the first plate 21 of the capacitor 2), and at the first The position of the first via hole 44 a exposes at least part of the position of the second plate 22 of the capacitor 2 .
  • the first interlayer dielectric layer 4 a includes a first passivation layer 41 , a planarization layer 42 and a second passivation layer 43 sequentially disposed on the substrate 10 away from the base.
  • both the first passivation layer 41 and the second passivation layer 43 can use inorganic materials, the materials of which can be the same or different, and the inorganic materials include: SiNx, SiNOx, SiOx, the first passivation layer 41 and The second passivation layer 43 can use one or more materials among SiNx, SiNOx and SiOx to form a single layer structure or a stacked layer structure.
  • the thicknesses of the first passivation layer 41 and the second passivation layer 43 are both in about.
  • the planarization layer 42 uses an organic material.
  • Organic materials include photosensitive OC materials, such as acrylic-based polymers, silicon-based polymers, and other materials.
  • the thickness of the planarization layer 42 is 2 ⁇ m-5 ⁇ m, for example, the thickness of the planarization layer 42 is 3 ⁇ m.
  • the step of forming the first first via hole 12a and the first first transfer hole 44a may specifically include: first, on the base substrate 10 on which the second plate 22 of the storage capacitor 2 is formed Form the first passivation layer 41 and the planarization layer 42 in sequence, and form the first sub-via hole and the second sub-via hole through the first passivation layer 41 and the planarization layer 42 through a patterning process, the first sub-via hole The position exposes one end of the first open-loop part 11 of the inductor 1 (this end is the end not connected to the first plate 21 of the capacitor 2), and the position of the second sub-via exposes the second pole of the storage capacitor 2 At least part of the position of the plate 22.
  • the second passivation layer 43 is formed, and the third sub-via hole and the fourth sub-via hole are formed through the second passivation layer 43, wherein the third sub-via hole and the first sub-via hole are connected to form the first via hole.
  • the hole 12a, the fourth sub-via and the second sub-via communicate to form a first transfer hole 44a.
  • step S14 may also include , after depositing the first passivation layer 41, the planarization layer 42 and the second passivation layer 43 in sequence, the first passivation layer 41, the planarization layer 42 and the second passivation layer 43 are formed through a patterning process.
  • a pattern including the second open-loop part 11 b of the inductor 1 and the transition part 5 is formed through a patterning process.
  • the second open-loop part 11b is connected to the first open-loop part 11a through the first first via hole 12a
  • the transfer part 5 is connected to the second plate of the capacitor 2 through the first first transfer hole 44a. 22 connections.
  • the second open-loop part 11b of the inductor 1 and the transition part 5 formed in step S15 adopt the same process method as the process method in step S11, such as copper electroplating, so it will not be described here. Repeat.
  • a second interlayer dielectric layer 4 is formed, and a second first via hole 12b penetrating through the second interlayer dielectric layer 4b is formed through a patterning process and the second first transfer hole 44b.
  • one end of the second open-loop portion 11b of the inductor 1 is exposed at the position of the second first via hole 12, and at least part of the transition portion 5 is exposed at the position of the second first transition hole 44b.
  • the second interlayer dielectric layer 4b and the first interlayer dielectric layer 4a may adopt the same film structure, for example, including a first passivation layer 41, a flat layer 42 and the second passivation layer 43, so the steps of forming the second first via hole 12b and the second first via hole 44b can be the same as S14, so the description will not be repeated here.
  • the second interlayer dielectric layer 4b when the second interlayer dielectric layer 4b is disposed along the first passivation layer 41, the planarization layer 42, and the second passivation layer 43 that are sequentially disposed on the substrate 10 away from the base, when the second interlayer dielectric layer 4b is formed, After the first passivation layer 41 of the interlayer dielectric layer 4b, it may also include forming the second passivation layer 43 penetrating through the first interlayer dielectric layer 4a and the first passivation layer 41 of the second interlayer dielectric layer 4b.
  • the second via hole 13 is used to make the planarization layer 42 of the first interlayer dielectric layer 4 contact with the planarization layer 42 of the second interlayer dielectric layer 4 through the first second via hole 13a.
  • the first and second via holes 13a are equivalent to ventilation channels, so as to release water, oxygen, etc. absorbed by each planarization layer 42 to the outside.
  • the third open-loop portion 11 c and the first connection portion 3 of the inductor 1 are formed on the base substrate 10 after the above steps are completed.
  • the third open loop portion 11c is connected to one end of the second open loop portion 11b through the second first via hole 12b, and the first connecting portion 3 is connected to the transition portion 5 through the second first transition hole 44b. connect.
  • the third open-loop part 11c and the first connecting part 3 of the inductor 1 formed in step S17 adopt the same process method as the process method in step S11 or S15, for example, copper electroplating is used, so it will not be repeated here. .
  • the protective layer 6 may include the above-mentioned first passivation layer 61 and planarization layer 61 , in this case, after the first passivation layer 61 , a first passivation layer penetrating through the protective layer 6 is formed. layer 61 and the second second via hole 13b of the second passivation layer 43 of the second interlayer dielectric layer 4, so that the planarization layer 62 of the protective layer 6 and the second interlayer dielectric layer 4 are flat The planarization layers 42 are in contact with each other so as to release water, oxygen, etc. absorbed by each planarization layer 42 to the outside.

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Abstract

本公开提供一种集成有无源器件的基板及其制备方法，属于射频器件技术领域。本公开的集成有无源器件的基板，其包括衬底基板和设置在所述衬底基板上的无源器件，所述无源器件至少包括电感；所述电感包括沿背离衬底基板方向依次设置、且顺次连接的多个开环部；其中，相邻设置的所述开环部之间设置有层间介质层，相邻设置的所述开环部通过贯穿所述层间介质层的第一过孔电连接；且任意两个所述开环部在所述衬底基板上的正投影至少部分重叠。

Description

集成有无源器件的基板及其制备方法 技术领域
本公开属于射频器件技术领域，具体涉及一种集成有无源器件的基板及其制备方法。
背景技术
在当代，消费电子产业发展日新月异，以手机特别是5G手机为代表的移动通信终端发展迅速，手机需要处理的信号频段越来越多，需要的射频芯片数量也水涨船高，而获得消费者喜爱的手机形式向小型化、轻薄化、长续航不断发展。在传统手机中，射频PCB板上存在大量的分立器件如电阻、电容、电感、滤波器等，它们具有体积大、功耗高、焊点多、寄生参数变化大的缺点，难以应对未来的需求。射频芯片相互间的互联、匹配等需要面积小、高性能、一致性好的集成无源器件。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种集成有无源器件的基板及其制备方法。
第一方面，本公开实施例提供一种集成有无源器件的基板，其包括衬底基板和设置在所述衬底基板上的无源器件，所述无源器件至少包括电感；所述电感包括沿背离衬底基板方向依次设置、且顺次连接的多个开环部；其中，相邻设置的所述开环部之间设置有层间介质层，相邻设置的所述开环部通过贯穿所述层间介质层的第一过孔电连接；且任意两个所述开环部在所述衬底基板上的正投影至少部分重叠。
其中，所述层间介质层包括沿背离衬底基板方向依次设置的第一钝化层、平坦化层、第二钝化层；所述基板包括N个层间介质层；第M个层间介质层中的平坦化层，通过贯穿第M-1层间介质层中的第二钝化层和第M个层间介质层中的第一钝化层的第二过孔，与第M-1层间介质层中平坦化层接触；N≥2，2≤M≤N，且M和N均为整数。
其中，至少部分位于不同层的所述第二过孔在所述衬底基板上 的正投影至少部分重叠。
其中，所述第M个层间介质层中的平坦化层通过多个所述第二过孔与所述第M-1层间介质层中平坦化层接触。
其中，至少部分所述第一过孔在所述衬底基板上的正投影无重叠。
其中，所述无源器件还包括电容，所述电容包括沿背离所述衬底基板一侧依次设置的第一极板和第二极板；所述第一极板与所述多个开环部中的一个同层设置，且材料相同。
其中，所述第一极板与所述多个开环部中在沿背离所述衬底方向上设置的第一个同层设置，且直接电连接。
其中，所述第二极板与所述第一极板的厚度比为1:100～1:30。
其中，所述基板还包括第一连接部，所述第一连接部与所述第二极板电连接，所述第一连接部与所述多个开环部中在沿背离所述衬底基板方向上设置的最后一个同层设置。
所述基板还包括转接部，所述转接部与多个开环部中位于第一个和最后一个之间的任意一个或者多个同层设置。
第二方面，本公开实施例提供一种集成有无源器件的基板的制备方法，其包括：提供一衬底基板，并在所述衬底基板上形成无源器件，所述无源器件包括电感；所述电感包括沿背离衬底基板方向依次设置、且顺次连接的多个开环部；其中，形成所述电感的步骤包括：在衬底基板上依次形成多个开环部和覆盖在所述开环部之上的层间介质层，相邻设置的所述开环部通过贯穿所述层间介质层的第一过孔电连接；且任意两个所述开环部在所述衬底基板上的正投影至少部分重叠。
其中，形成所述开环部的步骤包括：在所述衬底基板上形成金属薄膜，作为种子层；在所述种子层背离衬底基板的一侧形成牺牲层，并对牺牲层刻蚀形成与所述开环部对应的凹槽部；对所述种子层进行电镀，以使所述凹槽部形成金属材料；去除种子层，并通过构图工艺去除 所述凹槽部以外的金属材料，形成所述开环部。
其中，所述层间介质层包括沿背离衬底基板方向依次设置的第一钝化层、平坦化层、第二钝化层；所述基板包括N个层间介质层；所述方法还包括形成贯穿第M-1层间介质层中的第二钝化层和第M个层间介质层中的第一钝化层的第二过孔，以使第M个层间介质层中的平坦化层与第M-1层间介质层中平坦化层接触；N≥2，2≤M≤N，且M和N均为整数。
其中，所述无源器件还包括电容，形成所述电容的步骤包括：沿背离所述衬底基板一侧依次形成的第一极板和第二极板；所述第一极板与所述多个开环部中的一个在同一次构图工艺中形成。
其中，所述第一极板与所述多个开环部中在沿背离所述衬底方向上设置的第一个在同一次构图工艺中形成。
附图说明
图1为本公开实施例的集成有无源器件的基板的电感和电容的立体图。
图2为本公开实施例的集成有无源器件的基板的截面图。
图3为本公开实施例的集成有无源器件的基板的制备方法中的步骤S11所形成的中间产品的截面图。
图4为本公开实施例的集成有无源器件的基板的制备方法中的步骤S12所形成的中间产品的截面图。
图5为本公开实施例的集成有无源器件的基板的制备方法中的步骤S13所形成的中间产品的截面图。
图6为本公开实施例的集成有无源器件的基板的制备方法中的步骤S14所形成的中间产品的截面图。
图7为本公开实施例的集成有无源器件的基板的制备方法中的步骤S15所形成的中间产品的截面图。
图8为本公开实施例的集成有无源器件的基板的制备方法中的步骤S16所形成的中间产品的截面图。
图9为本公开实施例的集成有无源器件的基板的制备方法中的步骤S17所形成的中间产品的截面图。
图10为本公开实施例的集成有无源器件的基板的制备方法中的步骤S18所形成的中间产品的截面图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开实施例提供一种集成有无源器件的基板及其制备方法。其中，无源器件如电容、电感、电阻等，集成在基板上形成电路结构。在本公开实施例中以基板上集成LC振荡电路为例。也就是说，在基板上至少集成有电感和电容器件。应当理解的是，根据电路功能和性能，在基板上还可以集成有电阻等器件。
第一方面，结合图1和图2所示，本公开实施例提供一种集成有无源器件的基板，其包括衬底基板10，设置在衬底基板10上的无源器 件，该无源器件至少包括电感1。其中，电感1包括沿背离衬底基板10方向(也即，垂直于衬底基板10所在平面的方向)依次设置、且顺次连接的多个开环部11。具体的，任一开环部11均包括首端和末端，相邻设置开环部11的的首端和末端顺次连接。特别的是，任意开环部11背离衬底基板10的一侧均覆盖有层间介质层4，相邻设置的开环部11通过贯穿层间介质层4的第一过孔12电连接；在本公开实施例中任意两个开环部11在衬底基板10上的正投影至少部分重叠。
由于在本公开实施例中衬底基板10上形成的电感1的任意两个开环部11在衬底基板10上的正投影至少部分重叠，可以有效的缩小电感1所占衬底基板10的空间，有助于实现集成有无源器件的基板高集成度。
在一些示例中，电感1的各开环部11在衬底基板10上的正投影完全重叠，通过该种方式，最大的限度的缩小电感1的尺寸，提高基板的集成度。
在一些示例中，层间介质层4包括沿背离衬底基板10上依次设置的第一钝化层41、平坦化层42和第二钝化层43。在一些示例中，第一钝化层41和第二钝化层43均可以采用无机材料，二者材料可以相同也可以不同，无机材料包括：SiNx、SiNOx、SiOx，第一钝化层41和第二钝化层43均可以采用SiNx、SiNOx、SiOx中的一种或者多种材料组成单层结构或者叠层结构。第一钝化层41和第二钝化层43的厚度均在
Figure PCTCN2021127289-appb-000001
左右。平坦化层42采用有机材料。有机材料包括光敏的OC材料，例如：丙烯酸基聚合物、硅基聚合物等材料。平坦化层42的厚度在2μm-5μm，例如平坦化层42的厚度为3μm。
进一步的，当电感1具有N个开环部11时，层间介质层4的个数同样为N，N≥2，N为整数。在该种情况下，第M个层间介质层4中的平坦化层42，通过贯穿第M-1层间介质层4中的第二钝化层43和第M个层间介质层4中的第一钝化层41的第二过孔13，与第M-1层间介质层4中平坦化层42接触，2≤M≤N，M为整数。也就是说，对于任 一第二过孔13均贯穿相邻设置的层间介质层4中一者的第二钝化层43和另一者的第一钝化层41，以使相邻设置的层间介质层4中的平坦化层42相接触。之所以如此设置时因为，通常平坦化层42采用有机绝缘材料，此时第二过孔13相当于透气通道，以使各平坦化层42所吸收的水氧等导出基板。
进一步的，在一些示例中，至少部分位于不同层的第二过孔13在衬底基板10上的正投影至少部分重叠，也即在垂直衬底基板10的方向至少第二过孔13连通，这样有助于各平坦化层42的水氧等导出。在一个示例，基板上包括多层第二过孔13，且每层第二过孔13的数量均为多个。任意相邻层种的第二过孔13一一对应设置，且一一对应设置的多个第二过孔13在衬底基板10上的正投影完全重叠。通过该种方式最大限度的将各平坦化层42的水氧等导出。
在一些示例中，电感1中用于将相邻设置的开环部11之间电连接的第一过孔12中的至少部分在衬底基板10上的正投影无重叠。例如，沿背离衬底基板10方向上的第i个和第i+1个第一过孔12在衬底基板10上的正投影无重叠，i≥1。以此可以有效的避免第一过孔12集中设置，降低电感1器件出现不良的风险。在一些示例中，沿背离衬底基板10方向上的第i个和第i+1个第一过孔12在衬底基板10上的正投影无重叠，第i个和第i+2个第一过孔12在衬底基板10上的正投影完全重叠。在该种情况下，沿背离衬底基板10方向上的第i个和第i+2个开环部11的图形可以相同，且二者在衬底基板10上的正投影可以重叠。
在一些示例中，本公开实施例中的无源器件不仅包括电感1，还可以包括电容2，电容2的包括沿背离衬底基板10一侧依次设置的第一极板21和第二极板22，第一极板21可以与电感1的多个开环部11中的一个同层设置，且采用相同材料。在该种情况下，电容2的第一极板21和电感1的一个开环部11可以在一次构图工艺中形成，故可以减少工艺步骤和成本。例如：电容2的第一极板21可以与电感1在沿背离衬底方向上的第一个开环部11同层设置，且直接电连接，也即电容2的 第一极板21可以与电感1在沿背离衬底方向上的第一个开环部11为一体成型结构。在该种情况下，电容2的第二极板22与第一极板21之间可以设置一层介电层23，该介电层23可以包括SiNx、SiNOx、SiOx中的一种或者多种材料组成单层结构或者叠层结构，其厚度均在
Figure PCTCN2021127289-appb-000002
左右，例如为
Figure PCTCN2021127289-appb-000003
在本公开实施例中，电容2的第二极板22的厚度小于第一极板21的厚度，例如：第二极板22与所述第一极板2的厚度比为1:100～1:30，优选为1:60。当然也可以根据产品需要可以对电容2的两个极板的厚度进行具体设定。在一些示例中，在本公开实施例中还包括第一连接部3，该第一连接部3作为电容2的第二极板22的信号接收端子，其与电容2的第二极板22，该第一连接部3与多个开环部11中在沿背离衬底基板10方向上设置的最后一个同层设置。进一步的，为了防止第一连接部3和第二极板22之间的距离较大，而造成第一连接部3与第二极板22在连接时出现断线的问题，在第一连接部3与第二极板22之间还设置至少一个转接部5，第一连接部3通过转接部5与第二极板22电连接。例如：电感1包括三个开环部11，电容2的第一极板21与第一个开环部11同层设置，电容2的第二极板22仅与第一极板21之间假设一层介电层23，转接部5则可以与第二个开环部11同层设置，第一连接部3则可以第三个开环部11同层设置，此时第一连接部3连接转接部5，转接部5连接第二极板22，从而实现第一连接部3和第二极板22的电连接。在一些示例中，转接部5与电感1中的多个开环部11中位于第一个和最后一个之间的任意一个或者多个同层设置，这样一来，不会增加工艺步骤，也可以降低工艺成本。
需要说明的，在最后一个开环部11和第一连接部3所在层背离衬底基底的一层可以形成保护层6，保护层6中形成有第三过孔71和第四过孔72，在第三过孔71的位置裸露电感1的最后一个开环部11的一端，第四过孔72位置处裸露第一连接部3，以此便于为电容2和电感1加载信号。其中，保护层可以包括第一钝化层61和平坦化层62，该第一钝化层61和平坦化层62分别可与上述第一钝化层41和平坦化层42材 料相同，故在此不再重复赘述。
在一些示例中，本公开实施例中衬底基板10可以玻璃基板，也可以为一柔性薄膜，柔性薄膜材料可为COP薄膜、聚酰亚胺(PI)或聚对苯二甲酸乙二醇酯(PET)至少之一。本公开实施例中的衬底基板10的厚度可以在0.5mm-1mm左右，例如：衬底基板10的后为0.7mm。在本公开实施例的衬底基板10上可以形成反向应力层以减少玻璃翘曲。
第二方面，本公开实施例提供一种集成有无源器件的基板的制备方法，该方法可用于制备上述基板。该方法可以包括提供一衬底基板10，并在衬底基板10上形成无源器件，无源器件包括电感1；电感1包括沿背离衬底基板10方向依次设置、且顺次连接的多个开环部11；其中，形成电感1的步骤包括：在衬底基板10上依次形成多个开环部11和覆盖在开环部11之上的层间介质层4，相邻设置的开环部11通过贯穿层间介质层4的第一过孔12电连接；且任意两个开环部11在衬底基板10上的正投影至少部分重叠。
为了更记清楚本公开实施例中的制备方法，以下以电感1的开环部11为三个为例进行说明。在以下描述中不仅包括形成电感1的步骤，还包括形成的电容2的步骤，但应当理解的是，该基板中不形成电容2也在本公开实施例的保护范围之内。本公开实施例的制备方法具体可以包括如下步骤。
S11、参照图3，提供一衬底基板10，在该衬底基板10上形成包括电容2的第一极板21和电容2的第一个开环部11a的图形。
在一些示例中，步骤S11具体可以包括：
S111、提供一衬底基板10，并在第一衬底基板10上形成第一牺牲层，并对第一牺牲层进行图案化，形成在第一牺牲层中与待形成电容2的第一极板21和电容2的第一个开环部11a的图形对应的第一开槽。
其中，衬底基板10可以玻璃基板，也可以为一柔性薄膜，柔性薄膜材料可为COP薄膜、聚酰亚胺(PI)或聚对苯二甲酸乙二醇酯(PET) 至少之一，此时S1中可以将柔性COP薄膜通过透明光学胶(OCA胶)贴合在玻璃基板上，之后对形成有COP薄膜的玻璃基板进行清洗。第一牺牲层的材料包括但不限于有机材料，例该有材料例如包括聚酰亚胺、环氧树脂、压克力、聚酯、光致抗蚀剂、聚丙烯酸酯、聚酰胺、硅氧烷等树脂类材料等。
S112、利用电子束蒸镀设备在第一牺牲层背离衬底基板10的一侧蒸镀第一金属薄膜，将该第一金属薄膜作为第一种子层。第一金属薄膜的材料包括但不限于(Cu)、铝(Al)、钼(Mo)、银(Ag)中的至少一种，第一金属薄膜的厚度在100nm-500nm左右，进一步的可以在50nm-35μm，例如7μm。在以下描述中以第一金属薄膜的材料为铜为例。
S113、将完成上述步骤的衬底基板10放入电镀机台载具上，压上加电焊盘(pad)，放入填孔电镀槽(槽中使用专用填孔电解液)中，加电流，电镀液保持在第一金属薄膜表面持续快速流动，在第一开槽内壁上电镀液中的阳离子获得电子，成为原子淀积在内壁上，通过特殊配比的专用填孔电解液，可以做到主要在第一开槽内高速淀积金属铜(淀积速度0.5-3um/min)，而在衬底基板10为平整区域，这两个表面上的金属铜的淀积速度极小(0.005-0.05um/min)。随时间增加，第一开槽的内壁上的金属铜逐渐长厚，形成第一金属膜层，此时第一金属膜层相较于第一金属薄膜生长5μm以上。
S113、将除第一开槽外的第一金属膜层材料去除，以及将第一牺牲层去除，形成电感1的第一个开环部11a和电容2的第一极板21。
至此完成的电感1的第一个开环部11a和电容2的第一极板21，所采用的工艺主要为电镀工艺。需要说明的是，以上仅给出一种示例性的形成电感1的第一个开环部11a和电容2的第一极板21的方法，在一些示例中，还可以采用沉积第一金属膜层，之后通过曝光、显影、刻蚀的方式形成电感1的第一个开环部11a和电容2的第一极板21的图形。对于形成电感1的第一个开环部11a和电容2的第一极板21的方法在此不一一列举。
S12、参照图4，在完成上述步骤的衬底基板10上，形成介电层23，作为电容2的中介介质。
在一些示例中，介电层23具体可以为SiNx、SiNOx、SiOx中的一种或者多种材料组成单层结构或者叠层结构，其厚度均在
Figure PCTCN2021127289-appb-000004
左右，例如为
Figure PCTCN2021127289-appb-000005
S13、参照图5，在完成上述步骤的衬底基板10上，通过构图工艺形成包括电容2的第二极板22的步骤。
在一些示例中，电容2的第二极板22的材料可与第一极板21的材料相同，仅仅是第二极板22的厚度比第一极板21的厚度薄一些。通过构图工艺形成包括电容2的第二极板22的步骤具体可以包括：采用例如采控溅射的方式沉积第二金属薄膜，并通过曝光、显影、刻蚀工艺形成包括电容2的第二极板22的图形。
S14、参照图6，在完成上述步骤的衬底基板10上，形成第一个层间介质层4a，并通过构图工艺形成贯第穿第一个层间介质层4的第一个第一过孔12a和第一个第一转接孔44a。其中，在第一个第一过孔12a的位置裸露出电感1的第一个开环部11的一端(该端为不与电容2的第一极板21连接的一端)，在第一个第一转接孔44a的位置裸露出电容2的第二极板22的至少部分位置。
在一些示例中，第一个层间介质层4a包括沿背离衬底基板10上依次设置的第一钝化层41、平坦化层42和第二钝化层43。在一些示例中，第一钝化层41和第二钝化层43均可以采用无机材料，二者材料可以相同也可以不同，无机材料包括：SiNx、SiNOx、SiOx，第一钝化层41和第二钝化层43均可以采用SiNx、SiNOx、SiOx中的一种或者多种材料组成单层结构或者叠层结构。第一钝化层41和第二钝化层43的厚度均在
Figure PCTCN2021127289-appb-000006
左右。平坦化层42采用有机材料。有机材料包括光敏的OC材料，例如：丙烯酸基聚合物、硅基聚合物等材料。平坦化层42的厚度在2μm-5μm，例如平坦化层42的厚度为3μm。
在一些示例中，形成第一个第一过孔12a和第一个第一转接孔44a的步骤具体可以包括：首先，在形成有存储电容2的第二极板22的衬底基板10上依次形成第一钝化层41、平坦化层42，并通过构图工艺形成贯穿第一钝化层41、平坦化层42的第一子过孔和第二子过孔，第一子过孔的位置裸露出电感1的第一个开环部11的一端(该端为不与电容2的第一极板21连接的一端)，第二子过孔的位置裸露出存储电容2的第二极板22的至少部分位置。之后，形成第二钝化层43，并形成贯穿第二钝化层43的第三子过孔和第四子过孔，其中，第三子过孔和第一子过孔连通形成第一过孔12a，第四子过孔和第二子过孔连通形成第一转接孔44a。
需要说明的是，当第一个层间介质层4a包括沿背离衬底基板10上依次设置的第一钝化层41、平坦化层42和第二钝化层43时，步骤S14还可以包括，依次沉积第一钝化层41、平坦化层42和第二钝化层43之后通过一次构图工艺形成贯穿第一钝化层41、平坦化层42和第二钝化层43的第一个第一过孔12和第一个第一转接孔44a。
S15、参照图7，在完成上述步骤的衬底基板10上，通过构图工艺形成包括电感1的第二个开环部11b和转接部5的图形。其中，第二个开环部11b通过第一个第一过孔12a与第一个开环部11a连接，转接部5通过第一个第一转接孔44a与电容2的第二极板22连接。
在一些示例中，步骤S15中形成的电感1的第二个开环部11b和转接部5所采用的工艺方法与步骤S11中工艺方法相同，例如采用电镀铜的方式，故在此不再重复赘述。
S16、参照图8，在完成上述步骤的衬底基板10上，形成第二个层间介质层4，并通过构图工艺形成贯穿第二个层间介质层4b的第二个第一过孔12b和第二个第一转接孔44b。其中，在第二个第一过孔12的位置裸露出电感1的第二个开环部11b的一端，在第二个第一转接孔44b的位置裸露出转接部5的至少部分位置。
在一些示例中，第二个层间介质层4b与第一个层间介质层4a可以采用相同的膜层结构，例如包括沿背离衬底基板10上依次设置的第一钝化层41、平坦化层42和第二钝化层43，故形成第二个第一过孔12b和第二个第一转接孔44b的步骤可以与S14相同，故在此不再重复描述。
在一些示例中，当第二个层间介质层4b沿背离衬底基板10上依次设置的第一钝化层41、平坦化层42和第二钝化层43时，在形成第二个层间介质层4b的第一钝化层41之后，还可以包括形成贯穿第一个层间介质层4a的第二钝化层43和第二个层间介质层4b的第一钝化层41的第二过孔13，以使第一个层间介质层4的平坦化层42和第二个层间介质层4的平坦化层42通过第一个第二过孔13a接触。第一个第二过孔13a相当于透气通道，以使各平坦化层42所吸收的水氧等向外释放。
S17、参照图9，在完成上述步骤的衬底基板10上，形成电感1的第三个开环部11c和第一连接部3。其中，第三个开环部11c通过第二个第一过孔12b与第二个开环部11b的一端连接，第一连接部3通过第二个第一转接孔44b与转接部5连接。
步骤S17中形成的电感1的第三个开环部11c和第一连接部3所采用的工艺方法与步骤S11或者S15中工艺方法相同，例如采用电镀铜的方式，故在此不再重复赘述。
S18、参照图10，在完成上述步骤的衬底基板10上形成保护层6，形成贯穿保护层6的第三过孔71和第四过孔72。其中，在第三过孔71的位置裸露电感1的第三个开环部11c的一端，第四过孔72位置处裸露第一连接部3，以此便于为电容2和电感1加载信号。
在一些示例中，保护层6可以包括上述的第一钝化层61和平坦化层61，在该种情况下，还包括在第一钝化层61后，形成贯穿保护层6的第一钝化层61和第二个层间介质层4的第二钝化层43的第二个第二过孔13b，以使保护层6的平坦化层62和第二个层间介质层4的平坦化层42接触，以使各平坦化层42所吸收的水氧等向外释放。
至此完成，本公开实施例中的集成有无源器件的基板的制备。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (15)

  1. 一种集成有无源器件的基板，其包括衬底基板和设置在所述衬底基板上的无源器件，所述无源器件至少包括电感；所述电感包括沿背离衬底基板方向依次设置、且顺次连接的多个开环部；其中，
    相邻设置的所述开环部之间设置有层间介质层，相邻设置的所述开环部通过贯穿所述层间介质层的第一过孔电连接；且任意两个所述开环部在所述衬底基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的基板，其中，所述层间介质层包括沿背离衬底基板方向依次设置的第一钝化层、平坦化层、第二钝化层；所述基板包括N个层间介质层；第M个层间介质层中的平坦化层，通过贯穿第M-1层间介质层中的第二钝化层和第M个层间介质层中的第一钝化层的第二过孔，与第M-1层间介质层中平坦化层接触；N≥2，2≤M≤N，且M和N均为整数。
  3. 根据权利要求2所述的基板，其中，至少部分位于不同层的所述第二过孔在所述衬底基板上的正投影至少部分重叠。
  4. 根据权利要求2所述的基板，其中，所述第M个层间介质层中的平坦化层通过多个所述第二过孔与所述第M-1层间介质层中平坦化层接触。
  5. 根据权利要求1-4中任一项所述的基板，其中，至少部分所述第一过孔在所述衬底基板上的正投影无重叠。
  6. 根据权利要求1-4中任一项所述的基板，其中，所述无源器件还包括电容，所述电容包括沿背离所述衬底基板一侧依次设置的第一极板和第二极板；所述第一极板与所述多个开环部中的一个同层设置，且材料相同。
  7. 根据权利要求6所述的基板，其中，所述第一极板与所述多个开环部中在沿背离所述衬底方向上设置的第一个同层设置，且直接电连接。
  8. 根据权利要求6所述的基板，其中，所述第二极板与所述第一极板的厚度比为1:100～1:30。
  9. 根据权利要求6所述的基板，其中，所述基板还包括第一连接部， 所述第一连接部与所述第二极板电连接，所述第一连接部与所述多个开环部中在沿背离所述衬底基板方向上设置的最后一个同层设置。
  10. 根据权利要求6所述的基板，其中，所述基板还包括转接部，所述转接部与多个开环部中位于第一个和最后一个之间的任意一个或者多个同层设置。
  11. 一种集成有无源器件的基板的制备方法，其包括：提供一衬底基板，并在所述衬底基板上形成无源器件，所述无源器件包括电感；所述电感包括沿背离衬底基板方向依次设置、且顺次连接的多个开环部；其中，
    形成所述电感的步骤包括：
    在衬底基板上依次形成多个开环部和覆盖在所述开环部之上的层间介质层，相邻设置的所述开环部通过贯穿所述层间介质层的第一过孔电连接；且任意两个所述开环部在所述衬底基板上的正投影至少部分重叠。
  12. 根据权利要求11所述的制备方法，其中，形成所述开环部的步骤包括：
    在所述衬底基板上形成金属薄膜，作为种子层；
    在所述种子层背离衬底基板的一侧形成牺牲层，并对牺牲层刻蚀形成与所述开环部对应的凹槽部；
    对所述种子层进行电镀，以使所述凹槽部形成金属材料；
    去除种子层，并通过构图工艺去除所述凹槽部以外的金属材料，形成所述开环部。
  13. 根据权利要求11所述的制备方法，其中，所述层间介质层包括沿背离衬底基板方向依次设置的第一钝化层、平坦化层、第二钝化层；所述基板包括N个层间介质层；所述方法还包括形成贯穿第M-1层间介质层中的第二钝化层和第M个层间介质层中的第一钝化层的第二过孔，以使第M个层间介质层中的平坦化层与第M-1层间介质层中平坦化层接触；N≥2，2≤M≤N，且M和N均为整数。
  14. 根据权利要求11所述的制备方法，其中，所述无源器件还包括电容，形成所述电容的步骤包括：沿背离所述衬底基板一侧依次形成的第一极板和第二极板；所述第一极板与所述多个开环部中的一个在同一次构图工艺中形成。
  15. 根据权利要求14所述的制备方法，其中，所述第一极板与所述多个开环部中在沿背离所述衬底方向上设置的第一个在同一次构图工艺中形成。
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