WO2022222124A1 - 集成有无源器件的基板及其制备方法 - Google Patents

集成有无源器件的基板及其制备方法 Download PDF

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Publication number
WO2022222124A1
WO2022222124A1 PCT/CN2021/089141 CN2021089141W WO2022222124A1 WO 2022222124 A1 WO2022222124 A1 WO 2022222124A1 CN 2021089141 W CN2021089141 W CN 2021089141W WO 2022222124 A1 WO2022222124 A1 WO 2022222124A1
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Prior art keywords
layer
transparent medium
medium layer
substructure
connection
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PCT/CN2021/089141
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English (en)
French (fr)
Inventor
刘英伟
曹占锋
王珂
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/089141 priority Critical patent/WO2022222124A1/zh
Priority to US17/641,135 priority patent/US20240047507A1/en
Priority to CN202180000883.4A priority patent/CN115516761A/zh
Publication of WO2022222124A1 publication Critical patent/WO2022222124A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F17/00—Amplifiers using electroluminescent element or photocell
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6672—High-frequency adaptations for passive devices for integrated passive components, e.g. semiconductor device with passive components only

Definitions

  • the present disclosure belongs to the technical field of radio frequency devices, and in particular relates to a substrate integrated with passive devices and a preparation method thereof.
  • Si-based integrated passive devices have the advantage of being cheap, but Si itself has trace impurities (poor insulation), which leads to high microwave losses and average performance; GaAs-based integrated passive devices have the advantage of excellent performance, but are expensive.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a substrate integrated with passive devices and a preparation method thereof.
  • embodiments of the present disclosure provide a method for manufacturing a substrate integrated with passive devices, including:
  • a transparent medium layer is provided, and the transparent medium layer is processed to obtain the transparent medium layer with a first connection via hole;
  • the transparent medium layer includes a first surface and a second surface oppositely arranged along the thickness direction;
  • a passive device is integrated on the transparent medium layer; the passive device at least includes an inductor; wherein,
  • Integrating the passive device on the transparent medium layer includes:
  • a first substructure is formed on the first surface of the transparent medium layer, a second substructure is formed on the second surface, and a first connection electrode is formed in the first connection via; the first substructure , the first connection electrode and the second substructure are connected to form an inductive coil structure.
  • the preparation method includes:
  • a first connection electrode and a first substructure are formed in the first blind hole
  • a pattern including the second sub-structure is formed on the second surface of the transparent medium layer; the second sub-structure, the first connection electrode and the first sub-structure are connected to form an inductor coil structure.
  • providing a transparent medium layer and etching the transparent medium layer to form a first blind hole including:
  • the transparent medium layer is modified by laser, and the first blind hole is formed by HF etching.
  • the patterning process is used to form the first connection electrode and the first substructure in the first blind hole
  • a first protective layer and a first planarization layer are sequentially formed on the side of the first metal film layer away from the transparent medium layer, and a pattern including the first connection electrode and the first substructure is formed through a patterning process .
  • the preparation method includes:
  • the transparent medium layer has a first connection via hole
  • a first metal material is deposited on the first surface and the second surface of the transparent dielectric layer, respectively, and through an electroplating process, the first metal material covers at least the sidewall of the first connection via hole, and forms a part located on the first connection via hole.
  • a pattern including the second sub-structure is formed on the second surface of the transparent medium layer; the second sub-structure, the first connection electrode and the first sub-structure are connected to form an inductor coil structure.
  • providing a first base substrate, and attaching the transparent medium layer on the first base substrate including:
  • the first surface and the second surface of the transparent medium layer are respectively laser modified, and the first connection via hole is formed by HF etching.
  • the method further includes:
  • a first planarization layer is formed on the side of the first metal material away from the transparent medium layer, so that the first planarization layer fills the first connection via hole.
  • the first substructure after forming the first substructure, it also includes:
  • a second protective layer and a second planarization layer are sequentially formed on the side of the first substructure away from the transparent medium layer.
  • the passive device further includes a capacitor; while the second sub-structure is formed on the second surface, a first plate of the capacitor is also formed; the preparation method further includes:
  • a first interlayer dielectric layer is formed on the side of the first polar plate of the capacitor facing away from the transparent dielectric layer;
  • a second electrode plate of the capacitor is formed on the side of the first interlayer dielectric layer away from the transparent dielectric layer;
  • a second interlayer dielectric layer is formed on the side of the second electrode plate of the capacitor away from the transparent dielectric layer, and a second connection through the first interlayer dielectric layer and the second interlayer dielectric layer is formed a via hole, and a third connection via hole penetrating the second interlayer dielectric layer;
  • the second connection electrode passes through the second connection via hole and the third connection via to connect the second substructure and the second electrode plate of the capacitor.
  • a first buffer layer and a third planarization layer are deposited in sequence on a layer where the second connection electrode and the connection pad are located away from the transparent medium layer, and formed through the first buffer layer and the The fourth connection via hole of the third planarization layer exposes the connection pad.
  • the transparent medium layer includes a glass base.
  • An embodiment of the present disclosure provides a substrate integrated with a passive device, which includes: a transparent medium layer and a passive device integrated on the medium layer; wherein,
  • the transparent medium layer includes a first surface and a second surface oppositely disposed along its thickness direction; the transparent medium layer has a first connection via hole penetrating along its thickness direction;
  • the passive device includes at least an inductor; the inductor includes a first substructure disposed on the first surface and a second substructure disposed on the second surface, and disposed in the first connection via hole A first connection electrode connecting the first substructure and the second substructure in series.
  • the passive device further includes a capacitor; wherein the first plate of the capacitor and the second sub-structure of the inductor are arranged in the same layer; the substrate further includes a first plate of the capacitor facing away from the The first interlayer dielectric layer on one side of the transparent dielectric layer; the second electrode plate of the capacitor is located on the side of the first interlayer dielectric layer away from the first electrode plate of the capacitor.
  • the transparent medium layer includes a glass base.
  • FIG. 1 is a top view of an inductor according to an embodiment of the disclosure.
  • FIG. 2 is a schematic three-dimensional structure diagram of an LC oscillator circuit according to an embodiment of the disclosure.
  • FIG 3 is a cross-sectional view of a substrate integrated with passive devices according to an embodiment of the disclosure.
  • FIG. 4a is a schematic diagram of a substrate formed in step S11 of a method for fabricating a substrate with integrated passive devices according to an embodiment of the disclosure.
  • FIG. 4b is a schematic diagram of the substrate formed in step S12 of (1) of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.
  • FIG. 4c is a schematic diagram of the substrate formed in step S12 (2) of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.
  • FIG. 4d is a schematic diagram of the substrate formed in step S12 of (3) and (4) of the method for fabricating the passive device-integrated substrate according to the embodiment of the disclosure.
  • FIG. 4e is a schematic diagram of the substrate formed in step S12 (5) of the method for fabricating the passive device-integrated substrate according to the embodiment of the disclosure.
  • FIG. 4f is a schematic diagram of the substrate formed in step S13 of the method for fabricating the passive device-integrated substrate according to the embodiment of the disclosure.
  • FIG. 4g is a schematic diagram of the substrate formed in step S14 of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.
  • FIG. 4h is a schematic diagram of the substrate formed in step S15 of the method for fabricating the passive device-integrated substrate according to the embodiment of the disclosure.
  • FIG. 4i is a schematic diagram of the substrate formed in step S16 of the method for fabricating the passive device-integrated substrate according to the embodiment of the disclosure.
  • FIG. 4j is a schematic diagram of the substrate formed in step S17 of the method for preparing a substrate with integrated passive devices according to an embodiment of the disclosure.
  • FIG. 4k is a schematic diagram of the substrate formed in step S18 of the method for fabricating the passive device-integrated substrate according to the embodiment of the disclosure.
  • FIG. 5a is a schematic diagram of a substrate formed in step S21 of a method for manufacturing a substrate integrated with passive devices according to an embodiment of the disclosure.
  • 5b and 5c are schematic diagrams of the substrate formed in step S22 of (1) of the method for fabricating a passive device-integrated substrate according to an embodiment of the present disclosure.
  • FIG. 5d is a schematic diagram of the substrate formed in step S22 (2) of the method for fabricating the passive device-integrated substrate according to the embodiment of the disclosure.
  • FIG. 5e is a schematic diagram of the substrate formed in step S22 (3) of the method for fabricating the passive device-integrated substrate according to the embodiment of the disclosure.
  • FIG. 5f is a schematic diagram of the substrate formed in step S22 (4) of the method for fabricating the passive device-integrated substrate according to the embodiment of the disclosure.
  • FIG. 5g is a schematic diagram of the substrate formed in step S23 of the method for fabricating the passive device-integrated substrate according to the embodiment of the disclosure.
  • FIG. 5h is a schematic diagram of the substrate formed in steps S24-S27 of the method for preparing a substrate with integrated passive devices according to an embodiment of the disclosure.
  • FIG. 5i is a schematic diagram of the substrate formed in step S28 of the method for fabricating the passive device-integrated substrate according to the embodiment of the disclosure.
  • 6a and 6b are schematic diagrams of forming a first connection electrode in another method for fabricating a passive device-integrated substrate according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a substrate integrated with passive devices and a method for fabricating the same.
  • passive devices such as capacitors, inductors, resistors, etc.
  • an LC oscillator circuit integrated on a substrate is taken as an example. That is, at least inductive and capacitive devices are integrated on the substrate. It should be understood that, depending on the function and performance of the circuit, devices such as resistors may also be integrated on the substrate.
  • each first substructure 211 of the inductor extends along the first direction and is arranged side by side along the second direction; and each second substructure 212 of the inductor extends along the first direction. They extend in three directions and are arranged side by side along the second direction.
  • the first direction, the second direction, and the third direction are all different directions.
  • the first direction and the second direction are perpendicular to each other, and the first direction and the third direction intersect and are not perpendicular to each other. example.
  • the inductor includes N first substructures 211 and N ⁇ 1 second substructures 212 as an example for description, where N ⁇ 2, and N is an integer.
  • the first end and the second end of the first substructure 211 are respectively at least partially overlapped with the orthographic projection of a first connection via hole 11 on the glass substrate 10 .
  • the first end and the second end of a first substructure 211 correspond to different first connection vias 11 , that is, a first substructure 211 and two first connection vias 11 are orthographically projected on the glass substrate 10 at least.
  • the first end of the ith second substructure 212 of the inductor is connected to the first end of the ith first substructure 211 and the second end of the i+1th first substructure 211 to form an inductor coil, wherein , 1 ⁇ i ⁇ N-1, and i is an integer.
  • first lead end 22 is connected to the second end of the first first substructure 211 of the inductor coil, and the second lead end 23 is connected to the first end of the Nth first substructure 211 . connect. Further, the first lead terminal 22 and the second lead terminal 23 can be disposed on the same layer as the second sub-structure 212 and use the same material. At this time, the first lead terminal 22 can be connected to the first lead terminal 22 through the first connection via 11 The second end of the first substructure 211 is connected, and correspondingly, the second lead end 23 can be connected to the first end of the Nth first substructure 211 through the first connection via 11 .
  • the LC oscillating circuit includes an inductor and a capacitor 3 ; wherein the inductor includes a plurality of first substructures 211 and a plurality of second substructures 212 and a plurality of first connection electrodes 213; the first substructure 211 and the second substructure 212 are disposed at opposite ends of the first connection electrode 213, and the first connection electrode 213 connects the first substructure 211 and the second substructure 212 to each other connected to form a three-dimensional inductor coil structure (hereinafter referred to as inductor coil).
  • inductor coil three-dimensional inductor coil structure
  • the first lead end 22 of the inductor coil is connected to the first connection pad 41
  • the second lead end 23 of the inductor coil is connected to the first pole plate 31 of the capacitor 3
  • the second pole plate 32 of the capacitor 3 is connected to the second
  • the connection pads 42, the first connection pads 41 and the second connection pads 42 are connected to the positive and negative poles of the current source or the voltage source, respectively.
  • FIG. 3 is a cross-sectional view of a substrate integrated with passive devices according to an embodiment of the present disclosure; as shown in FIG. 3 , in an embodiment of the present disclosure, an LC oscillating circuit is integrated on a transparent medium layer, the transparent medium layer including a thickness of The first surface and the second surface are arranged in opposite directions, and the transparent medium layer has a first connection via hole 11 running through its thickness direction; the first connection electrode 213 of the inductance coil is formed in the first connection via hole 11, and the inductance coil
  • the first substructure 211 is formed on the first surface of the transparent medium layer, and the second substructure 212 of the inductor coil is formed on the second surface of the transparent medium layer.
  • the transparent medium layer includes, but is not limited to, any one of the glass substrate 10 , the flexible substrate, and at least an interlayer medium layer including an organic insulating layer. Since the passive device is integrated on the glass base 10, it has the advantages of small size, light weight, high performance, low power consumption, etc., in the embodiment of the present disclosure, the transparent medium layer preferably adopts the glass base 10.
  • the glass substrate 10 is used as an example for the transparent medium layer to be described.
  • the first plate 31 of the capacitor 3 is disposed on the second surface of the glass base 10, and is disposed on the same layer as the second substructure 212 of the inductor coil, and the first plate 31 of the capacitor 3 is away from the glass base.
  • a first interlayer dielectric layer 9 is provided on one side of
  • a second interlayer dielectric layer 12 is provided on one layer of the electrode plate 32 away from the glass base 10, and a second connection electrode 13 and a connection pad 4 are provided on the side of the second interlayer dielectric layer 12 away from the glass base 10; the second connection The electrode 13 connects the second lead of the inductor coil through the second connection via hole 121 penetrating the first interlayer dielectric layer 9 and the second interlayer dielectric layer 12 and the third connection via hole 122 penetrating the second interlayer dielectric layer 12 .
  • the terminal is connected to the second plate 32 of the capacitor 3 .
  • the connection pad 4 is connected to the first plate 31 of the capacitor 3 .
  • a second protective layer 7 and a second planarization layer 8 may be formed on the side of the first substructure 211 away from the glass substrate 10 to protect the first substructure 211 from water and oxygen corrosion.
  • the first buffer layer 14 and the third planarization layer 15 may also be formed on the side of the second connection electrode 13 and the connection pad 4 away from the glass substrate 10 , so that the connection electrode, the second substructure 212 , the capacitor 3 and other devices for protection.
  • fourth connection vias 16 penetrating the first buffer layer 14 and the third planarization layer 15 are formed at positions corresponding to the connection pads 4 to facilitate signal loading.
  • An embodiment of the present disclosure provides a method for preparing a substrate integrated with passive devices, the substrate may be the above-mentioned substrate, and the preparation method includes the following steps:
  • a glass base 10 is provided, and the glass base 10 is processed to obtain a glass base 10 having a first connection via hole 11 ; the glass base 10 includes a first surface and a second surface oppositely disposed along the thickness direction.
  • Passive devices are integrated on the glass substrate 10; the passive devices include at least an inductor.
  • integrating passive devices on the glass base 10 includes:
  • a first substructure 211 is formed on the first surface of the glass substrate 10, a second substructure 212 is formed on the second surface, and a first connection electrode 213 is formed in the first connection via hole 11; the first substructure 211, the first The connection electrode 213 and the second substructure 212 are connected to form an inductor coil.
  • the method for preparing a substrate with integrated passive devices specifically includes the following steps:
  • step S11 may specifically include the following steps:
  • the glass base 10 enters the cleaning machine for cleaning.
  • the thickness of the glass base 10 is around 0.1 mm-1.1 mm.
  • the first surface of the glass substrate 10 is modified by using a laser with a laser beam vertically incident, so as to form a plurality of first blind holes on the glass substrate 10 .
  • the laser beam interacts with the glass base 10
  • the atoms in the glass base 10 are ionized and ejected from the surface of the glass base 10 due to the high energy of laser photons, and the holes drilled gradually deepen as time increases until the first Blind hole.
  • the generally available laser wavelengths are 532nm, 355nm, 266nm, 248nm, 197nm, etc.
  • the pulse width of the laser can be selected from 1-100fs, 1-100ps, 1-100ns, etc.
  • the type of laser can be selected from continuous laser, pulsed laser, etc. .
  • the methods of laser drilling may include but are not limited to the following two.
  • the first method when the diameter of the light spot is large, the relative position of the laser beam and the glass substrate 10 is fixed, and the glass substrate 10 is directly hit to a preset depth by high energy. At this time, the shape of the first blind hole formed is inverted. The diameter of the circular truncated truncated truncated truncated cone decreases sequentially from top to bottom (the direction from the second surface to the first surface).
  • the laser beam scans in circles on the glass base 10, the focus point of the light spot is constantly changing, and the depth of focus is also changing, from the lower surface (first surface) of the glass base 10 to the glass base 10.
  • a spiral line is drawn on the upper surface (second surface) of the base 10, and the spiral radius decreases sequentially from bottom to top.
  • the glass base 10 is laser-cut into a truncated cone to form a first blind hole, and the shape of the first blind hole is a truncated cone .
  • step S12 may specifically include the following steps:
  • a first metal material 200 is formed on the first surface of the glass substrate 10 by means of measurement and control sputtering, as a seed layer, as shown in FIG. 4 b .
  • the first metal material 200 includes but is not limited to at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal film layer 201 is 100 nm- 500nm or so, and further can be 50nm-35 ⁇ m.
  • the material of the first metal film layer 201 is copper as an example.
  • magnetic A layer of auxiliary metal film is formed by means of controlled sputtering.
  • the material of the auxiliary metal film layer includes but is not limited to at least one of nickel (Ni), molybdenum (Mo) alloy, and titanium (Ti) alloy, such as MoNb, and the thickness of the auxiliary metal film layer is about 2nm-20nm.
  • Electroplating Put the glass base 10 on the carrier of the electroplating machine, press on the power-on pad, put it into the hole-filling electroplating tank (the special hole-filling electrolyte is used in the tank), apply current, and the electroplating solution It is maintained on the first surface of the glass base 10 to flow continuously and rapidly, and the cations in the electroplating solution on the inner wall of the first blind hole obtain electrons and become atoms deposited on the inner wall.
  • metal copper is deposited at a high speed (deposition rate of 0.5-3um/min), while the first surface of the glass substrate 10 is a flat area, and the deposition rate of metal copper on these two surfaces is extremely low ( 0.005-0.05um/min).
  • the metal copper on the inner wall of the first blind hole gradually grows thicker to form the first metal film layer 201.
  • the first metal film layer 201 grows by more than 5 ⁇ m compared with the first metal material 200, as shown in FIG. 4c. Show.
  • the first protective layer 5 is formed on the side of the first metal film layer 201 away from the glass substrate 10 , as shown in FIG. 4d .
  • the material of the first protective layer 5 is an inorganic insulating material.
  • the first protective layer 5 can be an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO 2 ), or an inorganic insulating layer formed of SiNx inorganic insulating layer and SiO 2 inorganic insulating layer.
  • the first planarization layer 6 is formed on the surface of the first protective layer 5 away from the glass substrate 10, as shown in FIG. 4d.
  • the first planarization layer 6 may include an organic insulating material such as polyimide, epoxy, acrylic, polyester, photoresist, polyacrylate, polyamide, silicon oxide Resin materials such as alkane, etc.
  • the organic insulating material includes an elastic material, such as urethane, thermoplastic polyurethane (TPU), and the like.
  • Patterning of the first surface film layer the first planarization layer 6 on the second surface is exposed, developed, and then etched. After etching, the strip is removed and the first protective layer 5 on the first surface is removed. The patterning of the first planarization layer 6 and the first metal film layer 201 is completed. At this time, the first substructure 211 and the first connection electrode 213 of the inductor coil located on the first surface are formed, as shown in FIG. 4e.
  • a second protective layer 7 and a second planarization layer 8 are sequentially formed on the side of the first planarization layer 6 away from the glass substrate 10, as shown in FIG. 4f.
  • the materials of the second protective layer 7 and the first protective layer 5 may be the same, so they are not repeated here.
  • the materials of the second planarization layer 8 and the first planarization layer 6 may be the same, so the detailed description is not repeated here.
  • a pattern including the second substructure 212 of the inductor coil and the first plate 31 of the capacitor 3 is formed through a patterning process, as shown in FIG. 4h.
  • the step S15 may specifically include forming the second metal film layer by means including but not limited to magnetron sputtering, applying glue, exposing, developing, and then performing wet etching, and stripping the glue after the etching, A pattern including the second substructure 212 of the inductor coil and the first plate 31 of the capacitor 3 is formed.
  • the material of the first interlayer dielectric layer 9 is an inorganic insulating material.
  • the first interlayer dielectric layer 9 is an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO 2 ), or an inorganic insulating layer formed of SiNx and SiO 2 .
  • SiNx silicon nitride
  • SiO 2 silicon oxide
  • SiNx and SiO 2 silicon oxide
  • the first interlayer dielectric layer 9 also serves as an intermediate dielectric layer of the capacitor 3 .
  • a third metal film layer can be formed on the side of the first interlayer dielectric layer 9 away from the glass substrate 10 by means of magnetron sputtering, and then glue is applied , exposure, development, and then wet etching. After etching, the strip is removed to form a pattern of the second electrode plate 32 including the capacitor 3 .
  • the material of the second interlayer dielectric layer 12 may be the same as the material of the first interlayer dielectric layer 9 , and thus will not be repeated here.
  • a pattern including the second connection electrode 13 and the connection pad 4 is formed through a patterning process, as shown in FIG. 4k .
  • step S18 may include forming a fourth metal film layer by magnetron sputtering, applying glue, exposing, developing, and then performing wet etching, and stripping the glue after etching to form a second connection including a second connection Pattern of electrodes 13 and connection pads 4 .
  • the material of the fourth metal film layer may be the same as the material of the first metal film layer 201 , and details are not described herein again.
  • the material of the first buffer layer 14 may be the same as the material of the first protective layer 5 , so the details are not repeated here.
  • the material of the third planarization layer 15 may be the same as the material of the first planarization layer 6 , and thus will not be repeated here.
  • the method for preparing a substrate with integrated passive devices specifically includes the following steps:
  • S21 Provide a glass base 10, and perform laser modification on the first surface and the second surface of the glass base 10 by laser, and form a glass base 10 with a first connection via hole 11 by HF etching, as shown in FIG. 5a shown.
  • step S21 may specifically include the following steps:
  • the glass base 10 enters the cleaning machine for cleaning.
  • the thickness of the glass base 10 is around 0.1 mm-1.1 mm.
  • Laser drilling use a laser to modify the first surface of the glass base 10 with a laser beam vertically incident to form a first sub-via on the first surface side of the glass base 10, and also use a laser to The beam hits the second surface of the glass substrate 10 in a way of perpendicular incidence to modify, so as to form a second sub-via on the second surface side of the glass substrate 10, and the second sub-via communicates with the first sub-via to form a first sub-via.
  • the atoms in the glass base 10 are ionized and ejected from the first surface of the glass base 10 due to the high energy of laser photons, and the holes drilled gradually deepen as time increases until the formation of For the first sub-via, the glass substrate 10 is turned over, and the second sub-via is formed according to the same principle.
  • the generally available laser wavelengths are 532nm, 355nm, 266nm, 248nm, 197nm, etc.
  • the pulse width of the laser can be selected from 1-100fs, 1-100ps, 1-100ns, etc.
  • the type of laser can be selected from continuous laser, pulsed laser, etc. .
  • the methods of laser drilling may include but are not limited to the following two.
  • the first method when the diameter of the light spot is large, the relative position of the laser beam and the glass substrate 10 is fixed, and the 10 is directly hit to the preset depth by high energy, and the shape of the first sub-via formed at this time is a rounded truncated , the diameter of the rounded truncated cone decreases sequentially from top to bottom (direction from the second surface to the first surface).
  • the second method when the diameter of the light spot is small, the laser beam scans in circles on the glass base 10, the focus point of the light spot is constantly changing, and the depth of focus is also changing, from the lower surface (first surface) of the glass base 10 to the glass base 10.
  • the upper surface (second surface) of the base 10 draws a spiral line, and the spiral radius decreases sequentially from bottom to top.
  • the glass base 10 is laser-cut into a truncated cone shape to form a first sub-via, and the shape of the first blind hole is The first sub-via hole and the second sub-via hole are formed in the same manner as the first sub-via hole, so the description will not be repeated. It can be seen that the first connection via hole 11 formed by the communication between the first sub-via hole and the second sub-via hole is in the shape of an hourglass.
  • step S22 may specifically include the following steps:
  • Growth seed layer provide a first base substrate 101 , attach the second surface of the glass base 10 to the first substrate of the first base substrate 101 , and pass the magnetron on the second surface of the glass base 10
  • the first metal material 200 is deposited by sputtering, the glass substrate 10 is turned over, and the first metal material 200 is deposited on the first surface by magnetron sputtering. At this time, the sidewall of the first connection via hole 11 is formed
  • a first metal material 200, as a seed layer, is shown in Figures 5b and 5c.
  • the first metal material 200 includes, but is not limited to, at least one of copper copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal material is 100nm-500nm Around, further can be at 50nm-35 ⁇ m.
  • the material of the first metal film layer 201 is copper as an example.
  • magnetic A layer of auxiliary metal film is formed by means of controlled sputtering.
  • the material of the auxiliary metal film layer includes but is not limited to at least one of nickel (Ni), molybdenum (Mo) alloy, and titanium (Ti) alloy, such as MoNb, and the thickness of the auxiliary metal film layer is about 2nm-20nm.
  • the first planarization layer 6 is formed on the surface of the glass substrate 10, and at this time, the first planarization layer 6 fills the first connection vias 11, as shown in FIG. 5e.
  • the first planarization layer 6 may include an organic insulating material such as polyimide, epoxy, acrylic, polyester, photoresist, polyacrylate, polyamide, silicon oxide Resin materials such as alkane, etc.
  • the organic insulating material includes an elastic material, such as urethane, thermoplastic polyurethane (TPU), and the like.
  • Patterning of the first surface film layer exposure and development are performed on the first planarization layer 6 on the first surface, followed by etching, and stripping is performed after etching, and the first planarization layer on the first surface is performed.
  • Layer 6 the patterning of the first metal film layer 201 is completed, and at this time, a first substructure 211 of the inductor coil located on the first surface is formed, as shown in FIG. 5f.
  • the materials of the second planarizing layer 8 and the first planarizing layer 6 may be the same, and thus are not repeated here.
  • the glass base 10 is turned over, the first base substrate 101 is peeled off on the second surface of the glass base 10, and a pattern of the second substructure 212 including the inductor coil and the first plate 31 of the capacitor 3 is formed through a patterning process , as shown in Figure 5h.
  • step S24 may specifically include forming the second metal film layer by means including but not limited to magnetron sputtering, coating, exposing, developing, and then performing wet etching, and stripping the glue after the etching, A pattern including the second substructure 212 of the inductor coil and the first plate 31 of the capacitor 3 is formed.
  • the material of the first interlayer dielectric layer 9 is an inorganic insulating material.
  • the first interlayer dielectric layer 9 is an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO 2 ), or an inorganic insulating layer formed of SiNx and SiO 2 .
  • SiNx silicon nitride
  • SiO 2 silicon oxide
  • SiNx and SiO 2 silicon oxide
  • the first interlayer dielectric layer 9 also serves as an intermediate dielectric layer of the capacitor 3 .
  • the second pole plate 32 of the capacitor 3 can use magnetron sputtering to form a third metal film layer on the side of the first interlayer dielectric layer 9 away from the glass substrate 10, and then perform glue coating, exposure, After developing, wet etching is performed, and after the etching, the strip is removed to form a pattern of the second electrode plate 32 including the capacitor 3 .
  • the material of the second interlayer dielectric layer 12 may be the same as the material of the first interlayer dielectric layer 9 , and thus will not be repeated here.
  • step S27 may include forming a fourth metal film layer by magnetron sputtering, applying glue, exposing, developing, and then performing wet etching, and stripping the glue after etching to form a second connection including a second connection.
  • Pattern of electrodes 13 and connection pads 4 may be the same as the material of the first metal film layer 201 , so it is not repeated here.
  • the material of the first buffer layer 14 may be the same as the material of the first protective layer 5 , so the details are not repeated here.
  • the material of the third planarization layer 15 may be the same as the material of the first planarization layer 6 , and thus will not be repeated here.
  • the preparation method of the passive device-integrated substrate is roughly the same as that of the second example, as shown in Figures 6a and 6b, the difference is only in step S22.
  • step S22 The formed first connection electrode 213 fills the first connection via hole 11 , so the step of forming the first planarization layer 6 is not required, and the remaining steps are the same as the method of the second example, and thus will not be repeated here.

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Abstract

本公开提供一种集成有无源器件的基板及其制备方法，属于射频器件技术领域。本公开的集成有无源器件的基板的制备方法，其包括：提供一透明介质层，并对所述透明介质层进行处理，得到具有第一连接过孔的所述透明介质层；所述透明介质层包括沿厚度方向相对设置的第一表面和第二表面；在所述透明介质层上集成无源器件；所述无源器件至少包括电感；其中，在所述透明介质层上集成所述无源器件包括：在所述透明介质层的第一表面形成第一子结构，在所述第二表面形成第二子结构，并在所述第一连接过孔内形成第一连接电极；所述第一子结构、所述第一连接电极和所述第二子结构连接形成电感的线圈结构。

Description

集成有无源器件的基板及其制备方法 技术领域
本公开属于射频器件技术领域，具体涉及一种集成有无源器件的基板及其制备方法。
背景技术
在当代，消费电子产业发展日新月异，以手机特别是5G手机为代表的移动通信终端发展迅速，手机需要处理的信号频段越来越多，需要的射频芯片数量也水涨船高，而获得消费者喜爱的手机形式向小型化、轻薄化、长续航不断发展。在传统手机中，射频PCB板上存在大量的分立器件如电阻、电容、电感、滤波器等，它们具有体积大、功耗高、焊点多、寄生参数变化大的缺点，难以应对未来的需求。射频芯片相互间的互联、匹配等需要面积小、高性能、一致性好的集成无源器件。目前市场上的集成无源器件主要是基于Si(硅)衬底和GaAs(砷化镓)衬底。Si基集成无源器件具有价格便宜的优点，但Si本身有微量杂质(绝缘性差)导致器件微波损耗较高，性能一般；GaAs基集成无源器件具有性能优良的优点，但价格昂贵。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种集成有无源器件的基板及其制备方法。
第一方面，本公开实施例提供一种集成有无源器件的基板的制备方法，其包括：
提供一透明介质层，并对所述透明介质层进行处理，得到具有第一连接过孔的所述透明介质层；所述透明介质层包括沿厚度方向相对设置的第一表面和第二表面；
在所述透明介质层上集成无源器件；所述无源器件至少包括电感；其中，
在所述透明介质层上集成所述无源器件包括：
在所述透明介质层的第一表面形成第一子结构，在所述第二表面形成第二子结构，并在所述第一连接过孔内形成第一连接电极；所述第一子结构、所述第一连接电极和所述第二子结构连接形成电感的线圈结构。
其中，所述制备方法包括：
提供一透明介质层，并对所述透明介质层进行刻蚀，形成第一盲孔；
通过构图工艺，形成位于第一盲孔内的第一连接电极和第一子结构；
对所述透明介质层背离所述第一子结构的一侧进行减薄处理，裸露出所述第一连接电极，并形成所述第一连接过孔；
在所述透明介质层的第二表面上形成包括所述第二子结构的图形；所述第二子结构、所述第一连接电极和所述第一子结构连接形成电感的线圈结构。
其中，所述提供一透明介质层，并对所述透明介质层进行刻蚀，形成第一盲孔，包括：
对所述透明介质层通过激光改性，并通过HF刻蚀形成所述第一盲孔。
其中，所述通过构图工艺，形成位于第一盲孔内的第一连接电极和第一子结构；
在形成有所述第一盲孔的所述透明介质层上依次衬底第一金属材料，并对所述第一金属材料进行电镀形成第一金属膜层；
在所述第一金属膜层背离所述透明介质层一侧依次形成第一保护层和第一平坦化层，并通过构图工艺形成包括所述第一连接电极和所述第一子结构的图形。
其中，所述制备方法包括：
提供第一衬底基板，并将所述透明介质层贴附在第一衬底基板上；所述透明介质层具有第一连接过孔；
在所述透明介质层的第一表面和第二表面分别沉积第一金属材料，通过电镀工艺，使得所述第一金属材料至少覆盖所述第一连接过孔侧壁，并形成 位于所述第一表面的第一金属膜层；
对所述第一金属膜层进行图案化，形成包括第一子结构的图形；
在所述透明介质层的第二表面上形成包括所述第二子结构的图形；所述第二子结构、所述第一连接电极和所述第一子结构连接形成电感的线圈结构。
其中，提供第一衬底基板，并将所述透明介质层贴附在第一衬底基板上，包括：
分别对所述透明介质层的所述第一表面和第二表面激光改性，并通过HF刻蚀形成所述第一连接过孔。
其中，所述第一金属膜层覆盖所述第一连接过孔侧壁，在所述形成第一金属膜层之前还包括：
在所述第一金属材料背离透明介质层的一侧形成第一平坦化层，以使所述第一平坦化层填充所述第一连接过孔。
其中，在形成所述第一子结构后还包括：
在所述第一子结构背离所述透明介质层的一侧依次形成第二保护层和第二平坦化层。
其中，所述无源器件还包括电容；在所述第二表面形成第二子结构的同时，还形成有所述电容的第一极板；所述制备方法还包括：
在所述电容的第一极板背离所述透明介质层的一侧形成第一层间介质层；
在所述第一层间介质层背离所述透明介质层的一侧形成所述电容的第二极板；
在所述电容的第二极板背离所述透明介质层的一侧形成第二层间介质层，并形成贯穿所述第一层间介质层和所述第二层间介质层的第二连接过孔，以及贯穿所述第二层间介质层的第三连接过孔；
在所述第二层间介质层背离所述透明介质层的一侧形成，通过构图工艺 形成包括第二连接电极和连接焊盘的图形；所述第二连接电极通过所述第二连接过孔和所述第三连接过孔将所述第二子结构和所述电容的第二极板连接。
其中，在所述第二连接电极和连接焊盘所在层背离所述透明介质层的一层，依次沉积第一缓冲层和第三平坦化层，并形成贯穿所述第一缓冲层和所述第三平坦化层的第四连接过孔，且所述第四连接过孔将所述连接焊盘裸露。
其中，所述透明介质层包括玻璃基。
本公开实施例提供一种集成有无源器件的基板，其包括：透明介质层和集成在所述介质层上的无源器件；其中，
所述透明介质层包括沿其厚度方向相对设置的第一表面和第二表面；所述透明介质层上具有沿其厚度方向贯穿的第一连接过孔；
所述无源器件至少包括电感；所述电感包括设置在所述第一表面的第一子结构和设置在所述第二表面的第二子结构，以及设置在所述第一连接过孔中将所述第一子结构和所述第二子结构依次串接的第一连接电极。
其中，所述无源器件还包括电容；其中所述电容的第一极板与所述电感的第二子结构同层设置；所述基板还包括位于所述电容的第一极板背离所述透明介质层一侧的第一层间介质层；所述电容的第二极板位于所述第一层间介质层背离所述电容的第一极板的一侧。
其中，所述透明介质层包括玻璃基。
附图说明
图1为本公开实施例的电感的俯视图.
图2为本公开实施例的LC振荡电路的立体结构示意图.
图3为本公开实施例的集成有无源器件的基板的截面图.
图4a为本公开实施例的集成有无源器件的基板的制备方法的步骤S11所形成基板示意图。
图4b为本公开实施例的集成有无源器件的基板的制备方法的步骤S12中(1)所形成基板示意图。
图4c为本公开实施例的集成有无源器件的基板的制备方法的步骤S12中(2)所形成基板示意图。
图4d为本公开实施例的集成有无源器件的基板的制备方法的步骤S12中(3)和(4)所形成基板示意图。
图4e为本公开实施例的集成有无源器件的基板的制备方法的步骤S12中(5)所形成基板示意图。
图4f为本公开实施例的集成有无源器件的基板的制备方法的步骤S13所形成基板示意图。
图4g为本公开实施例的集成有无源器件的基板的制备方法的步骤S14所形成基板示意图。
图4h为本公开实施例的集成有无源器件的基板的制备方法的步骤S15所形成基板示意图。
图4i为本公开实施例的集成有无源器件的基板的制备方法的步骤S16所形成基板示意图。
图4j为本公开实施例的集成有无源器件的基板的制备方法的步骤S17所形成基板示意图。
图4k为本公开实施例的集成有无源器件的基板的制备方法的步骤S18所形成基板示意图。
图5a为本公开实施例的集成有无源器件的基板的制备方法的步骤S21所形成基板示意图。
图5b和5c为本公开实施例的集成有无源器件的基板的制备方法的步骤S22中(1)所形成基板示意图。
图5d为本公开实施例的集成有无源器件的基板的制备方法的步骤S22中(2)所形成基板示意图。
图5e为本公开实施例的集成有无源器件的基板的制备方法的步骤S22中(3)所形成基板示意图。
图5f为本公开实施例的集成有无源器件的基板的制备方法的步骤S22中(4)所形成基板示意图。
图5g为本公开实施例的集成有无源器件的基板的制备方法的步骤S23所形成基板示意图。
图5h为本公开实施例的集成有无源器件的基板的制备方法的步骤S24-S27所形成基板示意图。
图5i为本公开实施例的集成有无源器件的基板的制备方法的步骤S28所形成基板示意图。
[根据细则91更正 30.06.2021]　
图6a和6b为本公开实施例的另一种集成有无源器件的基板的制备方法中形成第一连接电极的示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开实施例提供一种集成有无源器件的基板及其制备方法。其中，无源器件如电容、电感、电阻等，集成在基板上形成电路结构。在本公开实施 例中以基板上集成LC振荡电路为例。也就是说，在基板上至少集成有电感和电容器件。应当理解的是，根据电路功能和性能，在基板上还可以集成有电阻等器件。
图1为本公开实施例的电感的俯视图，参照图1，电感的各第一子结构211均沿第一方向延伸，且沿第二方向并排设置；电感的各第二子结构212均沿第三方向延伸，且沿第二方向并排设置。其中，第一方向、第二方向、第三方向均为不同的方向，在本公开实施例中，以第一方向和第二方向相互垂直，第一方向和第三方向相交且非垂直设置为例。当然，第一子结构211和第二子结构212的延伸方向也可以互换，均在本公开实施例的保护范围内。另外，在本公实施例中以电感包括N个第一子结构211和N-1个第二子结构212为例进行说明，其中，N≥2，且N为整数。第一子结构211的第一端和第二端分别与一个第一连接过孔11在玻璃基10上正投影至少部分交叠。且一个第一子结构211的第一端和第二端对应不同的第一连接过孔11，也即一个第一子结构211与两个第一连接过孔11在玻璃基10上正投影至少部分交叠。此时，电感的第i个第二子结构212第一端连接第i个第一子结构211的第一端和第i+1个第一子结构211的第二端，形成电感线圈，其中，1≤i≤N-1，且i为整数。
在此需要说明的是，其中，第一引线端22与电感线圈的第一个第一子结构211的第二端，第二引线端23则与第N个第一子结构211的第一端连接。进一步的，第一引线端22和第二引线端23可以与第二子结构212同层设置，且采用相同的材料，此时第一引线端22可以通过第一连接过孔11与第一个第一子结构211的第二端连接，相应的，第二引线端23则可以通过第一连接过孔11与第N个第一子结构211的第一端连接。
图2为本公开实施例的LC振荡电路的立体结构示意图；如图2所示，LC振荡电路包括电感和电容3；其中，电感包括多个第一子结构211、多个第二子结构212和多个第一连接电极213；第一子结构211、第二子结构212设置在第一连接电极213的相对端，且第一连接电极213将第一子结构211和第二子结构212彼此连接，形成立体电感线圈结构(以下简称电感线圈)。 继续参照图2，电感线圈的第一引线端22连接第一连接焊盘41，电感线圈的第二引线端23连接电容3的第一极板31，电容3的第二极板32与第二连接焊盘42，第一连接焊盘41和第二连接焊盘42与分别电流源或者电压源的正、负极连接。
图3为本公开实施例的集成有无源器件的基板的截面图；如图3所示，在本公开实施例中，LC振荡电路集成在透明介质层上，该透明介质层包括沿其厚度方向相对设置的第一表面和第二表面，且该透明介质层具有贯穿其厚度方向的第一连接过孔11；电感线圈的第一连接电极213形成在第一连接过孔11中，电感线圈的第一子结构211形成在透明介质层的第一表面，电感线圈的第二子结构212形成在透明介质层的第二表面。
其中，在本公开实施例中透明介质层包括但不限于玻璃基10、柔性衬底、至少包括有机绝缘层的层间介质层中的任意一种。由于将无源器件集成在玻璃基10上，具有体积小、重量轻、高性能、低功耗等优点，在本公开实施例中透明介质层优选采用玻璃基10。以下，以透明介质层采用玻璃基10为例进行说明。
继续参照图3，电容3的第一极板31设置在玻璃基10的第二表面上，且与电感线圈的第二子结构212同层设置，在电容3的第一极板31背离玻璃基10的一侧设置第一层间介质层9，并在第一层间介质层9背离电容3的第一极板31的一侧设置电容3的第二极板32；在电容3的第二极板32背离玻璃基10的一层设置第二层间介质层12，在第二层间介质层12背离玻璃基10的一侧设置有第二连接电极13和连接焊盘4；第二连接电极13通过贯穿第一层间介质层9和第二层间介质层12的第二连接过孔121、以及贯穿第二层间介质层12的第三连接过孔122将电感线圈的第二引线端和电容3的第二极板32连接。连接焊盘4与电容3的第一极板31连接。
继续参照3，在第一子结构211背离玻璃基10的一侧可以形成第二保护层7和第二平坦化层8，以对第一子结构211进行保护，防止水氧侵蚀。相应的，在第二连接电极13和连接焊盘4背离玻璃基10的一侧还可以形成第一缓冲层14和第三平坦化层15，以对连接电极、第二子结构212、电容3 等器件进行保护。需要注意的是，在与连接焊盘4对应的位置形成贯穿第一缓冲层14和第三平坦化层15的第四连接过孔16，以便于加载信号。
对于本公开实施例的集成有无源器件的基板上的各个器件的结构参数，在下述制备方法中逐一进行说明，故在此不进行详细描述。
本公开实施例中提供一种集成有无源器件的基板的制备方法，该基板可以为上述的基板，该制备方法包括如下步骤：
提供一玻璃基10，并对玻璃基10进行处理，得到具有第一连接过孔11的玻璃基10；玻璃基10包括沿厚度方向相对设置的第一表面和第二表面。
在玻璃基10上集成无源器件；无源器件至少包括电感。
其中，在玻璃基10上集成无源器件包括：
在玻璃基10的第一表面形成第一子结构211，在第二表面形成第二子结构212，并在第一连接过孔11内形成第一连接电极213；第一子结构211、第一连接电极213和第二子结构212连接形成电感线圈。
为了清楚本公开实施例中的制备方法，以下结合附图和具体实施例对本公开实施例中的集成有无源器件的基板的制备方法进行说明。
第一种示例，该集成有无源器件的基板的制备方法具体包括如下步骤：
S11、提供一透明介质层，并对所述透明介质层进行刻蚀，形成第一盲孔，如图4a所示。
在一些示例中，步骤S11具体可以包括如下步骤：
(1)清洗：玻璃基10进入清洗机进行清洗。
在一些示例中，玻璃基10的厚度在0.1mm-1.1mm左右。
(2)激光打孔：使用激光器以激光束垂直入射的方式打到玻璃基10的第一表面改性，以在玻璃基10上形成多个第一盲孔。具体的，在激光束与玻璃基10相互作用时，因激光光子能量较高将玻璃基10中的原子电离化并抛射出玻璃基10表面，随时间增加打的孔逐渐加深，直至形成第一盲孔。其中，一般可选用的激光波长为532nm、355nm、266nm、248nm、197nm 等，激光的脉冲宽度可选1-100fs、1-100ps、1-100ns等，激光器的类型可选连续激光器、脉冲激光器等。激光打孔的方式可以包括但不限于如下两种。第一种方式，当光斑直径较大时，激光束和玻璃基10的相对位置固定，依靠高能量直接把玻璃基10打到预设深度，此时所形成的第一盲孔的形状是倒圆台，倒圆台的直径自上而下(由第二表面指向第一表面的方向)依次减小。第二种方式，当光斑直径较小时，激光束在玻璃基10上画圈扫描，光斑聚焦点在不断变化，聚焦焦点深度也在不断变化，自玻璃基10下表面(第一表面)向玻璃基10上表面(第二表面)画螺旋线，且螺旋半径自下而上依次减小，玻璃基10被激光切割成圆台型，以形成第一盲孔，该第一盲孔的形状为圆台。
(3)HF刻蚀：由于在激光打孔过程会在第一盲孔内壁上表面靠近孔的区域约5-20微米范围内形成应力区，该区域内玻璃基10表面凹凸不平呈现熔融态多毛刺，且存在大量的微裂纹和宏观裂缝，并存在有残余应力。此时，使用2％-20％的HF刻蚀液，在适当温度下，进行一定时间的湿法刻蚀，将应力区的玻璃刻蚀掉，使第一盲孔内部和表面靠近孔的区域光滑平整，不存在微裂纹、宏观裂缝，并将应力区完全刻蚀掉。
S12、通过构图工艺，形成位于第一盲孔内的第一连接电极213和第一子结构211。
在一些示例中，步骤S12具体可以包括如下步骤：
(1)生长种子层：在玻璃基10的第一表面通过测控溅射的方式形成第一金属材料200，作为种子层，如图4b所示。
在一些示例中，第一金属材料200包括但不限于铜(Cu)、铝(Al)、钼(Mo)、银(Ag)中的至少一种，第一金属膜层201的厚度在100nm-500nm左右，进一步的可以在50nm-35μm。在以下描述中以第一金属膜层201的材料为铜为例。
在一些示例中，为了增加第一金属材料200与玻璃基10的第一表面的附着力，在形成第一金属材料200之前可以先在玻璃基10的第一表面上， 通过包括但不限于磁控溅射的方式形成一层辅助金属膜层。该辅助金属膜层的材料包括但不限于镍(Ni)、钼(Mo)合金，钛(Ti)合金中至少一种，例如采用MoNb，辅助金属膜层的厚度在2nm-20nm左右。
(2)电镀：将玻璃基10放入电镀机台载具上，压上加电焊盘(pad)，放入填孔电镀槽(槽中使用专用填孔电解液)中，加电流，电镀液保持在玻璃基10第一表面持续快速流动，在第一盲孔内壁上电镀液中的阳离子获得电子，成为原子淀积在内壁上，通过特殊配比的专用填孔电解液，可以做到主要在第一盲孔内高速淀积金属铜(淀积速度0.5-3um/min)，而在玻璃基10的第一表面为平整区域，这两个表面上的金属铜的淀积速度极小(0.005-0.05um/min)。随时间增加，第一盲孔的内壁上的金属铜逐渐长厚，形成第一金属膜层201，此时第一金属膜层201相较于第一金属材料200生长5μm以上，如图4c所示。
(3)保护层的形成：在第一金属膜层201背离玻璃基10的一侧形成第一保护层5，如图4d所示。该第一保护层5的材料为无机绝缘材料。例如：第一保护层5可以为由氮化硅(SiNx)形成的无机绝缘层，或者由氧化硅(SiO 2)形成的无机绝缘层，亦或者由SiNx无机绝缘层和SiO 2无机绝缘层的若干种叠层组合膜层。
(4)第一平坦化层6的形成：在第一保护层5背离玻璃基10的表面形成第一平坦化层6，如图4d。该第一平坦化层6可以包括有机绝缘材料，该有机绝缘材料例如包括聚酰亚胺、环氧树脂、压克力、聚酯、光致抗蚀剂、聚丙烯酸酯、聚酰胺、硅氧烷等树脂类材料等。再例如，该有机绝缘材料包括弹性材料，例如、氨基甲酸乙酯、热塑性聚氨酯(TPU)等。
(5)第一表面膜层图案化：在第二表面的第一平坦化层6、曝光、显影，随后进行刻蚀，刻蚀完后strip去胶，第一表面上的第一保护层5、第一平坦化层6、第一金属膜层201图案化完成，此时形成位于第一表面的电感线圈的第一子结构211和第一连接电极213，如图4e所示。
S13、在第一平坦化层6背离玻璃基10的一侧依次形成第二保护层7和 第二平坦化层8，如图4f所示。其中，第二保护层7与第一保护层5的材料可以相同，故在此不再重复赘述。第二平坦化层8与第一平坦化层6的材料可以相同，故在此不再重复赘述。
S14、将第一平坦化层6与第一衬底基板101绑定在一起，将玻璃基10进行翻转，对玻璃基10背离所述第一子结构211的一侧进行减薄处理，裸露出所述第一连接电极213，并形成所述第一连接过孔11，如图4g所示。
S15、在玻璃基10的第二表面上，通过构图工艺形成包括电感线圈的第二子结构212和电容3的第一极板31图形，如图4h所示。
在一些示例中，步骤S15具体可以包括通过包括但不限于磁控溅射的方式形成第二金属膜层，涂胶、曝光、显影，随后进行湿法刻蚀，刻蚀完后strip去胶，形成包括电感线圈的第二子结构212和电容3的第一极板31的图形。
S16、在电感线圈的第二子结构212和电容3的第一极板31背离玻璃基10的一侧形成第一层间介质层9，并在第一层间介质层9背离玻璃基10的一侧形成包括电容3的第二极板32图形，如图4i所示。
在一些示例中，第一层间介质层9的材料为无机绝缘材料。例如：第一层间介质层9为由氮化硅(SiNx)形成的无机绝缘层，或者由氧化硅(SiO 2)形成的无机绝缘层，亦或者由SiNx无机绝缘层和SiO 2无机绝缘层的若干种叠层组合膜层。当然，该第一层间介质层9也作为电容3的中间介质层。
在一些示例中，电容3的第二极板32的形成，可以采用磁控溅射的方式在第一层间介质层9背离玻璃基10的一侧形成第三金属膜层，然后进行涂胶、曝光、显影，随后进行湿法刻蚀，刻蚀完后strip去胶，形成包括电容3的第二极板32的图形。
S17、在电容3的第二极板32背离玻璃基10的一侧形成第二层间介质层12，并形成贯穿第一层介质层和第二层间介质层12的第二连接过孔121，以及贯穿第二层间介质层12的第三连接过孔122，如图4j所示。
其中，第二层间介质层12的材料可以与第一层间介质层9的材料相同，故在此不再重复赘述。
S18、在第二层间介质层12背离玻璃基10的一侧，通过构图工艺形成包括第二连接电极13和连接焊盘4的图形，如图4k所示。
在一些示例中，步骤S18可以包括通过磁控溅射的方式形成第四金属膜层，涂胶、曝光、显影，随后进行湿法刻蚀，刻蚀完后strip去胶，形成包括第二连接电极13和连接焊盘4的图形。其中，第四金属膜层的材料可以与第一金属膜层201的材料相同，故在此不再赘述。
S19、在第二连接电极13和连接焊盘4所在层背离玻璃基10的一侧，依次沉积第一缓冲层14和第三平坦化层15，并将第一衬底基板101剥离，如图3所示。
在一些示例中，第一缓冲层14的材料可以与第一保护层5的材料相同，故在此不再重复赘述。第三平坦化层15的材料可以与第一平坦化层6的材料相同，故在此不再重复赘述。
至此完成集成无源器件的基板的制备。
第二个示例，该集成有无源器件的基板的制备方法，具体包括如下步骤：
S21、提供一玻璃基10，并通过激光对分别玻璃基10的第一表面和第二表面进行激光改性，并通过HF刻蚀形成具有第一连接过孔11的玻璃基10，如图5a所示。
在一些示例中，步骤S21具体可以包括如下步骤：
(1)清洗：玻璃基10进入清洗机进行清洗。
在一些示例中，玻璃基10的厚度在0.1mm-1.1mm左右。
(2)激光打孔：使用激光器以激光束垂直入射的方式打到玻璃基10的第一表面改性，以在玻璃基10的第一表面侧形成第一子过孔，同样使用激光器以激光束垂直入射的方式打到玻璃基10的第二表面改性，以在玻璃基10的第二表面侧形成第二子过孔，第二子过孔和第一子过孔相通，形成第一连接过孔11。
具体的，在激光束与玻璃基10相互作用时，因激光光子能量较高将玻 璃基10中的原子电离化并抛射出玻璃基10第一表面，随时间增加打的孔逐渐加深，直至形成第一子过孔，将玻璃基10翻转，按照同样的原理形成第二子过孔。其中，一般可选用的激光波长为532nm、355nm、266nm、248nm、197nm等，激光的脉冲宽度可选1-100fs、1-100ps、1-100ns等，激光器的类型可选连续激光器、脉冲激光器等。激光打孔的方式可以包括但不限于如下两种。第一种方式，当光斑直径较大时，激光束和玻璃基10的相对位置固定，依靠高能量直接把10打到预设深度，此时所形成的第一子过孔的形状是倒圆台，倒圆台的直径自上而下(由第二表面指向第一表面的方向)依次减小。第二种方式，当光斑直径较小时，激光束在玻璃基10上画圈扫描，光斑聚焦点在不断变化，聚焦焦点深度也在不断变化，自玻璃基10下表面(第一表面)向玻璃基10上表面(第二表面)画螺旋线，且螺旋半径自下而上依次减小，玻璃基10被激光切割成圆台型，以形成第一子过孔，该第一盲孔的形状为第一子过孔；第二子过孔与第一子过孔的形成方式相同，故不再重复赘述。可以看出的是，第一子过孔和第二子过孔相通形成的第一连接过孔11呈沙漏状。
(3)HF刻蚀：由于在激光打孔过程会在第一连接过孔11内壁上表面靠近孔的区域约5-20微米范围内形成应力区，该区域内玻璃基10表面凹凸不平呈现熔融态多毛刺，且存在大量的微裂纹和宏观裂缝，并存在有残余应力。此时，使用2％-20％的HF刻蚀液，在适当温度下，进行一定时间的湿法刻蚀，将应力区的玻璃刻蚀掉，使第一连接过孔11内部和表面靠近孔的区域光滑平整，不存在微裂纹、宏观裂缝，并将应力区完全刻蚀掉。
S22、通过构图工艺，形成位于第一连接过孔11的第一连接电极213和第一子结构211。
在一些示例中，步骤S22具体可以如下步骤：
(1)生长种子层：提供一第一衬底基板101，将玻璃基10的第二表面与第一衬底基板101第一衬底相贴附，在玻璃基10的第二表面通过磁控溅射的方式沉积第一金属材料200，将玻璃基10翻转，在第一表面通过磁控溅射的方式沉积第一金属材料200，此时在，第一连接过孔11的侧壁上形成 第一金属材料200，作为种子层如图5b和5c所示。
在一些示例中，第一金属材料200包括但不限于铜铜(Cu)、铝(Al)、钼(Mo)、银(Ag)中的至少一种，第一金属材料的厚度在100nm-500nm左右，进一步的可以在50nm-35μm。在以下描述中以第一金属膜层201的材料为铜为例。
在一些示例中，为了增加第一金属材料200与玻璃基10的第一表面的附着力，在形成第一金属材料200之前可以先在玻璃基10的第一表面上，通过包括但不限于磁控溅射的方式形成一层辅助金属膜层。该辅助金属膜层的材料包括但不限于镍(Ni)、钼(Mo)合金，钛(Ti)合金中至少一种，例如采用MoNb，辅助金属膜层的厚度在2nm-20nm左右。
(2)电镀：将玻璃基10放入电镀机台载具上，压上加电焊盘(pad)，放入填孔电镀槽(槽中使用专用填孔电解液)中，加电流，电镀液保持在玻璃基10第一表面持续快速流动，在第一连接过孔11内壁上电镀液中的阳离子获得电子，成为原子淀积在内壁上，通过特殊配比的专用填孔电解液，可以做到主要在第一盲孔内高速淀积金属铜(淀积速度0.5-3um/min)，而在玻璃基10的第一表面为平整区域，这两个表面上的金属铜的淀积速度极小(0.005-0.05um/min)。随时间增加，第一连接孔的内壁上的金属铜逐渐长厚，形成第一金属膜层201，此时第一金属膜层201相较于第一金属材料200生长5μm以上。此时，第一金属膜层201并填充满第一连接过孔11，如图5d所示。
(3)第一平坦化层6的形成：玻璃基10的表面形成第一平坦化层6，此时第一平坦化层6将第一连接过孔11填充满，如图5e所示。该第一平坦化层6可以包括有机绝缘材料，该有机绝缘材料例如包括聚酰亚胺、环氧树脂、压克力、聚酯、光致抗蚀剂、聚丙烯酸酯、聚酰胺、硅氧烷等树脂类材料等。再例如，该有机绝缘材料包括弹性材料，例如、氨基甲酸乙酯、热塑性聚氨酯(TPU)等。
(4)第一表面膜层图案化：在第一表面的第一平坦化层6上进行曝光、 显影，随后进行刻蚀，刻蚀完后strip去胶，第一表面上的第一平坦化层6、第一金属膜层201图案化完成，此时形成位于第一表面的电感线圈的第一子结构211，如图5f所示。
S23、在第一平坦化层6背离玻璃基10的一侧形成第二平坦化层8，并在第二平坦化层8背离玻璃基10的一侧贴附第二衬底基板102，如图5g所示。
其中，第二平坦化层8与第一平坦化层6的材料可以相同，故在此不再重复赘述。
S24、将玻璃基10进行翻转，将第一衬底基板101剥离在玻璃基10的第二表面上，通过构图工艺形成包括电感线圈的第二子结构212和电容3的第一极板31图形，如图5h所示。
在一些示例中，步骤S24具体可以包括通过包括但不限于磁控溅射的方式形成第二金属膜层，涂胶、曝光、显影，随后进行湿法刻蚀，刻蚀完后strip去胶，形成包括电感线圈的第二子结构212和电容3的第一极板31的图形。
S25、在电感线圈的第二子结构212和电容3的第一极板31背离玻璃基10的一侧形成第一层间介质层9，并在第一层间介质层9背离玻璃基10的一侧形成包括电容3的第二极板32图形，如图5h所示。
在一些示例中，第一层间介质层9的材料为无机绝缘材料。例如：第一层间介质层9为由氮化硅(SiNx)形成的无机绝缘层，或者由氧化硅(SiO 2)形成的无机绝缘层，亦或者由SiNx无机绝缘层和SiO 2无机绝缘层的若干种叠层组合膜层。当然，该第一层间介质层9也作为电容3的中间介质层。
在一些示例中，电容3的第二极板32可以采用磁控溅射的方式在第一层间介质层9背离玻璃基10的一侧形成第三金属膜层，然后进行涂胶、曝光、显影，随后进行湿法刻蚀，刻蚀完后strip去胶，形成包括电容3的第二极板32的图形。
S26、在电容3的第二极板32背离玻璃基10的一侧形成第二层间介质层12，并形成贯穿第一层间介质层9和第二层间介质层12的第二连接过孔 121，以及贯穿第二层间介质层12的第三连接过孔122，如图5h所示。
其中，第二层间介质层12的材料可以与第一层间介质层9的材料相同，故在此不再重复赘述。
S27、在第二层间介质层12背离玻璃基10的一侧，通过构图工艺形成包括第二连接电极13和连接焊盘4的图形，如图5h所示。
在一些示例中，步骤S27可以包括通过磁控溅射的方式形成第四金属膜层，涂胶、曝光、显影，随后进行湿法刻蚀，刻蚀完后strip去胶，形成包括第二连接电极13和连接焊盘4的图形。其中，第四金属膜层的材料可以与第一金属膜层201的材料相同，故在此不再赘述。
S28、在第二连接电极13和连接焊盘4所在层背离玻璃基10的一侧，依次沉积第一缓冲层14和第三平坦化层15，并将第二衬底基板102剥离，如图5i所示。
在一些示例中，第一缓冲层14的材料可以与第一保护层5的材料相同，故在此不再重复赘述。第三平坦化层15的材料可以与第一平坦化层6的材料相同，故在此不再重复赘述。
至此完成集成无源器件的基板的制备。
第三种示例，该集成有无源器件的基板的制备方法与第二种示例的方法大致相同，如图6a和6b所示，区别仅在于步骤S22，在该方法中步骤S22在电镀时，所形成第一连接电极213填充第一连接过孔11，因此无需形成第一平坦化层6的步骤，其余步骤均与第二种示例的方法，故在此不再重复赘述。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (14)

  1. 一种集成有无源器件的基板的制备方法，其包括：
    提供一透明介质层，并对所述透明介质层进行处理，得到具有第一连接过孔的所述透明介质层；所述透明介质层包括沿厚度方向相对设置的第一表面和第二表面；
    在所述透明介质层上集成无源器件；所述无源器件至少包括电感；其中，
    在所述透明介质层上集成所述无源器件包括：
    在所述透明介质层的第一表面形成第一子结构，在所述第二表面形成第二子结构，并在所述第一连接过孔内形成第一连接电极；所述第一子结构、所述第一连接电极和所述第二子结构连接形成电感的线圈结构。
  2. 根据权利要求1所述的制备方法，其中，所述制备方法包括：
    提供一透明介质层，并对所述透明介质层进行刻蚀，形成第一盲孔；
    通过构图工艺，形成位于第一盲孔内的第一连接电极和第一子结构；
    对所述透明介质层背离所述第一子结构的一侧进行减薄处理，裸露出所述第一连接电极，并形成所述第一连接过孔；
    在所述透明介质层的第二表面上形成包括所述第二子结构的图形；所述第二子结构、所述第一连接电极和所述第一子结构连接形成电感的线圈结构。
  3. 根据权利要求2所述的制备方法，其中，所述提供一透明介质层，并对所述透明介质层进行刻蚀，形成第一盲孔，包括：
    对所述透明介质层通过激光改性，并通过HF刻蚀形成所述第一盲孔。
  4. 根据权利要求2所述的制备方法，其中，所述通过构图工艺，形成位于第一盲孔内的第一连接电极和第一子结构；
    在形成有所述第一盲孔的所述透明介质层上依次衬底第一金属材料，并对所述第一金属材料进行电镀形成第一金属膜层；
    在所述第一金属膜层背离所述透明介质层一侧依次形成第一保护层和 第一平坦化层，并通过构图工艺形成包括所述第一连接电极和所述第一子结构的图形。
  5. 根据权利要求1所述的制备方法，其中，所述制备方法包括：
    提供第一衬底基板，并将所述透明介质层贴附在第一衬底基板上；所述透明介质层具有第一连接过孔；
    在所述透明介质层的第一表面和第二表面分别沉积第一金属材料，通过电镀工艺，使得所述第一金属材料至少覆盖所述第一连接过孔侧壁，并形成位于所述第一表面的第一金属膜层；
    对所述第一金属膜层进行图案化，形成包括第一子结构的图形；
    在所述透明介质层的第二表面上形成包括所述第二子结构的图形；所述第二子结构、所述第一连接电极和所述第一子结构连接形成电感的线圈结构。
  6. 根据权利要求5所述的制备方法，其中，提供第一衬底基板，并将所述透明介质层贴附在第一衬底基板上，包括：
    分别对所述透明介质层的所述第一表面和第二表面激光改性，并通过HF刻蚀形成所述第一连接过孔。
  7. 根据权利要求5所述的制备方法，其中，所述第一金属膜层覆盖所述第一连接过孔侧壁，在所述形成第一金属膜层之前还包括：
    在所述第一金属材料背离透明介质层的一侧形成第一平坦化层，以使所述第一平坦化层填充所述第一连接过孔。
  8. 根据权利要求1-7中任一项所述的制备方法，其中，在形成所述第一子结构后还包括：
    在所述第一子结构背离所述透明介质层的一侧依次形成第二保护层和第二平坦化层。
  9. 根据权利要求1-7中任一项所述的制备方法，其中，所述无源器件还包括电容；在所述第二表面形成第二子结构的同时，还形成有所述电容的第 一极板；所述制备方法还包括：
    在所述电容的第一极板背离所述透明介质层的一侧形成第一层间介质层；
    在所述第一层间介质层背离所述透明介质层的一侧形成所述电容的第二极板；
    在所述电容的第二极板背离所述透明介质层的一侧形成第二层间介质层，并形成贯穿所述第一层间介质层和所述第二层间介质层的第二连接过孔，以及贯穿所述第二层间介质层的第三连接过孔；
    在所述第二层间介质层背离所述透明介质层的一侧形成，通过构图工艺形成包括第二连接电极和连接焊盘的图形；所述第二连接电极通过所述第二连接过孔和所述第三连接过孔将所述第二子结构和所述电容的第二极板连接。
  10. 根据权利要求9所述的制备方法，其中，在所述第二连接电极和连接焊盘所在层背离所述透明介质层的一层，依次沉积第一缓冲层和第三平坦化层，并形成贯穿所述第一缓冲层和所述第三平坦化层的第四连接过孔，且所述第四连接过孔将所述连接焊盘裸露。
  11. 根据权利要求1-10中任一项所述的制备方法，其中，所述透明介质层包括玻璃基。
  12. 一种集成有无源器件的基板，其包括：透明介质层和集成在所述介质层上的无源器件；其中，
    所述透明介质层包括沿其厚度方向相对设置的第一表面和第二表面；所述透明介质层上具有沿其厚度方向贯穿的第一连接过孔；
    所述无源器件至少包括电感；所述电感包括设置在所述第一表面的第一子结构和设置在所述第二表面的第二子结构，以及设置在所述第一连接过孔中将所述第一子结构和所述第二子结构依次串接的第一连接电极。
  13. 根据权利要求12所述的基板，其中，所述无源器件还包括电容；其中所述电容的第一极板与所述电感的第二子结构同层设置；所述基板还包 括位于所述电容的第一极板背离所述透明介质层一侧的第一层间介质层；所述电容的第二极板位于所述第一层间介质层背离所述电容的第一极板的一侧。
  14. 根据权利要求12或13所述的基板，其中，所述透明介质层包括玻璃基。
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