WO2024020819A1 - 功能基板及其制备方法、电子设备 - Google Patents

功能基板及其制备方法、电子设备 Download PDF

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Publication number
WO2024020819A1
WO2024020819A1 PCT/CN2022/108091 CN2022108091W WO2024020819A1 WO 2024020819 A1 WO2024020819 A1 WO 2024020819A1 CN 2022108091 W CN2022108091 W CN 2022108091W WO 2024020819 A1 WO2024020819 A1 WO 2024020819A1
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Prior art keywords
hole
connection
sub
layer
functional substrate
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PCT/CN2022/108091
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English (en)
French (fr)
Inventor
安齐昌
吴艺凡
肖月磊
李月
冯昱霖
李慧颖
李必奇
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002388.1A priority Critical patent/CN117836943A/zh
Priority to PCT/CN2022/108091 priority patent/WO2024020819A1/zh
Publication of WO2024020819A1 publication Critical patent/WO2024020819A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate

Definitions

  • the present disclosure belongs to the technical field of electronic components, and specifically relates to a functional substrate, a preparation method thereof, and electronic equipment.
  • Si-based integrated passive devices have the advantage of being cheap, but Si itself has trace impurities (poor insulation), resulting in high microwave loss and average performance of the device; GaAs-based integrated passive devices have the advantage of excellent performance, but are expensive.
  • the present invention aims to solve at least one of the technical problems existing in the prior art and provide a functional substrate, a preparation method thereof, and electronic equipment.
  • an embodiment of the present disclosure provides a functional substrate, which includes a first dielectric substrate; wherein the first dielectric substrate includes a first surface and a second surface that are oppositely arranged along its thickness direction; the first dielectric substrate The substrate has a first connection hole; the first connection hole at least penetrates the first surface; a first connection electrode is provided in the first connection hole;
  • the first connection hole includes a first sub-hole and a second sub-hole that are sequentially arranged and connected in a direction away from the second surface; the second sub-hole penetrates the first surface;
  • the opening width of the second sub-hole increases monotonically in a direction away from the second surface, and the minimum opening width of the second sub-hole is not less than the maximum opening width of the first sub-hole;
  • the connection position between one sub-hole and the second sub-hole forms a corner.
  • the first connection hole penetrates the first surface and the second surface
  • the first connection via hole also includes a third sub-hole connected to the first sub-hole and penetrating the second surface;
  • the opening width of the third sub-hole decreases monotonically in a direction away from the second surface, and the minimum opening width of the third sub-hole is not less than the maximum opening width of the first sub-hole;
  • the connection position between one sub-hole and the third sub-hole forms a corner.
  • the first sub-hole penetrates the second surface.
  • the first sub-hole is hourglass-shaped.
  • the opening width of the first sub-hole increases monotonically in a direction away from the second surface.
  • the first connection electrode fills the first connection hole or only covers the inner wall of the first connection hole.
  • the functional substrate further includes a first conductive layer located on the first surface and connected to the first connection electrode.
  • the first connection hole penetrates the second surface
  • the functional substrate further includes a second conductive layer located on the second surface, and the second conductive layer is connected to the first connection electrode.
  • the functional substrate further includes an inductor integrated on the first dielectric substrate, the inductor includes a first substructure, a second substructure and a plurality of first connection electrodes; the first substructure is located on The first surface, the second substructure are located on the second surface, and the first substructure is connected to the second substructure through the first connection electrode to form a coil structure of the inductor.
  • the functional substrate further includes a first plate of a capacitor located on the first conductive layer; a first interlayer dielectric layer is formed on a side of the first conductive layer facing away from the first dielectric substrate; A second plate of a capacitor is provided on a side of the first interlayer dielectric layer away from the first conductive layer.
  • the functional substrate further includes a second interlayer dielectric layer, a second connection electrode and a third connection electrode arranged on a side of the second plate of the capacitor facing away from the first dielectric substrate;
  • the second connection electrode is connected to the lead end of the inductor through a second connection hole penetrating the first interlayer dielectric layer and the second interlayer dielectric layer; the third connection electrode passes through the second interlayer dielectric layer.
  • the third connection hole in the interlayer is electrically connected to the second plate of the capacitor.
  • the functional substrate further includes a first protective layer and a first planarization layer arranged in sequence on a side of the layer where the second connection electrode and the third connection electrode are located away from the first dielectric substrate, and a first connection pad and a second connection pad;
  • the first connection pad is connected to the second connection electrode through a fourth connection hole, and the second connection pad is connected to the third connection electrode through a fifth connection hole; the fourth connection hole and the third connection electrode
  • the five connection holes all penetrate the first protective layer and the first planarization layer.
  • the functional substrate further includes a second protective layer and a second planarization layer arranged sequentially on a side of the second conductive layer facing away from the first dielectric substrate.
  • the first connection hole penetrates the second surface;
  • the functional substrate further includes a first conductive layer disposed on the first surface and a second conductive layer disposed on the second surface, so The first conductive layer and the second conductive layer are connected through the first connection hole; a first buffer layer is provided between the first conductive layer and the first surface; the second conductive layer A second buffer layer is provided between the second surface and the second surface.
  • An embodiment of the present disclosure also provides a method for preparing a functional substrate, which includes:
  • the first dielectric substrate includes a first surface and a second surface arranged oppositely along its thickness direction;
  • a first connection hole is formed on the first dielectric substrate; the first connection hole at least penetrates the first surface; the first connection hole includes connected holes arranged sequentially in a direction away from the second surface.
  • the minimum opening width of the second sub-hole is not less than the maximum opening width of the first sub-hole; the connection position of the first sub-hole and the second sub-hole forms a corner;
  • a first connection electrode located in the first connection hole is formed.
  • the step of forming the first connection hole includes:
  • the first dielectric substrate is irradiated with laser at a position corresponding to the fully exposed area, and the material of the first dielectric substrate at the position of the fully exposed area is removed to form the first connection hole.
  • the step of forming the first connection hole includes:
  • first dielectric substrate form a first photoresist layer on the first surface of the first dielectric substrate, and form a second photoresist layer on the second surface;
  • the resist layer is exposed, developed, and etched to form a completely first exposed area and a first unexposed area corresponding to the position of the first connection hole;
  • the second photoresist layer is exposed, developed, and etched , forming a completely second exposed area and a second unexposed area corresponding to the position of the first connection hole;
  • the material of a dielectric substrate forms the first connection hole; the first connection hole penetrates the second surface.
  • the preparation method further includes the step of forming a first conductive layer on the first surface; the first conductive layer is connected to the first connection electrode.
  • the preparation method further includes the step of forming a second conductive layer on the second surface; the second conductive layer is connected to the first connection electrode.
  • the preparation method further includes forming an inductor on the first dielectric substrate; the inductor includes a first substructure, a second substructure and a plurality of first connection electrodes; the first substructure is located on the The first surface, the second substructure is located on the second surface, and the first substructure is connected to the second substructure through the first connection electrode to form a coil structure of the inductor.
  • an embodiment of the present disclosure is an electronic device, which includes any of the above functional substrates.
  • FIG. 1 is a schematic diagram of a functional substrate according to a first example of an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a functional substrate according to a second example of an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a functional substrate according to a third example of an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an intermediate product formed in step S11 of the method for preparing a functional substrate according to the first example of the embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of an intermediate product formed in step S12 of the method for preparing a functional substrate according to the first example of the embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of an intermediate product formed in step S13 of the method for preparing a functional substrate according to the first example of the embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of an intermediate product formed in step S14 of the method for preparing a functional substrate according to the first example of the embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of an intermediate product formed in step S15 of the method for preparing a functional substrate according to the first example of the embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of an intermediate product formed in step S16 of the method for preparing a functional substrate according to the first example of the embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of an intermediate product formed in step S17 of the method for preparing a functional substrate according to the first example of the embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of an intermediate product formed in step S18 of the method for preparing a functional substrate according to the first example of the embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of an intermediate product formed in step S21 of the method for preparing a functional substrate according to the second example of the embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of an intermediate product formed in step S22 of the method for preparing a functional substrate according to the second example of the embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of an intermediate product formed in step S23 of the method for preparing a functional substrate according to the second example of the embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of an intermediate product formed in step S24 of the method for preparing a functional substrate according to the second example of the embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of an intermediate product formed in step S25 of the method for preparing a functional substrate according to the second example of the embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of an intermediate product formed in step S26 of the method for preparing a functional substrate according to the second example of the embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of an intermediate product formed in step S27 of the method for preparing a functional substrate according to the second example of the embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of an intermediate product formed in step S28 of the method for preparing a functional substrate according to the second example of the embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of an intermediate product formed in step S31 of the method for preparing a functional substrate according to the third example of the embodiment of the present disclosure.
  • FIG. 21 is a schematic diagram of an intermediate product formed in step S32 of the method for preparing a functional substrate according to the third example of the embodiment of the present disclosure.
  • FIG. 22 is a schematic diagram of an intermediate product formed in step S33 of the method for preparing a functional substrate according to the third example of the embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram of an intermediate product formed in step S34 of the method for preparing a functional substrate according to the third example of the embodiment of the present disclosure.
  • FIG. 24 is a schematic diagram of an intermediate product formed in step S35 of the method for preparing a functional substrate according to the third example of the embodiment of the present disclosure.
  • FIG. 25 is a schematic diagram of an intermediate product formed in step S36 of the method for preparing a functional substrate according to the third example of the embodiment of the present disclosure.
  • FIG. 26 is a schematic diagram of an intermediate product formed in step S37 of the method for preparing a functional substrate according to the third example of the embodiment of the present disclosure.
  • FIG. 27 is a schematic diagram of an intermediate product formed in step S41 of the method for preparing a functional substrate according to the fourth example of the embodiment of the present disclosure.
  • FIG. 28 is a schematic diagram of an intermediate product formed in step S42 of the method for preparing a functional substrate according to the fourth example of the embodiment of the present disclosure.
  • FIG. 29 is a schematic diagram of an intermediate product formed in step S43 of the method for preparing a functional substrate according to the fourth example of the embodiment of the present disclosure.
  • FIG. 30 is a schematic diagram of an intermediate product formed in step S44 of the method for preparing a functional substrate according to the fourth example of the embodiment of the present disclosure.
  • FIG. 31 is a schematic diagram of an intermediate product formed in step S45 of the method for preparing a functional substrate according to the fourth example of the embodiment of the present disclosure.
  • FIG. 32 is a schematic diagram of an intermediate product formed in step S46 of the method for preparing a functional substrate according to the fourth example of the embodiment of the present disclosure.
  • FIG. 33 is a schematic diagram of an intermediate product formed in step S47 of the method for preparing a functional substrate according to the fourth example of the embodiment of the present disclosure.
  • Figure 34 is a schematic structural diagram of a functional substrate according to an embodiment of the present disclosure.
  • Figure 35 is a top view of an inductor according to an embodiment of the present disclosure.
  • Figure 36 is a circuit diagram of a filter circuit according to an embodiment of the present disclosure.
  • FIG. 37 is a schematic diagram of an intermediate product formed in step S51 of the functional substrate preparation method shown in FIG. 34 .
  • FIG. 38 is a schematic diagram of an intermediate product formed in step S52 of the method for preparing a functional substrate shown in FIG. 34 .
  • FIG. 39 is a schematic diagram of an intermediate product formed in step S53 of the method for preparing a functional substrate shown in FIG. 34 .
  • FIG. 40 is a schematic diagram of an intermediate product formed in step S54 of the method for preparing a functional substrate shown in FIG. 34 .
  • FIG. 41 is a schematic diagram of an intermediate product formed in step S55 of the functional substrate preparation method shown in FIG. 34 .
  • FIG. 42 is a schematic diagram of an intermediate product formed in step S56 of the functional substrate preparation method shown in FIG. 34 .
  • FIG. 43 is a schematic diagram of an intermediate product formed in step S57 of the functional substrate preparation method shown in FIG. 34 .
  • FIG. 44 is a schematic diagram of an intermediate product formed in step S58 of the functional substrate preparation method shown in FIG. 34 .
  • FIG. 45 is a schematic diagram of an intermediate product formed in step S59 of the functional substrate preparation method shown in FIG. 34 .
  • FIG. 46 is a schematic diagram of an intermediate product formed in step S510 of the functional substrate preparation method shown in FIG. 34 .
  • FIG. 47 is a schematic diagram of an intermediate product formed in step S511 of the functional substrate preparation method shown in FIG. 34 .
  • an embodiment of the present disclosure provides a functional substrate, which includes a first dielectric substrate that includes a first surface and a second surface that are oppositely arranged along a thickness direction thereof.
  • the first dielectric substrate has a first connection hole.
  • the first connection hole at least penetrates the first surface, that is to say, the first connection hole can be a through hole or a blind hole.
  • the functional substrate also includes a first connection electrode disposed in the first connection hole.
  • the first connection hole includes a first sub-hole and a second sub-hole that are sequentially arranged and connected in a direction away from the second surface; the second sub-hole penetrates the first surface; and the opening of the second sub-hole
  • the width increases monotonically in a direction away from the second surface, and the minimum opening width of the second sub-hole is not less than the maximum opening width of the first sub-hole; the connection position of the first sub-hole and the second sub-hole forms a corner.
  • Figure 1 is a schematic diagram of a functional substrate according to a first example of an embodiment of the present disclosure; as shown in Figure 1, in the functional substrate, the first connection hole 11 penetrates the first dielectric substrate 10, and the third A connecting hole 11 only includes a first sub-hole 111 and a second sub-hole 112 .
  • the second sub-hole 112 penetrates the first surface; the opening width of the second sub-hole 112 increases monotonically in the direction away from the second surface, and the minimum opening width of the second sub-hole 112 is not less than the maximum opening of the first sub-hole 111 width; the connection position of the first sub-hole 111 and the second sub-hole 112 forms a corner.
  • FIG. 4 is a schematic diagram of an intermediate product formed in step S11 of the method for preparing a functional substrate according to the first example of the embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of the intermediate product formed in step S12 of the method of preparing a functional substrate according to the first example of the embodiment of the present disclosure.
  • a schematic diagram of the intermediate product formed
  • FIG. 6 is a schematic diagram of the intermediate product formed in step S13 of the method for preparing a functional substrate according to the first example of the embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of the functional substrate according to the first example of the embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of an intermediate product formed in step S15 of the preparation method of a functional substrate according to the first example of the embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of the intermediate product formed in the first example of the preparation method of the present disclosure.
  • FIG. 1 A schematic diagram of an intermediate product formed in step S16 of the first exemplary functional substrate preparation method
  • Figure 10 is a schematic diagram of an intermediate product formed in step S17 of the first exemplary functional substrate preparation method according to the embodiment of the present disclosure
  • Figure 11 is a schematic diagram of the intermediate product formed in step S16 of the first exemplary functional substrate preparation method
  • the preparation method specifically includes the following steps:
  • S11 Provide a first dielectric substrate 10, and form a photoresist layer on the first surface of the first dielectric substrate 10.
  • the first dielectric substrate 10 may be a glass substrate with a thickness of about 0.25mm-0.3mm.
  • the photosensitive resin material that is, the photoresist layer
  • the material of the photoresist layer includes but is not limited to BL-301, DL-1000C, etc., and the thickness of the photoresist layer is between 2 ⁇ m and 10 ⁇ m.
  • the photoresist layer 100 Expose, develop, and etch the photoresist layer 100 to form a fully exposed area 100a and an unexposed area 100b, and remove the photoresist layer material in the fully exposed area 100a.
  • the fully exposed area 100a corresponds to the area to be formed.
  • step S12 includes pattern exposure of the photoresist layer 100 using an exposure machine and a corresponding mask.
  • the exposure time (8-20 s) is adjusted according to the thickness of the photoresist layer 100. TGV will be required.
  • the resin at the opening position is exposed and developed (3 times of development for 80 to 100 seconds), and the first dielectric substrate 10 at the fully exposed area 100a leaks out.
  • step S13 may specifically use laser-induced etching to form the first connection hole 11 .
  • step S14 may include: etching the first surface and the second surface of the first dielectric substrate 10 using a double-sided etching solution, increasing the etching rate of the laser-modified glass to achieve the first dielectric
  • the substrate 10 is anisotropically etched in the thickness direction. Due to the blocking effect of the unexposed area of the photoresist layer, the etching liquid simultaneously performs isotropic etching near the first surface of the first dielectric substrate 10 . Etching and anisotropic etching are superimposed to form a single nail head through hole structure, that is, the formed first connection via hole includes a first sub-hole 111 and a second sub-hole 112 .
  • the etching rate is controlled by adjusting the concentration and temperature of the etching solution, thereby adjusting the diameter of the nail head. It should be noted that the diameter of the nail head (that is, the opening of the second sub-hole 112 on the first surface) needs to be smaller than the line width of the first layer of metal traces on the first surface and the second surface, and the diameter of the nail head of the adjacent TGV hole The spacing between the headers should be greater than the spacing between the first layer traces.
  • step S15 may include but is not limited to forming an auxiliary film layer by magnetron sputtering, and then continuously sputtering the first conductive film layer, using the first conductive film layer as the first seed layer 200. layer for electroplating.
  • the function of the auxiliary film layer is to increase the adhesion of the first conductive film layer.
  • the material of the auxiliary film layer includes but is not limited to titanium Ti, and the material of the first conductive film layer includes but is not limited to Cu.
  • the thickness of the auxiliary film layer is about 10 nm to 300 nm, and the thickness of the first conductive film layer is about 30 nm to 100 nm.
  • CMP chemical mechanical polishing
  • step S17 may use a strip method to debond, exposing the structure of the first conductive film layer that is higher than the first surface.
  • CMP chemical mechanical polishing
  • the maximum temperature is T1
  • room temperature is T0
  • the temperature change is T1-T0. Therefore, the change in temperature during the process causes the strain amount of the second sub-hole 112 relative to the first dielectric substrate 10 to be:
  • the height L1 of the second sub-hole 112 depends on the etching time. It is generally selected from 5 ⁇ m to 20 ⁇ m. Here, 5 ⁇ m is selected.
  • the strain amount ⁇ 2 of the first dielectric substrate 10 is 14 nm.
  • the expansion amount of the first connection hole 11 with the second sub-hole 112 is only 1/50 of the traditional first connection hole 11, which can greatly reduce the stress of filling the first connection electrode 23 in the first connection hole 11 and reduce breakage. The occurrence of defects such as wires is eliminated and the reliability of the device is improved.
  • Figure 2 is a schematic diagram of a functional substrate according to the second example of the embodiment of the present disclosure; as shown in Figure 2, the structure of the first connection hole 11 in this example is similar to the structure of the first example. The difference is that the first connection hole 11 not only includes a first sub-hole 111 and a second sub-hole 112, but also includes a third sub-hole that penetrates the second surface of the first dielectric substrate 10 and is connected with the first sub-hole 111. 113.
  • the opening width of the third sub-hole 113 decreases monotonically in the direction away from the second surface, and the minimum opening width of the third sub-hole 113 is not less than the maximum opening width of the first sub-hole 111; the first sub-hole 111 and the third sub-hole 111
  • the connection positions of the sub-holes 113 form corners. That is to say, both ends of the formed first connection hole 11 have nail head structures. This structure not only reduces the impact of thermal stress when forming a conductive structure connected to the first connection electrode 23 on the first surface, but also reduces the impact of thermal stress when forming a conductive structure connected to the first connection electrode 23 on the second surface. The influence of stress thereby reduces the occurrence of defects such as disconnection on the first surface and the second surface.
  • FIG. 12 is a schematic diagram of an intermediate product formed in step S21 of the method for preparing a functional substrate according to the second example of the embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of the intermediate product formed in step S22 of the method of preparing a functional substrate according to the second example of the embodiment of the present disclosure.
  • a schematic diagram of the intermediate product formed
  • Figure 14 is a schematic diagram of the intermediate product formed in step S23 of the method for preparing a functional substrate according to the second example of the embodiment of the present disclosure
  • Figure 15 is a schematic diagram of the functional substrate according to the second example of the embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of the intermediate product formed in step S25 of the preparation method of the functional substrate according to the second example of the embodiment of the present disclosure
  • Fig. 17 is a schematic diagram of the intermediate product formed in the second example of the preparation method of the present disclosure.
  • FIG. 12-19 A schematic diagram of an intermediate product formed in step S26 of the method for preparing a functional substrate according to the second example;
  • Figure 18 is a schematic diagram of an intermediate product formed in step S27 of the method for preparing a functional substrate according to the second example of the embodiment of the present disclosure;
  • Figure 19 is a schematic diagram of the intermediate product formed in step S26 of the method for preparing a functional substrate according to the second example of the present disclosure;
  • the method specifically includes the following steps.
  • the first dielectric substrate 10 may be a glass substrate with a thickness of about 0.25mm-0.3mm.
  • the photosensitive resin material on the first surface and the second surface is formed by a method including but not limited to spin coating, that is, the first photoresist layer is coated on the first surface of the first dielectric substrate 10, and the second photoresist layer is coated on the first surface of the first dielectric substrate 10.
  • the first layer is coated on the second surface of the first dielectric substrate 10, and then pre-baked and set at 110°C/150s.
  • the materials of the first photoresist layer and the second photoresist layer include but are not limited to BL-301, DL-1000C, etc., and the thickness of the first photoresist layer and the second photoresist layer is between 2 ⁇ m and 10 ⁇ m.
  • step S22 includes using an exposure machine and a corresponding mask to perform pattern exposure on the first photoresist layer and the second photoresist layer, respectively.
  • the thickness of the resist layer 120 is adjusted to the exposure time (8 to 20 s), and the resin at the position where the TGV opening is required is exposed and developed (3 times of development in 80 to 100 s) to leak out the first fully exposed area 110a and the second fully exposed area.
  • step S23 may specifically use laser-induced etching to form the first connection hole 11.
  • step S14 may include: etching the first surface and the second surface of the first dielectric substrate 10 using a double-sided etching solution, increasing the etching rate of the laser-modified glass to achieve the first dielectric
  • the substrate 10 is anisotropically etched in the thickness direction. Due to the blocking effect of the first unexposed area 110b of the first photoresist layer 110 and the second unexposed area 120b of the second photoresist layer 120, the etching liquid simultaneously Isotropic etching is performed near the first surface of the first dielectric substrate 10. The isotropic etching and the anisotropic etching are superimposed to form a double nail head through hole structure.
  • the formed first connection via hole includes a third A sub-hole 111, a second sub-hole 112 and a third sub-hole 113.
  • the etching rate is controlled by adjusting the concentration and temperature of the etching solution, thereby adjusting the diameter of the nail head.
  • the diameter of the nail head (that is, the opening of the second sub-hole 112 on the first surface) needs to be smaller than the line width of the first layer of metal traces on the first surface and the second surface, and the diameter of the nail head of the adjacent TGV hole
  • the spacing between the headers should be greater than the spacing between the first layer traces.
  • step S15 may include but is not limited to forming an auxiliary film layer by magnetron sputtering, and then continuously sputtering the first conductive film layer, using the first conductive film layer as the first seed layer 200.
  • Layer 200 is electroplated.
  • the function of the auxiliary film layer is to increase the adhesion of the first conductive film layer.
  • the material of the auxiliary film layer includes but is not limited to titanium Ti, and the material of the first conductive film layer includes but is not limited to Cu.
  • the thickness of the auxiliary film layer is about 10 nm to 300 nm, and the thickness of the first conductive film layer is about 30 nm to 100 nm.
  • CMP chemical mechanical polishing
  • step S27 may be debonding using a strip method to expose the structure 201 of the first conductive film layer that is higher than the first surface and the second surface.
  • CMP chemical mechanical polishing
  • the first connection hole 11 solution of the double nail head has the characteristics of relieving the stress of double-sided RDL, and is mainly used in the production of three-dimensional glass-based devices with double-sided RDL metal traces and thicker (>250 ⁇ m) glass-based carrier boards.
  • Figure 3 is a schematic diagram of a functional substrate according to a third example of the embodiment of the present disclosure; as shown in Figure 3, the first connection hole 11 in the functional substrate of this example may be a blind hole, and the first connection hole 11 in the functional substrate may be a blind hole.
  • the connection hole 11 includes a first sub-hole 111 and a second sub-hole 112.
  • the first sub-hole 111 is different from the first example.
  • the first sub-hole 111 in the first example is formed by double-sided etching. Hourglass shape, and in this example, the second sub-hole 112 has an inverted trapezoid shape.
  • FIG. 20 is a schematic diagram of an intermediate product formed in step S31 of the method for preparing a functional substrate according to the third example of the embodiment of the present disclosure
  • FIG. 21 is a schematic diagram of the intermediate product formed in step S32 of the method of preparing a functional substrate according to the third example of the embodiment of the disclosure.
  • a schematic diagram of the intermediate product formed
  • Figure 22 is a schematic diagram of the intermediate product formed in step S33 of the method for preparing a functional substrate according to the third example of the embodiment of the present disclosure
  • Figure 23 is a schematic diagram of the functional substrate according to the third example of the embodiment of the present disclosure.
  • FIG. 20-26 A schematic diagram of an intermediate product formed in step S34 of the preparation method;
  • Figure 24 is a schematic diagram of an intermediate product formed in step S35 of the preparation method of a functional substrate according to the third example of the embodiment of the present disclosure;
  • Figure 25 is a schematic diagram of the intermediate product formed in the third example of the preparation method of the present disclosure.
  • FIG. 26 is a schematic diagram of an intermediate product formed in step S37 of the third exemplary functional substrate preparation method according to the embodiment of the present disclosure.
  • the method specifically includes the following steps.
  • S31 Provide a first dielectric substrate 10, and form a photoresist layer on the first surface of the first dielectric substrate 10; expose, develop, and etch the photoresist layer to form the third fully exposed area 100c and the third fully exposed area 100c.
  • the first dielectric substrate 10 may be a glass substrate with a thickness of about 0.25mm-0.3mm.
  • the photosensitive resin material that is, the photoresist layer
  • the material of the photoresist layer includes but is not limited to BL-301, DL-1000C, etc., and the thickness of the photoresist layer is between 2 ⁇ m and 10 ⁇ m.
  • step S32 may specifically use laser-induced etching to form the first connection hole 11 .
  • step S33 may include: etching the first surface of the first dielectric substrate 10 using an etching solution.
  • the etching rate of the laser-modified glass is increased to achieve a thickness direction of the first dielectric substrate 10 .
  • Anisotropic etching due to the blocking effect of the unexposed area 100d of the photoresist layer, the etching liquid simultaneously performs isotropic etching near the first surface of the first dielectric substrate 10. Isotropic etching and isotropic etching The anisotropic etching is superimposed to form a single nail head through hole structure, that is, the formed first connection via hole includes a first sub-hole 111 and a second sub-hole 112 .
  • the etching rate is controlled by adjusting the concentration and temperature of the etching solution, thereby adjusting the diameter of the nail head. It should be noted that the diameter of the nail head (that is, the opening of the second sub-hole 112 on the first surface) needs to be smaller than the line width of the first layer of metal traces on the first surface, and the spacing between the nail heads of adjacent TGV holes must be Larger than the line spacing of the first layer of traces.
  • step S34 may include but is not limited to forming an auxiliary film layer by magnetron sputtering, and then continuously sputtering the first conductive film layer, using the first conductive film layer as the first seed layer 200.
  • Layer 200 is electroplated.
  • the function of the auxiliary film layer is to increase the adhesion of the first conductive film layer.
  • the material of the auxiliary film layer includes but is not limited to titanium Ti, and the material of the first conductive film layer includes but is not limited to Cu.
  • the thickness of the auxiliary film layer is about 10 nm to 300 nm, and the thickness of the first conductive film layer is about 30 nm to 100 nm.
  • CMP chemical mechanical polishing
  • step S36 may be debonding using a strip method to expose the structure 201 of the first conductive film layer that is higher than the first surface.
  • CMP chemical mechanical polishing
  • the second surface of the first dielectric substrate 10 can also be thinned to expose the first connection electrode 23, so as to form a metal wire structure on the subsequent second surface.
  • both the first buffer layer and the second buffer layer can be made of resin material, such as photoresist.
  • both the first buffer layer and the second buffer layer may adopt the photoresist layer used in modifying the first dielectric substrate 10 .
  • FIG. 27 is a schematic diagram of an intermediate product formed in step S41 of the fourth example of the method for preparing a functional substrate according to the embodiment of the present disclosure
  • FIG. 28 is a diagram of the intermediate product formed in step S42 of the method of preparing a functional substrate according to the fourth example of the embodiment of the present disclosure.
  • a schematic diagram of the intermediate product formed is a schematic diagram of the intermediate product formed in step S43 of the preparation method of the functional substrate according to the fourth example of the embodiment of the present disclosure
  • Figure 30 is the functional substrate of the fourth example of the embodiment of the present disclosure.
  • FIG. 33 is a schematic diagram of an intermediate product formed in step S47 of a fourth exemplary functional substrate preparation method according to the embodiment of the present disclosure. As shown in Figures 27-33, the method specifically includes the following steps.
  • the first dielectric substrate 10 may be a glass substrate with a thickness of about 0.25mm-0.3mm.
  • the photosensitive resin material on the first surface and the second surface is formed by a method including but not limited to spin coating, that is, the third photoresist layer 130 is coated on the first surface of the first dielectric substrate 10, and the fourth photolithography
  • the glue layer 140 is coated on the second surface of the first dielectric substrate 10, and then pre-baked and set at 110°C/150s.
  • the materials of the third photoresist layer 130 and the fourth photoresist layer 140 include but are not limited to BL-301, DL-1000C, etc.
  • the thickness of the third photoresist layer 130 and the fourth photoresist layer 140 is between 2 ⁇ m and 10 ⁇ m.
  • step S42 includes using an exposure machine and a corresponding mask to perform pattern exposure on the third photoresist layer 130 and the fourth photoresist layer 140, respectively.
  • the thickness of the four photoresist layers 140 is adjusted by the exposure time (8 to 20 s), and the resin at the location where the TGV opening is required is exposed and developed (developed once in 80 to 100 s).
  • step S43 includes using an exposure machine and a corresponding mask to perform pattern exposure on the third photoresist layer 130 and the fourth photoresist layer 140, respectively.
  • the thickness of the four photoresist layers 140 is adjusted to the exposure time (8 to 20 s), and the resin at the position where the TGV opening is required is exposed and developed (2 times of development in 80 to 100 s) to leak out the fourth fully exposed area 130c and the fifth fully exposed area 130c.
  • step S44 may use laser-induced etching to form the first connection hole 11 .
  • step S45 may include: etching the first surface and the second surface of the first dielectric substrate 10 using a double-sided etching solution, increasing the etching rate of the laser-modified glass to achieve the first dielectric
  • the substrate 10 is anisotropically etched in the thickness direction. Due to the blocking effect of the third photoresist layer 130 and the fourth photoresist layer 140 , the etching liquid simultaneously conducts anisotropic etching near the first surface of the first dielectric substrate 10 .
  • Isotropic etching, isotropic etching and anisotropic etching are superimposed to form a double nail head through hole structure, that is, the formed first connection via includes a first sub-hole 111, a second sub-hole 112 and a third sub-hole. Hole 113.
  • the etching rate is controlled by adjusting the concentration and temperature of the etching solution, thereby adjusting the diameter of the nail head.
  • the diameter of the nail head (that is, the opening of the second sub-hole 112 on the first surface) needs to be smaller than the line width of the first layer of metal traces on the first surface and the second surface, and the diameter of the nail head of the adjacent TGV hole
  • the spacing between the headers should be greater than the spacing between the first layer traces.
  • step S46 may include but is not limited to forming an auxiliary film layer by magnetron sputtering, and then continuously sputtering the first conductive film layer, using the first conductive film layer as the first seed layer 200. Layer 200 is electroplated.
  • the function of the auxiliary film layer is to increase the adhesion of the first conductive film layer.
  • the material of the auxiliary film layer includes but is not limited to titanium Ti, and the material of the first conductive film layer includes but is not limited to Cu.
  • the thickness of the auxiliary film layer is about 10 nm to 300 nm, and the thickness of the first conductive film layer is about 30 nm to 100 nm.
  • CMP chemical mechanical polishing
  • the above provides four examples of preparation methods of the first connection holes 11 and the first connection electrodes 23 on the functional substrate.
  • the functional substrate of the embodiment of the present disclosure not only includes the above structure, but also includes a first conductive layer located on the first surface.
  • the first connection hole 11 is a through hole, it may also include a second conductive layer located on the second surface. conductive layer.
  • FIG. 35 is a schematic diagram of a functional substrate according to an embodiment of the present disclosure; as shown in FIG. 35 , the functional substrate is integrated with structures such as capacitors and inductors, that is, the functional substrate is a substrate with a filtering function.
  • FIG. 36 is a top view of an inductor according to an embodiment of the present disclosure. Referring to FIGS. 35 and 36 , each first substructure 21 of the inductor extends along the first direction and is arranged side by side along the second direction; each second substructure 22 of the inductor extends along the first direction. Extend along the third direction and be arranged side by side along the second direction. Wherein, the first direction, the second direction, and the third direction are all different directions.
  • the first direction and the second direction are perpendicular to each other, and the first direction and the third direction intersect and are not vertically arranged as example.
  • the extending directions of the first substructure 21 and the second substructure 22 can also be interchanged, and both are within the protection scope of the embodiments of the present disclosure.
  • the inductor includes N first substructures 21 and N-1 second substructures 22 as an example for description, where N ⁇ 2, and N is an integer.
  • the first end and the second end of the first substructure 21 respectively overlap at least partially with a first connection via hole 11 in orthographic projection on the first dielectric substrate.
  • first end and the second end of a first substructure 21 correspond to different first connection vias 11, that is, a first substructure 21 and two first connection vias 11 are orthogonally projected on the first dielectric substrate. At least partially overlap.
  • first end of the ith second substructure 22 of the inductor is connected to the first end of the ith first substructure 21 and the second end of the i+1th first substructure 21 to form an inductor coil, where , 1 ⁇ i ⁇ N-1, and i is an integer.
  • first lead terminal 24 is connected to the second end of the first first substructure 21 of the inductor coil
  • second lead terminal 25 is connected to the first end of the Nth first substructure 21. connect.
  • first lead terminal 24 and the second lead terminal 25 can be arranged on the same layer as the second substructure 22 and use the same material.
  • the first lead terminal 24 can be connected to the first lead terminal 24 through the first connection via 11
  • the second end of the first substructure 21 is connected.
  • the second lead end 25 can be connected to the first end of the Nth first substructure 21 through the first connection via 11 .
  • Figure 37 is a diagram of a filter circuit; as shown in Figure 37, the filter circuit includes two inductors, a capacitor and a resistor. Among them, for ease of understanding, the two inductors are respectively called the first inductor L1 and the second inductor L2. Continuing to refer to Figure 2, the first lead end of the first inductor L1 is connected to the first end of the resistor R, the second lead end of the first inductor is connected to the second plate of the capacitor C, and the first lead end of the second inductor L2 is connected to the resistor R. The first end of the second inductor L2 is connected to the first plate of the capacitor C.
  • the resistor R can be implemented by a wire, or a high-resistance material, such as tin oxide (ITO) or nickel-chromium (NiCr) alloy, can be used for the resistor R.
  • ITO tin oxide
  • NiCr nickel-chromium
  • the formation of the resistor R is not limited, and the following mainly introduces the capacitor and the inductor.
  • the first plate of the capacitor can be arranged on the same layer as the first substructure of the inductor.
  • the first interlayer dielectric layer 4 is arranged on the side facing away from the first plate 31 of the capacitor, and the second plate 32 of the capacitor is arranged on the side of the first interlayer dielectric layer 4 facing away from the first plate 31 of the capacitor;
  • a second interlayer dielectric layer 5 is provided on a layer facing away from the second plate 32 of the capacitor.
  • a second connection electrode 61 and a third connection electrode 62 are provided on a side facing away from the second interlayer dielectric layer 5 .
  • the electrode 61 is connected to the first substructure 21 of the inductor through a second connection via that penetrates the first interlayer dielectric layer 4 and the second interlayer dielectric layer 5 ; the third connection electrode 62 passes through the second interlayer dielectric layer 5
  • the third connection via is connected to the second plate 32 of the capacitor.
  • a first protective layer 78 and a first planarization layer 101 are sequentially provided on the side of the second connection electrode 61 and the third connection electrode 62 away from the first dielectric substrate 10; and a first protective layer 78 and a first planarization layer are formed through the first protective layer 7 and the first planarization layer.
  • the first connection pad 102 and the second connection pad 103 are formed in the fourth connection via hole and the fifth connection via hole, respectively. Wherein, the first connection pad 102 and the second connection pad 103 may be solder.
  • a third protective layer and a third planarization layer may be formed on the side of the second substructure 22 away from the first dielectric substrate 10 to protect the second substructure 22 from water and oxygen erosion.
  • the first connection electrode 25 in the first connection via hole 11 only covers the inner wall of the first connection via hole 11 instead of filling the first connection via hole 11 completely.
  • first connection electrode 25 only covers the inner wall of the first connection via hole 11
  • first accommodation space located in the first connection via hole 11 is defined.
  • the first accommodation space can be filled with resin material as a filling. The structure prevents the first connection electrode 25 from being oxidized and plays a certain supporting role.
  • FIG. 37 is a schematic diagram of an intermediate product formed in step S51 of the functional substrate preparation method shown in FIG. 34 .
  • Figure 38 is a schematic diagram of an intermediate product formed in step S52 of the method of preparing a functional substrate shown in Figure 34;
  • Figure 39 is a schematic diagram of an intermediate product formed in step S53 of the method of preparing a functional substrate shown in Figure 34;
  • Figure 40 is a diagram 34 is a schematic diagram of the intermediate product formed in step S54 of the functional substrate preparation method;
  • Figure 41 is a schematic diagram of the intermediate product formed in step S55 of the functional substrate preparation method shown in Figure 34;
  • Figure 42 is a schematic diagram of the intermediate product shown in Figure 34 A schematic diagram of the intermediate product formed in step S56 of the functional substrate preparation method;
  • Figure 43 is a schematic diagram of the intermediate product formed in step S57 of the functional substrate preparation method shown in Figure 34;
  • Figure 44 is a preparation of the functional substrate shown in Figure 34 A schematic diagram of the intermediate product formed in step S58 of the method;
  • Figure 45 is a schematic diagram of the intermediate product formed in step S59 of the functional substrate preparation method shown in Figure 34;
  • Figure 46 is
  • the first substructure 21 includes a first part 211 , a second part 212 and a third part 213 that are sequentially stacked on the first surface of the first dielectric substrate 10
  • the first plate 31 of the capacitor includes sequentially
  • the fourth part 311, the fifth part 312 and the sixth part 313 are stacked on the first surface of the first dielectric substrate 10, wherein the first part 211 and the fourth part 311 are arranged on the same layer and are made of the same material;
  • the second part 212 and the fifth part 312 are arranged on the same layer and their materials are the same;
  • the third part 213 and the sixth part 313 are arranged on the same layer and their materials are the same.
  • Step S51 may specifically include the following steps.
  • the first film layer may be molybdenum.
  • Mo nickel
  • Ni nickel
  • the second film layer can be a copper (Cu) layer, with a thickness of about 0.3 ⁇ m ⁇ 0.5 ⁇ m
  • the third film layer can be Mo, Ni
  • the thickness of the alloy layer is about 0.02 ⁇ m ⁇ 0.05 ⁇ m.
  • the photoresist is removed by development, and then the copper in the area not protected by the photoresist is etched away with a copper etching solution to form a third inductor including the first part 211, the second part 212 and the third part 213 of the stacked arrangement.
  • a substructure 21 and a first plate 31 of a capacitor including a fourth part 311 , a fifth part 312 and a sixth part 313 arranged in a stack.
  • the layer where the first sub-section of the inductor and the first plate 31 of the capacitor are located is very critical in the entire device.
  • the functions they realize are the plates of the capacitor, so the flatness requirements are relatively high. If it is electroplating Thick copper requires chemical mechanical planarization.
  • the first substructure 21 serves as a connection structure between TGV holes (first connection vias 11 ) and a connection between inductors and capacitors. In order to ensure the reliability of the connection with the first connection electrode 25 in the first connection hole formed subsequently, the edge of the first substructure 21 exceeds the edge of the first connection electrode 25 in the first connection via hole 11 by 5um ⁇ 10 ⁇ m.
  • step S52 may include using standard processes such as ion-enhanced chemical vapor deposition (PECVD) to deposit The first interlayer dielectric layer 4 is formed.
  • PECVD ion-enhanced chemical vapor deposition
  • the material of the first interlayer dielectric layer 4 is an inorganic insulating material.
  • the first interlayer dielectric layer 4 is an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO 2 ), or an inorganic insulating layer of SiNx and SiO 2 Several laminated combination membrane layers.
  • the first interlayer dielectric layer 4 also serves as an intermediate dielectric layer of the capacitor.
  • the thickness of the first interlayer medium is about 120nm.
  • step S53 may adopt a method including but not limited to magnetron sputtering to sequentially deposit a fourth film layer, a fifth film layer and a sixth film layer, on the surface of the sixth film layer facing away from the first dielectric substrate 10
  • the photoresist irradiated by ultraviolet light is denatured, and then developed to remove the denatured photoresist.
  • use copper etching solution to remove the denatured photoresist.
  • the copper in the area protected by the photoresist is etched away to form the second plate 32 of the capacitor including the seventh part 321 , the eighth part 322 and the ninth part 323 arranged in a stack.
  • the fourth film layer can be a molybdenum (Mo) or nickel (Ni) alloy layer, with a thickness of about 0.03 ⁇ m to 0.05 ⁇ m;
  • the fifth film layer can be a copper (Cu) layer, with a thickness of about 0.3 ⁇ m to 0.5 ⁇ m;
  • the sixth film layer may be a Mo or Ni alloy layer with a thickness of about 0.02 ⁇ m to 0.05 ⁇ m.
  • step S54 includes depositing and forming the second interlayer dielectric layer 5 on the side of the second plate 32 of the capacitor away from the first dielectric substrate 10 using a standard process such as PECVD.
  • the second interlayer dielectric layer 5 can be made of the same material as the first interlayer dielectric layer 4 , and its thickness ranges from 0.2 ⁇ m to 0.5 ⁇ m.
  • step S55 includes forming a second connection via hole penetrating the first interlayer dielectric layer 4 and the second interlayer dielectric layer 5 through dry etching, and a third connection via hole penetrating the second interlayer dielectric layer 5 . Connect vias.
  • step S56 may include sequentially forming the seventh film layer 60 and the eighth film on the side of the second interlayer dielectric layer 5 away from the first dielectric substrate 10 by a method including but not limited to magnetron sputtering.
  • layer, the eighth film layer is used as the third seed layer, the third seed layer is electroplated, and then the electroplated long and thick eighth film layer and seventh film layer 60 are patterned to form the second connection electrode 61 and the third Connect electrode 62.
  • the seventh film layer may be a molybdenum (Mo) or nickel (Ni) alloy layer with a thickness of about 0.03 ⁇ m to 0.05 ⁇ m; the eighth film layer may be a copper (Cu) layer with a thickness of about 0.3 ⁇ m to 0.5 ⁇ m.
  • Mo molybdenum
  • Ni nickel
  • Cu copper
  • step S57 includes sequentially depositing and forming the first protective layer 7 using a standard process such as PECVD.
  • the first protective layer 7 is used to prevent water and oxygen from eroding devices formed on the first surface of the first dielectric substrate 10 .
  • the thickness of the first protective layer 7 is between 0.4 ⁇ m and 0.6 ⁇ m; the material of the first protective layer 7 may be an inorganic insulating material.
  • the first protective layer 7 may be an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO 2 ), or a combination of a SiNx inorganic insulating layer and an SiO 2 inorganic insulating layer.
  • the second substructure 22 of the inductor is sequentially formed on the second surface of the first dielectric substrate 10, and a second protection is formed on the side of the second substructure 22 away from the first dielectric substrate 10.
  • step S58 includes forming a second conductive film layer as a second seed layer on the second surface of the first dielectric substrate 10 on which the first connection electrode 25 is formed, using a method including but not limited to magnetron sputtering. , and then electroplating the second seed layer.
  • the thickness of the electroplated second seed layer is usually greater than 5 ⁇ m, and then patterning is performed to form the second substructure 22 of the inductor. Using standard processes such as PECVD, the second protective layer 8 is sequentially deposited.
  • the second protective layer 8 is used to prevent water and oxygen from eroding devices formed on the first surface of the first dielectric substrate 10 .
  • the thickness of the second protective layer 8 is between 0.4 ⁇ m and 0.6 ⁇ m; the material of the first protective layer 7 can be an inorganic insulating material.
  • the second protective layer 8 may be an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO 2 ), or a combination of a SiNx inorganic insulating layer and an SiO 2 inorganic insulating layer.
  • standard processes such as PECVD may be used to form the second protective layer 9 .
  • the thickness of the second planarization layer 9 is more than 2 ⁇ m; the material of the second planarization layer 9 may include organic insulating materials, such as polyimide, epoxy resin, acrylic, polyester, optical fiber, etc. Resist, polyacrylate, polyamide, silicone and other resin materials.
  • the organic insulating material includes elastic materials, such as urethane, thermoplastic polyurethane (TPU), and the like.
  • the thickness of the first planarization layer 101 is more than 2 ⁇ m; the material of the first planarization layer 101 may include organic insulating materials, such as polyimide, epoxy resin, acrylic, and polyester. , photoresist, polyacrylate, polyamide, silicone and other resin materials, etc.
  • the organic insulating material includes elastic materials, such as urethane, thermoplastic polyurethane (TPU), and the like.
  • connection pad 102 and the second connection pad 103 form the first connection pad 102 and the second connection pad 103.
  • the first connection pad 102 and the second connection pad 103 are respectively formed at positions corresponding to the fourth connection via hole and the fifth connection via hole, as shown in Figure 34 shown.
  • first connection pad 102 and the second connection pad 103 may be solder.
  • the capacitance value is determined by the thickness of the first interlayer dielectric layer 4 , the dielectric constant of the material of the first interlayer dielectric layer 4 , and the positive values of the first electrode plate 31 and the second electrode plate 32 . Determine the area.
  • the inductance value is determined by the number of turns of the spiral, the pitch of the spiral, and the diameter of the spiral. Therefore, the dielectric constant of the material of the first interlayer dielectric layer 4 of the capacitor, the parameters of the first plate 31 and the second plate 32 can be reasonably designed, as well as the first substructure 21 and the second substructure of the inductor coil. 22 size, spacing and other parameters to achieve the effect of optimizing the filter circuit.
  • embodiments of the present disclosure provide an electronic device, which includes any of the above functional substrates.

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Abstract

本公开提供一种功能基板及其制备方法、电子设备，属于电子元件技术领域。本公开的功能基板，其包括第一介质基板；其中，所述第一介质基板包括沿其厚度方向相对设置的第一表面和第二表面；所述第一介质基板具有第一连接孔；所述第一连接孔至少贯穿所述第一表面；所述第一连接孔内设置第一连接电极；所述第一连接孔包括沿背离所述第二表面的方向依次设置、且连通的第一子孔和第二子孔；所述第二子孔贯穿所述第一表面；所述第二子孔的开口宽度在沿背离所述第二表面的方向上单调增，且所述第二子孔的最小开口宽度不小于所述第一子孔的最大开口宽度；所述第一子孔和所述第二子孔的连接位置形成拐角。

Description

功能基板及其制备方法、电子设备 技术领域
本公开属于电子元件技术领域，具体涉及一种功能基板及其制备方法、电子设备。
背景技术
在当代，消费电子产业发展日新月异，以手机特别是5G手机为代表的移动通信终端发展迅速，手机需要处理的信号频段越来越多，需要的射频芯片数量也水涨船高，而获得消费者喜爱的手机形式向小型化、轻薄化、长续航不断发展。在传统手机中，射频PCB板上存在大量的分立器件如电阻、电容、电感、滤波器等，它们具有体积大、功耗高、焊点多、寄生参数变化大的缺点，难以应对未来的需求。射频芯片相互间的互联、匹配等需要面积小、高性能、一致性好的集成无源器件。目前市场上的集成无源器件主要是基于Si(硅)衬底和GaAs(砷化镓)衬底。Si基集成无源器件具有价格便宜的优点，但Si本身有微量杂质(绝缘性差)导致器件微波损耗较高，性能一般；GaAs基集成无源器件具有性能优良的优点，但价格昂贵。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种功能基板及其制备方法、电子设备。
第一方面，本公开实施例提供一种功能基板，其包括第一介质基板；其中，所述第一介质基板包括沿其厚度方向相对设置的第一表面和第二表面；所述第一介质基板具有第一连接孔；所述第一连接孔至少贯穿所述第一表面；所述第一连接孔内设置第一连接电极；
所述第一连接孔包括沿背离所述第二表面的方向依次设置、且连通的第一子孔和第二子孔；所述第二子孔贯穿所述第一表面；
所述第二子孔的开口宽度在沿背离所述第二表面的方向上单调增，且所述第二子孔的最小开口宽度不小于所述第一子孔的最大开口宽度；所述第一子孔和所述第二子孔的连接位置形成拐角。
其中，所述第一连接孔贯穿所述第一表面和第二表面，所述第一连接过孔还包括与所述第一子孔连通，且贯穿所述第二表面的第三子孔；所述第三子孔的开口宽度在沿背离所述第二表面的方向上单调减，且所述第三子孔的最小开口宽度不小于所述第一子孔的最大开口宽度；所述第一子孔和所述第三子孔的连接位置形成拐角。
其中，所述第一子孔贯穿所述所述第二表面。
其中，所述第一子孔呈沙漏状。
其中，所述第一子孔的开口宽度沿背离所述第二表面的方向单调增。
其中，所述第一连接电极填充所述第一连接孔或者仅覆盖所述第一连接孔的内壁。
其中，所述功能基板还包括位于所述第一表面上，且与所述第一连接电极连接的第一导电层。
其中，所述第一连接孔贯穿所述第二表面，所述功能基板还包括位于所述第二表面的第二导电层，且所述第二导电层与所述第一连接电极连接。
其中，所述功能基板还包括集成在所述第一介质基板上的电感，所述电感包括第一子结构、第二子结构和多个所述第一连接电极；所述第一子结构位于所述第一表面，所述第二子结构位于所述第二表面，且所述第一子结构通过所述第一连接电极与所述第二子结构连接形成所述电感的线圈结构。
其中，所述功能基板还包括位于所述第一导电层的电容的第一极板；在所述第一导电层背离所述第一介质基板的一侧形成第一层间介质层；在所述第一层间介质层背离所述第一导电层的一侧设置有电容的第二极板。
其中，所述功能基板还包括设置在所述电容的第二极板背离所述第一介质基板的一侧的第二层间介质层、第二连接电极和第三连接电极；
所述第二连接电极通过贯穿所述第一层间介质层和第二层间介质层的第二连接孔与所述电感的引线端连接；所述第三连接电极通过贯穿所述第二层间层的第三连接孔与所述电容的第二极板电连接。
其中，所述功能基板还包括在所述第二连接电极和所述第三连接电极所在层背离所述第一介质基板的一侧，依次设置的第一保护层和第一平坦化层，以及第一连接焊盘和第二连接焊盘；
所述第一连接焊盘通过第四连接孔连接所述第二连接电极，所述第二连接焊盘通过第五连接孔连接所述第三连接电极；所述第四连接孔和所述第五连接孔均贯穿贯穿所述第一保护层和所述第一平坦化层。
其中，所述功能基板还包括在所述第二导电层背离所述第一介质基板一侧依次设置的第二保护层和第二平坦化层。
其中，所述第一连接孔贯穿所述第二表面；所述功能基板还包括设置在所述第一表面上的第一导电层和设置在所述第二表面上的第二导电层，所述第一导电层和所述第二导电层通过所述第一连接孔连接；在所述第一导电层和所述第一表面之间设置有第一缓冲层；在所述第二导电层和所述第二表面之间设置有第二缓冲层。
本公开实施例还提供一种功能基板的制备方法，其包括：
提供一第一介质基板；所述第一介质基板包括沿其厚度方向相对设置的第一表面和第二表面；
在所述第一介质基板上形成第一连接孔；所述第一连接孔至少贯穿所述第一表面；所述第一连接孔包括沿背离所述第二表面的方向依次设置、且连通的第一子孔和第二子孔；所述第二子孔贯穿所述第一表面；所述第二子孔的开口宽度在沿背离所述第二表面的方向上单调增，且所述第二子孔的最小开口宽度不小于所述第一子孔的最大开口宽度；所述第一子孔和所述第二子孔的连接位置形成拐角；
形成位于所述第一连接孔内的第一连接电极。
其中，形成所述第一连接孔的步骤包括：
提供一所述第一介质基板，在所述第一介质基板的所述第一表面形成光刻胶层；
对光刻胶层进行曝光、显影、刻蚀，形成与所述第一连接孔位置对应的 完全曝光区和未曝光区；
对第一介质基板对应所述完全曝光区的位置进行激光辐照，并去除所述完全曝光区的位置的第一介质基板的材料，形成所述第一连接孔。
其中，所述第一连接孔贯穿所述第二表面
其中，形成所述第一连接孔的步骤包括：
提供一所述第一介质基板，在所述第一介质基板的所述第一表面形成第一光刻胶层，在所述第二表面形成第二光刻胶层；对所述第一光刻胶层进行曝光、显影、刻蚀，形成与所述第一连接孔位置对应的完全第一曝光区和第一未曝光区；对所述第二光刻胶层进行曝光、显影、刻蚀，形成与所述第一连接孔位置对应的完全第二曝光区和第二未曝光区；
分别对第一介质基板对应所述第一完全曝光区和所述第二完全曝光区的位置进行激光辐照，并去除所述第一完全曝光区和所述第二完全曝光区的位置的第一介质基板的材料，形成所述第一连接孔；所述第一连接孔贯穿所述第二表面。
其中，所述制备方法还包括在所述第一表面上形成第一导电层的步骤；所述第一导电层与所述第一连接电极连接。
其中，所述制备方法还包括在所述第二表面上形成第二导电层的步骤；所述第二导电层与所述第一连接电极连接。
其中，所述制备方法还包括在所述第一介质基板上形成电感；所述电感包括第一子结构、第二子结构和多个所述第一连接电极；所述第一子结构位于所述第一表面，所述第二子结构位于所述第二表面，且所述第一子结构通过所述第一连接电极与所述第二子结构连接形成所述电感的线圈结构。
第二方面，本公开实施例一种电子设备，其包括上述任一所述的功能基板。
附图说明
图1为本公开实施例的第一种示例的功能基板的示意图。
图2为本公开实施例的第二种示例的功能基板的示意图。
图3为本公开实施例的第三种示例的功能基板的示意图。
图4为本公开实施例的第一种示例的功能基板的制备方法的步骤S11所形成的中间产品示意图。
图5为本公开实施例的第一种示例的功能基板的制备方法的步骤S12所形成的中间产品示意图。
图6为本公开实施例的第一种示例的功能基板的制备方法的步骤S13所形成的中间产品示意图。
图7为本公开实施例的第一种示例的功能基板的制备方法的步骤S14所形成的中间产品示意图。
图8为本公开实施例的第一种示例的功能基板的制备方法的步骤S15所形成的中间产品示意图。
图9为本公开实施例的第一种示例的功能基板的制备方法的步骤S16所形成的中间产品示意图。
图10为本公开实施例的第一种示例的功能基板的制备方法的步骤S17所形成的中间产品示意图。
图11为本公开实施例的第一种示例的功能基板的制备方法的步骤S18所形成的中间产品示意图。
图12为本公开实施例的第二种示例的功能基板的制备方法的步骤S21所形成的中间产品示意图。
图13为本公开实施例的第二种示例的功能基板的制备方法的步骤S22所形成的中间产品示意图。
图14为本公开实施例的第二种示例的功能基板的制备方法的步骤S23所形成的中间产品示意图。
图15为本公开实施例的第二种示例的功能基板的制备方法的步骤S24 所形成的中间产品示意图。
图16为本公开实施例的第二种示例的功能基板的制备方法的步骤S25所形成的中间产品示意图。
图17为本公开实施例的第二种示例的功能基板的制备方法的步骤S26所形成的中间产品示意图。
图18为本公开实施例的第二种示例的功能基板的制备方法的步骤S27所形成的中间产品示意图。
图19为本公开实施例的第二种示例的功能基板的制备方法的步骤S28所形成的中间产品示意图。
图20为本公开实施例的第三种示例的功能基板的制备方法的步骤S31所形成的中间产品示意图。
图21为本公开实施例的第三种示例的功能基板的制备方法的步骤S32所形成的中间产品示意图。
图22为本公开实施例的第三种示例的功能基板的制备方法的步骤S33所形成的中间产品示意图。
图23为本公开实施例的第三种示例的功能基板的制备方法的步骤S34所形成的中间产品示意图。
图24为本公开实施例的第三种示例的功能基板的制备方法的步骤S35所形成的中间产品示意图。
图25为本公开实施例的第三种示例的功能基板的制备方法的步骤S36所形成的中间产品示意图。
图26为本公开实施例的第三种示例的功能基板的制备方法的步骤S37所形成的中间产品示意图。
图27为本公开实施例的第四种示例的功能基板的制备方法的步骤S41所形成的中间产品示意图。
图28为本公开实施例的第四种示例的功能基板的制备方法的步骤S42 所形成的中间产品示意图。
图29为本公开实施例的第四种示例的功能基板的制备方法的步骤S43所形成的中间产品示意图。
图30为本公开实施例的第四种示例的功能基板的制备方法的步骤S44所形成的中间产品示意图。
图31为本公开实施例的第四种示例的功能基板的制备方法的步骤S45所形成的中间产品示意图。
图32为本公开实施例的第四种示例的功能基板的制备方法的步骤S46所形成的中间产品示意图。
图33为本公开实施例的第四种示例的功能基板的制备方法的步骤S47所形成的中间产品示意图。
图34为本公开实施例的一种功能基板的结构示意图。
图35为本公开实施例的一种电感的俯视图。
图36为本公开实施例的滤波电路的电路图。
图37为图34所示的功能基板的制备方法的步骤S51所形成的中间产品示意图。
图38为图34所示的功能基板的制备方法的步骤S52所形成的中间产品示意图。
图39为图34所示的功能基板的制备方法的步骤S53所形成的中间产品示意图。
图40为图34所示的功能基板的制备方法的步骤S54所形成的中间产品示意图。
图41为图34所示的功能基板的制备方法的步骤S55所形成的中间产品示意图。
图42为图34所示的功能基板的制备方法的步骤S56所形成的中间产品示意图。
图43为图34所示的功能基板的制备方法的步骤S57所形成的中间产品示意图。
图44为图34所示的功能基板的制备方法的步骤S58所形成的中间产品示意图。
图45为图34所示的功能基板的制备方法的步骤S59所形成的中间产品示意图。
图46为图34所示的功能基板的制备方法的步骤S510所形成的中间产品示意图。
图47为图34所示的功能基板的制备方法的步骤S511所形成的中间产品示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
第一方面，本公开实施例提供一种功能基板，其包括第一介质基板，该第一介质基板包括沿其厚度方向相对设置的第一表面和第二表面。第一介质基板具有第一连接孔。第一连接孔至少贯穿第一表面，也就是说第一连接孔 可以通孔也可以是盲孔。该功能基板还包括设置在第一连接孔内的第一连接电极。
在本公开实施例中，第一连接孔包括沿背离第二表面的方向依次设置、且连通的第一子孔和第二子孔；第二子孔贯穿第一表面；第二子孔的开口宽度在沿背离第二表面的方向上单调增，且第二子孔的最小开口宽度不小于第一子孔的最大开口宽度；第一子孔和第二子孔的连接位置形成拐角。可以理解的是，第一连接孔的第二子孔贯穿第一表面的开口的尺寸相对较大，因此可以有效地降低在第一表面上形成与第一连接电极连接的导电结构时，热应力的影响，从而降低断线等不良的发生。
以下结合具体示例对本公开实施例的功能基板的结构及其制备方法进行说明。
第一种示例：图1为本公开实施例的第一种示例的功能基板的示意图；如图1所示，在该功能基板中，第一连接孔11贯穿第一介质基板10，且该第一连接孔11仅包括第一子孔111和第二子孔112。第二子孔112贯穿第一表面；第二子孔112的开口宽度在沿背离第二表面的方向上单调增，且第二子孔112的最小开口宽度不小于第一子孔111的最大开口宽度；第一子孔111和第二子孔112的连接位置形成拐角。
针对该功能基板，本公开实施例中提供了该功能基板的制备方法。图4为本公开实施例的第一种示例的功能基板的制备方法的步骤S11所形成的中间产品示意图；图5为本公开实施例的第一种示例的功能基板的制备方法的步骤S12所形成的中间产品示意图；图6为本公开实施例的第一种示例的功能基板的制备方法的步骤S13所形成的中间产品示意图；图7为本公开实施例的第一种示例的功能基板的制备方法的步骤S14所形成的中间产品示意图；图8为本公开实施例的第一种示例的功能基板的制备方法的步骤S15所形成的中间产品示意图；图9为本公开实施例的第一种示例的功能基板的制备方法的步骤S16所形成的中间产品示意图；图10为本公开实施例的第一种示例的功能基板的制备方法的步骤S17所形成的中间产品示意图；图11为本公开实施例的第一种示例的功能基板的制备方法的步骤S18所形成 的中间产品示意图。结合图4-11所示，该制备方法具体包括如下步骤：
S11、提供一第一介质基板10，并在第一介质基板10的第一表面上形成光刻胶层。
在一些示例中，第一介质基板10可以选用玻璃基板，其厚度在0.25mm-0.3mm左右。采用包括但不限于旋涂的方式将感光树脂材料，也即光刻胶层涂覆在第一介质基板10的第一表面上，之后进行110℃/150s的前烘烤定形。光刻胶层的材料包括当不限于BL-301、DL-1000C等，光刻胶层的厚度在2μm～10μm。
S12、对光刻胶层100进行曝光、显影、刻蚀，形成完全曝光区100a和未曝光区100b，并将完全曝光区100a的光刻胶层材料去除，完全曝光区100a的对应待形成的第一连接孔11。
在一些示例中，步骤S12包括用曝光机和相应的掩膜版Mask对光刻胶层100进行图形化曝光，根据光刻胶层100的厚度调整曝光时间(8～20s)，将需要进行TGV开孔位置的树脂进行曝光、显影(80～100s显影3次)，漏出完全曝光区100a位置的第一介质基板10。
S13、对完全曝光区100a位置处的第一介质基板10进行激光辐照，对该位置处的第一介质基板10的材料进行分子键改性。
在一些示例中，步骤S13具体可以采用激光诱导刻蚀的方式形成第一连接孔11。
S14、分别对第一介质基板10的第一表面和第二表面进行刻蚀，形成第一连接孔11。
在一些示例中，步骤S14可以包括：对第一介质基板10的第一表面和第二表面分别使用双面刻蚀液刻蚀，经过激光改性的玻璃的刻蚀速率增加，实现第一介质基板10的厚度方向上各向异性刻蚀，由于光刻胶层的未曝光区的阻挡作用，刻蚀液同时对第一介质基板10的第一表面附近进行各向同性刻蚀，各向同性刻蚀与各向异性刻蚀叠加形成单钉子头通孔结构，也即所形成的第一连接过孔包括第一子孔111和第二子孔112。通过调整刻蚀液的 浓度、温度等控制刻蚀速率，从而调整钉子头的直径。需要注意的是，钉子头(也即第二子孔112位于第一表面的开口)的直径需要小于第一表面和第二表面的第一层金属走线的线宽，相邻TGV孔的钉子头的间距要大于第一层走线的线间距。
S15、在第一连接孔11内形成第一种子层200，并进行电镀。
在一些示例中，步骤S15可以包括但不限于磁控溅射的方式形成辅助膜层，之后连续溅射第一导电膜层，将第一导电膜层作为第一种子层200，对第一种子层进行电镀。
其中，辅助膜层的作用是为了增加第一导电膜层的附着力。辅助膜层的材料包括但不限于钛Ti，第一导电膜层的材料包括但不限于Cu。辅助膜层的厚度在10nm～300nm左右，第一导电膜层的厚度在30nm～100nm左右。
S16、去除光刻胶层背离第一介质基板10一侧和第一介质基板10的第二表面的第一导电膜层，形成膜层201。
在一些示例中，步骤16中可以使用化学机械抛光(CMP)的方法将光刻胶层背离第一介质基板10一侧和第二表面多余的电镀铜去除干净。
S17、去除第一介质基板10的第一表面的光刻胶层100b。
在一些示例中，步骤S17可以采用strip方式进行脱胶，露出高出第一表面的第一导电膜层的结构。
S18、去除第一表面的第一表面的第一导电膜层的结构，形成第一连接电极23。
在一些示例中，步骤18中可以使用化学机械抛光(CMP)的方法将第一表面上多余的第一导电膜层的结构去除。
由于所形成的第一连接过孔的总长度长度L0为第一介质基板10的的厚度(250μm～300μm)，第二子孔112的高度L1(5μm～20μm)，第一连接过孔和第一介质基板10(玻璃基板)的热膨胀系数分别为α1＝17.5ppm/℃和α2＝3.2ppm/℃，功能基板的制备过程中最高温度为T1，室温为T0，温度变化为T1-T0。因此，制程中温度的变化引起第二子孔112相对于第一介质基 板10的应变量为：
ε2＝L1×(T1-T0)×(α1-α2)
第二子孔112的高度L1取决于刻蚀时间，一般选择为5μm～20μm，此处选择为5μm，制程最高温度T1仍为230℃，室温T0＝25℃的情况，第二子孔112相对于第一介质基板10的应变量ε2＝14nm。
具第二子孔112的第一连接孔11的膨胀量仅为传统的第一连接孔11的1/50，可极大降低第一连接孔11内填充第一连接电极23的应力，减少断线等不良的发生，提高器件的可靠性。
第二种示例：图2为本公开实施例的第二种示例的功能基板的示意图；如图2所示，该种示例中的第一连接孔11的结构与第一种示例的结构相似，区别在于，该第一连接孔11不仅包括第一子孔111和第二子孔112，而且还包括贯穿第一介质基板10的第二表面、且与第一子孔111连通的第三子孔113。第三子孔113的开口宽度在沿背离第二表面的方向上单调减，且第三子孔113的最小开口宽度不小于第一子孔111的最大开口宽度；第一子孔111和第三子孔113的连接位置形成拐角。也就是说，所形成第一连接孔11的两端均为钉子头结构。该种结构不仅在第一表面上形成与第一连接电极23连接的导电结构时，热应力的影响，而且还可以降低在第二表面上形成与第一连接电极23连接的导电结构时，热应力的影响，从而降低第一表面和第二表面上出现断线等不良的发生。
针对该功能基板，本公开实施例中提供了该功能基板的制备方法。图12为本公开实施例的第二种示例的功能基板的制备方法的步骤S21所形成的中间产品示意图；图13为本公开实施例的第二种示例的功能基板的制备方法的步骤S22所形成的中间产品示意图；图14为本公开实施例的第二种示例的功能基板的制备方法的步骤S23所形成的中间产品示意图；图15为本公开实施例的第二种示例的功能基板的制备方法的步骤S24所形成的中间产品示意图；图16为本公开实施例的第二种示例的功能基板的制备方法的步骤S25所形成的中间产品示意图；图17为本公开实施例的第二种示例 的功能基板的制备方法的步骤S26所形成的中间产品示意图；图18为本公开实施例的第二种示例的功能基板的制备方法的步骤S27所形成的中间产品示意图；图19为本公开实施例的第二种示例的功能基板的制备方法的步骤S28所形成的中间产品示意图。结合图12-19所示，该方法具体包括如下步骤。
S21、提供一第一介质基板10，并在第一介质基板10的第一表面上形成第一光刻胶层110，在第二表面形成第二光刻胶层120。
在一些示例中，第一介质基板10可以选用玻璃基板，其厚度在0.25mm-0.3mm左右。采用包括但不限于旋涂的方式形成第一表面和第二表面上的感光树脂材料，也即第一光刻胶层涂覆在第一介质基板10的第一表面上，第二光刻胶层涂覆在第一介质基板10的第二表面上，之后进行110℃/150s的前烘烤定形。第一光刻胶层和第二光刻胶层的材料包括当不限于BL-301、DL-1000C等，第一光刻胶层和第二光刻胶层的厚度在2μm～10μm。
S22、分别对第一光刻胶层110和第二光刻胶层120进行曝光、显影、刻蚀，形成完第一全曝光区110a和第一未曝光区110b，以及第二全曝光区120a和第二未曝光区120b，并将第一完全曝光区110a和第二完全曝光区120a的光刻胶层材料去除，第一完全曝光区110a和第二完全曝光区120a的对应待形成的第一连接孔11。
在一些示例中，步骤S22包括用曝光机和相应的掩膜版Mask分别对第一光刻胶层和第二光刻胶层进行图形化曝光，根据第一光刻胶层110和第二光刻胶层120的厚度调整曝光时间(8～20s)，将需要进行TGV开孔位置的树脂进行曝光、显影(80～100s显影3次)，漏出第一完全曝光区110a和第二完全曝光区120a位置处的第一介质基板10。
S23、对第一完全曝光区110a和第二完全曝光区120a位置处的第一介质基板10进行激光辐照，分别对第一完全曝光区110a和第二完全曝光区120a位置处的第一介质基板10的材料进行分子键改性。
在一些示例中，步骤S23具体可以采用激光诱导刻蚀的方式形成第一连 接孔11。
S24、分别对第一介质基板10的第一表面和第二表面进行刻蚀，形成第一连接孔11。
在一些示例中，步骤S14可以包括：对第一介质基板10的第一表面和第二表面分别使用双面刻蚀液刻蚀，经过激光改性的玻璃的刻蚀速率增加，实现第一介质基板10的厚度方向上各向异性刻蚀，由于第一光刻胶层110的第一未曝光区110b和第二光刻胶层120的第二未曝光区120b的阻挡作用，刻蚀液同时对第一介质基板10的第一表面附近进行各向同性刻蚀，各向同性刻蚀与各向异性刻蚀叠加形成双钉子头通孔结构，也即所形成的第一连接过孔包括第一子孔111、第二子孔112和第三子孔113。通过调整刻蚀液的浓度、温度等控制刻蚀速率，从而调整钉子头的直径。需要注意的是，钉子头(也即第二子孔112位于第一表面的开口)的直径需要小于第一表面和第二表面的第一层金属走线的线宽，相邻TGV孔的钉子头的间距要大于第一层走线的线间距。
S25、在第一连接孔11内形成第一种子层200，并进行电镀。
在一些示例中，步骤S15可以包括但不限于磁控溅射的方式形成辅助膜层，之后连续溅射第一导电膜层，将第一导电膜层作为第一种子层200，对第一种子层200进行电镀。
其中，辅助膜层的作用是为了增加第一导电膜层的附着力。辅助膜层的材料包括但不限于钛Ti，第一导电膜层的材料包括但不限于Cu。辅助膜层的厚度在10nm～300nm左右，第一导电膜层的厚度在30nm～100nm左右。
S26、去除第一光刻胶层和第二光刻胶层背离第一介质基板10一侧的第一导电膜层。
在一些示例中，步骤26中可以使用化学机械抛光(CMP)的方法将光刻胶层背离第一介质基板10一侧和第二表面多余的电镀铜去除干净。
S27、去除第一介质基板10的第一表面的第一光刻胶层110b和第二光刻胶层120b。
在一些示例中，步骤S27可以采用strip方式进行脱胶，露出高出第一表面和第二表面的第一导电膜层的结构201。
S28、去除第一表面和第二表面的第一表面的第一导电膜层的结构，形成第一连接电极23。
在一些示例中，步骤28中可以使用化学机械抛光(CMP)的方法将第一表面和第二表面上多余的第一导电膜层的结构去除。
该双钉子头的第一连接孔11方案具有缓解双面RDL应力的特点，主要应用于具有双面RDL金属走线的三维玻璃基器件以及较厚(>250μm)的玻璃基载板的制作。
第三种示例：图3为本公开实施例的第三种示例的功能基板的示意图；如图3所示，该种示例的功能基板中的第一连接孔11可以为盲孔，该第一连接孔11的包括第一子孔111和第二子孔112，第一子孔111与第一种示例不同，第一种示例中的第一子孔111是由双面刻蚀形成的故为沙漏状，而在该种示例中，第二子孔112呈倒梯形。
针对该功能基板，本公开实施例中提供了该功能基板的制备方法。图20为本公开实施例的第三种示例的功能基板的制备方法的步骤S31所形成的中间产品示意图；图21为本公开实施例的第三种示例的功能基板的制备方法的步骤S32所形成的中间产品示意图；图22为本公开实施例的第三种示例的功能基板的制备方法的步骤S33所形成的中间产品示意图；图23为本公开实施例的第三种示例的功能基板的制备方法的步骤S34所形成的中间产品示意图；图24为本公开实施例的第三种示例的功能基板的制备方法的步骤S35所形成的中间产品示意图；图25为本公开实施例的第三种示例的功能基板的制备方法的步骤S36所形成的中间产品示意图；图26为本公开实施例的第三种示例的功能基板的制备方法的步骤S37所形成的中间产品示意图。结合图20-26所示，该方法具体包括如下步骤。
S31、提供一第一介质基板10，并在第一介质基板10的第一表面上形成光刻胶层；对光刻胶层进行曝光、显影、刻蚀，形成第三完全曝光区100c 和第四未曝光区100d，并将第三完全曝光区100c的光刻胶层材料去除，第三完全曝光区100c的对应待形成的第一连接孔11。
在一些示例中，第一介质基板10可以选用玻璃基板，其厚度在0.25mm-0.3mm左右。采用包括但不限于旋涂的方式将感光树脂材料，也即光刻胶层涂覆在第一介质基板10的第一表面上，之后进行110℃/150s的前烘烤定形。光刻胶层的材料包括当不限于BL-301、DL-1000C等，光刻胶层的厚度在2μm～10μm。
采用曝光机和相应的掩膜版Mask对光刻胶层进行图形化曝光，根据光刻胶层的厚度调整曝光时间(8～20s)，将需要进行TGV开孔位置的树脂进行曝光、显影(80～100s显影3次)，漏出完全曝光区位置的第一介质基板10。
S32、对第三完全曝光区100c位置处的第一介质基板10进行激光辐照，对该位置处的第一介质基板10的材料进行分子键改性。
在一些示例中，步骤S32具体可以采用激光诱导刻蚀的方式形成第一连接孔11。
S33、分别对第一介质基板10的第一表面进行刻蚀，形成第一连接孔11。
在一些示例中，步骤S33可以包括：对第一介质基板10的第一表面和使用刻蚀液刻蚀，经过激光改性的玻璃的刻蚀速率增加，实现第一介质基板10的厚度方向上各向异性刻蚀，由于光刻胶层的未曝光区100d的阻挡作用，刻蚀液同时对第一介质基板10的第一表面附近进行各向同性刻蚀，各向同性刻蚀与各向异性刻蚀叠加形成单钉子头通孔结构，也即所形成的第一连接过孔包括第一子孔111和第二子孔112。通过调整刻蚀液的浓度、温度等控制刻蚀速率，从而调整钉子头的直径。需要注意的是，钉子头(也即第二子孔112位于第一表面的开口)的直径需要小于第一表面的第一层金属走线的线宽，相邻TGV孔的钉子头的间距要大于第一层走线的线间距。
S34、在第一连接孔11内形成第一种子层200，并进行电镀。
在一些示例中，步骤S34可以包括但不限于磁控溅射的方式形成辅助膜层，之后连续溅射第一导电膜层，将第一导电膜层作为第一种子层200，对第一种子层200进行电镀。
其中，辅助膜层的作用是为了增加第一导电膜层的附着力。辅助膜层的材料包括但不限于钛Ti，第一导电膜层的材料包括但不限于Cu。辅助膜层的厚度在10nm～300nm左右，第一导电膜层的厚度在30nm～100nm左右。
S35、去除光刻胶层背离第一介质基板10一侧的第一导电膜层。
在一些示例中，步骤35中可以使用化学机械抛光(CMP)的方法将光刻胶层背离第一介质基板10一侧多余的电镀铜去除干净。
S36、去除第一介质基板10的第一表面的光刻胶层。
在一些示例中，步骤S36可以采用strip方式进行脱胶，露出高出第一表面的第一导电膜层的结构201。
S37、去除第一表面的第一表面的第一导电膜层的结构，形成第一连接电极23。
在一些示例中，步骤37中可以使用化学机械抛光(CMP)的方法将第一表面上多余的第一导电膜层的结构去除。
需要说明的是，在步骤S37之后还可以对第一介质基板10的第二表面进行减薄，将第一连接电极23裸露，以便在后续的第二表面形成金属导线结构。
第四种示例：该种示例与第二种示例的结构大致相同，区别在于，在第一表面上形成有第一缓冲层，在第二表面上形成第二缓冲层。其中，第一缓冲层和第二缓冲层均可以采用树脂材料，例如光刻胶。在该种情况下，第一缓冲层和第二缓冲层均可以采用对第一介质基板10的改性时所用的光刻胶层。具体结合下述制备方法进行说明。
针对该功能基板，本公开实施例中提供了该功能基板的制备方法。图27为本公开实施例的第四种示例的功能基板的制备方法的步骤S41所形成的中间产品示意图；图28为本公开实施例的第四种示例的功能基板的制备 方法的步骤S42所形成的中间产品示意图；图29为本公开实施例的第四种示例的功能基板的制备方法的步骤S43所形成的中间产品示意图；图30为本公开实施例的第四种示例的功能基板的制备方法的步骤S44所形成的中间产品示意图；图31为本公开实施例的第四种示例的功能基板的制备方法的步骤S45所形成的中间产品示意图；图32为本公开实施例的第四种示例的功能基板的制备方法的步骤S46所形成的中间产品示意图；图33为本公开实施例的第四种示例的功能基板的制备方法的步骤S47所形成的中间产品示意图。结合图27-33所示，该方法具体包括如下步骤。
S41、提供一第一介质基板10，并在第一介质基板10的第一表面上形成第三光刻胶层130，在第二表面形成第四光刻胶层140。
在一些示例中，第一介质基板10可以选用玻璃基板，其厚度在0.25mm-0.3mm左右。采用包括但不限于旋涂的方式形成第一表面和第二表面上的感光树脂材料，也即第三光刻胶层130涂覆在第一介质基板10的第一表面上，第四光刻胶层140涂覆在第一介质基板10的第二表面上，之后进行110℃/150s的前烘烤定形。第三光刻胶层130和第四光刻胶层140的材料包括当不限于BL-301、DL-1000C等，第三光刻胶层130和第四光刻胶层140的厚度在2μm～10μm。
S42、分别对第三光刻胶层130和第四光刻胶层140进行曝光、显影、刻蚀，形成第一半曝光区130a和第四未曝光区130b，以及第二半曝光区140a和第五未曝光区140b，并将第一半曝光区130a和第二半曝光区140a的部分光刻胶材料去除。
在一些示例中，步骤S42包括用曝光机和相应的掩膜版Mask分别对第三光刻胶层130和第四光刻胶层140进行图形化曝光，根据第三光刻胶层130和第四光刻胶层140的厚度调整曝光时间(8～20s)，将需要进行TGV开孔位置的树脂进行曝光、显影(80～100s显影1次)。
S43、对第一半曝光区130a和第二半曝光区140a的光刻胶进行曝光、显影、刻蚀，形成第四完全曝光区130c和第五完全曝光区140c。
在一些示例中，步骤S43包括用曝光机和相应的掩膜版Mask分别对第三光刻胶层130和第四光刻胶层140进行图形化曝光，根据第三光刻胶层130和第四光刻胶层140的厚度调整曝光时间(8～20s)，将需要进行TGV开孔位置的树脂进行曝光、显影(80～100s显影2次)，漏出第四完全曝光区130c和第五完全曝光区140c位置处的第一介质基板10。
S44、对第四完全曝光区130c和第五完全曝光区140c位置处的第一介质基板10进行激光辐照，分别对第四完全曝光区130c和第五完全曝光区140c位置处的第一介质基板10的材料进行分子键改性。
在一些示例中，步骤S44具体可以采用激光诱导刻蚀的方式形成第一连接孔11。
S45、分别对第一介质基板10的第一表面和第二表面进行刻蚀，形成第一连接孔11。
在一些示例中，步骤S45可以包括：对第一介质基板10的第一表面和第二表面分别使用双面刻蚀液刻蚀，经过激光改性的玻璃的刻蚀速率增加，实现第一介质基板10的厚度方向上各向异性刻蚀，由于第三光刻胶层130和第四光刻胶层140的阻挡作用，刻蚀液同时对第一介质基板10的第一表面附近进行各向同性刻蚀，各向同性刻蚀与各向异性刻蚀叠加形成双钉子头通孔结构，也即所形成的第一连接过孔包括第一子孔111、第二子孔112和第三子孔113。通过调整刻蚀液的浓度、温度等控制刻蚀速率，从而调整钉子头的直径。需要注意的是，钉子头(也即第二子孔112位于第一表面的开口)的直径需要小于第一表面和第二表面的第一层金属走线的线宽，相邻TGV孔的钉子头的间距要大于第一层走线的线间距。
S46、在第一连接孔11内形成第一种子层200，并进行电镀。
在一些示例中，步骤S46可以包括但不限于磁控溅射的方式形成辅助膜层，之后连续溅射第一导电膜层，将第一导电膜层作为第一种子层200，对第一种子层200进行电镀。
其中，辅助膜层的作用是为了增加第一导电膜层的附着力。辅助膜层的 材料包括但不限于钛Ti，第一导电膜层的材料包括但不限于Cu。辅助膜层的厚度在10nm～300nm左右，第一导电膜层的厚度在30nm～100nm左右。
S47、去除第三光刻胶层130b和第四光刻胶层140b背离第一介质基板10一侧的第一导电膜层，并形成第一缓冲层和第二缓冲层(也即剩余的第三光刻胶层和第四光刻胶层材料)。
在一些示例中，步骤47中可以使用化学机械抛光(CMP)的方法将光刻胶层背离第一介质基板10一侧和第二表面多余的电镀铜去除干净。
以上给出了四种示例中功能基板上的第一连接孔11和第一连接电极23的制备方法。本公开实施例找那个的功能基板不仅包括上述结构，还包括位于第一表面上的第一导电层，当然当第一连接孔11为通孔时，还可以包括位于第二表面上的第二导电层。
在一些示例中，图35为本公开实施例的一种功能基板的示意图；如图35所示，该功能基板上集成有电容、电感等结构，也即该功能基板为具有滤波功能的基板。图36为本公开实施例的电感的俯视图，参照图35和36，电感的各第一子结构21均沿第一方向延伸，且沿第二方向并排设置；电感的各第二子结构22均沿第三方向延伸，且沿第二方向并排设置。其中，第一方向、第二方向、第三方向均为不同的方向，在本公开实施例中，以第一方向和第二方向相互垂直，第一方向和第三方向相交且非垂直设置为例。当然，第一子结构21和第二子结构22的延伸方向也可以互换，均在本公开实施例的保护范围内。另外，在本公实施例中以电感包括N个第一子结构21和N-1个第二子结构22为例进行说明，其中，N≥2，且N为整数。第一子结构21的第一端和第二端分别与一个第一连接过孔11在第一介质基板上正投影至少部分交叠。且一个第一子结构21的第一端和第二端对应不同的第一连接过孔11，也即一个第一子结构21与两个第一连接过孔11在第一介质基板上正投影至少部分交叠。此时，电感的第i个第二子结构22第一端连接第i个第一子结构21的第一端和第i+1个第一子结构21的第二端，形成电感线圈，其中，1≤i≤N-1，且i为整数。
在此需要说明的是，其中，第一引线端24与电感线圈的第一个第一子结构21的第二端，第二引线端25则与第N个第一子结构21的第一端连接。进一步的，第一引线端24和第二引线端25可以与第二子结构22同层设置，且采用相同的材料，此时第一引线端24可以通过第一连接过孔11与第一个第一子结构21的第二端连接，相应的，第二引线端25则可以通过第一连接过孔11与第N个第一子结构21的第一端连接。
图37为一种滤波电路图；如图37所示，该滤波电路包括两个电感和一电容和一个电阻。其中，为了便于理解分别将两个电感称之为第一电感L1和第二电感L2。继续参照图2，第一电感L1的第一引线端连接电阻R第一端，第一电感的第二引线端连接电容C的第二极板，第二电感L2的第一引线端连接电阻R的第一端，第二电感L2的第二引线端连接电容C的第一极板。
需要说明的是，电阻R可以通过导线实现，也可以通过电阻R可以采用高阻材料，例如，例如氧化锡(ITO)、镍铬(NiCr)合金。在本公开实施例中，对电阻R的形成不进行限定，以下主要对电容和电感进行介绍。
进一步的，当功能基板上的电容和电感形成滤波电路时，电容的第一极板可以与电感的第一子结构同层设置。在电容的第一极板31背离的一侧设置第一层间介质层4，并在第一层间介质层4背离电容的第一极板31的一侧设置电容的第二极板32；在电容的第二极板32背离的一层设置第二层间介质层5，在第二层间介质层5背离的一侧设置有第二连接电极61和第三连接电极62，第二连接电极61通过贯穿第一层间介质层4和第二层间介质层5的第二连接过孔与第电感的第一子结构21连接；第三连接电极62通过贯穿第二层间介质层5的第三连接过孔与电容的第二极板32连接。第二连接电极61和第三连接电极62背离第一介质基板10的一侧依次设置有第一保护层78和第一平坦化层101；并形成贯穿第一保护层7和第一平坦化层101的第四连接过孔91和第五连接过孔。第一连接焊盘102和第二连接焊盘103分别形成在第四连接过孔和第五连接过孔。其中，第一连接焊盘102和第二连接焊盘103可以为焊锡。
继续参照34，在第二子结构22背离第一介质基板10的一侧可以形成第三保护层和第三平坦化层，以对第二子结构22进行保护，防止水氧侵蚀。
在一些示例中，第一连接过孔11内的第一连接电极25仅覆盖第一连接过孔11的内壁，而并非将第一连接过孔11填充满。
进一步的，当第一连接电极25仅覆盖第一连接过孔11的内壁时，限定出位于第一连接过孔内的第一容纳空间，此时可以在第一容纳空间内填充树脂材料作为填充结构，防止第一连接电极25氧化的同时起到一定的支撑作用。
为了更清楚本公开实施例的功能基板的结构，以下以第一介质基板上形成有双钉子头结构的第一连接孔，且在第一连接孔内形成第一连接电极后形成电感和电容的功能基板的制备方法进行说明。图37为图34所示的功能基板的制备方法的步骤S51所形成的中间产品示意图。图38为图34所示的功能基板的制备方法的步骤S52所形成的中间产品示意图；图39为图34所示的功能基板的制备方法的步骤S53所形成的中间产品示意图；图40为图34所示的功能基板的制备方法的步骤S54所形成的中间产品示意图；图41为图34所示的功能基板的制备方法的步骤S55所形成的中间产品示意图；图42为图34所示的功能基板的制备方法的步骤S56所形成的中间产品示意图；图43为图34所示的功能基板的制备方法的步骤S57所形成的中间产品示意图；图44为图34所示的功能基板的制备方法的步骤S58所形成的中间产品示意图；图45为图34所示的功能基板的制备方法的步骤S59所形成的中间产品示意图；图46为图34所示的功能基板的制备方法的步骤S510所形成的中间产品示意图；图47为图34所示的功能基板的制备方法的步骤S511所形成的中间产品示意图。结合图37-47所示，本公开实施例的功能基板制备方法包括如下步骤。
S51、在第一介质基板10的第一表面上形成电感的第一子结构21和电容的第一极板31。
在一些示例中，第一子结构21包括依次叠层设置在第一介质基板10的 第一表面上的第一部分211、第二部分212和第三部分213，电容的第一极板31包括依次叠层设置在第一介质基板10的第一表面上的第四部分311、第五部分312和第六部分313，其中，第一部分211和第四部分311同层设置且二者材料相同；第二部分212和第五部分312同层设置且二者材料相同；第三部分213和第六部分313同层设置且二者材料相同。步骤S51具体可以包括如下步骤。
S511、在第一介质基板10的第一表面采用包括但不限于磁控溅射的方式，依次沉积第一膜层、第二膜层和第三膜层；其中，第一膜层可以为钼(Mo)、镍(Ni)合金层，厚度在0.03μm～0.05μm左右；第二膜层可以为铜(Cu)层，厚度在0.3μm～0.5μm左右；第三膜层可以为Mo、Ni合金层，厚度在0.02μm～0.05μm左右。
S512、通过减成法对第一膜层、第二膜层和第三膜层进行图案化，形成包括叠层设置的第一部分211、第二部分212和第三部分213的电感的第一子结构21，以及包括叠层设置的第四部分311、第五部分312和第六部分313的电容的第一极板31。例如：在第三膜层背离第一介质基板10的表面旋涂光刻胶，采用对应的掩膜版mask进行曝光，紫外光辐照过的光刻胶发生变性，然后进行显影，将变性的光刻胶显影去除，然后用铜的刻蚀液将未被光刻胶保护区域的铜刻蚀掉，形成包括叠层设置的第一部分211、第二部分212和第三部分213的电感的第一子结构21，以及包括叠层设置的第四部分311、第五部分312和第六部分313的电容的第一极板31。
需要说明的是，电感的第一子和电容的第一极板31所在层在整个器件中非常关键，其实现的功能一方面为电容的极板，因此对平整度要求较高，如果是电镀的厚铜，则需要对其进行化学机械平坦化。另一功能是第一子结构21作为TGV孔(第一连接过孔11)之间连接的连接结构以及电感与电容之间的连接。为保证与后续所形成的第一连接孔内第一连接电极25的连接处导通的可靠性，第一子结构21的边缘超出第一连接过孔11内第一连接电极25的边缘5um～10μm。
S52、在电感的第一子结构21和电容的第一极板31背离第一介质基板 10的一侧，形成第一层间介质层4。
在一些示例中，步骤S52可以包括在电感的第一子结构21和电容的第一极板31背离第一介质基板10的一侧，采用离子体增强化学气相沉积(PECVD)等标准工艺，沉积形成第一层间介质层4。
其中，第一层间介质层4的材料为无机绝缘材料。例如：第一层间介质层4为由氮化硅(SiNx)形成的无机绝缘层，或者由氧化硅(SiO 2)形成的无机绝缘层，亦或者由SiNx无机绝缘层和SiO 2无机绝缘层的若干种叠层组合膜层。当然，该第一层间介质层4也作为电容的中间介质层。第一层间的介质的厚度在120nm左右。
S53、在第一层间介质层4背离第一介质基板10的一侧形成包括电容的第二极板32的图形。
在一些示例中，步骤S53可以采用包括但不限于磁控溅射的方式，依次沉积第四膜层、第五膜层和第六膜层，在第六膜层背离第一介质基板10的表面旋涂光刻胶，采用对应的掩膜版mask进行曝光，紫外光辐照过的光刻胶发生变性，然后进行显影，将变性的光刻胶显影去除，然后用铜的刻蚀液将未被光刻胶保护区域的铜刻蚀掉，形成包括叠层设置的第七部分321、第八部分322和第九部分323的电容的第二极板32。
其中，第四膜层可以为钼(Mo)、镍(Ni)合金层，厚度在0.03μm～0.05μm左右；第五膜层可以为铜(Cu)层，厚度在0.3μm～0.5μm左右；第六膜层可以为Mo、Ni合金层，厚度在0.02μm～0.05μm左右。
S54、形成第二层间介质层5。
在一些示例中，步骤S54包括在电容的第二极板32背离第一介质基板10的一侧，采用PECVD等标准工艺，沉积形成第二层间介质层5。
其中，第二层间介质层5的材料可以与第一层间介质层4采用相同的材料，其厚度在0.2μm～0.5μm。
S55、在形成贯穿第一层间介质和第二层间介质层5的第二连接过孔，以及贯穿第二层间介质层5的第三连接过孔。
在一些示例中，步骤S55包括通过干法刻蚀，形成贯穿第一层间介质层4和第二层间介质层5的第二连接过孔，以及贯穿第二层间介质层5的第三连接过孔。
S56、形成第二连接电极61和第三连接电极62，第二连接电极61通过第二连接过孔与电感的引线端连接，第三连接电极62通过第三连接过孔与电容的第二极板32电连接。
在一些示例中，步骤S56可以包括在第二层间介质层5背离第一介质基板10的一侧，采用包括但不限于磁控溅射的方式，依次形成第七膜层60和第八膜层，将第八膜层作为第三种子层，对第三种子层进行电镀，再对电镀长厚的第八膜层和第七膜层60进行图案化处理形成第二连接电极61和第三连接电极62。
其中，第七膜层可以为钼(Mo)、镍(Ni)合金层，厚度在0.03μm～0.05μm左右；第八膜层可以为铜(Cu)层，厚度在0.3μm～0.5μm左右。之所以设置第七膜层60是为了增加第八膜层的附着力。
S57、形成第一保护层7。
在一些示例中，步骤S57包括采用PECVD等标准工艺，依次沉积形成第一保护层7。
其中，第一保护层7用于防止水氧侵蚀第一介质基板10的第一表面上形成器件。该第一保护层7的厚度在0.4μm～0.6μm；该第一保护层7材料可以为无机绝缘材料。例如：第一保护层7可以为由氮化硅(SiNx)形成的无机绝缘层，或者由氧化硅(SiO 2)形成的无机绝缘层，亦或者由SiNx无机绝缘层和SiO 2无机绝缘层的若干种叠层组合膜层。
S58、将第一介质基板10翻转，第一介质基板10的第二表面上依次形成电感的第二子结构22，并在第二子结构22背离第一介质基板10的一侧形成第二保护层8。
在一些示例中，步骤S58包括在形成第一连接电极25的第一介质基板10的第二表面上采用包括但不限于磁控溅射的方式，形成第二导电膜层， 作为第二种子层，再对第二种子层进行电镀，电镀后的第二种子层的厚度通常大于5μm，然后进行图形化形成电感的第二子结构22。采用PECVD等标准工艺，依次沉积形成第二保护层8。
其中，第二保护层8用于防止水氧侵蚀第一介质基板10的第一表面上形成器件。该第二保护层8的厚度在0.4μm～0.6μm；该第一保护层7材料可以为无机绝缘材料。例如：第二保护层8可以为由氮化硅(SiNx)形成的无机绝缘层，或者由氧化硅(SiO 2)形成的无机绝缘层，亦或者由SiNx无机绝缘层和SiO 2无机绝缘层的若干种叠层组合膜层。
S59、在第二保护层8背离第一介质基板10的一侧形成第二保护层9。
在一些示例中，可以采用采用PECVD等标准工艺，形成第二保护层9。
第二平坦化层9的厚度在2μm以上；该第二平坦化层9的材料可以包括有机绝缘材料，该有机绝缘材料例如包括聚酰亚胺、环氧树脂、压克力、聚酯、光致抗蚀剂、聚丙烯酸酯、聚酰胺、硅氧烷等树脂类材料等。再例如，该有机绝缘材料包括弹性材料，例如、氨基甲酸乙酯、热塑性聚氨酯(TPU)等。
S510、将第一介质基板10翻转，在第一保护层7背离第一介质基板10的一侧形成第一平坦化层101。
其中，第一平坦化层101的厚度在2μm以上；该第一平坦化层101的材料可以包括有机绝缘材料，该有机绝缘材料例如包括聚酰亚胺、环氧树脂、压克力、聚酯、光致抗蚀剂、聚丙烯酸酯、聚酰胺、硅氧烷等树脂类材料等。再例如，该有机绝缘材料包括弹性材料，例如、氨基甲酸乙酯、热塑性聚氨酯(TPU)等。
S511、对第一保护层和第二保护层进行刻蚀形成第四连接过孔和第五连接过孔。
S512，形成第一连接焊盘102和第二连接焊盘103，第一连接焊盘102和第二连接焊盘103分别形成在第四连接过孔和第五连接过孔对应的位置，如图34所示。
其中，第一连接焊盘102和第二连接焊盘103可以为焊锡。
至此完成滤波器的制备。
在此需要说明的是，在本公开实施例中电容值由第一层间介质层4厚度、第一层间介质层4材料介电常数、第一极板31和第二极板32的正对面积决定。电感值由螺线的匝数、螺线的间距、螺线的直径共同决定。因此，可以通过合理的设计电容的第一层间介质层4材料介电常数、第一极板31和第二极板32的参数，以及对电感线圈的第一子结构21、第二子结构22的尺寸、间距等参数，从而达到优化滤波电路的效果。
第二方面，本公开实施例提供一种电子设备，其包括上述任一功能基板。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (22)

  1. 一种功能基板，其包括第一介质基板；其中，所述第一介质基板包括沿其厚度方向相对设置的第一表面和第二表面；所述第一介质基板具有第一连接孔；所述第一连接孔至少贯穿所述第一表面；所述第一连接孔内设置第一连接电极；
    所述第一连接孔包括沿背离所述第二表面的方向依次设置、且连通的第一子孔和第二子孔；所述第二子孔贯穿所述第一表面；
    所述第二子孔的开口宽度在沿背离所述第二表面的方向上单调增，且所述第二子孔的最小开口宽度不小于所述第一子孔的最大开口宽度；所述第一子孔和所述第二子孔的连接位置形成拐角。
  2. 根据权利要求1所述的功能基板，其中，所述第一连接孔贯穿所述第一表面和第二表面，所述第一连接过孔还包括与所述第一子孔连通，且贯穿所述第二表面的第三子孔；所述第三子孔的开口宽度在沿背离所述第二表面的方向上单调减，且所述第三子孔的最小开口宽度不小于所述第一子孔的最大开口宽度；所述第一子孔和所述第三子孔的连接位置形成拐角。
  3. 根据权利要求1所述的功能基板，其中，所述第一子孔贯穿所述所述第二表面。
  4. 根据权利要求1所述的功能基板，其中，所述第一子孔呈沙漏状。
  5. 根据权利要求1所述的功能基板，其中，所述第一子孔的开口宽度沿背离所述第二表面的方向单调增。
  6. 根据权利要求1所述的功能基板，其中，所述第一连接电极填充所述第一连接孔或者仅覆盖所述第一连接孔的内壁。
  7. 根据权利要求1所述的功能基板，其中，还包括位于所述第一表面上，且与所述第一连接电极连接的第一导电层。
  8. 根据权利要求7所述的功能基板，其中，所述第一连接孔贯穿所述第二表面，所述功能基板还包括位于所述第二表面的第二导电层，且所述第二导电层与所述第一连接电极连接。
  9. 根据权利要求8所述的功能基板，其中，还包括集成在所述第一介质基板上的电感，所述电感包括第一子结构、第二子结构和多个所述第一连接电极；所述第一子结构位于所述第一表面，所述第二子结构位于所述第二表面，且所述第一子结构通过所述第一连接电极与所述第二子结构连接形成所述电感的线圈结构。
  10. 根据权利要求9所述的功能基板，其中，还包括位于所述第一导电层的电容的第一极板；在所述第一导电层背离所述第一介质基板的一侧形成第一层间介质层；在所述第一层间介质层背离所述第一导电层的一侧设置有电容的第二极板。
  11. 根据权利要求10所述的功能基板，其中，还包括设置在所述电容的第二极板背离所述第一介质基板的一侧的第二层间介质层、第二连接电极和第三连接电极；
    所述第二连接电极通过贯穿所述第一层间介质层和第二层间介质层的第二连接孔与所述电感的引线端连接；所述第三连接电极通过贯穿所述第二层间层的第三连接孔与所述电容的第二极板电连接。
  12. 根据权利要求10所述的功能基板，其中，还包括在所述第二连接电极和所述第三连接电极所在层背离所述第一介质基板的一侧，依次设置的第一保护层和第一平坦化层，以及第一连接焊盘和第二连接焊盘；
    所述第一连接焊盘通过第四连接孔连接所述第二连接电极，所述第二连接焊盘通过第五连接孔连接所述第三连接电极；所述第四连接孔和所述第五连接孔均贯穿贯穿所述第一保护层和所述第一平坦化层。
  13. 根据权利要求8所述的功能基板，其中，还包括在所述第二导电层背离所述第一介质基板一侧依次设置的第二保护层和第二平坦化层。
  14. 根据权利要求8所述的功能基板，其中，所述第一连接孔贯穿所述第二表面；所述功能基板还包括设置在所述第一表面上的第一导电层和设置在所述第二表面上的第二导电层，所述第一导电层和所述第二导电层通过所述第一连接孔连接；在所述第一导电层和所述第一表面之间设置有第一缓冲 层；在所述第二导电层和所述第二表面之间设置有第二缓冲层。
  15. 一种功能基板的制备方法，其包括：
    提供一第一介质基板；所述第一介质基板包括沿其厚度方向相对设置的第一表面和第二表面；
    在所述第一介质基板上形成第一连接孔；所述第一连接孔至少贯穿所述第一表面；所述第一连接孔包括沿背离所述第二表面的方向依次设置、且连通的第一子孔和第二子孔；所述第二子孔贯穿所述第一表面；所述第二子孔的开口宽度在沿背离所述第二表面的方向上单调增，且所述第二子孔的最小开口宽度不小于所述第一子孔的最大开口宽度；所述第一子孔和所述第二子孔的连接位置形成拐角；
    形成位于所述第一连接孔内的第一连接电极。
  16. 根据权利要求15所述的功能基板的制备方法，其中，形成所述第一连接孔的步骤包括：
    提供一所述第一介质基板，在所述第一介质基板的所述第一表面形成光刻胶层；
    对光刻胶层进行曝光、显影、刻蚀，形成与所述第一连接孔位置对应的完全曝光区和未曝光区；
    对第一介质基板对应所述完全曝光区的位置进行激光辐照，并去除所述完全曝光区的位置的第一介质基板的材料，形成所述第一连接孔。
  17. 根据权利要求16所述的功能基板的制备方法，其中，所述第一连接孔贯穿所述第二表面
  18. 根据权利要求15所述的功能基板的制备方法，其中，形成所述第一连接孔的步骤包括：
    提供一所述第一介质基板，在所述第一介质基板的所述第一表面形成第一光刻胶层，在所述第二表面形成第二光刻胶层；对所述第一光刻胶层进行曝光、显影、刻蚀，形成与所述第一连接孔位置对应的完全第一曝光区和第 一未曝光区；对所述第二光刻胶层进行曝光、显影、刻蚀，形成与所述第一连接孔位置对应的完全第二曝光区和第二未曝光区；
    分别对第一介质基板对应所述第一完全曝光区和所述第二完全曝光区的位置进行激光辐照，并去除所述第一完全曝光区和所述第二完全曝光区的位置的第一介质基板的材料，形成所述第一连接孔；所述第一连接孔贯穿所述第二表面。
  19. 根据权利要求15所述的功能基板的制备方法，其中，还包括在所述第一表面上形成第一导电层的步骤；所述第一导电层与所述第一连接电极连接。
  20. 根据权利要求19所述的功能基板的制备方法，其中，还包括在所述第二表面上形成第二导电层的步骤；所述第二导电层与所述第一连接电极连接。
  21. 根据权利要求20所述的功能基板的制备方法，其中，还包括在所述第一介质基板上形成电感；所述电感包括第一子结构、第二子结构和多个所述第一连接电极；所述第一子结构位于所述第一表面，所述第二子结构位于所述第二表面，且所述第一子结构通过所述第一连接电极与所述第二子结构连接形成所述电感的线圈结构。
  22. 一种电子设备，其包括权利要求1-14中任一项所述的功能基板。
PCT/CN2022/108091 2022-07-27 2022-07-27 功能基板及其制备方法、电子设备 WO2024020819A1 (zh)

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JPH0878525A (ja) * 1994-09-07 1996-03-22 Seiko Epson Corp 半導体装置及びその製造方法
JPH08186111A (ja) * 1994-12-28 1996-07-16 Sony Corp 接続孔の形成方法
CN1748299A (zh) * 2003-02-24 2006-03-15 浜松光子学株式会社 半导体装置及使用此半导体装置的放射线检测器
US20080054486A1 (en) * 2006-09-06 2008-03-06 Shinko Electric Industries Co., Ltd. Semiconductor device package, semiconductor apparatus, and methods for manufacturing the same
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JPH0878525A (ja) * 1994-09-07 1996-03-22 Seiko Epson Corp 半導体装置及びその製造方法
JPH08186111A (ja) * 1994-12-28 1996-07-16 Sony Corp 接続孔の形成方法
CN1748299A (zh) * 2003-02-24 2006-03-15 浜松光子学株式会社 半导体装置及使用此半导体装置的放射线检测器
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