WO2021253573A1 - 散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板 - Google Patents

散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板 Download PDF

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WO2021253573A1
WO2021253573A1 PCT/CN2020/104571 CN2020104571W WO2021253573A1 WO 2021253573 A1 WO2021253573 A1 WO 2021253573A1 CN 2020104571 W CN2020104571 W CN 2020104571W WO 2021253573 A1 WO2021253573 A1 WO 2021253573A1
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Prior art keywords
layer
shielding
metal
heat dissipation
dielectric layer
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PCT/CN2020/104571
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English (en)
French (fr)
Inventor
陈先明
谢炳森
黄本霞
冯磊
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珠海越亚半导体股份有限公司
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Priority to JP2021545754A priority Critical patent/JP7236549B2/ja
Priority to US17/428,822 priority patent/US20220310529A1/en
Priority to KR1020217024192A priority patent/KR102566363B1/ko
Publication of WO2021253573A1 publication Critical patent/WO2021253573A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • This application relates to the field of semiconductor packaging technology, and in particular to a heat dissipation and electromagnetic shielding embedded packaging structure, a manufacturing method thereof, and a substrate.
  • the volume of electronic products is becoming lighter and thinner, and the degree of integration is increasing.
  • Embedded packaging technology is becoming more and more popular.
  • the degree of integration increases, the computing power increases, and the requirements for heat dissipation and electromagnetic interference resistance of the package are increasing. high.
  • the heat dissipation on the market is mostly achieved by connecting copper pillars on one surface of the electronic component; and the anti-electromagnetic interference is mostly achieved by using a metal packaging shell on the outside of the substrate, and the existing packaging technology has the functions of heat dissipation and anti-electromagnetic interference It can't take into account the design.
  • the embodiments of the present application provide a heat dissipation and electromagnetic shielding embedded package structure, including:
  • the dielectric layer includes an upper surface and a lower surface, and at least one cavity unit is arranged inside the dielectric layer;
  • An electronic component one end is embedded in the insulating layer, and the other end is exposed in the cavity unit, and the electronic component includes a terminal;
  • the through hole penetrates the upper surface and the lower surface of the dielectric layer and communicates with the terminal;
  • a shielding layer is formed on the six surfaces of the dielectric layer to achieve the effect of omnidirectional electromagnetic radiation prevention; in the second aspect The through holes communicate with the terminals of the electronic components and lead to the circuit layers on the upper and lower surfaces to achieve efficient heat dissipation. It should be noted that the shielding layer on the opposite side of the terminals of the electronic components can not only achieve electromagnetic shielding function but also have a heat dissipation function.
  • the dielectric layer includes at least one layer, and a circuit layer is provided on the surface of each dielectric layer.
  • the shielding layer covering the exposed end of the electronic component and the shielding layer on the surface of the dielectric layer may also be connected through a through hole.
  • the metal layer includes a seed layer and a covering layer, and the seed layer is disposed at the bottom of the covering layer.
  • the insulating layer is a liquid photosensitive dielectric material, which can be cured at a high temperature.
  • embodiments of the present application provide a method for manufacturing a heat dissipation and electromagnetic shielding embedded package structure, including:
  • Disposing an insulating layer in the cavity unit attaching electronic components to the bottom of the insulating layer, curing and photoetching the insulating layer to expose the terminals of the electronic component, wherein the insulating layer is exposed at the upper end of the electronic component;
  • a first metal layer is formed on the upper surface and the lower surface of the first dielectric layer, and a first circuit layer and a first shielding layer are formed by photolithography of the first metal layer.
  • the first circuit layer and the terminal Communicate with the through hole; the first shielding layer communicates with the metal layer on the peripheral surface of the first dielectric layer.
  • the shielding layer is formed on the six surfaces of the dielectric layer to achieve the effect of omnidirectional electromagnetic radiation prevention.
  • efficient heat dissipation is achieved by connecting the terminals of the electronic component to the circuit layers on the upper and lower surfaces. It should be noted that the shielding layer located on the opposite side of the terminals of the electronic component can not only achieve the electromagnetic shielding function but also have the heat dissipation function.
  • disposing an insulating layer in the cavity unit, mounting electronic components to the bottom of the insulating layer, curing and photoetching the insulating layer to expose the terminals of the electronic components further includes:
  • the insulating layer is cured at a high temperature and photoetched to expose the terminals of the electronic component.
  • forming the first metal layer includes:
  • a covering layer is formed on the surface of the seed layer, and the covering layer is a metal material with a certain thickness.
  • it further includes:
  • the N+1th metal layer is lithographically formed to form an N+1th circuit layer and an N+1th shielding layer, the first circuit layer, ... the N+1th circuit layer is connected to the through hole, The first shielding layer, ... the N+1th shielding layer is connected to the metal layer on the peripheral surface of the dielectric layer, where N ⁇ 1.
  • the first shielding layer communicates with the N+1th shielding layer and the metal layer on the peripheral surface of the dielectric layer, wherein the first shielding layer is connected to the metal layer on the surrounding surface of the dielectric layer.
  • the connection mode of the N+1th shielding layer includes at least one of the following:
  • the N+1th dielectric layer corresponding to the upper surface of the cavity unit is completely etched away, and metal is filled so that the first shielding layer and the N+1th shielding layer are seamlessly connected through the metal;
  • the N+1th dielectric layer corresponding to the upper surface of the cavity unit is partially etched away to form a through hole window, and metal is filled to make the first shielding layer communicate with the N+1 shielding layer through the through hole.
  • an embodiment of the present application provides a substrate including the heat dissipation and electromagnetic shielding embedded package structure as described in the first aspect.
  • the substrate according to the embodiment of the third aspect of the present application has at least the following beneficial effects: on the first aspect, shielding layers are formed on the six surfaces of the substrate to achieve the effect of omnidirectional electromagnetic radiation prevention; on the second aspect, the through holes in the substrate and the electronic components The terminals are connected and lead out to the circuit layers on the upper and lower surfaces to achieve efficient heat dissipation. It should be noted that the shielding layer located on the opposite side of the electronic component terminals can not only achieve electromagnetic shielding function but also have a heat dissipation function.
  • FIG. 1 is a cross-sectional view of a heat dissipation and electromagnetic shielding embedded package structure provided by an embodiment of the present application;
  • FIG. 2 is a flow chart of steps of a method for manufacturing a heat dissipation and electromagnetic shielding embedded package structure provided by another embodiment of the present application;
  • FIG. 3 is a cross-sectional view corresponding to step S100 in a method for manufacturing a heat dissipation and electromagnetic shielding embedded package structure according to another embodiment of the present application;
  • FIGS. 4 to 5 are cross-sectional views corresponding to step S200 in a method for manufacturing a heat dissipation and electromagnetic shielding embedded package structure according to another embodiment of the present application;
  • FIGS. 6 to 7 are cross-sectional views corresponding to step S300 in a method for manufacturing a heat dissipation and electromagnetic shielding embedded package structure according to another embodiment of the present application;
  • FIGS. 8 to 9 are cross-sectional views corresponding to the intermediate state of the manufacturing method of the heat dissipation and electromagnetic shielding embedded package structure provided by another embodiment of the present application;
  • FIG. 10 is a cross-sectional view of a heat dissipation and electromagnetic shielding embedded package structure provided by another embodiment of the present application.
  • 11 to 12 are cross-sectional views corresponding to the intermediate state of the manufacturing method of the heat dissipation and electromagnetic shielding embedded package structure provided by another embodiment of the present application;
  • FIG. 13 is a cross-sectional view of a heat dissipation and electromagnetic shielding embedded package structure provided by another embodiment of the present application.
  • FIG. 14 is a cross-sectional view of a heat dissipation and electromagnetic shielding embedded package structure provided by another embodiment of the present application.
  • the present application provides a heat dissipation and electromagnetic shielding embedded packaging structure, including: a dielectric layer 100, including an upper surface and a lower surface, the dielectric layer 100 is provided with at least one cavity unit 130; an insulating layer 200 , Disposed in the cavity unit 130, the cavity unit 130 is partially filled by the insulating layer 200; the electronic component 300, one end is embedded in the insulating layer 200, and the other end is exposed to the cavity unit
  • the electronic component 300 includes a terminal 310; a through hole 400 that penetrates the upper and lower surfaces of the dielectric layer 100 and communicates with the terminal 310; and a metal layer 500 covers the dielectric layer 100
  • the six surfaces and the through holes 400 are respectively used to form a shielding layer 510 and a circuit layer 520.
  • the shielding layer 510 covers the exposed end of the electronic component 300.
  • the shielding layer 510 and the circuit layer 520 pass through the The dielectric layer 100 is blocked.
  • one or more cavity units 130 are provided inside the dielectric layer 100.
  • the cavity units 130 can be arranged in an array or a non-array arrangement, which can be arranged according to the number of electronic components 300 required.
  • the insulating layer 200 is filled.
  • the insulating layer 200 does not fill the cavity unit 130, and a certain space is reserved for placing the electronic component 300 and covering metal.
  • the electronic component 300 is divided according to whether there is a terminal 310
  • the front side has a terminal 310 placed at the bottom of the insulating layer 200 close to the lower surface of the cavity unit 130, and the reverse side is exposed on the insulating layer 200.
  • the metal layer 500 includes a shielding layer 510 and a circuit layer 520.
  • the shielding layer 510 covers the dielectric.
  • the circumference of the layer 100 and the upper and lower six surfaces, and also cover the upper part of the reverse side of the electronic component 300, the shielding layer 510 can achieve the effect of omnidirectional electromagnetic radiation prevention; in addition, a through hole 400 is provided inside the dielectric layer 100, The through hole 400 communicates with the connection terminal 310 of the electronic component 300 and extends to the circuit layer 520 on the upper and lower surfaces of the dielectric layer 100.
  • the heat dissipation method in which the circuit layers 520 on the upper surface and the lower surface are connected increases the heat dissipation area of the electronic component 300 and improves the heat dissipation efficiency, and the shield layer 510 covered on the reverse side of the electronic component 300 also has a heat dissipation function, which further improves the heat dissipation of the electronic component 300 Efficiency; the cavity unit 130 is pre-filled with the insulating layer 200 material again, and there is no need to go through the lamination and thinning process after the patch, which greatly shortens the production cycle and reduces the production cost, while reducing the amount of material used and reducing Pollution to the environment.
  • the electronic component 300 includes but is not limited to devices and chips. It can be an active device or a passive device. It can be an independent chip or device, or a combination of multiple chips or devices, classified by purpose. It can be a different power device, it can also be a radio frequency or logic chip. The type and number of chips or devices can be a combination of 3D back-to-back stacking multiple chips according to actual needs, or it can be a combination of up and down, left and right single-layer array designs.
  • the electronic component 300 can be installed in the cavity unit 130 from the front side, and conducts conduction and heat dissipation by communicating with the lower surface circuit layer 520. It can also be installed in the cavity unit 130 on the reverse side.
  • the circuit layer 520 is connected for conduction and heat dissipation, and the specific installation direction of the electronic component 310 can be set according to design requirements, which all fall within the protection scope of the present application.
  • the dielectric layer 100 includes at least one layer, and a circuit layer 520 is provided on the surface of each layer of the dielectric layer 100.
  • the dielectric layer 100 can be a single layer to realize the embedded packaging of the single-layer electronic component 300, or it can be multi-layered to realize the embedded packaging of the stacked electronic component 300, on the surface of each dielectric layer 100 A circuit layer 520 is provided, and the circuit layer 520 between the dielectric layers 100 is connected through the through hole 400, and finally a shielding layer 510 and a circuit layer 520 are formed on the upper or lower surface and surrounding surfaces of the outermost dielectric layer 100 , Realize the functions of shielding, heat dissipation and electrical interface extraction.
  • An embodiment of the present application provides a heat dissipation and electromagnetic shielding embedded packaging structure.
  • the shielding layer 510 covering the exposed end of the electronic component 300 and the shielding layer 510 on the surface of the dielectric layer 100 can also be connected through a through hole.
  • the shielding layer 510 covering the exposed end of the electronic component 300 and the shielding layer 510 on the surface of the dielectric layer 100 may be an integral metal layer 500, or may be in the middle of the metal layer 500
  • the dielectric layer 100 is spaced so that metal through holes 400 are formed between the originally connected metal layers 500 for communication, which can also achieve the functions of shielding and heat dissipation, and the filling method of the space dielectric layer 100 can also reduce the metal and electronic components 300. Surface stress damage caused by different thermal expansion coefficients.
  • the metal layer 500 includes a seed layer 530 and a cover layer 540.
  • the seed layer 530 is disposed on the cover layer. Bottom of layer 540.
  • the metal layer 500 is composed of a relatively thin seed layer 530 and a relatively thick cover layer 540.
  • the seed layer 530 is disposed at the bottom of the cover layer 540.
  • the seed layer 530 can provide good properties for the cover layer 540. Covering the foundation and improving the quality of the covering layer 540.
  • the seed layer 530 can be but not limited to metal materials such as titanium, copper, and titanium-tungsten alloy, and the covering layer 540 can be but not limited to metal copper.
  • the insulating layer 200 is a liquid photosensitive dielectric material that can be cured at a high temperature.
  • the insulating layer 200 is a liquid photosensitive dielectric material, which can be filled by dispensing, printing, etc.
  • the liquid photosensitive dielectric material has high temperature curing performance, and it is convenient to adjust the placement position of the electronic component 300 in the liquid state. As well as the exposure height, the electronic components 300 can be installed more accurately by adjusting and curing.
  • the insulating layer 200 can be made of, but not limited to, ink.
  • the cavity unit is pre-filled with liquid photosensitive dielectric material, without the need for mounting. The lamination and thinning process greatly shortens the production cycle and reduces the production cost, while reducing the amount of material used and reducing the pollution to the environment.
  • another embodiment of the present application also provides a flow chart of a method for manufacturing a heat dissipation and electromagnetic shielding embedded package structure.
  • the method includes but is not limited to the following steps:
  • the first dielectric layer 110 is used to make an organic frame.
  • the frame includes at least one through hole 400 and at least one cavity unit 130 inside.
  • the volume and quantity of the cavity unit 130 are based on the number of electronic components 300 that need to be embedded.
  • the size and design requirements are set, and the number and position of the through holes 400 can be set according to the position and heat dissipation of the electronic component.
  • an insulating layer 200 is provided in the cavity unit 130, the electronic component 300 is mounted to the bottom of the insulating layer 200, and the insulating layer 200 is cured and photoetched to expose the terminals 310 of the electronic component 300, wherein the upper end of the electronic component 300 is exposed.
  • the insulating layer 200 further refines the step S200, and the step S200 includes but is not limited to:
  • S220 fills a quantitative photosensitive liquid medium material into the cavity unit 130 to form the insulating layer 200;
  • S230 mount the electronic component 300 to the bottom of the insulating layer 200;
  • an adhesive tape 600 is laminated on the lower surface of the first dielectric layer 110 to seal the bottom of the cavity unit 130 and fill the insulating layer 200 composed of a liquid photosensitive dielectric material. Filling is beneficial to control the filling amount and filling height of the insulating layer 200 and facilitate the installation of electronic components 300. In addition, it does not require the lamination and thinning process after mounting the electronic components 300, which greatly shortens the production cycle and reduces the cost. Finally, the electronic components are mounted. The component 300 reaches the bottom of the insulating layer 200, wherein the terminal 310 of the electronic component 300 faces downward and is close to the lower surface of the first dielectric layer 110.
  • the top of the electronic component 300 is higher than the insulating layer 200 to facilitate subsequent connection with the metal layer 500 for heat dissipation and shielding.
  • the filled insulating layer 200 is pre-cured, the purpose is to solidify the liquid insulating layer 200 to facilitate the removal of the tape 600.
  • the pre-curing temperature will not cause damage to the tape 600.
  • the insulating layer 200 is It is cured at a high temperature, and further photolithography is performed on the surface of the cured insulating layer 200 to expose the terminals 310 of the power element.
  • the adhesive tape 600 plays a bearing role.
  • the adhesive tape 600 does not need to undergo high temperature curing treatment, which reduces the high performance requirements of the carrier tape 600 and reduces production costs.
  • the carrier tape 600 does not need to be subjected to high temperature treatment, the The carrier tape 600 is repeatedly used for many times. It is different from the direct contact between the electronic component 300 and the carrier tape 600 and cured at a high temperature. When the tape 600 is removed, a certain proportion of residual glue will be scrapped on the surface of the electronic component 300. This method is cured by high temperature. There is no need to directly contact the tape 600, which eliminates the risk of residual glue of the electronic component 300 and improves the product yield.
  • a first metal layer 501 is formed on the upper and lower surfaces of the first dielectric layer 110, and a first circuit layer 521 and a first shielding layer 511 are formed by photolithography on the first metal layer 501.
  • the circuit layer 521 communicates with the terminal 310 and the through hole 400, and the first shield layer 511 communicates with the metal layer 500 on the peripheral surface of the first dielectric layer 110.
  • forming the first metal layer 501 includes:
  • a seed layer 530 is formed on the upper surface of the first dielectric layer 110, and the seed layer 530 is made of metal and or metal alloy material;
  • a covering layer 540 is formed on the surface of the seed layer 530, and the covering layer 540 is a metal material with a certain thickness.
  • a thinner metal seed layer 530 is formed on the entire upper and lower surfaces of the first dielectric layer 110 on the basis of step S200 by electroless copper plating or sputtering.
  • the 530 metal is titanium, copper, titanium-tungsten alloy, but not limited to the above metals.
  • the metal seed layer 530 is further electroplated with a metal covering layer 540. Considering the good electrical and thermal conductivity of the metal, copper metal is selected for electroplating, and the hole-filled electroplating process is used
  • the cavity unit 130 and all the metal seed layers 530 are formed with a certain thickness of copper metal.
  • the purpose is to coat the back surface of the electronic component 300 and the side wall above the insulating layer 200 with metal, and to connect the electronic component 300 with the surrounding surface
  • the metal layer 500 is connected to better conduct heat to the outer surface of the package body and effectively reduce the operating temperature of the device.
  • the seed layer 530 can provide a good coverage foundation for the cover layer 540 and improve the quality of the cover layer 540. Therefore, in an embodiment of the present application, preferably, the seed layer 530 has a thickness of 1000 nanometers.
  • the thickness of the cover layer 540 is 8000 nanometers, the thickness of the seed layer 530 and the cover layer 540 are relatively designed, and the designed specific thickness parameter values only need to meet the actual process and design requirements, and they all fall within the protection scope of the present application.
  • the first metal layer 501 is lithographically formed to form a first circuit layer 521 and a first shielding layer 511, a photoresist or photosensitive dry film is attached to the surface of the first metal layer 501, and the photoresist or The photosensitive dry film is exposed and developed to form the circuit pattern, and the cover layer 540 and the seed layer 530 of the corresponding part of the pattern are removed by etching to form the first circuit layer 521 and the first shielding layer 511, the first circuit layer and the electronic component terminal 310 is connected and located on the two end surfaces of the first dielectric layer 110, which can realize the external lead out of the electrical pins of the electronic component 300, which is convenient for the subsequent electrical connection or testing of the electronic component 300.
  • the first shielding layer 511 is connected to the first dielectric layer 511.
  • the metal layer 500 on the surrounding surface of a dielectric layer is directly connected to prevent electromagnetic interference and heat dissipation. Finally, the photoresist or photosensitive dry film is removed by means of film stripping.
  • a method for manufacturing a heat dissipation and electromagnetic shielding embedded package structure provided by another embodiment of the present application may further include the following steps:
  • a second dielectric layer 120 is formed on the surface of the first metal layer 501, and a second metal layer 502 is formed by photolithographic coating on the second dielectric layer 120.
  • the second dielectric layer is based on step S300.
  • 120 includes upper and lower parts. On the outer surfaces of the upper and lower parts of the second dielectric layer 120, photoresist or photosensitive dry film is attached, and the photoresist or photosensitive dry film is lithographically formed to form metal through holes 400, and then electroplated to form metal pillars.
  • a second metal layer 502 is formed on the periphery and upper and lower surfaces of the second dielectric layer 120 by chemical plating or physical sputtering.
  • the second metal layer 502 includes a metal seed layer 530 and a cover layer 540, and further passes The second metal layer 502 is lithographically formed by pattern plating or negative etching to form a second circuit layer 522 and a second shielding layer 512, the first circuit layer 521 and the second circuit layer 522 and the through hole 400 is connected, the first shielding layer 511, the second shielding layer 512 and the metal on the peripheral surface of the first dielectric layer 110 are connected, as shown in FIG.
  • the solder mask material is a non-conductive dielectric material, and a specific solder mask window 700 is opened in the solder mask material through exposure and development.
  • the circuit layer 520 is connected to the electronic component 300, and the circuit layer 520 is isolated from the shielding layer 510 through the solder mask opening 700, which can realize the electrical isolation between the electrical pins of the internal electronic device and the surrounding surface shielding layer, thereby performing the internal Layout and testing of electronic devices.
  • a multilayer package structure may also be provided, that is, an N+1th dielectric layer 100 is formed on the surface of the Nth metal layer 500, and the N+1th The dielectric layer 100 is lithographically coated to form the N+1th metal layer 500;
  • the N+1th metal layer 500 is lithographically formed to form an N+1th circuit layer 520 and an N+1th shielding layer 510.
  • the first circuit layer 521, ... the N+1th circuit layer 520 and the The through hole 400 is in communication, the first shielding layer 511,...
  • the N+1th shielding layer 510 is in communication with the metal on the peripheral surface of the second dielectric layer 110, where N ⁇ 1.
  • the number of layers of the heat dissipation and electromagnetic shielding embedded packaging structure of the present application can be set to multiple layers as required by the number of layout and wiring layers.
  • the inner circuit layers 520 are finally connected to the surface of the outer dielectric layer 100 through the inner through holes 400.
  • the shielding layer 510 communicates with the inner through hole 400 through the metal layer 500 on the peripheral surface of each dielectric layer 100.
  • FIG. 8-13 another embodiment of the present application provides a method for manufacturing a heat dissipation and electromagnetic shielding embedded package structure.
  • the second medium 120 corresponding to the upper surface of the cavity unit 130 is completely etched away, so that the first shielding layer 511 and the second shielding layer 512 are seamlessly connected, as shown in the diagram of FIG. 8 described in the above embodiment 10 shown.
  • the communication between the first shielding layer 511 and the second shielding layer 512 may also be: partially etch away the second dielectric layer 120 corresponding to the upper surface of the cavity unit 130, so that The first shielding layer 511 and the second shielding layer 512 are filled with the second medium 120.
  • photoresist or photosensitive dry film is attached to the upper and lower surfaces of the second medium layer 120 based on step S300, Photolithography is performed on the photoresist or photosensitive dry film to form the metal through hole 400.
  • the metal through hole 400 includes both the metal through hole 400 connected to the circuit layer 520 and the metal on the metal layer 500 on the upper surface of the cavity unit 130.
  • the through hole 400 is then electroplated to form a metal pillar and a surrounding surface metal layer 500, and the material of the second dielectric layer 120 is pressed together, and the material of the second dielectric layer 120 is thinned by a process such as plasma etching or polishing, exposing the upper surface of the metal through hole 400 or The lower surface and the upper and lower surfaces of the second dielectric layer 120, as shown in FIG. 12, a second metal layer 502 is formed on the material surface of the second dielectric layer 120 by chemical plating or physical sputtering, including a metal seed layer 530 and the cover layer 540, and further form the second circuit layer 522 and the second shielding layer 512 by pattern plating or negative etching.
  • a process such as plasma etching or polishing
  • the second shielding layer 512 on the upper surface of the cavity unit 130 is filled with metal.
  • the hole 400 is connected to the first shielding layer 511 in the vertical direction, and the connection relationship between the metal through hole 400 and the dielectric spacing is helpful for the uniform diffusion of the surface stress of the electronic component 300, and the overall stress effect of the package structure is improved.
  • the solder resist material is coated or pressed on both sides of the outer layer.
  • the solder resist material is a non-conductive dielectric material, and a specific solder resist window 700 is opened on the solder resist material through exposure and development.
  • the circuit layer 520 is connected to the electronic component 300, and the circuit layer 520 is isolated from the shielding layer 510 through the solder mask opening 700, which can realize the electrical isolation between the electrical pins of the internal electronic device and the surrounding surface shielding layer, thereby performing the internal Layout and testing of electronic devices.
  • Another embodiment of the present application also provides a substrate, which includes the embedded package structure with electromagnetic shielding as in any of the above embodiments.

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Abstract

本申请公开了一种散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板，该散热兼电磁屏蔽嵌埋封装结构包括：介质层，包括上表面和下表面，介质层内部设置有至少一个空腔单元；绝缘层，设置于空腔单元中，空腔单元被绝缘层部分填充；电子元件，一端嵌埋于绝缘层中，另一端外露于空腔单元中，电子元件包括端子；通孔，贯穿于介质层的上表面和下表面，并与端子连通；金属层，覆盖在介质层的六个表面和通孔内，分别用于形成屏蔽层和线路层，屏蔽层覆盖电子元件外露一端，屏蔽层与线路层通过介质层阻隔。本申请的散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板能够同时实现较好的电磁辐射屏蔽和散热功能。

Description

散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板 技术领域
本申请涉及半导体封装技术领域，尤其涉及一种散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板。
技术背景
电子产品体积日趋轻薄，集成度日益提高，埋入式封装技术越来越受到青睐，但随着集成化程度增加，运算能力的提高，对封装体的散热性，抗电磁干扰性要求越来越高。
目前，市面上散热性多采用在电子元件一个表面通过连接铜柱实现；而抗电磁干扰多通过在基板的外部利用金属封装外壳实现，并且现有的封装技术而言散热和抗电磁干扰的功能并不能兼顾设计。
申请内容
本申请旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本申请提出一种散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板，以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。所述技术方案如下：
第一方面，本申请实施例提供了一种散热兼电磁屏蔽嵌埋封装结构，包括：
介质层，包括上表面和下表面，所述介质层内部设置有至少一个空腔单元；
绝缘层，设置于所述空腔单元中，所述空腔单元被所述绝缘层部分填充；
电子元件，一端嵌埋于所述绝缘层中，另一端外露于所述空腔单元中，所述电子元件包括端子；
通孔，贯穿于所述介质层的上表面和下表面，并与所述端子连通；
金属层，覆盖在所述介质层的六个表面和所述通孔中分别用于形成屏蔽层和线路层，所述屏蔽层覆盖所述电子元件外露一端，所述屏蔽层与所述线路层通过所述介质层阻隔。
根据本申请第一方面实施例的散热兼电磁屏蔽嵌埋封装结构，至少具有以下有益效果：第一方面通过在介质层的六个表面形成屏蔽层达到全方位防电磁辐射的效果，第二方面通过通孔与电子元件的端子连通并引出至上下表面的线路层中实现高效散热，需要说明的是，位于电子元件端子反面的屏蔽层不仅可以实现电磁屏蔽功能同时具有散热功能。
可选地，在本申请的一个实施例中，所述介质层至少包括一层，每一层所述介质层表面均设置有线路层。
可选地，在本申请的一个实施例中，覆盖所述电子元件外露一端的屏蔽层与所述介质层表面的屏蔽层还可以通过通孔连通。
可选地，在本申请的一个实施例中，所述金属层包括种子层和覆盖层，所述种子层设置在所述覆盖层底部。
可选地，在本申请的一个实施例中，所述绝缘层为液态感光型介质材料，通过高温可固化。
第二方面，本申请实施例提供一种散热兼电磁屏蔽嵌埋封装结构的制作方法，包括：
提供具有通孔和空腔单元的第一介质层，所述第一介质层的四周表面和所述通孔内覆盖有金属层；
在空腔单元内设置绝缘层，贴装电子元件至所述绝缘层底部，固化并光刻所述绝缘层露出电子元件端子，其中所述电子元件上端露出所述绝缘层；
在所述第一介质层的上表面和下表面形成第一金属层，并对所述第一金属层光刻形成第一线路层和第一屏蔽层，所述第一线路层与所述端子和所述通孔连通；所述第一屏蔽层与所述第一介质层的四周表面的金属层连通。
根据本申请第二方面实施例的散热兼电磁屏蔽嵌埋封装结构的制作方法，至少具有以下有益效果：第一方面通过在介质层的六个表面形成屏蔽层达到全方位防电磁辐射的效果，第二方面通过将电子元件的端子连接至上下表面的线路层中实现高效散热，需要说明的是，位于电子元件端子反面的屏蔽层不仅可以实现电磁屏蔽功能同时具有散热功能。
可选地，在本申请的一个实施例中，在空腔单元内设置绝缘层，贴装电子元件至所述绝缘层底部，固化并光刻所述绝缘层露出电子元件端子还包括：
在所述第一介质层下表面层压胶带；
填充定量感光性液态介质材料至空腔单元形成绝缘层；
贴装电子元件至所述绝缘层底部；
预固化所述绝缘层；
移出所述胶带；
高温固化并光刻所述绝缘层露出电子元件端子。
可选地，在本申请的一个实施例中，形成所述第一金属层包括：
在所述第一介质层上表面形成种子层，所述种子层为金属和或金属合金材料；
在所述种子层表面形成覆盖层，所述覆盖层为具有一定厚度的金属材料。
可选地，在本申请的一个实施例中，还包括：
在所述第N金属层表面形成第N+1介质层，并对所述第N+1介质层光刻镀膜形成第N+1金属层；
对所述第N+1金属层光刻形成第N+1线路层和第N+1屏蔽层，所述第一线路层、……所述第N+1线路层与所述通孔连通，所述第一屏蔽层、……所述第N+1屏蔽层与所述介质层的四周表面的金属层连通，其中N≥1。
可选地，在本申请的一个实施例中，所述第一屏蔽层与所述第N+1屏蔽层与所述介质层的四周表面的金属层连通，其中所述第一屏蔽层与所述第N+1屏蔽层连通方式包括以下至少之一：
完全刻蚀掉位于所述空腔单元上表面对应的第N+1介质层，填充金属使得所述第一屏蔽层与所述第N+1屏蔽层通过金属无缝连接；
部分刻蚀掉位于所述空腔单元上表面对应的第N+1介质层形成通孔窗口，填充金属使得所述第一屏蔽层与所述N+1屏蔽层通过通孔连通。
第三方面，本申请实施例提供一种基板，包括如上第一方面所述的散热兼电磁屏蔽嵌埋封装结构。
根据本申请第三方面实施例的基板，至少具有以下有益效果：第一方面通过在基板的六个表面形成屏蔽层达到全方位防电磁辐射的效果，第二方面通过基板内部通孔与电子元件的端子连通并引出至上下表面的线路层中实现高效散热，需要说明的是，位于电子元件端子反面的屏蔽层不仅可以实现电磁屏蔽功能同时具有散热功能。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本申请而了解。本申请的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1是本申请一个实施例提供的散热兼电磁屏蔽嵌埋封装结构的截面图；
图2是本申请另一个实施例提供的散热兼电磁屏蔽嵌埋封装结构的制作方法的步骤流程图；
图3是本申请另一个实施例提供的散热兼电磁屏蔽嵌埋封装结构的制作方法中步骤S100对应的截面图；
图4至图5是本申请另一个实施例提供的散热兼电磁屏蔽嵌埋封装结构的制作方法中步骤S200对应的截面图；
图6至图7是本申请另一个实施例提供的散热兼电磁屏蔽嵌埋封装结构的制作方法中步骤S300对应的截面图；
图8至图9是本申请另一个实施例提供的散热兼电磁屏蔽嵌埋封装结构的制作方法中间状态对应的截面图；
图10是本申请另一个实施例提供的散热兼电磁屏蔽嵌埋封装结构的截面图；
图11至图12是本申请另一个实施例提供的散热兼电磁屏蔽嵌埋封装结构的制作方法中间状态对应的截面图；
图13是本申请另一个实施例提供的散热兼电磁屏蔽嵌埋封装结构的截面图；
图14是本申请另一个实施例提供的散热兼电磁屏蔽嵌埋封装结构的截面图。
介质层100、第一介质层110、第二介质层120、空腔单元130、绝缘层200、电子元件300、端子310、通孔400、金属层500、第一金属层501、第二金属层502、屏蔽层510、第一屏蔽层511、第二屏蔽层512、线路层520、第一线路层521、第二线路层522、种子层530、覆盖层540、胶带600、阻焊开窗700
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本申请所能产生的功效及所能达成的目的下，均应仍落在本申请所揭示的技术内容得能涵盖的范围内。
本部分将详细描述本申请的具体实施例，本申请之较佳实施例在附图中示出，附图的作用在于用图形补充说明书文字部分的描述，使人能够直观地、形象地理解本申请的每个技术特征和整体技术方案，但其不能理解为对本申请保护范围的限制。
在申请的描述中，若干的含义是一个或者多个，多个的含义是两个及两个以上，大于、小于、超过等理解为不包括本数，以上、以下、以内等理解为包括本数。如果有描述到第一、第二只是用于区分技术特征为目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量或者隐含指明所指示的技术特征的先后关系。
参照图1，本申请提供了一种散热兼电磁屏蔽嵌埋封装结构，包括：介质层100，包括上表面和下表面，所述介质层100内部设置有至少一个空腔单元130；绝缘层200，设置于 所述空腔单元130中，所述空腔单元130被所述绝缘层200部分填充；电子元件300，一端嵌埋于所述绝缘层200中，另一端外露于所述空腔单元130中，所述电子元件300包括端子310；通孔400，贯穿于所述介质层100的上表面和下表面，并与所述端子310连通；金属层500，覆盖在所述介质层100的六个表面和所述通孔400中分别用于形成屏蔽层510和线路层520，所述屏蔽层510覆盖所述电子元件300外露一端，所述屏蔽层510与所述线路层520通过所述介质层100阻隔。
在一实施例中，介质层100内部设置有一个或多个空腔单元130，空腔单元130可以是阵列排布也可以是非阵列排布，根据所需电子元件300的数量要求进行设置，空腔单元130形成后进行绝缘层200填充，绝缘层200并未填满空腔单元130，而预留有一定空间用于放置电子元件300和覆盖金属，电子元件300按照是否有接线端子310分为正面和反面，正面具有接线端子310置于绝缘层200底部接近空腔单元130下表面，反面外露于绝缘层200之上，金属层500包括屏蔽层510和线路层520，屏蔽层510覆盖在介质层100的四周以及上下六个表面，并且还覆盖在电子元件300反面的上部，通过屏蔽层510的设置可以达到全方位防电磁辐射的效果；另外在介质层100的内部设置有通孔400，通孔400与电子元件300的接线端子310连通，并延伸至介质层100的上表面和下表面的的线路层520，相对于电子元件300单面散热的技术，通过通孔400和介质层100上表面和下表面的线路层520连通的散热方式增加了电子元件300的散热面积，提高散热效率，并且电子元件300反面覆盖的屏蔽层510同样具有散热功能，更进一步提高了电子元件300的散热效率；再次利用绝缘层200材料进行空腔单元130预填充，不需要经过贴片后的层压再减薄工艺，大大缩短了生产周期，降低了生产成本，同时降低了材料的使用量，减少了对环境的污染。
需要说明的是，电子元件300包括但不限于器件、芯片，可以是有源器件也可以是无源器件，可以是独立的芯片或器件，也可以是多颗芯片或者器件的组合，按用途分类可以是不同的功率器件，还可以是射频或逻辑芯片，芯片或器件的种类和数量可根据实际需求按照3D背靠背堆叠多颗芯片的组合，也可以是上下左右单层阵列组合设计。电子元件300可以正面向下安装于空腔单元130中，通过与下表面线路层520连通进行导电和散热，还可以反面安装于空腔单元中130，此时，端子310向上可与上表面设置的线路层520连通进行导电和散热，电子元件310具体的安装方向可依据设计需求进行设置，均属于本申请的保护范围。
参照图14，本申请的一个实施例提供了一种散热兼电磁屏蔽嵌埋封装结构，所述介质层100至少包括一层，每一层所述介质层100表面均设置有线路层520。
在一实施例中，介质层100可以是单层，实现单层电子元件300的嵌埋封装，也可以是多层，实现叠层电子元件300的嵌埋封装，在每一层介质层100表面均设置有线路层520， 各层介质层100之间的线路层520通过通孔400连通，并最终在最外层介质层100的上表面或者下表面以及四周表面形成屏蔽层510及线路层520，实现屏蔽、散热和电性接口引出功能。
本申请的一个实施例提供了一种散热兼电磁屏蔽嵌埋封装结构，覆盖所述电子元件300外露一端的屏蔽层510与所述介质层100表面的屏蔽层510还可以通过通孔连通。
参照图10和图13，在一实施例中，覆盖所述电子元件300外露一端的屏蔽层510与介质层100表面的屏蔽层510可以是一块整体的金属层500，也可以在金属层500中间间隔填充介质层100，使得原本连接在一起的金属层500中间形成金属通孔400进行连通，同样可以达到屏蔽和散热的功能，并且通过间隔介质层100填充的方式还可以降低金属与电子元件300表面因热膨胀系数不同而造成的应力损伤。
参照图6至图13，本申请的一个实施例提供了一种散热兼电磁屏蔽嵌埋封装结构，所述金属层500包括种子层530和覆盖层540，所述种子层530设置在所述覆盖层540底部。
在一实施例中，金属层500由相对厚度较薄的种子层530和相对厚度较厚的覆盖层540组成，种子层530设置在覆盖层540底部，种子层530可以为覆盖层540提供良好的覆盖基础，提高覆盖层540的质量，种子层530可以是但不限于钛、铜、钛钨合金等金属材料，覆盖层540可以但不限于是金属铜。
参照图1，本申请的一个实施例提供了一种散热兼电磁屏蔽嵌埋封装结构，所述绝缘层200为液态感光型介质材料，通过高温可固化。
在一实施例中，绝缘层200为液态感光型介质材料，可以通过点胶，印刷等方式进行填充，液态感光型介质材料具有高温固化的性能，液态状态时方便调整电子元件300的贴装位置以及露出高度，调整好进行固化可以将电子元件300安装的更加精准，绝缘层200材料可以但不限于是油墨，另外，利用液态感光型介质材料进行空腔单元预填充，不需要经过贴片后的层压再减薄工艺，大大缩短了生产周期，降低了生产成本，同时降低了材料的使用量，减少了对环境的污染。
基于上述散热兼电磁屏蔽嵌埋封装结构，提出本申请的散热兼电磁屏蔽嵌埋封装结构的制作方法的各个实施例。
参照图2，本申请的另一个实施例还提供了一种散热兼电磁屏蔽嵌埋封装结构的制作方法的流程图，该方法包括但不限于以下步骤：
S100，提供具有通孔400和空腔单元130的第一介质层110，所述第一介质层110的四周表面和所述通孔400内覆盖有金属层500；
如图3所示，利用第一介质层110制作有机框架，框架包括内部至少一个贯穿通孔400和至少一个空腔单元130，空腔单元130的体积和数量根据需要埋入的电子元件300的大小和设计需求设置，通孔400的数量和位置可以根据电子元件的位置和散热量进行设置。
S200在空腔单元130内设置绝缘层200，贴装电子元件300至所述绝缘层200底部，固化并光刻所述绝缘层200露出电子元件300端子310，其中所述电子元件300上端露出所述绝缘层200，对步骤S200进一步细化，该步骤S200包括但不限于：
S210在所述第一介质层110下表面层压胶带600；
S220填充定量感光性液态介质材料至空腔单元130形成绝缘层200；
S230贴装电子元件300至所述绝缘层200底部；
S240预固化所述绝缘层200；
S250移出所述胶带600；
S260高温固化并光刻所述绝缘层200露出电子元件300端子310。
如图4和图5所示，在图4中，在第一介质层110下表面层压胶带600，使空腔单元130底部密封，填充由液态感光性介质材料组成的绝缘层200，液态材料填充利于控制绝缘层200的填充量和填充高度，方便电子元件300安装，另外不需要经过贴装电子元件300后的层压再减薄工艺，大大缩短了生产周期降低了成本，最后贴装电子元件300至绝缘层200底部，其中电子元件300的端子310面朝下，接近第一介质层110下表面，电子元件300顶部高于绝缘层200方便后续与金属层500连接进行散热和屏蔽。在图5中，对填充好的绝缘层200进行预固化，目的是使液态绝缘层200凝固，方便移出胶带600，预固化温度不会造成胶带600的损伤，移出胶带600后对绝缘层200进行高温固化，进一步在固化后的绝缘层200表面进行光刻露出电源元件的端子310。
需要说明的是，胶带600起承载作用，胶带600不需经过高温固化处理，降低了对承载胶带600的高性能要求，降低生产成本，且因不需要对承载胶带600进行高温处理，可实现对承载胶带600多次重复利用，区别于以往电子元件300与承载胶带600直接接触并高温固化，在去除胶带600时往往会在电子元件300表面产生一定比例的残胶报废，此方法因高温固化时不需与胶带600直接接触，消除了电子元件300残胶的风险，提升了产品良率。
S300在所述第一介质层110的上表面和下表面形成第一金属层501，并对所述第一金属层501光刻形成第一线路层521和第一屏蔽层511，所述第一线路层521与所述端子310和所述通孔400连通，所述第一屏蔽层511与所述第一介质层110的四周表面的金属层500连通。
如图6所示，在一实施例中，形成所述第一金属层501包括：
在所述第一介质层110上表面形成种子层530，所述种子层530为金属和或金属合金材料；
在所述种子层530表面形成覆盖层540，所述覆盖层540为具有一定厚度的金属材料。
如图6所示，通过化学镀铜或溅射的方式在步骤S200的基础上在第一介质层110的上表面和下表面整面形成一层较薄的金属种子层530，常用的种子层530金属是钛、铜、钛钨合金，但不仅限于上述金属，进一步在金属种子层530上电镀金属覆盖层540，考虑金属的良好的导电导热性，选用铜金属进行电镀，通过填孔电镀工艺将空腔单元130以及所有金属种子层530上形成一定厚度的铜金属，目的是为了让电子元件300的背面以及绝缘层200上方侧壁部分都包覆金属，并将电子元件300与四周表面的金属层500相连，能更好的将热量传导至封装体的外表面，有效降低器件的工作温度。
在本申请的一些实施例中，种子层530可以为覆盖层540提供良好的覆盖基础，提高覆盖层540的质量，因此在本申请的一个实施例中，优选的，种子层530厚度为1000纳米，覆盖层540厚度为8000纳米，种子层530和盖层540的厚度是相对设计，设计的具体厚度参数值满足实际工艺和设计需求即可，都属于本申请的保护范围。
如图7所示，对第一金属层501光刻形成第一线路层521和第一屏蔽层511，在第一金属层501表面贴附光刻胶或者感光干膜，通过对光刻胶或者感光干膜曝光、显影的方式形成线路图案，通过蚀刻的方式去除图案对应部分的覆盖层540和种子层530，形成第一线路层521和第一屏蔽层511，第一线路层与电子元件端子310相连通并且位于第一介质层110的两端表面，可以实现电子元件300电气引脚的外部引出，方便后续进一步对电子元件300的电气电通或者测试，而第一屏蔽层511则与第一介质层四周表面的金属层500直接连通，实现防止电磁干扰和散热的作用。最后通过退膜的方式将光刻胶或感光干膜去除。
参照图8至图10，本申请的另一个实施例提供的一种散热兼电磁屏蔽嵌埋封装结构的制作方法的还可以包括以下步骤：
在所述第一金属层501表面形成第二介质层120，并对所述第二介质层120光刻镀膜形成第二金属层502，在图8中，在步骤S300基础上的第二介质层120包括上下两部分，在上下两部分第二介质层120的外侧表面贴附光刻胶或者感光干膜，对光刻胶或者感光干膜进行光刻形成金属通孔400，再电镀形成金属柱和四周表面金属层500，先压合第二介质层120材料，使连接更稳固，再利用等离子蚀刻或抛光等工艺减薄第二介质层120材料，露出金属柱上下表面和介质材料上下表，在图9中，通过化学电镀或者物理溅射的方式在第二介质层120材料四周和上下表面上形成第二金属层502，第二金属层502包括金属种子层530和覆盖层540，进一步通过图形电镀或负片蚀刻的方式对所述第二金属层502光刻形成第二线路 层522和第二屏蔽层512，所述第一线路层521与所述第二线路层522与所述通孔400连通，所述第一屏蔽层511、所述第二屏蔽层512与所述第一介质层110的四周表面的金属连通，如图10所示，在外层两面涂覆或压合阻焊材料，阻焊材料为不导电的介质材料，通过曝光和显影在阻焊材料开出特定的阻焊开窗700。线路层520与电子元件300连通，通过阻焊开窗700将线路层520和屏蔽层510隔离，可以实现内部电子器件的电性引脚与四周表面屏蔽层之间的电性隔离，从而进行内部电子器件的布局和测试。
参照图14，在本申请的一个实施例中，还可以设置成多层封装结构，即，在所述第N金属层500表面形成第N+1介质层100，并对所述第N+1介质层100光刻镀膜形成第N+1金属层500；
对所述第N+1金属层500光刻形成第N+1线路层520和第N+1屏蔽层510，所述第一线路层521、……所述第N+1线路层520与所述通孔400连通，所述第一屏蔽层511、……所述第N+1屏蔽层510与所述第介质层110的四周表面的金属连通，其中N≥1。本申请的散热兼电磁屏蔽嵌埋封装结构层数可以布板布线层数的需求设置多层，其中内部线路层520之间通过内部通孔400最终连通至外外一层介质层100的表面，屏蔽层510通过各个介质层100四周表面的金属层500和内部通孔400进行连通。
参考图8至图13，本申请的另一个实施例提供的一种散热兼电磁屏蔽嵌埋封装结构的制作方法，所述第一屏蔽层511、所述第二屏蔽层512与所述第一介质层110的四周表面的金属连通，其中所述第一屏蔽层511与所述第二屏蔽层512连通方式包括以下至少之一：
完全刻蚀掉位于所述空腔单元130上表面对应的第二介质120，使得所述第一屏蔽层511与所述第二屏蔽层512无缝连接，如上述实施例描述的图8之图10所示。
在一实施例中，所述第一屏蔽层511与所述第二屏蔽层512连通方式还可以是：部分刻蚀掉位于所述空腔单元130上表面对应的第二介质层120，使得所述第一屏蔽层511与所述第二屏蔽层512填充第二介质120，如图11所示，在步骤S300基础上的第二介质层120的上下表面贴附光刻胶或者感光干膜，对光刻胶或者感光干膜进行光刻形成金属通孔400，所述金属通孔400既包括与线路层520连接的金属通孔400，也包括位于空腔单元130上表面金属层500的金属通孔400，再电镀形成金属柱和四周表面金属层500，压合第二介质层120材料，利用等离子蚀刻或抛光等工艺减薄第二介质层120材料，露出金属通孔400的上表面或者下表面以及第二介质层120的上表面和下表面，如图12所示，通过化学电镀或者物理溅射的方式在第二介质层120材料表面上形成第二金属层502，包括金属种子层530和覆盖层540，进一步通过图形电镀或负片蚀刻的方式形成第二线路层522和第二屏蔽层512，需要说明的是，位于空腔单元130上表面的第二屏蔽层512通过金属填充通孔400的方式与垂 直方向的第一屏蔽层511相通，通过金属通孔400与介质间隔设置的连通关系有助于电子元件300表面应力的均匀扩散，提高封装结构的整体应力效果，在图13所示，在外层两面涂覆或压合阻焊材料，阻焊材料为不导电的介质材料，通过曝光和显影在阻焊材料开出特定的阻焊开窗700。线路层520与电子元件300连通，通过阻焊开窗700将线路层520和屏蔽层510隔离，可以实现内部电子器件的电性引脚与四周表面屏蔽层之间的电性隔离，从而进行内部电子器件的布局和测试。
本申请的另一个实施例还提供了一种基板，该基板包括有如上任一实施例中的兼电磁屏蔽嵌埋封装结构。
以上是对本申请的较佳实施进行了具体说明，但本申请并不局限于上述实施方式，熟悉本领域的技术人员在不违背本申请精神的前提下还可作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请权利要求所限定的范围内。

Claims (11)

  1. 一种散热兼电磁屏蔽嵌埋封装结构，其特征在于，包括：
    介质层，包括上表面和下表面，所述介质层内部设置有至少一个空腔单元；
    绝缘层，设置于所述空腔单元中，所述空腔单元被所述绝缘层部分填充；
    电子元件，一端嵌埋于所述绝缘层中，另一端外露于所述空腔单元中，所述电子元件包括端子；
    通孔，贯穿于所述介质层的上表面和下表面，并与所述端子连通；
    金属层，覆盖在所述介质层的六个表面和所述通孔内，分别用于形成屏蔽层和线路层，所述屏蔽层覆盖所述电子元件外露一端，所述屏蔽层与所述线路层通过所述介质层阻隔。
  2. 根据权利要求1所述的散热兼电磁屏蔽嵌埋封装结构，其特征在于，所述介质层至少包括一层，每一层所述介质层表面均设置有线路层。
  3. 根据权利要求1所述的散热兼电磁屏蔽嵌埋封装结构，其特征在于：覆盖所述电子元件外露一端的屏蔽层与所述介质层表面的屏蔽层还可以通过通孔连通。
  4. 根据权利要求1所述的散热兼电磁屏蔽嵌埋封装结构，其特征在于：所述金属层包括种子层和覆盖层，所述种子层设置在所述覆盖层底部。
  5. 根据权利要求1所述的散热兼电磁屏蔽嵌埋封装结构，其特征在于：所述绝缘层为液态感光型介质材料，通过高温可固化。
  6. 一种散热兼电磁屏蔽嵌埋封装结构的制作方法，其特征在于，包括以下步骤：
    提供具有通孔和空腔单元的第一介质层，所述第一介质层的四周表面和所述通孔内覆盖有金属层；
    在空腔单元内设置绝缘层，贴装电子元件至所述绝缘层底部，固化并光刻所述绝缘层露出电子元件的端子，其中所述电子元件上端露出所述绝缘层；
    在所述第一介质层的上表面和下表面形成第一金属层，并对所述第一金属层光刻形成第一线路层和第一屏蔽层，所述第一线路层与所述端子和所述通孔连通；所述第一屏蔽层与所述第一介质层的四周表面的金属层连通。
  7. 根据权利要求6所述的散热兼电磁屏蔽嵌埋封装结构的制作方法，其特征在于，在空腔单元内设置绝缘层，贴装电子元件至所述绝缘层底部，固化并光刻所述绝缘层露出电子元件的端子包括：
    在所述第一介质层下表面层压胶带；
    填充定量感光性液态介质材料至空腔单元形成绝缘层；
    贴装电子元件至所述绝缘层底部；
    预固化所述绝缘层；
    移出所述胶带；
    高温固化并光刻所述绝缘层露出电子元件的端子。
  8. 根据权利要求6所述的散热兼电磁屏蔽嵌埋封装结构的制作方法，其特征在于，形成所述第一金属层包括：
    在所述第一介质层上表面形成种子层，所述种子层为金属和或金属合金材料；
    在所述种子层表面形成覆盖层，所述覆盖层为具有一定厚度的金属材料。
  9. 根据权利要求6至8任一所述的散热兼电磁屏蔽嵌埋封装结构的制作方法，其特征在于，还包括：
    在所述第N金属层表面形成第N+1介质层，并对所述第N+1介质层光刻镀膜形成第N+1金属层；
    对所述第N+1金属层光刻形成第N+1线路层和第N+1屏蔽层，所述第一线路层、……所述第N+1线路层(520)与所述通孔连通，所述第一屏蔽层、……所述第N+1屏蔽层与所述介质层的四周表面的金属层连通，其中N≥1。
  10. 根据权利要求9所述的散热兼电磁屏蔽嵌埋封装结构的制作方法，其特征在于，所述第一屏蔽层与所述第N+1屏蔽层与所述介质层的四周表面的金属层连通，其中所述第一屏蔽层与所述第N+1屏蔽层连通方式包括以下至少之一：
    完全刻蚀掉位于所述空腔单元上表面对应的第N+1介质层，填充金属使得所述第一屏蔽层与所述第N+1屏蔽层通过金属无缝连接；
    部分刻蚀掉位于所述空腔单元上表面对应的第N+1介质层形成通孔窗口，填充金属使得所述第一屏蔽层与所述N+1屏蔽层通过通孔连通。
  11. 一种基板，包括如权利要求1至5任一所述的散热兼电磁屏蔽嵌埋封装结构。
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