WO2021196841A1 - 灵敏放大器、存储器和数据读出方法 - Google Patents

灵敏放大器、存储器和数据读出方法 Download PDF

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Publication number
WO2021196841A1
WO2021196841A1 PCT/CN2021/073804 CN2021073804W WO2021196841A1 WO 2021196841 A1 WO2021196841 A1 WO 2021196841A1 CN 2021073804 W CN2021073804 W CN 2021073804W WO 2021196841 A1 WO2021196841 A1 WO 2021196841A1
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WIPO (PCT)
Prior art keywords
switch
transistor
tube
source
bit line
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PCT/CN2021/073804
Other languages
English (en)
French (fr)
Inventor
曹堪宇
池性洙
尚为兵
汪瑛
Original Assignee
长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21765813.7A priority Critical patent/EP3926628B1/en
Priority to US17/389,608 priority patent/US11862284B2/en
Publication of WO2021196841A1 publication Critical patent/WO2021196841A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the present disclosure relates to the technical field of semiconductor memory, and in particular, to a sensitive amplifier, a memory, and a data reading method.
  • DRAM Dynamic Random Access Memory, dynamic random access memory
  • SRAM Static Random-Access Memory, static random access memory
  • SA Sense Amplifier
  • the memory cell stores "1" while the data read from the bit line is "0". In this way, it will seriously affect the performance of the semiconductor memory.
  • the purpose of the present disclosure is to provide a sensitive amplifier, a memory, and a data reading method, so as to overcome at least to a certain extent the problem of memory reading data errors caused by limitations and defects of related technologies.
  • a sensitive amplifier including: a first PMOS tube, the gate of the first PMOS tube is connected to the first bit line; a second PMOS tube, the gate of the second PMOS tube is connected to the second bit line
  • the bit line is connected, the source of the second PMOS tube is connected to the source of the first PMOS tube; wherein, the second bit line is an inverted bit line corresponding to the first bit line;
  • the first NMOS tube is the gate of the first NMOS tube
  • the electrode is connected to the drain of the second PMOS tube, the drain of the first NMOS tube is connected to the drain of the first PMOS tube;
  • the second NMOS tube, the gate of the second NMOS tube is connected to the drain of the first PMOS tube,
  • the drain of the second NMOS tube is connected to the drain of the second PMOS tube, and the source of the second NMOS tube is connected to the source of the first NMOS tube; wherein, in the offset compensation stage of the sense amplifier, the first PMOS tube and
  • the first PMOS tube and the second PMOS tube are configured in the signal receiving mode to be amplified for receiving the signal to be amplified, and the signal to be amplified is transmitted from the first bit line or the second bit line.
  • the charge in the parasitic capacitance and the charge in the corresponding storage unit are generated by charge sharing; and the first NMOS tube and the second NMOS tube are configured in a cross-coupling amplification mode.
  • the first PMOS tube and the first NMOS tube are configured as a first inverter
  • the second PMOS tube and the second NMOS tube are configured as a second inverter; wherein, The first inverter and the second inverter are configured in a latch mode.
  • the sensitive amplifier further includes: a first switch, the first end of the first switch is connected to the drain of the first PMOS transistor, and the second end of the first switch is connected to the gate of the first PMOS transistor; the second switch , The first terminal of the second switch is connected to the drain of the second PMOS tube, the second terminal of the second switch is connected to the gate of the second PMOS tube; the third switch, the first terminal of the third switch is connected to the first switch The first end of the third switch is connected to the second end of the second switch; the fourth switch, the first end of the fourth switch is connected to the first end of the second switch, and the second end of the fourth switch is connected to the first end of the second switch. The terminal is connected to the second terminal of the first switch.
  • the first switch and the second switch are closed, and the third switch and the fourth switch are opened; in the pre-amplification stage of the sense amplifier, the first switch, the second switch, and the third switch And the fourth switch are both open; in the write-back phase of the sensitive amplifier, the first switch and the second switch are open, and the third switch and the fourth switch are closed.
  • the sensitive amplifier further includes: a pull-up unit for connecting the source of the first PMOS tube to the power supply voltage in response to a pull-up control signal; a pull-down unit for connecting the source of the first NMOS tube to the source of the first NMOS tube in response to the pull-down control signal Grounded.
  • the pull-up unit includes a pull-up PMOS tube, the gate of the pull-up PMOS tube receives the pull-up control signal, the source of the pull-up PMOS tube is connected to the power supply voltage, and the drain of the pull-up PMOS tube is connected to the first PMOS tube
  • the pull-down unit includes a pull-down NMOS tube, the gate of the pull-down NMOS tube receives a pull-down control signal, the source of the pull-down NMOS tube is grounded, and the drain of the pull-down NMOS tube is connected to the source of the first NMOS tube.
  • the sensitive amplifier further includes: a first pre-charging unit for responding to a pre-charging control signal, so that when the first switch, the second switch, the third switch, and the fourth switch are all closed, the first PMOS The source of the tube and the source of the first NMOS tube are pre-charged; the second pre-charge unit is used to respond to the pre-charge control signal so that the first switch, the second switch, the third switch, and the fourth switch are all closed. In this case, the first bit line and the second bit line are precharged.
  • the sensitive amplifier further includes: a switch control unit for controlling the switching states of the first switch, the second switch, the third switch, and the fourth switch in response to the control signal.
  • the sensitive amplifier further includes: a fifth switch, the first end of the fifth switch is connected to the second end of the third switch, the second end of the fifth switch is connected to the second bit line; the sixth switch, the sixth switch The first end of the switch is connected to the second end of the fourth switch, and the second end of the sixth switch is connected to the first bit line.
  • the type of the first switch is PMOS, NMOS, or CMOS transmission gate
  • the type of the second switch is PMOS, NMOS, or CMOS transmission gate
  • the type of the third switch is PMOS, NMOS, or CMOS transmission
  • the type of the fourth switch is PMOS tube, NMOS tube or CMOS transmission gate
  • the type of the fifth switch is PMOS tube, NMOS tube or CMOS transmission gate
  • the type of the sixth switch is PMOS tube, NMOS tube or CMOS transmission gate.
  • a memory including the sense amplifier as described above.
  • a data readout method applied to any of the above-mentioned sense amplifiers; wherein the data readout method includes: precharging the sense amplifier; determining the offset compensation voltage of the sense amplifier, and storing The parasitic capacitance of the bit line is used to compensate for the offset of the sensitive amplifier; the charge in the parasitic capacitance and the charge in the storage unit are shared to generate the signal to be amplified; the signal to be amplified is amplified and output to realize the output from the storage unit Read the data.
  • the operation of pre-charging the sensitive amplifier includes: controlling the first switch, the second switch, the third switch, and the fourth switch to be in a closed state, and controlling the first bit line, the second bit line, and the first PMOS transistor.
  • the source electrode and the source electrode of the first NMOS tube are precharged.
  • the operation of storing the offset compensation voltage of the sensitive amplifier in the parasitic capacitance of the bit line includes: controlling the first switch and the second switch to be in the closed state; controlling the third switch and the fourth switch to be in the off state; controlling the first switch
  • the source of the PMOS tube is connected to the power supply voltage; the source of the first NMOS tube is controlled to be grounded.
  • the operation of performing charge sharing between the charge in the parasitic capacitance and the charge in the storage unit includes: controlling the source of the first PMOS transistor and the source of the first NMOS transistor to be charged to a precharged potential; controlling the first switch , The second switch, the third switch, and the fourth switch are in the off state; among them, when the memory cell reads out the charge in response to the turn-on signal of the word line, the charge in the parasitic capacitance is shared with the charge in the memory cell .
  • the operation of amplifying and outputting the signal to be amplified includes: the first step is to control the source of the first PMOS transistor to be connected to the power supply voltage, control the source of the first NMOS transistor to be grounded, and control the first switch and the second switch , The third switch and the fourth switch are in the off state; the second step is to control the third switch and the fourth switch to be in the closed state.
  • the operation of amplifying and outputting the signal to be amplified includes: controlling the source of the first PMOS transistor to be connected to the power supply voltage, controlling the source of the first NMOS transistor to be grounded; controlling the first switch and the second switch to be in an off state , Control the third switch and the fourth switch to be in the closed state.
  • controlling the third switch and the fourth switch to be in the closed state includes: controlling the voltages of the control terminals of the third switch and the fourth switch so that the on-resistance of the third switch and the fourth switch is gradually reduced.
  • the sensitive amplifier further includes a fifth switch and a sixth switch, the first end of the fifth switch is connected to the second end of the third switch, the second end of the fifth switch is connected to the second bit line, and the sixth switch The first end of the switch is connected to the second end of the fourth switch, and the second end of the sixth switch is connected to the first bit line; wherein, the operation of amplifying and outputting the signal to be amplified includes: the first step is to control the first PMOS transistor The source of is connected to the power supply voltage; the source of the first NMOS tube is controlled to be grounded; the first switch, the second switch, the fifth switch and the sixth switch are controlled to be in the off state; the third switch and the fourth switch are controlled to be in the closed state ; The second step is to control the fifth switch and the sixth switch to be in a closed state.
  • controlling the fifth switch and the sixth switch to be in a closed state includes: controlling the voltages of the control terminals of the fifth switch and the sixth switch so that the conduction impedance of the fifth switch and the sixth switch gradually decreases.
  • the offset compensation of the sense amplifier can be realized, the problem of reading data errors due to the difference of each transistor is solved, and the memory is improved. Performance.
  • Fig. 1 schematically shows a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure
  • Fig. 2 schematically shows a circuit diagram of a first precharging unit according to an exemplary embodiment of the present disclosure
  • FIG. 3 schematically shows a flowchart of a data readout method according to an exemplary embodiment of the present disclosure
  • Fig. 4 schematically shows a circuit diagram of a sensitive amplifier in a pre-charge stage according to an exemplary embodiment of the present disclosure
  • Fig. 5 schematically shows a circuit diagram of a sense amplifier in an offset compensation stage according to an exemplary embodiment of the present disclosure
  • Fig. 6 schematically shows a circuit diagram of a sense amplifier in a charge sharing stage according to an exemplary embodiment of the present disclosure
  • Fig. 7 schematically shows a circuit diagram of a sensitive amplifier in a pre-amplification stage according to an exemplary embodiment of the present disclosure
  • FIG. 8 schematically shows a circuit diagram of a sense amplifier in a write-back phase according to an exemplary embodiment of the present disclosure
  • FIG. 9 shows a schematic diagram of the change of the control terminal voltage of the switch S3 and the switch S4 in the write-back phase according to the exemplary embodiment of the present disclosure
  • FIG. 10 schematically shows a corresponding timing diagram of a sense amplifier according to an exemplary embodiment of the present disclosure
  • FIG. 11 schematically shows a circuit diagram of a sensitive amplifier in the pre-amplification stage according to another exemplary embodiment of the present disclosure
  • FIG. 12 schematically shows a corresponding timing diagram of a sense amplifier according to another exemplary embodiment of the present disclosure.
  • connection in the present disclosure may include direct connection and indirect connection.
  • direct connection there are no components between terminals.
  • the first terminal of switch A is connected to the first terminal of switch B, which can be the connection line between the first terminal of switch A and the first terminal of switch B
  • the indirect connection there may be other components between the terminal and the terminal.
  • the first terminal of the switch C and the first terminal of the switch D can be connected between the first terminal of the switch C and the first terminal of the switch D.
  • On the connection line in addition to the connection line, there is at least one other component (such as switch E, etc.) on the connection line.
  • the sensitive amplifier includes two symmetrically configured NMOS tubes. In an ideal state, it is hoped that the performance of the two NMOS tubes is exactly the same. However, in reality, the threshold voltages of the two NMOS transistors may be different, which will cause the circuit to be out of adjustment. If no measures are taken at this time, when reading data from the storage unit, it is possible to read the originally stored "1" as a "0" error output, or read the originally stored "0" as a "1" error output .
  • the present disclosure provides a new sensitive amplifier.
  • Fig. 1 schematically shows a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • the sensitive amplifier of the exemplary embodiment of the present disclosure may include a first PMOS tube (hereinafter referred to as transistor P1), a second PMOS tube (hereinafter referred to as transistor P2), a first NMOS tube (hereinafter referred to as transistor N1), and a second NMOS tube (hereinafter referred to as transistor N1).
  • transistor N2 first switch (hereinafter referred to as switch S1), second switch (hereinafter referred to as switch S2), third switch (hereinafter referred to as switch S3) and fourth switch (hereinafter referred to as switch S4).
  • the gate of the transistor P1 is connected to the first bit line BL, and the gate of the transistor P2 is connected to the second bit line BLB.
  • the second bit line BLB is an inverted bit line corresponding to the first bit line BL.
  • the source of the transistor P1 is connected to the source of the transistor P2.
  • the source of the transistor P1 and the source of the transistor P2 are both connected to the node ACT.
  • the gate of the transistor N1 is connected to the drain of the transistor P2.
  • the gate of the transistor N1 and the drain of the transistor P2 are both connected to the node NODE1.
  • the drain of the transistor N1 is connected to the drain of the transistor P1.
  • the drain of the transistor N1 and the drain of the transistor P1 are both connected to the node NODE2.
  • the gate of the transistor N2 is connected to the drain of the transistor P1, that is, the gate of the transistor N2 is connected to the node NODE2.
  • the drain of the transistor N2 is connected to the drain of the transistor P2, that is, the drain of the transistor N2 is connected to the node NODE1.
  • the source of the transistor N1 is connected to the source of the transistor N2.
  • the source of the transistor N1 and the source of the transistor N2 are both connected to the node NLAT.
  • the first end of the switch S1 is connected to the drain of the transistor P1, that is, the first end of the switch S1 is connected to the node NODE2.
  • the second end of the switch S1 is connected to the gate of the transistor P1 and the first bit line BL, that is, the second end of the switch S1 is also connected to the first bit line BL.
  • the first end of the switch S2 is connected to the drain of the transistor P2, that is, the first end of the switch S2 is connected to the node NODE1.
  • the second end of the switch S2 is connected to the gate of the transistor P2 and the second bit line BLB, that is, the second end of the switch S2 is also connected to the second bit line BLB.
  • the first end of the switch S3 is connected to the first end of the switch S1, that is, the first end of the switch S3 is connected to the node NODE2.
  • the second end of the switch S3 is connected to the second end of the switch S2, that is, the second end of the switch S3 is connected to the second bit line BLB.
  • the first end of the switch S4 is connected to the first end of the switch S2, that is, the first end of the switch S4 is connected to the node NODE1.
  • the second end of the switch S4 is connected to the second end of the switch S1, that is, the second end of the switch S4 is connected to the first bit line BL.
  • switch S1 may be a PMOS tube, NMOS tube, or CMOS transmission gate
  • switch S2 may be a PMOS tube, NMOS tube, or CMOS transmission gate
  • the switch S3 can be a PMOS tube, an NMOS tube or a CMOS transmission gate
  • the switch S4 can be a PMOS tube, an NMOS tube or a CMOS transmission gate.
  • the switches S1 to S4 may also include control terminals for controlling the opening and closing states thereof.
  • the sensitive amplifier of the exemplary embodiment of the present disclosure further includes a pull-up unit and a pull-down unit.
  • the pull-up unit is used to connect the source of the transistor P1 to the power supply voltage VDD in response to the pull-up control signal, that is, the pull-up unit can connect the node ACT to the power supply voltage VDD.
  • the pull-down unit is used to connect the source of the transistor N1 to the ground (ie, connected to VSS) in response to the pull-down control signal, that is, the pull-down unit can connect the node NLAT to VSS.
  • the pull-up unit may include a pull-up PMOS tube (hereinafter referred to as transistor P3), the gate of the transistor P3 receives the pull-up control signal Sense_P (the control signal for turning on the transistor P3), and the source of the transistor P3 Connected to the power supply voltage VDD, the drain of the transistor P3 is connected to the node ACT.
  • transistor P3 a pull-up PMOS tube
  • Sense_P the control signal for turning on the transistor P3
  • the pull-down unit may include a pull-down NMOS tube (hereinafter referred to as transistor N3), the gate of the transistor N3 receives the pull-down control signal Sense_N (the control signal for turning on the transistor N3), the source of the transistor N3 is grounded, and the transistor N3 is grounded.
  • the drain of N3 is connected to the node NLAT.
  • the use of the transistor P3 to form the pull-up unit and the transistor N3 to form the pull-down unit are only an example of the present disclosure.
  • the pull-up unit can also be implemented using an NMOS transistor.
  • the pull-down unit can also be implemented by using a PMOS tube, and the pull-up unit or the pull-down unit can include more than one device, and can also include multiple devices that are turned on or off by different control signals.
  • the schemes of making the node ACT connectable to VDD and making the node NLAT connectable to VSS should all fall within the scope of protection of the present disclosure.
  • the sense amplifier of the present disclosure may further include a first pre-charging unit and a second pre-charging unit.
  • the first pre-charging unit is used to respond to the pre-charging control signal to pre-charge the node ACT and the node NLAT when the switch S1, the switch S2, the switch S3, and the switch S4 are all closed.
  • the second pre-charging unit is used to respond to the pre-charging control signal, so that when the switch S1, the switch S2, the switch S3, and the switch S4 are all closed, the first bit line BL, the second bit line BLB, the node NODE1 and the node NODE2 Perform pre-charging.
  • the pre-charge voltage can be denoted as VEQ
  • the pre-charge voltage VEQ output by the first pre-charge unit and the second pre-charge unit can be configured as VDD/2 or other voltage values.
  • first pre-charging unit and the second pre-charging unit can be allocated and configured, or the first pre-charging unit and the second pre-charging unit can be configured as one charging unit, and the input of the charging unit includes a pre-charging control signal And the precharge voltage, and includes a plurality of output terminals respectively connected to the node ACT, the node NLAT, the node NODE1 and the node NODE2. This disclosure does not limit this.
  • Fig. 2 exemplarily shows a circuit structure of the first precharging unit, wherein the control terminal of the first precharging unit is used to receive a control signal EQ to control the on and off of each transistor in the first precharging unit State to pre-charge the node ACT and the node NLAT.
  • the switch S1, the switch S2, the switch S3, and the switch S4 are all closed, the node ACT and the node NLAT are precharged to VEQ.
  • the structure of the second precharging unit is similar to that of the first precharging unit.
  • the control terminal of the second precharging unit is also used to receive the control signal EQ to control the on and off states of the transistors in the second precharging unit, so as to precharge the node NODE1 and the node NODE2.
  • the switch S1, the switch S2, the switch S3, and the switch S4 are all closed, the node NODE1 and the node NODE2 are precharged to VEQ.
  • the sensitive amplifier of the present disclosure may further include a switch control unit for controlling the switching states (ie, closed and open) of the switches S1, S2, S3, and S4 in response to a control signal.
  • a switch control unit for controlling the switching states (ie, closed and open) of the switches S1, S2, S3, and S4 in response to a control signal.
  • the switch control unit can also output signals for controlling the switching states of the transistor P3 and the transistor N3, that is, the switch control unit can also output the pull-up control signal Sense_P and the pull-down control signal Sense_N.
  • the present disclosure also provides a data reading method, which includes the following steps:
  • the operation of precharging the sensitive amplifier includes controlling the switch S1, the switch S2, the switch S3, and the switch S4 to be in the closed state, and the first bit line BL, the second bit line BLB, the node NODE1, the node NODE2, and the node ACT Precharge with node NLAT.
  • the node ACT and the node NLAT may be connected to the output terminal of the first precharge unit, and the first precharge unit outputs the precharge voltage VEQ from the output terminal in response to the precharge control signal EQ, so as to realize the precharge of the node ACT and the node NLAT .
  • Node NODE1 and node NODE2 can be connected to the output terminal of the second precharge unit, and the second precharge unit outputs the precharge voltage VEQ from the output terminal in response to the precharge control signal EQ, so as to realize the precharge of node NODE1 and node NODE2, that is The precharging of the first bit line BL and the second bit line BLB is realized.
  • S34 Determine the offset compensation voltage of the sense amplifier and store it in the parasitic capacitance of the bit line to perform offset compensation on the sense amplifier.
  • the control switch S1 and the switch S2 are in the closed state, and the control switch S3 and the switch S4 are in the open state.
  • the transistor P1 and the transistor P2 are configured in a diode connection mode, and the transistor N1 and the transistor N2 are configured in a cross-coupled amplification mode.
  • control transistor P3 is turned on to connect the node ACT with the power supply voltage VDD; the control transistor N3 is turned on to ground the node NLAT.
  • an offset compensation voltage Vos will be generated between the first bit line BL and the second bit line BLB, and the offset compensation voltage Vos will be It is stored on the parasitic capacitance of the bit line, that is, the offset compensation voltage Vos is stored on the parasitic capacitance CBL2 of the first bit line BL and/or the parasitic capacitance CBL1 of the second bit line BLB.
  • Exemplary embodiments of the present disclosure configure the transistor N1 and the transistor N2 in the amplification mode, instead of configuring the transistor P1 and the transistor P2 in the amplification mode.
  • the use of transistors N1 and N2 for amplification can improve The speed at which the offset compensation voltage Vos is generated further improves the performance of the memory.
  • step S36 in the charge sharing phase corresponding to step S36, the control switch S1, the switch S2, the switch S3, and the switch S4 are all in an off state.
  • control transistor P3 and the transistor N3 are turned off, and the node ACT and the node NLAT are charged to the precharge potential (ie, VEQ).
  • the charge in the parasitic capacitance can be shared with the charge in the memory cell to generate a signal to be amplified.
  • the signal to be amplified is a small signal input voltage, which is input to the sensitive amplifier of the present disclosure for amplification.
  • Vkk is a relatively low voltage, and can even be a negative voltage, for example, -0.3 to -0.1V.
  • Vpp is a relatively high voltage, for example, 2.5 to 3.2V.
  • WL2 can be set to a lower voltage, so that the transistor can be completely turned off to avoid the charge leakage in the capacitor C2 caused by the sub-threshold leakage current.
  • WL2 can be set to a higher voltage, thus, the on-resistance of the transistor can be reduced, and the time required to read or write information can be shortened.
  • the step of amplifying the signal to be amplified may include the following two steps:
  • the switch S1, the switch S2, the switch S3, and the switch S4 are kept in the off state.
  • the control transistor P3 is turned on to connect the node ACT with the power supply voltage VDD; the control transistor N3 is turned on to ground the node NLAT.
  • the second step referring to Figure 8, maintain the node ACT connected to the power supply voltage and the node NLAT grounded state, control switch S3 and switch S4 closed, at this time, the first bit line BL is connected to the node NODE1, the second bit line BLB is connected to the node NODE2 is connected to realize writing back to the first bit line BL and the second bit line BLB. That is to say, the separation and amplification of the signals on the first bit line BL and the second bit line are realized to complete the reading of data from the memory cell.
  • the above-mentioned first step may be referred to as a pre-amplification process, and the above-mentioned second step may be referred to as a write-back process.
  • the process of the first step described above can also be omitted, that is, the switch S3 and the switch S4 are directly closed to achieve the purpose of simplifying the sequence.
  • the above-mentioned closing process of switch S3 and switch S4 may be a slow closing process.
  • the on-resistance of the switch S3 and the switch S4 can be gradually reduced, instead of a rapid closing process under ideal conditions.
  • the voltage that has been differentiated between the node NODE1 and the node NODE2 becomes close again, causing the signal separation and amplification process to fail.
  • By slowly closing the switch data write-back can be realized more quickly and reliably, and the robustness of the entire processing process is enhanced.
  • FIG. 9 shows a schematic diagram of the change of the control terminal voltage of the switch S3 and the switch S4.
  • V CTRL the voltage of the control terminal of the switch S3 is V CTRL .
  • V CTRL increases.
  • V TH of the switch S3 it will be within a preset period of time. Keep V CTRL unchanged, and then continue to increase V CTRL to VDD.
  • the switch S4 can also be slowly closed in this way.
  • Fig. 9 is only an exemplary description. On the one hand, it can also be maintained for a predetermined period of time near V TH , for example, for a predetermined period of time within the range of V TH ⁇ ⁇ , where ⁇ is a Smaller voltage value. On the other hand, you can also slowly increase V CTRL in the form of a curve. The present disclosure does not limit the process of slowly closing the switch S3 and the switch S4.
  • FIG. 10 shows a circuit timing diagram corresponding to the above steps S32 to S38.
  • the abscissa in FIG. 10 represents time, and the ordinate represents signal level, and the data "1" stored in the storage unit is taken as an example.
  • the switch S1, the switch S2, the switch S3, and the switch S4 are all in a closed state (denoted as ON).
  • the node ACT, the node NLAT, the first bit line BL, and the second bit line BLB are charged to VEQ.
  • the transistor P1 and the transistor P2 are configured in a diode connection mode, and the transistor N1 and the transistor N2 are configured in a cross-coupling amplification mode.
  • the closed state of the switch S1 and the switch S2 can be maintained, the switch S3 and the switch S4 can be opened (denoted as OFF), the node ACT can be connected to the power supply voltage VDD, and the node NLAT can be grounded.
  • the switch S1 and the switch S2 are also opened, and the node ACT and the node NLAT are set to VEQ.
  • the word line WL (for example, the aforementioned WL2) is changed from VKK to VPP, and the charge of the memory cell is read. As a result, a small signal to be amplified is generated.
  • the transistor P1 and the transistor P2 are configured in the signal receiving mode to be amplified for receiving the small signal to be amplified generated in the charge sharing stage.
  • the switch S1, the switch S2, the switch S3, and the switch S4 can be maintained in the off state, and the node ACT can be connected to the power supply voltage VDD, and the node NLAT can be grounded. At this time, the voltage on the node NODE1 and the node NODE2 is rapidly separated and amplified.
  • the transistor P1 and the transistor N1 are configured as a first inverter
  • the transistor P2 and the transistor N2 are configured as a second inverter, wherein the first inverter and the second inverter can be configured as a second inverter.
  • the separation and amplification of the voltage on the first bit line BL and the second bit line BLB are realized, and the data reading is realized.
  • another sensitive amplifier is also provided in another exemplary embodiment of the present disclosure.
  • the sensitive amplifier circuit may also include a fifth switch and a sixth switch.
  • the first end of the fifth switch may be connected to the second end of the third switch, and the second end of the fifth switch may be connected to the second bit line BLB.
  • the first end of the sixth switch may be connected to the second end of the fourth switch, and the second end of the sixth switch may be connected to the first bit line BL.
  • step S32, step S34, and step S36 the fifth switch and the sixth switch are all in the closed state, and the processing process is similar, and will not be repeated.
  • FIG. 11 schematically shows a circuit diagram of a sense amplifier including a fifth switch and a sixth switch.
  • the fifth switch may be simply referred to as switch S5
  • the sixth switch may be simply referred to as switch S6.
  • the switch S5 may be a PMOS tube, an NMOS tube or a CMOS transmission gate
  • the switch S6 may be a PMOS tube, an NMOS tube or a CMOS transmission gate.
  • the step of amplifying the signal to be amplified can also include two steps:
  • the switch S1, the switch S2, the switch S5, and the switch S6 are controlled to be in the off state, and the switch S3 and the switch S4 are controlled to be in the closed state.
  • the control transistor P3 is turned on to connect the node ACT with the power supply voltage VDD; the control transistor N3 is turned on to ground the node NLAT.
  • the transistor P1 and the transistor P2 are also configured in amplification mode
  • the transistor P1 and the transistor N1 form a CMOS inverter
  • the transistor P2 and the transistor N2 also form a CMOS inverter
  • the two inverters It is configured in the form of a cross-coupled latch. Because of this configuration, the maximum equivalent transconductance can be obtained, thereby increasing the amplification speed of the signal to be amplified and shortening the signal readout time.
  • the process of closing the switch S5 and the switch S6 may be a slow closing process.
  • the voltages of the control terminals of the switch S5 and the switch S6 can be controlled to gradually reduce the on-resistance of the switch S5 and the switch S6.
  • the operation process is similar to the above-mentioned process of slowly closing the switch S3 and the switch S4, and will not be repeated here.
  • Fig. 12 shows a timing diagram of a sense amplifier including a switch S5 and a switch S6.
  • the time sequence part corresponding to the time interval t 0 -t 3 in FIG. 12 is the same as the time sequence part corresponding to the time interval t 0 -t 3 shown in FIG. 10, and will not be repeated here.
  • the transistor P1 and the transistor N1 are configured as a first inverter
  • the transistor P2 and the transistor N2 are configured as a second inverter, wherein the first inverter and the second inverter can be configured as a second inverter. Configured as latch mode.
  • the switch S1, the switch S2, the switch S5, and the switch S6 are opened, the switch S3 and the switch S4 are closed, and the node ACT is connected to the power supply voltage VDD, and the node NLAT is grounded.
  • the voltage on node NODE1 and node NODE2 is quickly separated and amplified, and the speed is faster than that shown in Figure 10 (the slope of change is larger), thus, the speed of reading data from the memory is further improved, and the speed is increased. Memory performance.
  • time interval t 4- t 5 shown in FIG. 12 corresponds to the write-back phase of the sense amplifier.
  • switch S5 and switch S6 are closed, and the rest of the configuration remains unchanged.
  • the separation and amplification of the voltage on the first bit line BL and the second bit line BLB are realized, and the data reading is realized.
  • the offset compensation of the sense amplifier can be realized, the problem of reading data errors due to the difference of each transistor can be solved, and the memory is improved. Performance.
  • the present disclosure also provides a memory including the above-mentioned sensitive amplifier.

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Abstract

本公开提供了一种灵敏放大器、存储器和数据读出方法，涉及半导体存储器技术领域。该灵敏放大器包括：第一PMOS管、第二PMOS管、第一NMOS管、第二NMOS管、第一开关、第二开关、第三开关和第四开关，在灵敏放大器的失调补偿阶段，控制第一开关至第四开关的开合状态，使第一NMOS管和第二NMOS管配置为交叉耦合放大模式，使第一PMOS管和第二PMOS管配置为二极管连接模式。本公开可以实现灵敏放大器的失调补偿，提高存储器读出数据的正确性。

Description

灵敏放大器、存储器和数据读出方法
相关申请的交叉引用
本申请要求于2020年03月30日提交的申请号为202010237828.4、名称为“灵敏放大器、存储器和数据读出方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体存储器技术领域，具体而言，涉及一种灵敏放大器、存储器和数据读出方法。
背景技术
随着手机、平板、个人计算机等电子设备的普及，半导体存储器技术也得到了快速的发展。例如DRAM(Dynamic Random Access Memory，动态随机存取存储器)、SRAM(Static Random-Access Memory，静态随机存取存储器)的存储器由于高密度、低功耗、低价格等优点，已广泛应用于各种电子设备中。
灵敏放大器(Sense Amplifier，简称SA)是半导体存储器的一个重要组成部分，其主要作用是将位线上的小信号放大至数字信号，从而执行读出或写入操作。
然而，由于灵敏放大器内部的缺陷或环境的影响，可能出现读写错误的问题，例如，存储单元中存储的是“1”，而从位线读出的数据是“0”。这样，会严重影响半导体存储器的性能。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种灵敏放大器、存储器和数据读出方法，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的存储器读出数据错误的问题。
根据本公开的第一方面，提供一种灵敏放大器，包括：第一PMOS管，第一PMOS管的栅极与第一位线连接；第二PMOS管，第二PMOS管的栅极与第二位线连接，第二PMOS管的源极与第一PMOS管的源极连接；其中，第二位线是与第一位线对应的反位线；第一NMOS管，第一NMOS管的栅极与第二PMOS管的漏极连接，第一NMOS管的漏极与第一PMOS管的漏极连接；第二NMOS管，第二NMOS管的栅极与第一PMOS管的漏极连接，第二NMOS管的漏极与第二PMOS管的漏极连接，第二NMOS管的源极与第一NMOS管的源极连接；其中，在灵敏放大器的失调补偿阶段，第一PMOS管和第二PMOS管被配置为二极管连接模式，第一NMOS管和第二NMOS管被配置为交叉耦合 放大模式。
可选地，在灵敏放大器的预放大阶段，第一PMOS管和第二PMOS管被配置为待放大信号接收模式，用于接收待放大信号，待放大信号由第一位线或第二位线的寄生电容中的电荷与对应的存储单元中的电荷进行电荷共享而生成；以及第一NMOS管和第二NMOS管被配置为交叉耦合放大模式。
可选地，在灵敏放大器的回写阶段，第一PMOS管和第一NMOS管被配置为第一反相器，第二PMOS管和第二NMOS管被配置为第二反相器；其中，第一反相器和第二反相器被配置为锁存器模式。
可选地，灵敏放大器还包括：第一开关，第一开关的第一端与第一PMOS管的漏极连接，第一开关的第二端与第一PMOS管的栅极连接；第二开关，第二开关的第一端与第二PMOS管的漏极连接，第二开关的第二端与第二PMOS管的栅极连接；第三开关，第三开关的第一端与第一开关的第一端连接，第三开关的第二端与第二开关的第二端连接；第四开关，第四开关的第一端与第二开关的第一端连接，第四开关的第二端与第一开关的第二端连接。
可选地，在灵敏放大器的失调补偿阶段，第一开关和第二开关闭合，第三开关和第四开关断开；在灵敏放大器的预放大阶段，第一开关、第二开关、第三开关和第四开关均断开；在灵敏放大器的回写阶段，第一开关和第二开关断开，第三开关和第四开关闭合。
可选地，灵敏放大器还包括：上拉单元，用于响应上拉控制信号将第一PMOS管的源极与电源电压连接；下拉单元，用于响应下拉控制信号将第一NMOS管的源极接地。
可选地，上拉单元包括上拉PMOS管，上拉PMOS管的栅极接收上拉控制信号，上拉PMOS管的源极与电源电压连接，上拉PMOS管的漏极与第一PMOS管的源极连接；下拉单元包括下拉NMOS管，下拉NMOS管的栅极接收下拉控制信号，下拉NMOS管的源极接地，下拉NMOS管的漏极与第一NMOS管的源极连接。
可选地，灵敏放大器还包括：第一预充电单元，用于响应预充电控制信号，以在第一开关、第二开关、第三开关、第四开关均闭合的情况下，对第一PMOS管的源极和第一NMOS管的源极进行预充电；第二预充电单元，用于响应预充电控制信号，以在第一开关、第二开关、第三开关、第四开关均闭合的情况下，对第一位线和第二位线进行预充电。
可选地，灵敏放大器还包括：开关控制单元，用于响应控制信号，对第一开关、第二开关、第三开关和第四开关的开关状态进行控制。
可选地，灵敏放大器还包括：第五开关，第五开关的第一端与第三开关的第二端连接，第五开关的第二端与第二位线连接；第六开关，第六开关的第一端与第四开关的第二端连接，第六开关的第二端与第一位线连接。
可选地，第一开关的类型为PMOS管、NMOS管或CMOS传输门；第二开关的类型为PMOS管、NMOS管或CMOS传输门；第三开关的类型为PMOS管、NMOS管或CMOS传输门；第四开关的类型为PMOS管、NMOS管或CMOS传输门；第五开关的类型为PMOS 管、NMOS管或CMOS传输门；第六开关的类型为PMOS管、NMOS管或CMOS传输门。
根据本公开的第二方面，提供一种存储器，包括如上述任意一项的灵敏放大器。
根据本公开的第三方面，提供一种数据读出方法，应用于上述任意一种灵敏放大器；其中，数据读出方法包括：对灵敏放大器进行预充电；确定灵敏放大器的失调补偿电压，并存储于位线的寄生电容，以对灵敏放大器进行失调补偿；对寄生电容中的电荷与存储单元中的电荷进行电荷共享，生成待放大信号；对待放大信号进行放大并输出，以实现从存储单元中读取数据。
可选地，对灵敏放大器进行预充电的操作包括：控制第一开关、第二开关、第三开关和第四开关处于闭合状态，对第一位线、第二位线、第一PMOS管的源极和第一NMOS管的源极进行预充电。
可选地，将灵敏放大器的失调补偿电压存储于位线的寄生电容的操作包括：控制第一开关、第二开关处于闭合状态；控制第三开关、第四开关处于断开状态；控制第一PMOS管的源极与电源电压连接；控制第一NMOS管的源极接地。
可选地，对寄生电容中的电荷与存储单元中的电荷进行电荷共享的操作包括：控制第一PMOS管的源极和第一NMOS管的源极充电至预充电的电位；控制第一开关、第二开关、第三开关、第四开关处于断开状态；其中，在存储单元响应字线的开启信号而读出电荷的情况下，寄生电容中的电荷与存储单元中的电荷进行电荷共享。
可选地，对待放大信号进行放大并输出的操作包括：第一步，控制第一PMOS管的源极与电源电压连接，控制第一NMOS管的源极接地，控制第一开关、第二开关、第三开关、第四开关处于断开状态；第二步，控制第三开关和第四开关处于闭合状态。
可选地，对待放大信号进行放大并输出的操作包括：控制第一PMOS管的源极与电源电压连接，控制第一NMOS管的源极接地；控制第一开关和第二开关处于断开状态，控制第三开关和第四开关处于闭合状态。
可选地，控制第三开关和第四开关处于闭合状态包括：控制第三开关和第四开关的控制端的电压，使第三开关和第四开关的导通阻抗逐渐减小。
可选地，灵敏放大器还包括第五开关和第六开关，第五开关的第一端与第三开关的第二端连接，第五开关的第二端与第二位线连接，第六开关的第一端与第四开关的第二端连接，第六开关的第二端与第一位线连接；其中，对待放大信号进行放大并输出的操作包括：第一步，控制第一PMOS管的源极与电源电压连接；控制第一NMOS管的源极接地；控制第一开关、第二开关、第五开关和第六开关处于断开状态；控制第三开关和第四开关处于闭合状态；第二步，控制第五开关和第六开关处于闭合状态。
可选地，控制第五开关和第六开关处于闭合状态包括：控制第五开关和第六开关的控制端的电压，使第五开关和第六开关的导通阻抗逐渐减小。
在本公开的一些实施例所提供的技术方案中，通过配置如上描述的灵敏放大器，可以 实现灵敏放大器的失调补偿，解决了由于各晶体管的差异而可能导致读出数据错误的问题，提高了存储器的性能。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1示意性示出了根据本公开的示例性实施方式的灵敏放大器的电路图；
图2示意性示出了根据本公开的示例性实施方式的第一预充电单元的电路图；
图3示意性示出了根据本公开的示例性实施方式的数据读出方法的流程图；
图4示意性示出了根据本公开的示例性实施方式的在预充电阶段灵敏放大器的电路图；
图5示意性示出了根据本公开的示例性实施方式的在失调补偿阶段灵敏放大器的电路图；
图6示意性示出了根据本公开的示例性实施方式的在电荷共享阶段灵敏放大器的电路图；
图7示意性示出了根据本公开的示例性实施方式的在预放大阶段灵敏放大器的电路图；
图8示意性示出了根据本公开的示例性实施方式的在回写阶段灵敏放大器的电路图；
图9示出了根据本公开的示例性实施方式的回写阶段开关S3和开关S4的控制端电压的变化示意图；
图10示意性示出了根据本公开的示例性实施方式的灵敏放大器对应的时序图；
图11示意性示出了根据本公开的另一示例性实施方式的在预放大阶段灵敏放大器的电路图；
图12示意性示出了根据本公开的另一示例性实施方式的灵敏放大器对应的时序图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到， 可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。“第一”、“第二”、“第三”、“第四”、“第五”、“第六”的描述仅是为了区分，不应作为本公开的限制。
需要说明的是，本公开所说的术语“连接”，可以包括直接连接和间接连接。在直接连接中，端与端之间没有元器件，例如，开关A的第一端与开关B的第一端连接，可以是在开关A的第一端与开关B的第一端的连接线路上，只有连接线(如，金属线)，而不存在其他元器件。在间接连接中，端与端之间可以存在其他元器件，例如，开关C的第一端与开关D的第一端连接，可以是在开关C的第一端与开关D的第一端的连接线路上，除连接线外，连接线上还存在至少一个其他元器件(如，开关E等)。
在灵敏放大器中，由于制程上的差异以及工作环境的影响，可能导致晶体管的尺寸、迁移率、阈值电压等存在差别，各晶体管的性能通常不可能完全相同，这就会造成灵敏放大器失调，相当于出现了失调噪声，严重影响存储器读出数据的正确性。
例如，灵敏放大器包括两个对称配置的NMOS管，理想状态下，希望这两个NMOS管的性能完全相同。然而，在实际中，这两个NMOS管的阈值电压可能不同，这就会出现电路失调的情况。此时若不采取任何措施，在从存储单元读出数据时，就有可能将原本存储的“1”读成“0”错误输出，或者将原本存储的“0”读成“1”错误输出。
为了解决这个问题，本公开提供了一种新的灵敏放大器。
图1示意性示出了根据本公开的示例性实施方式的灵敏放大器的电路图。
本公开示例性实施方式的灵敏放大器可以包括第一PMOS管(下面简称晶体管P1)、第二PMOS管(下面简称晶体管P2)、第一NMOS管(下面简称晶体管N1)、第二NMOS管(下面简称晶体管N2)、第一开关(下面简称开关S1)、第二开关(下面简称开关S2)、第三开关(下面简称开关S3)和第四开关(下面简称开关S4)。下面将参考图1详细说明上述元件的连接方式：
晶体管P1的栅极与第一位线BL连接，晶体管P2的栅极与第二位线BLB连接。如图1所绘的，本领域技术人员容易理解的是，第二位线BLB是与第一位线BL对应的反位线。
晶体管P1的源极与晶体管P2的源极连接，为了方便描述，可以视为晶体管P1的源极及晶体管P2的源极均连接于节点ACT。
晶体管N1的栅极与晶体管P2的漏极连接，为了方便描述，可以视为晶体管N1的栅极与晶体管P2的漏极均连接于节点NODE1。晶体管N1的漏极与晶体管P1的漏极连接，为了方便描述，可以视为晶体管N1的漏极与晶体管P1的漏极均连接于节点NODE2。
晶体管N2的栅极与晶体管P1的漏极连接，也就是说，晶体管N2的栅极连接于节点 NODE2。晶体管N2的漏极与晶体管P2的漏极连接，也就是说，晶体管N2的漏极连接于节点NODE1。
晶体管N1的源极与晶体管N2的源极连接，为了方便描述，可以视为晶体管N1的源极及晶体管N2的源极均连接于节点NLAT。
开关S1的第一端与晶体管P1的漏极连接，也就是说，开关S1的第一端连接于节点NODE2。开关S1的第二端与晶体管P1的栅极以及第一位线BL连接，也就是说，开关S1的第二端也连接于第一位线BL。
开关S2的第一端与晶体管P2的漏极连接，也就是说，开关S2的第一端连接于节点NODE1。开关S2的第二端与晶体管P2的栅极以及第二位线BLB连接，也就是说，开关S2的第二端也连接于第二位线BLB。
开关S3的第一端与开关S1的第一端连接，也就是说，开关S3的第一端连接于节点NODE2。开关S3的第二端与开关S2的第二端连接，也就是说，开关S3的第二端连接于第二位线BLB。
开关S4的第一端与开关S2的第一端连接，也就是说，开关S4的第一端连接于节点NODE1。开关S4的第二端与开关S1的第二端连接，也就是说，开关S4的第二端连接于第一位线BL。
本公开对开关S1、开关S2、开关S3和开关S4的类型不做限制，例如，开关S1可以是PMOS管、NMOS管或CMOS传输门，开关S2可以是PMOS管、NMOS管或CMOS传输门，开关S3可以是PMOS管、NMOS管或CMOS传输门，开关S4可以是PMOS管、NMOS管或CMOS传输门。在这种情况下，本领域技术人员容易理解的是，开关S1至开关S4除包括第一端和第二端外，还可以包括控制其开合状态的控制端。
此外，本公开示例性实施方式的灵敏放大器还包括上拉单元和下拉单元。其中，上拉单元用于响应上拉控制信号将晶体管P1的源极与电源电压VDD连接，也就是说，上拉单元可以将节点ACT连接于电源电压VDD。下拉单元用于响应下拉控制信号将晶体管N1的源极接地(即，连接于VSS)，也就是说，下拉单元可以将节点NLAT连接于VSS。
在本公开的一个实施例中，上拉单元可以包括上拉PMOS管(下面简称晶体管P3)，晶体管P3的栅极接收上拉控制信号Sense_P(晶体管P3开启的控制信号)，晶体管P3的源极与电源电压VDD连接，晶体管P3的漏极连接于节点ACT。
在本公开的一个实施例中，下拉单元可以包括下拉NMOS管(下面简称晶体管N3)，晶体管N3的栅极接收下拉控制信号Sense_N(晶体管N3开启的控制信号)，晶体管N3的源极接地，晶体管N3的漏极连接于节点NLAT。
应当理解的是，以晶体管P3形成上拉单元以及以晶体管N3形成下拉单元仅是本公开的一个实例，本领域技术人员可以联想到其他的实现方式，例如，上拉单元也可以使用NMOS管实现，下拉单元也可以使用PMOS管实现，并且上拉单元或下拉单元可以包含不止一个器件，也可以包括通过不同的控制信号控制导通或关断的多个器件。然而，结合 本公开灵敏放大器的整体结构，使节点ACT可连接于VDD以及使节点NLAT可连接于VSS的方案均应属于本公开内容的保护范围。
另外，本公开的灵敏放大器还可以包括第一预充电单元和第二预充电单元。
第一预充电单元用于响应预充电控制信号，以在开关S1、开关S2、开关S3和开关S4均闭合的情况下，对节点ACT和节点NLAT进行预充电。
第二预充电单元用于响应预充电控制信号，以在开关S1、开关S2、开关S3和开关S4均闭合的情况下，对第一位线BL、第二位线BLB、节点NODE1和节点NODE2进行预充电。
其中，可以将预充电电压记为VEQ，第一预充电单元和第二预充电单元输出的预充电电压VEQ可以被配置为VDD/2，也可以是其它的电压值。
需要说明的是，第一预充电单元和第二预充电单元可以分配配置，也可以将第一预充电单元和第二预充电单元配置为一个充电单元，该充电单元的输入包括预充电控制信号和预充电电压，并且包括分别与节点ACT、节点NLAT、节点NODE1和节点NODE2连接的多个输出端。本公开对此不做限制。
图2示例性示出了第一预充电单元的一种电路结构，其中，第一预充电单元的控制端用于接收控制信号EQ，来控制第一预充电单元中各晶体管的导通关断状态，以对节点ACT和节点NLAT进行预充电。在开关S1、开关S2、开关S3和开关S4均闭合的情况下，节点ACT和节点NLAT被预充电至VEQ。
第二预充电单元与第一预充电单元的结构类似。第二预充电单元的控制端也用于接收控制信号EQ，来控制第二预充电单元中各晶体管的导通关断状态，以对节点NODE1和节点NODE2进行预充电。在开关S1、开关S2、开关S3和开关S4均闭合的情况下，节点NODE1和节点NODE2被预充电至VEQ。
此外，本公开的灵敏放大器还可以包括开关控制单元，该开关控制单元用于响应控制信号，对开关S1、开关S2、开关S3和开关S4的开关状态(即，闭合及断开)进行控制。
开关控制单元还可以输出控制晶体管P3和晶体管N3开关状态的信号，也就是说，开关控制单元还可以输出上拉控制信号Sense_P和下拉控制信号Sense_N。
下面将参考图3的流程以及图4至图12的描绘，对本公开示例性实施方式的灵敏放大器执行读出操作的工作过程进行说明。
参考图3，本公开还提供了一种数据读出方法，该方法包括以下步骤：
S32.对灵敏放大器进行预充电。
参考图4，对灵敏放大器进行预充电的操作包括控制开关S1、开关S2、开关S3和开关S4处于闭合状态，对第一位线BL、第二位线BLB、节点NODE1、节点NODE2、节点ACT和节点NLAT进行预充电。
具体的，节点ACT和节点NLAT可以连接于第一预充电单元的输出端，第一预充电单元响应预充电控制信号EQ由输出端输出预充电电压VEQ，以实现节点ACT和节点 NLAT的预充电。
节点NODE1和节点NODE2可以连接于第二预充电单元的输出端，第二预充电单元响应预充电控制信号EQ由输出端输出预充电电压VEQ，以实现节点NODE1和节点NODE2的预充电，也即实现了第一位线BL和第二位线BLB的预充电。
容易理解的是，在预充电阶段，晶体管P3和晶体管N3关断。
S34.确定所述灵敏放大器的失调补偿电压，并存储于位线的寄生电容，以对灵敏放大器进行失调补偿。
参考图5，在步骤S34对应的补偿阶段中，控制开关S1和开关S2处于闭合状态，控制开关S3和开关S4处于断开状态。由此，晶体管P1和晶体管P2被配置成二极管连接模式，晶体管N1和晶体管N2被配置成交叉耦合的放大模式。
另外，控制晶体管P3导通，以将节点ACT与电源电压VDD连接；控制晶体管N3导通，以将节点NLAT接地。
在这种情况下，由于晶体管P1、晶体管P2、晶体管N1、晶体管N2之间的失配，会在第一位线BL与第二位线BLB之间产生失调补偿电压Vos，失调补偿电压Vos会存储在位线的寄生电容上，也就是说，失调补偿电压Vos存储在第一位线BL的寄生电容CBL2上和/或第二位线BLB的寄生电容CBL1上。
本公开示例性实施方式将晶体管N1和晶体管N2配置为放大模式，而不是将晶体管P1和晶体管P2配置为放大模式。鉴于NMOS管沟道中载流子是电子，而PMOS管沟道中载流子是空穴，又因为电子的迁移率远大于空穴的迁移率，因此，采用晶体管N1和晶体管N2进行放大，可以提高产生失调补偿电压Vos的速度，进一步提高了存储器的性能。
S36.对所述寄生电容中的电荷与存储单元中的电荷进行电荷共享，生成待放大信号。
参考图6，在步骤S36对应的电荷共享阶段中，控制开关S1、开关S2、开关S3和开关S4均处于断开状态。
另外，控制晶体管P3和晶体管N3关断，将节点ACT和节点NLAT充电至预充电的电位(即VEQ)。
在存储单元响应字线的开启信号而读出电荷的情况下，寄生电容中的电荷可以与存储单元中的电荷进行电荷共享，从而生成待放大信号。应当理解的是，该待放大信号为小信号输入电压，输入到本公开的灵敏放大器中进行放大。
如图6所示，当字线WL2的控制信号由Vkk变为Vpp时，存储单元的晶体管开启，此时，存储于电容C2中的电荷会与位线BL的寄生电容CBL2的电荷进行电荷共享。
其中，Vkk是一个相对较低的电压，甚至可以是负电压，例如，-0.3～-0.1V。Vpp是一个相对较高的电压，例如，2.5～3.2V。
在存储单元中晶体管需要关断时，可以将WL2置为较低的电压，由此可以将该晶体管彻底关断，避免亚阈值泄露电流导致电容C2中的电荷泄露。在存储单元中晶体管需要开启时，可以将WL2置为较高的电压，由此，可以将该晶体管的导通阻抗减小，缩短读 出或写入信息所需的时间。
S38.对所述待放大信号进行放大并输出，以实现从所述存储单元中读取数据。
在本公开一个示例性实施方式中，对待放大信号进行放大的步骤可以包括以下两步：
第一步，参考图7，维持开关S1、开关S2、开关S3和开关S4的断开状态。控制晶体管P3导通，以将节点ACT与电源电压VDD连接；控制晶体管N3导通，以将节点NLAT接地。
在这种情况下，由于NODE1和NODE2并未与位线上的寄生电容CBL1或CBL2连接，使得待放大信号会被快速放大，节点NODE1和节点NODE2上的电压会快速分离。可以理解的是，该步骤的操作实现了节点NODE1和节点NODE2之间电压放大。
第二步，参考图8，维持节点ACT与电源电压连接以及节点NLAT接地的状态，控制开关S3和开关S4闭合，此时，第一位线BL与节点NODE1连接，第二位线BLB与节点NODE2连接，实现了对第一位线BL和第二位线BLB的回写。也就是说，实现了第一位线BL和第二位线上信号的分离、放大，以完成从所述存储单元中读取数据。
需要说明的是，可以将上述第一步称为预放大过程，将上述第二称为回写过程。另外，还可以省略上述第一步的过程，也就是说，直接将开关S3和开关S4闭合，以达到简化时序的目的。
另外，上述将开关S3和开关S4闭合的过程可以是缓慢闭合的过程。也就是说，可以通过控制开关S3和开关S4的控制端的电压，使得开关S3和开关S4的导通阻抗逐渐减小，而不是理想情况下的迅速闭合的过程。由此，避免了在开关S3和开关S4闭合时，由于位线寄生电容的接入，而使节点NODE1和节点NODE2之间已经区分的电压又变得接近，导致信号分离、放大的过程失败。通过缓慢闭合开关的操作，可以更快速更可靠地实现数据回写，增强了整个处理过程的鲁棒性。
图9示出了开关S3和开关S4的控制端电压的变化示意图。
以开关S3为一个NMOS晶体管为例，开关S3的控制端的电压为V CTRL，闭合操作开始时，V CTRL增大，当增大到开关S3的阈值电压V TH时，会在一段预设时间内保持V CTRL不变，然后，继续将V CTRL增大至VDD。类似地，开关S4也可以采用这种方式实现缓慢闭合。
需要说明的是，图9仅是示例性的描述，一方面，还可以在V TH附近保持一段预设时间，例如，在V TH±σ的范围内保持一段预设时间，其中，σ是一个较小的电压值。另一方面，还可以以曲线的形式缓慢增加V CTRL。本公开对使缓慢闭合开关S3和开关S4的过程不做限制。
图10示出了上述步骤S32至步骤S38对应的电路时序图。图10中的横坐标表示时间，纵坐标表示信号电平，并且以存储单元存储的数据“1”为例。
在时间间隔t 0-t 1中，对应于灵敏放大器的预充电阶段。在这种情况下，开关S1、开关S2、开关S3和开关S4均处于闭合状态(记为ON)。将节点ACT、节点NLAT、第一 位线BL、第二位线BLB充电至VEQ。
在时间间隔t 1-t 2中，对应于灵敏放大器的失调补偿阶段。在这种情况下，晶体管P1和晶体管P2被配置为二极管连接方式，晶体管N1和晶体管N2被配置为交叉耦合放大模式。具体的，可以维持开关S1和开关S2的闭合状态，将开关S3和开关S4断开(记为OFF)，并使节点ACT与电源电压VDD连接，使节点NLAT接地。
在时间间隔t 2-t 3中，对应于灵敏放大器的电荷共享阶段。在这种情况下，将开关S1和开关S2也断开，并将节点ACT和节点NLAT置为VEQ。另外，字线WL(例如，上述的WL2)由VKK变为VPP，读出存储单元的电荷。由此，产生了待放大的小信号。
在时间间隔t 3-t 4中，对应于灵敏放大器的预放大阶段。在这种情况下，晶体管P1和晶体管P2被配置为待放大信号接收模式，用于接收电荷共享阶段生成的待放大的小信号。具体的，可以维持开关S1、开关S2、开关S3和开关S4的断开状态，并使节点ACT与电源电压VDD连接，使节点NLAT接地。此时，节点NODE1和节点NODE2上的电压迅速分离并放大。
在时间间隔t 4-t 5中，对应于灵敏放大器的回写阶段。在这种情况下，晶体管P1和晶体管N1被配置为第一反相器，晶体管P2和晶体管N2被配置为第二反相器，其中，第一反相器和第二反相器又可被配置为锁存器模式。具体的，可以闭合开关S3和开关S4，其余配置不变。如上所述，闭合开关S3和开关S4的过程可以是缓慢闭合的过程。由此，实现了第一位线BL与第二位线BLB上电压的分离与放大，实现了数据的读出。
为了使上述预放大的过程更快速，本公开的另一个示例性实施方式中还提供了另一种灵敏放大器。
该灵敏放大器电路除包括上述晶体管及开关外，还可以包括第五开关和第六开关。
具体的，第五开关的第一端可以与第三开关的第二端连接，第五开关的第二端可以与第二位线BLB连接。第六开关的第一端可以与第四开关的第二端连接，第六开关的第二端可以与第一位线BL连接。
针对上述步骤S32至步骤S38的电路工作过程，在步骤S32、步骤S34和步骤S36中，第五开关和第六开关均处于闭合状态，处理过程类似，不再赘述。
针对上述步骤S38中预放大及回写的过程，图11示意性示出了包括第五开关和第六开关的灵敏放大器的电路图。可以将第五开关简称为开关S5，将第六开关简称为开关S6。另外，开关S5可以是PMOS管、NMOS管或CMOS传输门，开关S6可以是PMOS管、NMOS管或CMOS传输门。
对待放大信号进行放大的步骤也可以包括两步：
第一步，参考图11，控制开关S1、开关S2、开关S5和开关S6处于断开状态，控制开关S3和开关S4处于闭合状态。控制晶体管P3导通，以将节点ACT与电源电压VDD连接；控制晶体管N3导通，以将节点NLAT接地。
在这种情况下，晶体管P1和晶体管P2也被配置为放大模式，晶体管P1和晶体管 N1形成一个CMOS反向器，晶体管P2和晶体管N2也形成一个CMOS反向器，并且这两个反向器被配置为交叉耦合的锁存器形式，由于这样的配置方式可以获得最大的等效跨导，由此，提高了待放大信号的放大速度，缩短了信号读出的时间。
第二步，在回写阶段，仅需闭合开关S5和开关S6，即可实现第一位线BL与第二位线BLB上信号的分离、放大。
另外，闭合开关S5和开关S6的过程可以是缓慢闭合的过程。具体的，可以通过控制开关S5和开关S6的控制端的电压，使得开关S5和开关S6的导通阻抗逐渐减小。操作过程与上述缓慢闭合开关S3和开关S4的过程类似，在此不再赘述。
图12示出了包括开关S5和开关S6的灵敏放大器的时序图。
图12中时间间隔t 0-t 3对应的时序部分与图10所示的时间间隔t 0-t 3对应的时序部分相同，不再赘述。
在图12所示的时间间隔t 3-t 4中，对应于灵敏放大器的预放大阶段。在这种情况下，晶体管P1和晶体管N1被配置为第一反相器，晶体管P2和晶体管N2被配置为第二反相器，其中，第一反相器和第二反相器又可被配置为锁存器模式。
具体的，将开关S1、开关S2、开关S5和开关S6断开，将开关S3和开关S4闭合，并使节点ACT与电源电压VDD连接，使节点NLAT接地。此时，节点NODE1和节点NODE2上的电压迅速分离并放大，且速度比图10所示的速度更快(变化的斜率更大)，由此，进一步提高了存储器读取数据的速度，提升了存储器的性能。
在图12所示的时间间隔t 4-t 5中，对应于灵敏放大器的回写阶段。在这种情况下，闭合开关S5和开关S6，其余配置不变。由此，实现了第一位线BL与第二位线BLB上电压的分离与放大，实现了数据的读出。
基于本公开示例性实施方式的灵敏放大器及利用该灵敏放大器实现的数据读出过程，可以实现灵敏放大器的失调补偿，解决了由于各晶体管的差异而可能导致读出数据错误的问题，提高了存储器的性能。
进一步的，本公开还提供了一种存储器，该存储器包括上述灵敏放大器。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。

Claims (21)

  1. 一种灵敏放大器，包括：
    第一PMOS管，所述第一PMOS管的栅极与第一位线连接；
    第二PMOS管，所述第二PMOS管的栅极与第二位线连接，所述第二PMOS管的源极与所述第一PMOS管的源极连接；其中，所述第二位线是与所述第一位线对应的反位线；
    第一NMOS管，所述第一NMOS管的栅极与所述第二PMOS管的漏极连接，所述第一NMOS管的漏极与所述第一PMOS管的漏极连接；
    第二NMOS管，所述第二NMOS管的栅极与所述第一PMOS管的漏极连接，所述第二NMOS管的漏极与所述第二PMOS管的漏极连接，所述第二NMOS管的源极与所述第一NMOS管的源极连接；
    其中，在所述灵敏放大器的失调补偿阶段，所述第一PMOS管和所述第二PMOS管被配置为二极管连接模式，所述第一NMOS管和所述第二NMOS管被配置为交叉耦合放大模式。
  2. 根据权利要求1所述的灵敏放大器，其中，在所述灵敏放大器的预放大阶段，所述第一PMOS管和所述第二PMOS管被配置为待放大信号接收模式，用于接收待放大信号，所述待放大信号由所述第一位线或所述第二位线的寄生电容中的电荷与对应的存储单元中的电荷进行电荷共享而生成；以及
    所述第一NMOS管和所述第二NMOS管被配置为交叉耦合放大模式。
  3. 根据权利要求2所述的灵敏放大器，其中，在所述灵敏放大器的回写阶段，所述第一PMOS管和所述第一NMOS管被配置为第一反相器，所述第二PMOS管和所述第二NMOS管被配置为第二反相器；
    其中，所述第一反相器和所述第二反相器被配置为锁存器模式。
  4. 根据权利要求3所述的灵敏放大器，其中，所述灵敏放大器还包括：
    第一开关，所述第一开关的第一端与所述第一PMOS管的漏极连接，所述第一开关的第二端与所述第一PMOS管的栅极连接；
    第二开关，所述第二开关的第一端与所述第二PMOS管的漏极连接，所述第二开关的第二端与所述第二PMOS管的栅极连接；
    第三开关，所述第三开关的第一端与所述第一开关的第一端连接，所述第三开关的第二端与所述第二开关的第二端连接；
    第四开关，所述第四开关的第一端与所述第二开关的第一端连接，所述第四开关的第二端与所述第一开关的第二端连接。
  5. 根据权利要求4所述的灵敏放大器，其中，在所述灵敏放大器的失调补偿阶段，所述第一开关和所述第二开关闭合，所述第三开关和所述第四开关断开；
    在所述灵敏放大器的预放大阶段，所述第一开关、所述第二开关、所述第三开关和所述第四开关均断开；
    在所述灵敏放大器的回写阶段，所述第一开关和所述第二开关断开，所述第三开关和所述第四开关闭合。
  6. 根据权利要求4所述的灵敏放大器，其中，所述灵敏放大器还包括：
    上拉单元，用于响应上拉控制信号将所述第一PMOS管的源极与电源电压连接；
    下拉单元，用于响应下拉控制信号将所述第一NMOS管的源极接地。
  7. 根据权利要求6所述的灵敏放大器，其中，所述上拉单元包括上拉PMOS管，所述上拉PMOS管的栅极接收所述上拉控制信号，所述上拉PMOS管的源极与所述电源电压连接，所述上拉PMOS管的漏极与所述第一PMOS管的源极连接；
    所述下拉单元包括下拉NMOS管，所述下拉NMOS管的栅极接收所述下拉控制信号，所述下拉NMOS管的源极接地，所述下拉NMOS管的漏极与所述第一NMOS管的源极连接。
  8. 根据权利要求4所述的灵敏放大器，其中，所述灵敏放大器还包括：
    第一预充电单元，用于响应预充电控制信号，以在所述第一开关、所述第二开关、所述第三开关、所述第四开关均闭合的情况下，对所述第一PMOS管的源极和所述第一NMOS管的源极进行预充电；
    第二预充电单元，用于响应所述预充电控制信号，以在所述第一开关、所述第二开关、所述第三开关、所述第四开关均闭合的情况下，对所述第一位线和所述第二位线进行预充电。
  9. 根据权利要求4所述的灵敏放大器，其中，所述灵敏放大器还包括：
    开关控制单元，用于响应控制信号，对所述第一开关、所述第二开关、所述第三开关和所述第四开关的开关状态进行控制。
  10. 根据权利要求4至9中任一项所述的灵敏放大器，其中，所述灵敏放大器还包括：
    第五开关，所述第五开关的第一端与所述第三开关的第二端连接，所述第五开关的第二端与所述第二位线连接；
    第六开关，所述第六开关的第一端与所述第四开关的第二端连接，所述第六开关的第二端与所述第一位线连接。
  11. 根据权利要求10所述的灵敏放大器，其中，所述第一开关的类型为PMOS管、NMOS管或CMOS传输门；
    所述第二开关的类型为PMOS管、NMOS管或CMOS传输门；
    所述第三开关的类型为PMOS管、NMOS管或CMOS传输门；
    所述第四开关的类型为PMOS管、NMOS管或CMOS传输门；
    所述第五开关的类型为PMOS管、NMOS管或CMOS传输门；
    所述第六开关的类型为PMOS管、NMOS管或CMOS传输门。
  12. 一种存储器，包括如权利要求1至11中任一项所述的灵敏放大器。
  13. 一种数据读出方法，应用于如权利要求4至9中任一项所述的灵敏放大器；其中，所述数据读出方法包括：
    对所述灵敏放大器进行预充电；
    确定所述灵敏放大器的失调补偿电压，并存储于位线的寄生电容，以对所述灵敏放大器进行失调补偿；
    对所述寄生电容中的电荷与存储单元中的电荷进行电荷共享，生成待放大信号；
    对所述待放大信号进行放大并输出，以实现从所述存储单元中读取数据。
  14. 根据权利要求13所述的数据读出方法，其中，对所述灵敏放大器进行预充电的操作包括：
    控制所述第一开关、所述第二开关、所述第三开关和所述第四开关处于闭合状态，对所述第一位线、所述第二位线、所述第一PMOS管的源极和所述第一NMOS管的源极进行预充电。
  15. 根据权利要求13所述的数据读出方法，其中，将所述灵敏放大器的失调补偿电压存储于位线的寄生电容的操作包括：
    控制所述第一开关、所述第二开关处于闭合状态；
    控制所述第三开关、所述第四开关处于断开状态；
    控制所述第一PMOS管的源极与电源电压连接；
    控制所述第一NMOS管的源极接地。
  16. 根据权利要求13所述的数据读出方法，其中，对所述寄生电容中的电荷与存储单元中的电荷进行电荷共享的操作包括：
    控制所述第一PMOS管的源极和所述第一NMOS管的源极充电至预充电的电位；
    控制所述第一开关、所述第二开关、所述第三开关、所述第四开关处于断开状态；
    其中，在所述存储单元响应字线的开启信号而读出电荷的情况下，所述寄生电容中的电荷与所述存储单元中的电荷进行电荷共享。
  17. 根据权利要求13所述的数据读出方法，其中，对所述待放大信号进行放大并输出的操作包括：
    第一步，控制所述第一PMOS管的源极与电源电压连接，控制所述第一NMOS管的源极接地，控制所述第一开关、所述第二开关、所述第三开关、所述第四开关处于断开状态；
    第二步，控制所述第三开关和所述第四开关处于闭合状态。
  18. 根据权利要求13所述的数据读出方法，其中，对所述待放大信号进行放大并输出的操作包括：
    控制所述第一PMOS管的源极与电源电压连接，控制所述第一NMOS管的源极接地；
    控制所述第一开关和所述第二开关处于断开状态，控制所述第三开关和所述第四开关 处于闭合状态。
  19. 根据权利要求17或18所述的数据读出方法，其中，控制所述第三开关和所述第四开关处于闭合状态包括：
    控制所述第三开关和所述第四开关的控制端的电压，使所述第三开关和所述第四开关的导通阻抗逐渐减小。
  20. 根据权利要求13所述的数据读出方法，其中，所述灵敏放大器还包括第五开关和第六开关，所述第五开关的第一端与第三开关的第二端连接，所述第五开关的第二端与第二位线连接，所述第六开关的第一端与第四开关的第二端连接，所述第六开关的第二端与第一位线连接；其中，对所述待放大信号进行放大并输出的操作包括：
    第一步，控制所述第一PMOS管的源极与电源电压连接，控制所述第一NMOS管的源极接地，控制所述第一开关、所述第二开关、所述第五开关和所述第六开关处于断开状态，控制所述第三开关和所述第四开关处于闭合状态；
    第二步，控制所述第五开关和所述第六开关处于闭合状态。
  21. 根据权利要求20所述的数据读出方法，其中，控制所述第五开关和所述第六开关处于闭合状态包括：
    控制所述第五开关和所述第六开关的控制端的电压，使所述第五开关和所述第六开关的导通阻抗逐渐减小。
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