WO2022048073A1 - 灵敏放大器、存储器和灵敏放大器的控制方法 - Google Patents

灵敏放大器、存储器和灵敏放大器的控制方法 Download PDF

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Publication number
WO2022048073A1
WO2022048073A1 PCT/CN2020/139652 CN2020139652W WO2022048073A1 WO 2022048073 A1 WO2022048073 A1 WO 2022048073A1 CN 2020139652 W CN2020139652 W CN 2020139652W WO 2022048073 A1 WO2022048073 A1 WO 2022048073A1
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Prior art keywords
switch
sense amplifier
bit line
transistor
stage
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PCT/CN2020/139652
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English (en)
French (fr)
Inventor
蔺智挺
李剑卿
何军
应战
李新
曹堪宇
卢文娟
彭春雨
吴秀龙
陈军宁
Original Assignee
安徽大学
长鑫存储技术有限公司
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Application filed by 安徽大学, 长鑫存储技术有限公司 filed Critical 安徽大学
Priority to US17/474,166 priority Critical patent/US11862285B2/en
Publication of WO2022048073A1 publication Critical patent/WO2022048073A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof

Definitions

  • the present disclosure relates to the technical field of semiconductor memory, and in particular, to a sense amplifier, a memory and a control method of the sense amplifier.
  • DRAM Dynamic Random Access Memory, dynamic random access memory
  • SRAM Static Random-Access Memory, static random access memory
  • each bit line in a different array of memory cells is connected in pairs to a sense amplifier having one bit line BL (read bit line) input and one bit line BLB (reference bit line) input.
  • the function of the sense amplifier is to read the voltage difference between the bit line BL and the reference bit line BLB, and amplify the voltage difference between the two bit lines.
  • the purpose of the present disclosure is to provide a sense amplifier, a memory and a control method for the sense amplifier, thereby at least to a certain extent overcome the problem of errors in data read by the sense amplifier.
  • a sense amplifier comprising: an amplifying module for reading data in a storage unit on a first bit line or a second bit line; a control module, electrically connected to the amplifying module; wherein, In the case of reading the data in the memory cell on the first bit line, in the first amplification stage of the sense amplifier, the control module is configured to configure the amplification module to include a first current mirror structure, and mirror the first current mirror structure The terminal is connected to the second bit line; in the case of reading the data in the storage unit on the second bit line, in the first amplification stage of the sense amplifier, the control module is used to configure the amplification module to include the second current mirror structure, and The mirror end of the second current mirror structure is connected to the first bit line.
  • the amplifying module includes: a first PMOS transistor; a second PMOS transistor; a first NMOS transistor, the gate of the first NMOS transistor is connected to the second bit line, and the drain of the first NMOS transistor is connected to the The drain of a PMOS transistor is connected; the second NMOS transistor, the gate of the second NMOS transistor is connected to the first line, and the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor through the second node; wherein, In the case of reading the data in the storage unit on the first bit line, in the first amplification stage of the sense amplifier, the control module is used to configure the first PMOS transistor and the second PMOS transistor into a first current mirror structure, and the first The two-bit line is connected to the second node; in the case of reading the data in the storage unit on the second bit line, in the first amplification stage of the sense amplifier, the control module is used to configure the first PMOS transistor and the second PMOS transistor as The second current mirror structure connects the first
  • control module further includes: a first switch, the first end of the first switch is connected to the gate of the first PMOS transistor, the second end of the first switch is connected to the gate of the second PMOS transistor; the second switch , the first end of the second switch is connected to the gate of the second PMOS transistor, the second end of the second switch is connected to the first node; the third switch, the first end of the third switch is connected to the second node, the third The second end of the switch is connected to the gate of the first PMOS transistor; the fourth switch, the first end of the fourth switch is connected to the second node, the second end of the fourth switch is connected to the second bit line; the fifth switch, The first end of the fifth switch is connected to the first bit line, and the second end of the fifth switch is connected to the first node; wherein, in the case of reading the data in the storage unit on the first bit line, the first end of the sense amplifier is In an amplification stage, the first switch, the second switch and the fourth switch are closed, and the third switch and the fifth
  • the sources of the first PMOS transistor and the second PMOS transistor receive the first voltage, and the sources of the first NMOS transistor and the second NMOS transistor are grounded.
  • the control module in the case of reading the data in the storage unit on the first bit line, in the offset compensation stage of the sense amplifier, the control module is used to configure the amplifying module to include a first current mirror structure and a first diode structure ; In the case of reading the data in the memory cell on the second bit line, in the offset compensation stage of the sense amplifier, the control module is used to configure the amplifying module to include a second current mirror structure and a second diode structure.
  • control module further includes: a sixth switch, a first end of the sixth switch is connected to the first node, and a second end of the sixth switch is connected to the second bit line; a seventh switch, the first end of the seventh switch is connected The terminal is connected to the first bit line, and the second terminal of the seventh switch is connected to the second node; wherein, in the first amplification stage of the sense amplifier, the sixth switch and the seventh switch are disconnected; on the read first bit line In the case of data in the storage unit, in the offset compensation stage of the sense amplifier, the sixth switch is turned off, and the seventh switch is closed; in the case of reading the data in the memory cell on the second bit line, in the offset compensation stage of the sense amplifier , the sixth switch is closed, and the seventh switch is open.
  • the sources of the first PMOS transistor and the second PMOS transistor receive the first voltage, and the sources of the first NMOS transistor and the second NMOS transistor are grounded.
  • control module is configured to configure the amplification module as a cross-coupled amplification structure.
  • the first switch, the sixth switch and the seventh switch are turned off, and the second switch, the third switch, the fourth switch and the fifth switch are turned on.
  • the sources of the first PMOS transistor and the second PMOS transistor receive the first voltage, and the sources of the first NMOS transistor and the second NMOS transistor are grounded.
  • a sensing stage of the sense amplifier is also included; in the case of reading the data in the storage unit on the first bit line, in the sensing stage of the sense amplifier, The first switch and the second switch are closed, and the third switch, the fourth switch, the fifth switch, the sixth switch and the seventh switch are open; in the case of reading the data in the storage unit on the second bit line, in the sense amplifier In the induction stage, the first switch and the third switch are closed, and the second switch, the fourth switch, the fifth switch, the sixth switch and the seventh switch are open.
  • the sense amplifier further includes: a precharge module, configured to precharge the first bit line and the second bit line in a precharge stage before the offset compensation stage of the sense amplifier.
  • a precharge module configured to precharge the first bit line and the second bit line in a precharge stage before the offset compensation stage of the sense amplifier.
  • the sources of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second PMOS transistor all receive the second voltage.
  • a memory including the sense amplifier as described above.
  • a control method for a sense amplifier includes an amplification module and a control module
  • the control method for the sense amplifier includes: in the case of reading data in a storage unit on a first bit line, in the In the first amplification stage of the sense amplifier, the control module is used to configure the amplification module to include a first current mirror structure, and the mirror end of the first current mirror structure is connected to the second bit line; the storage unit is read on the second bit line
  • the control module is used to configure the amplification module to include a second current mirror structure, and the mirror end of the second current mirror structure is connected to the first bit line.
  • the amplification module in the case of reading the data in the storage unit on the first bit line, in the first amplification stage of the sense amplifier, is configured as It includes a first current mirror structure, and connects the mirror end of the first current mirror structure with the second bit line; in the case of reading the data in the storage unit on the second bit line, in the first amplification stage of the sense amplifier, the The amplifying module is configured to include a second current mirror structure, and the mirror end of the second current mirror structure is connected to the first bit line.
  • the non-read bit line voltage can be pre-amplified in the opposite direction in the first amplification stage, so as to ensure that in the second amplification stage, the voltage on the first bit line and the second bit line voltage can be effectively distinguished and amplified Line voltage, improve the accuracy of data reading, and then improve the performance of semiconductor memory.
  • FIG. 1 schematically shows a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure
  • FIG. 2 schematically shows a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure
  • FIG. 3 schematically shows a circuit diagram of a specific configuration of a sense amplifier according to an embodiment of the present disclosure
  • FIG. 5 schematically shows a circuit diagram of a sense amplifier in a precharge stage when reading data in a memory cell on a first bit line according to an embodiment of the present disclosure
  • FIG. 6 schematically shows a circuit diagram of a sense amplifier in an offset compensation stage when reading data in a memory cell on a first bit line according to an embodiment of the present disclosure
  • FIG. 7 schematically shows a circuit diagram of a sense amplifier in a sensing stage when reading data in a memory cell on a first bit line according to an embodiment of the present disclosure
  • FIG. 8 schematically shows a circuit diagram of a sense amplifier in a first amplification stage when reading data in a memory cell on a first bit line according to an embodiment of the present disclosure
  • FIG. 9 schematically shows a circuit diagram of a sense amplifier in a second amplifying stage when reading data in a memory cell on a first bit line according to an embodiment of the present disclosure
  • FIG. 11 schematically shows a circuit diagram of a sense amplifier in a precharge stage when reading data in a memory cell on the second bit line according to an embodiment of the present disclosure
  • FIG. 12 schematically shows a circuit diagram of a sense amplifier in an offset compensation stage when reading data in a memory cell on the second bit line according to an embodiment of the present disclosure
  • FIG. 13 schematically shows a circuit diagram of a sense amplifier in a sensing stage when reading data in a memory cell on the second bit line according to an embodiment of the present disclosure
  • FIG. 14 schematically shows a circuit diagram of a sense amplifier in a first amplifying stage when reading data in a memory cell on a second bit line according to an embodiment of the present disclosure
  • FIG. 15 schematically shows a circuit diagram of a sense amplifier in a second amplification stage when reading data in a memory cell on a second bit line according to an embodiment of the present disclosure
  • FIG. 16 schematically shows a flowchart of a control method of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • the present disclosure provides a new sense amplifier.
  • FIG. 1 schematically shows a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • the sense amplifier 1 may include an amplification module 11 and a control module 12 .
  • the amplifying module 11 can be used to read the data of the storage unit on the first bit line or the second bit line;
  • the control module 12 is electrically connected to the amplification module 11 .
  • control module 12 is configured to configure the amplification module 11 to include a first current mirror structure, and the first current mirror The mirrored end of the structure is connected to the second bit line.
  • control module 12 is configured to configure the amplification module 11 to include a second current mirror structure, and the second current mirror The mirrored end of the structure is connected to the first bit line.
  • the current mirror structure can include a source terminal and a mirror terminal.
  • the source terminal can be the terminal corresponding to the diode connection mode in the current mirror structure, or it can be understood as the source terminal directly connected to the diode Structural connection.
  • the mirror end may be the end corresponding to the non-diode connection in the current mirror structure, or it may be understood that the mirror end is not directly connected to the diode structure.
  • first current mirror structure and the second current mirror structure differ at least in circuit configuration.
  • the non-read bit line voltage can be pre-amplified in the opposite direction in the first amplification stage, so as to ensure that in the second amplification stage, the voltage on the first bit line and the second bit line voltage can be effectively distinguished and amplified Line voltage, improve the accuracy of data reading, and then improve the performance of semiconductor memory.
  • the amplifying module 11 may include a first PMOS transistor (hereinafter referred to as transistor P1), a second PMOS transistor (hereinafter referred to as transistor P2), a first NMOS transistor (hereinafter referred to as transistor N1), and a second NMOS transistor (hereinafter referred to as transistor N2).
  • the offset noise may be the offset voltage of the transistor P1 and the transistor P2, the offset voltage of the transistor N1 and the transistor N2, or the combined offset voltage of the two, which is not limited in the present disclosure .
  • FIG. 2 schematically shows a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • the working stage of the sense amplifier of the exemplary embodiment of the present disclosure may be divided into a precharging stage, an offset compensation stage, a first amplifying stage, and a second amplifying stage.
  • an induction stage (or voltage induction stage) may also be included.
  • the transistors P1 and P2 are configured as a first current mirror structure, and the second bit line BLB is connected with the second Node nR connection.
  • the transistors P1 and P2 are configured as a second current mirror structure, and the first bit line BL is connected to the first Node nL connection.
  • the control module may include a first switch (hereinafter referred to as switch K1), a second switch (hereinafter referred to as switch K2), a third switch (hereinafter referred to as switch K3), a fourth switch (hereinafter referred to as switch K4) and a fifth switch switch (hereinafter referred to as switch K5).
  • switch K1 a first switch
  • switch K2 a second switch
  • switch K3 a third switch
  • switch K4 hereinafter referred to as switch K4
  • switch K5 a fifth switch switch switch
  • the first end of the switch K1 is connected to the gate of the transistor P1, the second end of the switch K1 is connected to the gate of the transistor P2; the first end of the switch K2 is connected to the gate of the transistor P2, and the second end of the switch K2 is connected to the gate of the transistor P2.
  • a node nL is connected; the first end of the switch K3 is connected to the second node nR, the second end of the switch K3 is connected to the gate of the transistor P1; the first end of the switch K4 is connected to the second node nR, and the second end of the switch K4 is connected to the second node nR.
  • the terminal is connected to the second bit line BLB; the first terminal of the switch K5 is connected to the first bit line BL, and the second terminal of the switch K5 is connected to the first node nL.
  • the switch K1, the switch K2 and the switch K4 are closed, and the switch K3 and the switch K5 are opened.
  • the switch K1 In the case of reading the data in the memory cell on the second bit line BLB, in the first amplification stage of the sense amplifier, the switch K1, the switch K3 and the switch K5 are closed, and the switch K2 and the switch K4 are opened.
  • the transistor P1 and the transistor P2 form a first current mirror. structure
  • the source end of the first current mirror structure may be the first node nL
  • the mirror end of the first current mirror structure may be the second node nR.
  • the transistor P1 and the transistor P2 form a second current mirror structure
  • the second current The source end of the mirror structure may be the second node nR
  • the mirror end of the second current mirror structure may be the first node nL.
  • the present disclosure does not limit the types of switch K1 , switch K2 , switch K3 , switch K4 and switch K5 .
  • the switch K1 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K2 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K3 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K4 can be a PMOS transistor , NMOS tube or CMOS transmission gate
  • switch K5 can be PMOS tube, NMOS tube or CMOS transmission gate.
  • the switch K1 may include a control terminal for controlling the switch state of the switch K1 in response to a first control signal (referred to as control signal S1 ); the switch K2 may also include a control terminal for responding to the second control signal
  • the control signal (denoted as control signal S2) controls the switch state of switch K2;
  • switch K3 may also include a control terminal for controlling the switch state of switch K3 in response to the third control signal (denoted as control signal S3);
  • switch K4 may also include The control terminal is used to control the switch state of the switch K4 in response to the fourth control signal (referred to as the control signal S4);
  • the switch K5 may also include a control terminal, used to control the switching state of the switch K5 in response to the fifth control signal (referred to as the control signal S5). switch status.
  • the source of transistor P1 may receive control signal ACT1
  • the source of transistor P2 may receive control signal ACT2
  • the source of transistor N1 may receive control signal NLAT1
  • the source of transistor N2 may receive control signal NLAT2.
  • the source of the transistor P1 and the source of the transistor P2 may be connected, that is, the control signal ACT1 and the control signal ACT2 are the same.
  • the source of the transistor N1 and the source of the transistor N2 can be connected, that is, the control signal NLAT1 and the control signal NLAT2 are the same.
  • the sources of the transistors P1 and P2 both receive a first voltage, where the first voltage may be the power supply voltage VCC. That is, at this stage, both the control signal ACT1 and the control signal ACT2 are configured as the first voltage.
  • the sources of the transistor N1 and the transistor N2 are grounded (GND), that is, the voltages received by the control signal NLAT1 and the control signal NLAT2 are zero.
  • control module is configured to configure the amplification module to include the above-mentioned first current mirror structure and first diode structure.
  • control module is configured to configure the amplifying module to include the above-mentioned second current mirror structure and second diode structure.
  • the second diode structure differs from the first diode structure at least in circuit configuration.
  • the transistor N2 may be configured as the first diode structure
  • the transistor N1 may be configured as the second diode structure.
  • the sense amplifier of the present disclosure may further include a sixth switch (hereinafter referred to as switch K6 ) and a seventh switch (hereinafter referred to as switch K7 ).
  • switch K6 a sixth switch
  • switch K7 a seventh switch
  • the first end of the switch K6 is connected to the first node nL, the second end of the switch K6 is connected to the second bit line BLB; the first end of the switch K7 is connected to the first bit line BL, and the second end of the switch K7 is connected to the second bit line BLB. Node nR connection.
  • the present disclosure does not limit the types of switch K6 and switch K7.
  • the switch K6 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K7 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate.
  • the switch K6 may include a control terminal for controlling the switch state of the switch K6 in response to a sixth control signal (referred to as a control signal S6 ); the switch K7 may also include a control terminal for responding to the seventh control signal
  • the control signal (referred to as control signal S7) controls the switching state of the switch K7.
  • switch K6 and switch K7 are turned off.
  • the switch K6 In the case of reading the data in the memory cell on the first bit line BL, in the offset compensation stage of the sense amplifier, the switch K6 is turned off and the switch K7 is turned on; in the case of reading the data in the memory cell on the second bit line BLB , in the offset compensation stage of the sense amplifier, the switch K6 is closed and the switch K7 is opened.
  • the sources of the transistors P1 and P2 receive the first voltage, and the sources of the transistors N1 and N2 are grounded.
  • control module is further configured to configure the amplification module as a cross-coupled amplification structure.
  • the switch K1, the switch K6 and the switch K7 are turned off, and the switch K2, the switch K3, the switch K4 and the switch K5 are turned on.
  • the sources of the transistor P1 and the transistor P2 receive the first voltage, that is, the control signal ACT1 and the control signal ACT2 are VCC.
  • the sources of the transistor N1 and the transistor N2 are grounded, that is, the control signal NLAT1 and the control signal NLAT2 are 0.
  • a sensing stage of the sense amplifier is further included.
  • the switch K1 and the switch K2 are closed, and the switch K3, the switch K4, the switch K5, the switch K6 and the switch K7 are open.
  • the sense amplifier further includes a precharge module for precharging the first bit line BL and the second bit line BLB in a precharge stage before the offset compensation stage of the sense amplifier.
  • the sources of transistor P1, transistor P2, transistor N1 and transistor N2 all receive the second voltage.
  • the second voltage is smaller than the first voltage.
  • the second voltage may be VCC/2.
  • the switch K1, the switch K2, the switch K3, the switch K4, the switch K5, the switch K6, and the switch K7 may be in a closed state, which is not limited in the present disclosure.
  • FIG. 3 schematically shows a circuit diagram of a sense amplifier according to an embodiment of the present disclosure.
  • the switch K1 is configured as a transistor N3 to control the switch state in response to the control signal S1; the switch K2 is configured as a transistor N4 to control the switch state in response to the control signal S2; the switch K3 is configured as a transistor N5, which controls the switch state in response to the control signal S3; the switch K4 is configured as a transistor N6, which controls the switch state in response to the control signal S4; the switch K5 is configured as a transistor N7, which controls the switch state in response to the control signal S5; the switch K6 is configured as The transistor N8 controls the switch state in response to the control signal S6; the switch K7 is configured as a transistor N9 and controls the switch state in response to the control signal S7.
  • the precharge module may include a transistor N10, a transistor N11 and a transistor N12.
  • the gates of the transistor N10, the transistor N11 and the transistor N12 may all receive the precharge control signal BLP.
  • the source of the transistor N10 is connected to the first bit line BL, the drain of the transistor N10 is connected to the second bit line BLB; the source of the transistor N11 is connected to the second bit line BLB, and the drain of the transistor N11 is connected to the source of the transistor N12 connected to the precharge voltage Veq, wherein the precharge voltage Veq can be configured as VCC/2; the drain of the transistor N12 is connected to the first bit line BL.
  • the memory cell corresponding to the first bit line BL is configured to include a transistor N13 and a capacitor C1, and the transistor N13 controls the switching state in response to the word line control signal WL;
  • the memory cell corresponding to the second bit line BLB is configured to include a transistor N14 and a capacitor C2, the transistor N14 controls the switch state in response to the word line control signal WLB.
  • FIG. 4 schematically shows a timing diagram of various control signals involved in the sense amplifier when reading data in the memory cells on the first bit line BL according to an embodiment of the present disclosure.
  • FIG. 5 is directed to the precharge phase of the sense amplifier when reading data in the memory cells on the first bit line BL.
  • the precharge control signal BLP and the control signal S2 are at a high level, and the other control signals are at a low level.
  • transistor N10, transistor N11, transistor N12, and transistor N4 are turned on (corresponding to the closed state of the switch), and transistor N3, transistor N5, transistor N6, transistor N7, transistor N8, and transistor N9 are turned off (corresponding to the off state of the switch). ).
  • the first bit line BL and the second bit line BLB are connected to the precharge voltage Veq through the transistor N11 and the transistor N12, respectively, and are connected to each other through the transistor N10, so that the first bit line BL and the second bit line BLB is precharged to Veq.
  • the transistors N3, N4, N5, N6, N7, N8 and N9 One or more of them may be in a conducting state, which is not limited in the present disclosure.
  • FIG. 6 is directed to the offset compensation stage of the sense amplifier when reading data in the memory cells on the first bit line BL.
  • the control signal S1 , the control signal S2 and the control signal S7 are at a high level, and the other control signals are at a low level.
  • the transistor N3, the transistor N4 and the transistor N9 are turned on, and the transistor N5, the transistor N6, the transistor N7 and the transistor N8 are turned off.
  • the precharge voltage enters the sense amplifier through transistor N9, and based on the current mirror structure composed of transistor P1 and transistor P2, the current on the branch composed of transistor P1 and transistor N1 is the same as that composed of transistor P2 and transistor N2.
  • the currents on the branches are equal, thereby mitigating the effects of offset noise on the circuit.
  • FIG. 7 is directed to the sensing phase of the sense amplifier when reading data in the memory cells on the first bit line BL.
  • the control signal S1 and the control signal S2 are at high level, and the transistor N3 and the transistor N4 are turned on.
  • the induction phase the charge situation on the above two branches is stabilized.
  • the sense amplifier's operating phase may have no sensing phase. That is to say, after the offset compensation stage, the first amplification stage can be directly entered.
  • FIG. 8 is directed to the first amplification stage of the sense amplifier when reading data in the memory cells on the first bit line BL.
  • the control signal S1, the control signal S2, and the control signal S4 are at a high level, and the word line control signal WL is in an on state.
  • the transistor N3, the transistor N4 and the transistor N6 are turned on, and the transistor N5, the transistor N7, the transistor N8 and the transistor N9 are turned off.
  • the gate voltage of the transistor N2 increases, the conduction capability increases, the drain voltage decreases, and the drain is connected to the second bit line BLB, so the second bit line BLB is on the voltage drop.
  • the purpose of controlling the non-reading bit line voltage to be pre-amplified in the opposite direction is achieved, and the voltage difference between the first bit line BL and the second bit line BLB is increased, which is helpful for further amplifying the voltages of the two. Process.
  • the gate voltage of the transistor N2 is lowered, in this case the drain voltage is raised, that is, the voltage of the second bit line BLB is pulled up. Therefore, the purpose of increasing the voltage difference between the first bit line BL and the second bit line BLB is also achieved, which is helpful for the subsequent process of further amplifying the voltages of the two.
  • FIG. 9 is directed to the second amplification stage of the sense amplifier when reading data in the memory cells on the first bit line BL.
  • the control signal S2, the control signal S3, the control signal S4, and the control signal S5 are at a high level.
  • the transistor N4, the transistor N5, the transistor N6 and the transistor N7 are turned on, and the transistor N3, the transistor N8 and the transistor N9 are turned off.
  • the transistor P1, the transistor P2, the transistor N1 and the transistor N2 constitute a cross-coupled amplification structure.
  • the voltage on the first bit line BL is higher than the voltage on the second bit line BLB.
  • the transistor N2 and the transistor N6 are turned on, which can turn the second bit line BLB
  • the voltage on is discharged to ground (GND) through transistor N2.
  • the transistor P1 is turned on, which can raise the voltage on the first bit line BL to VCC.
  • the voltage on the first bit line BL is lower than the voltage on the second bit line BLB.
  • the transistor N1 and the transistor N7 are turned on, and the first bit line BL can be turned on.
  • the voltage on is discharged to ground (GND) through transistor N1.
  • the transistor P2 is turned on, which can raise the voltage on the second bit line BLB to VCC.
  • FIG. 10 schematically shows a timing diagram of various control signals involved in the sense amplifier when reading data in the memory cells on the second bit line BLB according to an embodiment of the present disclosure.
  • FIG. 11 is directed to the precharge phase of the sense amplifier when reading data in the memory cells on the second bit line BLB.
  • the precharge control signal BLP and the control signal S3 are at a high level, and the other control signals are at a low level.
  • the transistor N10, the transistor N11, the transistor N12, and the transistor N5 are turned on, and the transistor N3, the transistor N4, the transistor N6, the transistor N7, the transistor N8, and the transistor N9 are turned off.
  • the transistors N3, N4, N5, N6, N7, N8 and N9 One or more of them may be in an off state, which is not limited by the present disclosure.
  • control signal S1 is directed to the offset compensation stage of the sense amplifier when reading data in the memory cells on the second bit line BLB.
  • the control signal S1, the control signal S3 and the control signal S6 are at high level, and the other control signals are at low level.
  • the transistor N3, the transistor N5 and the transistor N8 are turned on, and the transistor N4, the transistor N6, the transistor N7 and the transistor N9 are turned off.
  • the precharge voltage enters the sense amplifier through transistor N8, and based on the current mirror structure composed of transistor P1 and transistor P2, the current on the branch composed of transistor P1 and transistor N1 is the same as that composed of transistor P2 and transistor N2.
  • the currents on the branches are equal, thereby mitigating the effects of offset noise on the circuit.
  • circuit configuration shown in FIG. 6 can also be used to implement offset compensation, which is not limited in the present disclosure.
  • the sense amplifier's operating phase may have no sensing phase. That is to say, after the offset compensation stage, the first amplification stage can be directly entered.
  • FIG. 14 is directed to the first amplification stage of the sense amplifier when reading data in the memory cells on the second bit line BLB.
  • the control signal S1, the control signal S3, and the control signal S5 are at a high level, and the word line control signal WLB is in an on state.
  • the transistor N3, the transistor N5 and the transistor N7 are turned on, and the transistor N4, the transistor N6, the transistor N8 and the transistor N9 are turned off.
  • the gate voltage of the transistor N1 increases, the conduction capability increases, the drain voltage decreases, and the drain is connected to the first bit line BL, so the first bit line BL is on the voltage drop.
  • the purpose of controlling the non-reading bit line voltage to be pre-amplified in the opposite direction is achieved, and the voltage difference between the first bit line BL and the second bit line BLB is increased, which is helpful for further amplifying the voltages of the two. Process.
  • the gate voltage of the transistor N1 is lowered, in this case the drain voltage is raised, that is, the voltage of the first bit line BL is pulled high. Therefore, the purpose of increasing the voltage difference between the first bit line BL and the second bit line BLB is also achieved, which is helpful for the subsequent process of further amplifying the voltages of the two.
  • FIG. 15 is directed to the second amplification stage of the sense amplifier when reading data in the memory cells on the second bit line BLB.
  • the second enlargement stage of FIG. 15 is the same as the process of FIG. 9 described above, and will not be repeated here.
  • the present disclosure also provides a control method for a sense amplifier.
  • control method of the sense amplifier may include the following steps:
  • the amplifying module in the case of reading data in the memory cells on the first bit line, in the offset compensation stage of the sense amplifier, is configured by the control module to include the first current mirror structure and the first diode structure; in the case of reading the data in the memory cell on the second bit line, in the offset compensation stage of the sense amplifier, the control module is used to configure the amplifying module to include a second current mirror structure and a second diode structure .
  • the amplification module in the second amplification stage after the first amplification stage of the sense amplifier, is configured as a cross-coupled amplification structure by the control module.
  • the sense amplifier may further include a pre-charging stage and a sensing stage, the details of which have been explained in the process of describing the configuration of the sense amplifier above, and will not be repeated here.
  • the non-read bit line voltage can be pre-amplified in the opposite direction in the first amplification stage, so as to ensure that in the second amplification stage, it can be effectively differentiated and amplified
  • the voltage on the first bit line and the voltage on the second bit line improve the accuracy of data reading, thereby improving the performance of the semiconductor memory; on the other hand, according to the data on the first bit line and the data on the second bit line to adjust the voltage of the bit lines on both sides of the sense amplifier respectively, thereby compensating for the influence of the offset noise on the voltage of the bit lines on both sides of the sense amplifier, and further improving the performance of the semiconductor memory.
  • the present disclosure also provides a memory including the above-mentioned sense amplifier.
  • the memory according to the exemplary embodiment of the present disclosure better realizes offset compensation and has a low read error rate, the memory performance is greatly improved.

Abstract

一种灵敏放大器、存储器和灵敏放大器的控制方法，涉及半导体存储器技术领域。该灵敏放大器（1）包括：放大模块（11），用于读取第一位线或第二位线上存储单元中的数据；控制模块（12），与放大模块（11）电连接；其中，在读取第一位线上存储单元中数据的情况下，在灵敏放大器（1）的第一放大阶段，控制模块（12）用于将放大模块（11）配置为包括第一电流镜结构，并将第一电流镜结构的镜像端与第二位线连接；在读取第二位线上存储单元中数据的情况下，在灵敏放大器（1）的第一放大阶段，控制模块（12）用于将放大模块（11）配置为包括第二电流镜结构，并将第二电流镜结构的镜像端与第一位线连接。该灵敏放大器（1）可以提高存储器读取数据的准确性。

Description

灵敏放大器、存储器和灵敏放大器的控制方法
相关申请的交叉引用
本申请要求于2020年09月01日提交的申请号为202010902453.9、名称为“灵敏放大器、存储器和灵敏放大器的控制方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体存储器技术领域，具体而言，涉及一种灵敏放大器、存储器和灵敏放大器的控制方法。
背景技术
随着手机、平板、个人计算机等电子设备的普及，半导体存储器技术也得到了快速的发展。例如DRAM(Dynamic Random Access Memory，动态随机存取存储器)、SRAM(Static Random-Access Memory，静态随机存取存储器)的存储器由于高密度、低功耗、低价格等优点，已广泛应用于各种电子设备中。
在DRAM中，不同存储单元阵列中的每一个位线都成对地连接到具有一个位线BL(读取位线)输入端和一个位线BLB(参考位线)输入端的灵敏放大器中。在读取操作(或刷新操作)中，灵敏放大器的作用就是读取位线BL和参考位线BLB之间的电压差，并放大两个位线间的电压差。
然而，在灵敏放大器执行放大操作时，可能出现异常，导致放大后输出的结果错误，严重影响半导体存储器的性能。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种灵敏放大器、存储器和灵敏放大器的控制方法，进而至少在一定程度上克服由于灵敏放大器读取数据出现错误的问题。
根据本公开的第一方面，提供一种灵敏放大器，包括：放大模块，用于读取第一位线或第二位线上存储单元中的数据；控制模块，与放大模块电连接；其中，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，控制模块用于将放大模块配置为包括第一电流镜结构，并将第一电流镜结构的镜像端与第二位线连接；在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，控制模块用于将放大模块配置为包括第二电流镜结构，并将第二电流镜结构的镜像端与第一位线连接。
可选地，放大模块包括：第一PMOS管；第二PMOS管；第一NMOS管，第一NMOS 管的栅极与第二位线连接，第一NMOS管的漏极通过第一节点与第一PMOS管的漏极连接；第二NMOS管，第二NMOS管的栅极与第一位线连接，第二NMOS管的漏极通过第二节点与第二PMOS管的漏极连接；其中，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，控制模块用于将第一PMOS管和第二PMOS管配置为第一电流镜结构，并将第二位线与第二节点连接；在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，控制模块用于将第一PMOS管和第二PMOS管配置为第二电流镜结构，并将第一位线与第一节点连接。
可选地，控制模块还包括：第一开关，第一开关的第一端与第一PMOS管的栅极连接，第一开关的第二端与第二PMOS管的栅极连接；第二开关，第二开关的第一端与第二PMOS管的栅极连接，第二开关的第二端与第一节点连接；第三开关，第三开关的第一端与第二节点连接，第三开关的第二端与第一PMOS管的栅极连接；第四开关，第四开关的第一端与第二节点连接，第四开关的第二端与第二位线连接；第五开关，第五开关的第一端与第一位线连接，第五开关的第二端与第一节点连接；其中，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，第一开关、第二开关和第四开关闭合，第三开关和第五开关断开；在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，第一开关、第三开关和第五开关闭合，第二开关和第四开关断开。
可选地，在灵敏放大器的第一放大阶段，第一PMOS管和第二PMOS管的源极接收第一电压，第一NMOS管和第二NMOS管的源极接地。
可选地，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，控制模块用于将放大模块配置为包括第一电流镜结构和第一二极管结构；在读取第二位线上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，控制模块用于将放大模块配置为包括第二电流镜结构和第二二极管结构。
可选地，控制模块还包括：第六开关，第六开关的第一端与第一节点连接，第六开关的第二端与第二位线连接；第七开关，第七开关的第一端与第一位线连接，第七开关的第二端与第二节点连接；其中，在灵敏放大器的第一放大阶段，第六开关和第七开关断开；在读取第一位线上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，第六开关断开，第七开关闭合；在读取第二位线上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，第六开关闭合，第七开关断开。
可选地，在灵敏放大器的失调补偿阶段，第一PMOS管和第二PMOS管的源极接收第一电压，第一NMOS管和第二NMOS管的源极接地。
可选地，在灵敏放大器的第一放大阶段之后的第二放大阶段，控制模块用于将放大模块配置为交叉耦合放大结构。
可选地，在灵敏放大器的第二放大阶段，第一开关、第六开关和第七开关断开，第二开关、第三开关、第四开关和第五开关闭合。
可选地，在灵敏放大器的第二放大阶段，第一PMOS管和第二PMOS管的源极接收 第一电压，第一NMOS管和第二NMOS管的源极接地。
可选地，在灵敏放大器的失调补偿阶段与第一放大阶段之间，还包括灵敏放大器的感应阶段；在读取第一位线上存储单元中数据的情况下，在灵敏放大器的感应阶段，第一开关、第二开关闭合，第三开关、第四开关、第五开关、第六开关和第七开关断开；在读取第二位线上存储单元中数据的情况下，在灵敏放大器的感应阶段，第一开关、第三开关闭合，第二开关、第四开关、第五开关、第六开关和第七开关断开。
可选地，在灵敏放大器还包括：预充模块，用于在灵敏放大器的失调补偿阶段之前的预充阶段，对第一位线和第二位线进行预充电。
可选地，在灵敏放大器的预充阶段，第一PMOS管、第二PMOS管、第一NMOS管和第二PMOS管的源极均接收第二电压。
根据本公开的第二方面，提供一种存储器，包括如上述任意一项的灵敏放大器。
根据本公开的第三方面，提供一种灵敏放大器的控制方法，灵敏放大器包括放大模块和控制模块，灵敏放大器的控制方法包括：在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，利用控制模块将放大模块配置为包括第一电流镜结构，并将第一电流镜结构的镜像端与第二位线连接；在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，利用控制模块将放大模块配置为包括第二电流镜结构，并将第二电流镜结构的镜像端与第一位线连接。
可选地，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，利用控制模块将放大模块配置为包括第一电流镜结构和第一二极管结构；在读取第二位线上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，利用控制模块将放大模块配置为包括第二电流镜结构和第二二极管结构。
在本公开的一些实施例所提供的技术方案中，通过控制模块的控制，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，将放大模块配置为包括第一电流镜结构，并将第一电流镜结构的镜像端与第二位线连接；在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，将放大模块配置为包括第二电流镜结构，并将第二电流镜结构的镜像端与第一位线连接。基于本公开的电路配置，可以在第一放大阶段使非读取的位线电压向相反方向预放大，以确保在第二放大阶段，能够有效区分并放大第一位线上电压和第二位线上电压，提高数据读取的准确性，进而提高半导体存储器的性能。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的 一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1示意性示出了根据本公开的示例性实施方式的灵敏放大器的框图；
图2示意性示出了根据本公开的示例性实施方式的灵敏放大器的电路图；
图3示意性示出了根据本公开一实施例的灵敏放大器的具体配置方式的电路图；
图4示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时灵敏放大器中所涉各控制信号的时序图；
图5示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时在预充阶段灵敏放大器的电路图；
图6示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时在失调补偿阶段灵敏放大器的电路图；
图7示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时在感应阶段灵敏放大器的电路图；
图8示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时在第一放大阶段灵敏放大器的电路图；
图9示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时在第二放大阶段灵敏放大器的电路图；
图10示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时灵敏放大器中所涉各控制信号的时序图；
图11示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时在预充阶段灵敏放大器的电路图；
图12示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时在失调补偿阶段灵敏放大器的电路图；
图13示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时在感应阶段灵敏放大器的电路图；
图14示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时在第一放大阶段灵敏放大器的电路图；
图15示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时在第二放大阶段灵敏放大器的电路图；
图16示意性示出了根据本公开的示例性实施方式的灵敏放大器的控制方法的流程图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结 构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。“第一”、“第二”、“第三”、“第四”、“第五”、“第六”、“第七”的描述仅是为了区分，不应作为本公开的限制。
需要说明的是，本公开所说的术语“连接”，可以包括直接连接和间接连接。在直接连接中，端与端之间没有元器件，例如，开关A的第一端与开关B的第一端连接，可以是在开关A的第一端与开关B的第一端的连接线路上，只有连接线(如，金属线)，而不存在其他元器件。在间接连接中，端与端之间可以存在其他元器件，例如，开关C的第一端与开关D的第一端连接，可以是在开关C的第一端与开关D的第一端的连接线路上，除连接线外，连接线上还存在至少一个其他元器件(如，开关E等)。
在灵敏放大器中，由于制程上的差异以及工作环境的影响，可能导致晶体管的尺寸、迁移率、阈值电压等存在差别，各晶体管的性能通常不可能完全相同，这就会造成灵敏放大器失调，相当于出现了失调噪声，严重影响存储器读取数据的正确性。
例如，灵敏放大器包括两个对称配置的NMOS管，理想状态下，希望这两个NMOS管的性能完全相同。然而，在实际中，这两个NMOS管的阈值电压可能不同，这就会出现电路失调的情况。此时若不采取任何措施，在从存储单元读取数据时，就有可能将原本存储的“1”读成“0”错误输出，或者将原本存储的“0”读成“1”错误输出。
此外，在灵敏放大器对位线上电压进行放大之前，可能存在两个位线上电压差距较小的问题，在这种情况下，进行放大后可能无法实现将一侧放大至0且另一侧放大至1的效果，由此，可能导致读出数据错误的问题，严重影响到半导体存储器的性能。
鉴于上述技术问题，本公开提供了一种新的灵敏放大器。
图1示意性示出了根据本公开的示例性实施方式的灵敏放大器的框图。如图1所示，灵敏放大器1可以包括放大模块11和控制模块12。
放大模块11可以用于读取第一位线或第二位线上存储单元的数据；
控制模块12与放大模块11电连接。
在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，控制模块12用于将放大模块11配置为包括第一电流镜结构，并将该第一电流镜结构的镜像端与第二位线连接。
在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，控制模块12用于将放大模块11配置为包括第二电流镜结构，并将该第二电流镜结构的镜像端与第一位线连接。
本领域技术人员容易理解的是，电流镜结构可以包括源端和镜像端，在结构上，源端可以是电流镜结构中二极管连接方式对应的端，也可以将其理解为源端直接与二极管结构连接。而镜像端可以是电流镜结构中非二极管连接方式对应的端，也可以将其理解为镜像端不直接与二极管结构连接。
另外，应当注意的是，第一电流镜结构与第二电流镜结构至少在电路配置上存在差异。
基于本公开的电路配置，可以在第一放大阶段使非读取的位线电压向相反方向预放大，以确保在第二放大阶段，能够有效区分并放大第一位线上电压和第二位线上电压，提高数据读取的准确性，进而提高半导体存储器的性能。
在本公开的一些实施例中，可以补偿由于失调噪声给灵敏放大器两边位线电压带来的影响，从而进一步提高半导体存储器的性能。
应当理解的是，本公开所述的失调噪声指的是放大模块11中至少两个晶体管(或元器件)之间的不一致而产生的电压差。在综合所有晶体管(或元器件)之间的电压差的情况下，失调噪声指代整个放大模块11的失调噪声。
放大模块11可以包括第一PMOS管(下面简称晶体管P1)、第二PMOS管(下面简称晶体管P2)、第一NMOS管(下面简称晶体管N1)、第二NMOS管(下面简称晶体管N2)。
在这种情况下，失调噪声可以是晶体管P1与晶体管P2的失调电压，也可以是晶体管N1与晶体管N2的失调电压，还可以是这二者综合后的失调电压，本公开对此不做限制。
图2示意性示出了根据本公开的示例性实施方式的灵敏放大器的电路图。
参考图2，晶体管P1的漏极与晶体管N1的漏极连接，晶体管P2的漏极与晶体管N2的漏极连接。另外，晶体管N1的栅极与第二位线BLB连接，晶体管N2的栅极与第一位线BL连接。
为了随后描述方便，可以在灵敏放大器中定义第一节点nL和第二节点nR。晶体管P1的漏极与晶体管N1的漏极连接于第一节点nL，晶体管P2的漏极与晶体管N2的漏极连接于第二节点nR。
本公开示例性实施方式的灵敏放大器的工作阶段可以被划分为：预充阶段、失调补偿阶段、第一放大阶段和第二放大阶段。
在一实施例中，在失调补偿阶段与第一放大阶段之间，还可以包括感应阶段(或称电压感应阶段)。
在读取第一位线BL上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，晶体管P1和晶体管P2被配置为第一电流镜结构，并将第二位线BLB与第二节点nR连接。
在读取第二位线BLB上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，晶体管P1和晶体管P2被配置为第二电流镜结构，并将第一位线BL与第一节点nL连接。
本公开示例性实施方式通过控制模块来实现上述配置。参考图2，控制模块可以包括 第一开关(下面简称开关K1)、第二开关(下面简称开关K2)、第三开关(下面简称开关K3)、第四开关(下面简称开关K4)和第五开关(下面简称开关K5)。
开关K1的第一端与晶体管P1的栅极连接，开关K1的第二端与晶体管P2的栅极连接；开关K2的第一端与晶体管P2的栅极连接，开关K2的第二端与第一节点nL连接；开关K3的第一端与第二节点nR连接，开关K3的第二端与晶体管P1的栅极连接；开关K4的第一端与第二节点nR连接，开关K4的第二端与第二位线BLB连接；开关K5的第一端与第一位线BL连接，开关K5的第二端与第一节点nL连接。
在读取第一位线BL上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，开关K1、开关K2和开关K4闭合，开关K3和开关K5断开。
在读取第二位线BLB上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，开关K1、开关K3和开关K5闭合，开关K2和开关K4断开。
与上面描述对应的，在读取第一位线BL上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，由于开关K1和开关K2闭合，晶体管P1和晶体管P2形成第一电流镜结构，该第一电流镜结构的源端可以是第一节点nL，第一电流镜结构的镜像端可以是第二节点nR。
在读取第二位线BLB上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，由于开关K1和开关K3闭合，晶体管P1和晶体管P2形成第二电流镜结构，该第二电流镜结构的源端可以是第二节点nR，第二电流镜结构的镜像端可以是第一节点nL。
其中，本公开对开关K1、开关K2、开关K3、开关K4和开关K5的类型不做限制。例如，开关K1可以是PMOS管、NMOS管或CMOS传输门；开关K2可以是PMOS管、NMOS管或CMOS传输门；开关K3可以是PMOS管、NMOS管或CMOS传输门；开关K4可以是PMOS管、NMOS管或CMOS传输门；开关K5可以是PMOS管、NMOS管或CMOS传输门。
在本公开的一些实施例中，开关K1可以包括控制端，用于响应第一控制信号(记为控制信号S1)控制开关K1的开关状态；开关K2也可以包括控制端，用于响应第二控制信号(记为控制信号S2)控制开关K2的开关状态；开关K3也可以包括控制端，用于响应第三控制信号(记为控制信号S3)控制开关K3的开关状态；开关K4也可以包括控制端，用于响应第四控制信号(记为控制信号S4)控制开关K4的开关状态；开关K5也可以包括控制端，用于响应第五控制信号(记为控制信号S5)控制开关K5的开关状态。
此外，晶体管P1的源极可以接收控制信号ACT1，晶体管P2的源极可以接收控制信号ACT2，晶体管N1的源极可以接收控制信号NLAT1，晶体管N2的源极可以接收控制信号NLAT2。
在本公开的一些实施例中，晶体管P1的源极与晶体管P2的源极可以连接，也就是说，控制信号ACT1与控制信号ACT2相同。晶体管N1的源极与晶体管N2的源极可以连接，也就是说，控制信号NLAT1与控制信号NLAT2相同。
在灵敏放大器的第一放大阶段，晶体管P1和晶体管P2的源极均接收第一电压，其中，第一电压可以是电源电压VCC。也就是说，在此阶段，控制信号ACT1和控制信号ACT2均被配置为第一电压。
在此阶段，晶体管N1与晶体管N2的源极接地(GND)，也就是说，控制信号NLAT1和控制信号NLAT2接收的电压是0。
在读取第一位线BL上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，控制模块用于将放大模块配置为包括上述第一电流镜结构和第一二极管结构。
在读取第二位线BLB上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，控制模块用于将放大模块配置为包括上述第二电流镜结构和第二二极管结构。
其中，第二二极管结构与第一二极管结构至少在电路配置上存在差异。具体的，可以将晶体管N2配置为上述第一二极管结构，将晶体管N1配置为上述第二二极管结构。
在这种情况下，参考图2，本公开的灵敏放大器还可以包括第六开关(下面简称开关K6)和第七开关(下面简称开关K7)。
开关K6的第一端与第一节点nL连接，开关K6的第二端与第二位线BLB连接；开关K7的第一端与第一位线BL连接，开关K7的第二端与第二节点nR连接。
类似地，本公开对开关K6和开关K7的类型不做限制。例如，开关K6可以是PMOS管、NMOS管或CMOS传输门；开关K7可以是PMOS管、NMOS管或CMOS传输门。
在本公开的一些实施例中，开关K6可以包括控制端，用于响应第六控制信号(记为控制信号S6)控制开关K6的开关状态；开关K7也可以包括控制端，用于响应第七控制信号(记为控制信号S7)控制开关K7的开关状态。
在灵敏放大器的第一放大阶段，开关K6和开关K7断开。
在读取第一位线BL上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，开关K6断开，开关K7闭合；在读取第二位线BLB上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，开关K6闭合，开关K7断开。
另外，在灵敏放大器的失调补偿阶段，晶体管P1和晶体管P2的源极接收第一电压，晶体管N1和晶体管N2的源极接地。
在灵敏放大器的第一放大阶段之后的第二放大阶段，控制模块还用于将放大模块配置为交叉耦合放大结构。
具体的，在第二放大阶段，开关K1、开关K6和开关K7断开，开关K2、开关K3、开关K4和开关K5闭合。并且，晶体管P1和晶体管P2的源极接收第一电压，即控制信号ACT1和控制信号ACT2为VCC。晶体管N1和晶体管N2的源极接地，即控制信号NLAT1和控制信号NLAT2为0。
在本公开的一些实施例中，在灵敏放大器的失调补偿阶段与第一放大阶段之间，还包括灵敏放大器的感应阶段。
在读取第一位线BL上存储单元中数据的情况下，在灵敏放大器的感应阶段，开关 K1、开关K2闭合，开关K3、开关K4、开关K5、开关K6和开关K7断开。
在读取第二位线BLB上存储单元中数据的情况下，在灵敏放大器的感应阶段，开关K1、开关K3闭合，开关K2、开关K4、开关K5、开关K6和开关K7断开。
此外，灵敏放大器还包括预充模块，用于在灵敏放大器的失调补偿阶段之前的预充阶段，对第一位线BL和第二位线BLB进行预充电。
在预充阶段，晶体管P1、晶体管P2、晶体管N1和晶体管N2的源极均接收第二电压。其中，第二电压小于第一电压。在一个实施例中，第二电压可以是VCC/2。
另外，在确保能够对第一位线BL和第二位线BLB进行预充电的情况下，开关K1、开关K2、开关K3、开关K4、开关K5、开关K6、开关K7中的一个或多个开关可以处于闭合状态，本公开对此不做限制。
图3示意性示出了根据本公开一实施例的灵敏放大器的电路图。
在图3所示的实施例中，开关K1被配置为晶体管N3，响应控制信号S1来控制开关状态；开关K2被配置为晶体管N4，响应控制信号S2来控制开关状态；开关K3被配置为晶体管N5，响应控制信号S3来控制开关状态；开关K4被配置为晶体管N6，响应控制信号S4来控制开关状态；开关K5被配置为晶体管N7，响应控制信号S5来控制开关状态；开关K6被配置为晶体管N8，响应控制信号S6来控制开关状态；开关K7被配置为晶体管N9，响应控制信号S7来控制开关状态。
预充模块可以包括晶体管N10、晶体管N11和晶体管N12。
晶体管N10、晶体管N11和晶体管N12的栅极均可以接收预充控制信号BLP。晶体管N10的源极与第一位线BL连接，晶体管N10的漏极与第二位线BLB连接；晶体管N11的源极与第二位线BLB连接，晶体管N11的漏极与晶体管N12的源极连接，且连接于预充电压Veq，其中，预充电压Veq可以被配置为VCC/2；晶体管N12的漏极与第一位线BL连接。
与第一位线BL对应的存储单元被配置为包括晶体管N13和电容C1，晶体管N13响应字线控制信号WL控制开关状态；与第二位线BLB对应的存储单元被配置为包括晶体管N14和电容C2，晶体管N14响应字线控制信号WLB控制开关状态。
下面将分别对读取第一位线BL上数据的过程和读取第二位线BLB上数据的过程进行说明。
图4示意性示出了根据本公开实施例的读取第一位线BL上存储单元中数据时灵敏放大器中所涉各控制信号的时序图。
下面将结合图4的时序图，对本公开实施例的读取第一位线BL上存储单元中数据时灵敏放大器的工作阶段进行说明。
图5针对读取第一位线BL上存储单元中数据时灵敏放大器的预充阶段。预充控制信号BLP和控制信号S2为高电平，其余控制信号为低电平。
对应的，晶体管N10、晶体管N11、晶体管N12、晶体管N4导通(对应开关的闭合 状态)，晶体管N3、晶体管N5、晶体管N6、晶体管N7、晶体管N8和晶体管N9关断(对应开关的断开状态)。
在这种情况下，第一位线BL和第二位线BLB分别通过晶体管N11和晶体管N12连接至预充电压Veq，并通过晶体管N10彼此相连，从而第一位线BL和第二位线BLB被预充至Veq。
另外，需要说明的是，在确保能够对第一位线BL和第二位线BLB进行预充电的情况下，晶体管N3、晶体管N4、晶体管N5、晶体管N6、晶体管N7、晶体管N8和晶体管N9中的一个或多个可以处于导通状态，本公开对此不做限制。
图6针对读取第一位线BL上存储单元中数据时灵敏放大器的失调补偿阶段。在失调补偿阶段，控制信号S1、控制信号S2和控制信号S7为高电平，其余控制信号为低电平。
对应的，晶体管N3、晶体管N4和晶体管N9导通，晶体管N5、晶体管N6、晶体管N7和晶体管N8关断。
在这种情况下，预充电压通过晶体管N9进入灵敏放大器，基于由晶体管P1和晶体管P2组成的电流镜结构，使得由晶体管P1、晶体管N1构成的支路上的电流与由晶体管P2、晶体管N2构成的支路上的电流相等，由此，缓解了由于失调噪声对电路造成的影响。
图7针对读取第一位线BL上存储单元中数据时灵敏放大器的感应阶段。在感应阶段，控制信号S1、控制信号S2为高电平，晶体管N3和晶体管N4导通。通过感应阶段，使上述两个支路上电荷情况趋于稳定。
应当理解的是，在本公开的一些实施例中，灵敏放大器的工作阶段可以没有感应阶段。也就是说，在失调补偿阶段后，可以直接进入第一放大阶段。
图8针对读取第一位线BL上存储单元中数据时灵敏放大器的第一放大阶段。控制信号S1、控制信号S2、控制信号S4为高电平，并且字线控制信号WL处于开启状态。
对应的，晶体管N3、晶体管N4和晶体管N6导通，晶体管N5、晶体管N7、晶体管N8和晶体管N9关断。
在针对第一位线BL读“1”时，晶体管N2的栅极电压升高，导通能力提高，漏极电压下降，而漏极与第二位线BLB连接，故第二位线BLB上电压下降。由此达到了控制非读取的位线电压向反方向预放大的目的，增大了第一位线BL与第二位线BLB的电压差，有助于随后对二者电压进行进一步放大的过程。
在针对第一位线BL读“0”时，晶体管N2的栅极电压降低，在这种情况下，漏极电压升高，也就是说，第二位线BLB的电压被拉高。由此，也达到了增大第一位线BL与第二位线BLB的电压差的目的，有助于随后对二者电压进行进一步放大的过程。
图9针对读取第一位线BL上存储单元中数据时灵敏放大器的第二放大阶段。控制信号S2、控制信号S3、控制信号S4和控制信号S5为高电平。相应的，晶体管N4、晶体管N5、晶体管N6和晶体管N7导通，晶体管N3、晶体管N8和晶体管N9关断。由此，晶体管P1、晶体管P2、晶体管N1和晶体管N2构成交叉耦合放大结构。
在针对第一位线BL读“1”时，第一位线BL上的电压高于第二位线BLB上的电压，此时，晶体管N2和晶体管N6导通，可以将第二位线BLB上的电压通过晶体管N2放电至地(GND)。另外，晶体管P1导通，可以将第一位线BL上的电压升高至VCC。
在针对第一位线BL读“0”时，第一位线BL上的电压低于第二位线BLB上的电压，此时，晶体管N1和晶体管N7导通，可以将第一位线BL上的电压通过晶体管N1放电至地(GND)。另外，晶体管P2导通，可以将第二位线BLB上的电压升高至VCC。
由此，通过这种交叉耦合放大结构，可以实现位线从存储单元中读取出来的小电压差放大至全摆幅(0或1)的目的。
图10示意性示出了根据本公开实施例的读取第二位线BLB上存储单元中数据时灵敏放大器中所涉各控制信号的时序图。
下面将结合图10的时序图，对本公开实施例的读取第二位线BLB上存储单元中数据时灵敏放大器的工作阶段进行说明。
图11针对读取第二位线BLB上存储单元中数据时灵敏放大器的预充阶段。预充控制信号BLP和控制信号S3为高电平，其余控制信号为低电平。
对应的，晶体管N10、晶体管N11、晶体管N12、晶体管N5导通，晶体管N3、晶体管N4、晶体管N6、晶体管N7、晶体管N8和晶体管N9关断。
在这种情况下，第一位线BL和第二位线BLB分别通过晶体管N11和晶体管N12连接至预充电压Veq，并通过晶体管N10彼此相连，从而第一位线BL和第二位线BLB被预充至Veq。
另外，需要说明的是，在确保能够对第一位线BL和第二位线BLB进行预充电的情况下，晶体管N3、晶体管N4、晶体管N5、晶体管N6、晶体管N7、晶体管N8和晶体管N9中的一个或多个可以处于关断状态，本公开对此不做限制。
图12针对读取第二位线BLB上存储单元中数据时灵敏放大器的失调补偿阶段。控制信号S1、控制信号S3和控制信号S6为高电平，其余控制信号为低电平。
对应的，晶体管N3、晶体管N5和晶体管N8导通，晶体管N4、晶体管N6、晶体管N7和晶体管N9关断。
在这种情况下，预充电压通过晶体管N8进入灵敏放大器，基于由晶体管P1和晶体管P2组成的电流镜结构，使得由晶体管P1、晶体管N1构成的支路上的电流与由晶体管P2、晶体管N2构成的支路上的电流相等，由此，缓解了由于失调噪声对电路造成的影响。
另外，本领域技术人员可以看出，读取第二位线BLB上存储单元中数据时，也可以采用如图6所示的电路配置来实现失调补偿，本公开对此不做限制。
图13针对读取第二位线BLB上存储单元中数据时灵敏放大器的感应阶段。控制信号S1、控制信号S3为高电平，晶体管N3和晶体管N5导通。通过感应阶段，使上述两个支路上电荷情况趋于稳定。
应当理解的是，在本公开的一些实施例中，灵敏放大器的工作阶段可以没有感应阶段。 也就是说，在失调补偿阶段后，可以直接进入第一放大阶段。
图14针对读取第二位线BLB上存储单元中数据时灵敏放大器的第一放大阶段。控制信号S1、控制信号S3、控制信号S5为高电平，并且字线控制信号WLB处于开启状态。
对应的，晶体管N3、晶体管N5和晶体管N7导通，晶体管N4、晶体管N6、晶体管N8和晶体管N9关断。
在针对第二位线BLB读“1”时，晶体管N1的栅极电压升高，导通能力提高，漏极电压下降，而漏极与第一位线BL连接，故第一位线BL上电压下降。由此达到了控制非读取的位线电压向反方向预放大的目的，增大了第一位线BL与第二位线BLB的电压差，有助于随后对二者电压进行进一步放大的过程。
在针对第二位线BLB读“0”时，晶体管N1的栅极电压降低，在这种情况下，漏极电压升高，也就是说，第一位线BL的电压被拉高。由此，也达到了增大第一位线BL与第二位线BLB的电压差的目的，有助于随后对二者电压进行进一步放大的过程。
图15针对读取第二位线BLB上存储单元中数据时灵敏放大器的第二放大阶段。图15的第二放大阶段与上面描述图9的过程相同，在此不再赘述。
进一步的，本公开还提供了一种灵敏放大器的控制方法。
图16示意性示出了根据本公开的示例性实施方式的灵敏放大器的控制方法的流程图。如上所述，灵敏放大器可以包括放大模块和控制模块。
参考图16，灵敏放大器的控制方法可以包括以下步骤：
S162.在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，利用控制模块将放大模块配置为包括第一电流镜结构，并将第一电流镜结构的镜像端与第二位线连接；
S164.在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，利用控制模块将放大模块配置为包括第二电流镜结构，并将第二电流镜结构的镜像端与第一位线连接。
根据本公开的示例性实施例，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，利用控制模块将放大模块配置为包括第一电流镜结构和第一二极管结构；在读取第二位线上存储单元中数据的情况下，在灵敏放大器的失调补偿阶段，利用控制模块将放大模块配置为包括第二电流镜结构和第二二极管结构。
根据本公开的示例性实施例，在灵敏放大器的第一放大阶段之后的第二放大阶段，利用控制模块将放大模块配置为交叉耦合放大结构。
根据本公开的示例性实施例，如上所述，灵敏放大器还可以包括预充阶段和感应阶段，这些阶段的细节在上面描述灵敏放大器的配置的过程中均已说明，在此不再赘述。
通过本公开示例性实施方式的灵敏放大器的控制方法，一方面，可以在第一放大阶段使非读取的位线电压向相反方向预放大，以确保在第二放大阶段，能够有效区分并放大第一位线上电压和第二位线上电压，提高数据读取的准确性，进而提高半导体存储器的性能； 另一方面，可以根据读取第一位线上数据与第二位线上数据的不同，来分别调节灵敏放大器两边位线的电压，从而补偿由于失调噪声给灵敏放大器两边位线电压带来的影响，进一步提高半导体存储器的性能。
进一步的，本公开还提供了一种存储器，该存储器包括上述灵敏放大器。
本公开示例性实施方式的存储器由于较好地实现了失调补偿，读取错误率低，因此，存储器性能得到了较大幅度的提升。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。

Claims (16)

  1. 一种灵敏放大器，包括：
    放大模块，用于读取第一位线或第二位线上存储单元中的数据；
    控制模块，与所述放大模块电连接；
    其中，在读取所述第一位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，所述控制模块用于将所述放大模块配置为包括第一电流镜结构，并将所述第一电流镜结构的镜像端与所述第二位线连接；在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，所述控制模块用于将所述放大模块配置为包括第二电流镜结构，并将所述第二电流镜结构的镜像端与所述第一位线连接。
  2. 根据权利要求1所述的灵敏放大器，其中，所述放大模块包括：
    第一PMOS管；
    第二PMOS管；
    第一NMOS管，所述第一NMOS管的栅极与所述第二位线连接，所述第一NMOS管的漏极通过第一节点与所述第一PMOS管的漏极连接；
    第二NMOS管，所述第二NMOS管的栅极与所述第一位线连接，所述第二NMOS管的漏极通过第二节点与所述第二PMOS管的漏极连接；
    其中，在读取所述第一位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，所述控制模块用于将所述第一PMOS管和所述第二PMOS管配置为所述第一电流镜结构，并将所述第二位线与所述第二节点连接；在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，所述控制模块用于将所述第一PMOS管和所述第二PMOS管配置为所述第二电流镜结构，并将所述第一位线与所述第一节点连接。
  3. 根据权利要求2所述的灵敏放大器，其中，所述控制模块还包括：
    第一开关，所述第一开关的第一端与所述第一PMOS管的栅极连接，所述第一开关的第二端与所述第二PMOS管的栅极连接；
    第二开关，所述第二开关的第一端与所述第二PMOS管的栅极连接，所述第二开关的第二端与所述第一节点连接；
    第三开关，所述第三开关的第一端与所述第二节点连接，所述第三开关的第二端与所述第一PMOS管的栅极连接；
    第四开关，所述第四开关的第一端与所述第二节点连接，所述第四开关的第二端与所述第二位线连接；
    第五开关，所述第五开关的第一端与所述第一位线连接，所述第五开关的第二端与所述第一节点连接；
    其中，在读取所述第一位线上存储单元中数据的情况下，在所述灵敏放大器的第一放 大阶段，所述第一开关、所述第二开关和所述第四开关闭合，所述第三开关和所述第五开关断开；在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，所述第一开关、所述第三开关和所述第五开关闭合，所述第二开关和所述第四开关断开。
  4. 根据权利要求3所述的灵敏放大器，其中，在所述灵敏放大器的第一放大阶段，所述第一PMOS管和所述第二PMOS管的源极接收第一电压，所述第一NMOS管和所述第二NMOS管的源极接地。
  5. 根据权利要求4所述的灵敏放大器，其中，在读取所述第一位线上存储单元中数据的情况下，在所述灵敏放大器的失调补偿阶段，所述控制模块用于将所述放大模块配置为包括所述第一电流镜结构和第一二极管结构；
    在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的失调补偿阶段，所述控制模块用于将所述放大模块配置为包括所述第二电流镜结构和第二二极管结构。
  6. 根据权利要求5所述的灵敏放大器，其中，所述控制模块还包括：
    第六开关，所述第六开关的第一端与所述第一节点连接，所述第六开关的第二端与所述第二位线连接；
    第七开关，所述第七开关的第一端与所述第一位线连接，所述第七开关的第二端与所述第二节点连接；
    其中，在所述灵敏放大器的第一放大阶段，所述第六开关和所述第七开关断开；在读取所述第一位线上存储单元中数据的情况下，在所述灵敏放大器的失调补偿阶段，所述第六开关断开，所述第七开关闭合；在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的失调补偿阶段，所述第六开关闭合，所述第七开关断开。
  7. 根据权利要求6所述的灵敏放大器，其中，在所述灵敏放大器的失调补偿阶段，所述第一PMOS管和所述第二PMOS管的源极接收所述第一电压，所述第一NMOS管和所述第二NMOS管的源极接地。
  8. 根据权利要求6所述的灵敏放大器，其中，在所述灵敏放大器的第一放大阶段之后的第二放大阶段，所述控制模块用于将所述放大模块配置为交叉耦合放大结构。
  9. 根据权利要求8所述的灵敏放大器，其中，在所述灵敏放大器的第二放大阶段，所述第一开关、所述第六开关和所述第七开关断开，所述第二开关、所述第三开关、所述第四开关和所述第五开关闭合。
  10. 根据权利要求9所述的灵敏放大器，其中，在所述灵敏放大器的第二放大阶段，所述第一PMOS管和所述第二PMOS管的源极接收所述第一电压，所述第一NMOS管和所述第二NMOS管的源极接地。
  11. 根据权利要求10所述的灵敏放大器，其中，在所述灵敏放大器的失调补偿阶段与第一放大阶段之间，还包括所述灵敏放大器的感应阶段；
    在读取所述第一位线上存储单元中数据的情况下，在所述灵敏放大器的感应阶段，所 述第一开关、所述第二开关闭合，所述第三开关、所述第四开关、所述第五开关、所述第六开关和所述第七开关断开；
    在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的感应阶段，所述第一开关、所述第三开关闭合，所述第二开关、所述第四开关、所述第五开关、所述第六开关和所述第七开关断开。
  12. 根据权利要求11所述的灵敏放大器，其中，在所述灵敏放大器还包括：
    预充模块，用于在所述灵敏放大器的失调补偿阶段之前的预充阶段，对所述第一位线和所述第二位线进行预充电。
  13. 根据权利要求12所述的灵敏放大器，其中，在所述灵敏放大器的预充阶段，所述第一PMOS管、所述第二PMOS管、所述第一NMOS管和所述第二PMOS管的源极均接收第二电压。
  14. 一种存储器，包括如权利要求1所述的灵敏放大器。
  15. 一种灵敏放大器的控制方法，所述灵敏放大器包括放大模块和控制模块，所述灵敏放大器的控制方法包括：
    在读取第一位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，利用所述控制模块将所述放大模块配置为包括第一电流镜结构，并将所述第一电流镜结构的镜像端与第二位线连接；
    在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，利用所述控制模块将所述放大模块配置为包括第二电流镜结构，并将所述第二电流镜结构的镜像端与所述第一位线连接。
  16. 根据权利要求15所述的灵敏放大器的控制方法，其中，在读取所述第一位线上存储单元中数据的情况下，在所述灵敏放大器的失调补偿阶段，利用所述控制模块将所述放大模块配置为包括所述第一电流镜结构和第一二极管结构；
    在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的失调补偿阶段，利用所述控制模块将所述放大模块配置为包括所述第二电流镜结构和第二二极管结构。
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