WO2022021772A1 - 灵敏放大器、存储器和灵敏放大器的控制方法 - Google Patents

灵敏放大器、存储器和灵敏放大器的控制方法 Download PDF

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Publication number
WO2022021772A1
WO2022021772A1 PCT/CN2020/139315 CN2020139315W WO2022021772A1 WO 2022021772 A1 WO2022021772 A1 WO 2022021772A1 CN 2020139315 W CN2020139315 W CN 2020139315W WO 2022021772 A1 WO2022021772 A1 WO 2022021772A1
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WIPO (PCT)
Prior art keywords
bit line
sense amplifier
gate
pmos transistor
switch unit
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PCT/CN2020/139315
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English (en)
French (fr)
Inventor
彭春雨
王子健
卢文娟
吴秀龙
何军
李新
应战
曹堪宇
蔺智挺
陈军宁
Original Assignee
安徽大学
长鑫存储技术有限公司
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Application filed by 安徽大学, 长鑫存储技术有限公司 filed Critical 安徽大学
Priority to US17/441,676 priority Critical patent/US11315610B1/en
Publication of WO2022021772A1 publication Critical patent/WO2022021772A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Definitions

  • the present disclosure relates to the technical field of semiconductor memory, and in particular, to a sense amplifier, a memory and a control method of the sense amplifier.
  • DRAM Dynamic Random Access Memory, dynamic random access memory
  • SRAM Static Random-Access Memory, static random access memory
  • SA Sense Amplifier
  • the purpose of the present disclosure is to provide a sense amplifier, a memory and a control method for the sense amplifier, thereby at least to a certain extent overcoming the problem of high power consumption of the sense amplifier caused by the limitations and defects of the related art.
  • a sense amplifier comprising: an amplification module for reading data of a memory cell on a bit line or a reference bit line; and a first switch module configured to read data on the bit line when the sense amplifier reads the bit line
  • the control amplification module is disconnected from the reference bit line; when the sense amplifier reads the second state for the bit line and the sense amplifier is in the amplification stage, the control amplification module is connected with the reference bit line.
  • the first switch module is configured to control the connection state of the amplification module and the reference bit line based on the voltage transmitted by the bit line and the data source control signal when the sense amplifier is in the amplification stage; wherein, the amplification module and the reference bit line
  • the connection state includes the amplifying module being disconnected from the reference bit line and the amplifying module being connected to the reference bit line.
  • the first switch module includes: a first NOR gate, a first input end of the first NOR gate is connected to the amplifying module through a first node, and a second input end of the first NOR gate is used to receive a data source control signal; a first switch unit, the first control end of the first switch unit is connected to the output end of the first NOR gate, the first end of the first switch unit is connected to the amplifying module through the second node, and the first end of the first switch unit is connected to the amplifier module through the second node. The second end is connected to the reference bit line.
  • the first switch module further includes: a second switch unit, the control end of the second switch unit is connected to the first node, the first end of the second switch unit is connected to the output end of the first NOR gate, the second The second end of the switch unit is connected to the reference bit line.
  • the first switch module controls the connection state between the amplification module and the reference bit line based on the voltage transmitted by the bit line and the data source control signal, including: the first switch module is configured to respond to the voltage transmitted by the bit line and control the data source.
  • the signal and the first control signal control the connection state between the amplification module and the reference bit line; wherein, the first switch unit further includes a second control terminal for receiving the first control signal.
  • the amplifying module includes: a first PMOS transistor, the drain of the first PMOS transistor is connected to the first node; a first NMOS transistor, the drain of the first NMOS transistor is connected to the first node, and the gate of the first NMOS transistor
  • the electrode is connected to the gate of the first PMOS tube; the second PMOS tube, the drain of the second PMOS tube is connected to the second node; the second NMOS tube, the drain of the second NMOS tube is connected to the second node, the second NMOS tube
  • the gate of the tube is connected to the gate of the second PMOS tube; for the third PMOS tube, the drain of the third PMOS tube is connected to the source of the first PMOS tube and the source of the second PMOS tube, and the gate of the third PMOS tube is connected
  • the electrode is used to receive the first control signal, and the source electrode of the third PMOS transistor is used to receive the power supply voltage; the drain electrode of the third NMOS transistor, the drain electrode of the third NMOS transistor, the
  • the first switch unit includes: a fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the output end of the first NOR gate, the drain of the fourth PMOS transistor is connected to the second node, and the fourth PMOS transistor The source is connected to the reference bit line.
  • the first switch unit includes: a fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the output end of the first NOR gate, the drain of the fourth PMOS transistor is connected to the second node, and the fourth PMOS transistor
  • the source of the fourth NMOS tube is connected to the reference bit line; the fourth NMOS tube, the gate of the fourth NMOS tube is used to receive the first control signal, the source of the fourth NMOS tube is connected to the second node, and the drain of the fourth NMOS tube is connected to Reference bit line connection.
  • the sense amplifier further includes: a second switch module configured to control the amplifying module to disconnect from the bit line when the sense amplifier reads the first state for the reference bit line and the sense amplifier is in the amplification stage; When the bit line reads the second state and the sense amplifier is in the amplification stage, the amplification module is controlled to be connected to the bit line.
  • the second switch module includes: an inverter, the input terminal of which is used to receive the data source control signal; a second NOR gate, the first input terminal of the second NOR gate and the output of the inverter
  • the third switch unit, the first control terminal of the third switch unit is connected with the output terminal of the second NOR gate, and the third switch unit
  • the first end of the unit is connected to the amplifying module through the first node, and the second end of the third switch unit is connected to the bit line.
  • the second switch module further includes: a fourth switch unit, the control end of the fourth switch unit is connected to the second node, the first end of the fourth switch unit is connected to the output end of the second NOR gate, the fourth The second end of the switch unit is connected to the bit line.
  • the third switch unit further includes: a second control terminal for receiving the first control signal.
  • the third switch unit includes: a fifth PMOS transistor, the gate of the fifth PMOS transistor is connected to the output end of the second NOR gate, the drain of the fifth PMOS transistor is connected to the first node, and the fifth PMOS transistor The source is connected to the bit line.
  • the third switch unit includes: a fifth PMOS transistor, the gate of the fifth PMOS transistor is connected to the output end of the second NOR gate, the drain of the fifth PMOS transistor is connected to the first node, and the fifth PMOS transistor
  • the source of the fifth NMOS tube is connected to the bit line; the gate of the fifth NMOS tube is used to receive the first control signal, the source of the fifth NMOS tube is connected to the first node, and the drain of the fifth NMOS tube is connected to the bit line line connection.
  • the sense amplifier further includes: a precharge module configured to precharge the bit line and the reference bit line when the sense amplifier is in the precharge phase.
  • reading the first state is read 0, and reading the second state is read 1.
  • a memory including the sense amplifier as described above.
  • a control method for a sense amplifier comprising: when the sense amplifier reads a first state for a bit line and the sense amplifier is in an amplification stage, controlling the sense amplifier to be disconnected from a reference bit line; When the second state is read for the bit line and the sense amplifier is in the amplification stage, the sense amplifier is controlled to be connected to the reference bit line.
  • the first switch module is configured to control the amplification module to disconnect from the reference bit line when the sense amplifier reads the first state for the bit line and the sense amplifier is in the amplification stage. Since the amplifying module is disconnected from the reference bit line, the sense amplifier will not amplify the voltage on the reference bit line during the amplifying stage. Therefore, when the bit line reads the first state, the power consumption of the sense amplifier will be greatly reduced. In addition, since the solution of the present disclosure does not perform voltage amplification on the reference bit line when the bit line reads the first state, the signal processing speed of the circuit is improved.
  • FIG. 1 schematically shows a schematic diagram of a sense amplifier according to an embodiment of the present disclosure
  • FIG. 2 schematically shows a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure
  • FIG. 3 schematically shows a block diagram of a sense amplifier according to another exemplary embodiment of the present disclosure
  • FIG. 4 schematically shows a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure
  • FIG. 5 schematically shows a circuit diagram of a first NOR gate and/or a second NOR gate according to an exemplary embodiment of the present disclosure
  • FIG. 6 schematically shows a circuit diagram of a first NOR gate and/or a second NOR gate according to another exemplary embodiment of the present disclosure
  • FIG. 7 schematically shows an operation timing diagram of a sense amplifier according to an exemplary embodiment of the present disclosure
  • FIG. 8 shows a schematic diagram of the voltages of the bit line and the reference bit line when the sense amplifier reads the first state of the bit line according to an exemplary embodiment of the present disclosure
  • FIG. 9 shows a schematic diagram of the voltage of the bit line and the reference bit line when the sense amplifier reads the second state of the bit line according to an exemplary embodiment of the present disclosure
  • FIG. 10 schematically shows a flowchart of a control method of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • connection mentioned in the present disclosure may include direct connection and indirect connection.
  • direct connection there are no components between the terminals.
  • the first terminal of switch A is connected to the first terminal of switch B, which can be the connection line between the first terminal of switch A and the first terminal of switch B.
  • wires eg, metal wires
  • the indirect connection other components may exist between the terminals.
  • the first terminal of switch C is connected to the first terminal of switch D, which may be the connection between the first terminal of switch C and the first terminal of switch D.
  • connection line in addition to the connection line, there is at least one other component (eg, switch E, etc.) on the connection line.
  • FIG. 1 schematically shows a schematic diagram of a sense amplifier according to an embodiment of the present disclosure.
  • the bit line BL and the reference bit line BL_B may be precharged to be precharged to VDD/2.
  • the corresponding word line WL is turned on.
  • the low level of the lowest bit A0 of the row address is an even address and a high level is an odd address. It can be specified that the memory cells connected to the bit line BL are opened by the even address after decoding, and the memory cells connected to the reference bit line BL_B are opened by the odd address.
  • the storage voltage and the bit line share the charge, and the bit line BL and the reference bit line BL_B generate a voltage difference.
  • an even address or an odd address is not limited to identification by the lowest bit A0 of the row address, or identification by other bits in the row address, or by performing a specific relationship to at least one bit in the row address. It is not limited in the present invention, and those skilled in the art can set it according to their own needs.
  • the connection between the sense amplifier and the reference bit line BL_B can be cut off in the amplification stage, so as to reduce the power consumption when the bit line BL reads 0.
  • the present disclosure further provides a new sense amplifier.
  • FIG. 2 schematically shows a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • the sense amplifier 2 may include an amplification module 20 and a first switch module 21 .
  • the amplifying module 20 can be used to read the data of the memory cell on the bit line or the reference bit line;
  • the first switch module 21 can be configured to control the amplifying module 20 to disconnect from the reference bit line when the sense amplifier 2 reads the first state for the bit line and the sense amplifier 2 is in the amplification stage; when the sense amplifier 2 reads the first state for the bit line When the two states and the sense amplifier 2 is in the amplification stage, the control amplification module 20 is connected to the reference bit line.
  • reading the first state in the present disclosure generally refers to reading 0, and reading the second state generally refers to reading 1.
  • the first state and the second state may be interchanged as required, and may also be other types of storage states, which are not limited in the present disclosure.
  • the amplifying module By controlling the amplifying module to be disconnected from the reference bit line when the sense amplifier reads the first state for the bit line and the sense amplifier is in the amplification stage, the power consumption of the sense amplifier can be effectively reduced, and the processing speed of the circuit can be improved.
  • the first switch module 21 can control the connection state between the amplification module 20 and the reference bit line based on the voltage transmitted by the bit line and the data source control signal. It is easy to understand that the connection state mentioned here generally refers to two situations: the amplifying module 20 is disconnected from the reference bit line, and the amplifying module 20 is connected to the reference bit line.
  • the data source control signal is used to refer to whether the data of the memory cell on the bit line or the reference bit line is read.
  • the lowest bit A0 of the row address can be used as the data source control signal.
  • the lowest bit A0 of the row address is low level It is an even address, corresponding to opening the storage unit on the bit line; the high level of the lowest bit A0 of the row address is an odd address, corresponding to opening the storage unit on the reference bit line.
  • the data source control signal described in the present disclosure may also be any signal capable of identifying the read bit line or the read reference bit line for storing cell data, which is not limited in the present disclosure.
  • the first switch module 21 may include a first NOR gate and a first switch unit.
  • the first input terminal of the first NOR gate is connected to the amplification module 20 through the first node, and is used for receiving the voltage of the bit line when the sense amplifier 2 is in the amplification stage.
  • the second input terminal of the first NOR gate is used for receiving the above-mentioned data source control signal.
  • the first control end of the first switch unit can be connected to the output end of the first NOR gate, the first end of the first switch unit is connected to the amplifying module 20 through the second node, and the second end of the first switch unit can be connected to the reference. bit line connection. It should be understood that the first switch unit can be used to control the connection state between the amplification module 20 and the reference bit line, and the connection state includes disconnection and connection.
  • the first switch module 21 may further include a second switch unit.
  • the control terminal of the second switch unit is connected to the first node, the first terminal of the second switch unit is connected to the output terminal of the first NOR gate, and the second terminal of the second switch unit is connected to the reference bit line.
  • the first switch unit may further include a second control terminal for receiving the first control signal.
  • the first switch module 21 may be configured to control the connection state of the amplification module 20 and the reference bit line in response to the voltage transmitted by the bit line, the data source control signal and the first control signal.
  • the amplifying module 20 may include a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor, a third PMOS transistor, and a third NMOS transistor.
  • the drain of the first PMOS transistor is connected to the first node, the gate of the first PMOS transistor is connected to the second node; the drain of the first NMOS transistor is connected to the first node, and the gate of the first NMOS transistor is connected to the second node.
  • the gate of the first PMOS tube is connected; the drain of the second PMOS tube is connected to the second node, the gate of the second PMOS tube is connected to the first node; the drain of the second NMOS tube is connected to the second node, and the second The gate of the NMOS tube is connected to the gate of the second PMOS tube; the drain of the third PMOS tube is connected to the source of the first PMOS tube and the source of the second PMOS tube, and the gate of the third PMOS tube is used for receiving For the first control signal, the source of the third PMOS transistor is used to receive the power supply voltage; the drain of the third NMOS transistor is connected to the source of the first NMOS transistor and the source of the second NMOS transistor, and the gate of the third NMOS transistor is connected For receiving the second control signal, the source of the third NMOS transistor is grounded.
  • the first switch unit may include a fourth PMOS transistor.
  • the gate of the fourth PMOS transistor is connected to the output end of the first NOR gate, the drain of the fourth PMOS transistor is connected to the second node, and the source of the fourth PMOS transistor is connected to the reference bit line.
  • the first switch unit may include a fourth NMOS transistor in addition to the fourth PMOS transistor.
  • the gate of the fourth NMOS transistor is used to receive the first control signal, the source of the fourth NMOS transistor is connected to the second node, and the drain of the fourth NMOS transistor is connected to the reference bit line.
  • the sense amplifier 3 may also include a second switch module 31 .
  • the second switch module 31 may be configured to perform: when the sense amplifier 3 reads the first state for the reference bit line and the sense amplifier 3 is in the amplification phase, the control amplification module 20 is disconnected from the bit line; when the sense amplifier 3 is directed to the reference bit line When the second state is read and the sense amplifier 3 is in the amplification stage, the amplification module 20 is controlled to be connected to the bit line.
  • connection state between the amplification module 20 and the bit line can be controlled by the second switch module 31 .
  • the second switch module By configuring the second switch module to control the amplification module to disconnect from the bit line when the sense amplifier reads the first state with respect to the reference bit line and the sense amplifier is in the amplification phase. Since the amplifying module is disconnected from the bit line, the sense amplifier will not amplify the voltage on the bit line in the amplifying stage. Therefore, when the first state is read with reference to the bit line, the power consumption of the sense amplifier will be greatly reduced. In addition, since the voltage on the bit line is not amplified when the first state is read with reference to the bit line, the signal processing speed of the circuit is improved.
  • the second switch module 31 can also be used to read the bit line after the sense amplifier 3 performs the read operation on the bit line. The signal is written back to the memory cell.
  • the second switch module 31 may include an inverter, a second NOR gate and a third switch unit.
  • the input end of the inverter is used for receiving the data source control signal.
  • the first input end of the second NOR gate is connected with the output end of the inverter, and the second input end of the second NOR gate is connected with the amplifying module through the second node.
  • the first control end of the third switch unit is connected to the output end of the second NOR gate, the first end of the third switch unit is connected to the amplifying module 20 through the first node, and the second end of the third switch unit is connected to the bit line .
  • the third switch unit further includes a second control terminal for receiving the first control signal.
  • the second switch module 21 may further include a fourth switch unit.
  • the control terminal of the fourth switch unit is connected to the second node, the first terminal of the fourth switch unit is connected to the output terminal of the second NOR gate, and the second terminal of the fourth switch unit is connected to the bit line.
  • the third switch unit may include a fifth PMOS transistor.
  • the gate of the fifth PMOS transistor is connected to the output end of the second NOR gate, the drain of the fifth PMOS transistor is connected to the first node, and the source of the fifth PMOS transistor is connected to the bit line.
  • the third switch unit may further include a fifth NMOS transistor.
  • the gate of the fifth NMOS transistor is used to receive the first control signal, the source of the fifth NMOS transistor is connected to the first node, and the drain of the fifth NMOS transistor is connected to the bit line.
  • the sense amplifier 3 may further include an isolation unit.
  • the first end of the isolation unit is connected to the second NOR gate, the second end of the isolation unit is grounded, and the control end of the isolation unit is used for receiving the second control signal.
  • the isolation unit can be configured as an NMOS transistor, for example.
  • the above-mentioned various configurations of the sense amplifiers may also include a pre-charging module.
  • the precharge module is configured to precharge the bit line and the reference bit line when the sense amplifier is in the precharge phase.
  • FIG. 4 schematically shows a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • bit line is denoted as BL
  • reference bit line is denoted as BL_B
  • first node is denoted as Q
  • second node is denoted as QB.
  • the first PMOS tube is denoted as P1
  • the first NMOS tube is denoted as N1
  • the second PMOS tube is denoted as P2
  • the second NMOS tube is denoted as N2
  • the third PMOS tube is denoted as P3
  • the third NMOS tube is denoted as N3,
  • the fourth The PMOS transistor is recorded as P4, the fourth NMOS transistor is recorded as N4, the fifth PMOS transistor is recorded as P5, the fifth NMOS transistor is recorded as N5, the first NOR gate is recorded as GNOR1, the second NOR gate is recorded as GNOR2, inverted
  • the device is recorded as INV.
  • the first control signal is referred to as signal SAP
  • the second control signal is referred to as signal SAN.
  • the second switch unit is configured as an NMOS transistor N7
  • the fourth switch unit is configured as an NMOS transistor N6.
  • the precharge module is configured to include NMOS transistors N8, N9 and N10, and the precharge control is performed by the precharge control signal PE.
  • the memory cell on the bit line BL may include an NMOS transistor N11 and a capacitor C1, and by means of the control of the word line WL1, data reading and writing in the capacitor C1 can be realized.
  • the memory cell on the reference bit line BL_B may include an NMOS transistor N12 and a capacitor C2. With the help of the control of the word line WL2, reading and writing of data in the capacitor C2 is realized.
  • the lowest bit A0 of the row address is used as the data source control signal.
  • FIG. 5 schematically shows a circuit diagram of a NOR gate, which can be used to implement the first NOR gate GNOR1 and/or the second NOR gate GNOR2 in the present disclosure.
  • the NOR gate can be configured as a circuit structure including two PMOS transistors and two NMOS transistors, ain and bin represent the two inputs of the first NOR gate GNOR1, and cout represents the first NOR gate GNOR1. output.
  • FIG. 6 schematically shows a circuit diagram of another NOR gate, which can also be used to implement the first NOR gate GNOR1 and/or the second NOR gate GNOR2 in the present disclosure.
  • the NOR gate can be configured as a circuit structure including two PMOS transistors and two NMOS transistors, ain and bin represent the two inputs of the second NOR gate GNOR2, and cout represents the second NOR gate GNOR2 output.
  • the NOR gate shown in FIG. 6 may further include an isolation unit, and the isolation unit may be configured as an NMOS transistor N13, for example, to control the switching state of the isolation unit based on the second control signal SAN .
  • the operation of the sense amplifier to read the bit line may include a precharging stage, a sensing stage and an amplification stage.
  • the first control signal SAP is at a high level
  • the second control signal SAN is at a low level.
  • the transistor P3 and the transistor N3 are turned off, and the transistor N4 and the transistor N5 are turned on.
  • the precharge control signal PE is at a high level to precharge the bit line BL and the reference bit line BL_B. In this case, the first node Q and the second node QB are precharged to VDD/2.
  • the word line WL is at a high level, the memory cell is turned on, and the voltages of the bit line BL and the reference bit line BL_B are transferred to the first node Q and the second node QB for charge sharing.
  • the first control signal SAP is at a low level
  • the second control signal SAN is at a high level
  • the transistor P3 and the transistor N3 are turned on, and the transistor N4 and the transistor N5 are turned off.
  • the sense amplifier can quickly amplify the voltage of the first node Q to a low level, and amplify the voltage of the second node QB to a high level, at this time, the transistor N6 is turned on, the transistor N7 is turned off, and at the same time , the first NOR gate GNOR1 outputs a high level, the second NOR gate GNOR2 outputs a low level, the transistor P4 is turned off, and the transistor P5 is turned on.
  • the first control signal SAP is at a high level
  • the second control signal SAN is at a low level.
  • the transistor P3 and the transistor N3 are turned off, and the transistor N4 and the transistor N5 are turned on.
  • the precharge control signal PE is at a high level to precharge the bit line BL and the reference bit line BL_B. In this case, the first node Q and the second node QB are precharged to VDD/2.
  • the word line WL is at a high level, the memory cell is turned on, and the voltages of the bit line BL and the reference bit line BL_B are transferred to the first node Q and the second node QB for charge sharing.
  • the first control signal SAP is at a low level
  • the second control signal SAN is at a high level
  • the transistor P3 and the transistor N3 are turned on, and the transistor N4 and the transistor N5 are turned off.
  • the sense amplifier can quickly amplify the voltage of the first node Q to a high level, and amplify the voltage of the second node QB to a low level.
  • the transistor N6 is turned off, the transistor N7 is turned on, and at the same time , the first NOR gate GNOR1 outputs a low level, the second NOR gate GNOR2 outputs a low level, the transistor P4 is turned on, and the transistor P5 is turned on. From this, it can be seen that the reference bit line BL_B is connected to the sense amplifier, and the write-back operation of the memory cell on the bit line BL is realized through the transistor P5, that is, 1 is rewritten into the capacitor C1.
  • FIG. 8 shows a schematic diagram of voltages of a bit line and a reference bit line when the sense amplifier reads the first state of the bit line according to an exemplary embodiment of the present disclosure.
  • the reference bit line BL_B when the sense amplifier reads the first state for the bit line BL, the reference bit line BL_B does not participate in the amplification, but keeps the pre-charged voltage VDD/2, and the power supply will not charge the reference bit line BL_B to generate power consumption .
  • FIG. 9 shows a schematic diagram of voltages of a bit line and a reference bit line when the sense amplifier reads the second state of the bit line according to an exemplary embodiment of the present disclosure.
  • the sense amplifier when the sense amplifier reads the second state for the bit line BL, the reference bit line BL_B remains connected to the sense amplifier, and will be discharged to the ground during the amplification stage to be precharged and balanced to VDD/2 in the next cycle, without affecting continuous operation.
  • Table 1 shows the power consumption comparison of the sense amplifier shown in Figure 1 and the sense amplifier shown in Figure 4. It can be seen that, by using the sense amplifier of the exemplary embodiment of the present disclosure, power consumption can be effectively reduced.
  • the sense amplifier of the exemplary embodiment of the present disclosure is described by taking the example of controlling the amplifying module to disconnect from the reference bit line when the bit line reads the first state and is in the amplifying stage.
  • the power consumption of the sense amplifier is greatly reduced, and the signal processing speed of the circuit is improved.
  • the present disclosure also provides a control method for a sense amplifier.
  • FIG. 10 schematically shows a flowchart of a control method of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • control method of the sense amplifier may include the following steps:
  • control method of the sense amplifier may further include: when the sense amplifier reads the first state for the reference bit line and the sense amplifier is in the amplification stage, controlling the sense amplifier to disconnect from the bit line; when the sense amplifier reads the second state for the reference bit line And when the sense amplifier is in the amplification stage, the sense amplifier is controlled to be connected to the bit line.
  • the control method of the sense amplifier of the present disclosure the power consumption of the sense amplifier can be effectively reduced, and the circuit speed can be improved.
  • the present disclosure also provides a memory including the above-mentioned sense amplifier.

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Abstract

一种灵敏放大器（2）、存储器和灵敏放大器（2）的控制方法，涉及半导体存储器技术领域。该灵敏放大器（2）包括：放大模块（20），用于读取位线或参考位线上存储单元的数据；第一开关模块（21），被配置为当灵敏放大器（2）针对位线读第一状态且灵敏放大器（2）处于放大阶段时，控制放大模块（20）与参考位线断开；当灵敏放大器（2）针对位线读第二状态且灵敏放大器（2）处于放大阶段时，控制放大模块（20）与参考位线连接，可以减小灵敏放大器的功耗。

Description

灵敏放大器、存储器和灵敏放大器的控制方法
相关申请的交叉引用
本申请要求于2020年07月27日提交的申请号为202010733096.8、名称为“灵敏放大器、存储器和灵敏放大器的控制方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体存储器技术领域，具体而言，涉及一种灵敏放大器、存储器和灵敏放大器的控制方法。
背景技术
随着手机、平板、个人计算机等电子设备的普及，半导体存储器技术也得到了快速的发展。例如DRAM(Dynamic Random Access Memory，动态随机存取存储器)、SRAM(Static Random-Access Memory，静态随机存取存储器)的存储器由于高密度、低功耗、低价格等优点，已广泛应用于各种电子设备中。
灵敏放大器(Sense Amplifier，简称SA)是半导体存储器的一个重要组成部分，其主要作用是将位线上的小信号进行放大，从而执行读取或写入操作。
功耗作为评价灵敏放大器性能的一个重要指标，直接影响着存储器的应用场景。目前，如何减小灵敏放大器的功耗，已成为亟待解决的问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种灵敏放大器、存储器和灵敏放大器的控制方法，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的灵敏放大器功耗偏高的问题。
根据本公开的第一方面，提供一种灵敏放大器，包括：放大模块，用于读取位线或参考位线上存储单元的数据；第一开关模块，被配置为当灵敏放大器针对位线读第一状态且灵敏放大器处于放大阶段时，控制放大模块与参考位线断开；当灵敏放大器针对位线读第二状态且灵敏放大器处于放大阶段时，控制放大模块与参考位线连接。
可选地，第一开关模块被配置为当灵敏放大器处于放大阶段时，基于位线传输的电压以及数据来源控制信号，控制放大模块与参考位线的连接状态；其中，放大模块与参考位线的连接状态包括放大模块与参考位线断开以及放大模块与参考位线连接。
可选地，第一开关模块包括：第一或非门，第一或非门的第一输入端通过第一节点与放大模块连接，第一或非门的第二输入端用于接收数据来源控制信号；第一开关单元，第 一开关单元的第一控制端与第一或非门的输出端连接，第一开关单元的第一端通过第二节点与放大模块连接，第一开关单元的第二端与参考位线连接。
可选地，第一开关模块还包括：第二开关单元，第二开关单元的控制端与第一节点连接，第二开关单元的第一端与第一或非门的输出端连接，第二开关单元的第二端与参考位线连接。
可选地，第一开关模块基于位线传输的电压以及数据来源控制信号，控制放大模块与参考位线的连接状态，包括：第一开关模块被配置为响应位线传输的电压、数据来源控制信号以及第一控制信号，控制放大模块与参考位线的连接状态；其中，第一开关单元还包括第二控制端，用于接收第一控制信号。
可选地，放大模块包括：第一PMOS管，第一PMOS管的漏极与第一节点连接；第一NMOS管，第一NMOS管的漏极与第一节点连接，第一NMOS管的栅极与第一PMOS管的栅极连接；第二PMOS管，第二PMOS管的漏极与第二节点连接；第二NMOS管，第二NMOS管的漏极与第二节点连接，第二NMOS管的栅极与第二PMOS管的栅极连接；第三PMOS管，第三PMOS管的漏极与第一PMOS管的源极、第二PMOS管的源极连接，第三PMOS管的栅极用于接收第一控制信号，第三PMOS管的源极用于接收电源电压；第三NMOS管，第三NMOS管的漏极与第一NMOS管的源极、第二NMOS管的源极连接，第三NMOS管的栅极用于接收第二控制信号，第三NMOS管的源极接地；其中，第一PMOS管的栅极与第二节点连接，第二PMOS管的栅极与第一节点连接。
可选地，第一开关单元包括：第四PMOS管，第四PMOS管的栅极与第一或非门的输出端连接，第四PMOS管的漏极与第二节点连接，第四PMOS管的源极与参考位线连接。
可选地，第一开关单元包括：第四PMOS管，第四PMOS管的栅极与第一或非门的输出端连接，第四PMOS管的漏极与第二节点连接，第四PMOS管的源极与参考位线连接；第四NMOS管，第四NMOS管的栅极用于接收第一控制信号，第四NMOS管的源极与第二节点连接，第四NMOS管的漏极与参考位线连接。
可选地，灵敏放大器还包括：第二开关模块，被配置为当灵敏放大器针对参考位线读第一状态且灵敏放大器处于放大阶段时，控制放大模块与位线断开；当灵敏放大器针对参考位线读第二状态且灵敏放大器处于放大阶段时，控制放大模块与位线连接。
可选地，第二开关模块包括：反相器，反相器的输入端用于接收数据来源控制信号；第二或非门，第二或非门的第一输入端与反相器的输出端连接，第二或非门的第二输入端通过第二节点与放大模块连接；第三开关单元，第三开关单元的第一控制端与第二或非门的输出端连接，第三开关单元的第一端通过第一节点与放大模块连接，第三开关单元的第二端与位线连接。
可选地，第二开关模块还包括：第四开关单元，第四开关单元的控制端与第二节点连接，第四开关单元的第一端与第二或非门的输出端连接，第四开关单元的第二端与位线连 接。
可选地，第三开关单元还包括：第二控制端，用于接收第一控制信号。
可选地，第三开关单元包括：第五PMOS管，第五PMOS管的栅极与第二或非门的输出端连接，第五PMOS管的漏极与第一节点连接，第五PMOS管的源极与位线连接。
可选地，第三开关单元包括：第五PMOS管，第五PMOS管的栅极与第二或非门的输出端连接，第五PMOS管的漏极与第一节点连接，第五PMOS管的源极与位线连接；第五NMOS管，第五NMOS管的栅极用于接收第一控制信号，第五NMOS管的源极与第一节点连接，第五NMOS管的漏极与位线连接。
可选地，灵敏放大器还包括：预充模块，被配置为当灵敏放大器处于预充阶段时，对位线和参考位线进行预充电。
可选地，读第一状态为读0，读第二状态为读1。
根据本公开的第二方面，提供一种存储器，包括如上述任意一种的灵敏放大器。
根据本公开的第三方面，提供一种灵敏放大器的控制方法，包括：当灵敏放大器针对位线读第一状态且灵敏放大器处于放大阶段时，控制灵敏放大器与参考位线断开；当灵敏放大器针对位线读第二状态且灵敏放大器处于放大阶段时，控制灵敏放大器与参考位线连接。
在本公开的一些实施例所提供的技术方案中，第一开关模块被配置为当灵敏放大器针对位线读第一状态且灵敏放大器处于放大阶段时，控制放大模块与参考位线断开。由于放大模块与参考位线断开，在放大阶段，灵敏放大器不会对参考位线上的电压进行放大，因此，在位线读第一状态时，将极大地减小灵敏放大器的功耗。另外，由于在位线读第一状态时，本公开方案不进行参考位线上电压的放大，因此，电路的信号处理速度得到了提升。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1示意性示出了根据本公开一个实施例的灵敏放大器的示意图；
图2示意性示出了根据本公开的示例性实施方式的灵敏放大器的框图；
图3示意性示出了根据本公开另一示例性实施方式的灵敏放大器的框图；
图4示意性示出了根据本公开示例性实施方式的灵敏放大器的电路图；
图5示意性示出了根据本公开示例性实施方式的第一或非门和/或第二或非门的电路图；
图6示意性示出了根据本公开另一示例性实施方式的第一或非门和/或第二或非门的电路图；
图7示意性示出了根据本公开示例性实施方式的灵敏放大器的工作时序图；
图8示出了根据本公开示例性实施方式的灵敏放大器在位线读第一状态时位线和参考位线的电压示意图；
图9示出了根据本公开示例性实施方式的灵敏放大器在位线读第二状态时位线和参考位线的电压示意图；
图10示意性示出了根据本公开的示例性实施方式的灵敏放大器的控制方法的流程图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。“第一”、“第二”、“第三”、“第四”、“第五”的描述仅是为了区分，不应作为本公开的限制。
需要说明的是，本公开所说的术语“连接”，可以包括直接连接和间接连接。在直接连接中，端与端之间没有元器件，例如，开关A的第一端与开关B的第一端连接，可以是在开关A的第一端与开关B的第一端的连接线路上，只有连接线(如，金属线)，而不存在其他元器件。在间接连接中，端与端之间可以存在其他元器件，例如，开关C的第一端与开关D的第一端连接，可以是在开关C的第一端与开关D的第一端的连接线路上，除连接线外，连接线上还存在至少一个其他元器件(如，开关E等)。
图1示意性示出了根据本公开一个实施例的灵敏放大器的示意图。
参考图1，在读取位线上存储单元中数据的过程中，首先，可以对位线BL和参考位线BL_B进行预充电，使它们被预充电至VDD/2。接下来，地址被译码后打开对应字线WL，例如，行地址最低位A0低电平为偶地址，高电平为奇地址。可以规定经地址译码后的偶地址打开的是连接在位线BL上的存储单元，奇地址打开的是连接在参考位线BL_B上的存储单元。随后，存储电压与位线进行电荷共享，位线BL与参考位线BL_B产生电压差。然后，在放大阶段，无论是读0还是读1，电源VDD均会做功，将一侧位线电压拉升至VDD，另一侧位线被GND拉低至零。需要注意的是，确定偶地址还是奇 地址也不限定是通过行地址最低位A0来识别，也可以是通过行地址中其他位来识别，还可以是通过对行地址中至少一位进行特定关系的处理后得出的结果来识别，本发明对此不做限定，本领域内技术人员可根据需要自行设定。
在针对位线BL读0时，因为参考位线BL_B不进行对存储单元回写的操作，参考位线BL_B的电压可以不用放大到VDD，也就是说，参考位线BL_B放大后的电位不会影响数据的读出。因此，可以在放大阶段切断灵敏放大器与参考位线BL_B的连接，以降低位线BL读0时的功耗。
鉴于此，本公开又提供了一种新的灵敏放大器。
图2示意性示出了根据本公开的示例性实施方式的灵敏放大器的框图。参考图2，灵敏放大器2可以包括放大模块20和第一开关模块21。
放大模块20可以用于读取位线或参考位线上存储单元的数据；
第一开关模块21可以被配置为：当灵敏放大器2针对位线读第一状态且灵敏放大器2处于放大阶段时，控制放大模块20与参考位线断开；当灵敏放大器2针对位线读第二状态且灵敏放大器2处于放大阶段时，控制放大模块20与参考位线连接。
应当理解的是，本公开所述的读第一状态通常指代读0，读第二状态通常指代读1。然而，第一状态和第二状态可以根据需要互换，也还可以是其他类型的存储状态，本公开对此不进行限定。
通过当灵敏放大器针对位线读第一状态且灵敏放大器处于放大阶段时控制放大模块与参考位线断开，可以有效减小灵敏放大器的功耗，并提升电路的处理速度。
具体的，当灵敏放大器2处于放大阶段时，第一开关模块21可以基于位线传输的电压以及数据来源控制信号，控制放大模块20与参考位线的连接状态。容易理解的是，这里所说的连接状态通常指两种情况：放大模块20与参考位线断开，以及放大模块20与参考位线连接。
其中，数据来源控制信号用于指代读取的是位线还是参考位线上存储单元的数据，通常可以将行地址最低位A0作为数据来源控制信号，例如，行地址最低位A0低电平为偶地址，对应打开位线上的存储单元；行地址最低位A0高电平为奇地址，对应打开参考位线上的存储单元。然而，应当注意的是，本公开所述的数据来源控制信号还可以是能识别出读取位线还是读取参考位线上存储单元数据的任意信号，本公开对此不做限制。
第一开关模块21可以包括第一或非门和第一开关单元。
具体的，第一或非门的第一输入端通过第一节点与放大模块20连接，用于当灵敏放大器2处于放大阶段时接收位线的电压。第一或非门的第二输入端用于接收上述数据来源控制信号。
第一开关单元的第一控制端可以与第一或非门的输出端连接，第一开关单元的第一端通过第二节点与放大模块20连接，第一开关单元的第二端可以与参考位线连接。应当理解的是，第一开关单元可以用于控制放大模块20与参考位线的连接状态，该连接状态包 括断开和连接。
另外，第一开关模块21还可以包括第二开关单元。
第二开关单元的控制端与第一节点连接，第二开关单元的第一端与第一或非门的输出端连接，第二开关单元的第二端与参考位线连接。
根据本公开的一些实施例，第一开关单元除包括第一控制端外，还可以包括第二控制端，用于接收第一控制信号。在这种情况下，第一开关模块21可以被配置为响应位线传输的电压、数据来源控制信号和第一控制信号，控制放大模块20与参考位线的连接状态。
在本公开的示例性实施方式中，放大模块20可以包括第一PMOS管、第一NMOS管、第二PMOS管、第二NMOS管、第三PMOS管和第三NMOS管。
具体的，第一PMOS管的漏极与第一节点连接，第一PMOS管的栅极与第二节点连接；第一NMOS管的漏极与第一节点连接，第一NMOS管的栅极与第一PMOS管的栅极连接；第二PMOS管的漏极与第二节点连接，第二PMOS管的栅极与第一节点连接；第二NMOS管的漏极与第二节点连接，第二NMOS管的栅极与第二PMOS管的栅极连接；第三PMOS管的漏极与第一PMOS管的源极、第二PMOS管的源极连接，第三PMOS管的栅极用于接收第一控制信号，第三PMOS管的源极用于接收电源电压；第三NMOS管的漏极与第一NMOS管的源极、第二NMOS管的源极连接，第三NMOS管的栅极用于接收第二控制信号，第三NMOS管的源极接地。
根据本公开的一个实施例，第一开关单元可以包括第四PMOS管。其中，第四PMOS管的栅极与第一或非门的输出端连接，第四PMOS管的漏极与第二节点连接，第四PMOS管的源极与参考位线连接。
根据本公开的另一个实施例，第一开关单元除包括第四PMOS管外，还可以包括第四NMOS管。其中，第四NMOS管的栅极用于接收第一控制信号，第四NMOS管的源极与第二节点连接，第四NMOS管的漏极与参考位线连接。
参考图3，灵敏放大器3除了包括上面描述的第一开关模块21和放大模块20外，还可以包括第二开关模块31。第二开关模块31可以被配置为执行：当灵敏放大器3针对参考位线读第一状态且灵敏放大器3处于放大阶段时，控制放大模块20与位线断开；当灵敏放大器3针对参考位线读第二状态且灵敏放大器3处于放大阶段时，控制放大模块20与位线连接。
也就是说，与第一开关模块21类似的，通过第二开关模块31可以控制放大模块20与位线的连接状态。
通过将第二开关模块配置为当灵敏放大器针对参考位线读第一状态且灵敏放大器处于放大阶段时，控制放大模块与位线断开。由于放大模块与位线断开，在放大阶段，灵敏放大器不会对位线上的电压进行放大，因此，在参考位线读第一状态时，将极大地减小灵敏放大器的功耗。另外，由于在参考位线读第一状态时，不进行位线上电压的放大，因此，电路的信号处理速度得到了提升。
另外，在利用第一开关模块21控制放大模块与参考位线的连接状态的情况下，第二开关模块31还可以用于在灵敏放大器3执行针对位线的读操作后，将读取到的信号回写至存储单元。
第二开关模块31可以包括反相器、第二或非门和第三开关单元。
其中，反相器的输入端用于接收数据来源控制信号。第二或非门的第一输入端与反相器的输出端连接，第二或非门的第二输入端通过第二节点与放大模块连接。第三开关单元的第一控制端与第二或非门的输出端连接，第三开关单元的第一端通过第一节点与放大模块20连接，第三开关单元的第二端与位线连接。
在一些实施例中，第三开关单元还包括第二控制端，用于接收第一控制信号。
另外，第二开关模块21还可以包括第四开关单元。
第四开关单元的控制端与第二节点连接，第四开关单元的第一端与第二或非门的输出端连接，第四开关单元的第二端与位线连接。
根据本公开的一个实施例，第三开关单元可以包括第五PMOS管。其中，第五PMOS管的栅极与第二或非门的输出端连接，第五PMOS管的漏极与第一节点连接，第五PMOS管的源极与位线连接。
根据本公开的另一个实施例，第三开关单元除包括第五PMOS管外，还可以包括第五NMOS管。其中，第五NMOS管的栅极用于接收第一控制信号，第五NMOS管的源极与第一节点连接，第五NMOS管的漏极与位线连接。
此外，灵敏放大器3还可以包括隔离单元。该隔离单元的第一端与第二或非门连接，隔离单元的第二端接地，隔离单元的控制端用于接收第二控制信号。具体的，隔离单元作为一个开关单元，可以例如被配置为NMOS管。
可以理解的是，上述各种配置的灵敏放大器，还可以包括预充模块。该预充模块被配置为当灵敏放大器处于预充阶段时，对位线和参考位线进行预充电。
图4示意性示出了根据本公开示例性实施方式的灵敏放大器的电路图。
在图4所示的实施例中，位线记为BL、参考位线记为BL_B、第一节点记为Q、第二节点记为QB。
第一PMOS管记为P1、第一NMOS管记为N1、第二PMOS管记为P2、第二NMOS管记为N2、第三PMOS管记为P3、第三NMOS管记为N3、第四PMOS管记为P4、第四NMOS管记为N4、第五PMOS管记为P5、第五NMOS管记为N5、第一或非门记为GNOR1、第二或非门记为GNOR2、反相器记为INV。另外，第一控制信号记为信号SAP、第二控制信号记为信号SAN。
第二开关单元被配置为NMOS晶体管N7，第四开关单元被配置为NMOS晶体管N6。
预充模块被配置为包括NMOS晶体管N8、N9和N10，通过预充控制信号PE进行预充控制。
此外，位线BL上存储单元可以包括NMOS晶体管N11和电容C1，借助于字线WL1 的控制，实现电容C1中数据的读写。参考位线BL_B上存储单元可以包括NMOS晶体管N12和电容C2，借助于字线WL2的控制，实现电容C2中数据的读写。
在图4所示的实例中，将行地址最低位A0作为数据来源控制信号。
应当理解的是，图4所示电路中元器件的配置仅是示例性描绘，其中涉及的具有开关功能的元件均可以被配置为NMOS晶体管、PMOS晶体管或传输门，本公开对此不做限制。
图5示意性示出了一种或非门的电路图，该或非门可以用来实现本公开中的第一或非门GNOR1和/或第二或非门GNOR2。参考图5，该或非门可以被配置为包括两个PMOS管和两个NMOS管的电路结构，ain和bin表示第一或非门GNOR1的两个输入，cout表示第一或非门GNOR1的输出。
图6示意性示出了另一种或非门的电路图，也可以利用该或非门来实现本公开中的第一或非门GNOR1和/或第二或非门GNOR2。参考图6，该或非门可以被配置为包括两个PMOS管和两个NMOS管的电路结构，ain和bin表示第二或非门GNOR2的两个输入，cout表示第二或非门GNOR2的输出。
区别于图5所示的或非门，图6所示的或非门还可以包括隔离单元，该隔离单元可以例如被配置为NMOS晶体管N13，基于第二控制信号SAN来控制隔离单元的开关状态。
灵敏放大器读取位线的操作可以包括预充阶段、感应阶段和放大阶段。
下面以行地址最低位A0低电平时打开位线BL上存储单元为例，结合图7的时序图，对如图4所示的本公开示例性实施方式的灵敏放大器的工作过程进行说明。
读第一状态：
在预充阶段，第一控制信号SAP为高电平、第二控制信号SAN为低电平。晶体管P3和晶体管N3关断，晶体管N4和晶体管N5导通。预充控制信号PE为高电平，对位线BL和参考位线BL_B进行预充电。在这种情况下，第一节点Q和第二节点QB会被预充至VDD/2。
在感应阶段，字线WL为高电平，存储单元打开，位线BL和参考位线BL_B的电压被传输至第一节点Q和第二节点QB，进行电荷共享。
在放大阶段，第一控制信号SAP为低电平、第二控制信号SAN为高电平。晶体管P3和晶体管N3导通，晶体管N4和晶体管N5关断。在这种情况下，灵敏放大器可以迅速将第一节点Q的电压放大到低电平，将第二节点QB的电压放大到高电平，此时，晶体管N6导通，晶体管N7关断，同时，第一或非门GNOR1输出高电平，第二或非门GNOR2输出低电平，晶体管P4关断，晶体管P5导通。由此，可以看出，参考位线BL_B与灵敏放大器断开连接，通过晶体管P5和晶体管N6实现位线BL上存储单元的回写操作，即将0重新写入电容C1。
读第二状态：
在预充阶段，第一控制信号SAP为高电平、第二控制信号SAN为低电平。晶体管 P3和晶体管N3关断，晶体管N4和晶体管N5导通。预充控制信号PE为高电平，对位线BL和参考位线BL_B进行预充电。在这种情况下，第一节点Q和第二节点QB会被预充至VDD/2。
在感应阶段，字线WL为高电平，存储单元打开，位线BL和参考位线BL_B的电压被传输至第一节点Q和第二节点QB，进行电荷共享。
在放大阶段，第一控制信号SAP为低电平、第二控制信号SAN为高电平。晶体管P3和晶体管N3导通，晶体管N4和晶体管N5关断。在这种情况下，灵敏放大器可以迅速将第一节点Q的电压放大到高电平，将第二节点QB的电压放大到低电平，此时，晶体管N6关断，晶体管N7导通，同时，第一或非门GNOR1输出低电平，第二或非门GNOR2输出低电平，晶体管P4导通，晶体管P5导通。由此，可以看出，参考位线BL_B与灵敏放大器连接，通过晶体管P5实现位线BL上存储单元的回写操作，即将1重新写入电容C1。
虽然上面以行地址最低位A0低电平时打开位线BL上存储单元为例进行说明，然而，本领域技术人员基于本公开的示例性方案可以联想到包含在本公开内容之内的其他方式。
图8示出了根据本公开示例性实施方式的灵敏放大器在位线读第一状态时位线和参考位线的电压示意图。
参考图8，在灵敏放大器针对位线BL读第一状态时，参考位线BL_B不参与放大，而一直保持预充时的电压VDD/2，电源不会对参考位线BL_B充电而产生功耗。
图9示出了根据本公开示例性实施方式的灵敏放大器在位线读第二状态时位线和参考位线的电压示意图。
参考图9，在灵敏放大器针对位线BL读第二状态时，参考位线BL_B与灵敏放大器保持连接，在放大阶段会对地放电，以在下个周期被预充平衡至VDD/2，不影响连续操作。
表1示出了图1所示灵敏放大器与图4所示灵敏放大器的功耗比对情况。可见，采用本公开示例性实施方式的灵敏放大器，可以有效减小功耗。
表1
Figure PCTCN2020139315-appb-000001
应当理解的是，在上面的描述中，以位线读第一状态且处于放大阶段时控制放大模块与参考位线断开为例，对本公开示例性实施方式的灵敏放大器进行说明。然而，如上面提 及的，基于本公开示例性实施方式的灵敏放大器，还可以在参考位线读第一状态且处于放大阶段时，控制放大模块与位线断开。由此，极大地减小灵敏放大器的功耗，并提升电路的信号处理速度。
进一步的，本公开还提供了一种灵敏放大器的控制方法。
图10示意性示出了根据本公开的示例性实施方式的灵敏放大器的控制方法的流程图。
参考图10，灵敏放大器的控制方法可以包括以下步骤：
S102.当灵敏放大器针对位线读第一状态且灵敏放大器处于放大阶段时，控制灵敏放大器与参考位线断开；
S104.当灵敏放大器针对位线读第二状态且灵敏放大器处于放大阶段时，控制灵敏放大器与参考位线连接。
此外，灵敏放大器的控制方法还可以包括：当灵敏放大器针对参考位线读第一状态且灵敏放大器处于放大阶段时，控制灵敏放大器与位线断开；当灵敏放大器针对参考位线读第二状态且灵敏放大器处于放大阶段时，控制灵敏放大器与位线连接。
本公开实现灵敏放大器的控制方法的过程在对灵敏放大器的描述中已进行了说明，在此不再赘述。
通过本公开的灵敏放大器的控制方法，可以有效减小灵敏放大器的功耗，并提升电路速度。
进一步的，本公开还提供了一种存储器，该存储器包括上述灵敏放大器。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。

Claims (18)

  1. 一种灵敏放大器，包括：
    放大模块，用于读取位线或参考位线上存储单元的数据；
    第一开关模块，被配置为当所述灵敏放大器针对所述位线读第一状态且所述灵敏放大器处于放大阶段时，控制所述放大模块与所述参考位线断开；当所述灵敏放大器针对所述位线读第二状态且所述灵敏放大器处于放大阶段时，控制所述放大模块与所述参考位线连接。
  2. 根据权利要求1所述的灵敏放大器，其中，所述第一开关模块被配置为当所述灵敏放大器处于放大阶段时，基于所述位线传输的电压以及数据来源控制信号，控制所述放大模块与所述参考位线的连接状态；
    其中，所述放大模块与所述参考位线的连接状态包括所述放大模块与所述参考位线断开以及所述放大模块与所述参考位线连接。
  3. 根据权利要求2所述的灵敏放大器，其中，所述第一开关模块包括：
    第一或非门，所述第一或非门的第一输入端通过第一节点与所述放大模块连接，所述第一或非门的第二输入端用于接收所述数据来源控制信号；
    第一开关单元，所述第一开关单元的第一控制端与所述第一或非门的输出端连接，所述第一开关单元的第一端通过第二节点与所述放大模块连接，所述第一开关单元的第二端与所述参考位线连接。
  4. 根据权利要求3所述的灵敏放大器，其中，所述第一开关模块还包括：
    第二开关单元，所述第二开关单元的控制端与所述第一节点连接，所述第二开关单元的第一端与所述第一或非门的输出端连接，所述第二开关单元的第二端与所述参考位线连接。
  5. 根据权利要求3所述的灵敏放大器，其中，所述第一开关模块基于所述位线传输的电压以及所述数据来源控制信号，控制所述放大模块与所述参考位线的连接状态，包括：
    所述第一开关模块被配置为响应所述位线传输的电压、所述数据来源控制信号以及第一控制信号，控制所述放大模块与所述参考位线的连接状态；
    其中，所述第一开关单元还包括第二控制端，用于接收所述第一控制信号。
  6. 根据权利要求1所述的灵敏放大器，其中，所述放大模块包括：
    第一PMOS管，所述第一PMOS管的漏极与第一节点连接；
    第一NMOS管，所述第一NMOS管的漏极与所述第一节点连接，所述第一NMOS管的栅极与所述第一PMOS管的栅极连接；
    第二PMOS管，所述第二PMOS管的漏极与第二节点连接；
    第二NMOS管，所述第二NMOS管的漏极与所述第二节点连接，所述第二NMOS管的栅极与所述第二PMOS管的栅极连接；
    第三PMOS管，所述第三PMOS管的漏极与所述第一PMOS管的源极、所述第二PMOS管的源极连接，所述第三PMOS管的栅极用于接收第一控制信号，所述第三PMOS管的源极用于接收电源电压；
    第三NMOS管，所述第三NMOS管的漏极与所述第一NMOS管的源极、所述第二NMOS管的源极连接，所述第三NMOS管的栅极用于接收第二控制信号，所述第三NMOS管的源极接地；
    其中，所述第一PMOS管的栅极与所述第二节点连接，所述第二PMOS管的栅极与所述第一节点连接。
  7. 根据权利要求3所述的灵敏放大器，其中，所述第一开关单元包括：
    第四PMOS管，所述第四PMOS管的栅极与所述第一或非门的输出端连接，所述第四PMOS管的漏极与所述第二节点连接，所述第四PMOS管的源极与所述参考位线连接。
  8. 根据权利要求5所述的灵敏放大器，其中，所述第一开关单元包括：
    第四PMOS管，所述第四PMOS管的栅极与所述第一或非门的输出端连接，所述第四PMOS管的漏极与所述第二节点连接，所述第四PMOS管的源极与所述参考位线连接；
    第四NMOS管，所述第四NMOS管的栅极用于接收所述第一控制信号，所述第四NMOS管的源极与所述第二节点连接，所述第四NMOS管的漏极与所述参考位线连接。
  9. 根据权利要求1所述的灵敏放大器，其中，所述灵敏放大器还包括：
    第二开关模块，被配置为当所述灵敏放大器针对所述参考位线读第一状态且所述灵敏放大器处于放大阶段时，控制所述放大模块与所述位线断开；当所述灵敏放大器针对所述参考位线读第二状态且所述灵敏放大器处于放大阶段时，控制所述放大模块与所述位线连接。
  10. 根据权利要求9所述的灵敏放大器，其中，所述第二开关模块包括：
    反相器，所述反相器的输入端用于接收数据来源控制信号；
    第二或非门，所述第二或非门的第一输入端与所述反相器的输出端连接，所述第二或非门的第二输入端通过第二节点与所述放大模块连接；
    第三开关单元，所述第三开关单元的第一控制端与所述第二或非门的输出端连接，所述第三开关单元的第一端通过第一节点与所述放大模块连接，所述第三开关单元的第二端与所述位线连接。
  11. 根据权利要求10所述的灵敏放大器，其中，所述第二开关模块还包括：
    第四开关单元，所述第四开关单元的控制端与所述第二节点连接，所述第四开关单元的第一端与所述第二或非门的输出端连接，所述第四开关单元的第二端与所述位线连接。
  12. 根据权利要求10所述的灵敏放大器，其中，所述第三开关单元还包括：
    第二控制端，用于接收第一控制信号。
  13. 根据权利要求10所述的灵敏放大器，其中，所述第三开关单元包括：
    第五PMOS管，所述第五PMOS管的栅极与所述第二或非门的输出端连接，所述第 五PMOS管的漏极与所述第一节点连接，所述第五PMOS管的源极与所述位线连接。
  14. 根据权利要求12所述的灵敏放大器，其中，所述第三开关单元包括：
    第五PMOS管，所述第五PMOS管的栅极与所述第二或非门的输出端连接，所述第五PMOS管的漏极与所述第一节点连接，所述第五PMOS管的源极与所述位线连接；
    第五NMOS管，所述第五NMOS管的栅极用于接收所述第一控制信号，所述第五NMOS管的源极与所述第一节点连接，所述第五NMOS管的漏极与所述位线连接。
  15. 根据权利要求1所述的灵敏放大器，其中，所述灵敏放大器还包括：
    预充模块，被配置为当所述灵敏放大器处于预充阶段时，对所述位线和所述参考位线进行预充电。
  16. 根据权利要求1所述的灵敏放大器，其中，所述读第一状态为读0，所述读第二状态为读1。
  17. 一种存储器，包括如权利要求1所述的灵敏放大器。
  18. 一种灵敏放大器的控制方法，包括：
    当所述灵敏放大器针对位线读第一状态且所述灵敏放大器处于放大阶段时，控制所述灵敏放大器与参考位线断开；
    当所述灵敏放大器针对位线读第二状态且所述灵敏放大器处于放大阶段时，控制所述灵敏放大器与参考位线连接。
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