WO2023202166A1 - 一种位线读取电路、存储器及电子设备 - Google Patents

一种位线读取电路、存储器及电子设备 Download PDF

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Publication number
WO2023202166A1
WO2023202166A1 PCT/CN2023/070713 CN2023070713W WO2023202166A1 WO 2023202166 A1 WO2023202166 A1 WO 2023202166A1 CN 2023070713 W CN2023070713 W CN 2023070713W WO 2023202166 A1 WO2023202166 A1 WO 2023202166A1
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Prior art keywords
transistor
bit line
line
switch
electrode
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PCT/CN2023/070713
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English (en)
French (fr)
Inventor
殷士辉
景蔚亮
季秉武
卜思童
王正波
廖恒
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华为技术有限公司
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Publication of WO2023202166A1 publication Critical patent/WO2023202166A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Definitions

  • the present application relates to the field of circuit technology, and in particular, to a bit line reading circuit, memory and electronic equipment.
  • DRAM Dynamic Random Access Memory
  • CPU Central Processing Unit
  • hard disks external memories
  • 1TnC-based ferroelectric memory FeRAM
  • FeRAM Feroelectric Random Access Memory
  • the information of the ferroelectric capacitor can be amplified and read out through the voltage change caused by the charge change on the bit line BL and through the sense amplifier (Sense amplifier, SA).
  • the change in the charge on the bit line BL mainly comes from the polarization charge released when the non-volatile ferroelectric capacitor is subjected to a voltage exceeding the coercive field strength.
  • the unselected ferroelectric capacitor will bear the "half-select" applied voltage V w /2 during the reading and writing process, that is, half of the voltage V w that the selected ferroelectric capacitor bears.
  • V w /2 is less than the coercive field voltage V c , so the unselected ferroelectric capacitor does not release significant polarization charge.
  • the node FN in the selected ferroelectric memory cell is because Connected to the sensitive amplifier, it will be in a voltage state of 0 or V w for a long time, while the unselected plate line PL is at V w /2, so the unselected ferroelectric capacitors in the ferroelectric memory unit (such as C2 ⁇ Cn in Figure 1 ) will be in the "half-selected" voltage state.
  • DDR Double Data Rate
  • This application provides a bit line reading circuit, memory and electronic equipment, which are used to improve the long-term "half-selected" state of the ferroelectric capacitor during the reading and writing process of the 1TnC ferroelectric memory.
  • inventions of the present application provide a bit line reading circuit.
  • the bit line reading circuit is used to read the level from a ferroelectric memory cell.
  • the bit line reading circuit may include a bit line and a reference line. , precharge battery, sense amplifier, first switch and second switch.
  • the bit line is connected to the ferroelectric memory cell.
  • the ferroelectric memory unit generally includes n ferroelectric capacitors and a transistor, where n is an integer greater than or equal to 2.
  • the gate of the transistor is connected to the word line, and the first electrode of the transistor is connected to the bit line.
  • the second electrode of the transistor is connected to one end of each ferroelectric capacitor among the n ferroelectric capacitors, and the other end of each ferroelectric capacitor is connected to a corresponding plate line.
  • the sensitive amplifier is connected to the bit line and the reference line respectively, and is used to differentially amplify the voltage on the bit line and the reference line;
  • the precharge circuit is connected to the bit line and the reference line respectively, and is used to precharge the bit line and the reference line;
  • the second A switch is connected to the bit line between the sense amplifier and the precharge circuit, and is used to turn on or off the bit line between the sense amplifier and the precharge circuit;
  • the second switch is connected to the reference line between the sense amplifier and the precharge circuit. On the line, it is used to connect or disconnect the reference line between the sense amplifier and the precharge circuit. In this way, when the bit line read circuit is in the read and write stage, the sense amplifier operates normally.
  • the first switch disconnects the bit line between the sense amplifier and the precharge circuit
  • the second switch disconnects the bit line between the sense amplifier and the precharge circuit.
  • the reference line is disconnected so that the bit line can be pulled by the precharge circuit to the same voltage as the plate line to which the unselected ferroelectric capacitor is connected in the ferroelectric memory cell, e.g. The voltage is V w /2, then the bit line is pulled to V w /2 by the precharge circuit, so that the voltage at both ends of the unselected ferroelectric capacitor is the same, so that it will not be in the "half-selected" state during the read and write stage. This in turn can reduce the time the ferroelectric capacitor is in the "half-selected" state.
  • connection position of the precharge circuit on the bit line is closer to the ferroelectric memory unit, that is, the information of the ferroelectric memory unit is first transmitted to the ferroelectric memory unit through the bit line.
  • the precharge circuit is then transmitted to the sense amplifier through the first switch; correspondingly, the signal charged to the reference line by the precharge circuit needs to be transmitted to the sense amplifier through the second switch.
  • the first switch may include a first transistor, the gate of the first transistor is connected to the first isolation control line, and the first pole and the second pole of the first transistor are connected to the sensitive
  • the first isolation control line controls the first switch to turn on
  • one end of the bit line close to the precharge circuit and one end of the bit line close to the sensitive amplifier are connected, and signals can be realized at both ends.
  • transmission when the first isolation control line controls the first switch to turn off, the end of the bit line close to the precharge circuit is disconnected from the end of the bit line close to the sensitive amplifier, and signal transmission cannot be realized between the two ends, thereby separating the precharge circuit from the Sensitive amplifier is isolated.
  • the first transistor may be a P-type transistor or an N-type transistor, which is not limited here.
  • the first transistor is a P-type transistor
  • the first transistor is turned on when the first isolation control line is at a low level, and is turned off when the first isolation control line is at a high level
  • the first transistor is an N-type transistor
  • the first transistor is turned on when the first isolation control line is at a high level.
  • the first isolation control line is at a high level
  • the first transistor is turned on, and when the first isolation control line is at a low level, the first transistor is turned off.
  • the above is only an example to illustrate the specific structure of the first switch.
  • the specific structure of the first switch is not limited to the above-mentioned structure provided in the embodiment of the present application, and can also be other structures known to those skilled in the art, which are not limited here. .
  • the second switch may include a second transistor, the gate of the second transistor is connected to the second isolation control line, and the first and second poles of the second transistor are connected to the reference between the sense amplifier and the precharge circuit.
  • the second isolation control line controls the second switch to turn on
  • the end of the reference line close to the precharge circuit and the end of the reference line close to the sense amplifier are connected, and signal transmission can be realized at both ends.
  • the second isolation control line controls When the second switch is turned off, the end of the reference line close to the precharge circuit is disconnected from the end of the reference line close to the sense amplifier, and no signal can be transmitted between the two ends, thereby isolating the precharge circuit from the sense amplifier.
  • the second transistor may be a P-type transistor or an N-type transistor, which is not limited here.
  • the second transistor is a P-type transistor
  • the second transistor is turned on when the second isolation control line is at a low level, and is turned off when the second isolation control line is at a high level;
  • the second transistor is an N-type transistor, the second transistor is turned on when the second isolation control line is at a high level.
  • the second isolation control line is at a high level, the second transistor is turned on, and when the second isolation control line is at a low level, the second transistor is turned off.
  • the above is only an example to illustrate the specific structure of the second switch.
  • the specific structure of the second switch is not limited to the above-mentioned structure provided in the embodiment of the present application, and can also be other structures known to those skilled in the art, which are not limited here. .
  • both the first transistor and the second transistor are N-type transistors.
  • the first transistor and the second transistor can also be both P-type transistors.
  • the first isolation control line and the second isolation control line may be the same control line, that is, the first transistor and the second transistor They are controlled by the same isolated control line at the same time, thereby reducing the number of control lines.
  • the first transistor and the second transistor can be controlled synchronously without the need for additional synchronous control circuits, thus simplifying the circuit structure.
  • the differential input of the sense amplifier is connected to the bit line and the reference line respectively, and the differential output of the sense amplifier is connected to the bit line and the reference line respectively to differentially amplify the voltages on the bit line and the reference line.
  • the sense amplifier may include: an N-type third transistor, an N-type fourth transistor, a P-type fifth transistor, and a P-type sixth transistor; wherein: a first electrode of the third transistor is connected to the bit line. , the second electrode of the third transistor is connected to the first reference voltage source, the gate electrode of the third transistor is connected to the reference line; the first electrode of the fourth transistor is connected to the reference line, and the second electrode of the fourth transistor is connected to the first reference line.
  • the voltage source is connected, the gate electrode of the fourth transistor is connected to the bit line; the first electrode of the fifth transistor is connected to the bit line, the second electrode of the fifth transistor is connected to the second reference voltage source, and the gate electrode of the fifth transistor is connected to the reference voltage source.
  • the first electrode of the sixth transistor is connected to the reference line, the second electrode of the sixth transistor is connected to the second reference voltage source, and the gate electrode of the sixth transistor is connected to the bit line.
  • the precharge circuit may include: a seventh transistor and an eighth transistor. Among them: the first electrode of the seventh transistor is connected to the bit line, the second electrode of the seventh transistor is connected to the precharge voltage source, the gate electrode of the seventh transistor is connected to the precharge control line; the first electrode of the eighth transistor is connected to the precharge control line.
  • the charging voltage source is connected, the second electrode of the eighth transistor is connected to the reference line, and the gate electrode of the eighth transistor is connected to the precharge control line.
  • the precharge circuit may further include a ninth transistor.
  • the first electrode of the ninth transistor is connected to the bit line
  • the second electrode of the ninth transistor is connected to the reference line
  • the gate electrode of the ninth transistor is connected to the precharge control line.
  • the turned-on ninth transistor can further ensure that the voltages on the bit line and the reference line are equal.
  • the seventh transistor, the eighth transistor and the ninth transistor in the precharge circuit are all N-channel transistors or are all P-channel transistors, which is not limited here.
  • the bit line reading circuit provided by the embodiment of the present application may also include a selection circuit; the selection circuit is connected to the bit line and the reference line, and is used to read the data on the bit line and the reference line, or to Lines and reference lines write data.
  • the bit line reading circuit of the present application can not only output data, but also write data.
  • the selection circuit may include a tenth transistor and an eleventh transistor.
  • the first electrode of the tenth transistor is used to write data or read data
  • the second electrode of the tenth transistor is connected to the bit line
  • the gate electrode of the tenth transistor is connected to the first selection control line
  • the first electrode of the eleventh transistor is connected to the bit line.
  • the second electrode of the eleventh transistor is connected to the reference line
  • the gate electrode of the eleventh transistor is connected to the second selection control line.
  • the first selection control line controls the tenth transistor to turn on, so that data is written to the bit line or data on the bit line is read through the turned on tenth transistor.
  • the second selection control line controls the eleventh transistor to be turned on, so that data is written to the reference line or data on the reference line is read through the turned-on eleventh transistor.
  • the reference line connected to the bit line reading circuit can be a complementary bit line.
  • the selected bit line and the ferroelectric memory cell connected to the complementary bit line are not connected to the same word line, so that when When the bit line reading circuit reads the selected bit line, the voltage of the complementary bit line is not affected by the ferroelectric memory cell to which it is connected.
  • bit line BL and the complementary bit line /BL can be two bit lines in the same memory array in the memory, or they can be different memory arrays in the memory. Two bit lines in the array.
  • the transistor mentioned in the above embodiments of the present application may be a thin film transistor (Thin Film Transistor, TFT) or a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET).
  • TFT Thi Film Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • one of the first electrode and the second electrode of the transistor is the source electrode, and the other is the drain electrode.
  • the source electrode and the drain electrode of the transistor can be interchanged, and no specific distinction is made.
  • the bit line reading circuit may also include a controller; the controller is used to make the first switch and the second switch switch when the sensitive amplifier differentially amplifies the voltage on the bit line and the reference line and then outputs the voltage. Turn off, and turn off the first switch and the second switch when writing data to the bit line and the reference line.
  • the controller is also used to control the sense amplifier and the precharge circuit, so that the sense amplifier differentially amplifies the voltage on the bit line and the reference line and outputs it, and the precharge circuit precharges the bit line and the reference line.
  • the controller can also control the selection circuit to read data on the bit line and the reference line, or control the selection circuit to write data to the bit line and the reference line.
  • the controller can be implemented by a logic circuit. Those skilled in the art can obtain the specific circuit structure according to the function, which is not limited here.
  • controller can control the working timing of the first switch, the second switch, the precharge circuit, the sense amplifier and the bit line reading circuit under the control of the timing controller.
  • embodiments of the present application also provide a reading method applied to the bit line reading circuit as described in the first aspect or various implementations of the first aspect.
  • the reading method may include the following steps:
  • the first stage the first switch and the second switch are turned on, and the precharge circuit precharges the bit line and reference line;
  • the second stage the first switch and the second switch are turned on, and the precharge circuit is turned off;
  • the third stage the first switch and the second switch are turned on, and the sense amplifier differentially amplifies the voltage on the bit line and the reference line;
  • the fourth stage the first switch and the second switch are turned off, and the precharge circuit precharges the bit line and reference line; the sense amplifier outputs the voltage on the bit line and reference line, or writes data to the bit line and reference line;
  • the fifth stage the first switch and the second switch are turned on, and the precharge circuit is turned off after a preset time.
  • bit line reading circuit provided by the embodiment of the present application is described below in conjunction with the timing sequence.
  • the word line connected to the selected ferroelectric memory cell is turned on for a period of time and then turned off.
  • the node, bit line and The reference line is precharged to 0V by the precharge circuit.
  • the bit line and reference line are precharged to the reference voltage by the precharge circuit.
  • the voltage on the board line connected to the selected ferroelectric capacitor is pulled up from V w /2 to V w , and the selected ferroelectric capacitor is selected.
  • the ferroelectric capacitor is subject to the voltage difference of V w .
  • the polarization direction of the ferroelectric capacitor will flip and release the polarization charge, causing the node's The potential rises obviously; if the data stored in the ferroelectric capacitor itself is in the same direction as the external electric field (data "0"), the polarization direction of the ferroelectric capacitor does not change, and the node potential rises not significantly.
  • the precharge circuit is turned off, the word line connected to the selected ferroelectric memory cell is turned on again, the charges on the node and the bit line are shared, the potential on the bit line depends on the potential of the node, and the bit line The potential will rise (data “1") or drop (data "0") by a certain amplitude, and the reference line will remain at the reference voltage, and the two will eventually form a stable voltage difference.
  • the first reference voltage source is pulled down to 0, and the second reference voltage source SAP is pulled up to V w .
  • the sensitive amplification circuit starts to work. If the ferroelectric capacitor selected in the ferroelectric storage unit stores The data is "1”, the sense amplifier pulls the bit line high to V w and the reference line low to 0. If the data stored in the selected ferroelectric capacitor in the ferroelectric memory cell is "0", the sense amplifier pulls the reference line high to V w and the bit line low to 0. As a result, the sensitive amplifier differentially amplifies the voltages on the bit line and the reference line, and then reads out the information stored in the selected ferroelectric capacitor.
  • the first switch and the second switch are turned off, the precharge circuit is turned on, and the node, the bit line on the right side of the first switch, and the reference line on the right side of the second switch are precharged to V by the precharge circuit.
  • w /2 if it is a read operation, the bit line on the left side of the first switch and the reference line on the left side of the second switch maintain the voltage in stage 4. If it is a write operation, the bit line on the left side of the first switch and the reference line on the left side of the second switch maintain the voltage in stage 4. The reference line on the left side of the second switch is rewritten to the new voltage.
  • the first switch and the second switch are turned on, and the precharge circuit is turned off after a preset time.
  • the board line is pulled down to 0 and then returned to V w /2, node, the first switch
  • the bit line on the right side and the reference line on the right side of the second switch are driven to corresponding potentials by the bit line on the left side of the first switch and the complementary bit on the left side of the second switch. If the node voltage is V w , the ferroelectric capacitor will be written back as data "1"; if the node voltage is 0, the ferroelectric capacitor will remain at data "0". Then the word line WL is turned off and all operations in the write-back phase are completed.
  • embodiments of the present application also provide a memory, including a ferroelectric memory unit and a bit line reading circuit as described in the first aspect or various implementations of the first aspect.
  • the ferroelectric memory unit includes a parallel A plurality of ferroelectric capacitors and a transistor connected to the plurality of ferroelectric capacitors, a gate electrode of the transistor is connected to a word line, a first electrode of the transistor is connected to a bit line, and a second electrode of the transistor is connected to a plurality of ferroelectric capacitors connected in parallel. Since the problem-solving principle of this memory is similar to that of the aforementioned bit line reading circuit, the implementation of this memory can be referred to the implementation of the aforementioned bit line reading circuit, and repeated details will not be repeated. Since the bit line reading circuit proposed in this application can reduce the time that the ferroelectric capacitor is in the "half-selected" state, a memory including the bit line reading circuit can also reduce the time that the ferroelectric capacitor is in the "half-selected” state.
  • the memory may also include control logic, and the control logic is used to: turn on the ferroelectric memory cell; and read the level on the bit line.
  • the control logic may be a controller in a memory, which is not limited here.
  • embodiments of the present application further provide an electronic device, including a processor and a memory coupled to the processor as described in the third aspect.
  • the processor can call the software program stored in the memory to execute the corresponding method and realize the corresponding function of the electronic device.
  • Figure 1 is a schematic structural diagram of a ferroelectric memory unit in the ferroelectric memory provided by the embodiment of the present application;
  • Figure 2 is a schematic structural diagram of a memory in an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of a commonly used bit line reading circuit
  • Figure 4 is a schematic structural diagram of a bit line reading circuit in an embodiment of the present application.
  • Figure 5 is a specific structural schematic diagram of the bit line reading circuit in the embodiment of the present application.
  • Figure 6 is another specific structural schematic diagram of the bit line reading circuit in the embodiment of the present application.
  • Figure 7 is a circuit timing diagram corresponding to the bit line reading circuit shown in Figure 6;
  • FIG. 8 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • T1 1st transistor; T2 second transistor;
  • T7 The seventh transistor; T8 The eighth transistor;
  • T9 The ninth transistor; T10 The tenth transistor;
  • the bit line reading circuit proposed in the embodiment of the present application can be applied in the memory of electronic equipment (such as internal memory and external buffer).
  • the electronic device can be a computer system, such as a server, a desktop computer, and a notebook computer.
  • the memory in the embodiment of the present application can be specifically applied to the last cache of the above-mentioned computer system close to the central processing unit (Central Processing Unit, CPU).
  • CPU Central Processing Unit
  • the above-mentioned electronic devices can also be mobile terminal products such as mobile phones.
  • the memory may specifically be dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the memory in this application can be specifically used to store data, and can write and read data.
  • the memory may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • FIG. 2 exemplarily shows a schematic structural diagram of a memory in an embodiment of the present application.
  • the memory 1 may include a memory cell array 10 and a differential amplifier 20 .
  • the memory cell array 10 may include a plurality of ferroelectric memory cells 101 arranged in an array, and a word line WL and a bit line BL connected to each ferroelectric memory cell 101; each ferroelectric memory cell 101 includes a transistor T0 and a plurality of ferroelectric memory cells 101. Capacitance C1 ⁇ Cn.
  • the transistor T0 in each row is connected to the same word line WL, and the transistor T0 in each column is connected to the same bit line BL.
  • the source or drain of the transistor T0 is connected to its corresponding bit line BL, and the gate of the transistor T0 is connected to its corresponding word line WL.
  • the differential amplifier 20 may include a plurality of bit line read circuits (not shown in FIG. 1 ), each bit line read circuit is respectively connected to a reference line and a bit line BL, and the bit line read circuit may convert the bit lines connected thereto.
  • the voltages of the line BL and the reference line are differentially amplified, and the level of the bit line is output.
  • the memory 1 may also include a column decoder 30, a row decoder 40 and a data buffer 50.
  • the column decoder 30 is used to decode the bit line BL address information and determine the bit line BL address to be read and written;
  • the row decoder 40 is used to decode the plate line PLi (i is any number from 1 to n) and the word line WL
  • the address information is decoded to determine the address of the word line WL to be read and written and the address of the ferroelectric capacitor Ci to be written;
  • the data buffer 50 is used to transmit the bit line level output from the bit line reading circuit to the external circuit.
  • Figure 3 is a schematic structural diagram of a commonly used bit line reading circuit 201'.
  • the bit line read circuit 201' includes a precharge circuit 001' and a sense amplifier (Sense amplifier, SA) 002'; when the bit line read circuit 201' works, it needs to be powered by the sense amplifier 002' after the precharge circuit 001' completes precharging. Perform voltage differential amplification and read it out after the sensitive amplifier 002' completes the voltage differential amplification.
  • SA sense amplifier
  • one end of n ferroelectric capacitors C1 ⁇ Cn is controlled by n plate lines PL1 ⁇ PLn respectively, and the other end of these n ferroelectric capacitors C1 ⁇ Cn is is connected to the common node FN in the ferroelectric memory cell 101, the node FN is connected to the source end of the field effect transistor T0, the drain end of the field effect transistor T0 is connected to the common bit line BL, and the gate of the field effect transistor T0 is connected to to word line WL.
  • the unselected ferroelectric capacitor will bear the "half-selected" applied voltage V w /2 during the reading and writing process, that is, half of the voltage V w that the selected ferroelectric capacitor bears.
  • V w /2 is less than the coercive field voltage V c , so the unselected ferroelectric capacitor does not release significant polarization charge.
  • the node FN in the selected ferroelectric memory cell 101 will be at 0 or 0 for a long time because it is connected to the sense amplifier 002'.
  • the voltage state of V w while the unselected plate line PL is at V w /2, so the unselected ferroelectric capacitors in the ferroelectric memory unit 101 (such as C2 ⁇ Cn in Figure 3 ) will be in the "half-selected" voltage state.
  • ferroelectric capacitor is at the "half-selected" voltage for a long time, the inherent spontaneous polarization intensity of the ferroelectric capacitor will also be significantly changed, which will affect the window size of the information reading.
  • it is usually necessary to perform a periodic refresh operation on ferroelectric capacitors. Therefore, preventing the ferroelectric capacitor from being in the "half-selected" state for a long time is an inevitable requirement to ensure the normal operation of the ferroelectric memory, and will also reduce the frequency of ferroelectric capacitor refresh.
  • embodiments of the present application provide a bit line reading circuit for reducing the time that the ferroelectric capacitor is in the "half-selected" state during the reading and writing process of the 1TnC ferroelectric memory cell.
  • FIG. 4 exemplarily shows a schematic structural diagram of a bit line reading circuit in an embodiment of the present application.
  • the bit line reading circuit 201 is used to read the level from the ferroelectric memory cell 101.
  • the bit line reading circuit 201 may include a bit line BL, a reference line REF, a precharge circuit 001, a sense amplifier 002, and a first switch. 0031 and the second switch 0032.
  • the bit line BL is connected to the ferroelectric memory unit 101.
  • the ferroelectric memory unit 101 generally includes n ferroelectric capacitors C1 ⁇ Cn and a transistor T0, where n is an integer greater than or equal to 2.
  • the gate of the transistor T0 is connected to the word line WL.
  • the first pole of the transistor T0 is connected to the bit line BL
  • the second pole of the transistor T0 is connected to the node FN
  • the node FN is connected to each ferroelectric capacitor Ci (i is 1 to N) among the n ferroelectric capacitors C1 to Cn One end of any number in ) is connected
  • the other end of each ferroelectric capacitor Ci is connected to a corresponding plate line PLi.
  • the sense amplifier 002 is connected to the bit line BL and the reference line REF respectively, and is used to differentially amplify the voltage on the bit line BL and the reference line REF;
  • the precharge circuit 001 is connected to the bit line BL and the reference line REF respectively, and is used for bit alignment.
  • the line BL and the reference line REF are precharged;
  • the first switch 0031 is connected to the bit line BL between the sense amplifier 002 and the precharge circuit, and is used to turn on or off the bit line between the sense amplifier 002 and the precharge circuit 001 BL;
  • the second switch 0032 is connected to the reference line REF between the sense amplifier 002 and the precharge circuit 001, and is used to turn on or off the reference line REF between the sense amplifier 002 and the precharge circuit 001. In this way, when the bit line read circuit 201 is in the read and write stage, the sense amplifier 002 operates normally.
  • the first switch 0031 disconnects the bit line BL between the sense amplifier 002 and the precharge circuit 001, and the second switch 0032 causes the sense amplifier to disconnect.
  • the reference line REF between 002 and the precharge circuit 001 is disconnected, so that the bit line BL can be pulled by the precharge circuit 001 to the same voltage as the plate line PLi to which the unselected ferroelectric capacitor Ci in the ferroelectric memory cell 101 is connected.
  • the voltage on the plate line PLi connected to the unselected ferroelectric capacitor Ci is V w /2, then the bit line BL is pulled to V w /2 by the precharge circuit 001, so that the voltage of the unselected ferroelectric capacitor Ci
  • the voltage at both ends is the same, so that the ferroelectric capacitor will not be in the "half-selected” state during the reading and writing stages, thereby reducing the time the ferroelectric capacitor is in the "half-selected” state.
  • connection position of the precharge circuit 001 on the bit line BL is closer to the ferroelectric memory unit 101, see Figure 4, that is, the ferroelectric memory unit
  • the information of unit 101 is first transmitted to the precharge circuit 001 through the bit line BL, and then transmitted to the sense amplifier 002 through the first switch 0031; correspondingly, the signal charged by the precharge circuit 001 to the reference line REF needs to pass through the second switch 0032. Transmitted to sense amplifier 002.
  • FIG. 5 exemplarily shows a specific structural schematic diagram of the bit line reading circuit in the embodiment of the present application.
  • the first switch 0031 may include a first transistor T1, the gate of the first transistor T1 is connected to the first isolation control line ISO1, and the first pole and the second pole of the first transistor T1 are connected.
  • the first electrode of the first transistor T1 is connected to an end BL_a of the bit line BL close to the precharge circuit 001, and the second electrode of the first transistor T1 is connected to the bit line BL_a.
  • the line BL is close to one end BL_b of the sense amplifier 002.
  • the first isolation control line ISO1 controls the first switch 0031 to be turned on, the end BL_a of the bit line BL close to the precharge circuit 001 and the end BL_b of the bit line BL close to the sense amplifier 002 are turned on. , signal transmission can be realized at both ends.
  • the first isolation control line ISO1 controls the first switch 0031 to turn off, the end BL_a of the bit line BL close to the precharge circuit 001 and the end BL_b of the bit line BL close to the sensitive amplifier 002 are disconnected, and both ends Signal transmission cannot be achieved between them, thereby isolating the precharge circuit 001 from the sense amplifier 002 .
  • the first transistor T1 may be a P-type transistor or an N-type transistor, which is not limited here.
  • the first transistor T1 is a P-type transistor, the first transistor T1 is turned on when the first isolation control line ISO1 is at a low level, and is turned off when the first isolation control line ISO1 is at a high level;
  • the first transistor T1 is As an N-type transistor, when the first isolation control line ISO1 is at a high level, the first transistor T1 is turned on, and when the first isolation control line ISO1 is at a low level, the first transistor T1 is turned off.
  • the above is only an example to illustrate the specific structure of the first switch.
  • the specific structure of the first switch is not limited to the above-mentioned structure provided in the embodiment of the present application, and can also be other structures known to those skilled in the art, which are not limited here. .
  • the second switch 0032 may include a second transistor T2 , the gate of the second transistor T2 is connected to the second isolation control line ISO2 , and the first electrode of the second transistor T2 and the second electrode is connected to the reference line REF between the sense amplifier 002 and the precharge circuit 001.
  • the first electrode of the second transistor T2 is connected to one end REF_a of the reference line REF close to the precharge circuit 001.
  • the first electrode of the second transistor T2 The two poles are connected to one end REF_b of the reference line REF close to the sense amplifier 002.
  • the reference line REF is close to one end REF_a of the precharge circuit 001 and the reference line REF is close to the sense amplifier 002.
  • One end REF_b is turned on, and signal transmission can be achieved at both ends.
  • the second isolation control line ISO2 controls the second switch 0032 to be turned off, the reference line REF is close to the end REF_a of the precharge circuit 001 and the reference line REF is close to the end REF_b of the sensitive amplifier 002 When disconnected, signal transmission cannot be realized between the two ends, thereby isolating the precharge circuit 001 from the sense amplifier 002.
  • the second transistor T2 may be a P-type transistor or an N-type transistor, which is not limited here.
  • the second transistor T2 is a P-type transistor
  • the second transistor T2 is turned on when the second isolation control line ISO2 is at a low level, and the second transistor T2 is turned off when the second isolation control line ISO2 is at a high level;
  • the second transistor T2 is As an N-type transistor, when the second isolation control line ISO2 is at a high level, the second transistor T2 is turned on, and when the second isolation control line ISO2 is at a low level, the second transistor T2 is turned off.
  • the above is only an example to illustrate the specific structure of the second switch.
  • the specific structure of the second switch is not limited to the above-mentioned structure provided in the embodiment of the present application, and can also be other structures known to those skilled in the art, which are not limited here. .
  • the first transistor T1 and the second transistor T2 may both be N-type transistors as shown in FIG. 6 .
  • the first transistor T1 and the second transistor T2 may both be P-type transistors.
  • the first isolation control line ISO1 and the second isolation control line ISO2 may be the same control line, That is, the first transistor T1 and the second transistor T2 are controlled by the same isolated control line at the same time, thereby reducing the number of control lines, and the first transistor T1 and the second transistor T2 can be controlled synchronously without the need for additional synchronous control circuits.
  • the circuit structure can be simplified.
  • the differential inputs of the sense amplifier 002 are respectively connected to the bit line BL and the reference line REF, and the differential outputs of the sense amplifier 002 are respectively connected to the bit line BL and the reference line REF to align the bit line BL and the reference line REF.
  • the voltage on line REF is differentially amplified.
  • the sense amplifier 002 may include: an N-type third transistor T3 , an N-type fourth transistor T4 , a P-type fifth transistor T5 , and a P-type sixth transistor T6 ;
  • the first electrode of the third transistor T3 is connected to the bit line BL
  • the second electrode of the third transistor T3 is connected to the first reference voltage source SAN
  • the gate electrode of the third transistor T3 is connected to the reference line REF
  • the fourth transistor The first electrode of T4 is connected to the reference line REF
  • the second electrode of the fourth transistor T4 is connected to the first reference voltage source SAN
  • the gate electrode of the fourth transistor T4 is connected to the bit line BL
  • the first electrode of the fifth transistor T5 is connected to The bit line BL is connected
  • the second electrode of the fifth transistor T5 is connected to the second reference voltage source SAP
  • the gate electrode of the fifth transistor T5 is connected to the reference line REF
  • the first electrode of the sixth transistor T6 is connected to the reference line
  • the precharge circuit 001 may include: a seventh transistor T7 and an eighth transistor T8.
  • the first electrode of the seventh transistor T7 is connected to the bit line BL
  • the second electrode of the seventh transistor T7 is connected to the precharge voltage source VBLP
  • the gate electrode of the seventh transistor T7 is connected to the precharge control line PCH
  • the eighth transistor The first electrode of T8 is connected to the precharge voltage source VBLP
  • the second electrode of the eighth transistor T8 is connected to the reference line REF
  • the gate electrode of the eighth transistor T8 is connected to the precharge control line PCH.
  • the precharge control line PCH controls both the seventh transistor T7 and the eighth transistor T8 to be turned on, and the voltage of the precharge voltage source VBLP is transmitted to the bit line BL through the seventh transistor T7 and the eighth transistor T8 respectively. and the reference line REF, thereby making the voltages of the bit line BL and the reference line REF equal.
  • the precharge circuit 001 may also include a ninth transistor T9.
  • the first electrode of the ninth transistor T9 is connected to the bit line BL.
  • the second electrode of the ninth transistor T9 is connected to the reference line REF.
  • the gate of the nine-transistor T9 is connected to the precharge control line PCH.
  • the precharge control line PCH controls the ninth transistor T9 to turn on.
  • the turned on ninth transistor T9 can further ensure that the voltages on the bit line BL and the reference line REF are equal.
  • the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 in the precharge circuit 001 are all N-channel transistors or are all P-channel transistors, which are not limited here.
  • the bit line reading circuit provided by the embodiment of the present application may also include a selection circuit 004; the selection circuit 004 is connected to the bit line BL and the reference line REF for reading the bit line. data on BL and reference line REF, or write data to bit line BL and reference line REF.
  • the bit line reading circuit 201 of the present application can not only output data, but also write data.
  • the selection circuit 004 may include a tenth transistor T10 and an eleventh transistor T11.
  • the first electrode of the tenth transistor T10 is used to write data or read data.
  • the second electrode of the tenth transistor T10 is connected to the bit line BL.
  • the gate electrode of the tenth transistor T10 is connected to the first selection control line YS1.
  • the first electrode of a transistor T11 is used to write data or read data
  • the second electrode of the eleventh transistor T11 is connected to the reference line REF
  • the gate electrode of the eleventh transistor REF is connected to the second selection control line YS2.
  • the first selection control line YS1 controls the tenth transistor T10 to be turned on, so that data is written to the bit line BL or data on the bit line BL is read through the turned on tenth transistor T10.
  • the second selection control line YS2 controls the eleventh transistor T11 to be turned on, so that data is written to the reference line REF or data on the reference line REF is read through the turned-on eleventh transistor T11.
  • the reference line REF connected to the bit line reading circuit 201 can be the complementary bit line /BL.
  • the selected bit line BL is connected to the complementary bit line /BL.
  • the ferroelectric memory cells 101 are not connected to the same word line.
  • the ferroelectric memory cell 101 connected to the selected bit line BL is connected to the word line WL and the unselected bit line /BL is connected to the ferroelectric storage
  • the word line /WL connected to the cell 101 is a different word line, so when the bit line reading circuit reads the selected bit line BL, the voltage of the complementary bit line /BL is not affected by the ferroelectric memory cell 101 to which it is connected. .
  • bit line BL and the complementary bit line /BL can be two bit lines in the same memory array in the memory, or they can be a memory Two bit lines in different memory arrays.
  • the transistors mentioned in the above embodiments of the present application may be thin film transistors or metal oxide semiconductor field effect transistors, which are not limited here.
  • one of the first electrode and the second electrode of the transistor is the source electrode, and the other is the drain electrode.
  • the source electrode and the drain electrode of the transistor can be interchanged, and no specific distinction is made.
  • the bit line reading circuit 201 may also include a controller 005; the controller 005 is used to perform differential voltage on the bit line BL and the reference line REF in the sense amplifier 002.
  • the first switch 0031 and the second switch 0032 are turned off, and when writing data to the bit line BL and the reference line REF, the first switch 0031 and the second switch 0032 are turned off.
  • the controller 005 is also used to control the sense amplifier 002 and the precharge circuit 001, so that the sense amplifier 002 differentially amplifies the voltage on the bit line BL and the reference line REF and outputs it, so that The precharge circuit 001 precharges the bit line BL and the reference line REF.
  • the controller 005 can also control the selection circuit 004 to read data on the bit line BL and the reference line REF, or control the selection circuit 004 to write data to the bit line BL and the reference line REF.
  • the controller can be implemented by a logic circuit. Those skilled in the art can obtain the specific circuit structure according to the function, which is not limited here.
  • controller can control the working timing of the first switch, the second switch, the precharge circuit, the sense amplifier and the bit line reading circuit under the control of the timing controller.
  • inventions of the present application also provide a reading method applied to any of the above bit line reading circuits.
  • the reading method may include the following steps:
  • the first stage the first switch and the second switch are turned on, and the precharge circuit precharges the bit line and the reference line;
  • the second stage the first switch and the second switch are turned on, and the precharge circuit is turned off;
  • the third stage the first switch and the second switch are turned on, and the sensitive amplifier performs differential amplification on the voltage on the bit line and the reference line;
  • the fourth stage the first switch and the second switch are turned off, the precharge circuit precharges the bit line and the reference line; the sense amplifier voltage output, or write data to the bit line and the reference line;
  • the fifth stage the first switch and the second switch are turned on, and the precharge circuit is turned off after a preset time and then turned on.
  • bit line reading circuit provided by the embodiment of the present application is described below in conjunction with the timing sequence. Specifically, taking the bit line reading circuit shown in FIG. 6 as an example, its corresponding input timing diagram is shown in FIG. 7 .
  • the word line WL connected to the selected ferroelectric memory cell 101 is turned on for a period of time and then turned off. During the turn on of the word line WL, the node FN, the bit line BL and the complementary bit line /BL are precharged. Charging circuit 001 precharges to 0V.
  • the bit line BL and the complementary bit line /BL are precharged to the reference voltage V ref by the precharge circuit 001.
  • the voltage on the plate line PL1 connected to the selected ferroelectric capacitor such as C1 changes from V w /2 is pulled up to V w , and the selected ferroelectric capacitor C1 is subject to the voltage difference of V w .
  • the precharge circuit 001 is turned off, the word line WL connected to the selected ferroelectric memory cell 101 is turned on again, the charges of the node FN and the bit line BL are shared, and the potential on the bit line BL depends on the node
  • the potential of FN and the potential of bit line BL will rise (data "1") or fall (data "0") by a certain amplitude, and the complementary bit line /BL will be maintained at the reference voltage V ref , and the two will eventually form a stable voltage. Difference.
  • the first reference voltage source SAN is pulled down to 0, the second reference voltage source SAP is pulled up to V w , and the sense amplifier 002 starts to work. If the ferroelectric capacitor selected in the ferroelectric memory unit 101 The data stored in C1 is "1", which causes the voltage of the bit line BL to rise, causing the fourth transistor T4 to turn on first.
  • the voltage of the first reference voltage source SAN is transmitted to the complementary bit line /BL through the fourth transistor T4.
  • the complementary bit line /BL The voltage is pulled low, and the complementary bit line /BL controls the fifth transistor T5 to turn on.
  • the voltage of the second reference voltage source SAP is transmitted to the bit line BL through the fifth transistor T5.
  • the voltage of the bit line BL is pulled high.
  • the bit line BL is pulled high to Vw , and the complementary bit line /BL is pulled low to 0. If the data stored in the selected ferroelectric capacitor C1 in the ferroelectric memory unit 101 is "0", causing the voltage of the bit line BL to drop, the sixth transistor T6 is turned on first, and the voltage of the second reference voltage source SAP is transmitted to The complementary bit line /BL, the voltage of the complementary bit line /BL is pulled up, the complementary bit line /BL controls the third transistor T3 to turn on, and the voltage of the first reference voltage source SAN is transmitted to the bit line BL through the third transistor T3.
  • the bit line The voltage of BL is pulled low, and through continuous positive feedback, the complementary bit line /BL is pulled high to V w and the bit line BL is pulled low to 0.
  • the sense amplifier 002 implements differential amplification of the voltages on the bit line BL and the complementary bit line /BL, and then reads out the information stored in the selected ferroelectric capacitor C1.
  • the first transistor T1 and the second transistor T2 are turned off, the precharge circuit 001 is turned on, the node FN, the bit line BL_a on the right side of the first transistor T1 and the complementary bit line on the right side of the second transistor T2 /BL_a is precharged to V w /2 by the precharge circuit.
  • bit line BL_b on the left of the first transistor T1 and the complementary bit line /BL_b on the left of the second transistor T2 maintain the voltage in the 4 stage
  • bit line BL_b on the left side of the first transistor T1 and the complementary bit line /BL_b on the left side of the second transistor T2 are rewritten to the new voltage.
  • the first transistor T1 and the second transistor T2 are turned on, the precharge circuit 001 is first closed and then opened.
  • the board line PL1 is pulled down to 0 and then returned to V w /2, node FN,
  • the bit line BL_a on the right side of the first transistor T1 and the complementary bit line /BL_a on the right side of the second transistor T2 are driven by the bit line BL_b on the left side of the first transistor T1 and the complementary bit line /BL_b on the left side of the second transistor T2. corresponding potential.
  • the ferroelectric capacitor C1 will be written back as data "1"; if the voltage of the node FN is 0, the ferroelectric capacitor C1 will remain at the data "0". Then the word line WL is turned off and all operations in the write-back phase are completed.
  • the node FN, the bit line BL_a on the right side of the first transistor T1 and the complementary bit line /BL_a on the right side of the second transistor T2 are Maintained at V w /2, the voltage difference across the unselected ferroelectric capacitors C2 ⁇ Cn is 0, thereby avoiding the "half-selected" voltage interference of the unselected ferroelectric capacitors C2 ⁇ Cn at this stage.
  • the bit line reading circuit proposed in the embodiment of this application can be applied in a memory.
  • the memory provided by this application includes: a bit line reading circuit and a ferroelectric storage unit in any of the above technical solutions of this application.
  • the ferroelectric storage unit includes multiple ferroelectric capacitors connected in parallel and transistors connected to the multiple ferroelectric capacitors.
  • the gate electrode of the transistor is connected to the word line, the first electrode of the transistor is connected to the bit line, and the second electrode of the transistor is connected to a plurality of ferroelectric capacitors connected in parallel.
  • the structure of the memory can be seen as shown in Figure 2 above.
  • bit line reading circuit proposed in this application can reduce the time that the ferroelectric capacitor is in the "half-selected" state, a memory including the bit line reading circuit can also reduce the time that the ferroelectric capacitor is in the "half-selected" state.
  • the memory may also include control logic, and the control logic is used to: turn on the ferroelectric memory cell; and read the level on the bit line.
  • the control logic may be a controller in a memory, which is not limited here.
  • the electronic device includes a processor 2 and a memory 1 coupled to the processor.
  • the memory 1 may be the memory shown in FIG. 2 .
  • the processor 2 can call the software program stored in the memory 1 to execute the corresponding method and realize the corresponding function of the electronic device.

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Abstract

一种位线读取电路（201）、存储器（1）及电子设备。其中，该位线读取电路中（201），位线（BL）与铁电存储单元（101）相连，铁电存储单元（101）包括n个铁电电容（Ci）和晶体管（T2, T4, T6, T8, T10）；灵敏放大器（002）和预充电电路（001）均分别与位线（BL）和参考线（REF）连接，第一开关（0031）连接于灵敏放大器（002）与预充电电路（001）之间的位线（BL）上，第二开关（0032）连接于灵敏放大器（002）与预充电电路（001）之间的参考线（REF）上。在读写阶段时，灵敏放大器（002）正常工作，第一开关（0031）使灵敏放大器（002）与预充电电路（001）之间的位线（BL）断开，第二开关（0032）使灵敏放大器（002）与预充电电路（001）之间的参考线（REF）断开，从而位线（BL）可以被预充电电路（001）拉到与铁电存储单元（101）中未选中的铁电电容（Ci）相同的电压，这样未选中的铁电电容（Ci）的两端的电压就相同，从而可以降低铁电电容（Ci）处于"半选"状态的时间。

Description

一种位线读取电路、存储器及电子设备
相关申请的交叉引用
本申请要求在2022年04月20日提交中国专利局、申请号为202210417231.7、申请名称为“一种位线读取电路、存储器及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路技术领域，尤其涉及一种位线读取电路、存储器及电子设备。
背景技术
现有的计算系统中，动态随机存取存储器(Dynamic Random Access Memory，DRAM)作为内存，可以用于暂存中央处理器(Central Processing Unit，CPU)的运算数据，以及与硬盘等外部存储器交换的数据。
随着基于1T1C的DRAM的尺寸微缩逐渐碰到瓶颈，基于1TnC的铁电存储器(Ferroelectric Random Access Memory，FeRAM)成为进一步提高DRAM集成密度的重要选项。如图1所示，在一个1TnC的储存单元中，n个铁电电容C1～Cn的一端分别由n个板线(plate line)PL1～PLn控制，这n个铁电电容C1～Cn的另一端则连接到铁电存储单元内公共的节点FN，节点FN连到场效应晶体管(Field Effect Transistor，FET)T0的源极一端，场效应晶体管T0的漏极一端连接到公共的位线(Bit line，BL)，场效应晶体管T0的栅极则连到字线(Word line，WL)。铁电电容的信息可以通过位线BL上由于电荷变化而导致的电压变化并通过灵敏放大器(Sense amplifier，SA)放大并读出。位线BL上电荷的变化主要来自非易失性的铁电电容受到超过矫顽场强度的电压时释放出来的极化电荷。
由于n个铁电电容C1～Cn有一端连在了公共的节点FN上，为了区分这n个铁电电容C1～Cn中的选中的铁电电容和未选中的n-1个铁电电容，未选中的铁电电容在读写过程中将承受“半选(half-select)”的外加电压V w/2，亦即选中铁电电容承受的电压V w的一半。通常“半选”电压V w/2小于矫顽场电压V c，所以未选中的铁电电容不会释放出显著的极化电荷。为了和传统双倍速率(Double Data Rate，DDR)DRAM协议兼容，在一行铁电存储单元激活(Activate)之后直至下一个预充电(Precharge)命令之前，选中的铁电存储单元中的节点FN因为与灵敏放大器相连，将长时间处于0或者V w的电压状态，而未选中的板线PL处于V w/2，因此铁电存储单元中未选中的铁电电容(例如图1中C2～Cn)将处于“半选”电压状态。但是如果铁电电容长时间处于“半选”电压下，铁电电容内在的自发极化强度也会受到明显的改变，进而影响到信息读取的窗口大小。为了改善铁电电容因长时间受到“半选”电压干扰而发生极化状态的改变，通常需要对铁电电容进行周期性的刷新操作。因此，如何减小铁电电容处于“半选”电压状态是本领域技术人员亟需解决的技术问题。
发明内容
本申请提供了一种位线读取电路、存储器及电子设备，用于改善1TnC铁电存储器在 读写过程中铁电电容长时间处在“半选”状态。
第一方面，本申请实施例提供了一种位线读取电路，该位线读取电路用于从铁电存储单元中读取电平，该位线读取电路可以包括位线、参考线、预充电电、灵敏放大器、第一开关和第二开关。位线与铁电存储单元相连，铁电存储单元一般包括n个铁电电容和一个晶体管，其中n为大于或等于2的整数，晶体管的栅极与字线连接，晶体管的第一极与位线连接，晶体管的第二极与该n个铁电电容中每一铁电电容的一端连接，而每一铁电电容的另一端分别对应连接有一条板线。灵敏放大器分别与位线和参考线连接，用于对位线和参考线上的电压进行差分放大；预充电电路分别与位线和参考线连接，用于对位线和参考线预充电；第一开关连接于灵敏放大器与预充电电路之间的位线上，用于导通或者断开灵敏放大器与预充电电路间的位线；第二开关连接于灵敏放大器与预充电电路之间的参考线上，用于导通或者断开灵敏放大器与预充电电路之间的参考线。这样，该位线读取电路在读写阶段时，灵敏放大器正常工作，第一开关使灵敏放大器与预充电电路之间的位线断开，第二开关使灵敏放大器与预充电电路之间的参考线断开，从而位线可以被预充电电路拉到与铁电存储单元中未选中的铁电电容所连接的板线相同的电压，例如未选中的铁电电容所连接的板线上的电压为V w/2，那么位线就被预充电电路拉到V w/2，这样未选中的铁电电容的两端的电压就相同，从而在读写阶段不会处于“半选”状态，进而可以降低铁电电容处于“半选”状态的时间。
需要说明的是，在本申请中，预充电电路与灵敏放大器相比，预充电电路在位线上的连接位置更为靠近铁电存储单元，即铁电存储单元的信息通过位线先传输至预充电电路，然后通过第一开关传输至灵敏放大器；对应的，预充电电路充至参考线上的信号需要通过第二开关才能传输至灵敏放大器。
下面结合具体实施例，对本申请进行详细说明。需要说明的是，本实施例中是为了更好的解释本申请，但不限制本申请。
示例性的，在该位线读取电路中，第一开关可以包括第一晶体管，第一晶体管的栅极与第一隔离控制线连接，第一晶体管的第一极和第二极连接于灵敏放大器与预充电电路之间的位线上，当第一隔离控制线控制第一开关导通时，位线靠近预充电电路的一端与位线靠近灵敏放大器的一端导通，两端可以实现信号传输，当第一隔离控制线控制第一开关截止时，位线靠近预充电电路的一端与位线靠近灵敏放大器的一端断开，两端之间不能实现信号的传输，从而将预充电电路与灵敏放大器隔离开。
在具体实施时，第一晶体管可以是P型晶体管，也可以是N型晶体管，在此不作限定。当第一晶体管为P型晶体管时，第一隔离控制线为低电平时第一晶体管导通，第一隔离控制线为高电平时第一晶体管截止；当第一晶体管为N型晶体管时，第一隔离控制线为高电平时第一晶体管导通，第一隔离控制线为低电平时第一晶体管截止。
以上仅是举例说明第一开关的具体结构，在具体实施时，第一开关的具体结构不限于本申请实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
示例性的，第二开关可以包括第二晶体管，第二晶体管的栅极与第二隔离控制线连接，第二晶体管的第一极和第二极连接于灵敏放大器与预充电电路之间的参考线上，当第二隔离控制线控制第二开关导通时，参考线靠近预充电电路的一端与参考线靠近灵敏放大器的一端导通，两端可以实现信号传输，当第二隔离控制线控制第二开关截止时，参考线靠近预充电电路的一端与参考线靠近灵敏放大器的一端断开，两端之间不能实现信号的传输， 从而将预充电电路与灵敏放大器隔离开。
在具体实施时，第二晶体管可以是P型晶体管，也可以是N型晶体管，在此不作限定。当第二晶体管为P型晶体管时，第二隔离控制线为低电平时第二晶体管导通，第二隔离控制线为高电平时第二晶体管截止；当第二晶体管为N型晶体管时，第二隔离控制线为高电平时第二晶体管导通，第二隔离控制线为低电平时第二晶体管截止。
以上仅是举例说明第二开关的具体结构，在具体实施时，第二开关的具体结构不限于本申请实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
可选的，第一晶体管和第二晶体管均为N型晶体管，当然，第一晶体管和第二晶体管也可以均为P型晶体管。
示例性的，当第一晶体管和第二晶体管均为N型晶体管或者均为P型晶体管时，第一隔离控制线与第二隔离控制线可以为同一控制线，即第一晶体管和第二晶体管同时被同一隔离控制线控制，从而可以减少控制线的数量，并且，第一晶体管和第二晶体管可以同步被控制，不需要额外设置同步控制电路，从而可以简化电路结构。
示例性的，灵敏放大器的差分输入分别接位线和参考线，灵敏放大器的差分输出分别接位线和参考线，以对位线和参考线上的电压进行差分放大。
示例性的，灵敏放大器可以包括：N型的第三晶体管、N型的第四晶体管、P型的第五晶体管和P型的第六晶体管；其中：第三晶体管的第一极与位线连接，第三晶体管的第二极与第一参考电压源连接，第三晶体管的栅极与参考线连接；第四晶体管的第一极与参考线连接，第四晶体管的第二极与第一参考电压源连接，第四晶体管的栅极与位线连接；第五晶体管的第一极与位线连接，第五晶体管的第二极与第二参考电压源连接，第五晶体管的栅极与参考线连接；第六晶体管的第一极与参考线连接，第六晶体管的第二极与第二参考电压源连接，第六晶体管的栅极与位线连接。
示例性的，预充电电路可以包括：第七晶体管和第八晶体管。其中：第七晶体管的第一极与位线连接，第七晶体管的第二极与预充电电压源连接，第七晶体管的栅极与预充电控制线连接；第八晶体管的第一极与预充电电压源连接，第八晶体管的第二极与参考线连接，第八晶体管的栅极与预充电控制线连接。
可选地，预充电电路中还可以包括第九晶体管。第九晶体管的第一极与位线连接，第九晶体管的第二极与参考线连接，第九晶体管的栅极与预充电控制线连接。当预充电电路工作时，导通的第九晶体管可以进一步保证位线和参考线上的电压相等。
可选地，在本申请实施例中，预充电电路中第七晶体管、第八晶体管和第九晶体管均为N沟道晶体管或者均为P沟道晶体管，在此不作限定。
可选地，在本申请实施例提供的位线读取电路中，还可以包括选择电路；选择电路与位线和参考线连接，用于读取位线和参考线上的数据，或者向位线和参考线写入数据。本申请的位线读取电路不仅可以实现数据的输出，还可以实现数据的写入。
示例性的，该选择电路可以包括第十晶体管和第十一晶体管。第十晶体管的第一极用于写入数据或者读取数据，第十晶体管的第二极与位线连接，第十晶体管的栅极与第一选择控制线连接，第十一晶体管的第一极用于写入数据或者读取数据，第十一晶体管的第二极与参考线连接，第十一晶体管的栅极与第二选择控制线连接。当选择电路工作时，第一选择控制线控制第十晶体管导通，从而通过导通的第十晶体管向位线写入数据或者读取位线上的数据。第二选择控制线控制第十一晶体管导通，从而通过导通的第十一晶体管向参 考线写入数据或者读取参考线上的数据。
可选地，在本申请实施例中，位线读取电路连接的参考线可以为互补位线，一般选中的位线与互补位线所连接的铁电存储单元不连接同一字线，这样当位线读取电路读取选中的位线时，互补位线的电压不受其所连接的铁电存储单元影响。
需要说明的是，本申请对位线BL和互补位线/BL的位置不作限定，例如位线和互补位线可以是存储器中同一存储阵列中的两条位线，也可以是存储器中不同存储阵列中的两条位线。
需要说明的是，本申请上述实施例中提到的晶体管可以是薄膜晶体管(Thin Film Transistor，TFT)，也可以是金属氧化物半导体场效应管(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)，在此不作限定。在具体实施时，晶体管的第一极和第二极中之一为源极，另一为漏极，晶体管的源极和漏极可以互换，不做具体区分。
可选地，本申请中，位线读取电路中还可以包括控制器；控制器用于在灵敏放大器对位线和参考线上的电压进行差分放大后进行输出时使第一开关和第二开关截止，以及在向位线和参考线写入数据时使第一开关和第二开关截止。
示例性的，该控制器还用于控制灵敏放大器和预充电电路，以使灵敏放大器对位线和参考线上的电压进行差分放大后输出，使预充电电路对位线和参考线预充电。
示例性的，该控制器还可以控制选择电路读取位线和参考线上的数据，或者控制选择电路向位线和参考线写入数据。
在具体实施时，控制器可以通过逻辑电路实现，本领域技术人员可以根据功能来得到具体的电路结构，在此不作限定。
进一步地，控制器可以在时序控制器的控制下第一开关、第二开关、预充电电路、灵敏放大器以及位线读取电路的工作时序。
第二方面，本申请实施例还提供了一种应用于如第一方面或第一方面的各种实施方式所述的位线读取电路的读取方法，该读取方法可以包括以下步骤：
第一阶段：第一开关和第二开关导通，预充电电路对位线和参考线预充电；
第二阶段：第一开关和第二开关导通，预充电电路关闭；
第三阶段：第一开关和第二开关导通，灵敏放大器对位线和参考线上的电压进行差分放大；
第四阶段：第一开关和第二开关截止，预充电电路对位线和参考线预充电；灵敏放大器将位线和参考线上的电压输出，或者向位线和参考线写入数据；
第五阶段：第一开关和第二开关导通，预充电电路关闭预设时间后打开。
下面结合时序对本申请实施例提供的位线读取电路的工作过程作以描述。
在①阶段(节点(铁电存储单元中晶体管的第二极)预充阶段)，选中的铁电存储单元所连接的字线开启一段时间后关闭，在字线开启期间，节点、位线和参考线被预充电电路预充至0V。
在②阶段(铁电翻转阶段)，位线和参考线被预充电电路预充至参考电压，同时选中的铁电电容所连接的板线上电压从V w/2上拉至V w，选中的铁电电容受到V w的压差，若铁电电容自身存储的数据与外加电场方向相反(数据“1”)，铁电电容极化方向将发生翻转并释放出极化电荷，使得节点的电位明显抬升；若铁电电容自身存储的数据与外加电场方向相同(数据“0”)，铁电电容极化方向不发生改变，节点电位抬升不明显。
在③阶段(电荷共享阶段)，预充电电路关闭，选中的铁电存储单元所连接的字线再次打开，节点和位线的电荷共享，位线上的电位取决于节点的电位，位线的电位会上抬(数据“1”)或者下降(数据“0”)一定幅值，参考线则维持在参考电压，两者最终形成稳定的电压差。
在④阶段(灵敏放大阶段)，将第一参考电压源下拉到0，第二参考电压源SAP上拉到V w，灵敏放大电路开始工作，如果铁电存储单元中选中的铁电电容存储的数据为“1”，灵敏放大器将位线拉高为V w，参考线拉低为0。如果铁电存储单元中选中的铁电电容存储的数据为“0”，灵敏放大器将参考线拉高为V w，位线拉低为0。从而灵敏放大器实现对位线和参考线上的电压进行差分放大，进而读出选中的铁电电容存储的信息。
在⑤阶段(读写阶段)，第一开关和第二开关截止，预充电电路打开，节点、第一开关右侧的位线和第二开关右侧的参考线被预充电电路预充至V w/2，如果是读取操作，第一开关左侧的位线和第二开关左侧的参考线则维持④阶段时的电压，如果为写操作，第一开关左侧的位线和第二开关左侧的参考线则被改写至新的电压。
在⑥阶段(回写阶段)，第一开关和第二开关导通，预充电电路关闭预设时间后打开，与此同时板线下拉至0再回复至V w/2,节点，第一开关右侧的位线和第二开关右侧的参考线则被第一开关左侧的位线和第二开关左侧的互补位驱动至相应电位。如果节点电压为V w，则铁电电容将被回写成数据“1”；如果节点电压为0，则铁电电容将维持在数据“0”。随后字线WL关闭，完成回写阶段所有操作。
由上述工作过程可知，由于第一开关和第二开关的引入，在⑤阶段，节点、第一开关右侧的位线和第二开关右侧的参考线得以维持在V w/2，使得非选中的铁电电容两端压差为0，从而避免了在该阶段非选中铁电电容的“半选”电压干扰。
第三方面，本申请实施例还提供了一种存储器，包括铁电存储单元以及如第一方面或第一方面的各种实施方式所述的位线读取电路，铁电存储单元包括并联的多个铁电电容以及与多个铁电电容连接的晶体管，晶体管的栅极与字线连接，晶体管的第一极与位线连接，晶体管的第二极与并联的多个铁电电容连接。由于该存储器解决问题的原理与前述一种位线读取电路相似，因此该存储器的实施可以参见前述位线读取电路的实施，重复之处不再赘述。由于本申请提出的位线读取电路可以降低铁电电容处于“半选”状态的时间，因此包含该位线读取电路的存储器同样可以降低铁电电容处于“半选”状态的时间。
可选地，在本申请实施例中，存储器还可以包括控制逻辑，控制逻辑用于：导通铁电存储单元；将位线上的电平读出。本申请实施例中，控制逻辑可以是存储器中的控制器，在此不作限定。
第四方面，本申请实施例还提供了一种电子设备，包括处理器以及与所述处理器耦合的如第三方面所述的存储器。
具体地，处理器可以调用存储器中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。
上述第三方面和第四方面可以达到的技术效果可以参照上述第一方面中任一可能设计可以达到的技术效果说明，这里不再重复赘述。
附图说明
图1为本申请实施例提供的铁电存储器中一个铁电存储单元的结构示意图；
图2为本申请实施例中存储器的一种结构示意图；
图3为常用位线读取电路的结构示意图；
图4为本申请实施例中位线读取电路的一种结构示意图；
图5为本申请实施例中位线读取电路的一种具体结构示意图；
图6为本申请实施例中位线读取电路的另一种具体结构示意图；
图7为图6所示的位线读取电路对应的电路时序图；
图8为本申请实施例提供的电子设备的结构示意图。
附图标记说明：
1             存储器；               2            处理器；
10            存储单元阵列；         20           差分放大器；
30            列解码器；             40           行解码器；
50            数据缓冲器；           WL           字线；
201           位线读取电路；         101          铁电存储单元；
001           预充电电路；           002          灵敏放大器；
0031          第一开关；             0032         第二开关；
004           选择电路；             005          控制器；
BL            位线；                 PCH          预充电控制线；
REF           参考线；               /BL          互补位线；
PLi           板线；                 Ci           铁电电容；
T1            第一晶体管；           T2           第二晶体管；
T3            第三晶体管；           T4           第四晶体管；
T5            第五晶体管；           T6           第六晶体管；
T7            第七晶体管；           T8           第八晶体管；
T9            第九晶体管；           T10          第十晶体管；
T11           第十一晶体管；         YS1          第一选择控制线；
YS2           第二选择控制线；       ISO1         第一隔离控制线；
ISO2          第二隔离控制线；       SAN          第一参考电压源；
SAP           第二参考电压源；       VBLP         预充电电压源。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实 施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
本申请实施例提出的位线读取电路可以应用于电子设备的存储器(例如内部存储器和外部缓存器)中。电子设备可以为计算机系统，如服务器、台式机电脑和笔记本电脑，本申请实施例中的存储器具体可以应用于上述计算机系统靠近中央处理器(Central Processing Unit，CPU)的最后一个缓存。此外上述电子设备还可以为手机等移动终端产品，本申请对电子设备的类型不做具体限制。存储器具体可以为动态随机存取存储器(DRAM)。本申请中的存储器可以具体用于存储数据，可以进行数据的写入以及读取。存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。
参见图2，图2示例性示出了本申请实施例中存储器的一种结构示意图。存储器1可以包括存储单元阵列10和差分放大器20。
存储单元阵列10可以包括阵列排布的多个铁电存储单元101，以及与各铁电存储单元101连接的字线WL和位线BL；每个铁电存储单元101包括晶体管T0和多个铁电电容C1～Cn。每行的晶体管T0与同一根字线WL连接，每列的晶体管T0与同一根位线BL连接。通常来说，晶体管T0的源极或漏极被连接至与其对应的位线BL上，而晶体管T0的栅极被连接至与其对应的字线WL上。
差分放大器20可以包括多个位线读取电路(图1中未示出)，每一位线读取电路分别连接一条参考线和一条位线BL，位线读取电路可以将与其连接的位线BL和参考线的电压进行差分放大，并且输出位线的电平。
在本申请的实施例中，存储器1还可以包括列解码器30、行解码器40和数据缓冲器50。其中，列解码器30用于将位线BL地址信息解码，确定要读写的位线BL地址；行解码器40用于将板线PLi(i为1至n的任意数)和字线WL地址信息解码，确定要读写的字线WL地址和要写的铁电电容Ci的地址；数据缓冲器50用于将从位线读取电路输出的位线电平传到外部电路。
参见图3，图3为常用的位线读取电路201’的结构示意图。位线读取电路201’包括预充电电路001’和灵敏放大器(Sense amplifier，SA)002’；位线读取电路201’工作时需要在预充电电路001’完成预充电后由灵敏放大器002’进行电压差分放大，在灵敏放大器002’完成电压差分放大后读出。
继续参见图3，在一个1TnC的铁电储存单元101中，n个铁电电容C1～Cn的一端分别由n个板线PL1～PLn控制，这n个铁电电容C1～Cn的另一端则连接到铁电存储单元101内公共的节点FN，节点FN连到场效应晶体管T0的源极一端，场效应晶体管T0的漏极一端连接到公共的位线BL，场效应晶体管T0的栅极则连到字线WL。由于n个铁电电容C1～Cn有一端连在了公共的节点FN上，为了区分这n个铁电电容C1～Cn中的选中的铁电电容和未选中的n-1个铁电电容，未选中的铁电电容在读写过程中将承受“半选”的外加电压V w/2，亦即选中铁电电容承受的电压V w的一半。通常“半选”电压V w/2小于矫顽场电压V c，所以未选中的铁电电容不会释放出显著的极化电荷。为了和传统DDR DRAM协议兼容，在一行铁电存储单元101激活之后直至下一个预充电命令之前，选中的铁电存储单元101中的节点FN因为与灵敏放大器002’相连，将长时间处于0或者V w的电压状态，而未选中的板线PL处于V w/2，因此铁电存储单元101中未选中的铁电电容(例如图3中C2～Cn)将处于“半选”电压状态。但是如果铁电电容长时间处于“半选”电压下，铁电电容内在的自 发极化强度也会受到明显的改变，进而影响到信息读取的窗口大小。为了改善铁电电容因长时间受到“半选”电压干扰而发生极化状态的改变，通常需要对铁电电容进行周期性的刷新操作。因此，避免铁电电容长时间处于“半选”状态是保证铁电存储器正常工作的必然要求，也将减小铁电电容刷新的频率。
有鉴于此，本申请实施例提供了一种位线读取电路，用于降低1TnC铁电存储单元在读写过程中铁电电容处在“半选”状态的时间。
参见图4，图4示例性示出了本申请实施例中位线读取电路的一种结构示意图。该位线读取电路201用于从铁电存储单元101中读取电平，该位线读取电路201可以包括位线BL、参考线REF、预充电电路001、灵敏放大器002、第一开关0031和第二开关0032。位线BL与铁电存储单元101相连，铁电存储单元101一般包括n个铁电电容C1～Cn和一个晶体管T0，其中n为大于或等于2的整数，晶体管T0的栅极与字线WL连接，晶体管T0的第一极与位线BL连接，晶体管T0的第二极与节点FN连接，节点FN与该n个铁电电容C1～Cn中每一铁电电容Ci(i为1～N中的任意数)的一端连接，而每一铁电电容Ci的另一端分别对应连接有一条板线PLi。灵敏放大器002分别与位线BL和参考线REF连接，用于对位线BL和参考线REF上的电压进行差分放大；预充电电路001分别与位线BL和参考线REF连接，用于对位线BL和参考线REF预充电；第一开关0031连接于灵敏放大器002与预充电电路之间的位线BL上，用于导通或者断开灵敏放大器002与预充电电路001之间的位线BL；第二开关0032连接于灵敏放大器002与预充电电路001之间的参考线REF上，用于导通或者断开灵敏放大器002与预充电电路001之间的参考线REF。这样，该位线读取电路201在读写阶段时，灵敏放大器002正常工作，第一开关0031使灵敏放大器002与预充电电路001之间的位线BL断开，第二开关0032使灵敏放大器002与预充电电路001之间的参考线REF断开，从而位线BL可以被预充电电路001拉到与铁电存储单元101中未选中的铁电电容Ci所连接的板线PLi相同的电压，例如未选中的铁电电容Ci所连接的板线PLi上的电压为V w/2，那么位线BL就被预充电电路001拉到V w/2，这样未选中的铁电电容Ci的两端的电压就相同，从而在读写阶段不会处于“半选”状态，进而可以降低铁电电容处于“半选”状态的时间。
需要说明的是，在本申请中，预充电电路001与灵敏放大器002相比，预充电电路001在位线BL上的连接位置更为靠近铁电存储单元101，参见图4，即铁电存储单元101的信息通过位线BL先传输至预充电电路001，然后通过第一开关0031传输至灵敏放大器002；对应的，预充电电路001充至参考线REF上的信号需要通过第二开关0032才能传输至灵敏放大器002。
下面结合具体实施例，对本申请进行详细说明。需要说明的是，本实施例中是为了更好的解释本申请，但不限制本申请。
参见图5，图5示例性示出了本申请实施例中位线读取电路的一种具体结构示意图。在该位线读取电路201中，第一开关0031可以包括第一晶体管T1，第一晶体管T1的栅极与第一隔离控制线ISO1连接，第一晶体管T1的第一极和第二极连接于灵敏放大器002与预充电电路001之间的位线BL上，第一晶体管T1的第一极连接于位线BL靠近预充电电路001的一端BL_a，第一晶体管T1的第二极连接于位线BL靠近灵敏放大器002的一端BL_b，当第一隔离控制线ISO1控制第一开关0031导通时，位线BL靠近预充电电路001的一端BL_a与位线BL靠近灵敏放大器002的一端BL_b导通，两端可以实现信 号传输，当第一隔离控制线ISO1控制第一开关0031截止时，位线BL靠近预充电电路001的一端BL_a与位线BL靠近灵敏放大器002的一端BL_b断开，两端之间不能实现信号的传输，从而将预充电电路001与灵敏放大器002隔离开。
在具体实施时，第一晶体管T1可以是P型晶体管，也可以是N型晶体管，在此不作限定。当第一晶体管T1为P型晶体管时，第一隔离控制线ISO1为低电平时第一晶体管T1导通，第一隔离控制线ISO1为高电平时第一晶体管T1截止；当第一晶体管T1为N型晶体管时，第一隔离控制线ISO1为高电平时第一晶体管T1导通，第一隔离控制线ISO1为低电平时第一晶体管T1截止。
以上仅是举例说明第一开关的具体结构，在具体实施时，第一开关的具体结构不限于本申请实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
继续参见图5，在该位线读取电路201中，第二开关0032可以包括第二晶体管T2，第二晶体管T2的栅极与第二隔离控制线ISO2连接，第二晶体管T2的第一极和第二极连接于灵敏放大器002与预充电电路001之间的参考线REF上，第二晶体管T2的第一极连接于参考线REF靠近预充电电路001的一端REF_a，第二晶体管T2的第二极连接于参考线REF靠近灵敏放大器002的一端REF_b，当第二隔离控制线ISO2控制第二开关0032导通时，参考线REF靠近预充电电路001的一端REF_a与参考线REF靠近灵敏放大器002的一端REF_b导通，两端可以实现信号传输，当第二隔离控制线ISO2控制第二开关0032截止时，参考线REF靠近预充电电路001的一端REF_a与参考线REF靠近灵敏放大器002的一端REF_b断开，两端之间不能实现信号的传输，从而将预充电电路001与灵敏放大器002隔离开。
在具体实施时，第二晶体管T2可以是P型晶体管，也可以是N型晶体管，在此不作限定。当第二晶体管T2为P型晶体管时，第二隔离控制线ISO2为低电平时第二晶体管T2导通，第二隔离控制线ISO2为高电平时第二晶体管T2截止；当第二晶体管T2为N型晶体管时，第二隔离控制线ISO2为高电平时第二晶体管T2导通，第二隔离控制线ISO2为低电平时第二晶体管T2截止。
以上仅是举例说明第二开关的具体结构，在具体实施时，第二开关的具体结构不限于本申请实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
可选的，第一晶体管T1和第二晶体管T2可以均为如图6所示的N型晶体管，当然，第一晶体管T1和第二晶体管T2也可以均为P型晶体管。
示例性的，当第一晶体管T1和第二晶体管T2均为N型晶体管或者均为P型晶体管时，参见图6，第一隔离控制线ISO1与第二隔离控制线ISO2可以为同一控制线，即第一晶体管T1和第二晶体管T2同时被同一隔离控制线控制，从而可以减少控制线的数量，并且，第一晶体管T1和第二晶体管T2可以同步被控制，不需要额外设置同步控制电路，从而可以简化电路结构。
示例性的，参见图5和图6，灵敏放大器002的差分输入分别接位线BL和参考线REF，灵敏放大器002的差分输出分别接位线BL和参考线REF，以对位线BL和参考线REF上的电压进行差分放大。
示例性的，如图5和图6所示，灵敏放大器002可以包括：N型的第三晶体管T3、N型的第四晶体管T4、P型的第五晶体管T5和P型的第六晶体管T6；其中：第三晶体管T3的第一极与位线BL连接，第三晶体管T3的第二极与第一参考电压源SAN连接，第三 晶体管T3的栅极与参考线REF连接；第四晶体管T4的第一极与参考线REF连接，第四晶体管T4的第二极与第一参考电压源SAN连接，第四晶体管T4的栅极与位线BL连接；第五晶体管T5的第一极与位线BL连接，第五晶体管T5的第二极与第二参考电压源SAP连接，第五晶体管T5的栅极与参考线REF连接；第六晶体管T6的第一极与参考线REF连接，第六晶体管T6的第二极与第二参考电压源SAP连接，第六晶体管T6的栅极与位线BL连接。
示例性的，参见图5和图6，预充电电路001可以包括：第七晶体管T7和第八晶体管T8。其中：第七晶体管T7的第一极与位线BL连接，第七晶体管T7的第二极与预充电电压源VBLP连接，第七晶体管T7的栅极与预充电控制线PCH连接；第八晶体管T8的第一极与预充电电压源VBLP连接，第八晶体管T8的第二极与参考线REF连接，第八晶体管T8的栅极与预充电控制线PCH连接。当预充电电路001工作时，预充电控制线PCH控制第七晶体管T7和第八晶体管T8均导通，预充电电压源VBLP的电压分别通过第七晶体管T7和第八晶体管T8传输至位线BL和参考线REF，从而使位线BL和参考线REF的电压相等。
可选的，在本申请中，预充电电路001还可以包括第九晶体管T9，第九晶体管T9的第一极与位线BL连接，第九晶体管T9的第二极与参考线REF连接，第九晶体管T9的栅极与预充电控制线PCH连接。当预充电电路001工作时，预充电控制线PCH控制第九晶体管T9导通，导通的第九晶体管T9可以进一步保证位线BL和参考线REF上的电压相等。
可选地，在本申请实施例中，预充电电路001中第七晶体管T7、第八晶体管T8和第九晶体管T9均为N沟道晶体管或者均为P沟道晶体管，在此不作限定。
可选地，在本申请实施例提供的位线读取电路中，如图6所示，还可以包括选择电路004；选择电路004与位线BL和参考线REF连接，用于读取位线BL和参考线REF上的数据，或者向位线BL和参考线REF写入数据。本申请的位线读取电路201不仅可以实现数据的输出，还可以实现数据的写入。
示例性的，参见图6，该选择电路004可以包括第十晶体管T10和第十一晶体管T11。第十晶体管T10的第一极用于写入数据或者读取数据，第十晶体管T10的第二极与位线BL连接，第十晶体管T10的栅极与第一选择控制线YS1连接，第十一晶体管T11的第一极用于写入数据或者读取数据，第十一晶体管T11的第二极与参考线REF连接，第十一晶体管REF的栅极与第二选择控制线YS2连接。当选择电路004工作时，第一选择控制线YS1控制第十晶体管T10导通，从而通过导通的第十晶体管T10向位线BL写入数据或者读取位线BL上的数据。第二选择控制线YS2控制第十一晶体管T11导通，从而通过导通的第十一晶体管T11向参考线REF写入数据或者读取参考线REF上的数据。
可选地，在本申请实施例中，如图6所示，位线读取电路201连接的参考线REF可以为互补位线/BL，一般选中的位线BL与互补位线/BL所连接的铁电存储单元101不连接同一字线，例如图6中，选中的位线BL所连接的铁电存储单元101所连接的字线WL和未选中的位线/BL所连接的铁电存储单元101所连接的字线/WL为不同的字线，这样当位线读取电路读取选中的位线BL时，互补位线/BL的电压不受其所连接的铁电存储单元101影响。
需要说明的是，本申请对位线BL和互补位线/BL的位置不作限定，例如位线BL和互补位线/BL可以是存储器中同一存储阵列中的两条位线，也可以是存储器中不同存储阵列 中的两条位线。
需要说明的是，本申请上述实施例中提到的晶体管可以是薄膜晶体管，也可以是金属氧化物半导体场效应管，在此不作限定。在具体实施时，晶体管的第一极和第二极中之一为源极，另一为漏极，晶体管的源极和漏极可以互换，不做具体区分。
可选地，本申请中，如图5所示，位线读取电路201中还可以包括控制器005；控制器005用于在灵敏放大器002对位线BL和参考线REF上的电压进行差分放大后进行输出时使第一开关0031和第二开关0032截止，以及在向位线BL和参考线REF写入数据时使第一开关0031和第二开关0032截止。
示例性的，如图6所示，该控制器005还用于控制灵敏放大器002和预充电电路001，以使灵敏放大器002对位线BL和参考线REF上的电压进行差分放大后输出，使预充电电路001对位线BL和参考线REF预充电。
示例性的，如图6所示，该控制器005还可以控制选择电路004读取位线BL和参考线REF上的数据，或者控制选择电路004向位线BL和参考线REF写入数据。
在具体实施时，控制器可以通过逻辑电路实现，本领域技术人员可以根据功能来得到具体的电路结构，在此不作限定。
进一步地，控制器可以在时序控制器的控制下第一开关、第二开关、预充电电路、灵敏放大器以及位线读取电路的工作时序。
相应地，本申请实施例还提供了一种应用于上述任一种位线读取电路的读取方法，该读取方法可以包括以下步骤：
第一阶段：所述第一开关和所述第二开关导通，所述预充电电路对所述位线和所述参考线预充电；
第二阶段：所述第一开关和所述第二开关导通，所述预充电电路关闭；
第三阶段：所述第一开关和所述第二开关导通，所述灵敏放大器对所述位线和所述参考线上的电压进行差分放大；
第四阶段：所述第一开关和所述第二开关截止，所述预充电电路对所述位线和所述参考线预充电；所述灵敏放大器将所述位线和所述参考线上的电压输出，或者向所述位线和所述参考线写入数据；
第五阶段：所述第一开关和所述第二开关导通，所述预充电电路关闭预设时间后打开。
下面结合时序对本申请实施例提供的位线读取电路的工作过程作以描述。具体地，以图6所示的位线读取电路为例，其对应的输入时序图如图7所示。
在①阶段(FN预充阶段)，选中的铁电存储单元101所连接的字线WL开启一段时间后关闭，在字线WL开启期间，节点FN、位线BL和互补位线/BL被预充电电路001预充至0V。
在②阶段(铁电翻转阶段)，位线BL和互补位线/BL被预充电电路001预充至参考电压V ref，同时选中的铁电电容例如C1所连接的板线PL1上电压从V w/2上拉至V w，选中的铁电电容C1受到V w的压差，若铁电电容C1自身存储的数据与外加电场方向相反(数据“1”)，铁电电容C1极化方向将发生翻转并释放出极化电荷，使得节点FN的电位明显抬升；若铁电电容C1自身存储的数据与外加电场方向相同(数据“0”)，铁电电容C1极化方向不发生改变，节点FN电位抬升不明显。
在③阶段(电荷共享阶段)，预充电电路001关闭，选中的铁电存储单元101所连接 的字线WL再次打开，节点FN和位线BL的电荷共享，位线BL上的电位取决于节点FN的电位，位线BL的电位会上抬(数据“1”)或者下降(数据“0”)一定幅值，互补位线/BL则维持在参考电压V ref，两者最终形成稳定的电压差。
在④阶段(灵敏放大阶段)，将第一参考电压源SAN下拉到0，第二参考电压源SAP上拉到V w，灵敏放大器002开始工作，如果铁电存储单元101中选中的铁电电容C1存储的数据为“1”导致位线BL电压上升，导致第四晶体管T4先导通，第一参考电压源SAN的电压通过第四晶体管T4传输至互补位线/BL，互补位线/BL的电压拉低，互补位线/BL控制第五晶体管T5导通，第二参考电压源SAP的电压通过第五晶体管T5传输至位线BL，位线BL的电压拉高，通过不断正反馈，实现位线BL拉高为V w，互补位线/BL拉低为0。如果铁电存储单元101中选中的铁电电容C1存储的数据为“0”，导致位线BL电压下降，第六晶体管T6先导通，第二参考电压源SAP的电压通过第六晶体管T6传输至互补位线/BL，互补位线/BL的电压拉高，互补位线/BL控制第三晶体管T3导通，第一参考电压源SAN的电压通过第三晶体管T3传输至位线BL，位线BL的电压拉低，通过不断正反馈，实现互补位线/BL拉高为V w，位线BL拉低为0。从而灵敏放大器002实现对位线BL和互补位线/BL上的电压进行差分放大，进而读出选中的铁电电容C1存储的信息。
在⑤阶段(读写阶段)，第一晶体管T1和第二晶体管T2截止，预充电电路001打开，节点FN、第一晶体管T1右侧的位线BL_a和第二晶体管T2右侧的互补位线/BL_a被预充电电路预充至V w/2，如果是读取操作，第一晶体管T1左侧的位线BL_b和第二晶体管T2左侧的互补位线/BL_b则维持④阶段时的电压，如果为写操作，第一晶体管T1左侧的位线BL_b和第二晶体管T2左侧的互补位线/BL_b则被改写至新的电压。
在⑥阶段(回写阶段)，第一晶体管T1和第二晶体管T2导通，预充电电路001先关闭后打开，与此同时板线PL1下拉至0再回复至V w/2,节点FN，第一晶体管T1右侧的位线BL_a和第二晶体管T2右侧的互补位线/BL_a则被第一晶体管T1左侧的位线BL_b和第二晶体管T2左侧的互补位线/BL_b驱动至相应电位。如果节点FN电压为V w，则铁电电容C1将被回写成数据“1”；如果节点FN电压为0，则铁电电容C1将维持在数据“0”。随后字线WL关闭，完成回写阶段所有操作。
由上述工作过程可知，由于第一晶体管T1和第二晶体管T2的引入，在⑤阶段，节点FN、第一晶体管T1右侧的位线BL_a和第二晶体管T2右侧的互补位线/BL_a得以维持在V w/2，使得非选中的铁电电容C2～Cn两端压差为0，从而避免了在该阶段非选中铁电电容C2～Cn的“半选”电压干扰。
本申请实施例提出的位线读取电路可以应用于存储器中。本申请提供的存储器，包括：本申请上述任意技术方案中的位线读取电路以及铁电存储单元，铁电存储单元包括并联的多个铁电电容以及与多个铁电电容连接的晶体管，晶体管的栅极与字线连接，晶体管的第一极与位线连接，晶体管的第二极与并联的多个铁电电容连接。在具体实施时，存储器的结构可以参见上述图2所示。由于该存储器解决问题的原理与前述一种位线读取电路相似，因此该存储器的实施可以参见前述位线读取电路的实施，重复之处不再赘述。由于本申请提出的位线读取电路可以降低铁电电容处于“半选”状态的时间，因此包含该位线读取电路的存储器同样可以降低铁电电容处于“半选”状态的时间。
可选地，在本申请实施例中，存储器还可以包括控制逻辑，控制逻辑用于：导通铁电存储单元；将位线上的电平读出。本申请实施例中，控制逻辑可以是存储器中的控制器， 在此不作限定。
基于同一技术构思，本申请实施例还提供一种电子设备。参见图8，该电子设备包括处理器2以及与处理器耦合的存储器1，存储器1可以是图2所示的存储器。
具体地，处理器2可以调用存储器1中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (14)

  1. 一种位线读取电路，其特征在于，用于从铁电存储单元中读取电平，其中所述位线读取电路包括：
    位线，与所述铁电存储单元相连；
    参考线；
    灵敏放大器，分别与所述位线和所述参考线连接，用于对所述位线和所述参考线上的电压进行差分放大后输出；
    预充电电路，分别与所述位线和所述参考线连接，用于对所述位线和所述参考线预充电；
    第一开关，连接于所述灵敏放大器与所述预充电电路之间的所述位线上；
    第二开关，连接于所述灵敏放大器与所述预充电电路之间的所述参考线上。
  2. 如权利要求1所述的位线读取电路，其特征在于，所述位线读取电路还包括控制器；
    所述控制器用于在所述灵敏放大器对所述位线和所述参考线上的电压进行差分放大后进行输出时使所述第一开关和所述第二开关截止，以及在向所述位线和所述参考线写入数据时使所述第一开关和所述第二开关截止。
  3. 如权利要求2所述的位线读取电路，其特征在于，所述控制器还用于控制所述灵敏放大器和所述预充电电路，以使所述灵敏放大器对所述位线和所述参考线上的电压进行差分放大后输出，使所述预充电电路对所述位线和所述参考线预充电。
  4. 如权利要求1-3任一项所述的位线读取电路，其特征在于，所述第一开关包括第一晶体管，和/或所述第二开关包括第二晶体管；
    所述第一晶体管的栅极与第一隔离控制线连接，所述第一晶体管的第一极和第二极连接于所述灵敏放大器与所述预充电电路之间的所述位线上；
    所述第二晶体管的栅极与第二隔离控制线连接，所述第二晶体管的第一极和第二极连接于所述灵敏放大器与所述预充电电路之间的所述参考线上。
  5. 如权利要求4所述的位线读取电路，其特征在于，所述第一晶体管和所述第二晶体管均为N型晶体管或均为P型晶体管。
  6. 如权利要求5所述的位线读取电路，其特征在于，所述第一隔离控制线与所述第二隔离控制线为同一控制线。
  7. 如权利要求1-6任一项所述的位线读取电路，其特征在于，所述灵敏放大器包括：N型的第三晶体管、N型的第四晶体管、P型的第五晶体管和P型的第六晶体管；其中：
    所述第三晶体管的第一极与所述位线连接，所述第三晶体管的第二极与第一参考电压源连接，所述第三晶体管的栅极与所述参考线连接；
    所述第四晶体管的第一极与所述参考线连接，所述第四晶体管的第二极与所述第一参 考电压源连接，所述第四晶体管的栅极与所述位线连接；
    所述第五晶体管的第一极与所述位线连接，所述第五晶体管的第二极与第二参考电压源连接，所述第五晶体管的栅极与所述参考线连接；
    所述第六晶体管的第一极与所述参考线连接，所述第六晶体管的第二极与所述第二参考电压源连接，所述第六晶体管的栅极与所述位线连接。
  8. 如权利要求1-6任一项所述的位线读取电路，其特征在于，所述预充电电路包括：第七晶体管和第八晶体管；其中：
    所述第七晶体管的第一极与所述位线连接，所述第七晶体管的第二极与预充电电压源连接，所述第七晶体管的栅极与预充电控制线连接；
    所述第八晶体管的第一极与所述预充电电压源连接，所述第八晶体管的第二极与所述参考线连接，所述第八晶体管的栅极与所述预充电控制线连接。
  9. 如权利要求8所述的位线读取电路，其特征在于，所述预充电电路还包括第九晶体管；
    所述第九晶体管的第一极与所述位线连接，所述第九晶体管的第二极与所述参考线连接，所述第九晶体管的栅极与所述预充电控制线连接。
  10. 如权利要求1-6任一项所述的位线读取电路，其特征在于，还包括选择电路，所述选择电路分别与所述位线和所述参考线连接，用于读取所述位线和所述参考线上的数据，或者向所述位线和所述参考线写入数据。
  11. 如权利要求10所述的位线读取电路，其特征在于，所述选择电路包括第十晶体管和第十一晶体管；
    所述第十晶体管的第一极用于写入数据或者读取数据，所述第十晶体管的第二极与所述位线连接，所述第十晶体管的栅极与第一选择控制线连接；
    所述第十一晶体管的第一极用于写入数据或者读取数据，所述第十一晶体管的第二极与所述参考线连接，所述第十一晶体管的栅极与第二选择控制线连接。
  12. 一种存储器，其特征在于，包括如权利要求1-11任一项所述的位线读取电路，以及铁电存储单元，所述铁电存储单元包括并联的多个铁电电容以及与所述多个铁电电容连接的晶体管，所述晶体管的栅极与字线连接，所述晶体管的第一极与所述位线连接，所述晶体管的第二极与并联的所述多个铁电电容连接。
  13. 一种电子设备，其特征在于，包括处理器以及与所述处理器耦合的如权利要求12所述的存储器。
  14. 一种应用于如权利要求1-11任一项所述的位线读取电路的读取方法，其特征在于，包括：
    第一阶段：所述第一开关和所述第二开关导通，所述预充电电路对所述位线和所述参 考线预充电；
    第二阶段：所述第一开关和所述第二开关导通，所述预充电电路关闭；
    第三阶段：所述第一开关和所述第二开关导通，所述灵敏放大器对所述位线和所述参考线上的电压进行差分放大；
    第四阶段：所述第一开关和所述第二开关截止，所述预充电电路对所述位线和所述参考线预充电；所述灵敏放大器将所述位线和所述参考线上的电压输出，或者向所述位线和所述参考线写入数据；
    第五阶段：所述第一开关和所述第二开关导通，所述预充电电路关闭预设时间后打开。
PCT/CN2023/070713 2022-04-20 2023-01-05 一种位线读取电路、存储器及电子设备 WO2023202166A1 (zh)

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