WO2023169075A1 - 读写电路、读写方法以及铁电存储器 - Google Patents

读写电路、读写方法以及铁电存储器 Download PDF

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WO2023169075A1
WO2023169075A1 PCT/CN2023/070639 CN2023070639W WO2023169075A1 WO 2023169075 A1 WO2023169075 A1 WO 2023169075A1 CN 2023070639 W CN2023070639 W CN 2023070639W WO 2023169075 A1 WO2023169075 A1 WO 2023169075A1
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Prior art keywords
voltage
transistor
bit line
sense amplifier
ferroelectric memory
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PCT/CN2023/070639
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English (en)
French (fr)
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徐亮
卜思童
方亦陈
刘晓真
许俊豪
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华为技术有限公司
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Publication of WO2023169075A1 publication Critical patent/WO2023169075A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Definitions

  • the present application relates to the field of data storage technology, and specifically to a read and write circuit, a read and write method for a ferroelectric memory array, and a ferroelectric memory.
  • Ferroelectric memory or ferroelectric random access memory includes one or more ferroelectric capacitors (capacitors, C). Ferroelectric capacitors serve as memory cells and can be used to store information. Among them, a ferroelectric crystal is deposited between the two electrode plates of the ferroelectric capacitor, and the ferroelectric effect of the ferroelectric crystal can be used to achieve data storage.
  • the iron atom in the crystal center of a ferroelectric crystal has two stable states or polarization states. These two polarization states can be set as negative polarization state and positive polarization state respectively.
  • the ferroelectric effect means that when a certain electric field is applied to a ferroelectric crystal, the central atom of the crystal moves under the action of the electric field and reaches a stable state (or negative polarization state); when the electric field is removed from the crystal, the central atom will remain in its original position. This is because there is a high energy level between the two states of the crystal, and the central atom cannot cross the high energy level to reach another stable position (or positively polarized state) without obtaining external energy. Therefore, ferroelectric memory can retain data in the event of power outage, is non-volatile, and can be used as non-volatile memory.
  • the remnant polarization (Pr) of the ferroelectric capacitor corresponding to the negative polarization state represents the proportion of iron atoms in the ferroelectric capacitor that are in the negative polarization state. That is to say, when the Pr corresponding to the negative polarization state of the ferroelectric capacitor is high, the information corresponding to the negative polarization state stored in the ferroelectric capacitor can be clearly read. If the Pr corresponding to the negative polarization state of the ferroelectric capacitor is low, it may be difficult to read the information corresponding to the negative polarization state stored in the ferroelectric capacitor.
  • Embodiments of the present application provide a read and write circuit, a read and write method for a ferroelectric memory array, and a ferroelectric memory, which can reduce the power consumption and cost of the ferroelectric memory.
  • a read-write circuit for a ferroelectric memory array includes a first ferroelectric memory unit; the read-write circuit includes a sense amplifier coupled to a first bit line of the first ferroelectric memory unit. and a first reference bit line; a first voltage switching circuit connected to the sense amplifier for outputting a first voltage or a second voltage to the sense amplifier; a second voltage switching circuit connected to the sense amplifier for outputting a third voltage to the sense amplifier Or a fourth voltage; wherein, first voltage>second voltage>third voltage>fourth voltage.
  • the sense amplifier when the voltage on the first bit line is higher than the voltage on the first reference bit line, the sense amplifier is used to output the first voltage or the second voltage to the first bit line and output the third voltage to the first reference bit line. Or fourth voltage.
  • the sense amplifier When the voltage on the first bit line is lower than the voltage on the first reference bit line, the sense amplifier is used to output a first voltage or a second voltage to the first reference bit line, and to output a third voltage or a third voltage to the first bit line.
  • the read-write circuit provided by the embodiment of the present application can output different voltages to the sensitive amplifier at a specific stage. For example, during the read and write phase of the first ferroelectric memory cell, a second voltage or a third voltage smaller than the first voltage is output to the sense amplifier, so that the sense amplifier can output the second voltage or the third voltage to the first bit line, That is, the sensitive amplifier applies a smaller voltage to the first bit line during the reading and writing stage of the first ferroelectric memory unit. Therefore, a smaller voltage can be used to transmit the information on the first bit line to the processor. That is, the operating voltage on the data path between the first bit line and the processor is reduced, thereby reducing the read and write power consumption of the ferroelectric memory unit.
  • the first voltage and the fourth voltage with a relatively large voltage difference can be output to the sense amplifier, so that the sense amplifier can output the first voltage or the fourth voltage to the first bit line.
  • the sense amplifier can output the first voltage or the fourth voltage to the first bit line.
  • embodiments of the present application provide a read and write circuit for a ferroelectric memory array, which can output voltages of different sizes to the sensitive amplifier and then output voltages of different sizes to the first bit line to achieve different operations on the ferroelectric memory cells. , and its simple structure helps reduce the size and cost of ferroelectric memory.
  • the second voltage switching circuit when the first voltage switching circuit is used to output a first voltage to the sense amplifier, the second voltage switching circuit is used to output a fourth voltage to the sense amplifier; when the first voltage switching circuit is used to output a fourth voltage to the sense amplifier; When the sense amplifier outputs the second voltage, the second voltage switching circuit is used to output a third voltage to the sense amplifier.
  • the second voltage switching circuit when the first voltage switching circuit is used to output the first voltage to the sense amplifier, the second voltage switching circuit is used to output the fourth voltage to the sense amplifier, so that the sense amplifier can output the third voltage to the first bit line.
  • a voltage or a fourth voltage enables the first ferroelectric memory cell to complete recovery or write back after being damaged.
  • the second voltage switching circuit is used to output the third voltage to the sense amplifier, so that the sense amplifier can output the second voltage or the third voltage to the first line.
  • a smaller voltage smaller than the write voltage Vw can be used to transfer the information on the first bit line to the processor, that is, the operating voltage on the data path between the first bit line and the processor is reduced, and thus Reduce the read and write power consumption of ferroelectric memory cells.
  • the first voltage is the write voltage Vw of the first ferroelectric memory cell
  • the fourth voltage is the zero voltage V0 of the first ferroelectric memory cell
  • the first voltage and the fourth voltage are respectively the write voltage Vw and the zero voltage V0 of the first ferroelectric memory cell, which can cause the sense amplifier to output the write voltage Vw or the zero voltage V0 to the first bit line, so that the This allows the first ferroelectric storage unit to complete recovery or write-back after being damaged.
  • the first voltage switching circuit includes a first transistor and a second transistor; wherein, the first electrode of the first transistor is connected to the sense amplifier, and the second electrode is connected to the first drive circuit; and the second electrode of the second transistor is connected to the sense amplifier.
  • One pole is connected to the sense amplifier, and the second pole is connected to the second drive circuit; when the first transistor is turned on, the first drive circuit is used to output the first voltage to the sense amplifier through the first transistor; when the second transistor is turned on , the second driving circuit is used to output a second voltage to the sense amplifier through the second transistor; the second voltage switching circuit includes a third transistor and a fourth transistor; wherein the first pole of the third transistor is connected to the sense amplifier, and the second pole is connected to A third drive circuit; the first pole of the fourth transistor is connected to the sense amplifier, and the second pole is connected to the fourth drive circuit; wherein, when the third transistor is turned on, the third drive circuit is used to output the third drive circuit to the sense amplifier through the third transistor. Three voltages; when the fourth transistor is turned on, the fourth driving circuit is used to output the fourth voltage to the sense amplifier through the fourth transistor.
  • This embodiment provides a specific implementation form of the voltage switching circuit, which has a simple structure, stable performance, and high reliability, and can further reduce the cost and reliability of the ferroelectric memory.
  • the first voltage switching circuit is used to output the first voltage or the second voltage to the first line of the sense amplifier
  • the second voltage switching circuit is used to output the third voltage to the second line of the sense amplifier. or fourth voltage.
  • the first voltage switching circuit can provide voltage to the first line of the sense amplifier
  • the second switching circuit can provide voltage to the second line of the sense amplifier, so that the sense amplifier can supply voltage to the first line and the third line.
  • a reference bit line outputs a corresponding voltage to realize reading and writing of the first ferroelectric memory cell.
  • the first line is a pull-up signal wiring
  • the second line is a pull-down signal wiring
  • the sense amplifier includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; wherein the first line is connected to the first pole of the seventh transistor, and is connected to the first pole of the eighth transistor.
  • One pole; the second line is connected to the first pole of the fifth transistor, and is connected to the first pole of the sixth transistor; the first line is connected to the second pole of the seventh transistor, and is connected to the gate electrode of the sixth transistor; the first reference The bit line is connected to the second electrode of the sixth transistor and to the gate of the seventh transistor; when the voltage on the first bit line is higher than the voltage on the first reference bit line, the seventh transistor is turned on, so that the seventh transistor is turned on.
  • One line outputs the first voltage or the second voltage to the first bit line; when the first line outputs the first voltage or the second voltage to the first bit line, the sixth transistor is turned on, causing the second line to output the first voltage to the first reference bit.
  • the line outputs the third voltage or the fourth voltage.
  • This embodiment provides a specific implementation form of the sensitive amplifier, which has a simple structure, stable performance, and high reliability, and can further reduce the cost and reliability of the ferroelectric memory.
  • the first bit line is connected to the second electrode of the fifth transistor and to the gate of the eighth transistor;
  • the first reference bit line is connected to the second electrode of the eighth transistor and to the gate of the fifth transistor. gate; when the voltage on the first bit line is lower than the voltage on the first reference bit line, the eighth transistor is turned on, causing the first line to output the first voltage or the second voltage to the first reference bit line; when When the first line applies the first voltage or the second voltage to the first reference bit line, the fifth transistor is turned on, so that the second line outputs the third voltage or the fourth voltage to the first bit line.
  • This embodiment provides a specific implementation form of the sensitive amplifier, which has a simple structure, stable performance, and high reliability, and can further reduce the cost and reliability of the ferroelectric memory.
  • the ferroelectric memory array further includes a second ferroelectric memory unit; the second ferroelectric memory unit and the first ferroelectric memory unit are connected to different first electrodes and connected to the same second electrode; The electrode is connected to the first line.
  • the ferroelectric memory array includes a second ferroelectric memory cell sharing a second electrode with the first ferroelectric memory cell, wherein the second electrode is connected to the first bit line, that is, the first ferroelectric memory cell and the second ferroelectric memory cell.
  • the ferroelectric memory cell is connected to the first bit line at the same time.
  • the sense amplifier can output a second voltage or a third voltage to the first bit line, wherein the second voltage and the third voltage are both smaller than the first voltage, And both are greater than the fourth voltage.
  • the second ferroelectric memory unit can be reduced in the read and write phase of the first ferroelectric memory unit.
  • the voltage difference between the two ends of the second ferroelectric memory unit can be reduced, thereby reducing the number of atoms whose polarization state is reversed in the second ferroelectric memory unit, so that the second ferroelectric memory unit can maintain the residual polarization intensity and improve the memory performance of the ferroelectric memory array. reliability.
  • the ferroelectric memory array further includes a third ferroelectric memory unit; the third ferroelectric memory unit and the first ferroelectric memory unit share a first electrode, and the second electrode of the third ferroelectric memory unit is The electrode and the second electrode of the first ferroelectric memory cell are respectively connected to the first bit line through different transistors.
  • the ferroelectric memory array includes a third ferroelectric memory cell sharing a first electrode with the first ferroelectric memory cell, and the second electrode of the third ferroelectric memory cell and the third ferroelectric memory cell The two electrodes are respectively connected to the first bit line through different transistors.
  • the sense amplifier can output a second voltage or a third voltage to the first bit line, wherein the second voltage and the third voltage are both smaller than the first voltage, And both are greater than the fourth voltage.
  • the voltage difference between the source and the drain of the transistor of the third ferroelectric memory unit can be reduced, thereby reducing the leakage current of the transistor of the third ferroelectric memory unit, and reducing the second electrode of the third ferroelectric memory unit.
  • the offset between the actual voltage and the theoretical voltage This can reduce the voltage difference between the two ends of the third ferroelectric memory unit, that is, reduce the risk of polarization state reversal of the third ferroelectric memory unit, reduce the risk of errors in stored information, and improve the memory location of the ferroelectric memory array. reliability.
  • the read and write circuit further includes: an equalizer, coupled to the first bit line and the first reference bit line; the equalizer is used to output different voltages to the first bit line at different times, and at different times. Different voltages are output to the first reference bit line at all times.
  • the equalizer included in the read and write circuit can output different voltages to the first bit line and the first reference bit line at different times.
  • the voltage Vpre1 can be output to the first bit line and the first reference bit line; during the destruction phase of the first ferroelectric memory cell, the voltage Vpre1 can be output to the first bit line and the first reference bit line.
  • the reference bit line outputs voltage Vpre2; during the standby phase of the first ferroelectric memory cell, voltage 1/2Vw is output to the first bit line and the first reference bit line.
  • the equalizer can output different voltages to the first bit line and the first reference bit line at different times, thereby realizing time division multiplexing of the equalizer and reducing the cost of the read and write circuits.
  • a method for reading and writing a ferroelectric memory array includes a first ferroelectric memory unit.
  • the method is applied to a read-write circuit.
  • the read-write circuit includes a sense amplifier, a first voltage switching circuit, In a second voltage switching circuit, the sense amplifier is coupled to the first bit line and the first reference bit line of the first ferroelectric memory cell; the method includes: the first voltage switching circuit outputs the first voltage or the second voltage to the sense amplifier; The two voltage switching circuits output a third voltage or a fourth voltage to the sense amplifier; where, the first voltage > the second voltage > the third voltage > the fourth voltage; when the voltage on the first bit line is higher than the first reference bit line When the voltage is , the sense amplifier outputs a first voltage or a second voltage to the first bit line, and outputs a third voltage or a fourth voltage to the first reference bit line.
  • the method further includes: when the voltage on the first bit line is lower than the voltage on the first reference bit line, the sense amplifier outputs the first voltage or the second voltage to the first reference bit line. , outputting the third voltage or the fourth voltage to the first reference bit line.
  • the first voltage switching circuit outputting the first voltage or the second voltage to the sense amplifier, and the second voltage switching circuit outputting the third voltage or the fourth voltage to the sense amplifier include: the first voltage switching circuit outputting the first voltage to the sense amplifier.
  • the sense amplifier outputs a first voltage
  • the second voltage switching circuit outputs a fourth voltage to the sense amplifier; or, when the first voltage switching circuit outputs a second voltage to the sense amplifier, the second voltage switching circuit outputs a third voltage to the sense amplifier.
  • the first voltage is the write voltage Vw of the first ferroelectric memory cell
  • the fourth voltage is the zero voltage V0 of the first ferroelectric memory cell
  • the first voltage switching circuit outputting the first voltage or the second voltage to the sense amplifier, and the second voltage switching circuit outputting the third voltage or the fourth voltage to the sense amplifier include: the first voltage switching circuit outputting the first voltage to the sense amplifier.
  • the first line of the sense amplifier outputs a first voltage or a second voltage
  • the second voltage switching circuit outputs a third voltage or a fourth voltage to the second line of the sense amplifier.
  • the ferroelectric memory array further includes a second ferroelectric memory unit; the first electrode of the second ferroelectric memory unit and the first ferroelectric memory unit are connected to different first electrodes, and are connected to the same second ferroelectric memory unit. electrode; the second electrode is connected to the first line.
  • the ferroelectric memory array further includes a third ferroelectric memory unit; the third ferroelectric memory unit and the first ferroelectric memory unit share a first electrode, and the second electrode of the third ferroelectric memory unit is The electrode and the second electrode of the first ferroelectric memory cell are respectively connected to the first bit line through different transistors.
  • the first line is a pull-up signal wiring
  • the second line is a pull-down signal wiring
  • the method provided in the second aspect can be implemented by the read-write circuit provided in the first aspect. Therefore, the beneficial effects of the method provided in the second aspect can be referred to the beneficial effects of the read-write circuit provided in the first aspect. The introduction will not be repeated here.
  • a memory including a read-write circuit in the first aspect and a ferroelectric memory array.
  • Figure 1 is a schematic structural diagram of a ferroelectric memory array provided by an embodiment of the present application.
  • Figure 2A is a schematic structural diagram of a DRAM read and write circuit
  • Figure 2B is a schematic structural diagram of a read and write circuit for operating the ferroelectric memory array shown in Figure 1;
  • Figure 3A is the equivalent circuit diagram of a ferroelectric capacitor sharing BL and PL;
  • Figure 3B is a schematic diagram of the voltage difference between the two ends of the ferroelectric capacitor that shares BL and PL with the selected ferroelectric capacitor;
  • Figure 4 is a schematic structural diagram of a read and write circuit for controlling the ferroelectric memory array shown in Figure 1 provided by an embodiment of the present application;
  • Figure 5 is a flow chart of a memory cell array operating method provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of the voltage on electrode B1 and electrode B2 of ferroelectric capacitor C2 during the reading and writing stage of ferroelectric capacitor C1.
  • Figure 1 shows a ferroelectric memory array consisting of multiple 1TnC structures.
  • 1T refers to a transistor (transistor, T)
  • nC refers to n ferroelectric capacitors (capacitor, C)
  • n is a positive integer greater than or equal to 1.
  • a 1TnC structure includes a transistor and n ferroelectric capacitors.
  • the transistor can be manufactured using a back end of line (BEOL) process. Therefore, the transistor can also be called a back end of line transistor or back end tube. That is, the transistor in the 1TnC structure is manufactured using a back end of line process. production.
  • BEOL back end of line
  • the transistor has a gate (G), an electrode A1 and an electrode A2.
  • the electrode A1 of the transistor may be the source (S) of the transistor, and the electrode A2 of the transistor may be the drain (D) of the transistor.
  • electrode A1 of the transistor may be the drain of the transistor, and electrode A2 of the transistor may be the source of the transistor. That is to say, electrode A1 can be either a source electrode or a drain electrode; electrode A2 can be either a source electrode or a drain electrode.
  • electrode A1 when electrode A1 is the source electrode, electrode A2 is the drain electrode; when electrode A1 is the drain electrode, electrode A2 is the source electrode.
  • the transistor Under the action of the gate, the transistor can generate two-dimensional electron gas (2DEG) to conduct electrode A1 and electrode A2.
  • the ferroelectric capacitor has electrode B1 and electrode B2. Among them, the ferroelectric capacitors on the same layer in the ferroelectric memory array shown in Figure 1 share the electrode B1.
  • the n ferroelectric capacitors in the same 1TnC structure are located in different layers and share the same electrode B2. In other words, n ferroelectric capacitors in the same 1TnC structure are connected to different electrodes B1 and connected to the same electrode B2. For example, the electrodes B1 of different layers are parallel to each other.
  • the electrodes B2 of the n ferroelectric capacitors in the same 1TnC structure are connected to the electrodes A2 of the transistors in the 1TnC structure. That is, n ferroelectric capacitors in the same 1TnC structure are connected to the same electrode A2.
  • n ferroelectric capacitors in the same 1TnC structure belong to different layers, that is, n ferroelectric capacitors in the same 1TnC structure are connected to different electrodes B1, and different electrodes B1 are connected to different plate lines (PL).
  • n ferroelectric capacitors in the same 1TnC structure are connected to different plate lines through electrode B1.
  • different ferroelectric capacitors among n ferroelectric capacitors in the same 1TnC structure are connected to different plate lines.
  • n ferroelectric capacitors can be selected from the ferroelectric memory array through transistors, and a certain ferroelectric capacitor can be selected from the n ferroelectric capacitors through board lines, and then the selected ferroelectric capacitor can be operated.
  • the gate of the transistor is connected to the word line (WL), and the electrode A1 of the transistor is connected to the bit line (BL).
  • the gate electrodes of the transistors in the same row are connected to the same word line, and the electrodes A1 of the transistors in the same column are connected to the same bit line.
  • word lines and bit lines are perpendicular to each other.
  • the so-called rows and the so-called columns in the ferroelectric memory array shown in Figure 1 are parallel to the so-called layers in the array.
  • an operation mode similar to that of DRAM is used to operate the 1TnC structure. details as follows.
  • Figure 2A shows a typical read and write circuit of DRAM
  • Figure 2B shows the read and write circuit used to operate the 1TnC structure in this solution.
  • WLn+1 and WLn respectively represent different word lines.
  • BLN is the reverse bit line, which can also be called the reference bit line.
  • BLN and BL appear in pairs, that is, one BL corresponds to one BLN.
  • SAN refers to the sense amplifier pull-down signal (sense amplifier pull-down) wiring in the sense amplifier
  • SAP refers to the sense amplifier pull-up signal (sense amplifier pull-up) wiring in the sense amplifier.
  • SAN can also be called low-voltage side power wiring, and SAN can also be called high-voltage side power wiring.
  • EQ refers to the gate line of the equalizer, which is used to apply voltage to the gate of the equalizer so that the equalizer is in a conductive state.
  • CSL refers to the column select line, and WE (write enable) is used to generate the write enable signal.
  • the function and operation mode of the reading and writing circuit shown in FIG. 2A can be referred to the introduction of the existing technology, and will not be described again here.
  • the function and operation mode of the read-write circuit shown in FIG. 2B are similar to those of the read-write circuit shown in FIG. 2A, and will not be described again here.
  • the voltage on the selected electrode B2 is the voltage V0 or the voltage Vw.
  • the voltage Vw can be called the write voltage.
  • Voltage V0 can be called zero voltage.
  • Zero voltage voltage V0 may be 0V in some embodiments.
  • the read and write stage refers to the stage in which the information on the BL is processed during the operation of the storage unit. Specifically, if the operation on the memory cell is a read operation, then the read and write stage specifically refers to the stage in which the voltage on BL (representing the bit "1" or "0") is transferred to the processor.
  • the read and write stage specifically refers to adjusting the voltage on BL to a voltage corresponding to the information to be written (bit "1" or "0")).
  • "operation” can be a general term for a read operation, a write operation, etc. of a storage unit.
  • the storage unit refers to the smallest unit in the memory used to store or record information, and one storage unit is used to store or record one bit value.
  • the operation performed on the 1TnC structure is similar to the operation performed on the memory cell in DRAM shown in Figure 2A.
  • the voltage on the selected electrode B2 is the voltage V0 or is the voltage Vw.
  • the voltage on the electrode B1 of the unselected ferroelectric capacitor among the n ferroelectric capacitors is the half-selected voltage, that is, 1/2Vw. In this way, there is a voltage difference of 1/2Vw across the unselected ferroelectric capacitors among the n ferroelectric capacitors.
  • 1/2Vw is smaller than the coercive field voltage Vc of the ferroelectric capacitor and will not cause the polarization state of the ferroelectric capacitor to be reversed.
  • the read and write phases last longer (usually 72 ⁇ s). That is, there is a voltage difference of 1/2Vw across the unselected ferroelectric capacitor for a long time.
  • the window size reduces the reliability of ferroelectric memory. Although the reliability of the ferroelectric memory can be maintained through periodic refresh operations, this will lead to a significant increase in the power consumption of the ferroelectric memory.
  • the voltage on the electrode B1 of the selected ferroelectric capacitor is respectively the voltage Vw and voltage V0. Because in the ferroelectric memory array shown in Figure 1, ferroelectric capacitors on the same layer share electrode B1. That is, during the destruction stage and recovery stage of the selected ferroelectric capacitor, the voltages on the electrodes B1 of other ferroelectric capacitors in the same layer as the selected ferroelectric capacitor are also the voltage Vw and the voltage V0 respectively.
  • the electrodes A1 of the transistors in the same column are connected to the same BL, that is, one BL can be connected to the electrodes A1 of multiple transistors.
  • the voltage on the BL corresponding to the selected ferroelectric capacitor is the voltage V0 or the voltage Vw, so that the unstroed connected to the BL
  • the voltage on the unselected electrode B2 is 1/2Vw
  • the voltage on the electrode A2 connected to the unselected electrode B2 is also 1/2Vw).
  • the embodiment of the present application provides a memory cell array operation scheme that can operate ferroelectric capacitors in a 1TnC structure, such as ferroelectric capacitor C1.
  • ferroelectric capacitor C1 during the operation process of the ferroelectric capacitor C1, during the reading and writing stage, the voltage on the electrode B2 of the ferroelectric capacitor C1 can be smaller than the voltage Vw and larger than the voltage V0, so that other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1
  • the voltage difference between the electrode B2 and the electrode B1 of the capacitor is less than the half-selection voltage, which reduces the impact on the residual polarization intensity of other ferroelectric capacitors, thereby reducing the impact on the reliability of the ferroelectric memory.
  • the voltage on the electrode B2 of the ferroelectric capacitor C1 is less than the voltage Vw and greater than the voltage V0, which reduces the leakage current of the transistor of the ferroelectric capacitor that shares BL with the ferroelectric capacitor C1, thereby reducing the leakage current of the transistor that shares BL with the ferroelectric capacitor C1 and
  • the voltage difference between other ferroelectric capacitors sharing PL reduces the possibility of polarization state reversal of iron atoms in the other ferroelectric capacitors, improving the reliability of the ferroelectric memory.
  • the voltage Vw may be called the write voltage Vw.
  • Voltage V0 can be called zero voltage V0.
  • the writing voltage Vw is greater than the zero voltage V0, and the voltage difference between the writing voltage Vw and the zero voltage V0 is greater than the coercive field voltage Vc of the ferroelectric capacitor.
  • zero voltage V0 may be 0V.
  • the zero voltage V0 may be greater than 0V, for example, it may be 0.05V, 0.1V, etc.
  • the embodiment of the present application provides a read and write circuit that can implement this operation scheme, including a sense amplifier 401, a voltage output circuit 402, an equalizer 403, etc.
  • the sense amplifier 401 can be coupled to BL405 and BLN406, and sense the voltage difference between BL405 and BLN406, and adjust the voltage on BL405 and BLN406 according to the voltage difference, so that the voltage of the low voltage is lower and the voltage of the high voltage is lower. higher, thereby amplifying the voltage difference between the two.
  • BL405 is the bit line
  • BLN406 is the inverse bit line.
  • the inverted bit line may also be called the reference bit line.
  • Bit lines and inverted bit lines appear in pairs, and the information stored in the corresponding ferroelectric memory cell can be read by comparing the voltages on the bit lines and inverted bit lines. Specifically, the same voltage can be applied to BL405 (i.e., bit line) and BLN406 (reverse bit line) first. Then, in the subsequent destruction stage, if the polarization state of the ferroelectric capacitor is reversed, it will cause the An increase in voltage, if the polarization state of the ferroelectric capacitor is not reversed, will cause the voltage across the BL405 to decrease. The voltage of BLN406 remains unchanged.
  • the voltage V1 and the voltage V2 are output from the voltage output circuit 402 to the sense amplifier 401, so that the sense amplifier 401 adjusts the voltages on BL405 and BLN406 according to the voltage V1 and the voltage V2.
  • voltage V1 takes a value between voltage Vw and voltage Vprot1
  • voltage V2 takes a value between voltage V0 and voltage Vprot0.
  • voltage V1 is voltage Vw
  • voltage V2 is voltage V0.
  • voltage V2 is voltage Vprot0.
  • the voltage Vprot1 and the voltage Vprot0 will be introduced below and will not be described in detail here.
  • the voltage output circuit 402 includes a voltage switching circuit 4021 and a voltage switching circuit 4022 .
  • the voltage switching circuit 4021 is used to output the voltage V0 or the voltage Vprot0 to the sense amplifier 401
  • the voltage switching circuit 4022 is used to output the voltage Vw or the voltage Vprot1 to the sense amplifier 401.
  • the voltage switching circuit 4021 can be connected to the sense amplifier 401 through a conductor 406
  • the voltage switching circuit 4022 can be connected to the sense amplifier 401 through a conductor 407 . That is, sense amplifier 401 may be connected to voltage output circuit 402 via conductor 406 and conductor 407.
  • conductor 406 may be specifically wired for a pull-down signal (sense amplifier pull-down), and conductor 407 may be wired for a pull-up signal (sense amplifier pull-up). That is, the sense amplifier 401 can be connected to the voltage output circuit 402 through the pull-down signal wiring and the pull-up signal wiring. As described above, the voltage output circuit 402 inputs two voltages with different magnitudes, namely the voltage V1 and the voltage V2, to the sense amplifier 401 .
  • the voltage output circuit 402 outputs the lower voltage of the two voltages (voltage V2) to the sense amplifier 401 through the pull-down signal wiring, and outputs the higher voltage of the two voltages (voltage V1) to the sense amplifier 401 through the pull-up signal wiring.
  • the pull-down signal wiring is used to receive the lower voltage of the two voltages output by the voltage output circuit 402 and transmit it to the sense amplifier 401 .
  • the pull-up signal wiring is used to receive the higher voltage of the two voltages output by the voltage output circuit 402 and transmit it to the sense amplifier 401 .
  • the voltage switching circuit 4021 may include a transistor RB0 and a transistor RW0.
  • the source (or drain) of the transistor RB0 is connected to the driving circuit whose voltage is voltage V0, and the drain (or source) is connected to the conductor 406.
  • the source (or drain) of the transistor RW0 is connected to the driving circuit whose voltage is the voltage Vprot0, and the drain (or source) is connected to the conductor 406 .
  • the transistor RB0 When the transistor RB0 is turned on, the voltage V0 is transmitted to the conductor 406 through the transistor RB0, and then transmitted to the sense amplifier 401 through the conductor 406, thereby outputting the voltage V0 to the sense amplifier 401.
  • the transistor RW0 is turned on, the voltage Vprot0 is transmitted to the conductor 406 through the transistor RW0, and then transmitted to the sense amplifier 401 through the conductor 406, thereby outputting the voltage Vprot0 to the sense amplifier 401.
  • the voltage switching circuit 4022 may include a transistor RB1 and a transistor RW1.
  • the source (or drain) of the transistor RB1 is connected to the driving circuit whose voltage is the voltage Vw, and the drain (or source) is connected to the conductor 407 .
  • the source (or drain) of the transistor RW1 is connected to the drive circuit whose voltage is the voltage Vprot1, and the drain (or source) is connected to the conductor 407.
  • the transistor RB1 is turned on, the voltage Vw is transmitted to the conductor 407 through the transistor RB1, and then transmitted to the sense amplifier 401 through the conductor 407, thereby outputting the voltage Vw to the sense amplifier 401.
  • the transistor RW1 is turned on, the voltage Vprot1 is transmitted to the conductor 407 through the transistor RW1, and then transmitted to the sense amplifier 401 through the conductor 407, thereby outputting the voltage Vprot1 to the sense amplifier 401.
  • the sense amplifier 401 may include an N-type transistor 4011 , an N-type transistor 4012 , a P-type transistor 4013 , and a P-type transistor 4014 .
  • N-type transistor refers to a transistor whose channel layer is an N-type semiconductor
  • P-type transistor refers to a transistor whose channel layer is a P-type semiconductor.
  • N-type semiconductor refers to a semiconductor doped with N-type impurities (also called donor impurities, used to provide electrons).
  • P-type semiconductor refers to a semiconductor doped with P-type impurities (also called acceptor impurities, used to provide holes).
  • the voltage on the gate of the N-type transistor is higher, the N-type transistor is turned on. When the voltage on the gate of the P-type transistor is low, the P-type transistor turns on.
  • the voltage switching circuit 4021 connects the electrode A1 of the N-type transistor 4011 and the electrode A1 of the N-type transistor 4012 through the conductor 406, and the voltage switching circuit 4022 connects the electrode A1 of the P-type transistor 4013 and the P-type transistor 4014 through the conductor 407.
  • the electrode A1, BL404 is connected to the electrode A2 of the N-type transistor 4011 and the electrode A2 of the P-type transistor 4013
  • BLN405 is connected to the electrode A2 of the N-type transistor 4012 and the electrode A2 of the P-type transistor 4014
  • BL404 is also connected to the gate of the N-type transistor 4012.
  • BLN405 also connects the gate of N-type transistor 4011 and the gate of P-type transistor 4013.
  • the electrode A1 and the electrode A2 of the transistor can refer to the above introduction to the transistor shown in Figure 1, and will not be described again here.
  • the voltages of BLN405 and BL404 are relatively low (for example, the voltage on BLN405 is voltage Vpre1, and the voltage on BL404 is voltage Vrd1 or voltage Vrd0, which will be introduced below) .
  • the N-type transistor does not conduct, and the P-type transistor conducts, and the P-type transistor with the lower gate voltage has stronger conduction ability.
  • the voltage of BLN405 can be set lower than the voltage on BL404, so that the conduction capability of P-type transistor 4013 is stronger than that of P-type transistor 4014. More voltage from the voltage switching circuit 4022 acts on BL404, increasing the voltage of BL404. The increase in the voltage of BL404 also causes the voltage on the gate of N-type transistor 4012 to increase. In this way, N-type transistor 4012 is turned on, and the voltage from the voltage switching circuit 4021 acts on BLN405, reducing the voltage of BLN405. In this way, the voltage on BL404 increases and the voltage on BLN405 decreases, thereby amplifying the voltage difference.
  • the voltage of BLN405 can be set to be higher than the voltage of BL404. In this way, the conduction capability of P-type transistor 4014 is stronger than that of P-type transistor 4013. More voltage from the voltage switching circuit 4022 acts on BLN405, increasing the voltage of BLN405. The voltage increase of BLN405 also causes the voltage on the gate of N-type transistor 4011 to increase. In this way, N-type transistor 4011 is turned on, and the voltage from the voltage switching circuit 4021 acts on BL404, reducing the voltage of BL404. In this way, the voltage on BL404 increases and the voltage on BL404 decreases, thereby amplifying the voltage difference.
  • the voltage V1 and the voltage V2 can be applied to BL404 and BLN405 respectively.
  • the equalizer 403 can output voltage Vpre1 to BL404 and BLN405, can also output voltage Vpre2 to BL404 and BLN405, or can output voltage 1/2Vw to BL404 and BLN405.
  • the equalizer 403 that outputs voltage Vpre1, voltage Vpre2, and voltage 1/2Vw to BL404 and BLN 405 may be the same equalizer.
  • the equalizer can output different voltages to BL404 and BLN405 at different times to realize time division multiplexing of the equalizer. Voltage Vpre1 and voltage Vpre2 will be introduced below and will not be described in detail here.
  • equalizer 403 may include different equalizers. Different equalizers output different voltages to BL404 and BLN405 respectively.
  • FIG. 5 shows a flow chart of a memory cell array operation scheme provided by an embodiment of the present application.
  • a complete operation process of this operation plan includes a read precharge stage, a destruction stage, a read stage, an amplification stage, a read and write stage, a recovery stage, a precharge standby stage, and a standby stage.
  • the ferroelectric capacitor C1 may be a ferroelectric capacitor in the ferroelectric memory array shown in FIG. 1 .
  • the ferroelectric capacitor C1 is the selected ferroelectric capacitor, and the other ferroelectric capacitors are unselected ferroelectric capacitors.
  • the ferroelectric capacitor C1 may be a ferroelectric capacitor in other structures, such as a ferroelectric capacitor in a 1T1C structure.
  • a ferroelectric capacitor may also be called a ferroelectric memory unit, which is a memory unit in a ferroelectric memory or a ferroelectric memory array. That is, a ferroelectric capacitor in the ferroelectric memory or ferroelectric memory array is a memory unit in the ferroelectric memory or ferroelectric memory array.
  • the ferroelectric capacitor C1 Before the ferroelectric capacitor C1 is operated, the ferroelectric capacitor C1 is in a standby stage.
  • the standby stage is a stage of waiting for operation, that is, during the standby stage of ferroelectric capacitor C1, ferroelectric capacitor C1 is in a state of waiting for operation.
  • the transistor of the ferroelectric capacitor C1 When the ferroelectric capacitor C1 is in the standby stage, the transistor of the ferroelectric capacitor C1 is in the off state (that is, the voltage on WL is the voltage V0), the voltage on PL (or electrode B1) is 1/2Vw, and the voltage on the electrode B2 The voltage is also 1/2Vw to maintain the stability of the voltage across the ferroelectric capacitor C1.
  • 1/2Vw refers to one-half of the voltage Vw, which can be called the half-selected voltage. In one example, voltage Vw is 2V.
  • the operation command for the ferroelectric capacitor C1 can trigger the ferroelectric capacitor C1 to enter the read precharge stage from the standby stage.
  • the initial voltage Vpre1 is provided to the electrode B2 of the ferroelectric capacitor C1.
  • the initial voltage Vpre1 is preset, and the initial voltage Vpre1 can be set according to the following requirements.
  • the initial voltage Vpre1 is less than the voltage Vw, and the voltage difference between the initial voltage Vpre1 and the voltage Vw is greater than the coercive field voltage Vc of the ferroelectric capacitor, so that when the polarization state of the iron atoms is inconsistent with the direction of the voltage difference, the Iron atoms cross higher energy levels and reach another polarization state.
  • the initial voltage Vpre1 combined with the voltage Vw can destroy the ferroelectric capacitor C1 or reverse the polarization state of the iron atoms in the ferroelectric capacitor C1.
  • the initial voltage Vpre1 may be equal to the voltage V0.
  • the voltage on BL of ferroelectric capacitor C1 can be adjusted to the initial voltage Vpre1.
  • the voltage on BL of the ferroelectric capacitor C1 can be adjusted to the initial voltage Vpre1 through the equalizer 403 in the read-write circuit shown in FIG. 5 .
  • the voltage on WL of the ferroelectric capacitor C1 can be adjusted to the voltage Vdd, so that the transistor of the ferroelectric capacitor C1 enters the conducting state, whereby the initial voltage Vpre1 on BL can be transferred to the electrode B2 of the ferroelectric capacitor C1 , thereby providing the initial voltage Vpre1 to the electrode B2 of the ferroelectric capacitor C1.
  • the voltage Vdd can be called the highest voltage or the power supply voltage.
  • the voltage Vdd has a higher value, in one example, the voltage Vdd is 2.5V.
  • the voltage on PL of ferroelectric capacitor C1 is still 1/2Vw.
  • the destruction phase can be entered.
  • the transistor of the ferroelectric capacitor C1 is turned off (for example, the voltage on WL of the ferroelectric capacitor C1 is adjusted to the voltage V0), so that the electrode B2 of the ferroelectric capacitor C1 is floating.
  • the voltage of electrode B2 after entering the floating state can be set to voltage Vfg0. It can be understood that the voltage of electrode B2 after entering the suspended state and the voltage before entering the suspended state remain almost unchanged, that is, the voltage Vfg0 is equal to or approximately equal to the initial voltage Vpre1. Among them, the voltage Vfg0 combined with the voltage Vw can also destroy the ferroelectric capacitor C1 or reverse the polarization state of the iron atoms in the ferroelectric capacitor C1.
  • the voltage on PL of ferroelectric capacitor C1 is adjusted to Vw, that is, the voltage on electrode B1 of ferroelectric capacitor C1 is Vw.
  • the voltage on the electrode B2 of the ferroelectric capacitor C1 is the voltage Vfg0.
  • the direction of the voltage difference between the electrode B1 and the electrode B2 of the ferroelectric capacitor C1 is the positive polarization direction.
  • ferroelectric capacitor C1 If the ferroelectric capacitor C1 is in a negatively polarized state, then under the action of the voltage difference between the electrode B1 and the electrode B2 of the ferroelectric capacitor C1, the ferroelectric capacitor C1 changes from a negatively polarized state to a positively polarized state. During the transition from the negative polarization state to the positive polarization state, the positive charge in the ferroelectric capacitor C1 will enter the electrode B2, causing the voltage of the electrode B2 to rise from the voltage Vfg0 to the voltage Vfg1.
  • the ferroelectric capacitor C1 If the ferroelectric capacitor C1 is in a positive polarization state, the voltage difference between the electrode B1 and the electrode B2 of the ferroelectric capacitor C1 will not change the polarization state of the ferroelectric capacitor C1, that is, the ferroelectric capacitor C1 still maintains the voltage Vfg0.
  • the voltage on PL of the ferroelectric capacitor C1 can be adjusted to the voltage Vw, so that the ferroelectric capacitor C1 converts from a negative polarization state to a positive polarization state, or the process of the ferroelectric capacitor C1 maintaining a negative polarization state is understood as the ferroelectric capacitor C1. Destruction of capacitor C1.
  • the voltage on the BL of the ferroelectric capacitor C1 and the voltage on the BLN of the ferroelectric capacitor C1 can be adjusted to the voltage Vpre2.
  • the voltages on BL and BLN of the ferroelectric capacitor C1 can be adjusted to the voltage Vpre2 through the equalizer 403 in the read-write circuit shown in FIG. 5 .
  • the voltage Vpre2 is preset, and the setting requirements for the voltage Vpre2 will be specifically introduced below and will not be described again here.
  • the destruction phase after turning off the transistor of the ferroelectric capacitor C1, that is, in this embodiment, adjusting the voltage on BL and BLN to the voltage Vpre2 and destroying the ferroelectric capacitor C1 simultaneously to increase the operating speed.
  • the read phase can be entered.
  • the voltage on WL of the ferroelectric capacitor C1 is raised to the voltage Vdd, causing the transistor of the ferroelectric capacitor C1 to enter a conductive state.
  • the charges of the electrode B2 of the ferroelectric capacitor C1 and the BL of the ferroelectric capacitor C1 are balanced.
  • the voltage on electrode B2 of ferroelectric capacitor C1 is voltage Vfg (that is, voltage Vfg0 or voltage Vfg1)
  • the voltage on BL of ferroelectric capacitor C1 is voltage Vpre2.
  • the voltage on electrodes B2 and BL of ferroelectric capacitor C1 becomes voltage Vrd.
  • the voltage on BLN of ferroelectric capacitor C1 is still Vpre2.
  • the voltage Vrd when the voltage Vfg is specifically the voltage Vfg0, the voltage Vrd is specifically the voltage Vrd0.
  • voltage Vfg is specifically voltage Vfg1, voltage Vrd is specifically voltage Vrd1.
  • voltage Vfg1 is greater than voltage Vpre2, and voltage Vrd0 is less than voltage Vpre2.
  • voltage Vpre2 is a set value. In order to make voltage Vfg1 greater than voltage Vpre2 and voltage Vrd0 less than voltage Vpre2, voltage Vpre2, voltage Vfg0, voltage Vrd0, voltage Vfg1, and voltage Vrd1 need to satisfy the following relationships.
  • Cfg is the total capacitance of electrode B2 of ferroelectric capacitor C1
  • Cbl is the total capacitance of BL of ferroelectric capacitor C1.
  • equation (1) equation (2) and equation (3), determine the value of voltage Vpre2.
  • the voltage on BL of ferroelectric capacitor C1 will be different depending on the polarization state of ferroelectric capacitor C1. That is, when the polarization state of ferroelectric capacitor C1 is the positive polarization state, the BL of ferroelectric capacitor C1 The voltage on BL is voltage Vrd0; when the polarization state of ferroelectric capacitor C1 is a negative polarization state, the voltage on BL of ferroelectric capacitor C1 is voltage Vrd1. In this way, the bit value recorded or stored in the ferroelectric capacitor C1 can be read.
  • the ferroelectric capacitor C1 when the polarization state of the ferroelectric capacitor C1 is a positive polarization state, the ferroelectric capacitor C1 records the bit value D1, and when the polarization state of the ferroelectric capacitor C1 is a negative polarization state, the ferroelectric capacitor C1 records the bit value D2. That is, the voltage Vrd0 represents the bit value D1, and the voltage Vrd1 represents the bit value D2. Among them, the bit value D1 is "0" and the bit value D2 is "1”; or, the bit value D1 is "1” and the bit value D2 is "0".
  • the amplification phase can be entered, that is, the voltage on the BL of the ferroelectric capacitor C1 is increased or decreased, so that after the voltage on the BL of the ferroelectric capacitor C1 is passed to the processor, the processor can identify The information represented by this voltage. Specifically, during the amplification stage, if the voltage on BL of ferroelectric capacitor C1 is voltage Vrd0, the voltage on BL of ferroelectric capacitor C1 is adjusted to voltage Vprot0. If the voltage on BL of ferroelectric capacitor C1 is voltage Vrd1, then the voltage on BL of ferroelectric capacitor C1 is adjusted to voltage Vprot1.
  • the voltage Vrd0 represents the bit value D1
  • the voltage Vrd1 represents the bit value D2. Therefore, the voltage Vprot0 represents the bit value D1, and the voltage Vprot1 represents the bit value D2.
  • the voltage Vprot0 and the voltage Vprot1 are both preset values. Both voltage Vprot0 and voltage Vprot1 are less than voltage Vw and both are greater than voltage V0, and the voltage difference between voltage Vprot0 and voltage Vprot1 is greater than or equal to the preset threshold E1, so that the voltage Vprot0 on BL is transferred to the processor.
  • the value or the voltage value of the voltage Vprot1 on the BL when it is passed to the processor can be recognized by the processor, thereby enabling the processor to recognize the information represented by the voltage from the BL.
  • the voltage difference between the voltage Vrd1 and the voltage Vrd0 is less than the threshold E1. Therefore, the process of adjusting the voltage on the BL of the ferroelectric capacitor C1 from the voltage Vrd0 to the voltage Vprot0, and the process of adjusting the voltage on the BL of the ferroelectric capacitor C1
  • the process of adjusting the voltage from voltage Vrd1 to voltage Vprot1 can be called amplification.
  • voltage Vprot0 is smaller than voltage Vprot1. That is, voltage Vw>voltage Vprot1>voltage Vprot0>voltage V0.
  • the read and write circuit shown in Figure 5 can be used to increase or decrease the voltage on BL of ferroelectric capacitor C1. Specifically, the transistor RW0 in the voltage switching circuit 4021 of the SAN is turned on, and the voltage Vprot0 is output to the sense amplifier 401 through the SAN. At the same time, the transistor RW1 in the voltage switching circuit 4022 of the SAP is strobed, and the voltage Vprot1 is output to the sense amplifier 401 through the SAP.
  • the sense amplifier 401 switches the voltage on BL of ferroelectric capacitor C1 The voltage is adjusted from voltage Vrd0 to voltage Vprot0. At the same time, the sense amplifier 401 adjusts the voltage on BLN of the ferroelectric capacitor C1 from the voltage Vpre2 to the voltage Vprot1.
  • the sense amplifier 401 switches the voltage on BL of ferroelectric capacitor C1 The voltage is adjusted from voltage Vrd1 to voltage Vprot1. At the same time, the sense amplifier 401 adjusts the voltage on BLN of the ferroelectric capacitor C1 from the voltage Vpre2 to the voltage Vprot0.
  • the read and write stage refers to the processing stage of information on BL during the operation of ferroelectric capacitor C1.
  • the read and write stage specifically refers to the stage of transferring the voltage on BL (representing the bit value "1” or "0") to the processor.
  • the read and write phase specifically refers to adjusting the voltage on BL to the voltage corresponding to the information to be written (bit value "1" or "0")).
  • the read and write phase specifically refers to changing the voltage on BL of the ferroelectric capacitor C1 (Vprot0 or Vprot1 ) is passed to the processor stage. If the operation command for the ferroelectric capacitor C1 is specifically a write command, then the read and write phase specifically refers to adjusting the voltage on BL to the voltage corresponding to the information to be written (bit value "1" or "0")). Among them, the voltage Vprot0 represents the bit value D1, and the voltage Vprot1 represents the bit value D2.
  • the operation command for the ferroelectric capacitor C1 is specifically a write command
  • the information to be written is the bit value D1
  • the voltage on the BL of the ferroelectric capacitor C1 is the voltage Vprot0
  • the voltage on the BL of the ferroelectric capacitor C1 is Vprot0.
  • the voltage continues to maintain voltage Vprot0.
  • the voltage on BL of ferroelectric capacitor C1 is voltage Vprot1 (that is, the information recorded in ferroelectric capacitor C1 is bit value D2)
  • the voltage on BL of ferroelectric capacitor C1 is The voltage Vprot1 is adjusted to the voltage Vprot0, so that in the subsequent write-back stage, the information recorded on the ferroelectric capacitor is adjusted from the bit value D2 to the bit value D1, thereby completing the writing of the information to be written.
  • the voltage on BL of ferroelectric capacitor C1 is voltage Vprot0 or voltage Vprot1, and at this time, the transistor of ferroelectric capacitor C1 is in the gated state. Therefore, the voltage on electrode B2 of ferroelectric capacitor C1 The voltage is voltage Vprot0 or voltage Vprot1. Among them, voltage Vprot0 and voltage Vprot1 are both smaller than voltage Vw, and both are larger than voltage V0. From the above, during the reading and writing stage of the ferroelectric capacitor C1, the voltage on the electrode B1 of other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1 is 1/2Vw.
  • the voltage difference between the two ends of other ferroelectric capacitors that share electrode B2 with ferroelectric capacitor C1 is less than 1/2Vw, thereby reducing the number of iron atoms with polarization states reversed in the other ferroelectric capacitors, making the ferroelectric capacitor The residual polarization intensity can be maintained and the reliability of the ferroelectric memory is improved.
  • Figure 6 shows the voltage on the electrode B1 and the electrode B2 of the ferroelectric capacitor C2 during the reading and writing stage of the ferroelectric capacitor C1. It can be seen that the voltage difference between the electrode B1 and the electrode B2 of the ferroelectric capacitor C2 is less than 1/ 2Vw.
  • the ferroelectric capacitor C2 may be a ferroelectric capacitor other than the ferroelectric capacitor C1 in the ferroelectric memory array shown in Figure 1, and the ferroelectric capacitor C2 and the ferroelectric capacitor C1 share the electrode B2.
  • the voltage on the BL of the ferroelectric capacitor C1 is the voltage Vprot0 or the voltage Vprot1, so that the voltage difference between the electrode A2 and the electrode A1 of the unstrobed transistor connected to the BL is less than 1/2Vw (not 1/2Vw).
  • the voltage on the selected electrode B2 is 1/2Vw, and the voltage on the electrode A2 connected to the unselected electrode B2 is also 1/2Vw), thereby reducing the leakage between the electrode A1 and the electrode A2 of the unselected transistor.
  • the voltage on BL of ferroelectric capacitor C1 is voltage Vprot0 or voltage Vprot1, which is lower than voltage Vw, which reduces the operating voltage on the data path (datapath) that transmits the voltage on BL to the processor. further saves power consumption.
  • the recovery stage can also be called the write-back stage.
  • the ferroelectric capacitor C1 that was destroyed in the destruction stage (that is, the polarization state was reversed) can be restored or written back.
  • the transistor of the ferroelectric capacitor C1 continues to maintain the gated state, that is, the voltage on WL of the ferroelectric capacitor C1 continues to maintain Vdd.
  • the voltage of electrode B1 or PL of ferroelectric capacitor C1 is adjusted to voltage V0. Because when the voltage difference across the ferroelectric capacitor C1 is Vw, the polarization state of the ferroelectric capacitor can be changed.
  • the voltage on the electrode B2 of the ferroelectric capacitor C1 is the voltage Vprot0 or the voltage Vprot1, both of which are less than Vw. Therefore, during the recovery stage, the voltage on the electrode B2 of the ferroelectric capacitor C1 needs to be adjusted from the voltage Vprot1 to the voltage Vw, or from the voltage Vprot0 to the voltage V0.
  • the voltage on the electrode B2 of the ferroelectric capacitor C1 is the voltage Vprot0, it means that during the destruction stage, the polarization state of the ferroelectric capacitor C1 has not been reversed and still maintains the positive polarization state, or it means that it is waiting to be written.
  • the information corresponds to the positive polarization state (the information to be written corresponds to the voltage Vprot0, which is the bit value D1).
  • the voltage on the electrode B2 of the ferroelectric capacitor C1 is adjusted from the voltage Vprot0 to the voltage V0.
  • the voltage at both ends of the ferroelectric capacitor C1 is voltage V0, that is, the voltage difference is 0.
  • the ferroelectric capacitor C1 can still maintain the positive polarization state, thereby completing the write-back or writing of information.
  • the voltage on the electrode B2 of the ferroelectric capacitor C1 is the voltage Vprot1
  • the polarization state of the ferroelectric capacitor C1 has been reversed, that is, it has been reversed from the negative polarization state to the positive polarization state, or it means that the polarization state is to be reversed.
  • the written information corresponds to the negative polarization state (the information to be written corresponds to the voltage Vprot1, which is the bit value D2).
  • the voltage on the electrode B2 of the ferroelectric capacitor C1 is adjusted from the voltage Vprot1 to the voltage Vw.
  • the voltage difference between the electrode B1 and the electrode B2 of the ferroelectric capacitor C1 is -Vw, which can reverse the polarization state of the ferroelectric capacitor C1 from the positive polarization state to the negative polarization state, completing the information write-back or write-back. enter.
  • the read and write circuit shown in Figure 5 can be used to perform write back or writing. Specifically, the transistor RB0 in the voltage switching circuit 4021 of the SAN is turned on, and the voltage V0 is output to the sense amplifier 401 through the SAN. At the same time, the transistor RB1 in the voltage switching circuit 4022 of the SAP is turned on, and the voltage Vw is output to the sense amplifier 401 through the SAP.
  • the sense amplifier 402 adjusts the voltage on BLN of the ferroelectric capacitor C1 to the voltage Vprot0 and at the same time adjusts the voltage on the BLN of the ferroelectric capacitor C1 to the voltage Vprot1.
  • the sense amplifier 402 adjusts the voltage on BLN of the ferroelectric capacitor C1 to the voltage Vprot1 and simultaneously adjusts the voltage on the BLN of the ferroelectric capacitor C1 to the voltage Vprot0.
  • the sense amplifier 401 when the voltage on BL of ferroelectric capacitor C1 is voltage Vprot0 and the voltage on BLN is voltage Vprot1, that is, when the voltage on BL of ferroelectric capacitor C1 is less than the voltage on BLN, the sense amplifier 401 will The voltage on BL of capacitor C1 is adjusted from voltage Vprot0 to voltage V0. At the same time, the sense amplifier 401 adjusts the voltage on BLN of the ferroelectric capacitor C1 from the voltage Vprot1 to the voltage Vw.
  • the sense amplifier 401 When the voltage on BL of ferroelectric capacitor C1 is voltage Vprot1 and the voltage on BLN is voltage Vprot0, that is, when the voltage on BL of ferroelectric capacitor C1 is greater than the voltage on BLN, the sense amplifier 401 will The voltage on is adjusted from voltage Vprot1 to voltage Vw. At the same time, the sense amplifier 401 adjusts the voltage on BLN of the ferroelectric capacitor C1 from the voltage Vprot0 to the voltage V0.
  • the transistor of the ferroelectric capacitor C1 continues to maintain the strobe state, that is, the voltage on WL of the ferroelectric capacitor C1 continues to maintain Vdd. Adjust the voltage on BL and BLN of ferroelectric capacitor C1 to 1/2Vw. Through the BL of the ferroelectric capacitor C1, the voltage on the electrode B2 of the ferroelectric capacitor C1 is also adjusted to 1/2Vw. Adjust the voltage of electrode B1 or PL of ferroelectric capacitor C1 to voltage 1/2Vw. Therefore, the voltage difference between the two ends of the ferroelectric capacitor C1 is 0, so as to keep the polarization state of the ferroelectric capacitor C1 unchanged.
  • the voltage on BL and the voltage on BLN of the ferroelectric capacitor C1 can be adjusted to the voltage 1/2Vw through the equalizer 403 in the read-write circuit shown in FIG. 5 .
  • the standby phase begins. As shown in Figure 5, in the standby phase, the voltage on WL of ferroelectric capacitor C1 is V0, and the transistor is in the off state. PL, BL and BLN of the ferroelectric capacitor C1 maintain the voltage Vw/2, and the voltage difference between the two ends of the ferroelectric capacitor C1 is 0 to keep the polarization state of the ferroelectric capacitor C1 unchanged.
  • the voltage difference between the two ends of other ferroelectric capacitors that share electrode B2 with the currently selected ferroelectric capacitor is reduced to less than 1/2Vw, thereby reducing the number of iron atoms with polarization states reversed in the other ferroelectric capacitors, This allows the ferroelectric capacitor to maintain the residual polarization intensity and improves the reliability of the ferroelectric memory. At the same time, it can reduce the frequency of memory refresh operations and reduce the power consumption of ferroelectric memory;
  • the voltage difference between the two ends of the unselected ferroelectric capacitors that share BL and PL with the currently selected ferroelectric capacitor is reduced.
  • the actual voltage difference thereby reduces the risk of polarization state reversal of iron atoms in unselected ferroelectric capacitors and reduces the risk of errors in stored information.
  • the voltage on the BL of the currently selected ferroelectric capacitor is lower, which reduces the operating voltage on the data path that transmits the voltage on the BL to the processor, further saving power consumption.
  • the term "and/or" is only an association relationship describing associated objects, indicating that there can be three relationships.
  • a and/or B can mean: A alone exists, and A alone exists. There is B, and there are three situations A and B at the same time.
  • the term "plurality" means two or more.
  • multiple systems refer to two or more systems
  • multiple terminals refer to two or more terminals.
  • first and second are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • the terms “including,” “includes,” “having,” and variations thereof all mean “including but not limited to,” unless otherwise specifically emphasized.

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Abstract

本申请涉及数据存储技术领域，具体涉及一种读写电路、读写方法以及铁电存储器。该读写电路包括：灵敏放大器，耦合至第一铁电存储单元的第一位线和第一参考位线；连接灵敏放大器的第一电压切换电路，用于向灵敏放大器输出第一电压或者第二电压；连接灵敏放大器的第二电压切换电路，用于向灵敏放大器输出第三电压或者第四电压；其中，第一电压＞第二电压＞第三电压＞第四电压。其中，当第一位线上的电压高于第一参考位线上的电压时，灵敏放大器用于向第一位线输出第一电压或者第二电压，向第一参考位线输出第三电压或者第四电压。该读写电路可以降低铁电存储器的功耗及成本。

Description

读写电路、读写方法以及铁电存储器
本申请要求于2022年3月11日提交中国国家知识产权局、申请号为202210243375.5、申请名称为“读写电路、读写方法以及铁电存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据存储技术领域，具体涉及一种铁电存储阵列的读写电路、读写方法以及铁电存储器。
背景技术
铁电存储器或者说铁电随机存储器(ferroelectric random access memory，FeRAM)包括一个或多个铁电电容(capacitor，C)。铁电电容作为存储单元，可以用于存储信息。其中，铁电电容的两个电极板中间沉积有铁电晶体，可以利用铁电晶体的铁电效应实现数据存储。铁电晶体的晶体中心铁原子有两种稳定状态或者说极化状态。可以设定这两种极化状态分别为负极化状态和正极化状态。铁电效应是指在铁电晶体上施加一定的电场时，晶体中心原子在电场的作用下运动，并达到一种稳定状态(或者说负极化状态)；当电场从晶体移走后，中心原子会保持在原来的位置。这是由于晶体的两个状态之间是一个高能阶，中心原子在没有获得外部能量时不能越过高能阶到达另一稳定位置(或者说正极化状态)。因此，铁电存储器可以在断电的情况下保持数据，具有非易失性，可用作非易失性存储器。
铁电电容对应负极化状态的剩余极化强度(the remnant polarization，Pr)表示了铁电电容中处于负极化状态的铁原子的比例。也就是说，当铁电电容对应负极化状态的Pr较高，可以明确读出该铁电电容存储的对应负极化状态的信息。若铁电电容对应负极化状态的Pr较低时，可能难以读出该铁电电容存储的对应负极化状态的信息。
因此，如何保持铁电电容的剩余极化强度，对铁电存储器的可靠性具有重要影响。
发明内容
本申请实施例提供了一种铁电存储阵列的读写电路、读写方法以及铁电存储器，可以降低铁电存储器的功耗以及成本。
第一方面，提供了一种铁电存储阵列的读写电路，铁电存储阵列包括第一铁电存储单元；读写电路包括：灵敏放大器，耦合至第一铁电存储单元的第一位线和第一参考位线；连接灵敏放大器的第一电压切换电路，用于向灵敏放大器输出第一电压或者第二电压；连接灵敏放大器的第二电压切换电路，用于向灵敏放大器输出第三电压或者第四电压；其中，第一电压＞第二电压＞第三电压＞第四电压。
其中，当第一位线上的电压高于第一参考位线上的电压时，灵敏放大器用于向第一位线输出第一电压或者第二电压，向第一参考位线输出第三电压或者第四电压。当第一位线上的电压低于第一参考位线上的电压时，灵敏放大器用于向第一参考位线输出第一电压或者第二电压，向第一位线输出第三电压或者第四电压。
本申请实施例提供的读写电路，可以在特定的阶段，可以向灵敏放大器输出不同大小的电压。例如在第一铁电存储单元的读写阶段，向灵敏放大器输出的小于第一电压且的第二电压或第三电压，使得灵敏放大器可以向第一位线输出第二电压或第三电压，即灵敏放大器在第一铁电存储单元的读写阶段，向第一位线施加的电压较小，由此，可以采用较小的的电压，将第一位线上的信息传递至处理器，即降低了第一位线和处理器之间的数据路径上的操作电 压，进而降低铁电存储单元的读写功耗。
再例如，在铁电存储单元的恢复阶段或者说回写阶段，可以向灵敏放大器输出电压差比较大的第一电压和第四电压，使得灵敏放大器可以向第一位线输出第一电压或第四电压，从而可以完成铁电存储单元的回写。
也就是说，本申请实施例提供铁电存储阵列的读写电路，可以向灵敏放大器输出不同大小的电压，进而向第一位线输出不同大小的电压，以实现对铁电存储单元的不同操作，并且结构简单，有助于降低铁电存储器的体积和成本。
在一种可能的实施方式中，当第一电压切换电路用于向灵敏放大器输出第一电压时，第二电压切换电路用于向灵敏放大器输出第四电压；当第一电压切换电路用于向灵敏放大器输出第二电压时，第二电压切换电路用于向灵敏放大器输出第三电压。
在该实施方式中，当第一电压切换电路用于向灵敏放大器输出第一电压时，第二电压切换电路用于向灵敏放大器输出第四电压，从而使得灵敏放大器可以向第一位线输出第一电压或第四电压，使得第一铁电存储单元在被破坏后可以完成恢复或者回写。当第一电压切换电路用于向灵敏放大器输出第二电压时，第二电压切换电路用于向灵敏放大器输出第三电压，从而使得灵敏放大器可以向第一位线输出第二电压或第三电压，由此，可以采用较小的小于写电压Vw的电压，将第一位线上的信息传递至处理器，即降低了第一位线和处理器之间的数据路径上的操作电压，进而降低存储单元铁电存储单元的读写功耗。
在一种可能的实施方式中，第一电压为第一铁电存储单元的写电压Vw，第四电压为第一铁电存储单元的零电压V0。
在该实施方式中，第一电压和第四电压分别为第一铁电存储单元的写电压Vw和零电压V0，可使得灵敏放大器向第一位线输出写电压Vw或者零电压V0，从而可以使得第一铁电存储单元在被破坏后可以完成恢复或者回写。
在一种可能的实施方式中，第一电压切换电路包括第一晶体管和第二晶体管；其中，第一晶体管的第一极连接灵敏放大器，第二极连接第一驱动电路；第二晶体管的第一极连接灵敏放大器，第二极连接第二驱动电路；其中，当第一晶体管导通时，第一驱动电路用于通过第一晶体管向灵敏放大器输出第一电压；当第二晶体管导通时，第二驱动电路用于通过第二晶体管向灵敏放大器输出第二电压；第二电压切换电路包括第三晶体管和第四晶体管；其中，第三晶体管的第一极连接灵敏放大器，第二极连接第三驱动电路；第四晶体管的第一极连接灵敏放大器，第二极连接第四驱动电路；其中，当第三晶体管导通时，第三驱动电路用于通过第三晶体管向灵敏放大器输出第三电压；当第四晶体管导通时，第四驱动电路用于通过第四晶体管向灵敏放大器输出第四电压。
该实施方式提供了电压切换电路的一种具体实现形式，该形式结构简单、性能稳定、可靠性高，可进一步降低铁电存储器的成本和可靠性。
在一种可能的实施方式中，第一电压切换电路用于向灵敏放大器的第一线路输出第一电压或者第二电压，第二电压切换电路用于向灵敏放大器的第二线路输出第三电压或第四电压。
在该实施例方式中，第一电压切换电路可以为灵敏放大器的第一线路提供电压，第二切换电路可以为灵敏放大器的第二线路提供电压，从而使得灵敏放大器可以向第一位线和第一参考位线输出相应电压，实现对第一铁电存储单元的读写。
在一种可能的实施方式中，第一线路为上拉信号布线，第二线路为下拉信号布线。
在一种可能的实施方式中，灵敏放大器包括：第五晶体管、第六晶体管、第七晶体管、第八晶体管；其中，第一线路连接第七晶体管的第一极，以及连接第八晶体管的第一极；第 二线路连接第五晶体管的第一极，以及连接第六晶体管的第一极；第一位线连接第七晶体管的第二极，以及连接第六晶体管的栅极；第一参考位线连接第六晶体管的第二极，以及连接第七晶体管的栅极；其中，当第一位线上的电压高于第一参考位线上的电压时，第七晶体管导通，使得第一线路向第一位线输出第一电压或者第二电压；当第一线路向第一位线输出第一电压或第二电压时，第六晶体管导通，使得第二线路向第一参考位线输出第三电压或第四电压。
该实施方式提供了灵敏放大器的一种具体实现形式，该形式结构简单、性能稳定、可靠性高，可进一步降低铁电存储器的成本和可靠性。
在一种可能的实施方式中，第一位线连接第五晶体管的第二极，以及连接第八晶体管的栅极；第一参考位线连接第八晶体管的第二极，以及连接第五晶体管的栅极；当第一位线上的电压低于第一参考位线上的电压时，第八晶体管导通，使得第一线路向第一参考位线输出第一电压或者第二电压；当第一线路向第一参考位线施加第一电压或者第二电压时，第五晶体管导通，使得第二线路向第一位线输出第三电压或者第四电压。
该实施方式提供了灵敏放大器的一种具体实现形式，该形式结构简单、性能稳定、可靠性高，可进一步降低铁电存储器的成本和可靠性。
在一种可能的实施方式中，铁电存储阵列还包括第二铁电存储单元；第二铁电存储单元和第一铁电存储单元连接不同的第一电极，连接同一第二电极；第二电极连接第一位线。
在该实施方式中，铁电存储阵列包括与第一铁电存储单元共用第二电极的第二铁电存储单元，其中第二电极连接第一位线，即第一铁电存储单元和第二铁电存储单元同时连通第一位线。利用该读写电路，在第一铁电存储单元的读写阶段，灵敏放大器可以向第一位线输出第二电压或第三电压，其中，第二电压和第三电压均小于第一电压，且均大于第四电压。由此，对于也在第一铁电存储单元读写阶段和第一位线保持连通的第二铁电存储单元而言，可以降低第二铁电存储单元在第一铁电存储单元读写阶段的两端电压差，从而可以减少第二铁电存储单元中极化状态发生反转的原子的数量，使得第二铁电存储单元可以保持剩余极化强度，提高了铁电存储阵列所在存储器的可靠性。
在一种可能的实施方式中，铁电存储阵列还包括第三铁电存储单元；第三铁电存储单元和第一铁电存储单元共用第一电极，且第三铁电存储单元的第二电极和第一铁电存储单元的第二电极分别通过不同的晶体管连接到第一位线。
在该实施方式中，铁电存储阵列包括与第一铁电存储单元共用第一电极的第三铁电存储单元，且第三铁电存储单元的第二电极和第一铁电存储单元的第二电极分别通过不同的晶体管连接到第一位线。利用该读写电路，在第一铁电存储单元的读写阶段，灵敏放大器可以向第一位线输出第二电压或第三电压，其中，第二电压和第三电压均小于第一电压，且均大于第四电压。从而可以降低第三铁电存储单元的晶体管的源极和漏极之间的电压差，进而可以减少第三铁电存储单元的晶体管的漏电流，减少了第三铁电存储单元的第二电极上的实际电压和理论电压之间的偏移。这可以降低第三铁电存储单元两端之间的电压差，即降低了第三铁电存储单元的极化状态反转的风险，降低了存储信息出错风险，提高了铁电存储阵列所在存储器的可靠性。
在一种可能的实施方式中，读写电路还包括：均衡器，耦合至第一位线和第一参考位线；均衡器用于在不同时刻向第一位线输出不同的电压，以及在不同时刻向第一参考位线输出不同的电压。
在该实施方式中，读写电路包括的均衡器可以在不同时刻向第一位线和第一参考位线输 出不同的电压。例如，可以在第一铁电存储单元的读预充阶段，向第一位线和第一参考位线输出电压Vpre1；在第一铁电存储单元的破坏阶段，向第一位线和第一参考位线输出电压Vpre2；在第一铁电存储单元的待命阶段，向第一位线和第一参考位线输出电压1/2Vw。从而可以结合其他部件完成第一铁电存储单元的完整操作流程。
并且，均衡器可以在不同时刻向第一位线和第一参考位线输出不同的电压，实现了均衡器的时分复用，降低了读写电路的成本。
第二方面，提供了一种铁电存储阵列的读写方法，铁电存储阵列包括第一铁电存储单元，该方法应用于读写电路，读写电路包括灵敏放大器、第一电压切换电路、第二电压切换电路，灵敏放大器耦合至第一铁电存储单元的第一位线和第一参考位线；该方法包括：第一电压切换电路向灵敏放大器输出第一电压或者第二电压，第二电压切换电路向灵敏放大器输出第三电压或第四电压；其中，第一电压＞第二电压＞第三电压＞第四电压；当第一位线上的电压高于第一参考位线上的电压时，灵敏放大器向第一位线输出第一电压或者第二电压，向第一参考位线输出第三电压或者第四电压。
在一种可能的实施方式中，该方法还包括：当第一位线上的电压低于第一参考位线上的电压时，灵敏放大器向第一参考位线输出第一电压或者第二电压，向第一参考位线输出第三电压或者第四电压。
在一种可能的实施方式中，第一电压切换电路向灵敏放大器输出第一电压或者第二电压，第二电压切换电路向灵敏放大器输出第三电压或第四电压包括：第一电压切换电路向灵敏放大器输出第一电压，且第二电压切换电路向灵敏放大器输出第四电压；或者，第一电压切换电路向灵敏放大器输出第二电压时，且第二电压切换电路向灵敏放大器输出第三电压。
在一种可能的实施方式中，第一电压为第一铁电存储单元的写电压Vw，第四电压为第一铁电存储单元的零电压V0。
在一种可能的实施方式中，第一电压切换电路向灵敏放大器输出第一电压或者第二电压，第二电压切换电路向灵敏放大器输出第三电压或第四电压包括：第一电压切换电路向灵敏放大器的第一线路输出第一电压或者第二电压，第二电压切换电路向灵敏放大器的第二线路输出第三电压或第四电压。
在一种可能的实施方式中，铁电存储阵列还包括第二铁电存储单元；第二铁电存储单元的第一电极和第一铁电存储单元连接不同的第一电极，连接同一第二电极；第二电极连接第一位线。
在一种可能的实施方式中，铁电存储阵列还包括第三铁电存储单元；第三铁电存储单元和第一铁电存储单元共用第一电极，且第三铁电存储单元的第二电极和第一铁电存储单元的第二电极分别通过不同的晶体管连接到第一位线。
在一种可能的实施方式中，第一线路为上拉信号布线，第二线路为下拉信号布线。
可以理解的是，第二方面提供的方法可由第一方面提供的读写电路实施，因此，第二方面提供的方法的有益效果，可以参考上文对第一方面提供的读写电路的有益效果的介绍，在此不再赘述。
第三方面，提供了一种存储器，包括第一方面读写电路和铁电存储阵列。
利用本申请实施例提供的读写电路和方法，向铁电存储单元的位线输出不同大小的电压，以实现对铁电存储单元的不同操作，并且可以降低铁电存储器的功耗，以及该读写电路结构简单，有助于降低铁电存储器的体积和成本。
附图说明
图1为本申请实施例提供的一种铁电存储阵列的结构示意图；
图2A为一种DRAM读写电路的结构示意图；
图2B为一种用于操作图1所示铁电存储阵列的读写电路的结构示意图；
图3A为共用BL和PL的铁电电容的等效电路图；
图3B为与选中的铁电电容共用BL和PL的铁电电容的两端间电压差示意图；
图4为本申请实施例提供的一种用于控制图1所示铁电存储阵列的读写电路的结构示意图；
图5为本申请实施例提供的一种存储单元阵列操作方法流程图；
图6为在铁电电容C1的读写阶段，铁电电容C2的电极B1和电极B2上的电压示意图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
图1示出了一种铁电存储阵列，由多个1TnC结构组成。其中，1T是指一个晶体管(transistor，T)，nC是指n个铁电电容(capacitor，C)，n为大于或等于1的正整数。也就是说，一个1TnC结构包括一个晶体管和n个铁电电容。示例性的，晶体管可以是采用后道(back end of line，BEOL)工艺制备而成的，因此，晶体管也可以称为后道晶体管或后道管，即1TnC结构中的晶体管是采用后道工艺制成。
晶体管具有栅极(gate，G)、电极A1和电极A2。其中，晶体管的电极A1可以是晶体管的源极(source，S)，晶体管的电极A2可以是晶体管的漏极(drain，D)。或者，晶体管的电极A1可以是晶体管的漏极，晶体管的电极A2可以是晶体管的源极。也就是说，电极A1既可以是源极，也可以是漏极；电极A2既可以是源极，也可以是漏极。其中，当电极A1是源极时，电极A2是漏极；当电极A1是漏极时，电极A2是源极。在栅极的作用下，晶体管可以产生二维电子气(two-dimensional electron gas，2DEG)，以导通电极A1和电极A2。
铁电电容具有电极B1和电极B2。其中，图1所示的铁电存储阵列中同一层的铁电电容共用电极B1。同一1TnC结构中的n个铁电电容分别位于不同层，且共用电极B2。换言之，同一1TnC结构中的n个铁电电容连接不同的电极B1，连接同一电极B2。示例性的，不同层的电极B1相互平行。
同一1TnC结构中的n个铁电电容的电极B2和该1TnC结构中的晶体管的电极A2连接。即同一1TnC结构中的n个铁电电容连接同一电极A2。另外，同一1TnC结构中的n个铁电电容分属于不同层，即同一1TnC结构中的n个铁电电容连接不同的电极B1，不同的电极B1连接不同的板线(plate line，PL)。换言之，同一1TnC结构中的n个铁电电容通过电极B1分别连接不同的板线。也就是说，同一1TnC结构中的n个铁电电容中的不同铁电电容连接的板线不同。
由此，可以通过晶体管从铁电存储阵列中选中n个铁电电容，以及通过板线从该n个铁电电容中选中某个铁电电容，进而可以对选中的铁电电容进行操作。
如图1所示，晶体管的栅极连接字线(word line，WL)，晶体管的电极A1连接位线(bit line，BL)。其中，图1所示的铁电存储阵列中同一行的晶体管的栅极和同一字线连接，同一列的晶体管的电极A1和同一位线连接。示例性的，字线和位线相互垂直。其中，图1所示的铁电存储阵列中所谓的行和所谓的列，均与该阵列中所谓的层平行。
可以理解，在图1所示的1TnC结构中，n个铁电电容实现了三维堆叠。由此，相对于 采用传统的1T1C结构(即一个晶体管和一个铁电电容的结构)，可以提高铁电存储器的存储密度。
在一种方案中，为了与传统的动态随机存取存储器(dynamic random access memory，DRAM)协议兼容，采用与DRAM的操作方式类似的操作方式，来操作1TnC结构。具体如下。
图2A示出了DRAM的典型读写电路，图2B示出了本方案中用于操作1TnC结构的读写电路。其中，WLn+1和WLn分别代表不同的字线。BLN是反位线，也可以称为参考位线。BLN和BL成对出现，即一个BL对应一个BLN。通过比较BLN和BL上的电压大小，可以读取存储单元中存储的信息。SAN是指灵敏放大器中的灵敏放大器下拉信号(sense amplifier pull-down)布线，SAP是指灵敏放大器中的灵敏放大器上拉信号(sense amplifier pull-up)布线。其中，SAN也可以称为低压侧电源布线，SAN也可以称为高压侧电源布线。EQ是指均衡器的栅极线，用于向均衡器的栅极施加电压，以使得均衡器处于导通状态。CSL是指列选择线(column select line)，WE(write enable)用于产生写使能信号。其中，图2A所示的读写电路的功能以及操作方式可以参考现有技术介绍，在此不再赘述。图2B所示的读写电路的功能以及操作方式与图2A所示的读写电路的功能以及操作方式类似，在此也不再赘述。
利用图2A所示的对DRAM中的存储单元进行操作时，在读写阶段，选中的(selected)电极B2上的电压为电压V0或者为电压Vw。其中，电压Vw可以称为写电压。电压V0可以称为零电压。在一些实施例中零电压电压V0可以为0V。其中，读写阶段是指在对存储单元进行操作的过程中，对BL上的信息进行处理的阶段。具体而言，若对存储单元的操作具体为读操作，那么读写阶段具体是指将BL上的电压(代表了比特“1”或“0”)传递到处理器的阶段。若对存储单元的操作具体为写操作，那么读写阶段具体是指将BL上的电压调整为对应待写入信息(比特“1”或“0”))的电压。其中，“操作”可以是存储单元的读操作、写操作等的统称。其中，存储单元是指存储器中用于存储或者说记录信息的最小单元，一个存储单元用于存储或记录一个比特值。
利用图2B所示读写电路，对1TnC结构进行的操作，与利用图2A所示的对DRAM中的存储单元进行的操作类似，在读写阶段，选中的电极B2上的电压为电压V0或者为电压Vw。由于1TnC结构中的n个铁电电容共用电极B2。该n个铁电电容中未选中的铁电电容的电极B1上的电压为半选电压，即1/2Vw。如此，对于该n个铁电电容中未选中的铁电电容两端存在大小为1/2Vw的电压差。理论上讲，1/2Vw小于铁电电容的矫顽场电压Vc，不会导致铁电电容的极化状态发生反转。读写阶段持续的时间较长(通常为72μs)。即未选中的铁电电容两端长时间存在大小为1/2Vw的电压差。实验表明，铁电电容长时间存在大小为1/2Vw的电压差时，铁电电容中一部分的铁原子的极化状态会发生反转，降低铁电电容的剩余极化强度，影响信息读取的窗口大小，降低了铁电存储器的可靠性。虽然，可以通过周期性的刷新操作，来保持铁电存储器的可靠性，但这会导致铁电存储器功耗的大大增加。
另外，参阅图3A和图3B，在利用图2B所示读写电路，对1TnC结构进行的操作的过程中，在破坏阶段和恢复阶段，选中的铁电电容的电极B1上的电压分别为电压Vw和电压V0。由于在图1所示的铁电存储阵列中，同一层的铁电电容共用电极B1。即在选中铁电电容的破坏阶段和恢复阶段，与选中的铁电电容处于同一层的其他铁电电容的电极B1上的电压也分别为电压Vw和电压V0。此外，在图1所示的铁电存储阵列中，同一列的晶体管的电极A1和同一BL连接，即一个BL可以连接多个晶体管的电极A1。在利用图2B所示读写 电路，对1TnC结构进行的操作的过程中，在读写阶段，对应选中铁电电容的BL上的电压为电压V0或电压Vw，使得连接该BL的未选通的晶体管的电极A2和电极A1之间存在大小为1/2Vw的电压差(未选中的电极B2上的电压为1/2Vw，与未选中的电极B2连接的电极A2上的电压也为1/2Vw)，导致未选通的晶体管的电极A1和电极A2之间存在漏电流，进而导致未选中电极B2上的实际电压和1/2Vw存在ΔV(不为零)的偏移，也就是说，未选中电极B2上的实际电压为1/2Vw±ΔV。如此，导致与选中的铁电电容共用BL且共用PL的未选中铁电电容(即与选中的铁电电容处于同一层，且同一列的未选中铁电电容)的两端之间的实际电压差为1/2Vw±ΔV。也就是说，未选中的铁电电容两端的电压有可能大于1/2Vw，这可能会导致铁电电容中的铁原子的极化状态反转，导致存储的信息出错。
本申请实施例提供了一种可以存储单元阵列操作方案，可以对1TnC结构中的铁电电容进行操作，例如铁电电容C1。其中，在铁电电容C1进行操作过程，可以在读写阶段，使得铁电电容C1的电极B2上的电压小于电压Vw，且大于电压V0，从而使得与铁电电容C1共用电极B2的其他铁电电容的电极B2和电极B1之间的电压差小于半选电压，减少了对其他铁电电容的剩余极化强度的影响，进而减少了对铁电存储器可靠性的影响。并且，铁电电容C1的电极B2上的电压小于电压Vw，且大于电压V0，减少与铁电电容C1共用BL的铁电电容的晶体管的漏电流，进而降低了与铁电电容C1共用BL且共用PL的其他铁电电容之间的电压差，减少了该其他铁电电容中的铁原子的极化状态反转的可能性，提高了铁电存储器的可靠性。
其中，在本申请实施例中，电压Vw可以称为写电压Vw。电压V0可以称为零电压V0。其中，写电压Vw大于零电压V0，并且写电压Vw和零电压V0之间的电压差大于铁电电容的矫顽场电压Vc。在一些实施例中，零电压V0可以为0V。在另一些实施例中，零电压V0可以大于0V，例如可以为0.05V、0.1V等等。
接下来，对本申请实施例提供的存储单元阵列操作方案进行说明。
参阅图4，本申请实施例提供了一种可以实施该操作方案的读写电路，包括灵敏放大器401、电压输出电路402、均衡器403等。其中，灵敏放大器401可以耦合至BL405和BLN406，并感知BL405和BLN406之间的电压差，并根据该电压差调整BL405和BLN406上的电压，使得低电压者的电压更低，高电压者的电压更高，从而放大两者之间的电压差。其中，BL405是位线，BLN406是反位线。如上所述，反位线也可以称为参考位线。位线和反位线成对出现，可以通过比较位线和反位线上的电压，来读取相应铁电存储单元中存储的信息。具体而言，可以先向BL405(即位线)和BLN406(反位线)施加相同的电压，然后，在后续的破坏阶段，若铁电电容的极化状态发生反转，则会导致BL405上的电压升高，若铁电电容的极化状态不发生反转，则会导致BL405上的电压降低。而BLN406的电压保持不变。这会导致BL405上的电压大于BLN406上的电压，或BL405上的电压小于BLN406上的电压的情况。从而可以通过比较BL405和BLN406上的电压，实现信息读取。其中，当BL405上的电压大于BLN406上的电压时，灵敏放大器401将BL405上的电压调整到电压V1，将BLN406上的电压调整到电压V2。反之亦然。其中，电压V1大于电压V2。电压V1和电压V2由电压输出电路402向灵敏放大器401输出，以便灵敏放大器401根据电压V1和电压V2，调整BL405和BLN406上的电压。其中，电压V1在电压Vw和电压Vprot1这两个中取值，电压V2在电压V0和电压Vprot0这两个中取值。具体而言，当电压V1为电压Vw时，电压V2为电压V0。当电压V1为电压Vprot1时，电压V2为电压Vprot0。其中，电压Vprot1和电压Vprot0将在下文进行介绍，在此不再赘述。
更具体地，如图4所示，电压输出电路402包括电压切换电路4021和电压切换电路4022。其中，电压切换电路4021用于向灵敏放大器401输出电压V0或电压Vprot0，电压切换电路4022用于向灵敏放大器401输出电压Vw或电压Vprot1。示例性的，如图4所示，电压切换电路4021可以通过导体406和灵敏放大器401连接，电压切换电路4022可以通过导体407和灵敏放大器401连接。也就是说，灵敏放大器401可以通过导体406和导体407连接电压输出电路402。
在一些实施例中，导体406具体可以为下拉信号(sense amplifier pull-down)布线，导体407可以为上拉信号(sense amplifier pull-up)布线。也就是说，灵敏放大器401可以通过下拉信号布线和上拉信号布线连接电压输出电路402。如上所述，电压输出电路402向灵敏放大器401输入大小不同的两个电压，即电压V1和电压V2。其中，电压输出电路402通过下拉信号布线向灵敏放大器401输出两个电压中的较低电压(电压V2)，通过上拉信号布线向灵敏放大器401输出两个电压中的较高电压(电压V1)。换言之，下拉信号布线用于承接电压输出电路402输出的两个电压中的较低电压，并传递至灵敏放大器401。上拉信号布线用于承接电压输出电路402输出的两个电压中的较高电压，并传递至灵敏放大器401。
其中，电压切换电路4021可以包括晶体管RB0和晶体管RW0。其中，晶体管RB0的源极(或漏极)连接电压为电压V0的驱动电路，漏极(或源极)连接导体406。晶体管RW0的源极(或漏极)连接电压为电压Vprot0的驱动电路，漏极(或源极)连接导体406。当晶体管RB0导通时，电压V0通过晶体管RB0传递到导体406上，进而通过导体406传递到灵敏放大器401，从而将电压V0输出到灵敏放大器401。当晶体管RW0导通时，电压Vprot0通过晶体管RW0传递到导体406上，进而通过导体406传递到灵敏放大器401，从而将电压Vprot0输出到灵敏放大器401。
其中，电压切换电路4022可以包括晶体管RB1和晶体管RW1。其中，晶体管RB1的源极(或漏极)连接电压为电压Vw的驱动电路，漏极(或源极)连接导体407。晶体管RW1的源极(或漏极)连接电压为电压Vprot1的驱动电路，漏极(或源极)连接导体407。当晶体管RB1导通时，电压Vw通过晶体管RB1传递到导体407上，进而通过导体407传递到灵敏放大器401，从而将电压Vw输出到灵敏放大器401。当晶体管RW1导通时，电压Vprot1通过晶体管RW1传递到导体407上，进而通过导体407传递到灵敏放大器401，从而将电压Vprot1输出到灵敏放大器401。
接下来，结合图4，示例描述放大BL404和BLN405之间电压差的方案。
如图4所示，灵敏放大器401可以包括N型晶体管4011、N型晶体管4012、P型晶体管4013、P型晶体管4014。其中，N型晶体管是指沟道层为N型半导体的晶体管，P型晶体管是指沟道层为P型半导体的晶体管。N型半导体是指掺杂有N型杂质(也称为施主杂质，用于提供电子)的半导体。P型半导体是指掺杂有P型杂质(也称为受主杂质，用于提供空穴)的半导体。其中，当N型晶体管栅极上的电压较高时，N型晶体管导通。当P型晶体管栅极上电压较低时，P型晶体管导通。
如图4所示，电压切换电路4021通过导体406连接N型晶体管4011的电极A1和N型晶体管4012的电极A1，电压切换电路4022通过导体407连接P型晶体管4013的电极A1和P型晶体管4014的电极A1，BL404连接N型晶体管4011的电极A2和P型晶体管4013的电极A2，BLN405连接N型晶体管4012的电极A2和P型晶体管4014的电极A2，BL404还连接N型晶体管4012的栅极和P型晶体管4014的栅极，BLN405还连接N 型晶体管4011的栅极和P型晶体管4013的栅极。其中，晶体管的电极A1和电极A2可以参考上文对图1所示晶体管的介绍，在此不再赘述。
在灵敏放大器401向BLN405和BL404施加相关电压之前，BLN405和BL404的电压都比较低(例如，BLN405上的电压为电压Vpre1，BL404上的电压为电压Vrd1或电压Vrd0，具体将在下文进行介绍)。这种情况下，N型晶体管不导通，P型晶体管导通，并且栅极电压越低的P型晶体管的导通能力越强。
可以设定BLN405的电压低于BL404上的电压，如此，P型晶体管4013的导通能力强于P型晶体管4014。来自电压切换电路4022的电压更多作用到BL404上，升高BL404的电压。BL404电压升高，也导致N型晶体管4012栅极上的电压升高，如此，N型晶体管4012导通，来自电压切换电路4021上的电压作用到BLN405上，降低BLN405的电压。如此，使得BL404上的电压升高，BLN405上的电压降低，实现电压差的放大。
同理，可以设定BLN405的电压高于BL404上的电压，如此，P型晶体管4014的导通能力强于P型晶体管4013。来自电压切换电路4022的电压更多作用到BLN405上，升高BLN405的电压。BLN405电压升高，也导致N型晶体管4011栅极上的电压升高，如此，N型晶体管4011导通，来自电压切换电路4021上的电压作用到BL404上，降低BL404的电压。如此，使得BL404上的电压升高，BL404上的电压降低，实现电压差的放大。
如此，通过本申请实施例提供的灵敏放大器以及电压切换电路，可以向BL404和BLN405分别施加电压V1和电压V2。
继续参阅图4，均衡器403可以向BL404和BLN405输出电压Vpre1，也可以向BL404和BLN405输出电压Vpre2，也可以向BL404和BLN405输出电压1/2Vw。
在一些实施例中，向BL404和BLN405输出电压Vpre1、电压Vpre2以及电压1/2Vw的均衡器403可以为同一均衡器。该均衡器可以在不同时刻向BL404和BLN405输出不同电压，实现均衡器的时分复用。电压Vpre1、电压Vpre2将在下文进行介绍，在此不再赘述。
在一些实施例中，均衡器403可以包括不同的均衡器。不同的均衡器分别向BL404和BLN405输出不同电压。
图4所示读写电路的更具体功能将在下文中，结合存储器的操作方案流程，进行介绍，在此不再赘述。
图5示出了本申请实施例提供存储单元阵列操作方案流程图。该操作方案的一个完整操作流程包括读预充阶段、破坏阶段、读取阶段、放大阶段、读写阶段、恢复阶段、预充待命阶段、待命阶段。
接下来，以对铁电电容C1的操作为例，分别介绍各阶段的具体操作过程。在一些实施例中，铁电电容C1可以为图1所示的铁电存储阵列中的一个铁电电容。在铁电电容C1的完整操作周期中，铁电电容C1为选中的铁电电容，其他的铁电电容为未选中的铁电电容。在一些实施例中，铁电电容C1可以为其他结构中的铁电电容，例如1T1C结构中的铁电电容。在本申请实施例中，铁电电容也可以称为铁电存储单元，为铁电存储器或者铁电存储阵列中的存储单元。即铁电存储器或者铁电存储阵列中的一个铁电电容为该铁电存储器或者铁电存储阵列中的一个存储单元。
在铁电电容C1被操作之前，铁电电容C1处于待命阶段。待命阶段为等待操作的阶段，即在铁电电容C1的待命阶段，铁电电容C1处于等待操作的状态。当铁电电容C1处于待命阶段时，铁电电容C1的晶体管处于关断状态(即WL上的电压为电压V0)，PL(或者说电极B1)上的电压为1/2Vw，电极B2上的电压也为1/2Vw，以保持铁电电容C1两端电压的 稳定。1/2Vw是指电压Vw的二分之一，可以称为半选电压。在一个例子中，电压Vw为2V。
针对铁电电容C1的操作命令，可以触发铁电电容C1从待命阶段进入到读预充阶段。在读预充阶段，为铁电电容C1的电极B2提供初始电压Vpre1。其中，初始电压Vpre1为预设的，可以按照如下要求设定初始电压Vpre1。
初始电压Vpre1小于电压Vw，并且，初始电压Vpre1和电压Vw之间的电压差大于铁电电容的矫顽场电压Vc，从而能够在铁原子的极化状态和该电压差的方向不一致时，使得铁原子越过高能阶，而达到另一种极化状态。也就是说，初始电压Vpre1联合电压Vw能够破坏铁电电容C1或者说能够使铁电电容C1中铁原子的极化状态反转。在一个例子中，初始电压Vpre1可以等于电压V0。
其中，可以将铁电电容C1的BL上的电压调整为初始电压Vpre1。在一个例子中，可以通过图5所示的读写电路中的均衡器403，将铁电电容C1的BL上的电压调整为初始电压Vpre1。然后，可以将铁电电容C1的WL上的电压调整为电压Vdd，使得铁电电容C1的晶体管进入导通状态，由此，可以将BL上的初始电压Vpre1传递至铁电电容C1的电极B2，从而为铁电电容C1的电极B2提供初始电压Vpre1。其中，电压Vdd可以称为最高电压或者电源电压。电压Vdd的值较高，在一个例子中，电压Vdd为2.5V。
在读预充阶段，铁电电容C1的PL上的电压仍为1/2Vw。
在读预充阶段结束后，可以进入破坏阶段。在破坏阶段，关闭铁电电容C1的晶体管(例如，将铁电电容C1的WL上的电压调整为电压V0)，使得铁电电容C1的电极B2进行悬空状态(floating)。可以设定电极B2在进入悬空状态后的电压为电压Vfg0。可以理解，电极B2在进入悬空状态后的电压和在进入悬空状态前的电压几乎保持不变，即电压Vfg0等于或者约等于初始电压Vpre1。其中，电压Vfg0联合电压Vw也能够破坏铁电电容C1或者说能够使铁电电容C1中铁原子的极化状态反转。
在破坏阶段，将铁电电容C1的PL上的电压调整为Vw，即铁电电容C1的电极B1上的电压为Vw。同时，铁电电容C1的电极B2上的电压为电压Vfg0。此时铁电电容C1的电极B1和电极B2之间的电压差的方向为正极化方向。
若铁电电容C1处于负极化状态，那么在铁电电容C1的电极B1和电极B2之间的电压差的作用下，铁电电容C1从负极化状态转化为正极化状态。在从负极化状态转化为正极化状态转化的过程中，铁电电容C1中的正电荷会进入到电极B2，使得电极B2的电压从电压Vfg0上升到电压Vfg1。
若铁电电容C1处于正极化状态，那么铁电电容C1的电极B1和电极B2之间的电压差不会改变铁电电容C1的极化状态，即铁电电容C1仍保持电压Vfg0。
其中，可以将铁电电容C1的PL上的电压调整为电压Vw，使铁电电容C1从负极化状态转化为正极化状态，或者铁电电容C1保持负极化状态的这一过程理解为对铁电电容C1的破坏。
在铁电电容C1的晶体管处于关闭状态下，可以将铁电电容C1的BL上的电压和铁电电容C1的BLN上的电压，均调整为电压Vpre2。在一个例子中，可以通过图5所示的读写电路中的均衡器403，将铁电电容C1的BL和BLN上的电压调整为电压Vpre2。电压Vpre2为预设的，其中，电压Vpre2的设置要求具体将在下文介绍，在此不再赘述。
在一些实施例中，在破坏阶段，在关闭铁电电容C1的晶体管后，也就是说，在该实施例中，将BL和BLN上的电压调整为电压Vpre2和对铁电电容C1的破坏同时进行，可以提升操作速度。
在破坏阶段结束后，可以进入读取阶段。在读取阶段，将铁电电容C1的WL上的电压提升至电压Vdd，使铁电电容C1的晶体管进入导通状态。如此，铁电电容C1的电极B2和铁电电容C1的BL进行电荷均衡。其中，在电荷均衡前，如上所述，铁电电容C1的电极B2上的电压为电压Vfg(即电压Vfg0或电压Vfg1)，铁电电容C1的BL上的电压为电压Vpre2。在电荷均衡后，铁电电容C1的电极B2和BL上的电压变为电压Vrd。铁电电容C1的BLN上的电压仍为Vpre2。
其中，当电压Vfg具体为电压Vfg0，电压Vrd具体为电压Vrd0。当电压Vfg具体为电压Vfg1，电压Vrd具体为电压Vrd1。其中，电压Vfg1大于电压Vpre2，电压Vrd0小于电压Vpre2。其中，电压Vpre2为设定值，为了能够使电压Vfg1大于电压Vpre2，电压Vrd0小于电压Vpre2，电压Vpre2、电压Vfg0、电压Vrd0、电压Vfg1、电压Vrd1，需要满足如下关系。
Vfg0×Cfg+Vpre2×Cbl＝Vrd0×(Cfg+Cbl)        式(1)；
Vfg1×Cfg+Vpre2×Cbl＝Vrd1×(Cfg+Cbl)        式(2)；
Vfg0＜Vpre2＜Vfg1                              式(3)；
其中，Cfg为铁电电容C1的电极B2的总电容，Cbl为铁电电容C1的BL的总电容。
根据式(1)、式(2)和式(3)，确定电压Vpre2的值。
在读取阶段，铁电电容C1的BL上的电压会因铁电电容C1的极化状态的不同而不同，即铁电电容C1的极化状态为正极化状态时，铁电电容C1的BL上的电压为电压Vrd0；铁电电容C1的极化状态为负极化状态时，铁电电容C1的BL上的电压为电压Vrd1。如此，可以读取到铁电电容C1所记录或者说存储的比特值。可以设定铁电电容C1的极化状态为正极化状态时，铁电电容C1记录比特值D1,铁电电容C1的极化状态为负极化状态时，铁电电容C1记录比特值D2。即电压Vrd0代表比特值D1，电压Vrd1代表比特值D2。其中，比特值D1为“0”，比特值D2为“1”；或者，比特值D1为“1”，比特值D2为“0”。
在读取阶段结束后，可以进入放大阶段，即将铁电电容C1的BL上的电压增大或降低，以便在将铁电电容C1的BL上的电压传递至处理器后，处理器可以识别出该电压所代表的信息。具体而言，在放大阶段，若铁电电容C1的BL上的电压为电压Vrd0，则将铁电电容C1的BL上的电压调整为电压Vprot0。若铁电电容C1的BL上的电压为电压Vrd1，则将铁电电容C1的BL上的电压调整为电压Vprot1。
其中，由上所述，电压Vrd0代表比特值D1，电压Vrd1代表比特值D2。因此，电压Vprot0代表比特值D1，电压Vprot1代表比特值D2。
其中，电压Vprot0和电压Vprot1均为预设值。电压Vprot0和电压Vprot1均小于电压Vw，且均大于电压V0，以及电压Vprot0和电压Vprot1之间的电压差大于或等于预设的阈值E1，使得BL上的电压Vprot0被传递至处理器时的电压值或BL上的电压Vprot1被传递至处理器时的电压值，能够被处理器识别，从而使得处理器能够识别来自BL的电压所代表的信息。
其中，可以理解，电压Vrd1和电压Vrd0之间的电压差小于阈值E1，因此，将铁电电容C1的BL上的电压由电压Vrd0调整为电压Vprot0的过程，以及将铁电电容C1的BL上的电压由电压Vrd1调整为电压Vprot1的过程，可以称之为放大。
如图5所示，电压Vprot0小于电压Vprot1。即电压Vw＞电压Vprot1＞电压Vprot0＞电压V0。
在一些实施例中，可以利用图5所示的读写电路，增大或降低铁电电容C1的BL上的电 压。具体而言，SAN的电压切换电路4021中的晶体管RW0选通，通过SAN向灵敏放大器401输出电压Vprot0。同时，SAP的电压切换电路4022中的晶体管RW1选通，通过SAP向灵敏放大器401输出电压Vprot1。
当铁电电容C1的BL上的电压小于铁电电容C1的BLN上的电压Vpre2时，即当铁电电容C1的BL上的电压为电压Vrd0时，灵敏放大器401将铁电电容C1的BL上的电压由电压Vrd0调整为电压Vprot0。与此同时，灵敏放大器401将铁电电容C1的BLN上的电压由电压Vpre2调整为电压Vprot1。
当铁电电容C1的BL上的电压大于铁电电容C1的BLN上的电压Vpre2时，即当铁电电容C1的BL上的电压为电压Vrd1时，灵敏放大器401将铁电电容C1的BL上的电压由电压Vrd1调整为电压Vprot1。与此同时，灵敏放大器401将铁电电容C1的BLN上的电压由电压Vpre2调整为电压Vprot0。
之后，进入读写阶段。如上所述，读写阶段是指在对铁电电容C1进行操作的过程中的对BL上信息的处理阶段。其中，若针对铁电电容C1的操作命令具体为读命令，那么读写阶段具体是指将BL上的电压(代表了比特值“1”或“0”)传递到处理器的阶段。若针对铁电电容C1的操作命令具体为写命令，那么读写阶段具体是指将BL上的电压调整为对应待写入信息(比特值“1”或“0”))的电压。更具体地，如图5所示，在读写阶段，若针对铁电电容C1的操作命令具体为读命令，那么读写阶段具体是指将铁电电容C1的BL上的电压(Vprot0或Vprot1)传递到处理器的阶段。若针对铁电电容C1的操作命令具体为写命令，那么读写阶段具体是指将BL上的电压调整为对应待写入信息(比特值“1”或“0”))的电压。其中，电压Vprot0代表比特值D1，电压Vprot1代表比特值D2。
在针对铁电电容C1的操作命令具体为写命令的情况下，若待写入信息为比特值D1，且铁电电容C1的BL上的电压为电压Vprot0，则铁电电容C1的BL上的电压继续保持电压Vprot0。以便在后续回写阶段，将比特值D1再次写入到铁电电容C1中，或者，保持铁电电容C1记录的信息不变。
若待写入信息为比特值D1，且铁电电容C1的BL上的电压为电压Vprot1(即铁电电容C1中记录的信息为比特值D2)，则将铁电电容C1的BL上的电压由电压Vprot1调整为电压Vprot0，以便在后续回写阶段，将铁电电容记录的信息由比特值D2调整为比特值D1，从而完成待写入信息的写入。
由上文可知，在读写阶段，铁电电容C1的BL上的电压为电压Vprot0或电压Vprot1，且此时铁电电容C1的晶体管处于选通状态，因此，铁电电容C1的电极B2上的电压为电压Vprot0或电压Vprot1。其中，电压Vprot0和电压Vprot1均小于电压Vw，且均大于电压V0。由上所述，在铁电电容C1的读写阶段，与铁电电容C1共用电极B2的其他铁电电容的电极B1上的电压为1/2Vw。由此，与铁电电容C1共用电极B2的其他铁电电容的两端电压差小于1/2Vw，从而减少了该其他铁电电容中极化状态反转的铁原子的数量，使得铁电电容可以保持剩余极化强度，提高了铁电存储器的可靠性。
其中，图6示出了在铁电电容C1的读写阶段，铁电电容C2的电极B1和电极B2上的电压，可见铁电电容C2的电极B1和电极B2之间的电压差小于1/2Vw。其中，铁电电容C2可以为图1所示铁电存储阵列中的除铁电电容C1之外一个铁电电容，且铁电电容C2和铁电电容C1共用电极B2。
并且，在读写阶段，铁电电容C1的BL上的电压为电压Vprot0或电压Vprot1，使得连接该BL的未选通的晶体管的电极A2和电极A1之间的电压差小于1/2Vw(未选中的电极B2 上的电压为1/2Vw，与未选中的电极B2连接的电极A2上的电压也为1/2Vw)，从而可以减少未选通的晶体管的电极A1和电极A2之间的漏电流，进而减少了未选中电极B2上的实际电压和1/2Vw之间的电压偏移，因此，降低了与铁电电容C1共用BL且共用PL的未选中铁电电容(即与选中的铁电电容处于同一层，且同一列的未选中铁电电容)的两端之间的实际电压差，从而降低了未选中铁电电容中的铁原子的极化状态反转的风险，降低了存储信息出错风险。
此外，可以理解，当BL上的电压较低时，在将BL上的电压传递至处理器的数据路径(datapath)上，采用较低的电压，就可以将BL上的电压传递至处理器。在本申请实施例中，铁电电容C1的BL上的电压为电压Vprot0或电压Vprot1，低于电压Vw，降低了将BL上的电压传递至处理器的数据路径(datapath)上的操作电压，进一步节省了功耗。
读写阶段之后，可以进入恢复阶段。恢复阶段也可以称为回写阶段，在该阶段可以对在破坏阶段被破坏(即极化状态发生了反转)的铁电电容C1进行恢复或者说回写。继续参阅图5，在恢复阶段，铁电电容C1的晶体管继续保持选通状态，即铁电电容C1的WL上的电压继续保持Vdd。在恢复阶段，将铁电电容C1的电极B1或者说PL的电压调整为电压V0。由于当铁电电容C1两端的电压差为Vw时，才能够改变铁电电容的极化状态。而在读写阶段，铁电电容C1的电极B2上的电压为电压Vprot0或电压Vprot1，均小于Vw。因此，在恢复阶段，需要将铁电电容C1的电极B2上的电压由电压Vprot1调整为电压Vw，或者由电压Vprot0调整为电压V0。
具体而言，当铁电电容C1的电极B2上的电压为电压Vprot0时，说明在破坏阶段，铁电电容C1的极化状态未发生反转，仍保持正极化状态，或者说明，待写入信息对应正极化状态(待写入信息对应电压Vprot0，为比特值D1)。在这种情况下，将铁电电容C1的电极B2上的电压由电压Vprot0调整为电压V0。此时，铁电电容C1两端的电压均为电压V0，即电压差为0，铁电电容C1仍可以保持正极化状态，从而完成信息的回写或者说写入。
当铁电电容C1的电极B2上的电压为电压Vprot1时，说明在破坏阶段，铁电电容C1的极化状态发生了反转，即由负极化状态反转为了正极化状态，或者，说明待写入信息对应负极化状态(待写入信息对应电压Vprot1，为比特值D2)。在这种情况下，将铁电电容C1的电极B2上的电压由电压Vprot1调整为电压Vw。此时，铁电电容C1的电极B1和电极B2之间的压差为-Vw，可以将铁电电容C1的极化状态从正极化状态反转为负极化状态，完成信息回写或者说写入。
在一些实施例中，在恢复阶段，可以利用图5所示的读写电路，进行回写或者说写入。具体而言，具体而言，SAN的电压切换电路4021中的晶体管RB0选通，通过SAN向灵敏放大器401输出电压V0。同时，SAP的电压切换电路4022中的晶体管RB1选通，通过SAP向灵敏放大器401输出电压Vw。
由上文所述，在放大阶段，灵敏放大器402在将铁电电容C1的BL上的电压调整为电压Vprot0的同时，将铁电电容C1的BLN上的电压调整为电压Vprot1。灵敏放大器402在将铁电电容C1的BL上的电压调整为电压Vprot1的同时，将铁电电容C1的BLN上的电压调整为电压Vprot0。
那么在恢复阶段，当铁电电容C1的BL上的电压为电压Vprot0，BLN上的电压为电压Vprot1时，即铁电电容C1的BL上的电压小于BLN上的电压时，灵敏放大器401将铁电电容C1的BL上的电压由电压Vprot0调整为电压V0。与此同时，灵敏放大器401将铁电电容C1的BLN上的电压由电压Vprot1调整为电压Vw。
当铁电电容C1的BL上的电压为电压Vprot1，BLN上的电压为电压Vprot0时，即铁电电容C1的BL上的电压大于BLN上的电压时，灵敏放大器401将铁电电容C1的BL上的电压由电压Vprot1调整为电压Vw。与此同时，灵敏放大器401将铁电电容C1的BLN上的电压由电压Vprot0调整为电压V0。
恢复阶段之后，进入预充待命阶段。在预充待命阶段，如图5所示，铁电电容C1的晶体管继续保持选通状态，即铁电电容C1的WL上的电压继续保持Vdd。将铁电电容C1的BL和BLN上的电压调整为1/2Vw。通过铁电电容C1的BL，使得铁电电容C1的电极B2上的电压也被调整为1/2Vw。将铁电电容C1的电极B1或者说PL的电压调整为电压1/2Vw。由此，铁电电容C1的两端电压差为0，以保持铁电电容C1的极化状态不变。
在一些实施例中，可以通过图5所示的读写电路中的均衡器403，将铁电电容C1的BL上的电压和BLN上的电压调整为电压1/2Vw。
预充待命阶段结束后，进行待命阶段。如图5所示，在待命阶段，铁电电容C1的WL上的电压为V0，晶体管处于关断状态。铁电电容C1的PL、BL以及BLN保持电压Vw/2，铁电电容C1的两端电压差为0，以保持铁电电容C1的极化状态不变。
由此，完成了对铁电电容C1的一个完整操作流程。
上文以对铁电电容C1的操作为了，示例介绍了对铁电电容的操作方案。在该方案中，在放大阶段和读写阶段，将BL上的电压调整为低于电压Vw，且高于电压V0的电压，减低了对当前选中的铁电电容的操作对其他铁电电容的影响。具体而言：
降低了与当前选中的铁电电容共用电极B2的其他铁电电容的两端电压差，使之小于1/2Vw，从而减少了该其他铁电电容中极化状态反转的铁原子的数量，使得铁电电容可以保持剩余极化强度，提高了铁电存储器的可靠性。同时，可减少存储器刷新操作的频率，降低了铁电存储器功耗；
并且，降低了与当前选中的铁电电容共用BL且共用PL的未选中铁电电容(即与选中的铁电电容处于同一层，且同一列的未选中铁电电容)的两端之间的实际电压差，从而降低了未选中铁电电容中的铁原子的极化状态反转的风险，降低了存储信息出错风险。
另外，当前选中的铁电电容的BL上的电压较低，降低了将BL上的电压传递至处理器的数据路径上的操作电压，进一步节省了功耗。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以适合的方式结合。
可以理解的是，在本申请实施例的描述中，“示例性的”、“例如”或者“举例来说”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”、“例如”或者“举例来说”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”、“例如”或者“举例来说”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，单独存在B，同时存在A和B这三种情况。另外，除非另有说明，术语“多个”的含义是指两个或两个以上。例如，多个系统是指两个或两个以上的系统，多个终端是指两个或两个以上的终端。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
可以理解的是，以上实施例仅用以说明本申请的技术方案，而对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种铁电存储阵列的读写电路，其特征在于，所述铁电存储阵列包括第一铁电存储单元；所述读写电路包括：
    灵敏放大器，耦合至所述第一铁电存储单元的第一位线和第一参考位线；
    连接所述灵敏放大器的第一电压切换电路，用于向所述灵敏放大器输出第一电压或者第二电压；
    连接所述灵敏放大器的第二电压切换电路，用于向所述灵敏放大器输出第三电压或第四电压；
    其中，所述第一电压＞所述第二电压＞所述第三电压＞所述第四电压；
    当所述第一位线上的电压高于所述第一参考位线上的电压时，所述灵敏放大器用于向所述第一位线输出所述第一电压或者所述第二电压，向所述第一参考位线输出所述第三电压或者所述第四电压。
  2. 根据权利要求1所述的读写电路，其特征在于，当所述第一位线上的电压低于所述第一参考位线上的电压时，所述灵敏放大器用于向所述第一参考位线输出所述第一电压或者所述第二电压，向所述第一位线输出所述第三电压或者所述第四电压。
  3. 根据权利要求1或2所述的读写电路，其特征在于，
    当所述第一电压切换电路用于向所述灵敏放大器输出所述第一电压时，所述第二电压切换电路用于向所述灵敏放大器输出所述第四电压；
    当所述第一电压切换电路用于向所述灵敏放大器输出所述第二电压时，所述第二电压切换电路用于向所述灵敏放大器输出所述第三电压。
  4. 根据权利要求1-3任一项所述的读写电路，其特征在于，所述第一电压为所述第一铁电存储单元的写电压Vw，所述第四电压为所述第一铁电存储单元的零电压V0。
  5. 根据权利要求1-4任一项所述的读写电路，其特征在于，
    所述第一电压切换电路包括第一晶体管和第二晶体管；其中，所述第一晶体管的第一极连接所述灵敏放大器，第二极连接第一驱动电路；所述第二晶体管的第一极连接所述灵敏放大器，第二极连接第二驱动电路；其中，当所述第一晶体管导通时，所述第一驱动电路用于通过所述第一晶体管向所述灵敏放大器输出所述第一电压；当所述第二晶体管导通时，所述第二驱动电路用于通过所述第二晶体管向所述灵敏放大器输出所述第二电压；
    所述第二电压切换电路包括第三晶体管和第四晶体管；其中，所述第三晶体管的第一极连接所述灵敏放大器，第二极连接第三驱动电路；所述第四晶体管的第一极连接所述灵敏放大器，第二极连接第四驱动电路；其中，当所述第三晶体管导通时，所述第三驱动电路用于通过所述第三晶体管向所述灵敏放大器输出所述第三电压；当所述第四晶体管导通时，所述第四驱动电路用于通过所述第四晶体管向所述灵敏放大器输出所述第四电压。
  6. 根据权利要求1-5任一项所述的读写电路，其特征在于，所述第一电压切换电路用于向所述灵敏放大器的第一线路输出所述第一电压或者所述第二电压，所述第二电压切换电路用于向所述灵敏放大器的第二线路输出所述第三电压或所述第四电压。
  7. 根据权利要求6所述的读写电路，其特征在于，所述第一线路为上拉信号布线，所述第二线路为下拉信号布线。
  8. 根据权利要求6或8所述的读写电路，其特征在于，所述灵敏放大器包括：第五晶体管、第六晶体管、第七晶体管、第八晶体管；其中，
    所述第一线路连接所述第七晶体管的第一极，以及连接所述第八晶体管的第一极；所述 第二线路连接所述第五晶体管的第一极，以及连接所述第六晶体管的第一极；
    所述第一位线连接所述第七晶体管的第二极，以及连接所述第六晶体管的栅极；所述第一参考位线连接所述第六晶体管的第二极，以及连接所述第七晶体管的栅极；
    其中，当所述第一位线上的电压高于所述第一参考位线上的电压时，所述第七晶体管导通，使得所述第一线路向所述第一位线输出所述第一电压或者所述第二电压；
    当所述第一线路向所述第一位线输出所述第一电压或所述第二电压时，所述第六晶体管导通，使得所述第二线路向所述第一参考位线输出所述第三电压或所述第四电压。
  9. 根据权利要求8所述的读写电路，其特征在于，所述第一位线连接所述第五晶体管的第二极，以及连接所述第八晶体管的栅极；所述第一参考位线连接所述第八晶体管的第二极，以及连接所述第五晶体管的栅极；
    当所述第一位线上的电压低于所述第一参考位线上的电压时，所述第八晶体管导通，使得所述第一线路向所述第一参考位线输出所述第一电压或者所述第二电压；
    当所述第一线路向所述第一参考位线施加所述第一电压或者所述第二电压时，所述第五晶体管导通，使得所述第二线路向所述第一位线输出所述第三电压或者所述第四电压。
  10. 根据权利要求1-9任一项所述的读写电路，其特征在于，所述铁电存储阵列还包括第二铁电存储单元；所述第二铁电存储单元和第一铁电存储单元连接不同的第一电极，连接同一第二电极；所述第二电极连接所述第一位线。
  11. 根据权利要求1-10任一项所述的读写电路，其特征在于，所述铁电存储阵列还包括第三铁电存储单元；所述第三铁电存储单元和所述第一铁电存储单元共用第一电极，且所述第三铁电存储单元的第二电极和所述第一铁电存储单元的第二电极分别通过不同的晶体管连接到所述第一位线。
  12. 根据权利要求1-11任一项所述的读写电路，其特征在于，所述读写电路还包括：
    均衡器，耦合至所述第一位线和所述第一参考位线；所述均衡器用于在不同时刻向所述第一位线输出不同的电压，以及在不同时刻向所述第一参考位线输出不同的电压。
  13. 一种铁电存储阵列的读写方法，其特征在于，所述铁电存储阵列包括第一铁电存储单元，所述方法应用于读写电路，所述读写电路包括灵敏放大器、第一电压切换电路、第二电压切换电路，所述灵敏放大器耦合至所述第一铁电存储单元的第一位线和第一参考位线；
    所述方法包括：
    所述第一电压切换电路向所述灵敏放大器输出第一电压或者第二电压，所述第二电压切换电路向所述灵敏放大器输出第三电压或第四电压；其中，所述第一电压＞所述第二电压＞所述第三电压＞所述第四电压；
    当所述第一位线上的电压高于所述第一参考位线上的电压时，所述灵敏放大器向所述第一位线输出所述第一电压或者所述第二电压，向所述第一参考位线输出所述第三电压或者所述第四电压。
  14. 根据权利要求13所述的方法，其特征在于，所述方法还包括：
    当所述第一位线上的电压低于所述第一参考位线上的电压时，所述灵敏放大器向所述第一参考位线输出所述第一电压或者所述第二电压，向所述第一参考位线输出所述第三电压或者所述第四电压。
  15. 根据权利要求13或14所述的方法，其特征在于，所述第一电压切换电路向所述灵敏放大器输出第一电压或者第二电压，所述第二电压切换电路向所述灵敏放大器输出第三电压或第四电压包括：
    所述第一电压切换电路向所述灵敏放大器输出所述第一电压，且所述第二电压切换电路向所述灵敏放大器输出第四电压；或者，
    所述第一电压切换电路向所述灵敏放大器输出所述第二电压时，且所述第二电压切换电路向所述灵敏放大器输出第三电压。
  16. 根据权利要求13-15任一项所述的方法，其特征在于，所述第一电压为所述第一铁电存储单元的写电压Vw，所述第四电压为所述第一铁电存储单元的零电压V0。
  17. 根据权利要求13-16任一项所述的方法，其特征在于，所述第一电压切换电路向所述灵敏放大器输出第一电压或者第二电压，所述第二电压切换电路向所述灵敏放大器输出第三电压或第四电压包括：
    所述第一电压切换电路向所述灵敏放大器的第一线路输出第一电压或者第二电压，所述第二电压切换电路向所述灵敏放大器的第二线路输出第三电压或第四电压。
  18. 根据权利要求17所述的方法，其特征在于，所述第一线路为上拉信号布线，所述第二线路为下拉信号布线。
  19. 根据权利要求13-18任一项所述的方法，其特征在于，所述铁电存储阵列还包括第二铁电存储单元；所述第二铁电存储单元的第一电极和所述第一铁电存储单元连接不同的第一电极，连接同一第二电极；所述第二电极连接所述第一位线。
  20. 根据权利要求13-19任一项所述的方法，其特征在于，所述铁电存储阵列还包括第三铁电存储单元；所述第三铁电存储单元和所述第一铁电存储单元共用第一电极，且所述第三铁电存储单元的第二电极和所述第一铁电存储单元的第二电极分别通过不同的晶体管连接到所述第一位线。
  21. 一种铁电存储器，其特征在于，包括权利要求1-12任一项所述的读写电路和铁电存储阵列。
PCT/CN2023/070639 2022-03-11 2023-01-05 读写电路、读写方法以及铁电存储器 WO2023169075A1 (zh)

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