WO2024001622A1 - 一种铁电存储器、铁电存储器的读出电路及读出方法 - Google Patents

一种铁电存储器、铁电存储器的读出电路及读出方法 Download PDF

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Publication number
WO2024001622A1
WO2024001622A1 PCT/CN2023/096131 CN2023096131W WO2024001622A1 WO 2024001622 A1 WO2024001622 A1 WO 2024001622A1 CN 2023096131 W CN2023096131 W CN 2023096131W WO 2024001622 A1 WO2024001622 A1 WO 2024001622A1
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Prior art keywords
voltage
ferroelectric memory
bit line
memory unit
transistor
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PCT/CN2023/096131
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English (en)
French (fr)
Inventor
徐亮
卜思童
刘晓真
方亦陈
高强
许俊豪
李文魁
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华为技术有限公司
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Publication of WO2024001622A1 publication Critical patent/WO2024001622A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G11C11/2255—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G11C11/2257—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods

Definitions

  • the present application relates to the technical field of ferroelectric memory, and in particular to a ferroelectric memory, a readout circuit and a readout method of the ferroelectric memory.
  • DRAM Dynamic Random Access Memory
  • storage unit storage unit
  • equalizer sense amplifier
  • the output modes of traditional DRAM mainly include: Folded Bit Line (FBL) output mode and Open Bit Line (Open Bit Line, OBL) output mode.
  • FBL Folded Bit Line
  • OBL Open Bit Line
  • the memory cells in DRAM store free charges, on the same word line (Word Line, WL), the bit line (Bit Line, BL) and the reference bit line can only have one memory cell. This will cause the DRAM to have a load mismatch problem connected to it, which will affect the accuracy of the data read by the sense amplifier.
  • the present application provides a ferroelectric memory, a readout circuit and a readout method of the ferroelectric memory, so as to accurately read or write the stored information in the ferroelectric memory using a sensitive amplifier.
  • the present application provides a readout circuit of a ferroelectric memory, including: a first switch tube, a second switch tube, an equalizer and a sense amplifier; the equalizer communicates with the first ferroelectric memory through a first bit line.
  • the first switch tube is connected to the equalizer and the sensitive amplifier respectively;
  • the equalizer is also connected to the second ferroelectric memory unit through a second bit line;
  • the second switch tube is connected to the The equalizer and the sensitive amplifier;
  • the first ferroelectric memory unit and the second ferroelectric memory unit share a first word line;
  • the first ferroelectric memory unit and the second ferroelectric memory unit are ferroelectric Any two ferroelectric memory cells in the electrical memory cell array;
  • the equalizer is used to balance the voltage between the first bit line and the second bit line;
  • the sensitive amplifier is used to respectively The voltages on the first bit line and the second bit line are amplified, so that the readout circuit reads or writes the storage information of the ferroelectric memory cells in the ferroelectric memory cell array.
  • this application disposes a first switch tube and a second switch tube between the equalizer and the sense amplifier, so that the first ferroelectric memory unit and the second ferroelectric memory unit can share the same word line, and thus When the transistor in the first ferroelectric memory unit and the transistor in the second ferroelectric memory unit are turned on at the same time, it can ensure that the load terminal connected to the ferroelectric memory is in a balanced state, so that the ferroelectric memory can be accurately read or written using a sensitive amplifier. Store information in memory.
  • both the first switch tube and the second switch tube are in a conductive state;
  • both the first switch tube and the second switch tube are in a closed state.
  • the first switch tube is in a conducting state, and the second switching tube is in a closed state;
  • the fourth stage the first switching tube and the second switching tube are both in a conducting state.
  • the present application can isolate the ferroelectric memory unit from the sensitive amplifier when reading out the stored information of the ferroelectric memory unit in the ferroelectric memory. , to avoid the interference problem of ferroelectric memory cells for a long time, and also to improve the accuracy of reading stored information.
  • the present application provides a ferroelectric memory, including: a ferroelectric memory cell array and the readout circuit described in the first aspect and any of its designs.
  • the first ferroelectric memory cell in the ferroelectric memory cell array includes a transistor and n capacitors; where n is a positive integer, the gate of the transistor is connected to the first word line, and the source of the transistor The first bit line is connected, the drain of the transistor is connected to the first floating gate, the first floating gate is also connected to one end of each capacitor, and the other end of each capacitor is connected to different board lines.
  • This application can increase the amount of data stored in the first ferroelectric memory unit by configuring the first ferroelectric memory unit to include a transistor and n capacitors. It is also possible to set a first floating gate node in the first ferroelectric memory unit, and then accurately adjust the voltage according to whether there is a conduction state between the first bit line and the first floating gate.
  • the present application provides a readout method of a ferroelectric memory, which is applied to the ferroelectric memory in the second aspect and any of the designs thereof.
  • the method includes: When the electric memory unit and the second ferroelectric memory unit share the first word line, when both the first switch tube and the second switch tube are in the on state in the first stage, an equalizer is used to balance the first ferroelectric memory unit. The voltage between the connected first bit line and the second bit line connected to the second ferroelectric memory unit; in the second stage, when both the first switch tube and the second switch tube are in a closed state, A sense amplifier is used to amplify the voltage on the first bit line and the second bit line respectively to determine the stored information in the first ferroelectric memory unit.
  • the first stage further includes: after adjusting the voltage of the first word line connected to the first ferroelectric memory unit to the first voltage, based on the connection of the first ferroelectric memory unit
  • the second voltage of the first plate line determines the voltage of the first floating gate connected to the first ferroelectric memory unit; the equalizer is used to balance the first bit line and the voltage connected to the first ferroelectric memory unit.
  • the voltage between the second bit lines connected to the second ferroelectric memory unit includes: adjusting the first voltage of the first bit line and the third voltage of the second bit line according to the equalizer to be A fourth voltage; wherein the voltage values of the first voltage, the fourth voltage, the third voltage, and the second voltage increase in sequence.
  • the The first stage after using an equalizer to balance the voltage between the first bit line connected to the first ferroelectric memory unit and the second bit line connected to the second ferroelectric memory unit, the The first stage also includes: after adjusting the first voltage of the first word line to a fifth voltage, both the fourth voltage of the first bit line and the voltage of the first floating gate change; wherein, The fifth voltage is greater than the second voltage; in the second stage, a sensitive amplifier is used to amplify the voltages on the first bit line and the second bit line respectively to determine that the first ferroelectric
  • the storage information in the memory unit includes: based on the sensitive amplifier amplifying the changed voltage of the first bit line and the fourth voltage of the second bit line, determining the voltage in the first ferroelectric memory unit. Store information.
  • the method before determining the voltage of the first floating gate connected to the first ferroelectric memory unit based on the second voltage of the first plate line connected to the first ferroelectric memory unit, the method further includes: after adjusting the voltage of the first word line to the fifth voltage, adjusting the voltage of the first floating gate to the third voltage according to the first voltage of the first bit line.
  • this application uses the first voltage of the first bit line to make the first floating gate have an initial voltage, and then determines the first voltage through different storage information in the first ferroelectric memory unit. Floating gate voltage. After the first floating gate has an initial voltage, the voltage of the first floating gate can be adjusted more accurately. The voltage of the first floating gate determined separately according to different storage information in the ferroelectric memory unit is more accurate.
  • the equalizer includes a first transistor and a second transistor; the first transistor is used to control the voltage of the first bit line, and the second transistor is used to control the voltage of the second bit line. voltage; when the voltage of the first floating gate is adjusted to the first voltage according to the first voltage of the first bit line, the first transistor is in a conducting state and the second transistor is in a Disabled.
  • the voltage of the first floating gate can be made to be the first voltage with higher accuracy.
  • both the first transistor and the second transistor are in a conductive state.
  • the voltage of the first floating gate can be determined with higher accuracy.
  • the first transistor before adjusting the first voltage of the first word line to a fifth voltage, the first transistor is in a closed state; and before adjusting the first voltage of the first word line to a fifth voltage, the first transistor is in a closed state; After five voltages, the second transistor is off.
  • the gate voltage allows for more accurate charge sharing.
  • both the first transistor and the second transistor when determining the stored information in the first ferroelectric memory unit, both the first transistor and the second transistor are in a conductive state. At this time, both the first transistor and the second transistor are in the on state, and the first switch tube and the second switch tube are in the off state, so that when the stored information of the ferroelectric memory unit in the ferroelectric memory is read out, the ferroelectric The electrical storage unit is isolated from the sensitive amplifier to prevent the ferroelectric storage unit from enduring interference for a long time, and also improves the accuracy of reading the stored information.
  • the method further includes: in the third stage, when both the first transistor and the second transistor are in an off state, and the voltage of the first word line is the fifth voltage. , reducing the voltage of the first plate line to change the polarity state of the capacitor in the first ferroelectric memory unit.
  • the on-state and off-state of the first switch tube and the second switch tube, and the on-state and off-state of the first transistor and the second transistor it is possible to adjust only the polarity state of the capacitor in the first ferroelectric memory unit. , the polarity state of the capacitor in the second ferroelectric memory unit does not change.
  • the present application provides an electronic device, including a ferroelectric memory designed in any one of the second aspects and a circuit board, where the ferroelectric memory is disposed on the circuit board.
  • the present application provides a computer-readable storage medium that stores computer instructions.
  • the computer instructions are executed by the ferroelectric memory in the second aspect and any of its designs, the computer-readable storage medium can The ferroelectric memory in the second aspect and any design thereof is caused to perform the method of any design in the above-mentioned third aspect.
  • the present application provides a computer program product.
  • the computer program product includes computer instructions.
  • the computer instructions are executed by the ferroelectric memory in the second aspect and any of the designs thereof, the second aspect and the ferroelectric memory in any of the designs thereof can be made.
  • the ferroelectric memory in any of its designs performs the method of any of the designs in the third aspect.
  • Figure 1 is a schematic structural diagram of a readout circuit of a memory in the prior art
  • Figure 2 is a schematic structural diagram of a readout circuit of a ferroelectric memory provided by an embodiment of the present application
  • Figure 3 is a schematic structural diagram of the readout circuit of the ferroelectric memory when the first floating gate precharge voltage is provided by the embodiment of the present application;
  • Figure 4 is a schematic structural diagram of the readout circuit of the ferroelectric memory when redetermining the first floating gate voltage according to the embodiment of the present application;
  • Figure 5 is a schematic structural diagram of a readout circuit of a ferroelectric memory during charge sharing according to an embodiment of the present application
  • Figure 6 is a schematic structural diagram of the readout circuit of the ferroelectric memory when the sensitive amplifier provided by the embodiment of the present application amplifies the voltage;
  • Figure 7 is a schematic structural diagram of the readout circuit of the ferroelectric memory when reading or writing information stored in the first ferroelectric memory unit according to an embodiment of the present application;
  • Figure 8 is a schematic structural diagram of the readout circuit of the ferroelectric memory when restoring the polarity state of the capacitor in the first ferroelectric memory unit provided by the embodiment of the present application;
  • Figure 9 is a schematic structural diagram of the readout circuit of the ferroelectric memory in the standby state after completing the read and write operations provided by the embodiment of the present application;
  • Figure 10 is a schematic diagram of a circuit simulation waveform provided by an embodiment of the present application.
  • dynamic random access memory includes: storage unit, equalizer (Equalizer, EQ) and sense amplifier (Sense Amplifier, SA).
  • the output modes of traditional DRAM mainly include: folded bit line output mode and open bit line output mode.
  • the output mode of the folded bit line and the output mode of the open bit line since the memory cells in DRAM store free charges, there can only be one memory cell for the bit line and the reference bit line on the same word line. .
  • Figure 1 when there is a first memory cell between the first word line and the first bit line, there is no memory cell between the first word line and the second bit line, and the second bit line and the second bit line There is a second memory cell between the word lines. This will cause the DRAM to have a load mismatch problem connected to it, which will affect the accuracy of the data read by the sense amplifier.
  • SAN and SAP in Figure 1 respectively represent the low voltage and high voltage of the sense amplifier.
  • the functional implementation of EQ, CSL, and WE in Figure 1 will be described in detail below and will not be repeated here.
  • embodiments of the present application provide a ferroelectric memory, a readout circuit and a readout method of the ferroelectric memory.
  • the present application will be described in further detail below in conjunction with the accompanying drawings.
  • an embodiment of the present application provides a readout circuit of a ferroelectric memory, including: a first switch tube, a second switch tube, an equalizer and a sense amplifier.
  • the equalizer is connected to the first ferroelectric memory unit through the first bit line
  • the first switch tube is connected to the equalizer and the sensitive amplifier respectively
  • the equalizer is also connected to the second ferroelectric memory unit through the second bit line
  • the second switch The tubes are connected to the equalizer and sensitivity amplifier respectively.
  • the first ferroelectric memory unit and the second ferroelectric memory unit share the first word line.
  • the first ferroelectric memory unit and the second ferroelectric memory unit are any two ferroelectric memory cells in the ferroelectric memory cell array.
  • the equalizer includes a first transistor and a second transistor, and the source of the first transistor is connected to the drain of the second transistor.
  • the drain of the first transistor is connected to the first bit line, and the source of the second transistor is connected to the second bit line.
  • the voltage between the first bit line and the second bit line can be balanced through an equalizer.
  • the sense amplifier includes two inverters, and the two inverters are connected end to end.
  • One inverter may include a P-type transistor and an N-type transistor, and the gate of the P-type transistor is connected to the gate of the N-type transistor.
  • SAN and SAP represent the low voltage and high voltage of the sensitive amplifier respectively.
  • the sense amplifier can be used to amplify the voltages on the first bit line and the second bit line respectively, so that the readout circuit can read or write the storage information of the ferroelectric memory cells in the ferroelectric memory cell array.
  • a first switch tube and a second switch tube are arranged between the equalizer and the sense amplifier, so that the first ferroelectric memory unit and the second ferroelectric memory unit can share the same word line, and thus the first ferroelectric memory unit
  • the transistor in the ferroelectric memory unit and the transistor in the second ferroelectric memory unit are turned on at the same time, it can be ensured that the load end connected to the ferroelectric memory is in a balanced state, so that the sensitive amplifier can be used to accurately read or write the stored information in the ferroelectric memory.
  • the first ferroelectric memory unit in the ferroelectric memory cell array includes one transistor and n capacitors, for example, represented by 1TnC (One Transistor and one Capacitors).
  • 1TnC One Transistor and one Capacitors
  • the gate of the transistor is connected to the first word line
  • the source of the transistor is connected to the first bit line
  • the drain of the transistor is connected to the first floating gate (FG)
  • the first floating gate is also One end of each capacitor is connected
  • the other end of each capacitor is connected to the first plate line, the second plate line, ..., and the nth plate line.
  • each capacitor is connected in parallel.
  • first ferroelectric memory cell in the ferroelectric memory cell array is only an example of the first ferroelectric memory cell in the ferroelectric memory cell array, and this application does not limit the specific structure of the first ferroelectric memory cell.
  • the stored information of the ferroelectric memory cells in the ferroelectric memory cell array can be accurately processed. Read or write.
  • an embodiment of the present application also provides a ferroelectric memory, including: a ferroelectric memory cell array, a first switch tube, a second switch tube, an equalizer and a sense amplifier.
  • a ferroelectric memory including: a ferroelectric memory cell array, a first switch tube, a second switch tube, an equalizer and a sense amplifier.
  • the connection relationship between each device can refer to the connection relationship shown in Figure 2, which will not be described again.
  • the ferroelectric memory may be Ferroelectric Random Access Memory (FeRAM).
  • the second ferroelectric memory unit in the ferroelectric memory cell array serves as the reference ferroelectric memory unit of the first ferroelectric memory unit, and
  • the second ferroelectric memory cell and the first ferroelectric memory cell share the same word line.
  • the initial voltage of the first word line connected to the first ferroelectric memory cell is V0
  • the initial voltage of the first plate line is V1
  • the initial voltage of the first bit line is V1
  • the second bit line connected to the second ferroelectric memory cell The initial voltage is V1.
  • the second switch tubes are all in a conductive state.
  • V0 is smaller than V1
  • V0 can be 0V
  • V1 can be 1V. This is just an example.
  • the initial voltage of the first word line is adjusted, that is, the initial voltage V0 of the first word line is adjusted to V2.5.
  • the first bit line and the first floating gate are in a conductive state
  • the second bit line and the second floating gate are in a conductive state.
  • the first transistor in the equalizer to the on state and the second transistor to the off state
  • the first ferroelectric memory unit and the second ferroelectric memory unit are in the off state. That is, the voltage of the first bit line can be transferred to the first floating gate, and the voltage of the second bit line can be transferred to the second floating gate, but there is no difference between the voltage of the first bit line and the voltage of the second bit line. pass each other. Therefore, in order to ensure that there is a voltage difference across the capacitor of the first ferroelectric memory unit in subsequent steps, the initial voltage V0 can be provided to the first floating gate first.
  • V2.5 can be 2.5V, which is just an example.
  • V2 can be 2V, which is just an example.
  • the first ferroelectric memory unit contains the first storage information "1", and both ends of the capacitor in the first ferroelectric memory unit are in a negative polarization state, the voltage V2 of the first plate line is greater than the first floating gate
  • the voltage of the gate is V0
  • the polarization state of the capacitor in the first ferroelectric memory unit will change, that is, from negative polarization to The state changes to the positive polarization state.
  • the charge on the capacitor in the first ferroelectric memory unit will be transferred to the first floating gate, so that the voltage of the first floating gate is adjusted from V0 to Vfg1.
  • the first ferroelectric memory unit contains the second storage information "0"
  • both ends of the capacitor in the first ferroelectric memory unit are in a positive polarization state
  • the voltage V2 of the first plate line is greater than the voltage V0 of the first floating gate.
  • the polarization state of the capacitor in the first ferroelectric memory unit will not change.
  • a small amount of charge on the capacitor in the first ferroelectric memory unit is transferred to the first floating gate, so that the voltage of the first floating gate is adjusted from V0 to Vfg0.
  • the first transistor and the second transistor in the equalizer can also be set to a conductive state, and the equalizer is used to combine the voltage V0 of the first bit line and the voltage V0 of the second bit line.
  • Voltage V1 is adjusted to Vref. By performing the above two steps simultaneously, the processing speed can be increased.
  • Vref is greater than V0 and less than V1.
  • the first transistor of the equalizer is in the off state before adjusting the voltage of the first word line
  • the second transistor of the equalizer is in the off state after adjusting the voltage of the first word line. This allows the voltage of the second floating gate to be adjusted to Vref according to the voltage Vref of the second bit line.
  • the capacitance CBL of the first bit line and the capacitance Cfg of the first floating gate can share charges.
  • the voltage of the first bit line and the voltage of the first floating gate are both adjusted to Vrd1 or Vrd0.
  • the voltage of the second bit line and the voltage of the second floating gate are both Vref.
  • the voltage of the first bit line is Vrd1
  • the voltage of the second bit line is Vref.
  • Vref is less than Vrd1
  • the voltage of the first bit line and the voltage of the second bit line are amplified to V2 and V0 respectively through the sense amplifier.
  • the voltage of the first bit line is Vrd0 and the voltage of the second bit line is Vref, Assuming that Vref is greater than Vrd0, the voltage of the first bit line and the voltage of the second bit line are amplified to V0 and V2 respectively through the sense amplifier.
  • the voltage of the first bit line and the voltage of the second bit line are always driven at V2 and V0 through the sense amplifier, or the voltage of the first bit line and the voltage of the second bit line are driven through the sense amplifier.
  • the stored information in the first ferroelectric storage unit can be read or written.
  • the first floating gate and the first bit line are in a conductive state, and the voltage of the first floating gate is also V0 or V2. Since the voltage of the first plate line is V1, in order to reduce the interference effect caused by the different pressures at both ends of the capacitor of the first ferroelectric memory unit, the first switch tube and the second switch tube are turned off, and the first transistor and the second switch tube in the equalizer are Two transistors are turned on.
  • the equalizer is used to adjust the voltage of the first bit line, the voltage of the first floating gate, the voltage of the second bit line and the voltage of the second floating gate to V1, thereby reducing the capacitor of the first ferroelectric memory unit. Interference effects caused by different pressures at both ends.
  • both the first transistor and the second transistor in the equalizer are in a conductive state, and the first switch tube and the second switch tube are turned on.
  • the tubes are all in conductive state. Adjust the voltage of the first plate line from V0 to V1, and use an equalizer to adjust both the voltage of the first bit line and the voltage of the second bit line to V1. Since the first bit line and the first floating gate are in a conductive state, the voltage of the first floating gate is also V1. At this time, the voltage difference across the capacitor of the first ferroelectric memory unit is 0, and the polarity state does not change.
  • Figure 2 also shows the connection relationship between the second word line, the third ferroelectric memory unit, and the fourth ferroelectric memory unit.
  • the electrical storage unit will not be described in detail here.
  • the Write Enable (WE) in Figure 2 can be used to write storage information into the ferroelectric memory cell, and the current steering logic (CSL) can be used to control the current in the readout circuit of the ferroelectric memory. .
  • An embodiment of the present application also provides an electronic device, including the above-described ferroelectric memory and a circuit board, where the ferroelectric memory is disposed on the circuit board.
  • Embodiments of the present application also provide a computer-readable storage medium.
  • the computer-readable storage medium stores computer instructions. When the computer instructions are executed by the ferroelectric memory, the above reading method of the ferroelectric memory can be executed.
  • An embodiment of the present application also provides a computer program product, which includes computer instructions.
  • the computer instructions are executed by a ferroelectric memory, the above reading method of the ferroelectric memory can be executed.
  • various aspects of the method provided by the present application can also be implemented in the form of a program product, which includes program code.
  • program code When the program code is run on a computer device or a circuit product, the program code is used to cause the computer device to execute The steps in the readout method of the ferroelectric memory described above in this specification.
  • embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present application may employ a computer program product implemented on one or more computer-usable storage media (including, but not limited to, magnetic disk ferroelectric memory, CD-ROM, optical ferroelectric memory, etc.) embodying computer-usable program code therein. form.
  • computer-usable storage media including, but not limited to, magnetic disk ferroelectric memory, CD-ROM, optical ferroelectric memory, etc.
  • These computer program instructions may also be stored in a computer-readable ferroelectric memory capable of directing a computer or other programmable data processing apparatus to operate in a particular manner, such that generation of the instructions stored in the computer-readable ferroelectric memory includes the manufacture of the instruction means product, the instruction device implements the function specified in one process or multiple processes in the flow chart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

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Abstract

本申请提供一种铁电存储器、铁电存储器的读出电路及读出方法，其中读出电路包括第一开关管、第二开关管、均衡器和灵敏放大器。均衡器通过第一位线与第一铁电存储单元连接，均衡器还通过第二位线与第二铁电存储单元连接，第一开关管和第二开关管分别连接均衡器和灵敏放大器，第一铁电存储单元和第二铁电存储单元共用第一字线。通过在均衡器和灵敏放大器之间设置第一开关管和第二开关管，这样可以使得第一铁电存储单元和第二铁电存储单元共用同一字线，进而第一铁电存储单元中的晶体管和第二铁电存储单元中的晶体管同时导通时，可以保证铁电存储器连接的负载端处于均衡状态，从而可以利用灵敏放大器准确读出或写入铁电存储器中的存储信息。

Description

一种铁电存储器、铁电存储器的读出电路及读出方法
相关申请的交叉引用
本申请要求在2022年06月27日提交中国专利局、申请号为202210744834.8、申请名称为“一种铁电存储器、铁电存储器的读出电路及读出方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及铁电存储器技术领域，尤其涉及一种铁电存储器、铁电存储器的读出电路及读出方法。
背景技术
目前，动态随机存取存储器(Dynamic Random Access Memory，DRAM)包括：存储单元、均衡器和灵敏放大器。传统DRAM的输出方式主要包括：折叠式位线(Folded Bit Line，FBL)的输出方式和开放式位线(Open Bit Line，OBL)的输出方式。
针对折叠式位线的输出方式和开放式位线的输出方式来说，由于DRAM中的存储单元存储的是自由电荷，因此在同一字线(Word Line，WL)上，位线(Bit Line，BL)和参考位线只能有一个存储单元。这样会导致DRAM出现连接的负载不匹配问题，进而影响灵敏放大器读取数据的准确性。
发明内容
有鉴于此，本申请提供一种铁电存储器、铁电存储器的读出电路及读出方法，以便于利用灵敏放大器准确读出或写入铁电存储器中的存储信息。
第一方面，本申请提供一种铁电存储器的读出电路，包括：第一开关管、第二开关管、均衡器和灵敏放大器；所述均衡器通过第一位线与第一铁电存储单元连接；所述第一开关管分别连接所述均衡器和所述灵敏放大器；所述均衡器还通过第二位线与第二铁电存储单元连接；所述第二开关管分别连接所述均衡器和所述灵敏放大器；所述第一铁电存储单元和所述第二铁电存储单元共用第一字线；所述第一铁电存储单元和所述第二铁电存储单元为铁电存储单元阵列中任意两个铁电存储单元；所述均衡器，用于平衡所述第一位线和所述第二位线之间的电压；所述灵敏放大器，用于分别对所述第一位线和所述第二位线上的电压进行放大，以使所述读出电路对所述铁电存储单元阵列中的铁电存储单元的存储信息进行读出或写入。
相对于现有技术，本申请通过在均衡器和灵敏放大器之间设置第一开关管和第二开关管，这样可以使得第一铁电存储单元和第二铁电存储单元共用同一字线，进而第一铁电存储单元中的晶体管和第二铁电存储单元中的晶体管同时导通时，可以保证铁电存储器连接的负载端处于均衡状态，从而可以利用灵敏放大器准确读出或写入铁电存储器中的存储信息。
一种可能的设计中，在第一阶段，所述第一开关管和所述第二开关管均为导通状态； 在第二阶段，所述第一开关管和所述第二开关管均为关闭状态。在第三阶段，所述第一开关管处于导通状态，所述第二开关管处于关闭状态；在第四阶段，所述第一开关管和所述第二开关管均为导通状态。
本申请通过控制第一开关管、第二开关管处于导通状态或者关闭状态，可以使得在对铁电存储器中铁电存储单元的存储信息进行读出时，将铁电存储单元与灵敏放大器进行隔离，避免铁电存储单元承受较长时间的干扰问题，也提高了读出存储信息的准确度。
第二方面，本申请提供一种铁电存储器，包括：铁电存储单元阵列和第一方面及其任一设计中所述的读出电路。
一种可能的设计中，所述铁电存储单元阵列中第一铁电存储单元包括一个晶体管和n个电容器；其中，n为正整数，晶体管的栅极连接第一字线，晶体管的源极连接第一位线，晶体管的漏极连接第一浮动栅门，所述第一浮动栅门还连接每个电容器的一端，每个电容器的另一端分别连接不同板线。
本申请通过将第一铁电存储单元设置为包括一个晶体管和n个电容器，可以增加第一铁电存储单元的存储数据量。还可以在第一铁电存储单元中设置第一浮动栅门节点，进而根据第一位线和第一浮动栅门之间是否导通状态对电压进行准确的调整。
第三方面，本申请提供一种铁电存储器的读出方法，应用于如第二方面及其任一设计中的铁电存储器，所述方法包括：在铁电存储单元阵列中的第一铁电存储单元和第二铁电存储单元共用第一字线情况下，第一阶段中第一开关管和第二开关管均为导通状态时，利用均衡器平衡所述第一铁电存储单元连接的第一位线和所述第二铁电存储单元连接的第二位线之间的电压；在第二阶段中所述第一开关管和所述第二开关管均为关闭状态时，利用灵敏放大器分别对所述第一位线和所述第二位线上的电压进行放大，确定所述第一铁电存储单元中的存储信息。
一种可能的设计中，所述第一阶段，还包括：将所述第一铁电存储单元连接的第一字线的电压调整为第一电压后，基于所述第一铁电存储单元连接的第一板线的第二电压，确定所述第一铁电存储单元连接的第一浮动栅门的电压；所述利用均衡器平衡所述第一铁电存储单元连接的第一位线和所述第二铁电存储单元连接的第二位线之间的电压，包括：根据所述均衡器调整所述第一位线的第一电压和所述第二位线的第三电压均为第四电压；其中，所述第一电压、所述第四电压、所述第三电压、所述第二电压的电压值依次增大。
一种可能的设计中，在利用均衡器平衡所述第一铁电存储单元连接的第一位线和所述第二铁电存储单元连接的第二位线之间的电压后，所述第一阶段还包括：将所述第一字线的第一电压调整为第五电压后，所述第一位线的第四电压和所述第一浮动栅门的电压均发生变化；其中，所述第五电压大于所述第二电压；所述第二阶段中所述利用灵敏放大器分别对所述第一位线和所述第二位线上的电压进行放大，确定所述第一铁电存储单元中的存储信息，包括：基于所述灵敏放大器对变化后所述第一位线的电压和所述第二位线的第四电压进行放大，确定所述第一铁电存储单元中的存储信息。
一种可能的设计中，在所述基于所述第一铁电存储单元连接的第一板线的第二电压，确定所述第一铁电存储单元连接的第一浮动栅门的电压之前，所述方法还包括：将所述第一字线的电压调整为所述第五电压后，根据所述第一位线的第一电压，调整所述第一浮动栅门的电压为所述第一电压；所述基于所述第一铁电存储单元连接的第一板线的第二电压，确定所述第一铁电存储单元连接的第一浮动栅门的电压，包括：若所述第一铁电存储单元 中包含第一存储信息，则所述第一浮动栅门的电压由所述第一电压变更为第六电压；若所述第一铁电存储单元中包含第二存储信息，则所述第一浮动栅门的电压由所述第一电压变更为第七电压；其中，所述第六电压、所述第四电压、所述第七电压的电压值依次减少，所述第一存储信息和所述第二存储信息为不同的存储信息。
本申请在确定第一浮动栅门的电压之前，利用第一位线的第一电压使得第一浮动栅门具有一个初始电压，然后通过第一铁电存储单元中不同的存储信息分别确定第一浮动栅门的电压。在第一浮动栅门具有初始电压后，可以更准确的对第一浮动栅门的电压进行调整。根据铁电存储单元中不同的存储信息分别确定的第一浮动栅门的电压更准确。
一种可能的设计中，均衡器包括第一晶体管和第二晶体管；所述第一晶体管用于控制所述第一位线的电压，所述第二晶体管用于控制所述第二位线的电压；所述根据所述第一位线的第一电压，调整所述第一浮动栅门的电压为所述第一电压时，所述第一晶体管处于导通状态、所述第二晶体管处于关闭状态。通过均衡器中第一晶体管的导通状态和第二晶体管的关闭状态，可以使得第一浮动栅门的电压为第一电压的准确度更高。
一种可能的设计中，所述确定所述第一铁电存储单元连接的第一浮动栅门的电压时，所述第一晶体管和所述第二晶体管均处于导通状态。通过均衡器中第一晶体管的导通状态和第二晶体管的导通状态，可以使得确定的第一浮动栅门的电压的准确度更高。
一种可能的设计中，在将所述第一字线的第一电压调整为第五电压之前，所述第一晶体管处于关闭状态；在将所述第一字线的第一电压调整为第五电压之后，所述第二晶体管处于关闭状态。通过在第一位线和第一浮动栅门之间导通的前后时刻，确定第一晶体管和第二晶体管的导通状态、关闭状态，以便于第一位线的第四电压和第一浮动栅门的电压更准确的进行电荷共享。
一种可能的设计中，在确定所述第一铁电存储单元中的存储信息时，所述第一晶体管和所述第二晶体管均处于导通状态。通过此时第一晶体管和第二晶体管均处于导通状态、第一开关管和第二开关管处于关闭状态，可以使得在对铁电存储器中铁电存储单元的存储信息进行读出时，将铁电存储单元与灵敏放大器进行隔离，避免铁电存储单元承受较长时间的干扰问题，也提高了读出存储信息的准确度。
一种可能的设计中，所述方法还包括：在第三阶段中所述第一晶体管和所述第二晶体管均处于关闭状态、以及所述第一字线的电压为所述第五电压时，降低所述第一板线的电压，以改变所述第一铁电存储单元中电容极性状态。通过第一开关管和第二开关管的导通状态、关闭状态，以及第一晶体管和第二晶体管的导通状态、关闭状态，可以使得只调整第一铁电存储单元中电容的极性状态，第二铁电存储单元中电容的极性状态不发生改变。
第四方面，本申请提供一种电子设备，包括第二方面中任一设计的铁电存储器和电路板，所述铁电存储器设置于所述电路板上。
第五方面，本申请提供一种计算机可读存储介质，所述计算机可读存储介质存储有计算机指令，当所述计算机指令被第二方面及其任一设计中的铁电存储器执行时，可以使得第二方面及其任一设计中的铁电存储器执行上述第三方面中任一设计的方法。
第六方面，本申请提供一种计算机程序产品，所述计算机程序产品包括计算机指令，当所述计算机指令被第二方面及其任一设计中的铁电存储器执行时，可以使得第二方面及其任一设计中的铁电存储器执行上述第三方面中任一设计的方法。
附图说明
图1为现有技术中存储器的读出电路的结构示意图；
图2为本申请实施例提供的铁电存储器的读出电路的结构示意图；
图3为本申请实施例提供的第一浮动栅门预充电压时，铁电存储器的读出电路的结构示意图；
图4为本申请实施例提供的重新确定第一浮动栅门电压时，铁电存储器的读出电路的结构示意图；
图5为本申请实施例提供的电荷共享时，铁电存储器的读出电路的结构示意图；
图6为本申请实施例提供的灵敏放大器对电压进行放大时，铁电存储器的读出电路的结构示意图；
图7为本申请实施例提供的读取或写入第一铁电存储单元中存储信息时，铁电存储器的读出电路的结构示意图；
图8为本申请实施例提供的恢复第一铁电存储单元中电容器极性状态时，铁电存储器的读出电路的结构示意图；
图9为本申请实施例提供的完成读写操作后待命状态下，铁电存储器的读出电路的结构示意图；
图10为本申请实施例提供的电路仿真波形图示意图。
具体实施方式
为了使本领域普通人员更好地理解本申请的技术方案，下面将结合附图，对本申请实施例中的技术方案进行清楚、完整地描述。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应所述理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
目前，动态随机存取存储器包括：存储单元、均衡器(Equalizer，EQ)和灵敏放大器(Sense Amplifier，SA)。传统DRAM的输出方式主要包括：折叠式位线的输出方式和开放式位线的输出方式。针对折叠式位线的输出方式和开放式位线的输出方式来说，由于DRAM中的存储单元存储的是自由电荷，因此在同一字线上，位线和参考位线只能有一个存储单元。如图1所示，当第一字线与第一位线之间存在第一存储单元时，第一字线与第二位线之间是不存在存储单元的，第二位线与第二字线之间存在第二存储单元。这样会导致DRAM出现连接的负载不匹配问题，进而影响灵敏放大器读取数据的准确性。
这里，图1中的SAN、SAP分别表示灵敏放大器的低电压、高电压。图1中的EQ、CSL、WE的功能实现等在下面进行详细描述，在此不再赘述。
有鉴于此，本申请实施例提供了一种铁电存储器、铁电存储器的读出电路及读出方法。为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
如图2所示，本申请实施例提供的一种铁电存储器的读出电路，包括：第一开关管、第二开关管、均衡器和灵敏放大器。其中，均衡器通过第一位线与第一铁电存储单元连接，第一开关管分别连接均衡器和灵敏放大器，均衡器还通过第二位线与第二铁电存储单元连接，第二开关管分别连接均衡器和灵敏放大器。第一铁电存储单元和第二铁电存储单元共用第一字线，这里，第一铁电存储单元和第二铁电存储单元为铁电存储单元阵列中任意两个铁电存储单元。
可选的，均衡器包括第一晶体管和第二晶体管，第一晶体管的源极连接第二晶体管的漏极。第一晶体管的漏极连接第一位线，第二晶体管的源极连接第二位线，通过均衡器可以平衡第一位线和第二位线之间的电压。
灵敏放大器包括两个反向器，且两个反向器首尾相连，一个反向器可以包括一个P型晶体管和一个N型晶体管，并且P型晶体管的栅极和N型晶体管的栅极连接。SAN、SAP分别表示灵敏放大器的低电压、高电压。利用灵敏放大器可以分别对第一位线和第二位线上的电压进行放大，以使读出电路对铁电存储单元阵列中的铁电存储单元的存储信息进行读出或写入。
本申请通过在均衡器和灵敏放大器之间设置第一开关管和第二开关管，这样可以使得第一铁电存储单元和第二铁电存储单元共用同一字线，进而第一铁电存储单元中的晶体管和第二铁电存储单元中的晶体管同时导通时，可以保证铁电存储器连接的负载端处于均衡状态，从而可以利用灵敏放大器准确读出或写入铁电存储器中的存储信息。
可选的，如图2所示，铁电存储单元阵列中第一铁电存储单元包括一个晶体管和n个电容器，例如用1TnC(One Transistor and one Capacitors)表示。其中，n为正整数，晶体管的栅极连接第一字线，晶体管的源极连接第一位线，晶体管的漏极连接第一浮动栅门(Floating Gate，FG)，第一浮动栅门还连接每个电容器的一端，每个电容器的另一端分别连接第一板线、第二板线、…、第n板线。这里，每个电容器之间并联。通过将第一铁电存储单元设置为1TnC的结构，可以提高第一铁电存储单元的存储数据量。
应理解，在此仅是举例说明铁电存储单元阵列中的第一铁电存储单元，本申请并不限定第一铁电存储单元的具体结构。利用铁电存储单元比其他类型的存储单元需要提供的功耗小、读写速度快以及抗辐照能力强的优点，可以准确的对铁电存储单元阵列中的铁电存储单元的存储信息进行读出或写入。
一种可能的设计中，本申请实施例还提供了一种铁电存储器，包括：铁电存储单元阵列、第一开关管、第二开关管、均衡器和灵敏放大器。这里，每个器件之间的连接关系可参考图2中示出的连接关系，在此不再赘述。例如，铁电存储器可以是铁电随机存取存储器(Ferroelectric Random Access Memory，FeRAM)。
在介绍了本申请实施例提供的一种铁电存储器、铁电存储器的读出电路的连接关系后，接下来继续介绍本申请实施例提供的一种铁电存储器的读出方法，可以应用于上面描述的铁电存储器，具体包括以下步骤：
假设对铁电存储单元阵列中的第一铁电存储单元的存储信息进行读出，铁电存储单元阵列中的第二铁电存储单元作为第一铁电存储单元的参考铁电存储单元，且第二铁电存储单元与第一铁电存储单元共用同一字线。第一铁电存储单元连接的第一字线的初始电压为V0，第一板线的初始电压为V1，第一位线的初始电压为V1，第二铁电存储单元连接的第二位线的初始电压为V1。此时，均衡器中的第一晶体管和第二晶体管、以及第一开关管、 第二开关管均为导通状态。这里，V0小于V1，V0可以是0V，V1可以是1V，在此仅是举例说明。
首先，如图3所示，调整第一字线的初始电压，也即将第一字线的初始电压V0调整为V2.5。此时，第一位线和第一浮动栅门之间处于导通状态，第二位线和第二浮动栅门之间处于导通状态。通过将均衡器中的第一晶体管设置为导通状态，第二晶体管设置为关闭状态，使得第一铁电存储单元与第二铁电存储单元之间处于关闭状态。也即第一位线的电压可以传递至第一浮动栅门，第二位线的电压可以传递至第二浮动栅门，但是第一位线的电压与第二位线的电压之间不会互相传递。因此为了保证后续步骤中第一铁电存储单元的电容器两端存在电压差，可以先给第一浮动栅门提供初始电压V0。这里，V2.5可以是2.5V，在此仅是举例说明。
其次，如图4所示，继续调整第一字线的电压，也即将第一字线的电压V2.5调整为V0。此时，第一位线和第一浮动栅门之间处于关闭状态，第二位线和第二浮动栅门之间处于关闭状态。在将第一板线(Plate Line，PL)的初始电压V1调整为V2后，根据第一板线的电压V2、第一浮动栅门的电压V0以及第一铁电存储单元的存储信息，重新确定第一浮动栅门的电压。这里，V2可以是2V，在此仅是举例说明。
示例性的，若第一铁电存储单元中包含第一存储信息“1”，且第一铁电存储单元中电容器的两端处于负极化状态，第一板线的电压V2大于第一浮动栅门的电压V0时，由于第一板线和第一浮动栅门之间的电压差为正极化状态下，则第一铁电存储单元中电容器的极化状态会发生改变，也即从负极化状态转变为正极化状态。在这个过程中，第一铁电存储单元中电容器上的电荷会传输至第一浮动栅门，使得第一浮动栅门的电压由V0调整为Vfg1。
若第一铁电存储单元中包含第二存储信息“0”，且第一铁电存储单元中电容器的两端处于正极化状态，第一板线的电压V2大于第一浮动栅门的电压V0时，由于第一板线和第一浮动栅门之间的电压差为正极化状态下，则第一铁电存储单元中电容器的极化状态不会发生改变。在这个过程中，第一铁电存储单元中电容器上的电荷会少量传输至第一浮动栅门，使得第一浮动栅门的电压由V0调整为Vfg0。
在重新确定第一浮动栅门的电压时，还可以将均衡器中的第一晶体管和第二晶体管均设置为导通状态，利用均衡器将第一位线的电压V0和第二位线的电压V1均调整为Vref。通过将上述两个步骤同时执行，可以提高处理速度。这里，Vref大于V0，小于V1。
然后，如图5所示，继续调整第一板线的电压和第一字线的电压，也即将第一板线的电压V2调整为V1，将第一字线的电压V0调整为V2.5。此时，均衡器的第一晶体管在调整第一字线的电压之前处于关闭状态，均衡器的第二晶体管在调整第一字线的电压之后处于关闭状态。这样可以使得根据第二位线的电压Vref，调整第二浮动栅门的电压为Vref。同时，第一位线的电容CBL和第一浮动栅门的电容Cfg可以进行电荷共享。例如通过以下公式一和公式二进行电荷共享：
Vfg1*Cfg+Vref*CBL＝Vrd1*(Cfg+CBL)    公式一
Vfg0*Cfg+Vref*CBL＝Vrd0*(Cfg+CBL)    公式二
在电荷共享结束后，第一位线的电压和第一浮动栅门的电压均调整为Vrd1或者Vrd0。此时，第二位线的电压和第二浮动栅门的电压均为Vref。如图6所示，当第一铁电存储单元中的存储信息为“1”，且对第一铁电存储单元进行存储信息的读取时，第一位线的电压 为Vrd1，第二位线的电压为Vref，假设Vref小于Vrd1，则通过灵敏放大器将第一位线的电压和第二位线的电压分别放大至V2和V0。当第一铁电存储单元中的存储信息为“0”，且对第一铁电存储单元进行存储信息的读取时，第一位线的电压为Vrd0，第二位线的电压为Vref，假设Vref大于Vrd0，则通过灵敏放大器将第一位线的电压和第二位线的电压分别放大至V0和V2。
如图7所示，通过灵敏放大器将第一位线的电压和第二位线的电压一直驱动在V2和V0情况下，或者通过灵敏放大器将第一位线的电压和第二位线的电压一直驱动在V0和V2情况下，可以对第一铁电存储单元中的存储信息进行读取或者写入。此时，第一浮动栅门与第一位线之间处于导通状态，第一浮动栅门的电压也为V0或者V2。由于第一板线的电压为V1，为了降低第一铁电存储单元的电容器两端压力不同导致的干扰影响，将第一开关管和第二开关管关闭，均衡器中的第一晶体管和第二晶体管导通。这样利用均衡器将第一位线的电压、第一浮动栅门的电压、第二位线的电压和第二浮动栅门的电压均调整为V1，进而可以降低第一铁电存储单元的电容器两端压力不同导致的干扰影响。
在对第一铁电存储单元的存储信息进行读取或者写入后，由于读取第一铁电存储单元的存储信息“1”情况下，对第一铁电存储单元中电容器的极性进行了改变，因此需要将电容器的极性恢复。如图8所示，为了保证仅对第一铁电存储单元的电容器极性进行改变，不改变第二铁电存储单元的电容器极性，将均衡器中的第一晶体管和第二晶体管均关闭，并且第一开关管处于导通状态，第二开关管处于关闭状态。此时，灵敏放大器将V2传输至第一位线和第一浮动栅门。通过进一步调整第一板线的电压，即将第一板线的电压V1调整为V0，第一铁电存储单元的电容器存在压差，使得第一铁电存储单元的电容器的极性可以恢复。
在对第一铁电存储单元的电容器极性进行恢复后，如图9所示，将均衡器中的第一晶体管和第二晶体管均处于导通状态，并且将第一开关管和第二开关管均处于导通状态。将第一板线的电压从V0调整为V1，利用均衡器将第一位线的电压和第二位线的电压均调整至V1。由于第一位线与第一浮动栅门之间处于导通状态，因此第一浮动栅门的电压也为V1。此时，第一铁电存储单元的电容器的两端压差为0，极性状态不发生改变。
最后，将第一字线的电压从V2.5调整为V0，第一位线的电压、第二位线的电压、第一板线的电压、第一浮动栅门的电压、第二浮动栅门的电压均为V1。此时，第一铁电存储单元的电容器的两端压差为0，极性状态不发生改变。如图10所示，示出了上述每个步骤对应的电路仿真波形图示意图。
另外，图2中还示出了第二字线、第三铁电存储单元、第四铁电存储单元的连接关系，功能实现可参考第一字线、第一铁电存储单元和第二铁电存储单元，在此不再赘述。图2中的写入使能(Write Enable，WE)可以用于铁电存储单元写入存储信息，电流控制逻辑(current steering logic，CSL)可以用于铁电存储器的读出电路中电流的控制。
本申请通过在均衡器和灵敏放大器之间设置开关管，利用开关管的导通状态和关闭状态，不仅可以恢复第一铁电存储单元的电容器极性，还可以在对第一铁电存储单元的存储信息进行读取或写入时降低电容器两端压力不同产生的干扰影响。进而解决对铁电存储单元进行信息存储时准确率较低的问题，减少功耗。
本申请实施例还提供一种电子设备，包括上述描述的铁电存储器和电路板，铁电存储器设置于电路板上。
本申请实施例还提供一种计算机可读存储介质，计算机可读存储介质存储有计算机指令，当计算机指令被铁电存储器执行时，可以使得上述铁电存储器的读出方法被执行。
本申请实施例还提供一种计算机程序产品，包括计算机指令，当计算机指令被铁电存储器执行时，可以使得上述铁电存储器的读出方法被执行。
也就是说，本申请提供的方法的各个方面还可以实现为一种程序产品的形式，其包括程序代码，当程序代码在计算机设备上或电路产品上运行时，程序代码用于使计算机设备执行本说明书上述描述的铁电存储器的读出方法中的步骤。
此外，尽管在附图中以特定顺序描述了本申请方法的操作，但是，这并非要求或者暗示必须按照该特定顺序来执行这些操作，或是必须执行全部所示的操作才能实现期望的结果。附加地或备选地，可以省略某些步骤，将多个步骤合并为一个步骤执行，和/或将一个步骤分解为多个步骤执行。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘铁电存储器、CD-ROM、光学铁电存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读铁电存储器中，使得存储在该计算机可读铁电存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (15)

  1. 一种铁电存储器的读出电路，其特征在于，包括：第一开关管、第二开关管、均衡器和灵敏放大器；
    所述均衡器通过第一位线与第一铁电存储单元连接；所述第一开关管分别连接所述均衡器和所述灵敏放大器；所述均衡器还通过第二位线与第二铁电存储单元连接；所述第二开关管分别连接所述均衡器和所述灵敏放大器；所述第一铁电存储单元和所述第二铁电存储单元共用第一字线；所述第一铁电存储单元和所述第二铁电存储单元为铁电存储单元阵列中任意两个铁电存储单元；
    所述均衡器，用于平衡所述第一位线和所述第二位线之间的电压；
    所述灵敏放大器，用于分别对所述第一位线和所述第二位线上的电压进行放大，以使所述读出电路对所述铁电存储单元阵列中的铁电存储单元的存储信息进行读出或写入。
  2. 如权利要求1所述的读出电路，其特征在于，在第一阶段，所述第一开关管和所述第二开关管均为导通状态；在第二阶段，所述第一开关管和所述第二开关管均为关闭状态。
  3. 如权利要求1或2所述的读出电路，其特征在于，在第三阶段，所述第一开关管处于导通状态，所述第二开关管处于关闭状态；在第四阶段，所述第一开关管和所述第二开关管均为导通状态。
  4. 一种铁电存储器，其特征在于，包括：铁电存储单元阵列和权利要求1-3任一所述的读出电路。
  5. 如权利要求4所述的铁电存储器，其特征在于，所述铁电存储单元阵列中第一铁电存储单元包括一个晶体管和n个电容器；其中，n为正整数，晶体管的栅极连接第一字线，晶体管的源极连接第一位线，晶体管的漏极连接第一浮动栅门，所述第一浮动栅门还连接每个电容器的一端，每个电容器的另一端分别连接不同板线。
  6. 一种电子设备，其特征在于，包括如权利要求4或5所述的铁电存储器和电路板，所述铁电存储器设置于所述电路板上。
  7. 一种铁电存储器的读出方法，其特征在于，应用于如权利要求4或5所述的铁电存储器，所述方法包括：
    在铁电存储单元阵列中的第一铁电存储单元和第二铁电存储单元共用第一字线情况下，第一阶段中第一开关管和第二开关管均为导通状态时，利用均衡器平衡所述第一铁电存储单元连接的第一位线和所述第二铁电存储单元连接的第二位线之间的电压；
    在第二阶段中所述第一开关管和所述第二开关管均为关闭状态时，利用灵敏放大器分别对所述第一位线和所述第二位线上的电压进行放大，确定所述第一铁电存储单元中的存储信息。
  8. 如权利要求7所述的读出方法，其特征在于，所述第一阶段，还包括：
    将所述第一铁电存储单元连接的第一字线的电压调整为第一电压后，基于所述第一铁电存储单元连接的第一板线的第二电压，确定所述第一铁电存储单元连接的第一浮动栅门的电压；
    所述利用均衡器平衡所述第一铁电存储单元连接的第一位线和所述第二铁电存储单元连接的第二位线之间的电压，包括：
    根据所述均衡器调整所述第一位线的第一电压和所述第二位线的第三电压均为第四电压；其中，所述第一电压、所述第四电压、所述第三电压、所述第二电压的电压值依次增大。
  9. 如权利要求8所述的读出方法，其特征在于，在利用均衡器平衡所述第一铁电存储单元连接的第一位线和所述第二铁电存储单元连接的第二位线之间的电压后，所述第一阶段还包括：
    将所述第一字线的第一电压调整为第五电压后，所述第一位线的第四电压和所述第一浮动栅门的电压均发生变化；其中，所述第五电压大于所述第二电压；
    所述第二阶段中所述利用灵敏放大器分别对所述第一位线和所述第二位线上的电压进行放大，确定所述第一铁电存储单元中的存储信息，包括：
    基于所述灵敏放大器对变化后所述第一位线的电压和所述第二位线的第四电压进行放大，确定所述第一铁电存储单元中的存储信息。
  10. 如权利要求8所述的读出方法，其特征在于，在所述基于所述第一铁电存储单元连接的第一板线的第二电压，确定所述第一铁电存储单元连接的第一浮动栅门的电压之前，所述方法还包括：
    将所述第一字线的电压调整为所述第五电压后，根据所述第一位线的第一电压，调整所述第一浮动栅门的电压为所述第一电压；
    所述基于所述第一铁电存储单元连接的第一板线的第二电压，确定所述第一铁电存储单元连接的第一浮动栅门的电压，包括：
    若所述第一铁电存储单元中包含第一存储信息，则所述第一浮动栅门的电压由所述第一电压变更为第六电压；若所述第一铁电存储单元中包含第二存储信息，则所述第一浮动栅门的电压由所述第一电压变更为第七电压；其中，所述第六电压、所述第四电压、所述第七电压的电压值依次减少，所述第一存储信息和所述第二存储信息为不同的存储信息。
  11. 如权利要求10所述的读出方法，其特征在于，所述均衡器包括第一晶体管和第二晶体管；所述第一晶体管用于控制所述第一位线的电压，所述第二晶体管用于控制所述第二位线的电压；
    所述根据所述第一位线的第一电压，调整所述第一浮动栅门的电压为所述第一电压时，所述第一晶体管处于导通状态、所述第二晶体管处于关闭状态。
  12. 如权利要求11所述的读出方法，其特征在于，所述确定所述第一铁电存储单元连接的第一浮动栅门的电压时，所述第一晶体管和所述第二晶体管均处于导通状态。
  13. 如权利要求11或12所述的读出方法，其特征在于，在将所述第一字线的第一电压调整为第五电压之前，所述第一晶体管处于关闭状态；在将所述第一字线的第一电压调整为第五电压之后，所述第二晶体管处于关闭状态。
  14. 如权利要求11-13任一所述的读出方法，其特征在于，在确定所述第一铁电存储单元中的存储信息时，所述第一晶体管和所述第二晶体管均处于导通状态。
  15. 如权利要求11-14任一所述的读出方法，其特征在于，所述方法还包括：
    在第三阶段中所述第一晶体管和所述第二晶体管均处于关闭状态、以及所述第一字线的电压为所述第五电压时，降低所述第一板线的电压，以改变所述第一铁电存储单元中电容极性状态。
PCT/CN2023/096131 2022-06-27 2023-05-24 一种铁电存储器、铁电存储器的读出电路及读出方法 WO2024001622A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1700473A (zh) * 2004-05-21 2005-11-23 松下电器产业株式会社 铁电体存储装置及其读出方法
CN1885428A (zh) * 2005-06-22 2006-12-27 精工爱普生株式会社 铁电存储装置
US20070036012A1 (en) * 2005-07-28 2007-02-15 Madan Sudhir K Stable source-coupled sense amplifier
CN105448322A (zh) * 2014-09-24 2016-03-30 拉碧斯半导体株式会社 铁电存储器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1700473A (zh) * 2004-05-21 2005-11-23 松下电器产业株式会社 铁电体存储装置及其读出方法
CN1885428A (zh) * 2005-06-22 2006-12-27 精工爱普生株式会社 铁电存储装置
US20070036012A1 (en) * 2005-07-28 2007-02-15 Madan Sudhir K Stable source-coupled sense amplifier
CN105448322A (zh) * 2014-09-24 2016-03-30 拉碧斯半导体株式会社 铁电存储器

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