JP7137477B2 - データキャッシング - Google Patents
データキャッシング Download PDFInfo
- Publication number
- JP7137477B2 JP7137477B2 JP2018555917A JP2018555917A JP7137477B2 JP 7137477 B2 JP7137477 B2 JP 7137477B2 JP 2018555917 A JP2018555917 A JP 2018555917A JP 2018555917 A JP2018555917 A JP 2018555917A JP 7137477 B2 JP7137477 B2 JP 7137477B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- memory cell
- read
- sense amplifier
- bank
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2253—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2253—Address circuits or decoders
- G11C11/2255—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2253—Address circuits or decoders
- G11C11/2257—Word-line or row circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2273—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2275—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
- G06F2212/1036—Life time enhancement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Description
本特許出願は、2017年4月25出願の「データキャッシング」という名称のPCT出願PCT/US2017/029420に対して優先権を主張する。さらに、そのPCT出願は、2016年4月27日出願の「データキャッシング」という名称のカジガヤによる米国特許出願15/140,073に対して優先権を主張する。各出願は本出願の譲受人に譲渡され、各出願は参照によりその全体が本明細書に組み込まれる。
Claims (16)
- メモリデバイスを動作させる方法であって、
第1のメモリセルの最初の読出しを実行するときに、ロウバッファのセンスアンプにおいて、メモリセルのバンクの前記第1のメモリセルから読み出された論理値をキャッシングすることであり、前記センスアンプは、前記第1のメモリセルに関連付けられたロウアドレスが前記メモリセルの前記バンクに対応するアドレスラッチにラッチされることに少なくとも部分的に基づいて、及び前記第1のメモリセルから読み出された前記論理値が前記ロウバッファの前記センスアンプにおいてキャッシングされることに少なくとも部分的に基づいて、前記第1のメモリセルから読み出された前記論理値を含むことと、
前記第1のメモリセルから読み出された前記論理値をキャッシングすることに少なくとも部分的に基づいて、前記第1のメモリセルの前記最初の読出しを実行した後に、前記第1のメモリセルの少なくとも2回目の読出しを実行することを決定することと、
第2のロウアドレスに関連付けられた1つ以上のメモリセル上でアクセス動作を実行した後に前記第1のメモリセルの少なくとも前記2回目の読出しのために、前記センスアンプから前記第1のメモリセルから読み出された前記論理値を読み出すことと、
を含む、備える方法。 - 少なくとも前記第1のメモリセルは強誘電体メモリセルを含む、請求項1に記載の方法。
- 前記第1のメモリセルは、破壊読出しモードで動作するように構成され、前記方法は、
前記センスアンプにおいて前記第1のメモリセルから読み出された前記論理値をキャッシングした後、前記第1のメモリセルから読み出された前記論理値を前記第1のメモリセルに書き戻すことを更に含む、
請求項2に記載の方法。 - 前記センスアンプにおいて前記第1のメモリセルから読み出された前記論理値をキャッシングする前に、絶縁ゲートを閉じ、前記第1のメモリセルが結合されているビットラインを前記センスアンプに結合することと、
前記第1のメモリセルから読み出された前記論理値を前記第1のメモリセルに書き戻した後に、前記絶縁ゲートを開いて、前記センスアンプから前記ビットラインを切り離すことと
を更に含む、請求項3に記載の方法。 - 前記第1のメモリセルから読み出された前記論理値は、前記絶縁ゲートが開いている間に、前記第1のメモリセルの少なくとも前記2回目の読出しのために、前記センスアンプから読み出される、請求項4に記載の方法。
- 前記絶縁ゲートを開いた後に、前記第1のメモリセルのセルプレートと同じ電圧に前記ビットラインをプリチャージすることを更に含む、請求項4に記載の方法。
- 前記センスアンプにおいて前記第1のメモリセルから読み出された前記論理値をキャッシングする前に、絶縁ゲートを閉じ、前記第1のメモリセルが結合されているビットラインを前記センスアンプに結合することと、
前記センスアンプにおいて前記第1のメモリセルから読み出された前記論理値をキャッシングした後に、前記絶縁ゲートを開き、前記センスアンプから前記ビットラインを切り離すことと
を更に含む、請求項1に記載の方法。 - 前記センスアンプにキャッシュされた前記第1のメモリセルから読み出された前記論理値を、前記センスアンプに結合された第2のメモリセルに書き込むことを更に含む、請求項1に記載の方法。
- 前記第1のメモリセルの前記2回目の読出しは、前記第1のメモリセルの前記最初の読出し後の前記第1のメモリセルの次の読出しを含む、請求項1に記載の方法。
- メモリサブシステムを動作させる方法であって、
各メモリバンクがロウバッファに関連付けられているメモリデバイスのメモリバンクの異なるグループに、マルチコアプロセッサのプロセスをマッピングすることと、
メモリバンク内のメモリアドレスに関連付けられた複数のメモリセルをアドレス指定して、データワードの読出しのための最初のメモリ読出し要求を受信したときに前記データワードを取得することであって、前記最初のメモリ読出し要求を受信したときに前記メモリアドレスの内のロウアドレスは前記メモリバンクに対応するアドレスラッチにラッチされることと、
前記プロセスから、前記メモリアドレスに関連付けられた、前記データワードの読出しのための少なくとも2回目のメモリ読出し要求を受信したときに、前記メモリバンクに関連付けられたロウバッファをアドレス指定して、前記データワードを取得することと
を含む、方法。 - 前記マルチコアプロセッサはコアを含み、前記メモリバンクの異なるグループに前記マルチコアプロセッサの前記プロセスをマッピングすることは、前記メモリバンクの異なるグループに前記マルチコアプロセッサの前記コアをマッピングすることに少なくとも部分的に基づく、請求項10に記載の方法。
- 前記2回目のメモリ読出し要求は、前記最初のメモリ読出し要求の後の前記複数のメモリセルの次の読出し要求を含む、請求項10に記載の方法。
- データプロセッサであり、前記データプロセッサは、マルチコアプロセッサを含み、前記マルチコアプロセッサは、主記憶内のメモリバンクの異なるグループに前記マルチコアプロセッサのプロセスをマッピングする、前記データプロセッサと、
前記主記憶と、
前記主記憶と前記データプロセッサの間でデータを転送するように構成されたメモリコントローラとを含み、
前記主記憶は、
複数のメモリバンクに配置された複数のメモリセルと、
前記メモリバンクから読み出された複数の論理値を一時的にキャッシングする動作が可能な複数のセンスアンプを含む、メモリバンクごとのロウバッファと、
前記メモリコントローラからメモリ読出し要求に関連付けられたメモリアドレスを受信することと、メモリバンクから前記メモリアドレスに関連付けられた前記複数の論理値を読み出すことと、前記ロウバッファの前記複数のセンスアンプのうちの少なくとも1つにおいて前記複数の論理値をキャッシングすることであり、前記メモリバンクから読み出された前記複数の論理値の前記メモリアドレスの内のロウアドレスは前記メモリバンクに対応するアドレスラッチにラッチされ、前記複数のセンスアンプは前記複数の論理値と、前記メモリバンクからの少なくとも1つのその他のメモリセルから読み出された論理値とを含むことと、前記メモリアドレスの前記ロウアドレスに関連付けられた次のメモリ読出し要求の受信時に、前記メモリバンクに関連付けられた前記ロウバッファの前記複数のセンスアンプから前記複数の論理値を読み出すこととの動作が可能であるコントローラと、
を含む、データ処理システム。 - 前記マルチコアプロセッサは、前記マルチコアプロセッサの前記プロセスを、前記メモリバンクの異なるグループへの前記マルチコアプロセッサのマッピングコアに少なくとも部分的に基づいて、前記メモリバンクの異なるグループにマップする動作が可能である、
請求項13に記載のデータ処理システム。 - 前記複数のメモリセルは、複数の強誘電体メモリセルを含む、請求項13に記載のデータ処理システム。
- 前記複数のメモリセルが破壊読出しモードで動作するように構成され、前記コントローラは、前記複数のセンスアンプにキャッシングされている前記複数の論理値を、前記複数の論理値が前記複数のセンスアンプにキャッシングされた後に、前記複数の論理値が読み出された前記メモリバンクに書き戻す動作が可能である、請求項15に記載のデータ処理システム。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2021113929A JP2021168225A (ja) | 2016-04-27 | 2021-07-09 | データキャッシング |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/140,073 US10082964B2 (en) | 2016-04-27 | 2016-04-27 | Data caching for ferroelectric memory |
US15/140,073 | 2016-04-27 | ||
PCT/US2017/029420 WO2017189579A2 (en) | 2016-04-27 | 2017-04-25 | Data caching |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021113929A Division JP2021168225A (ja) | 2016-04-27 | 2021-07-09 | データキャッシング |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019515409A JP2019515409A (ja) | 2019-06-06 |
JP7137477B2 true JP7137477B2 (ja) | 2022-09-14 |
Family
ID=60158303
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018555917A Active JP7137477B2 (ja) | 2016-04-27 | 2017-04-25 | データキャッシング |
JP2021113929A Pending JP2021168225A (ja) | 2016-04-27 | 2021-07-09 | データキャッシング |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021113929A Pending JP2021168225A (ja) | 2016-04-27 | 2021-07-09 | データキャッシング |
Country Status (6)
Country | Link |
---|---|
US (3) | US10082964B2 (ja) |
EP (1) | EP3449376A4 (ja) |
JP (2) | JP7137477B2 (ja) |
KR (3) | KR20200104432A (ja) |
CN (2) | CN113127379B (ja) |
WO (1) | WO2017189579A2 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10082964B2 (en) | 2016-04-27 | 2018-09-25 | Micron Technology, Inc | Data caching for ferroelectric memory |
KR102548599B1 (ko) * | 2016-06-17 | 2023-06-29 | 삼성전자주식회사 | 버퍼메모리를 포함하는 메모리 장치 및 이를 포함하는 메모리 모듈 |
KR102630116B1 (ko) * | 2016-10-18 | 2024-01-29 | 에스케이하이닉스 주식회사 | 데이터 저장 장치 및 그것의 동작 방법 |
US10217494B2 (en) * | 2017-06-28 | 2019-02-26 | Apple Inc. | Global bit line pre-charging and data latching in multi-banked memories using a delayed reset latch |
EP3662474B1 (en) * | 2017-07-30 | 2023-02-22 | NeuroBlade Ltd. | A memory-based distributed processor architecture |
US10403347B2 (en) | 2018-01-29 | 2019-09-03 | Micron Technology, Inc. | Apparatuses and methods for accessing ferroelectric memory including providing reference voltage level |
US10636469B2 (en) * | 2018-05-09 | 2020-04-28 | Micron Technology, Inc. | Cell voltage accumulation discharge |
US10636459B2 (en) * | 2018-05-30 | 2020-04-28 | Micron Technology, Inc. | Wear leveling |
US11360704B2 (en) | 2018-12-21 | 2022-06-14 | Micron Technology, Inc. | Multiplexed signal development in a memory device |
US11373695B2 (en) * | 2019-12-18 | 2022-06-28 | Micron Technology, Inc. | Memory accessing with auto-precharge |
US20220244870A1 (en) * | 2021-02-03 | 2022-08-04 | Alibaba Group Holding Limited | Dynamic memory coherency biasing techniques |
US11798608B2 (en) * | 2021-12-28 | 2023-10-24 | Micron Technology, Inc. | Techniques to perform a sense operation |
JP2024002003A (ja) * | 2022-06-23 | 2024-01-11 | キオクシア株式会社 | メモリデバイス及びメモリシステム |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001210073A (ja) | 2000-01-21 | 2001-08-03 | Sharp Corp | 不揮発性半導体記憶装置およびそれを用いたシステムlsi |
US20050111275A1 (en) | 2003-11-26 | 2005-05-26 | Oliver Kiehl | Cost efficient row cache for DRAMs |
JP2007512657A (ja) | 2003-11-26 | 2007-05-17 | インテル・コーポレーション | メモリ性能を改善する方法および装置 |
US20070156947A1 (en) | 2005-12-29 | 2007-07-05 | Intel Corporation | Address translation scheme based on bank address bits for a multi-processor, single channel memory system |
JP2012221338A (ja) | 2011-04-12 | 2012-11-12 | Hitachi Ltd | 半導体装置、不揮発性メモリ装置の制御方法 |
JP2013114644A (ja) | 2011-12-01 | 2013-06-10 | Fujitsu Ltd | メモリモジュールおよび半導体記憶装置 |
JP2016506009A (ja) | 2013-01-08 | 2016-02-25 | クゥアルコム・インコーポレイテッドQualcomm Incorporated | 開放されたロウの好適する数をもつメモリ装置 |
JP6208796B2 (ja) | 2008-08-13 | 2017-10-04 | コーニング インコーポレイテッド | 規則性メソポーラス炭素−ケイ素ナノ複合材料の合成 |
Family Cites Families (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4694205A (en) * | 1985-06-03 | 1987-09-15 | Advanced Micro Devices, Inc. | Midpoint sense amplification scheme for a CMOS DRAM |
US5270967A (en) | 1991-01-16 | 1993-12-14 | National Semiconductor Corporation | Refreshing ferroelectric capacitors |
JPH06208796A (ja) * | 1993-11-01 | 1994-07-26 | Hitachi Ltd | 半導体メモリ |
JPH07211062A (ja) * | 1994-01-10 | 1995-08-11 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH11339466A (ja) * | 1998-03-27 | 1999-12-10 | Fujitsu Ltd | 破壊読出型メモリ回路、リストア用アドレス記憶・制御回路及びセンスアンプ |
KR100329024B1 (ko) * | 1998-03-27 | 2002-03-18 | 아끼구사 나오유끼 | 파괴 읽기형 메모리 회로, 이를 위한 리스토어 회로 및 감지 증폭기 |
DE10014387C1 (de) * | 2000-03-23 | 2001-09-27 | Infineon Technologies Ag | Integrierter Speicher mit Bitleitungsreferenzspannung und Verfahren zum Erzeugen der Bitleitungsreferenzspannung |
TW525185B (en) * | 2000-03-30 | 2003-03-21 | Matsushita Electric Ind Co Ltd | Semiconductor memory device having normal and standby modes, semiconductor integrated circuit and mobile electronic unit |
CN1303612C (zh) | 2001-08-01 | 2007-03-07 | 联华电子股份有限公司 | 选择性存储器刷新电路与刷新方法 |
JP2003059273A (ja) * | 2001-08-09 | 2003-02-28 | Hitachi Ltd | 半導体記憶装置 |
US20030058681A1 (en) * | 2001-09-27 | 2003-03-27 | Intel Corporation | Mechanism for efficient wearout counters in destructive readout memory |
KR100463599B1 (ko) * | 2001-11-17 | 2004-12-29 | 주식회사 하이닉스반도체 | 불휘발성 강유전체 메모리 장치 및 그의 구동방법 |
US6873536B2 (en) | 2002-04-19 | 2005-03-29 | Texas Instruments Incorporated | Shared data buffer in FeRAM utilizing word line direction segmentation |
US7048237B2 (en) * | 2003-04-08 | 2006-05-23 | Air Techniques, Inc. | Mounting assembly for a dental x-ray system |
KR100492781B1 (ko) * | 2003-05-23 | 2005-06-07 | 주식회사 하이닉스반도체 | 멀티비트 제어 기능을 갖는 불휘발성 강유전체 메모리 장치 |
KR100596849B1 (ko) * | 2004-01-12 | 2006-07-04 | 주식회사 하이닉스반도체 | 차동 데이터를 갖는 불휘발성 강유전체 메모리 장치 |
JP2005243164A (ja) * | 2004-02-27 | 2005-09-08 | Toshiba Corp | 半導体記憶装置 |
US7239557B2 (en) * | 2005-06-17 | 2007-07-03 | Micron Technology, Inc. | Program method with optimized voltage level for flash memory |
US7372746B2 (en) * | 2005-08-17 | 2008-05-13 | Micron Technology, Inc. | Low voltage sensing scheme having reduced active power down standby current |
KR100802248B1 (ko) | 2005-12-30 | 2008-02-11 | 주식회사 하이닉스반도체 | 비휘발성 반도체 메모리 장치 |
US7599208B2 (en) * | 2006-07-27 | 2009-10-06 | Hynix Semiconductor Inc. | Nonvolatile ferroelectric memory device and refresh method thereof |
US7307911B1 (en) * | 2006-07-27 | 2007-12-11 | International Business Machines Corporation | Apparatus and method for improving sensing margin of electrically programmable fuses |
US7738306B2 (en) | 2007-12-07 | 2010-06-15 | Etron Technology, Inc. | Method to improve the write speed for memory products |
US20090248955A1 (en) * | 2008-03-31 | 2009-10-01 | Satoru Tamada | Redundancy for code in rom |
US7843725B2 (en) * | 2008-06-11 | 2010-11-30 | Micron Technology, Inc. | M+L bit read column architecture for M bit memory cells |
US7813201B2 (en) * | 2008-07-08 | 2010-10-12 | Atmel Corporation | Differential sense amplifier |
US9208902B2 (en) * | 2008-10-31 | 2015-12-08 | Texas Instruments Incorporated | Bitline leakage detection in memories |
US8023334B2 (en) * | 2008-10-31 | 2011-09-20 | Micron Technology, Inc. | Program window adjust for memory cell signal line delay |
KR101053525B1 (ko) * | 2009-06-30 | 2011-08-03 | 주식회사 하이닉스반도체 | 감지 증폭기 및 이를 이용한 반도체 집적회로 |
US8310893B2 (en) | 2009-12-16 | 2012-11-13 | Micron Technology, Inc. | Techniques for reducing impact of array disturbs in a semiconductor memory device |
US8982659B2 (en) * | 2009-12-23 | 2015-03-17 | Intel Corporation | Bitline floating during non-access mode for memory arrays |
JP2011197819A (ja) * | 2010-03-17 | 2011-10-06 | Toshiba Corp | 半導体装置 |
US8208314B2 (en) * | 2010-06-01 | 2012-06-26 | Aptina Imaging Corporation | Sequential access memory elements |
JP6097222B2 (ja) * | 2010-12-24 | 2017-03-15 | マイクロン テクノロジー, インク. | メモリ用連続的ページ読み出し |
JP5243568B2 (ja) | 2011-02-23 | 2013-07-24 | 株式会社半導体理工学研究センター | センスアンプ回路 |
US9432298B1 (en) * | 2011-12-09 | 2016-08-30 | P4tents1, LLC | System, method, and computer program product for improving memory systems |
US8953395B2 (en) * | 2012-02-23 | 2015-02-10 | Apple Inc. | Memory with variable strength sense amplifier |
US8954672B2 (en) * | 2012-03-12 | 2015-02-10 | Advanced Micro Devices, Inc. | System and method for cache organization in row-based memories |
US8996782B2 (en) * | 2012-03-23 | 2015-03-31 | Kabushiki Kaisha Toshiba | Memory system and bank interleaving method |
US9070424B2 (en) * | 2012-06-29 | 2015-06-30 | Samsung Electronics Co., Ltd. | Sense amplifier circuitry for resistive type memory |
US8848419B2 (en) * | 2012-08-09 | 2014-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sensing memory element logic states from bit line discharge rate that varies with resistance |
US9418714B2 (en) * | 2013-07-12 | 2016-08-16 | Nvidia Corporation | Sense amplifier with transistor threshold compensation |
US8964496B2 (en) * | 2013-07-26 | 2015-02-24 | Micron Technology, Inc. | Apparatuses and methods for performing compare operations using sensing circuitry |
KR20150064880A (ko) * | 2013-12-04 | 2015-06-12 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그의 구동방법 |
US20150228314A1 (en) * | 2014-02-10 | 2015-08-13 | Qualcomm Incorporated | Level shifters for systems with multiple voltage domains |
US9330731B2 (en) * | 2014-02-17 | 2016-05-03 | Taiwan Semiconductor Manufacturing Company Ltd. | Circuits in strap cell regions |
KR102237735B1 (ko) | 2014-06-16 | 2021-04-08 | 삼성전자주식회사 | 저항성 메모리 장치의 메모리 코어, 이를 포함하는 저항성 메모리 장치 및 저항성 메모리 장치의 데이터 감지 방법 |
US9286971B1 (en) * | 2014-09-10 | 2016-03-15 | Apple Inc. | Method and circuits for low latency initialization of static random access memory |
US20160093353A1 (en) * | 2014-09-27 | 2016-03-31 | Qualcomm Incorporated | Dual stage sensing current with reduced pulse width for reading resistive memory |
JP6514074B2 (ja) * | 2015-09-11 | 2019-05-15 | 株式会社東芝 | 判定回路 |
US9542998B1 (en) * | 2015-11-02 | 2017-01-10 | Synopsys, Inc | Write assist circuit integrated with leakage reduction circuit of a static random access memory for increasing the low voltage supply during write operations |
US10082964B2 (en) | 2016-04-27 | 2018-09-25 | Micron Technology, Inc | Data caching for ferroelectric memory |
US11367480B2 (en) * | 2019-12-04 | 2022-06-21 | Marvell Asia Pte, Ltd. | Memory device implementing multiple port read |
-
2016
- 2016-04-27 US US15/140,073 patent/US10082964B2/en active Active
-
2017
- 2017-04-25 EP EP17790270.7A patent/EP3449376A4/en not_active Withdrawn
- 2017-04-25 CN CN202110534459.XA patent/CN113127379B/zh active Active
- 2017-04-25 CN CN201780026279.2A patent/CN109154909B/zh active Active
- 2017-04-25 WO PCT/US2017/029420 patent/WO2017189579A2/en active Application Filing
- 2017-04-25 JP JP2018555917A patent/JP7137477B2/ja active Active
- 2017-04-25 KR KR1020207024810A patent/KR20200104432A/ko not_active Application Discontinuation
- 2017-04-25 KR KR1020187033881A patent/KR102151659B1/ko active Application Filing
- 2017-04-25 KR KR1020217033217A patent/KR102434162B1/ko active IP Right Grant
-
2018
- 2018-09-05 US US16/122,526 patent/US10776016B2/en active Active
-
2020
- 2020-08-20 US US16/998,601 patent/US11520485B2/en active Active
-
2021
- 2021-07-09 JP JP2021113929A patent/JP2021168225A/ja active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001210073A (ja) | 2000-01-21 | 2001-08-03 | Sharp Corp | 不揮発性半導体記憶装置およびそれを用いたシステムlsi |
US20050111275A1 (en) | 2003-11-26 | 2005-05-26 | Oliver Kiehl | Cost efficient row cache for DRAMs |
JP2007512657A (ja) | 2003-11-26 | 2007-05-17 | インテル・コーポレーション | メモリ性能を改善する方法および装置 |
US20070156947A1 (en) | 2005-12-29 | 2007-07-05 | Intel Corporation | Address translation scheme based on bank address bits for a multi-processor, single channel memory system |
JP6208796B2 (ja) | 2008-08-13 | 2017-10-04 | コーニング インコーポレイテッド | 規則性メソポーラス炭素−ケイ素ナノ複合材料の合成 |
JP2012221338A (ja) | 2011-04-12 | 2012-11-12 | Hitachi Ltd | 半導体装置、不揮発性メモリ装置の制御方法 |
JP2013114644A (ja) | 2011-12-01 | 2013-06-10 | Fujitsu Ltd | メモリモジュールおよび半導体記憶装置 |
JP2016506009A (ja) | 2013-01-08 | 2016-02-25 | クゥアルコム・インコーポレイテッドQualcomm Incorporated | 開放されたロウの好適する数をもつメモリ装置 |
Also Published As
Publication number | Publication date |
---|---|
CN113127379A (zh) | 2021-07-16 |
CN109154909B (zh) | 2021-05-28 |
KR102434162B1 (ko) | 2022-08-19 |
US10082964B2 (en) | 2018-09-25 |
KR102151659B1 (ko) | 2020-09-04 |
CN113127379B (zh) | 2023-12-01 |
US20190004713A1 (en) | 2019-01-03 |
KR20200104432A (ko) | 2020-09-03 |
US11520485B2 (en) | 2022-12-06 |
EP3449376A2 (en) | 2019-03-06 |
JP2021168225A (ja) | 2021-10-21 |
KR20180128089A (ko) | 2018-11-30 |
US20200379655A1 (en) | 2020-12-03 |
JP2019515409A (ja) | 2019-06-06 |
CN109154909A (zh) | 2019-01-04 |
EP3449376A4 (en) | 2019-12-25 |
KR20210128034A (ko) | 2021-10-25 |
WO2017189579A3 (en) | 2018-07-26 |
WO2017189579A2 (en) | 2017-11-02 |
US20170315737A1 (en) | 2017-11-02 |
US10776016B2 (en) | 2020-09-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7137477B2 (ja) | データキャッシング | |
JP7101216B2 (ja) | Feram-dramハイブリッドメモリ | |
US11501814B2 (en) | Parallel access techniques within memory sections through section independence | |
US9886991B1 (en) | Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated from digit lines |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181112 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20181112 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20191225 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200128 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200424 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20200424 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200923 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20201217 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20210323 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20210709 |
|
C60 | Trial request (containing other claim documents, opposition documents) |
Free format text: JAPANESE INTERMEDIATE CODE: C60 Effective date: 20210709 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20210727 |
|
C21 | Notice of transfer of a case for reconsideration by examiners before appeal proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C21 Effective date: 20210803 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20210910 |
|
C211 | Notice of termination of reconsideration by examiners before appeal proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C211 Effective date: 20210914 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20211130 |
|
C13 | Notice of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: C13 Effective date: 20220315 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20220405 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220609 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20220705 |
|
C23 | Notice of termination of proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C23 Effective date: 20220712 |
|
C03 | Trial/appeal decision taken |
Free format text: JAPANESE INTERMEDIATE CODE: C03 Effective date: 20220809 |
|
C30A | Notification sent |
Free format text: JAPANESE INTERMEDIATE CODE: C3012 Effective date: 20220809 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20220902 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7137477 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |