WO2021244080A1 - 读写转换电路以及存储器 - Google Patents

读写转换电路以及存储器 Download PDF

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WO2021244080A1
WO2021244080A1 PCT/CN2021/078506 CN2021078506W WO2021244080A1 WO 2021244080 A1 WO2021244080 A1 WO 2021244080A1 CN 2021078506 W CN2021078506 W CN 2021078506W WO 2021244080 A1 WO2021244080 A1 WO 2021244080A1
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Prior art keywords
data line
read
nmos transistor
write
electrically connected
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PCT/CN2021/078506
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English (en)
French (fr)
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尚为兵
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长鑫存储技术有限公司
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Priority to US17/595,721 priority Critical patent/US11995341B2/en
Priority to EP21818325.9A priority patent/EP4020477A4/en
Publication of WO2021244080A1 publication Critical patent/WO2021244080A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular to a read-write conversion circuit and a memory.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor storage device commonly used in computers, which consists of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • DRAM Dynamic Random Access Memory
  • DRAM is divided into double rate synchronous (Double Data Rate, DDR) dynamic random access memory, GDDR (Graphics Double Data Rate) dynamic random access memory, and low power double rate synchronous (Low Power Double Data Rate, LPDDR) dynamic random access memory.
  • DDR Double Data Rate
  • GDDR Graphics Double Data Rate
  • LPDDR Low Power Double Data Rate
  • the embodiments of the present application provide a read-write conversion circuit and a memory to solve the problem of slow data transmission speed during read-write operations.
  • an embodiment of the present application provides a read-write conversion circuit, which includes: a first data line connected to a bit line via a column selection module and a first complementary data line connected to a complementary bit line via a column selection module;
  • the second data line and the second complementary data line further include: a read-write conversion module, in response to a read-write control signal, during a read-write operation, data is transmitted between the first data line and the second data line, so Data is transmitted between the first complementary data line and the second complementary data line; an amplifying module, connected between the first data line and the first complementary data line, is used to transmit data to the first data line The data of and the data of the first complementary data line are amplified.
  • the amplifying module includes: a first inverter, an input terminal of the first inverter is electrically connected to the first data line, and an output terminal of the first inverter is complementary to the first The data line is electrically connected; a second inverter, the input end of the second inverter is electrically connected to the output end of the first inverter and the first complementary data line, the second inverter The output terminal of is electrically connected with the input terminal of the first inverter and the first data line.
  • the first inverter includes: a first PMOS tube and a first NMOS tube, the gate of the first PMOS tube and the gate of the first NMOS tube are connected and serve as the input of the first inverter
  • the source of the first PMOS transistor is connected to a working power source
  • the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and serves as the output terminal of the first inverter.
  • the second inverter includes: a second PMOS tube and a second NMOS tube, the gate of the second PMOS tube is connected to the gate of the second NMOS tube and serves as an input terminal of the second inverter,
  • the source of the second PMOS transistor is connected to a working power source, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and serves as an output terminal of the second inverter.
  • the source of the first NMOS transistor is grounded, and the source of the second NMOS transistor is grounded.
  • the read-write conversion module includes: a first read-write unit that transmits the data of the first data line to the second data line in response to the read control signal in the read-write control signal, or , In response to the write control signal in the read and write control signal, transmit the data of the second data line to the first data line; the second read and write unit, in response to the read control signal, will The data of the first complementary data line is transmitted to the second complementary data line, or, in response to the write control signal, the data of the second complementary data line is transmitted to the first complementary data line.
  • the first read-write unit includes: a third NMOS tube, a fourth NMOS tube, and a fifth NMOS tube; the gate of the third NMOS tube receives the write control signal, and the third NMOS tube responds to The write control signal is electrically connected to the first data line and the second data line; the gate of the fourth NMOS transistor is electrically connected to the first complementary data line, and the drain of the fourth NMOS transistor is electrically connected to the The second data line is electrically connected, the source of the fourth NMOS transistor is electrically connected to the drain of the fifth NMOS transistor, and the gate of the fifth NMOS transistor receives the read control signal.
  • the second read-write unit includes: a seventh NMOS tube, an eighth NMOS tube, and a ninth NMOS tube; the gate of the seventh NMOS tube receives the write control signal, and the seventh NMOS tube responds to The write control signal is electrically connected to the first complementary data line and the second complementary data line; the gate of the eighth NMOS transistor is electrically connected to the first data line, and the drain of the eighth NMOS transistor It is electrically connected to the second complementary data line, the source of the eighth NMOS transistor is electrically connected to the drain of the ninth NMOS transistor, and the gate of the ninth NMOS transistor receives the read control signal.
  • the read-write conversion circuit further includes: a sixth NMOS transistor, the gate of the sixth NMOS transistor receives an enable signal, the drain of the sixth NMOS transistor is connected to the first inverter and the second The inverter is connected and is also electrically connected to the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor is grounded.
  • the amplifying module further includes: an enabling NMOS tube, the drain of the enabling NMOS tube is electrically connected to the first inverter and the second inverter, and the gate of the enabling NMOS tube receives An enabling signal, and the source of the enabling NMOS transistor is grounded.
  • the read-write conversion module includes: a read unit, which transmits the data of the first data line to the second data line in response to the read control signal in the read-write control signal, and transmits the The data of the first complementary data line is transmitted to the second complementary data line; the write unit, in response to the write control signal in the read-write control signal, transmits the data of the second data line to the first A data line transmits the data of the second complementary data line to the first complementary data line.
  • the writing unit includes: a sixth NMOS tube, a seventh NMOS tube, and an eighth NMOS tube; the gate of the eighth NMOS tube and the gate of the sixth NMOS tube receive the writing control signal, so The eighth NMOS transistor is electrically connected to the first data line and the second data line in response to the write control signal, the gate of the seventh NMOS transistor is electrically connected to the second data line, and the first The drain of the seventh NMOS transistor is electrically connected to the first complementary data line, the source of the seventh NMOS transistor is electrically connected to the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded.
  • the writing unit further includes: a third NMOS tube, a fourth NMOS tube, and a fifth NMOS tube; the gates of the third NMOS tube and the fifth NMOS tube receive the writing control signal, the The third NMOS transistor is electrically connected to the first complementary data line and the second complementary data line in response to the write control signal, the gate of the fourth NMOS transistor is electrically connected to the second complementary data line, so The drain of the fourth NMOS transistor is electrically connected to the first data line, the source of the fourth NMOS transistor is electrically connected to the drain of the fifth NMOS transistor, and the source of the fifth NMOS transistor is grounded.
  • the read unit includes: a tenth NMOS transistor and a twelfth NMOS transistor; the gate of the twelfth NMOS transistor receives the read control signal; the drain of the twelfth NMOS transistor and the second NMOS transistor Two data lines are electrically connected, the source of the twelfth NMOS transistor is electrically connected to the drain of the tenth NMOS transistor, the gate of the tenth NMOS transistor is electrically connected to the first complementary data line, and the tenth NMOS transistor is electrically connected to the first complementary data line.
  • the source of the NMOS tube is grounded.
  • the reading unit further includes: a ninth NMOS transistor and an eleventh NMOS transistor; the gate of the ninth NMOS transistor is electrically connected to the first data line, the source is grounded, and the drain is connected to the tenth NMOS transistor.
  • An NMOS transistor source is electrically connected; the gate of the eleventh NMOS transistor receives the read control signal, and the drain of the eleventh NMOS transistor is electrically connected to the second complementary data line.
  • a pre-charging module connected between the first data line and the first complementary data line, and configured to respond to a pre-charge control signal to perform a charge on the first data line and the first complementary data line.
  • the first complementary data line is precharged.
  • the pre-charging module includes: a third PMOS tube, a fourth PMOS tube, and a fifth PMOS tube, the third PMOS tube gate, the fourth PMOS tube gate, and the fifth PMOS tube gate A precharge control signal is received; the source of the third PMOS transistor and the source of the fourth PMOS transistor are connected to a working power source, and the drain of the third PMOS transistor is electrically connected to the first data line; the fourth PMOS The drain of the transistor is electrically connected to the first complementary data line; the fifth PMOS transistor is electrically connected to the first data line and the first complementary data line in response to the precharge control signal.
  • an embodiment of the present application also provides a memory including the above-mentioned read-write conversion circuit.
  • the memory further includes: a number of memory modules, each of the memory modules includes a memory array and a sensitive amplifier array; the read-write conversion circuit is connected to the sensitive amplifier array.
  • the memory includes DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND flash memory or NOR flash memory.
  • the embodiment of the present application provides a read-write conversion circuit, which includes a first data line connected to a bit line via a column selection module, and a first complementary data line connected to a complementary bit line via the column selection module; the read-write conversion module is configured to respond In the read control signal or the write control signal, data is transmitted between the first data line and the first complementary data line and the second data line and the second complementary data line; and also includes the connection between the first data line and the first data line;
  • the amplifying module between the complementary data lines is used to amplify the data of the first data line and the data of the first complementary data line.
  • the arrangement of the amplifying module is beneficial for accelerating the distinction between the data signal of the first data line and the first complementary data line, and plays a role of amplifying the data signal, so that the data transmission speed in the read-write conversion circuit is improved.
  • the memory provided by the present application includes the above-mentioned read-write conversion circuit with excellent structural performance, and the corresponding memory has the advantage of fast transmission speed.
  • the read-write conversion circuit in the memory has a low requirement for the drive capability of the memory.
  • the first data line and the first complementary data line have low requirements for the drive capability of the first-stage amplifier in the memory. Even if the area of the first-stage amplifier is reduced, it can still ensure sufficient driving capability to meet the development trend of miniaturization and miniaturization of devices.
  • FIG. 1 is a schematic diagram of functional modules of a read-write conversion circuit provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of the circuit structure of a read-write conversion circuit provided by an embodiment of the application;
  • FIG. 3 is a circuit timing diagram of the read-write conversion circuit provided by an embodiment of the application during a read operation
  • FIG. 4 is a schematic diagram of a circuit structure of a read-write conversion circuit provided by another embodiment of the application.
  • FIG. 5 is a schematic diagram of another circuit structure of a read-write conversion circuit provided by another embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a memory provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of a partial enlarged structure of area A in FIG. 6.
  • the data in the corresponding memory cell will be transferred to the bit line (BL, Bit Line), causing the voltage on the bit line to appear weakly. Increase or decrease.
  • the sense amplifier connected to the bit line is usually called a first-stage amplifier (FSA, first sense amplifier), which pulls the bit line signal to 0 or 1 according to this weak signal.
  • FSA first-stage amplifier
  • the column selection module transmits the 0 or 1 signal on the selected bit line to the local data line (LocalDataLine) according to the column selection signal, and then transmits the signal in the local data line to the global data line (GlobalDataLine) through the read-write conversion circuit superior. It should be noted that the foregoing 0 represents the signal level is low, and 1 represents the signal level is high.
  • the drive performance of the first-stage amplifier of the memory is required to be high.
  • the first-stage amplifier when reading data, after the level of the column select signal line (CSL, Column Select Line) is pulled high, the first-stage amplifier will directly drive the local data line. If the first-stage amplifier has insufficient drive capability, it will greatly Affects the speed of pulling up or pulling down the level of the local data line.
  • the first-stage amplifier is made smaller and smaller, and the corresponding driving capability of the first-stage amplifier is difficult to improve. Therefore, in order to ensure high data transmission capability, it is necessary to consider how to reduce the requirement of the local data line on the driving capability of the first-stage amplifier.
  • the embodiment of the present application provides a read-write conversion circuit.
  • the first data line is connected to the bit line through the column selection module, and the first complementary data line is connected to the complementary bit line through the column selection module.
  • An amplifying module is arranged between the first complementary data line and the first complementary data line to amplify the data signals of the first data line and the first complementary data line, so as to accelerate the distinction between the first data line and the first complementary data line, for example, to have a lower voltage
  • the first data line or the first complementary data line becomes 0 more quickly, and the first data line or the first complementary data line with a higher voltage becomes 1 more quickly, thereby speeding up the read operation or write operation
  • Data transmission reduces the requirements of the first data line and the first complementary data line for the driving capability of the first-stage amplifier.
  • FIG. 1 is a schematic diagram of functional modules of a read-write conversion circuit provided by an embodiment of this application
  • FIG. 2 is a schematic diagram of a circuit structure provided by an embodiment of this application.
  • the read-write conversion circuit includes: a first data line Ldat and a first complementary data line Ldat#, the first data line Ldat is connected to the bit line BL via the column selection module 100, A complementary data line Ldat# is electrically connected to the complementary bit line BL# via the column selection module 100, the second data line Gdat# and the second complementary data line Gdat; the read-write conversion module 101, in response to the read-write control signal, is During operation, data is transmitted between the first data line Ldat and the second data line Gdat, and data is transmitted between the first complementary data line Ldat# and the second complementary data line Gdat#; the amplifying module 102 is connected to the first data line Ldat Between the first complementary data line Ldat# and the first complementary data line Ldat#, it is used to amplify the data of the first data line Ldat and the data of the first complementary data line Ldat#.
  • the amplifying module 102 constitutes a circuit for amplifying the signal of the first data line Ldat and the signal of the first complementary data line Ldat#, which helps to accelerate the distinction between the level of the first data line Ldat and the level of the first complementary data line Ldat# , Thereby increasing the speed of data signal transmission and improving the speed of data reading and writing.
  • the first data line Ldat and the first complementary data line Ldat# are required for the driving capability of the first-stage amplifying circuit in the memory.
  • the first-stage amplifying circuit still has sufficient driving capability for the first data line Ldat and the first complementary data line Ldat#, so as to meet the requirements of device miniaturization. At the same time, it ensures that the read-write conversion circuit has good electrical performance, thereby improving the storage performance of the memory containing the read-write conversion circuit.
  • the read data or the written data signals are in pairs, and each pair of data signals includes two data.
  • the read-write conversion circuit includes at least a pair of first data lines Ldat and a first complementary data line Ldat#, and at least a pair of second data lines Gdat and a second complementary data line Gdat#.
  • data is transmitted to the second data line Gdat and the second complementary data line Gdat# via the first data line Ldat and the first complementary data line Ldat#; the read-write conversion circuit is writing During the input operation, data is transmitted to the first data line Ldat and the first complementary data line Ldat# via the second data line Gdat and the second complementary data line Gdat#.
  • the first data line Ldat is a local data line (local data line, also called a local data line), the first complementary data line Ldat# is a complementary local data line; the second data line Gdat is a global data line, The second complementary data line Gdat# is a complementary global data line.
  • the read-write conversion circuit is applied to a memory.
  • the memory includes a column selection module 100.
  • the first data line Ldat is connected to the bit line BL through the column selection module 100, and the first complementary data line Ldat# passes through the column selection module. 100 is connected to the complementary bit line BL#.
  • a memory cell for reading or writing is selected by the column selection module 100, and correspondingly, the bit line BL connected to the selected memory cell transmits a signal with the first data line Ldat, and is connected to the selected memory cell Signals are transmitted between the complementary bit line BL# and the first complementary data line Ldat#.
  • the read and write control signals include a read control signal Rd and a write control signal Wr.
  • the read and write conversion module 101 transmits the data of the first data line Ldat and the first complementary data line Ldat# to the second data line Gdat and the second complementary data line Gdat#
  • the read-write conversion module 101 transmits the data of the second data line Gdat and the second complementary data line Gdat# to the first data line Ldat and the first complementary data line Ldat#.
  • the read-write conversion module 101 includes: a first read-write unit 111, which transmits the data of the first data line Ldat to the second data line Gdat in response to the read control signal Rd, or, in response to the write control The signal Wr transmits the data of the second data line Gdat to the first data line Ldat; the second reading and writing unit 121, in response to the read control signal Rd, transmits the data of the first complementary data line Ldat# to the second complementary data The line Gdat#, or, in response to the write control signal Wr, transmits the data of the second complementary data line Gdat# to the first complementary data line Ldat#.
  • the first read-write unit 111 may include: a third NMOS tube MN3, a fourth NMOS tube MN4, and a fifth NMOS tube MN5; the gate of the third NMOS tube MN3 receives the write control signal Wr, and the third NMOS tube MN3 receives the write control signal Wr.
  • the NMOS transistor MN3 is electrically connected to the first data line Ldat and the second data line Gdat in response to the write control signal Wr; the gate of the fourth NMOS transistor MN4 is electrically connected to the first complementary data line Ldat#, and the drain of the fourth NMOS transistor MN4 is electrically connected to the The second data line Gdat is electrically connected, the source of the fourth NMOS transistor MN4 is electrically connected to the drain of the fifth NMOS transistor MN5, and the gate of the fifth NMOS transistor MN5 receives the read control signal Rd.
  • the second reading and writing unit 121 may include: a seventh NMOS tube MN7, an eighth NMOS tube MN8, and a ninth NMOS tube MN9; the gate of the seventh NMOS tube MN7 receives the write control signal Wr, and the seventh NMOS tube MN7 responds to the write
  • the control signal Wr is electrically connected to the first complementary data line Ldat# and the second complementary data line Gdat#; the gate of the eighth NMOS transistor MN8 is electrically connected to the first data line Ldat, and the drain is electrically connected to the second complementary data line Gdat#,
  • the source is electrically connected to the drain of the ninth NMOS transistor MN9, and the gate of the ninth NMOS transistor MN9 receives the read control signal Rd.
  • the first read-write unit 111 and the second read-write unit 121 have the same circuit structure, that is, the connection relationship between the transistors included in the first read-write unit 111 and the connection of the transistors included in the second read-write unit 121 The relationship is the same.
  • the circuit structure diagrams of the first read-write unit and the second read-write unit may also be different, as long as data transmission can be realized during the read-write operation.
  • the read-write conversion circuit may further include: a sixth NMOS transistor MN6, the gate of the sixth NMOS transistor MN6 receives the enable signal En, the drain of the sixth NMOS transistor MN6, the source of the fifth NMOS transistor MN5, and the second The source of the nine NMOS transistor MN9 is electrically connected, and the source of the sixth NMOS transistor MN6 is grounded.
  • the column selection module 100 data is first transferred from the selected bit line BL and the complementary bit line BL# to the first data line Ldat and the first complementary data line Ldat#.
  • the level of the first data line Ldat and the level of the first complementary data line Ldat# will quickly reach a low or high level. Then the data will be transferred from the first data line Ldat and the first complementary data line Ldat# to the second data line Gdat and the second complementary data line Gdat#.
  • the read control signal Rd is at a high level
  • the write control signal Wr is at a low level
  • the third NMOS tube MN3 and the seventh NMOS tube MN7 are turned off
  • the fifth NMOS tube MN5 and the ninth NMOS tube MN9 are turned on
  • the eighth NMOS transistor MN8 and the sixth NMOS transistor MN6 are turned on, and data flows from the first complementary data line Ldat# is transmitted to the second complementary data line Gdat#, the second complementary data line Gdat# becomes 0, and the second data line Gdat is 1.
  • the fourth NMOS transistor MN4 and the sixth NMOS transistor MN6 are turned on, data is transmitted from the first data line Ldat to the second data line Gdat, the second data line Gdat becomes 0, and the second complementary data line Gdat# is 1.
  • the second data line Gdat becomes 0, it means that the level of the second data line Gdat changes from a high level to a low level.
  • the second complementary data line Gdat# being 1 refers to the power of the second complementary data line Gdat#. Level is high.
  • the data transmission direction is opposite to the data transmission direction during the read operation, that is, data is transmitted from the second data line Gdat and the second complementary data line Gdat# to the first data line Ldat and the first complementary data line Ldat. #.
  • the amplifying module 102 includes: a first inverter 112.
  • the first input terminal in1 of the first inverter 112 is electrically connected to the first data line Ldat; and the second inverter 122 is electrically connected to the first data line Ldat.
  • the second input terminal in2 of the second inverter 122 is electrically connected to the first output terminal out1 of the first inverter 112 and the first complementary data line Ldat#, and the second output terminal out2 of the second inverter 122 is electrically connected to the first output terminal out1 of the first inverter 112.
  • the first input terminal in1 of the inverter 112 and the first data line Ldat are electrically connected.
  • the transmission speed of data from the bit line BL to the first data line Ldat is increased, and the transmission speed of data from the complementary bit line BL# to the first complementary data line Ldat# It is improved, and the drive demand of the first-stage amplifier for the memory is reduced.
  • the first output terminal out1 of the first inverter 112 is connected to the second input terminal in2 of the second inverter 122, and is transmitted to the first data line Ldat and the first data line Ldat and the first data line Ldat on the bit line BL and the complementary bit line BL#
  • the setting of the amplifying module 102 will make the first complementary data line Ldat# with a lower level pull down to “0” more quickly, or make the first data line Ldat with a higher level Pull up to "1" more quickly.
  • the first data line Ldat and the first complementary data line Ldat# can reach a high level or a low level more quickly, the first data line Ldat and the first complementary data line can be connected earlier
  • the line Ldat# is transmitted to the second data line Gdat and the second complementary data line Gdat#, so that when data is read, the data is transferred from the first data line Ldat and the first complementary data line Ldat# to the second data line Gdat and the second data line Gdat.
  • the speed of the two complementary data line Gdat# can be improved.
  • the amplifying module 102 can also amplify the first data line Ldat and the first complementary data line Ldat# to enhance the data transmission from the second data line Gdat and the second complementary data line Gdat# Speed to the first data line Ldat and the first complementary data line Ldat#.
  • the first inverter 112 includes: a first PMOS tube MP1 and a first NMOS tube MN1.
  • the gate of the first PMOS tube MP1 and the gate of the first NMOS tube MN1 are electrically connected and serve as the first inverter of the first inverter.
  • the source of the first PMOS transistor MP1 is connected to the working power supply VDD
  • the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 and serves as the first output terminal out1 of the first inverter 112.
  • the second inverter 122 includes a second PMOS tube MP2 and a second NMOS tube MN2.
  • the gate of the second PMOS tube MP2 is connected to the gate of the second NMOS tube MN2 and serves as the second input terminal in2 of the second inverter 122.
  • the source of the second PMOS transistor MP2 is connected to the working power supply VDD, and the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2 and serves as the second output terminal out2 of the second inverter 122.
  • the first PMOS tube MP1, the first NMOS tube MN1, the second PMOS tube MP2, and the second NMOS tube MN2 constitute the amplification module 102.
  • first inverter 112 and the second inverter 122 are also connected to the drain of the sixth NMOS transistor.
  • the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are connected to the drain of the sixth NMOS transistor MN6.
  • the source of the first NMOS transistor MN1 is grounded, and the source of the second NMOS transistor MN2 is grounded.
  • the read-write conversion circuit may further include: a pre-charging module 103, which is connected between the first data line Ldat and the first complementary data line Ldat# for responding to the pre-charging
  • the control signal Eq precharges the first data line Ldat and the first complementary data line Ldat# line.
  • the pre-charging module 103 includes: a third PMOS tube MP3, a fourth PMOS tube MP4, and a fifth PMOS tube MP5; a third PMOS tube MP3 gate, a fourth PMOS tube MP4 gate, and a fifth PMOS tube MP5 gate Receive the precharge control signal Eq; the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are connected to the working power supply VDD, the drain of the third PMOS tube MP3 is electrically connected to the first data line Ldat; the drain of the fourth PMOS tube MP4 It is electrically connected to the first complementary data line Ldat#; the fifth PMOS transistor MN5 is electrically connected to the first data line Ldat and the first complementary data line Ldat# in response to the precharge control signal Eq.
  • FIG. 3 is a circuit timing diagram of the read-write conversion circuit without the amplification module and the read-write conversion circuit provided by this embodiment during the read operation.
  • the circuit timing diagram is for the same signal with a change in timing.
  • the dashed line represents the timing corresponding to the amplifier module not added
  • the solid line represents the timing corresponding to this embodiment
  • CSL represents the column selection signal.
  • the data of the first data line Ldat and the first complementary data line Ldat# reach a high level or a low level t time in advance.
  • Level that is, in this embodiment, data can be transmitted t time earlier, the rising edge time of the read control signal Rd can be advanced from time A1 to time A2, and the difference between time A2 and time A1 is t.
  • Another embodiment of the present application also provides a read-write conversion circuit.
  • the specific circuit structure of the read-write conversion module in this embodiment is different from the previous embodiment.
  • the read-write conversion circuit provided in this embodiment will be described below with reference to the accompanying drawings. It should be noted that, for the same or corresponding parts as the previous embodiment, please refer to the detailed description of the previous embodiment, which will not be repeated in detail below.
  • FIG. 4 is a schematic diagram of a circuit structure of a read-write conversion circuit provided by another embodiment of the application.
  • the read-write conversion circuit includes: a first data line Ldat, a first complementary data line Ldat#, a second data line Gdat, a second complementary data line Gdat#, a read-write conversion module, and an amplifying module 202.
  • the amplifying module 202 includes a first inverter 212 and a second inverter 222.
  • the first inverter 212 includes a first PMOS tube mp1 and a first NMOS tube mn1
  • the second inverter 222 includes a second PMOS tube mp2 and The second NMOS tube mn2.
  • first inverter and the second inverter please refer to the detailed description of the foregoing embodiment.
  • the amplifying module 202 further includes: enabling the NMOS tube mn, and the drain of the enabling NMOS tube mn is electrically connected to the first inverter 212 and the second inverter 222, The gate of the enabling NMOS tube mn receives the enabling signal En, and the source of the enabling NMOS tube mn is grounded.
  • the drain of the enabling NMOS transistor mn is electrically connected to the source of the first NMOS transistor mn1 and the source of the second NMOS transistor mn2.
  • the first PMOS tube mp1, the first NMOS tube mn1, the second PMOS tube mp2, the second NMOS tube mn2, and the enabling NMOS tube mn constitute the amplification module 202, which is used to connect the first data line Ldat and the first complementary data line Ldat# The data is zoomed in.
  • the read-write conversion module includes: a read unit 211, in response to the read control signal Rd, transmits the data of the first data line Ldat and the first complementary data line Ldat# to the second data line Gdat and the second data line Gdat, respectively Two complementary data lines Gdat#; the writing unit 221, in response to the writing control signal Wr, transmits the data of the second data line Gdat and the second complementary data line Gdat# to the first data line Ldat and the first complementary data line, respectively Ldat#.
  • the writing unit 221 includes: a third NMOS tube mn3, a fourth NMOS tube mn4, a fifth NMOS tube mn5, a sixth NMOS tube mn6, a seventh NMOS tube mn7, and an eighth NMOS tube mn8.
  • the drain of the third NMOS transistor mn3 is electrically connected to the first output terminal out1 of the first inverter 212, the gate of the third NMOS transistor mn3 and the gate of the fifth NMOS transistor mn5 receive the write control signal Wr, and the third NMOS transistor mn3
  • the first complementary data line Ldat# and the second complementary data line Gdat# are electrically connected
  • the gate of the fourth NMOS transistor mn4 is electrically connected to the second complementary data line Gdat#
  • the drain of the fourth NMOS transistor mn4 Electrically connected to the first data line Ldat
  • the source of the fourth NMOS transistor mn4 is electrically connected to the drain of the fifth NMOS transistor drain mn5, the source of the fifth NMOS transistor mn5 is grounded
  • the drain of the eighth NMOS transistor mn8 is connected to the second inverter
  • the second output terminal out2 of 222 is electrically connected, the gate of the eighth
  • the writing unit 221 is used to transmit data from the second data line Gdat to the first data line Ldat, and to transmit data from the second complementary data line Gdat# to the first complementary data line Ldat#.
  • the write control signal Wr is at a high level
  • the third NMOS transistor mn3, the fifth NMOS transistor mn5, the sixth NMOS transistor mn6, and the eighth NMOS transistor mn8 are turned on
  • the second complementary data line Gdat# is transmitted to the first complementary data line Ldat#
  • the first data line Ldat becomes 0, the first complementary The data line Ldat# becomes 1.
  • the time required for the first data line Ldat to become 0 is shortened, thereby accelerating the speed of distinguishing the first data line Ldat from the first complementary data line Ldat#, so as to increase the transfer of the first data line Ldat. And the speed at which data is written into the corresponding storage unit on the first complementary data line Ldat#.
  • the second complementary data line Gdat# When the second complementary data line Gdat# is at a low level, the second data line Gdat is at a high level, the fourth NMOS transistor mn4 is turned off and the seventh NMOS transistor mn7 is turned on, the second data line Gdat is transmitted to the first data line Ldat, The first complementary data line Ldat# becomes 0, and the first data line Ldat becomes 1.
  • the time required for the first complementary data line Ldat# to become 0 is shortened, thereby accelerating the speed of distinguishing the first data line Ldat from the first complementary data line Ldat#, so as to improve the transfer of the first data line Ldat# The speed at which data on the line Ldat and the first complementary data line Ldat# are written into the corresponding memory cell.
  • the reading unit 211 includes: a ninth NMOS tube mn9, a tenth NMOS tube mn10, an eleventh NMOS tube mn11, and a twelfth NMOS tube mn12.
  • the gate of the ninth NMOS transistor mn9 is electrically connected to the first data line Ldat, the source is grounded, the drain is electrically connected to the source of the eleventh NMOS transistor mn11, and the gates of the eleventh NMOS transistor mn11 and the twelfth NMOS transistor mn12 receive Write the control signal Rd, and the drain of the eleventh NMOS transistor mn11 is electrically connected to the second complementary data line Gdat#;
  • the gate of the twelfth NMOS transistor mn12 receives the read control signal Rd, the drain of the twelfth NMOS transistor mn12 is electrically connected to the second data line Gdat, and the source of the twelfth NMOS transistor mn12 is electrically connected to the drain of the tenth NMOS transistor mn10 ,
  • the gate of the tenth NMOS transistor mn10 is electrically connected to the first complementary data line Ldat#, and the source of the tenth NMOS transistor mn10 is grounded.
  • the reading unit 211 is used to transmit data from the first data line Ldat to the second data line Gdat, and to transmit data from the first complementary data line Ldat# to the second complementary data line Gdat#.
  • the read control signal Rd is at a high level
  • the eleventh NMOS transistor mn11 and the twelfth NMOS transistor mn12 are turned on
  • the ninth NMOS transistor mn9 is turned on when the first data line Ldat is at a high level.
  • the ninth NMOS transistor is turned off and the tenth NMOS transistor is turned on when the voltage level is reached, the data of the first complementary data line Ldat# is transmitted to the second complementary data line Gdat#, the second complementary data line Gdat# becomes 1, and the second data line Gdat becomes Is 0.
  • the reaction time for the first data line Ldat or the first complementary data line Ldat# to change from a high level to a low level is shortened, so the second data line Gdat and the second complementary data line Gdat# follow The speed of change is increased, thereby increasing the data transmission speed.
  • the circuit diagram involved in Figure 4 can also have other suitable modifications.
  • the gates of the ninth NMOS transistor mn9 and the tenth NMOS transistor mn10 receive the read control signal Rd, and the gates of the eleventh NMOS transistor mn11 and the second A data line Ldat is connected, and the gate of the twelfth NMOS transistor mn12 is connected to the first complementary data line Ldat#; or, the source of the fifth NMOS transistor mn5 and the source of the sixth NMOS transistor mn6 are electrically connected to the enable NMOS transistor mn Drain.
  • both the writing unit 221 and the reading unit 211 adopt a double-ended transmission mode, that is, the first data line Ldat and the first complementary data line Ldat# are both connected to the writing unit 221. Both the second data line Gdat and the second complementary data line Gdat# are connected to the reading unit 211.
  • at least one of the writing unit or the reading unit may also adopt a single-ended transmission mode, that is, one of the first data line and the first complementary data line is connected to the writing unit, and the second data One of the line and the second complementary data line is connected to the reading unit.
  • FIG. 5 is a schematic diagram of another circuit structure of the read-write conversion circuit provided in this embodiment.
  • the writing unit 221 includes: a sixth NMOS tube mn6, a seventh NMOS tube mn7, and an eighth NMOS tube mn8; the gate of the eighth NMOS tube mn8 and the gate of the sixth NMOS tube mn6 receive the writing control signal Wr,
  • the eighth NMOS transistor mn8 is electrically connected to the first data line Ldat and the second data line Gdat in response to the write control signal Wr, the gate of the seventh NMOS transistor mn7 is electrically connected to the second data line Gdat, and the seventh NMOS transistor mn7 drains
  • the electrode is electrically connected to the first complementary data line Ldat#, the source of the seventh NMOS transistor mn7 is electrically connected to the drain of the sixth NMOS transistor mn6, and the source of the sixth NMOS transistor mn6 is grounded.
  • the reading unit 211 includes: a tenth NMOS transistor mn10 and a twelfth NMOS transistor mn12; the gate of the twelfth NMOS transistor mn12 receives the read control signal Rd; the drain of the twelfth NMOS transistor mn12 and the second The data line Gdat is electrically connected, the source of the twelfth NMOS transistor mn12 is electrically connected to the drain of the tenth NMOS transistor mn10, the gate of the tenth NMOS transistor mn10 is electrically connected to the first complementary data line Ldat#, the tenth NMOS transistor mn10 The source is grounded.
  • the read-write conversion circuit may further include: a pre-charging module 203.
  • the precharge module 203 includes: a third PMOS tube mp3, a fourth PMOS tube mp4, and a fifth PMOS tube mp5, a gate of the third PMOS tube mp3, a gate of the fourth PMOS tube mp4, and a gate of the fifth PMOS tube mp5 Receiving the precharge control signal Eq; the source of the third PMOS tube mp3 and the source of the fourth PMOS tube mp4 are connected to the working power supply VDD, the drain of the third PMOS tube mp3 is electrically connected to the first data line Ldat; the drain of the fourth PMOS tube mp4 It is electrically connected to the first complementary data line Ldat#; the fifth PMOS transistor mp5 is electrically connected to the first data line Ldat and the first complementary data line Ldat# in response to the precharge signal Eq.
  • the read-write conversion circuit provided in this embodiment can only be used for signal amplification during one of the read operation or the write operation period, and can also be used for signal amplification during the read operation and the write operation period. .
  • the “change to 0” or “1” mentioned above may include the following situations: for a certain data line (such as the first data line Ldat, the first complementary data line Ldat#, the first For the second data line Gdat or the second complementary data line Gdat#), if the pre-charged state is pre-charged to 0, then for the data line, the description of the next state “becomes 0" should be understood as “ Maintained at 0", if the pre-charged state is pre-charged to 1, then the "change to 1" described in the next state for the data line should be understood as “maintained at 1".
  • the second complementary data line Gdat# in the writing unit simultaneously affects the first data line Ldat and the first complementary data line Ldat#, or the second complementary data line Ldat#.
  • the two data lines Gdat affect the first data line Ldat and the first complementary data line Ldat# at the same time, so the writing operation speed of the memory using the read-write conversion circuit is faster.
  • an embodiment of the present application also provides a memory including the read-write conversion circuit in any of the foregoing embodiments.
  • 6 is a schematic structural diagram of a memory provided by an embodiment of this application
  • FIG. 7 is a partially enlarged schematic structural diagram of area A in FIG. 6.
  • the memory includes: a number of memory modules, each memory module includes a memory array 301 and a sense amplifier array 302, the sense amplifier array 302 includes a plurality of sense amplifiers 312, the memory array 301 includes a plurality of memory cells; Select signal line CSL; word line WL; read-write conversion circuit 300, read-write conversion circuit 300 is connected to the sensitive amplifier array 302, and read-write conversion circuit 302 includes a first data line Ldat, a first complementary data line Ldat#, a second Data line Gdat and second complementary data line Gdat#; row decoding circuit 303; column decoding circuit 304; driving circuit 305.
  • the number of the read-write conversion circuits 300 may be the same as the number of the sense amplifier arrays 302, and each read-write conversion circuit 300 is connected to the corresponding sense amplifier array 302.
  • the data in the memory array 301 corresponding to the word line WL is transferred to the sense amplifier 312, and the data is amplified by the sense amplifier 312, and then written back to the selected word line WL In the connected storage unit.
  • the column decoding circuit 304 selects the corresponding sensitive amplifier 312, and the data is transferred from the second data line Gdat and the second complementary data line Gdat# to the first data line Ldat and the first complementary data line through the read-write conversion circuit 300.
  • the data line Ldat# is then written into the corresponding sense amplifier 312 and the connected memory cell.
  • the read-write conversion circuit 300 not only has the function of signal transmission, but also can amplify the first data line Ldat and the first complementary data line Ldat#, which is beneficial to quickly connect the first data line Ldat and the first complementary data line Ldat#.
  • the signal of the data line Ldat# is separated.
  • the column decoding circuit 304 selects the corresponding sensitive amplifier 312, and transmits the data to the first data line Ldat and the first complementary data line Ldat#, and then transmits to the second data line Gdat and the second complementary data line Gdat via the read-write conversion circuit 300 #.
  • the read-write conversion circuit 300 can greatly increase the discrimination speed of the first data line Ldat and the first complementary data line Ldat#, and the data passes through the sensitive amplifier 312, the first data line Ldat and the first data line Ldat#. The transmission speed of the complementary data line Ldat# to the second data line Gdat and the second complementary data line Gdat# is improved.
  • the memory may have multiple pairs of second data lines and second complementary data lines; similarly In actual use, the memory may have multiple pairs of first data lines and first complementary data lines.
  • the memory can be DRAM, SRAM (Static Random-Access Memory, SRAM, static random access memory), MRAM (Magnetoresistive Random Access Memory, magnetic random access memory), FeRAM (Ferroelectric RAM, ferroelectric random access memory), PCRAM (Phase Change RAM, Phase change random access memory), NAND flash memory or NOR flash memory.
  • SRAM Static Random-Access Memory
  • SRAM static random access memory
  • MRAM Magneticoresistive Random Access Memory, magnetic random access memory
  • FeRAM Feroelectric RAM, ferroelectric random access memory
  • PCRAM Phase Change RAM, Phase change random access memory
  • NAND flash memory or NOR flash memory.

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Abstract

一种读写转换电路以及存储器。读写转换电路包括：经由列选择模块（100）与位线（BL）连接的第一数据线（Ldat），经由列选择模块（100）与互补位线（BL#）连接的第一互补数据线（Ldat#），第二数据线（Gdat）以及第二互补数据线（Gdat#），还包括：读写转换模块（101），响应于读写控制信号，在读写操作期间，第一数据线（Ldat）与第二数据线（Gdat）之间传输数据，第一互补数据线（Ldat#）与第二互补数据线（Gdat#）之间传输数据；放大模块（102），连接在第一数据线（Ldat）与第一互补数据线（Ldat#）之间，用于对第一数据线（Ldat）的数据以及第一互补数据线（Ldat#）的数据放大。

Description

读写转换电路以及存储器
交叉引用
本申请引用于2020年6月5日递交的名称为“读写转换电路以及存储器”的第202010504964.5号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体技术领域，特别涉及一种读写转换电路以及存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
DRAM分为双倍速率同步(Double Data Rate，DDR)动态随机存储器、GDDR(Graphics Double Data Rate)动态随机存储器、低功耗双倍速率同步(Low Power Double Data Rate，LPDDR)动态随机存储器。随着DRAM应用的领域越来越多，如DRAM越来越多地应用于移动领域，用户对于DRAM速度指标的要求越来越高。
然而，目前的DRAM在读写期间的数据传输速度仍有待提高。
申请内容
本申请实施例提供一种读写转换电路以及存储器，以解决读写操作期间数据传输速度慢的问题。
为解决上述问题，本申请实施例提供一种读写转换电路，包括：经由列选择模块与位线连接的第一数据线以及经由列选择模块与互补位线连接的第一互补数据线，第二数据线以及第二互补数据线，还包括：读写转换模块，响应于读写控制信号，在读写操作期间，所述第一数据线与所述第二数据线之间传输数据，所述第一互补数据线与所述第二互补数据线之间传输数据；放大模块，连接在所述第一数据线与所述第一互补数据线之间，用于对所述第一数据线的数据以及所述第一互补数据线的数据放大。
另外，所述放大模块包括：第一反相器，所述第一反相器的输入端与所述第一数据线电连接，所述第一反相器的输出端与所述第一互补数据线电连接；第二反相器，所述第二反相器的输入端与所述第一反相器的输出端以及所述第一互补数据线电连接，所述第二反相器的输出端与所述第一反相器的输入端以及所述第一数据线电连接。
另外，所述第一反相器包括：第一PMOS管以及第一NMOS管，所述第一PMOS管栅极以及所述第一NMOS管栅极连接且作为所述第一反相器的输入端，所述第一PMOS管源极与工作电源连接，所述第一PMOS管漏极与所述第一NMOS管漏极连接且作为所述第一反相器的输出端。
所述第二反相器包括：第二PMOS管以及第二NMOS管，所述第二PMOS 管栅极与所述第二NMOS管栅极连接且作为所述第二反相器的输入端，所述第二PMOS管源极与工作电源连接，所述第二PMOS管漏极与所述第二NMOS管漏极连接且作为所述第二反相器的输出端。
另外，所述第一NMOS管源极接地，所述第二NMOS管源极接地。
另外，所述读写转换模块包括：第一读写单元，响应于所述读写控制信号中的读取控制信号，将所述第一数据线的数据传输至所述第二数据线，或者，响应于所述读写控制信号中的写入控制信号，将所述第二数据线的数据传输至所述第一数据线；第二读写单元，响应于所述读取控制信号，将所述第一互补数据线的数据传输至所述第二互补数据线，或者，响应于所述写入控制信号，将所述第二互补数据线的数据传输至所述第一互补数据线。
另外，所述第一读写单元包括：第三NMOS管、第四NMOS管以及第五NMOS管；所述第三NMOS管栅极接收所述写入控制信号，所述第三NMOS管响应于所述写入控制信号电连接所述第一数据线和所述第二数据线；所述第四NMOS管栅极与所述第一互补数据线电连接，所述第四NMOS管漏极与所述第二数据线电连接，所述第四NMOS管源极与所述第五NMOS管漏极电连接，且所述第五NMOS管栅极接收所述读取控制信号。
另外，所述第二读写单元包括：第七NMOS管、第八NMOS管以及第九NMOS管；所述第七NMOS管栅极接收所述写入控制信号，所述第七NMOS管响应于所述写入控制信号电连接所述第一互补数据线和所述第二互补数据线；所述第八NMOS管栅极与所述第一数据线电连接，所述第八NMOS管漏极与所述第二互补数据线电连接，所述第八NMOS管源极与所述第九NMOS管漏极电连接，且所述第九NMOS管栅极接收所述读取控制信号。
另外，所述读写转换电路还包括：第六NMOS管，所述第六NMOS管栅极接收使能信号，所述第六NMOS管漏极与所述第一反相器以及所述第二反相器连接，且还与所述第五NMOS管源极电连接，所述第六NMOS管源极接地。
另外，所述放大模块还包括：使能NMOS管，所述使能NMOS管漏极与所述第一反相器以及所述第二反相器电连接，所述使能NMOS管栅极接收使能信号，且所述使能NMOS管源极接地。
另外，所述读写转换模块包括：读取单元，响应于所述读写控制信号中的读取控制信号，将所述第一数据线的数据传输至所述第二数据线，将所述第一互补数据线的数据传输至所述第二互补数据线；写入单元，响应于所述读写控制信号中的写入控制信号，将所述第二数据线的数据传输至所述第一数据线，将所述第二互补数据线的数据传输至所述第一互补数据线。
另外，所述写入单元包括：第六NMOS管、第七NMOS管以及第八NMOS管；所述第八NMOS管栅极以及所述第六NMOS管栅极接收所述写入控制信号，所述第八NMOS管响应于所述写入控制信号电连接所述第一数据线和所述第二数据线，所述第七NMOS管栅极与所述第二数据线电连接，所述第七NMOS管漏极与所述第一互补数据线电连接，所述第七NMOS管源极与所述第六NMOS管漏极电连接，所述第六NMOS管源极接地。
另外，所述写入单元还包括：第三NMOS管、第四NMOS管、第五NMOS管；所述第三NMOS管和所述第五NMOS管栅极接收所述写入控制信号，所述第三NMOS管响应于所述写入控制信号电连接所述第一互补数据线和所述第二互补数据线，所述第四NMOS管栅极与所述第二互补数据线电连接，所述 第四NMOS管漏极与所述第一数据线电连接，所述第四NMOS管源极与所述第五NMOS管漏极电连接，所述第五NMOS管源极接地。另外，所述读取单元包括：第十NMOS管以及第十二NMOS管；所述第十二NMOS管栅极接收所述读取控制信号；所述第十二NMOS管漏极与所述第二数据线电连接，所述第十二NMOS管源极与所述第十NMOS管漏极电连接，所述第十NMOS管栅极与所述第一互补数据线电连接，所述第十NMOS管源极接地。
另外，所述读取单元还包括：第九NMOS管以及第十一NMOS管；所述第九NMOS管栅极与所述第一数据线电连接，源极接地，漏极与所述第十一NMOS管源极电连接；所述第十一NMOS管栅极接收所述读取控制信号，所述第十一NMOS管漏极与所述第二互补数据线电连接。
另外，还包括：预充电模块，所述预充电模块连接在所述第一数据线与所述第一互补数据线之间，用于响应预充电控制信号，对所述第一数据线以及所述第一互补数据线进行预充电。
另外，所述预充电模块包括：第三PMOS管、第四PMOS管以及第五PMOS管，所述第三PMOS管栅极、所述第四PMOS管栅极以及所述第五PMOS管栅极接收预充电控制信号；所述第三PMOS管源极以及所述第四PMOS管源极接工作电源，所述第三PMOS管漏极与所述第一数据线电连接；所述第四PMOS管漏极与所述第一互补数据线电连接；所述第五PMOS管响应于所述预充电控制信号电连接所述第一数据线和所述第一互补数据线。
相应的，本申请实施例还提供一种存储器，包括上述的读写转换电路。
另外，所述存储器还包括：若干个存储模块，每一所述存储模块包括存储器阵列以及灵敏放大器阵列；所述读写转换电路与所述灵敏放大器阵列相连。
另外，所述存储器包括DRAM、SRAM、MRAM、FeRAM、PCRAM、NAND闪存或者NOR闪存。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
本申请实施例提供一种读写转换电路，包括经由列选择模块与位线连接的第一数据线，经由列选择模块与互补位线连接的第一互补数据线；读写转换模块用于响应于读取控制信号或者写入控制信号，在第一数据线以及第一互补数据线与第二数据线以及第二互补数据线之间传输数据；且还包括连接在第一数据线与第一互补数据线之间的放大模块，用于对第一数据线的数据以及第一互补数据线的数据放大。该放大模块的设置，有利于加速区分第一数据线以及第一互补数据线的数据信号，起到放大数据信号的作用，从而使得读写转换电路中数据传输的速度得到提升。
本申请提供的存储器包括上述结构性能优异的读写转换电路，相应的存储器具有传输速度快的优点。此外，由于放大模块的设置，使得存储器中读写转化电路对于存储器的驱动能力需求低，具体地，第一数据线以及第一互补数据线对于存储器中第一级放大器的驱动能力需求低，因而即使第一级放大器的面积减小仍能保证具有足够的驱动能力，满足器件小型化微型化的发展趋势。
附图说明
图1为本申请一实施例提供的读写转换电路的功能模块示意图；
图2为本申请一实施例提供的读写转换电路的电路结构示意图；
图3为本申请实施例提供的读写转换电路在读取操作期间的电路时序图；
图4为本申请另一实施例提供的读写转换电路的一种电路结构示意图；
图5为本申请另一实施例提供的读写转换电路的另一种电路结构示意图；
图6为本申请一实施例提供的存储器的结构示意图；
图7为图6中区域A局部放大结构示意图。
具体实施方式
在DRAM读取操作中，选中的字线(WL，Word Line)被激活后，对应存储单元中的数据会被传输至位线(BL，Bit Line)中，导致位线上的电压出现微弱地增加或减小。与位线连接的感测放大器，通常称为第一级放大器(FSA，first sense amplifier)，会根据此微弱信号将位线信号拉至0或1。列选择模块会依据列选择信号将选中位线上的0或1信号传输至局部数据线(LocalDataLine)上上，接着通过读写转换电路将局部数据线中的信号传输至全局数据线(GlobalDataLine)上。需要说明的是，前述0代表信号的电平为低电平，1代表信号的电平为高电平。
然而，为保证高的数据传输速度，对存储器第一级放大器的驱动性能要求高。例如，在读出数据时，列选择信号线(CSL，Column Select Line)的电平拉高以后，第一级放大器将会直接驱动局部数据线，若第一级放大器驱动能力不足，将极大地影响上拉或下拉局部数据线的电平的速度。然而，随着工艺更新和面积减小的要求，第一级放大器做的越来越小，相应第一级放大器的驱动能力却难以再提高。因此，为保证高数据传输能力，需要考虑如何降低局部数据线对第一级放大器的驱动能力的要求。
为解决上述问题，本申请实施例提供一种读写转换电路，第一数据线通过列选择模块与位线连接，第一互补数据线通过列选择模块与互补位线连接， 在第一数据线与第一互补数据线之间设置放大模块，用于放大第一数据线以及第一互补数据线的数据信号，以便于加速区分第一数据线以及第一互补数据线，例如使具有更低电压的第一数据线或第一互补数据线更快速地变为0，具有更高电压的第一数据线或第一互补数据线更快速地变为1，从而加速读取操作或者写入操作的数据传输，降低第一数据线以及第一互补数据线对于第一级放大器驱动能力的需求。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请一实施例提供的读写转换电路的功能模块示意图，图2为本申请一实施例提供的电路结构示意图。
结合参考图1及图2，本实施例中，读写转换电路包括：第一数据线Ldat和第一互补数据线Ldat#，第一数据线Ldat经由列选择模块100与位线BL连接，第一互补数据线Ldat#经由列选择模块100与互补位线BL#电连接，第二数据线Gdat#和第二互补数据线Gdat；读写转换模块101，响应于读写控制信号，在读写操作期间，第一数据线Ldat与第二数据线Gdat之间传输数据，第一互补数据线Ldat#与第二互补数据线Gdat#之间传输数据；放大模块102，连接在第一数据线Ldat与第一互补数据线Ldat#之间，用于对第一数据线Ldat的数据以及第一互补数据线Ldat#的数据放大。
放大模块102构成了对第一数据线Ldat信号放大以及第一互补数据线 Ldat#信号放大的电路，有助于加速区分第一数据线Ldat的电平与第一互补数据线Ldat#的电平，从而提高数据信号传输的速度，改善数据读写速度。此外，由于第一数据线Ldat和第一互补数据线Ldat#的数据信号得到放大，使得第一数据线Ldat和第一互补数据线Ldat#对于存储器中的第一级放大电路的驱动能力的需求降低，因而即使第一级放大电路的面积逐渐减小，该第一级放大电路对于第一数据线Ldat和第一互补数据线Ldat#而言仍具有足够的驱动能力，以便于在满足器件微型化发展趋势的同时，保证该读写转换电路具有良好的电学性能，进而提高包含该读写转换电路的存储器的存储性能。
以下将结合附图对本实施例提供的读写转换电路进行详细说明。
本实施例中，读取的数据或者写入的数据信号都是成对的，每对数据信号包括两个数据，在进行读写操作过程中，这两个数据中的一个数据为高电平信号，另一数据为低电平信号，因此，读写转换电路至少包括一对第一数据线Ldat以及第一互补数据线Ldat#，至少包括一对第二数据线Gdat以及第二互补数据线Gdat#。具体地，读写转换电路在读取操作期间，数据经由第一数据线Ldat以及第一互补数据线Ldat#传输至第二数据线Gdat以及第二互补数据线Gdat#；读写转换电路在写入操作期间，数据经由第二数据线Gdat以及第二互补数据线Gdat#传输至第一数据线Ldat以及第一互补数据线Ldat#。
第一数据线Ldat为局部数据线(local data line，也称为本地数据线)，第一互补数据线Ldat#为互补局部数据线；第二数据线Gdat为全局数据线(global data line)，第二互补数据线Gdat#为互补全局数据线。
在一个具体实施例中，读写转换电路应用于存储器中，存储器包括列选择模块100，第一数据线Ldat通过列选择模块100与位线BL连接，第一互补 数据线Ldat#通过列选择模块100与互补位线BL#连接。通过列选择模块100选中进行读取操作或者写入操作的存储单元，相应的，与该选中的存储单元连接的位线BL与第一数据线Ldat之间传输信号，与该选中的存储单元连接的互补位线BL#与第一互补数据线Ldat#之间传输信号。
读写控制信号包括读取控制信号Rd和写入控制信号Wr。在读写操作期间，响应于读取控制信号Rd，读写转换模块101将第一数据线Ldat以及第一互补数据线Ldat#的数据传输至第二数据线Gdat以及第二互补数据线Gdat#，或者，响应于写入控制信号Wr，读写转换模块101将第二数据线Gdat以及第二互补数据线Gdat#的数据传输至第一数据线Ldat以及第一互补数据线Ldat#。
本实施例中，读写转换模块101包括：第一读写单元111，响应于读取控制信号Rd，将第一数据线Ldat的数据传输至第二数据线Gdat，或者，响应于写入控制信号Wr，将第二数据线Gdat的数据传输至第一数据线Ldat；第二读写单元121，响应于读取控制信号Rd，将第一互补数据线Ldat#的数据传输至第二互补数据线Gdat#，或者，响应于写入控制信号Wr，将第二互补数据线Gdat#的数据传输至第一互补数据线Ldat#。
在一个具体实施例中，第一读写单元111可以包括：第三NMOS管MN3、第四NMOS管MN4以及第五NMOS管MN5；第三NMOS管MN3栅极接收写入控制信号Wr，第三NMOS管MN3响应于写入控制信号Wr电连接第一数据线Ldat和第二数据线Gdat；第四NMOS管MN4栅极与第一互补数据线Ldat#电连接，第四NMOS管MN4漏极与第二数据线Gdat电连接，第四NMOS管MN4源极与第五NMOS管MN5漏极电连接，且第五NMOS管MN5栅极接收读取控制信号Rd。
第二读写单元121可以包括：第七NMOS管MN7、第八NMOS管MN8以及第九NMOS管MN9；第七NMOS管MN7栅极接收写入控制信号Wr，第七NMOS管MN7响应于写入控制信号Wr电连接第一互补数据线Ldat#和第二互补数据线Gdat#；第八NMOS管MN8栅极与第一数据线Ldat电连接，漏极与第二互补数据线Gdat#电连接，源极与第九NMOS管MN9漏极电连接，且第九NMOS管MN9栅极接收读取控制信号Rd。
本实施例中，第一读写单元111与第二读写单元121的电路结构相同，即第一读写单元111包括的各晶体管的连接关系与第二读写单元121包含的各晶体管的连接关系相同。在其他实施例中，第一读写单元与第二读写单元的电路结构图也可以不同，只要在读写操作期间能够实现数据传输即可。
本实施例中，读写转换电路还可以包括：第六NMOS管MN6，第六NMOS管MN6栅极接收使能信号En，且第六NMOS管MN6漏极与第五NMOS管MN5源极以及第九NMOS管MN9源极电连接，第六NMOS管MN6源极接地。
在读取操作期间，通过列选择模块100，数据首先从被选择的位线BL与互补位线BL#传输至第一数据线Ldat与第一互补数据线Ldat#。而经由放大模块102的放大，第一数据线Ldat的电平与第一互补数据线Ldat#的电平会快速达到低或高电平。然后数据将从第一数据线Ldat以及第一互补数据线Ldat#传输至第二数据线Gdat以及第二互补数据线Gdat#。读取控制信号Rd为高电平，写入控制信号Wr为低电平，第三NMOS管MN3以及第七NMOS管MN7截止，第五NMOS管MN5以及第九NMOS管MN9导通；当第一数据线Ldat为高电平、第一互补数据线Ldat#为低电平且使能信号En为高电平时，第八NMOS管MN8以及第六NMOS管MN6导通，数据从第一互补数据线Ldat# 传输至第二互补数据线Gdat#，第二互补数据线Gdat#变为0，第二数据线Gdat为1；当第一数据线Ldat为低电平且第一互补数据线Ldat#为高电平时，第四NMOS管MN4以及第六NMOS管MN6导通，数据从第一数据线Ldat传输至第二数据线Gdat，第二数据线Gdat变为0，第二互补数据线Gdat#为1。第二数据线Gdat变为0指的是第二数据线Gdat的电平由高电平变为低电平，第二互补数据线Gdat#为1指的是第二互补数据线Gdat#的电平为高电平。
本申请实施例中所称的“为1”指的是电平为高电平，“为0”指的是电平为低电平，“变为1”指的是电平变为高电平，“变为0”指的是电平变为低电平。
在写入操作期间，数据传输方向与读取操作期间的数据传输方向相反，即数据从第二数据线Gdat以及第二互补数据线Gdat#传输至第一数据线Ldat以及第一互补数据线Ldat#。
参考图2，本实施例中，放大模块102包括：第一反相器112，第一反相器112的第一输入端in1与第一数据线Ldat电连接；第二反相器122，第二反相器122的第二输入端in2与第一反相器112的第一输出端out1以及第一互补数据线Ldat#电连接，第二反相器122的第二输出端out2与第一反相器112的第一输入端in1以及第一数据线Ldat电连接。
在读取期间，由于放大模块102的设置，使得数据从位线BL传输至第一数据线Ldat的传输速度得到提升，数据从互补位线BL#传输到第一互补数据线Ldat#的传输速度得到提升，存储器对第一级放大器的驱动需求降低。具体地，以位线BL的数据为高电平，互补位线BL#的数据为低电平为例，由于第一反相器112的第一输入端in1连接第二反相器122的第二输出端out2，第一 反相器112的第一输出端out1连接第二反相器122的第二输入端in2，在位线BL以及互补位线BL#传输至第一数据线Ldat以及第一互补数据线Ldat#期间，放大模块102的设置会使得具备更低电平的第一互补数据线Ldat#更快速地下拉到“0”，或者使得具备更高电平的第一数据线Ldat更快速地上拉到“1”。因此，第一数据线Ldat的电平被上拉的速度得到提高，第一互补数据线Ldat#的电平被下拉的速度也得到提高，因而第一数据线Ldat以及第一互补数据线Ldat#对第一级放大器的驱动需求降低。
同时，由于第一数据线Ldat的电平和第一互补数据线Ldat#的电平可以更快速地达到高电平或低电平，则可以更早地将第一数据线Ldat和第一互补数据线Ldat#传输至第二数据线Gdat和第二互补数据线Gdat#，这样在读出数据时，数据从第一数据线Ldat以及第一互补数据线Ldat#传输至第二数据线Gdat以及第二互补数据线Gdat#的速度得以提高。
相应的，在写入期间，放大模块102也能对第一数据线Ldat以及第一互补数据线Ldat#起到放大的作用，提升数据从第二数据线Gdat以及第二互补数据线Gdat#传输至第一数据线Ldat以及第一互补数据线Ldat#的速度。
具体地，第一反相器112包括：第一PMOS管MP1以及第一NMOS管MN1，第一PMOS管MP1栅极以及第一NMOS管MN1栅极电连接且作为第一反相器的第一输入端in1，第一PMOS管MP1源极与工作电源VDD连接，第一PMOS管MP1漏极与第一NMOS管MN1漏极连接且作为第一反相器112的第一输出端out1。
第二反相器122包括：第二PMOS管MP2以及第二NMOS管MN2，第二PMOS管MP2栅极与第二NMOS管MN2栅极连接且作为第二反相器122 的第二输入端in2，第二PMOS管MP2源极与工作电源VDD连接，第二PMOS管MP2漏极与第二NMOS管MN2漏极连接且作为第二反相器122的第二输出端out2。
第一PMOS管MP1、第一NMOS管MN1、第二PMOS管MP2以及第二NMOS管MN2构成放大模块102。
此外，第一反相器112以及第二反相器122还与第六NMOS管漏极连接。具体地，第一NMOS管MN1源极以及第二NMOS管MN2源极与第六NMOS管MN6漏极连接。在另一些实施例中，第一NMOS管MN1源极接地，第二NMOS管MN2源极接地。
本实施例中，参考图2，读写转换电路还可以包括：预充电模块103，预充电模块103连接在第一数据线Ldat与第一互补数据线Ldat#之间，用于响应于预充电控制信号Eq，对第一数据线Ldat以及第一互补数据线Ldat#线预充电。
具体地，预充电模块103包括：第三PMOS管MP3、第四PMOS管MP4以及第五PMOS管MP5；第三PMOS管MP3栅极、第四PMOS管MP4栅极以及第五PMOS管MP5栅极接收预充电控制信号Eq；第三PMOS管MP3源极以及第四PMOS管MP4源极接工作电源VDD，第三PMOS管MP3漏极与第一数据线Ldat电连接；第四PMOS管MP4漏极与第一互补数据线Ldat#电连接；第五PMOS管MN5响应于预充电控制信号Eq电连接第一数据线Ldat和第一互补数据线Ldat#。
图3为未增加放大模块的读写转换电路与本实施例提供的读写转换电路在读取操作期间的电路时序图，为便于区别，电路时序图中，对于时序有变化的同一信号而言，虚线表征未增加放大模块对应的时序，实线表征本实施例对 应的时序，CSL表示列选择信号。
如图3所示，相较于未增加放大模块的读写转换电路而言，本实施例中，第一数据线Ldat和第一互补数据线Ldat#的数据提前t时间达到高电平或低电平，也就是说，本实施例中，数据可提前t时间被传输，读取控制信号Rd的上升沿时刻可以从A1时刻提前至A2时刻，且A2时刻与A1时刻之差为t。
本申请另一实施例还提供一种读写转换电路，该实施例中读写转换模块的具体电路结构与前一实施例不同。以下将结合附图对本实施提供的读写转换电路进行说明，需要说明的是，与前一实施例相同或者相应的部分，请参考前一实施例的详细说明，以下将不做详细赘述。
图4为本申请另一实施例提供的读写转换电路的一种电路结构示意图。
参考图4，本实施例中，读写转换电路包括：第一数据线Ldat、第一互补数据线Ldat#、第二数据线Gdat、第二互补数据线Gdat#、读写转换模块以及放大模块202。
以下将结合附图对本实施例提供的读写转换电路进行详细说明。
放大模块202包括第一反相器212和第二反相器222，第一反相器212包括第一PMOS管mp1和第一NMOS管mn1，第二反相器222包括第二PMOS管mp2和第二NMOS管mn2。有关第一反相器和第二反相器的详细描述，可参考前述实施例的详细说明。
与前一实施例不同的是，本实施例中，放大模块202还包括：使能NMOS管mn，使能NMOS管mn漏极与第一反相器212以及第二反相器222电连接，使能NMOS管mn栅极接收使能信号En，且使能NMOS管mn源极接地。
具体地，使能NMOS管mn漏极与第一NMOS管mn1源极以及第二 NMOS管mn2源极电连接。
第一PMOS管mp1、第一NMOS管mn1、第二PMOS管mp2、第二NMOS管mn2以及使能NMOS管mn构成放大模块202，用于对第一数据线Ldat以及第一互补数据线Ldat#的数据放大。
本实施例中，读写转换模块包括：读取单元211，响应于读取控制信号Rd，将第一数据线Ldat以及第一互补数据线Ldat#的数据分别传输至第二数据线Gdat以及第二互补数据线Gdat#；写入单元221，响应于写入控制信号Wr，将第二数据线Gdat以及第二互补数据线Gdat#的数据分别传输至第一数据线Ldat以及第一互补数据线Ldat#。
具体地，写入单元221包括：第三NMOS管mn3、第四NMOS管mn4、第五NMOS管mn5、第六NMOS管mn6、第七NMOS管mn7以及第八NMOS管mn8。
第三NMOS管mn3漏极与第一反相器212的第一输出端out1电连接，第三NMOS管mn3栅极以及第五NMOS管mn5栅极接收写入控制信号Wr，第三NMOS管mn3响应于写入控制信号Wr电连接第一互补数据线Ldat#和第二互补数据线Gdat#，第四NMOS管mn4栅极与第二互补数据线Gdat#电连接，第四NMOS管mn4漏极与第一数据线Ldat电连接；第四NMOS管mn4源极与第五NMOS管漏mn5漏极电连接，第五NMOS管mn5源极接地；第八NMOS管mn8漏极与第二反相器222的第二输出端out2电连接，第八NMOS管mn8栅极以及第六NMOS管mn6栅极接收写入控制信号Wr，第八NMOS管mn8响应于写入控制信号Wr电连接第一数据线Ldat和第二数据线Gdat；第七NMOS管mn7栅极与第二数据线Gdat电连接，第七NMOS管mn7漏极与第一 互补数据线Ldat#电连接，第七NMOS管mn7源极与第六NMOS管mn6漏极电连接，第六NMOS管mn6源极接地。
在写入操作期间，写入单元221用于将第二数据线Gdat数据传输到第一数据线Ldat，将第二互补数据线Gdat#数据传输到第一互补数据线Ldat#。
具体地，写入操作期间，写入控制信号Wr为高电平，第三NMOS管mn3、第五NMOS管mn5、第六NMOS管mn6以及第八NMOS管mn8导通，第二互补数据线Gdat#为高电平时第四NMOS管mn4导通且第七NMOS管mn7截止，第二互补数据线Gdat#数据传输至第一互补数据线Ldat#，第一数据线Ldat变为0，第一互补数据线Ldat#变为1。由于放大模块202的设置，使得第一数据线Ldat变为0所需的时间缩短，从而加速区分第一数据线Ldat以及第一互补数据线Ldat#的速度，以便于提高将第一数据线Ldat以及第一互补数据线Ldat#数据写入相应存储单元的速度。
第二互补数据线Gdat#为低电平时第二数据线Gdat为高电平，第四NMOS管mn4截止且第七NMOS管mn7导通，第二数据线Gdat数据传输至第一数据线Ldat，第一互补数据线Ldat#变为0，第一数据线Ldat变为1。由于放大模块202的设置，使得第一互补数据线Ldat#变为0所需的时间缩短，从而加速区分第一数据线Ldat以及第一互补数据线Ldat#的速度，以便于提高将第一数据线Ldat以及第一互补数据线Ldat#数据写入相应存储单元的速度。
具体地，读取单元211包括：第九NMOS管mn9、第十NMOS管mn10、第十一NMOS管mn11以及第十二NMOS管mn12。
第九NMOS管mn9栅极与第一数据线Ldat电连接，源极接地，漏极与第十一NMOS管mn11源极电连接，第十一NMOS管mn11以及第十二NMOS 管mn12栅极接收写入控制信号Rd，第十一NMOS管mn11漏极与第二互补数据线Gdat#电连接；
第十二NMOS管mn12栅极接收读取控制信号Rd，第十二NMOS管mn12漏极与第二数据线Gdat电连接，第十二NMOS管mn12源极与第十NMOS管mn10漏极电连接，第十NMOS管mn10栅极与第一互补数据线Ldat#电连接，第十NMOS管mn10源极接地。
在读取操作期间，读取单元211用于将第一数据线Ldat数据传输到第二数据线Gdat，将第一互补数据线Ldat#数据传输到第二互补数据线Gdat#。
具体地，在读取操作期间，读取控制信号Rd为高电平，第十一NMOS管mn11以及第十二NMOS管mn12导通，第一数据线Ldat为高电平时第九NMOS管mn9导通且第十NMOS管mn10截止，第一数据线Ldat数据传输至第一数据线Gdat，第二互补数据线Gdat#变为0，第二数据线Gdat变为1；第一数据线Ldat为低电平时第九NMOS管截止且第十NMOS管导通，第一互补数据线Ldat#数据传输至第二互补数据线Gdat#，第二互补数据线Gdat#变为1，第二数据线Gdat变为0。由于放大模块202的设置，使得第一数据线Ldat或者第一互补数据线Ldat#由高电平变更为低电平的反应时间缩短，因而第二数据线Gdat以及第二互补数据线Gdat#跟随变化的速度得到提升，从而提升数据传输速度。
需要说的是，图4涉及的电路图也可以有其他合适的变形，例如，第九NMOS管mn9和第十NMOS管mn10栅极接收读取控制信号Rd，第十一NMOS管mn11栅极与第一数据线Ldat连接，第十二NMOS管mn12栅极与第一互补数据线Ldat#连接；或者，第五NMOS管mn5源极以及第六NMOS管mn6源 极电连接至使能NMOS管mn的漏极。
可以理解的是，图4所示的例子中，写入单元221和读取单元211均采用双端式传输模式，即第一数据线Ldat以及第一互补数据线Ldat#均连接至写入单元221，第二数据线Gdat以及第二互补数据线Gdat#均连接至读取单元211。在其他实施例中，写入单元或者读取单元中的至少一个也可以采用单端式传输模式，即第一数据线和第一互补数据线中的一者连接至写入单元，第二数据线以及第二互补数据线中的一者连接至读取单元。以写入单元和读取单元均采取单端式传输模式为例，图5为本实施例提供的读写转换电路的另一种电路结构示意图。
参考图5，写入单元221包括：第六NMOS管mn6、第七NMOS管mn7以及第八NMOS管mn8；第八NMOS管mn8栅极以及第六NMOS管mn6栅极接收写入控制信号Wr，第八NMOS管mn8响应于写入控制信号Wr电连接第一数据线Ldat和所述第二数据线Gdat，第七NMOS管mn7栅极与第二数据线Gdat电连接，第七NMOS管mn7漏极与第一互补数据线Ldat#电连接，第七NMOS管mn7源极与第六NMOS管mn6漏极电连接，第六NMOS管mn6源极接地。
继续参考图5，读取单元211包括：第十NMOS管mn10以及第十二NMOS管mn12；第十二NMOS管mn12栅极接收读取控制信号Rd；第十二NMOS管mn12漏极与第二数据线Gdat电连接，第十二NMOS管mn12源极与第十NMOS管mn10漏极电连接，第十NMOS管mn10栅极与第一互补数据线Ldat#电连接，所述第十NMOS管mn10源极接地。
本实施例中，参考图4，读写转换电路还可以包括：预充电模块203。
具体地，预充电模块203包括：第三PMOS管mp3、第四PMOS管mp4以及第五PMOS管mp5，第三PMOS管mp3栅极、第四PMOS管mp4栅极以及第五PMOS管mp5栅极接收预充电控制信号Eq；第三PMOS管mp3源极以及第四PMOS管mp4源极接工作电源VDD，第三PMOS管mp3漏极与第一数据线Ldat电连接；第四PMOS管mp4漏极与第一互补数据线Ldat#电连接；第五PMOS管mp5响应于预充电信号Eq电连接第一数据线Ldat与第一互补数据线Ldat#。
可以理解的是，本实施例提供的读写转换电路，可以仅用于读取操作或者写入操作期间中的一者的信号放大，也可以用于读取操作以及写入操作期间的信号放大。
另外，需要说明的是，上述提及的“变为0”或者变为“1”可以包括如下的情况：对于某一数据线(如第一数据线Ldat、第一互补数据线Ldat#、第二数据线Gdat或者第二互补数据线Gdat#)而言，如果预充电后的状态为预充电至0，那么对于该数据线而言对下一个状态描述的“变为0”应理解为“维持为0”，如果预充电后的状态为预充电至1，那么对于该数据线而言对下一个状态描述的“变为1”应理解为“维持为1”。
与前一实施例相比，本实施例提供的读写转换电路中，由于写入单元中的第二互补数据线Gdat#同时影响第一数据线Ldat以及第一互补数据线Ldat#，或者第二数据线Gdat同时影响第一数据线Ldat以及第一互补数据线Ldat#，因而采用该读写转换电路的存储器的写入操作速度更快。
相应的，本申请实施例还提供一种存储器，包括上述任一实施例中的读写转换电路。图6为本申请一实施例提供的存储器的结构示意图，图7为图6 中区域A的局部放大结构示意图。
参考图6及图7，存储器包括：若干个存储模块，每一存储模块包括存储器阵列301以及灵敏放大器阵列302，灵敏放大器阵列302包括多个灵敏放大器312，存储器阵列301包括多个存储单元；列选择信号线CSL；字线WL；读写转换电路300，读写转换电路300与灵敏放大器阵列302相连，且读写转换电路302包括第一数据线Ldat、第一互补数据线Ldat#、第二数据线Gdat以及第二互补数据线Gdat#；行译码电路303；列译码电路304；驱动电路305。具体地，读写转换电路300的数量可以与灵敏放大器阵列302的数量相同，且每一读写转换电路300与对应的灵敏放大器阵列302相连。
以下结合存储器的工作机理对存储器进行说明。
当一根字线WL经行译码电路303选中后，该字线WL对应的存储器阵列301中的数据传输至灵敏放大器312，数据经灵敏放大器312放大后，再回写至选中的字线WL连接的存储单元中。
数据需要写入时，列译码电路304选中相应的灵敏放大器312，数据由第二数据线Gdat以及第二互补数据线Gdat#经过读写转换电路300传输至第一数据线Ldat以及第一互补数据线Ldat#，再写入对应的灵敏放大器312以及相连接的存储单元。在写入期间，读写转换电路300不仅具有信号传输的作用，且还能够对第一数据线Ldat以及第一互补数据线Ldat#进行放大，有利于迅速将第一数据线Ldat以及第一互补数据线Ldat#的信号分开。如此，不仅有利于提高数据传输速度，且还降低了读写转换电路300对于灵敏放大器312驱动能力的要求，使得具有较小面积的灵敏放大器312即可满足驱动能力的要求，大大的降低了灵敏放大器312的工艺难度，且符合器件小型化微型化的发展趋势。
数据读出时，数据传输的方向与数据写入时的传输方向相反。列译码电路304选中相应的灵敏放大器312，数据传输至第一数据线Ldat以及第一互补数据线Ldat#，再经由读写转换电路300传输至第二数据线Gdat以及第二互补数据线Gdat#。同样的，在数据读出时，读写转换电路300可以极大的提升第一数据线Ldat以及第一互补数据线Ldat#的区分速度，数据经由灵敏放大器312、第一数据线Ldat和第一互补数据线Ldat#传输至第二数据线Gdat以及第二互补数据线Gdat#的速度得到提升。
可以理解的是，图6及图7中仅示意出一对第二数据线以及第二互补数据线，在实际使用时，存储器中可以具有多对第二数据线以及第二互补数据线；同样的，实际使用时存储器可以具有多对第一数据线以及第一互补数据线。
该存储器可以为DRAM、SRAM(Static Random-Access Memory，SRAM，静态随机存储器)、MRAM(Magnetoresistive Random Access Memory，磁性随机存储器)、FeRAM(Ferroelectric RAM，铁电随机存储器)、PCRAM(Phase Change RAM，相变随机存储器)、NAND闪存或者NOR闪存等存储器。如前述分析可知，本实施例提供的存储器具有数据传输速度快的优势，对于感测放大器的驱动能力的需求低，有利于满足器件微型化的发展趋势。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种读写转换电路，其中，包括：经由列选择模块与位线连接的第一数据线以及经由列选择模块与互补位线连接的第一互补数据线，第二数据线以及第二互补数据线，还包括：
    读写转换模块，响应于读写控制信号，在读写操作期间，所述第一数据线与所述第二数据线之间传输数据，所述第一互补数据线与所述第二互补数据线之间传输数据；
    放大模块，连接在所述第一数据线与所述第一互补数据线之间，用于对所述第一数据线的数据以及所述第一互补数据线的数据放大。
  2. 如权利要求1所述的读写转换电路，其中，所述放大模块包括：第一反相器，所述第一反相器的第一输入端与所述第一数据线电连接，所述第一反相器的第一输出端与所述第一互补数据线电连接；第二反相器，所述第二反相器的第二输入端与所述第一反相器的第一输出端以及所述第一互补数据线电连接，所述第二反相器的第二输出端与所述第一反相器的第一输入端以及所述第一数据线电连接。
  3. 如权利要求2所述的读写转换电路，其中，所述第一反相器包括：第一PMOS管以及第一NMOS管，所述第一PMOS管栅极以及所述第一NMOS管栅极连接且作为所述第一反相器的第一输入端，所述第一PMOS管源极与工作电源连接，所述第一PMOS管漏极与所述第一NMOS管漏极连接且作为所述第一反相器的第一输出端。
  4. 如权利要求3所述的读写转换电路，其中，所述第二反相器包括：第二PMOS管以及第二NMOS管，所述第二PMOS管栅极与所述第二NMOS管栅极连 接且作为所述第二反相器的第二输入端，所述第二PMOS管源极与工作电源连接，所述第二PMOS管漏极与所述第二NMOS管漏极连接且作为所述第二反相器的第二输出端。
  5. 如权利要求4所述的读写转换电路，其中，所述第一NMOS管源极接地，所述第二NMOS管源极接地。
  6. 如权利要求4所述的读写转换电路，其中，所述读写转换模块包括：第一读写单元，响应于所述读写控制信号中的读取控制信号，将所述第一数据线的数据传输至所述第二数据线，或者，响应于所述读写控制信号中的写入控制信号，将所述第二数据线的数据传输至所述第一数据线；第二读写单元，响应于所述读取控制信号，将所述第一互补数据线的数据传输至所述第二互补数据线，或者，响应于所述写入控制信号，将所述第二互补数据线的数据传输至所述第一互补数据线。
  7. 如权利要求6所述的读写转换电路，其中，所述第一读写单元包括：第三NMOS管、第四NMOS管以及第五NMOS管；所述第三NMOS管栅极接收所述写入控制信号，所述第三NMOS管响应于所述写入控制信号电连接所述第一数据线和所述第二数据线；所述第四NMOS管栅极与所述第一互补数据线电连接，所述第四NMOS管漏极与所述第二数据线电连接，所述第四NMOS管源极与所述第五NMOS管漏极电连接，且所述第五NMOS管栅极接收所述读取控制信号。
  8. 如权利要求6所述的读写转换电路，其中，所述第二读写单元包括：第七NMOS管、第八NMOS管以及第九NMOS管；所述第七NMOS管栅极接收所述写入控制信号，所述第七NMOS管响应于所述写入控制信号电连接 所述第一互补数据线和所述第二互补数据线；所述第八NMOS管栅极与所述第一数据线电连接，所述第八NMOS管漏极与所述第二互补数据线电连接，所述第八NMOS管源极与所述第九NMOS管漏极电连接，且所述第九NMOS管栅极接收所述读取控制信号。
  9. 如权利要求7所述的读写转换电路，其中，所述读写转换电路还包括：第六NMOS管，所述第六NMOS管栅极接收使能信号，所述第六NMOS管漏极与所述第一反相器以及所述第二反相器连接，且还与所述第五NMOS管源极电连接，所述第六NMOS管源极接地。
  10. 如权利要求5所述的读写转换电路，其中，所述放大模块还包括：使能NMOS管，所述使能NMOS管漏极与所述第一反相器以及所述第二反相器电连接，所述使能NMOS管栅极接收使能信号，且所述使能NMOS管源极接地。
  11. 如权利要求5所述的读写转换电路，其中，所述读写转换模块包括：读取单元，响应于所述读写控制信号中的读取控制信号，将所述第一数据线的数据传输至所述第二数据线，将所述第一互补数据线的数据传输至所述第二互补数据线；写入单元，响应于所述读写控制信号中的写入控制信号，将所述第二数据线的数据传输至所述第一数据线，将所述第二互补数据线的数据传输至所述第一互补数据线。
  12. 如权利要求11所述的读写转换电路，其中，所述写入单元包括：第六NMOS管、第七NMOS管以及第八NMOS管；所述第八NMOS管栅极以及所述第六NMOS管栅极接收所述写入控制信号，所述第八NMOS管响应于所述写入控制信号电连接所述第一数据线和所述第二数据线，所述第七NMOS管栅极与所述第二数据线电连接，所述第七NMOS管漏极与所述第一互补数 据线电连接，所述第七NMOS管源极与所述第六NMOS管漏极电连接，所述第六NMOS管源极接地。
  13. 如权利要求12所述的读写转换电路，其中，所述写入单元还包括：第三NMOS管、第四NMOS管、第五NMOS管；所述第三NMOS管和所述第五NMOS管栅极接收所述写入控制信号，所述第三NMOS管响应于所述写入控制信号电连接所述第一互补数据线和所述第二互补数据线，所述第四NMOS管栅极与所述第二互补数据线电连接，所述第四NMOS管漏极与所述第一数据线电连接，所述第四NMOS管源极与所述第五NMOS管漏极电连接，所述第五NMOS管源极接地。
  14. 如权利要求12所述的读写转换电路，其中，所述读取单元包括：第十NMOS管以及第十二NMOS管；所述第十二NMOS管栅极接收所述读取控制信号；所述第十二NMOS管漏极与所述第二数据线电连接，所述第十二NMOS管源极与所述第十NMOS管漏极电连接，所述第十NMOS管栅极与所述第一互补数据线电连接，所述第十NMOS管源极接地。
  15. 如权利要求14所述的读写转换电路，其中，所述读取单元还包括：第九NMOS管以及第十一NMOS管；所述第九NMOS管栅极与所述第一数据线电连接，源极接地，漏极与所述第十一NMOS管源极电连接；所述第十一NMOS管栅极接收所述读取控制信号，所述第十一NMOS管漏极与所述第二互补数据线电连接。
  16. 如权利要求1所述的读写转换电路，其中，还包括：预充电模块，所述预充电模块连接在所述第一数据线与所述第一互补数据线之间，用于响应预充电控制信号，对所述第一数据线以及所述第一互补数据线进行预充电。
  17. 如权利要求16所述的读写转换电路，其中，所述预充电模块包括：第三PMOS管、第四PMOS管以及第五PMOS管，所述第三PMOS管栅极、所述第四PMOS管栅极以及所述第五PMOS管栅极接收预充电控制信号；
    所述第三PMOS管源极以及所述第四PMOS管源极接工作电源，所述第三PMOS管漏极与所述第一数据线电连接；所述第四PMOS管漏极与所述第一互补数据线电连接；所述第五PMOS管响应于所述预充电控制信号电连接所述第一数据线和所述第一互补数据线。
  18. 一种存储器，其中，包括如权利要求1所述的读写转换电路。
  19. 如权利要求18所述的存储器，其中，所述存储器还包括：若干个存储模块，每一所述存储模块包括存储器阵列以及灵敏放大器阵列；所述读写转换电路与所述灵敏放大器阵列相连。
  20. 如权利要求18所述的存储器，其中，所述存储器包括DRAM、SRAM、MRAM、FeRAM、PCRAM、NAND闪存或者NOR闪存。
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