WO2021253870A1 - 半导体集成电路以及存储器 - Google Patents

半导体集成电路以及存储器 Download PDF

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WO2021253870A1
WO2021253870A1 PCT/CN2021/078505 CN2021078505W WO2021253870A1 WO 2021253870 A1 WO2021253870 A1 WO 2021253870A1 CN 2021078505 W CN2021078505 W CN 2021078505W WO 2021253870 A1 WO2021253870 A1 WO 2021253870A1
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Prior art keywords
data line
read
data
signal
local
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PCT/CN2021/078505
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English (en)
French (fr)
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尚为兵
陈继兴
武贤君
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长鑫存储技术有限公司
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Priority to EP21819709.3A priority Critical patent/EP3971897A4/en
Priority to US17/396,688 priority patent/US11848045B2/en
Publication of WO2021253870A1 publication Critical patent/WO2021253870A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor integrated circuit and a memory.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor storage device commonly used in computers, which consists of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • DRAM Dynamic Random Access Memory
  • DRAM is divided into double rate synchronous (Double Data Rate, DDR) dynamic random access memory, GDDR (Graphics Double Data Rate) dynamic random access memory, and low power double rate synchronous (Low Power Double Data Rate, LPDDR) dynamic random access memory.
  • DDR Double Data Rate
  • GDDR Graphics Double Data Rate
  • LPDDR Low Power Double Data Rate
  • the embodiments of the present application provide a semiconductor integrated circuit and a memory to reduce the number of data lines.
  • an embodiment of the present application provides a semiconductor integrated circuit, a first data line connected to a bit line via a column selection module, a first complementary data line connected to a complementary bit line via a column selection module, and a second data line ,
  • a reference data line, the reference data line is used to provide a reference reference signal, further comprising: a local read-write conversion module, in response to the read-write control signal, during a read-write operation, the first data line and the second Data is transmitted between the data lines, and data is transmitted between the first complementary data line and the second data line; the amplifying module is used to receive the data signal of the second data line and the reference signal, and to The data signal of the second data line is amplified, and the reference reference signal serves as a reference for amplifying the data signal of the second data line.
  • the reference data line has a fixed potential.
  • a reference reference module which outputs the reference reference signal to the reference data line in response to a read control signal in the read/write control signal, and during a read operation, the reference reference module has a discharge characteristic, So that the potential of the reference signal gradually decreases.
  • the local read/write conversion module has a first discharge speed; during the read operation, the reference module has a second discharge speed, and the second discharge speed is less than the first discharge speed.
  • a reference control line for providing a reference control signal
  • the reference reference module is connected to the reference control line, and the reference reference module responds to the read control signal and the reference control signal, Outputting the reference reference signal to the reference data line.
  • the reference reference module has a first port, a second port, a third port, and a fourth port.
  • the first port receives the read control signal
  • the second port is connected to the reference data line.
  • the third port is grounded
  • the fourth port receives the reference control signal
  • the reference reference module responds to the read control signal and the reference control signal so that the second port is connected to the third port Discharge, so that the potential of the reference data line gradually decreases.
  • the reference reference module includes: a first switch unit, the first switch unit is connected to the first port and the third port, the first switch unit has a first node, and the first switch The unit is connected to the first node and the third port in response to the read control signal; a second switch unit, the second switch unit is connected to the second port and the fourth port , The second switch unit has a second node, the second node is connected to the first node, and the second switch unit responds to the reference control signal to turn on the second port and the The second node is connected.
  • the local read-write conversion module includes: a local read unit, in response to the read control signal in the read-write control signal, during a read operation, connect the first data line or the first complementary The data signal of the data line is transmitted to the second data line; the local reading unit includes at least two local transistors, the reference reference module includes at least one reference transistor, and the conduction capability of at least one reference transistor is less than that of all Describes the conduction capability of the local transistor.
  • each reference transistor is smaller than the channel width of the local transistor.
  • the at least two local transistors include: a local read control tube, which is turned on in response to the read control signal, and one port of the local read control tube is grounded; a local read transmission tube, which responds to all The data signal of the first complementary data line is turned on, so that the second data line is grounded via the local read transmission tube and the local read control tube;
  • the at least one reference transistor includes: a reference control tube, In response to the read control signal being turned on, the reference data line is grounded via the reference control tube, and the channel width of the reference control tube is smaller than the channel width of the local read control tube.
  • the at least one reference transistor further includes: a reference transmission tube, in response to the reference control signal being turned on, the reference data line is grounded via the reference control tube and the reference transmission tube, and the reference The channel width of the transmission tube is smaller than the channel width of the local read transmission tube.
  • the channel width of the reference control tube is less than or equal to 2/3 of the channel width of the local read control tube; the channel width of the reference transmission tube is less than or equal to that of the local read transmission tube 2/3 of the channel width.
  • the channel width of the reference control tube is 1/2 of the channel width of the local read control tube; the channel width of the reference transfer tube is the same as the channel width of the local read transfer tube. 1/2.
  • the amplifying module includes a differential amplifier, a first input end of the differential amplifier is connected to the second data line, and a second input end of the differential amplifier is connected to the reference data line.
  • a local amplifying module connected between the first data line and the first complementary data line, and configured to compare the data of the first data line and the first complementary data line The data of the data line is enlarged.
  • the local amplifying module includes a first inverter, a first input terminal of the first inverter is electrically connected to the first data line, and a first output terminal of the first inverter is electrically connected to the first data line.
  • the first complementary data line is electrically connected; a second inverter, the second input terminal of the second inverter is electrically connected to the first output terminal of the first inverter and the first complementary data line Connected, the second output terminal of the second inverter is electrically connected with the first input terminal of the first inverter and the first data line.
  • an embodiment of the present application further provides a memory, including: alternately arranged memory cell arrays and sense amplifier arrays, each of the memory cell arrays is connected to at least one of the sense amplifier arrays to form a memory array;
  • each of the first data line and the first complementary data line are connected to the corresponding memory cell array via the sense amplifier array, and the local read-write conversion module is used to The storage cell array performs read and write operations.
  • the sense amplifier array includes: a plurality of first group sense amplifier arrays located in odd-numbered columns and a plurality of second group sense amplifier arrays located in even-numbered columns;
  • the second data line includes: A first set of data lines corresponding to a set of sense amplifier arrays, a second set of data lines corresponding to the second set of sense amplifier arrays, and the first set of data lines and the first set of sense amplifier arrays
  • the connected first data line corresponds to the first complementary data line
  • the second group of data lines are connected to the first data line and the first complementary data connected to the second group of sense amplifier arrays Line correspondence;
  • the reference data line includes: a first reference data line for providing a first reference reference signal and a second reference data line for providing a second reference reference signal;
  • the amplifying module includes: a first set of amplification A module for receiving the first reference reference signal and the data signal of the first group of data lines, and amplifying the data signal of the first group of data lines; a second group of amplifying modules, for receiving
  • the first group of amplifying modules corresponds to the sense amplifier array in odd columns
  • the second group of amplifying modules corresponds to the sensor amplifier array in even columns
  • the first group of amplifying modules share the same The first reference data line
  • the second group of amplifying modules share the same second reference data line.
  • half of the plurality of second data lines are located on one side of the first reference data line and the second reference data line, and the other half of the plurality of second data lines are located on the first reference data line.
  • An embodiment of the application provides a semiconductor integrated circuit, including a first data line connected to a bit line via a column selection module, a first complementary data line connected to a complementary bit line via a column selection module, a second data line, and a reference data line ;
  • the local read-write conversion module in response to the read-write control signal, transmits data between the first data line and the first complementary data line and the second data line during the read-write operation. Since the second complementary data line whose phase is opposite to the second data line during the read operation is no longer provided, the number of data lines used in the semiconductor integrated circuit is reduced, thereby reducing power consumption and reducing heat dissipation requirements. Therefore, it is beneficial to improve the electrical performance of the semiconductor integrated circuit.
  • the local read-write conversion module has a first discharge speed; the reference reference module, in response to the read control signal, outputs a reference reference signal to the reference data line, and the reference reference signal serves as the second data line
  • the reference reference of the data signal and during the read operation, the reference reference module has a discharge characteristic, and the reference reference module has a second discharge speed, and the second discharge speed is less than the first discharge speed.
  • the reference reference module Since the reference reference module has discharge characteristics, during the read operation, when the second data line reads 1, the potential difference between the data signal of the second data line and the reference data signal gradually increases, so the detection margin of the semiconductor integrated circuit reads 1
  • the second data line reads When the second data line reads 0, the potentials of the data signal and the reference data signal of the second data line gradually decrease, and because the second discharge speed is lower than the first discharge speed, the data signal of the second data line
  • the potential drop rate of is faster than that of the reference data signal, so that the potential difference between the data signal of the second data line and the reference data signal gradually increases, so the detection margin of the semiconductor integrated circuit reading 0 gradually increases.
  • the detection margin of reading 0 and the detection margin of reading 1 can be basically the same; and the detection margin of reading 0 and the detection margin of reading 1 can both increase with the increase of time, The situation where the detection margin of reading 1 remains unchanged but the detection margin of reading 0 increases is avoided, thereby improving the reading performance.
  • the semiconductor integrated circuit further includes: a reference data line that provides a reference control signal, and the reference reference module responds to the read control signal at the same time, and the number of reference control signals is the same as the number of control signals of the local read unit in the local read-write conversion module, It is beneficial to control the difference between the first discharge speed and the second discharge speed by designing the difference in transistor performance, thereby further improving the reading performance.
  • FIG. 1 is a schematic diagram of functional modules of a semiconductor integrated circuit provided by some embodiments of the application;
  • FIG. 2 is a schematic diagram of the circuit structure of a local read-write conversion module in a semiconductor integrated circuit provided by some embodiments of the application
  • Fig. 3 is an equivalent circuit diagram of the amplifying module in Fig. 1 being a single-ended amplifier
  • FIG. 4 is a schematic diagram of a data signal potential change of a second data line during a read operation in some embodiments of the application;
  • FIG. 5 is a schematic diagram of functional modules of semiconductor integrated circuits provided by other embodiments of the application.
  • FIG. 6 is a schematic diagram of potential changes of the second data line and the reference data line during a read operation in some other embodiments of the application;
  • FIG. 7 is a schematic structural diagram of a semiconductor integrated circuit provided by still other embodiments of the application.
  • FIG. 8 is a schematic diagram of a circuit structure of a semiconductor integrated circuit provided by some other embodiments of the application.
  • FIG. 9 is a schematic diagram of potential changes of the second data line and the reference data line during a read operation in some other embodiments of the application.
  • FIG. 10 is a schematic structural diagram of a memory provided by an embodiment of this application.
  • Fig. 11 is a partial schematic diagram of Fig. 10.
  • the data in the corresponding memory cell will be transferred to the bit line, causing the voltage on the bit line to slightly increase or decrease.
  • the sense amplifier connected to the bit line that is, the first-stage amplifier (FSA, first sense amplifier)
  • FSA first sense amplifier
  • the column selection module transmits the 0 or 1 signal on the selected bit line to the local data line (Local Data Line) according to the column selection signal, and then transmits the signal from the local data line to the global data line (Global Data Line) through the semiconductor integrated circuit. Line) to complete the reading operation.
  • the transmission direction of the signal is opposite to the transmission direction in the aforementioned read operation, that is, the signal is transmitted through the global data line to the local data line, then through the local data line to the bit line, and then through the bit line Transfer to the corresponding storage unit to complete the write operation.
  • the foregoing 0 represents the signal level is low, and 1 represents the signal level is high.
  • a local data line includes at least a pair of first data lines.
  • the global data line includes at least a pair of second data lines.
  • the second data line is at a high level, the other second data line is at a low level.
  • the second data line can be identified and defined as high level quickly and accurately.
  • the embodiments of the present application provide a semiconductor integrated circuit.
  • the second data line of the semiconductor integrated circuit adopts a single-phase transmission mode.
  • the number of data lines in this way, the use of data lines in the memory can be reduced by nearly half the use of data lines, for example, according to the traditional double-ended transmission method, it needs twice 136, or 272 second data lines, but Adopting the single-phase transmission mode will only need 136 second data lines.
  • FIG. 1 is a schematic diagram of functional modules of a semiconductor integrated circuit provided by some embodiments of the application
  • FIG. 2 is a schematic diagram of a circuit structure of a local read/write conversion module in a semiconductor integrated circuit provided by some embodiments of the application.
  • the semiconductor integrated circuit includes: a first data line Ldat connected to the bit line BL via the column selection module 10, and a first complementary data line Ldat connected to the complementary bit line BL# via the column selection module 10 #, the second data line YIO, the reference data line YIO#, the reference data line YIO is used to provide the reference reference signal, and also includes: the local read-write conversion module 11, in response to the read-write control signal, during the read-write operation, the first Data is transmitted between the data line Ldat and the second data line YIO, and data is transmitted between the first complementary data line Ldat# and the second data line YIO; the amplifying module 13 is used to receive the data signal of the second data line YIO and the reference reference Signal to amplify the data signal of the second data line YIO, and the reference reference signal is used as a reference reference for amplifying the data signal of the second data line YIO.
  • the semiconductor integrated circuit includes at least a pair of the first data line Ldat and the first complementary data line Ldat#, that is, the first data line Ldat and the first complementary data line Ldat# are paired.
  • the data signal of one of the first data line Ldat and the first complementary data line Ldat# is a high-level signal
  • the data signal of the other is a low-level signal.
  • the first data line Ldat is a local data line (local data line, also referred to as a local data line), the first complementary data line Ldat# is a complementary local data line; and the second data line YIO is a global data line (global data line).
  • the semiconductor integrated circuit is applied to a memory.
  • the memory includes a column selection module 10 and a plurality of memory cells.
  • the memory cell for reading or writing is selected by the column selection module 10. Signals are transmitted between the bit line BL connected to the selected memory cell and the first data line Ldat, and signals are transmitted between the complementary bit line BL# and the first complementary data line Ldat# connected to the selected memory cell.
  • the read and write control signals include a read control signal Rd and a write control signal Wr.
  • the read-write conversion module 11 transmits the data of the first data line Ldat and the first complementary data line Ldat# to the second data line YIO, or, in response to the write control With the signal Wr, the read-write conversion module 11 transmits the data of the second data line YIO to the first data line Ldat and the first complementary data line Ldat#.
  • the local read-write conversion module 11 includes: a local read unit 311, in response to the read control signal Rd in the read-write control signal, during the read operation, the first The data signal of the data line Ldat or the first complementary data line Ldat# is transmitted to the second data line YIO; the local writing unit 312, in response to the writing control signal Wr in the reading and writing control signal, during the writing operation, the first The data signal of the second data line YIO is transmitted to the first data line Ldat or the first complementary data line Ldat#.
  • the local reading unit 311 includes: a local reading control tube MN11, which is turned on in response to the reading control signal Rd, and one port of the local reading control tube MN11 is grounded; a local reading transmission tube MN21, which responds to the first The data signal of a complementary data line Ldat# is turned on, so that the second data line YIO is grounded via the local read transmission tube MN21 and the local read control tube MN11.
  • one port of the local read control tube MN11 can be directly grounded.
  • one port of the local read control tube MN11 can be grounded through the switch tube, that is, the port is grounded during the on-time of the switch tube, and the port is suspended during the off-time of the switch tube.
  • the source of the local read control tube MN11 is grounded, the drain is connected to the source of the local read transfer tube MN21, and the drain of the local read transfer tube MN21 is connected to the second data line YIO.
  • the local write unit 312 in response to the write control signal Wr in the read and write control signal, transmits the data signal of the second data line YIO to the first data line Ldat or the first complementary data line Ldat# during the write operation. .
  • the local writing unit 312 includes: a first local writing control tube MN31, the gate of the first local writing control tube MN31 receives the writing control signal Wr, a port of the first local writing control tube MN31 and the second The second data line YIO is connected, and the other port is connected to the first data line Ldat; the second local write control tube MN41, the gate of the second local write control tube MN41 receives the write control signal Wr, the second local write control One port of the pipe MN41 is grounded, and the other port is connected to a port of the local write transmission pipe MN51; the local write transmission pipe MN51, the gate of the local write transmission pipe MN51 is connected to the second data line YIO, and the local write transmission The other port of the tube MN51 is connected to the first complementary data line Ldat#.
  • the first local write control tube MN31 is electrically connected to the second data line YIO and the first data line Ldat; the source of the second local write control signal MN41 is grounded, and the drain is connected to the local write transmission tube The source of MN51 is connected.
  • the semiconductor integrated circuit may further include: a local amplifying module 15, which is connected between the first data line Ldat and the first complementary data line Ldat#, and is used to compare data on the first data line Ldat and The data of the first complementary data line Ldat# is amplified.
  • a local amplifying module 15 which is connected between the first data line Ldat and the first complementary data line Ldat#, and is used to compare data on the first data line Ldat and The data of the first complementary data line Ldat# is amplified.
  • the local amplifying module 15 constitutes a circuit for amplifying the signal of the first data line Ldat and the signal of the first complementary data line Ldat#, which helps to speed up the distinction between the first data line Ldat and the first complementary data line Ldat#, thereby improving the data signal
  • the transmission speed improves the data read and write speed.
  • the first data line Ldat and the first complementary data line Ldat# are required for the driving capability of the first-stage amplifying circuit in the memory.
  • the first-stage amplifying circuit still has sufficient driving capability for the first data line Ldat and the first complementary data line Ldat#, so as to meet the requirements of device miniaturization.
  • the semiconductor integrated circuit is guaranteed to have good electrical performance, thereby improving the storage performance of the memory containing the semiconductor integrated circuit.
  • the local amplifying module 15 includes: a first inverter 151, a first input terminal in1 of the first inverter 151 is electrically connected to a first data line Ldat, and a first output terminal out1 of the first inverter 151 Electrically connected to the first complementary data line Ldat#; the second inverter 152, the second input terminal in2 of the second inverter 152 and the first output terminal out1 of the first inverter 151 and the first complementary data line Ldat #Electrical connection, the second output terminal out2 of the second inverter 152 is electrically connected to the first input terminal in1 of the first inverter 151 and the first data line Ldat.
  • the first inverter 151 includes: a first PMOS tube MP1 and a first NMOS tube MN1, the gate of the first PMOS tube MP1 and the gate of the first NMOS tube MN1 are electrically connected and serve as the first input terminal of the first inverter 151 in1, the source of the first PMOS transistor MP1 is connected to the working power supply VDD, and the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 and serves as the first output terminal out1 of the first inverter 151.
  • the second inverter 152 includes: a second PMOS tube MP2 and a second NMOS tube MN2.
  • the gate of the second PMOS tube MP2 is connected to the gate of the second NMOS tube MN2 and serves as the second input terminal in2 of the second inverter 152.
  • the source of the second PMOS transistor MP2 is connected to the working power supply VDD, and the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2 and serves as the second output terminal out2 of the second inverter 152.
  • the first PMOS tube MP1, the first NMOS tube MN1, the second PMOS tube MP2, and the second NMOS tube MN2 constitute a local amplifying module 15.
  • the transmission speed of data from the bit line BL to the first data line Ldat is increased, and the data is transmitted from the complementary bit line BL# to the first complementary data line Ldat#.
  • the transmission speed is improved, and therefore, the drive demand of the first-stage amplifier for the memory is reduced.
  • the first input terminal in1 of the first inverter 151 is connected to the second inverter 152 Two output terminals out2.
  • the first output terminal out1 of the first inverter 151 is connected to the second input terminal in2 of the second inverter 152, and is transmitted to the first data line Ldat and the first data line Ldat and the first data line Ldat on the bit line BL and the complementary bit line BL#.
  • a complementary data line Ldat# the speed at which the first data line Ldat is pulled up is increased, so that the first data line Ldat is pulled up to 1 quickly, and the speed at which the first complementary data line Ldat# is pulled down is also increased so that the first data line Ldat# is pulled down.
  • the complementary data line Ldat# quickly pulls down to 0, so the driving requirements of the first data line Ldat and the first complementary data line Ldat# on the first-stage amplifier are reduced.
  • the first data line Ldat is complementary to the first complementary data line Ldat#, that is, when one of the first data line Ldat and the first complementary data line Ldat# is at a high level, the other is at a low level, Due to the setting of the local amplifying module 15, the signals of the first data line Ldat and the first complementary data line Ldat# are amplified, so that the difference between the first data line Ldat and the first complementary data line Ldat# is accelerated and the data is increased from the first data line Ldat. The transmission speed of a data line Ldat and the first complementary data line Ldat# to the second data line YIO is improved.
  • the first data line Ldat is at a high level and the first complementary data line Ldat# is at a low level.
  • the first data line Ldat is 1 and the first complementary data line Ldat# is 0, the first data line The data of Ldat and the first complementary data line Ldat# will be transmitted to the second data line YIO; due to the setting of the local amplifying module 15, the first complementary data line Ldat# will approach 0 faster, that is, the first complementary data
  • the low level of the line Ldat# is lower, which is beneficial to accelerate the distinction between the first data line Ldat and the first complementary data line Ldat#, and increase the speed of the first data line Ldat and the first complementary data line Ldat# to achieve a large signal In this way, when data is read, the data transmission speed from the first data line Ldat and the first complementary data line Ldat# to the second data line YIO can be increased.
  • the semiconductor integrated circuit may further include: the enabling NMOS transistor MN6, the gate of the enabling NMOS transistor MN6 receives the enabling signal En, and the source of the enabling NMOS transistor MN6 is grounded.
  • the first inverter and the second inverter are also connected to the drain of the enabling NMOS transistor MN6.
  • the source of the first NMOS tube MN1 and the source of the second NMOS tube MN2 are connected to the drain of the enabling NMOS tube MN6, and one port of the local read control tube MN11 is grounded through the enabling NMOS tube MN6.
  • the semiconductor integrated circuit may further include: a precharge module 307, which is connected between the first data line Ldat and the first complementary data line Ldat# for responding to the precharge control signal Eq, The first data line Ldat and the first complementary data line Ldat# are precharged.
  • a precharge module 307 which is connected between the first data line Ldat and the first complementary data line Ldat# for responding to the precharge control signal Eq, The first data line Ldat and the first complementary data line Ldat# are precharged.
  • the pre-charging module 307 includes: a third PMOS tube MP3, a fourth PMOS tube MP4, and a fifth PMOS tube MP5; a third PMOS tube MP3 gate, a fourth PMOS tube MP4 gate, and a fifth PMOS tube MP5 gate Receive the precharge control signal Eq; the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are connected to the working power supply VDD, the drain of the third PMOS tube MP3 is electrically connected to the first data line Ldat; the drain of the fourth PMOS tube MP4 It is electrically connected to the first complementary data line Ldat#; the fifth PMOS transistor MN5 is electrically connected to the first data line Ldat and the first complementary data line Ldat# in response to the precharge control signal Eq.
  • FIG. 3 is a schematic diagram of the equivalent circuit structure of the amplifying module 13 provided by this embodiment.
  • the amplifying module 13 is a single-ended amplifier SA with a fixed reference signal, that is to say, the reference data line YIO# has a fixed potential, that is, the reference reference
  • the signal is a fixed potential signal
  • the reference reference signal serves as a reference reference for whether the second data line YIO is 0 or 1, and the reference reference signal is used to detect 1 (sense 1) or detect 0 (sense 0).
  • the reference data line YIO# can be built in the single-ended amplifier SA.
  • the semiconductor integrated circuit will be described in detail below in conjunction with the mechanism of read and write operations.
  • the local read control tube MN11 is turned on, and the first complementary data line Ldat# is 0, the corresponding first data line Ldat is 1, and due to the second data
  • the potential of the line YIO was precharged to be high before, and the local read transmission tube MN21 is not turned on, so the second data line YIO maintains a high level, which is also 1.
  • the amplifying module 13 receives the signal of the second data line YIO. After the data signal, the data signal of the second data line YIO is amplified and output based on the reference signal, that is, the data signal of the second data line YIO output by the amplifying module 13 is 0.
  • the single-ended amplifier amplifies the data signal of the second data line YIO , That is, the second data line YIO is pulled down to 0.
  • the threshold is determined by the parameter characteristics of the single-ended amplifier SA.
  • Figure 4 is a schematic diagram of the data signal potential change of the second data line during the read operation in the solution using a single-ended amplifier.
  • Ref represents the reference reference signal
  • ideal sense margin for 1 refers to the ideal detection margin of sense 1
  • ideal sense margin for 0 refers to sense 0
  • the second data line adopts a single-phase transmission mode, that is, the second data line no longer appears in pairs, and does not need to be set in the opposite phase to the second data line during the read operation. Therefore, the number of data lines required by the semiconductor integrated circuit is significantly reduced, thereby reducing the power consumption of the semiconductor integrated circuit, reducing the heat generated by the data line, and reducing the difficulty of data line wiring.
  • the amplifying module may be a single-ended amplifier, so that the semiconductor integrated circuit can amplify the data signal of the second data line while simplifying the circuit structure of the semiconductor integrated circuit.
  • inventions of the present application also provide a semiconductor integrated circuit, which is substantially the same as the semiconductor integrated circuit provided in the foregoing embodiments, with the main difference being: the reference reference signal provided by the reference data line is used as the reference reference of the second data line And the reference signal is variable, so the detection margins of sense 0 and sense 1 change with time, thereby improving the read performance of the semiconductor integrated circuit during the read operation.
  • the semiconductor integrated circuits provided by other embodiments of the present application will be described in detail below with reference to the accompanying drawings. For the same or corresponding parts as the previous embodiment, reference may be made to the detailed description of the foregoing embodiment, which will not be repeated below.
  • FIG. 5 is a schematic diagram of functional modules of semiconductor integrated circuits provided by other embodiments of the application.
  • the semiconductor integrated circuit includes: a first data line Ldat connected to the bit line BL via the column selection module 100, and a first complementary data line Ldat connected to the complementary bit line BL# via the column selection module 100 #, the second data line YIO, refer to the data line YIO#, also includes: the local read-write conversion module 101, in response to the read-write control signal, during the read-write operation, between the first data line Ldat and the second data line YIO To transmit data, data is transmitted between the first complementary data line Ldat# and the second data line YIO; the reference reference module 102, in response to the read control Rd in the read/write control signal, outputs a reference reference signal ref to the reference data line YIO# ,
  • the reference reference signal ref is used as the reference reference of the data signal of the second data line YIO, and during the read operation, the reference reference module 102 has a discharge characteristic, so that the potential of the reference reference signal ref gradually decreases; the amplifying module 103 is
  • the second data line YIO in the semiconductor integrated circuit appears in the form of a single bus, that is, the transmission mode of the data signal of the second data line YIO is a single-ended transmission mode. Due to the setting of the reference module 102, it can be Provide a reference for whether the second data line YIO is 1 or 0; and, since the process of changing the data signal of the second data line YIO from 1 to 0 during the read operation is a discharge process, refer to the discharge of the reference module 102 The speed is lower than the discharge speed of the read-write conversion module 101.
  • the reference reference signal ref can be used as a reference for whether the second data line YIO is 0 or 1. It can be understood that reading out whether the second data line YIO is 0 or 1 refers to whether the second data line YIO amplified by the amplifying module 103 is 0 or 1.
  • the reference reference module 102 has discharge characteristics, so that the potential of the reference reference signal ref gradually decreases. Therefore, during the read operation and the second data line YIO During the process of being 1, the potential difference between the second data line YIO and the reference signal ref is no longer fixed but changes with the passage of time; during the read operation and the second data line YIO is changed from In the process from 1 to 0, the potential difference between the second data line YIO and the reference signal ref also changes with the passage of time. Therefore, the detection margins of sense 0 and sense 1 in this embodiment change with time, which is beneficial to further improve the reading accuracy of the reading operation.
  • the second data line YIO is lowered from the first level to the second level (that is, the second data line YIO changes from 1 to 1).
  • the first level (“1") may be generated during the precharge high process)
  • the local read-write conversion module 101 has the first discharge speed; during the read operation, the reference module 102 has the second The discharge rate, and the second discharge rate is less than the first discharge rate.
  • the potential of the reference signal ref is always higher than the potential of the data signal of the second data line YIO
  • the accuracy of amplifying the second data line YIO by the amplifying module 103 during the period when the second data line YIO changes from 1 to 0 can be further improved. This is because if the potential of the reference reference signal is lower than the potential of the second data line during the period when the second data line changes from 1 to 0, if the second data line is amplified at this time, then the second data line The data line will be erroneously amplified to 1, while in fact the second data line is 0.
  • FIG. 6 is a schematic diagram of the potential changes of the second data line YIO and the reference data line YIO# during the read operation, YIO(1) represents the potential change of the second data line YIO during reading 1, and YIO(0) represents the second data The potential change of the line YIO during reading 0, YIO# represents the potential change of the reference data line.
  • the second data line YIO remains at 1 or changes to 1. Since the reference module 102 has discharge performance, The potential of the reference signal ref gradually decreases, so the detection margin for sense 1 increases over time. For example, the detection margin for sense 1 increases from m11 to m12.
  • the second data line YIO changes from 1 to 0. Since the reference reference module 102 has discharge performance, the reference reference The potential of the signal ref gradually decreases, and the local read-write conversion module 101 also has discharge performance, so the potential of the second data line YIO also gradually decreases; because the second discharge speed of the reference reference module 102 is lower than that of the local read-write conversion module 101 Therefore, the potential change speed of the second data line YIO is greater than the potential change speed of the reference reference signal ref, that is, the second data line YIO has a lower potential than the reference data line YIO#, and the second data line YIO The potential of the line YIO will preferentially become 0, so the second data line YIO is read as 0; in addition, the detection margin for sense 0 (sense margin for 0) increases over time, for example, the sense margin for sense 0 The degree changes from m01 to m02.
  • the process in which the second data line YIO changes from 1 to 0 is the discharge process of the local read-write conversion module 101.
  • the local read-write conversion module 101 has a first A discharge speed; during the read operation, the reference data line YIO# changes from 1 to 0, which is the discharge process of the reference reference module 102, during which the reference reference module 102 has the second discharge speed.
  • the detection margin of Sense 0 has an ideal detection margin (ideal sense margin for 0), which is called the first ideal detection margin m00.
  • the first ideal detection margin m00 is: during the reading of 0 on the second data line YIO, when the first ideal detection margin m00 is After the second data line YIO is discharged, refer to the absolute value of the potential difference between the reference line YIO# and the second data line YIO.
  • the detection margin of sense 1 has an ideal detection margin (ideal sense margin for 1), which is called the second ideal detection margin m10.
  • the second ideal detection margin m10 is: during the reading period of the second data line YIO, when the reference After the reference module 102 is discharged for a proper time, the absolute value of the potential difference between the reference data line YIO# and the second data line YIO is referenced.
  • the first ideal detection margin m00 and the second ideal detection margin m00 can be equal. It is understandable that the second discharge speed can be adjusted by adjusting the specific circuit structure of the reference reference module 102, and the first discharge speed can be adjusted by adjusting the specific circuit structure of the local read-write conversion module 101, so as to achieve the first ideal detection margin.
  • the purpose of m00 being equal to the second ideal detection margin m00.
  • first ideal detection margin m00 may also be smaller than the second ideal detection margin m00, or the first ideal detection margin m00 may also be greater than the second ideal detection margin m00.
  • the amplifying module 103 may be a differential amplifier, that is, a differential amplifier with two input terminals, the two input terminals are respectively connected to the second data line YIO and the reference data line YIO#, and output the amplified data of the second data line YIO.
  • the second data line YIO is 1, and the potential of the second data line YIO is always higher than the potential of the reference data line YIO#; if "0" is read, During the period when the second data line YIO changes from 1 to 0, the potential of the second data line YIO is always lower than the potential of the reference data line YIO#.
  • the reference module 102 includes at least one transistor.
  • the semiconductor integrated circuit further includes: a reference control line Co for providing a reference control signal cnt, and the reference reference module 102 is connected to the reference control line Co, and the reference reference module 102 responds to the read control signal Rd and the reference control The signal cnt outputs the reference reference signal ref to the reference data line YIO#.
  • the read control signal Rd and the reference control signal cnt jointly affect the reference reference module 102, it is beneficial to better control the second discharge speed of the reference reference module 102, thereby facilitating better control of the first discharge speed and the second discharge speed
  • the relationship between the size and the size of the relationship is further improved due to the inconsistency of the sense margin.
  • the reference reference module may only respond to the read control signal, or the reference reference module may also respond to other control signals in addition to the read control signal and the reference control signal.
  • the semiconductor integrated circuit may further include: a dummy module 104, which receives the write control signal Wr in the read and write control signal, and is connected to the reference data line YIO# for making the reference data line YIO# and
  • the situation of the second data line YIO is the same.
  • the same situation means that the circuit structure around the reference data line YIO# is consistent with the circuit structure of the second data line YIO, and the noise and other effects on the reference data line YIO# are consistent with the noise and other effects on the second data line YIO.
  • the number of transistors in the dummy compensation module 104 may be the same as the number of transistors in the reference module 102.
  • the virtual module 104 does not need to participate in data transmission.
  • the configuration of the virtual module 104 can reduce or offset the noise problem caused by the reference module 102, and is beneficial to the symmetry of the layout.
  • the semiconductor integrated circuit may further include: a local amplifying module 105, which is connected between the first data line Ldat and the first complementary data line Ldat#, and is used to compare the data of the first data line Ldat and The data of the first complementary data line Ldat# is amplified.
  • a local amplifying module 105 which is connected between the first data line Ldat and the first complementary data line Ldat#, and is used to compare the data of the first data line Ldat and The data of the first complementary data line Ldat# is amplified.
  • the reference reference module 102 discharges. It can be understood that, in other embodiments, during the read operation, it may also be: when the reference control signal provided by the reference control line is at a low level, the reference reference module discharges.
  • the semiconductor integrated circuit provided in this embodiment reduces the number of second data lines YIO while providing a reference signal that changes with the data signal of the second data line YIO, which is beneficial to ensure a sense 0 detection margin. Consistency with the detection margin of sense 1. More specifically, both the sense margin of sense 0 and the sense margin of sense 1 will increase over time, so the difference between the detection margins of sense 0 and sense 1 is small, which is beneficial to further improve the amplification module 103 to enlarge the second data line The accuracy of YIO.
  • the local read-write conversion module 101 has the first discharge speed; during the read operation, the reference module 102 has the second discharge speed, And the second discharge rate is less than the first discharge rate.
  • the potential of the second data line YIO is always lower than the potential of the reference signal ref; then, during this period, no matter when the amplifying module 103 is The amplification of the two data lines YIO can ensure that the second data line YIO amplified by the amplification module 103 is 0, thereby further improving the accuracy of reading 0 by the second data line YIO.
  • Still other embodiments of the present application also provide a semiconductor integrated circuit.
  • the semiconductor integrated circuit is roughly the same as the foregoing embodiments, with the main difference being that the reference module is further subdivided.
  • the semiconductor integrated circuit provided by this embodiment will be described below in conjunction with the accompanying drawings. It should be noted that, for the same or corresponding parts as the foregoing embodiment, please refer to the detailed description of the foregoing embodiment, which will not be repeated in detail below.
  • FIG. 7 is a schematic structural diagram of a semiconductor integrated circuit provided by still other embodiments of the application.
  • the semiconductor integrated circuit includes: a first data line Ldat connected to the bit line BL via the column selection module 200, a first complementary data line Ldat# connected to the complementary bit line BL# via the column selection module 200, and a second Data line YIO, reference control line Co, reference data line YIO#; local read/write conversion module 201; reference reference module 202, in response to the read control signal Rd in the read/write control signal and the reference control signal provided by the reference control line Co cnt, output a reference reference signal ref to the reference data line YIO#, the reference reference signal ref is used as a reference reference for the data signal of the second data line YIO, and during the read operation, the reference reference module 202 has discharge characteristics to make the reference reference signal The potential of ref gradually decreases; the amplification module 203.
  • the semiconductor integrated circuit including the reference control line Co as an example for detailed description.
  • the semiconductor integrated circuit may not include the reference control line, that is, the reference module does not need to respond to the reference control signal.
  • the reference reference module 202 has a first port A, a second port B, a third port C, and a fourth port D.
  • the first port A receives the read control signal Rd
  • the second port B is connected to the reference data line YIO.
  • the third port C is grounded, the fourth port D receives the reference control signal cnt, the reference reference module 202 responds to the read control line signal Rd and the reference control signal cnt to discharge between the second port B and the third port C, So that the potential of the reference data line YIO# is gradually reduced.
  • the read control signal Rd is at a high level and the reference control signal cnt is at a high level, and the reference reference module 202 is turned on.
  • Discharge between the second port B and the third port C that is, the potential of the reference data line YIO# is pulled down to 0; or, during the read operation, the read control signal Rd is high and the reference control signal cnt is low Level, the reference reference module 202 is turned on, and the second port B and the third port C are discharged, that is, the potential of the reference data line YIO# is pulled down to 0.
  • the above description of the working mechanism is based on the condition that the read operation is performed as the read control signal Rd is at a high level; of course, when the condition for the read operation is that the read control signal is at a low level , The description of "the read control signal Rd is at a high level” in the above working mechanism can be replaced with "the read control signal Rd is at a low level”.
  • the reference module 202 includes: a first switch unit 211, the first switch unit 211 is connected to the first port A and the third port C, the first switch unit 211 has a first node a, and the first switch unit 211 responds to The read control signal Rd is turned on to connect the first node a to the third port C; the second switch unit 212, the second switch unit 212 is connected to the second port B and the fourth port D, and the second switch unit 212 has The second node b is connected to the first node a, and the second switch unit 212 is turned on in response to the reference control signal cnt to connect the second port B to the second node b.
  • the second port B can be grounded via the first switch unit 211 and the second switch unit 212, so the signal of the reference data line YIO# is pulled down to 0.
  • the reference reference module may also be: the first switch unit is connected to the fourth port and the third port, so the first switch unit is turned on in response to the reference control signal; the second switch unit is connected to the The first port and the second port are connected, so the second switch unit is turned on in response to the read control signal.
  • the first switching unit 211 may include at least one transistor, and the second switching unit 212 may include at least one transistor.
  • the transistor can be a PMOS transistor or an NMOS transistor.
  • the reference reference module only responds to the read control signal, correspondingly, the reference reference module only includes the first switch unit.
  • the local read/write conversion module 201 has a first discharge speed; during a read operation, the reference module 202 has a second discharge speed, and the second discharge speed is less than the first discharge speed, so that during the read operation and the second data line YIO is reduced from the first level to the first In the two-level process, the potential of the reference reference signal ref is higher than the potential of the data signal of the second data line YIO.
  • the local read-write conversion module 201 includes a local read unit 221, the first discharge speed of the local read-write conversion module 201 is the discharge speed of the local read unit 221, and the local read unit 221 may also include Multiple transistors. Specifically, in response to the read control signal in the read and write control signal, the local read unit 221 transmits the data signal of the first data line Ldat or the first complementary data line Ldat# to the second data line during the read operation.
  • the local reading unit 221 includes at least 2 local transistors, the reference reference module 202 includes at least 1 reference transistor, and the conduction capability of at least one reference transistor is less than the conduction capability of the local transistor, so as to discharge the reference reference module 202
  • the speed is lower than the discharge speed of the local read unit 221. Specifically, the stronger the conduction capability, the faster the corresponding discharge speed; the weaker the conduction capability, the slower the corresponding discharge speed.
  • the transistor of the local reading unit 221 is a PMOS tube or an NMOS tube. It can be understood that the transistor type of the local reading unit 221 is the same as the transistor type of the reference module 202, for example, both are PMOS transistors or both are NMOS transistors.
  • the first discharge speed of the local reading unit 221 is related to the number of transistors inside and the characteristics of the transistors
  • the second discharge speed of the reference module 202 is also related to the number of transistors inside and the characteristics of the transistors.
  • the transistor characteristics include transistors. ⁇ channel width.
  • the reference reference module 202 may have the same number of transistors as the local reading unit 221, and the reference reference module 202 has a transistor channel width smaller than that of the local reading unit 221. In this way, it is beneficial to ensure that the second discharge speed of the reference module 202 is lower than the first discharge speed of the local read/write conversion module 201.
  • different discharge speeds can also be set by designing different performances such as threshold voltage.
  • the reference module 202 has a transistor channel width less than or equal to 2/3 of the transistor channel width of the local reading unit 221. Specifically, the channel width of the transistor of the reference module 202 may be 1/2 of the channel width of the transistor of the local reading unit 221.
  • the reference reference module 202 responds to the read control signal Rd and the reference control signal cnt, which facilitates the reference reference module 202 and the local reading unit
  • the number of 221 transistors is the same, so that the difference between the first discharging speed and the second discharging speed is more effectively controlled, which is beneficial to read 1 or 0 on the second data line YIO faster.
  • the semiconductor integrated circuit may also include: a virtual module 204 and a local amplification module 205.
  • a virtual module 204 and a local amplifying module 205 For the detailed description of the virtual module 204 and the local amplifying module 205, please refer to the foregoing embodiment, which will not be repeated here.
  • the reference reference line YIO# Before performing the read operation, the reference reference line YIO# can be precharged to make the reference reference line YIO# a high level, that is, the reference reference signal ref is a high level signal.
  • the reference reference module 202 is turned on, the second port B and the third port C are turned on, and the second port B and the third port are turned on.
  • the port C is discharged, the potential of the reference data line YIO# is pulled down to 0, that is, the reference signal ref is pulled down to 0.
  • the potential gap between the reference data line YIO# and the second data line YIO gradually increases, so the detection margin of the sense 1 of the amplifying module 203 gradually increases.
  • the reference signal ref is used as a reference, so that the difficulty of reading the second data line YIO as 1 is reduced.
  • the reference reference module 202 is turned on, the second port B and the third port C are turned on, and the second port B and the third port C are discharged ,
  • the potential of the reference data line YIO# is pulled down to 0, that is, the reference reference signal ref is pulled down from 1 to 0; and the local read/write conversion module 201 is also in the discharge period, that is, the potential of the second data line YIO is pulled down from 1 to 0,
  • the first discharge speed of the local read-write conversion module 202 is greater than the second discharge speed of the reference reference module 202, so the potential of the second data line YIO will be pulled down to 0 faster than the reference data line YIO#.
  • the potential difference between the reference data line YIO# and the second data line YIO is getting larger and larger.
  • the reference reference signal ref as a reference
  • the difficulty of reading the second data line YIO as 0 is reduced.
  • the potential gap between the reference data line YIO# and the second data line YIO gradually increases, so the detection margin of sense 0 gradually increases.
  • the detection margins of sense 0 and sense 1 increase over time, thereby avoiding the detection margin difference between sense 0 and sense 1 over time The problem becomes too big.
  • the second data line YIO is kept at 1 in the embodiment of the present application, it means that the second data line YIO is pre-charged to a high level before the read operation is performed, and therefore the second data line YIO is being read. It is 1 before the operation.
  • the second data line YIO remains at 1 during the read operation.
  • Still other embodiments of the present application also provide a semiconductor integrated circuit.
  • the semiconductor integrated circuit is substantially the same as the foregoing embodiments, with the main difference being that the specific structures of the local reading conversion module and the reference module are described in more detail.
  • the semiconductor integrated circuits provided by some other embodiments of the present application will be described below with reference to the accompanying drawings. It should be noted that, for the same or corresponding parts as the foregoing embodiments, please refer to the detailed description of the foregoing embodiments, which will not be repeated in detail below.
  • FIG. 8 is a schematic diagram of the circuit structure of a semiconductor integrated circuit provided by some other embodiments of the application, and some of the circuits in FIG. 8 are the same as those in FIG. 2;
  • FIG. 9 is a schematic diagram of voltage changes of the second data line and the reference data line during the read operation .
  • the semiconductor integrated circuit includes: a first data line Ldat, a first complementary data line Ldat#, a second data line YIO, a reference control line Co, a reference data line YIO#; a local read-write conversion module (Not labeled), during the read operation, the local read/write conversion module has the first discharge speed when the second data line YIO is reduced from the first level to the second level; refer to the reference module 302, respond to the read/write The read control signal Rd in the control signal and the reference control signal cnt provided by the reference control line Co output the reference reference signal ref to the reference data line YIO#, and the reference reference signal ref serves as the reference reference for the data signal of the second data line YIO, And during the reading operation, the reference reference module 302 has a discharge characteristic, and the reference reference module 302 has a second discharge speed, the second discharge speed is less than the first discharge speed; an amplifying module (not shown).
  • the local read-write conversion module includes: a local read unit 311, in response to the read control signal Rd in the read-write control signal, during a read operation, connect the first data line Ldat or the first complementary data line The data signal of Ldat# is transmitted to the second data line YIO.
  • both the reference reference module 302 and the local read unit 311 have discharge characteristics, and the reference reference module 302 has a discharge speed lower than that of the local read unit 311.
  • the circuit structure of the reference module 302 is similar to the circuit structure of the local reading unit 311, and it is ensured that the discharge speed of the circuit structure of the reference module 302 is lower than that of the circuit structure of the local reading unit 311.
  • the local reading unit 311 includes at least two local transistors
  • the reference reference module 302 includes at least one reference transistor
  • the channel width of the at least one reference transistor is smaller than the channel width of the local transistor.
  • the type of the local transistor is the same as the type of the reference transistor.
  • the type of the local transistor and the type of the reference transistor are both N-type, that is, the local transistors are both NMOS transistors, and the reference transistors are both NMOS transistors.
  • the channel width of each reference transistor is smaller than the channel width of the local transistor.
  • the channel width of each reference transistor is 1/2 of the channel width of the corresponding local transistor.
  • the channel width of at least one reference transistor may also be greater than or equal to the channel width of the local transistor to ensure that the discharge speed of the reference reference module and the discharge speed of the local read unit meet the requirements. .
  • the number of local transistors is the same as the number of reference transistors.
  • At least two local transistors include: the local read control tube MN11, which is turned on in response to the read control signal Rd, and one port of the local read control tube MN11 is grounded; the local read transmission tube MN21 In response to the data signal of the first complementary data line Ldat# being turned on, the second data line YIO is grounded via the local read transmission tube MN21 and the local read control tube MN11.
  • the source of the local read control tube MN11 is grounded, the drain is connected to the source of the local read transfer tube MN21, and the drain of the local read transfer tube MN21 is connected to the second data line YIO.
  • the source of the local read control tube MN11 can be directly grounded or grounded via a switch tube.
  • At least one reference transistor includes: a reference control tube MN12, in response to the read control signal Rd being turned on, the reference data line YIO# is grounded through the reference control tube MN12, and the channel width of the reference control tube MN12 is smaller than that of the local read control tube The channel width of MN11.
  • At least one reference transistor further includes: a reference transmission tube MN22, in response to the reference control signal cnt being turned on, the reference data line YIO# is grounded through the reference control tube MN12 and the reference transmission tube MN22, and the reference transmission tube MN22
  • the channel width of is smaller than the channel width of the local read transfer tube MN21.
  • the source of the reference control tube MN12 is grounded, and the drain is connected to the source of the reference transmission tube MN22; the gate of the reference transmission tube MN22 is connected to the reference control line Co, and the drain is connected to the reference data line YIO#.
  • the reference control tube MN12 and the local read control tube MN12 are both NMOS transistors, and the channel width of the reference control tube MN12 is less than or equal to 2/3 of the channel width of the local read control tube MN12; The channel width is less than or equal to 2/3 of the channel width of the local transmission tube MN21.
  • the channel width of the reference control tube MN12 is 1/2 of the channel width of the local read control tube MN11; the channel width of the reference transmission tube MN22 is 1 of the channel width of the local read transmission tube MN21. /2.
  • the second discharge speed of the reference reference module 302 is 1/2 of the first discharge speed of the local reading conversion module 301.
  • the proportional relationship between the second discharge speed and the first discharge speed can be adjusted reasonably according to actual requirements, that is, the channel width of the reference control tube and the local read control tube can be adjusted reasonably.
  • the proportional relationship of the channel width reasonably adjust the proportional relationship between the channel width of the reference transmission tube and the channel width of the local read transmission tube.
  • the channel width of the reference control tube can be the channel width of the local read control tube
  • the channel width of the reference transmission tube can be 1/3 or 1/4 of the channel width of the local reading transmission tube.
  • the positions of the reference control tube MN12 and the reference transmission tube MN22 in the circuit can be interchanged, that is, the reference control tube MN12 grid receives the reference control signal cnt and responds to the reference control signal cnt is turned on, the gate of the reference transmission tube MN22 receives the read control signal Rd and is turned on in response to the read control signal Rd.
  • the reference reference module may also include only one reference transistor, and the gate of the reference transistor receives the read control signal, and the channel width of the reference transistor is set reasonably to ensure the reference reference.
  • the second discharge speed of the module and the first discharge speed of the local read-write conversion module only need to meet the requirements.
  • the semiconductor integrated circuit further includes: a dummy module 304.
  • the dummy module 304 receives the write control signal Wr in the read/write control signal and is connected to the reference data line YIO#, and the number of transistors in the dummy module 304 and the reference The reference module 304 has the same number of transistors.
  • the virtual module 304 includes: a virtual control tube MN32, the gate of the virtual control tube 314 receives the write control signal Wr, and a port of the virtual control tube MN32 is grounded; the virtual transmission tube MN42, the gate of the virtual transmission tube MN42 is connected to The reference data line YIO# is connected, and the other port of the virtual control tube MN32 is connected to a port of the virtual transmission tube MN42, and the other port of the virtual transmission tube MN42 is grounded.
  • the virtual control tube MN32 and the virtual transmission tube MN42 are both NMOS tubes. It is not difficult to find that the circuit structure of the virtual compensation module 304 is similar to the local writing transmission tube MN51 and the second local writing control tube MN41 in the local writing unit 312. The circuit structure is similar, and the virtual transmission tube and the virtual control tube are connected between the two ground terminals, so the virtual compensation module 304 does not actually participate in the transmission of the data signal.
  • the setting of the virtual compensation module 304 can make the reference data line YIO# and the second data line YIO basically the same, reduce or offset the noise problem, improve the accuracy of the amplification result of the amplification module, and make the layout symmetrical , To reduce the difficulty of layout layout.
  • the local read-write conversion module further includes: a local write unit 312, in response to the write control signal Wr in the read-write control signal, during the write operation, the data signal of the second data line YIO is transmitted to The first data line Ldat or the first complementary data line Ldat#.
  • a local write unit 312 in response to the write control signal Wr in the read-write control signal, during the write operation, the data signal of the second data line YIO is transmitted to The first data line Ldat or the first complementary data line Ldat#.
  • the semiconductor integrated circuit may further include: a local amplifying module 306, which is connected between the first data line Ldat and the first complementary data line Ldat#, and is used to compare data on the first data line Ldat and The data of the first complementary data line Ldat# is amplified.
  • a local amplifying module 306 which is connected between the first data line Ldat and the first complementary data line Ldat#, and is used to compare data on the first data line Ldat and The data of the first complementary data line Ldat# is amplified.
  • the semiconductor integrated circuit further includes: an enabling NMOS tube MN6, the gate of the enabling NMOS tube MN6 receives the enabling signal En, and the source of the enabling NMOS tube MN6 is grounded.
  • the first inverter and the second inverter are also connected to the drain of the enabling NMOS transistor MN6.
  • the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are connected to the drain of the enabling NMOS transistor MN6.
  • the semiconductor integrated circuit may further include: a precharge module 307, which is connected between the first data line Ldat and the first complementary data line Ldat# for responding to the precharge control signal Eq, The first data line Ldat and the first complementary data line Ldat# are precharged.
  • a precharge module 307 which is connected between the first data line Ldat and the first complementary data line Ldat# for responding to the precharge control signal Eq, The first data line Ldat and the first complementary data line Ldat# are precharged.
  • the local amplifying module 306, the enabling NMOS transistor MN6, and the pre-charging module 307 please refer to the corresponding description of the foregoing embodiment, which will not be repeated here.
  • the second data line YIO and the reference data line YIO# are precharged to a high level; the read operation is performed while the read control signal Rd is at a high level, and the first data line Ldat is at a high level and The first complementary data line Ldat# is at low level, the local read control tube MN11 is turned on, the local read transmission tube MN21 is turned off, and the path from the second data line YIO# to the ground is disconnected, so the second data line YIO# remains high Level.
  • the reference control signal cnt provided by the reference control line Co is high, the reference control tube MN12 is turned on, and the reference transmission tube MN22 is turned on, so the path from the reference data line YIO# to the ground is turned on, and the reference data line YIO# goes through the reference
  • the control tube MN12 and the reference transmission tube MN22 discharge to the ground, so the potential of the reference data line YIO# becomes lower and lower and gradually becomes 0, and the potential difference between the reference data line YIO# and the second data line YIO becomes larger and larger.
  • the amplifying module can amplify the second data line YIO to 1 in time and accurately. Moreover, during the discharge period, the detection margin of the sense 1 of the second data line YIO is getting larger and larger, rather than being fixed.
  • the read operation is performed while the read control signal Rd is at a high level, the first data line Ldat is at a low level and the first complementary data line Ldat# is at a high level, the local read control tube MN11 and the local read transmission tube MN21 Both are turned on, the path between the second data line YIO and the ground is turned on, so the second data line YIO is discharged to the ground through the local read control tube MN11 and the local read transfer tube MN21, and the level of the second data line YIO increases Lower until it becomes 0.
  • the reference control signal cnt provided by the reference control line Co is at a high level, the reference control tube MN12 and the reference transmission tube MN22 are turned on, so the reference data line YIO# is turned on, and the reference data line YIO# passes through the reference control tube MN12 And the reference transmission tube MN22 discharges to the ground, so the potential of the reference data line YIO# becomes lower and lower and gradually becomes 0.
  • the second data line YIO Since the discharge speed of the reference data line YIO# to the ground is lower than the discharge speed of the second data line YIO to the ground, the second data line YIO is always closer to 0 than the reference data line YIO#, that is, the second data line YIO The potential is always lower than the potential of the reference data line YIO#; with the potential of the reference data line YIO# as a reference, the amplification module can effectively and accurately amplify the second data line YIO to 0 in time.
  • the sense 0 detection margin of the second data line YIO becomes larger and larger. Therefore, the detection margins of sense 0 and sense 1 of the second data line YIO are both larger and larger, avoiding a situation where the detection margin of sense 0 becomes larger and the detection margin of sense 1 remains unchanged.
  • line 1 is a schematic diagram of the potential change of the reference data line YIO# over time
  • line 2 is a schematic diagram of the potential change over time during the second data line YIO reading 1
  • line 3 is the second data line YIO reading 0 period Schematic diagram of potential changes over time.
  • the slope of line 1 is the second discharge rate
  • the slope of line 3 is the first discharge rate.
  • the detection margin of a semiconductor integrated circuit that reads 0 ie sense 0
  • the detection margin of circuit read 1 increases with time
  • the maximum detection margin of sense 0 is the first ideal detection margin (ideal sense margin for 0), and the maximum detection margin of sense 1 It is the second ideal sense margin for 1.
  • the semiconductor integrated circuit including the reference control line Co may not include the reference control line, that is, the reference reference module does not need to respond to the reference control.
  • the corresponding reference transistor may not include the reference pass tube.
  • FIG. 10 is a schematic structural diagram of a memory provided by an embodiment of this application
  • FIG. 11 is a partial schematic diagram corresponding to FIG. 10 rotated 90° clockwise.
  • the memory includes: alternately arranged memory cell array 41 and sense amplifier array 42, each memory cell array 41 is connected with at least one sense amplifier array 42 to form a memory array; the semiconductor device provided by the foregoing embodiment Integrated circuit, each of the first data line Ldat and the first complementary data line Ldat# is connected to the corresponding memory cell array 41 via the sense amplifier array 42, and the local read-write conversion module is used to perform read and write operations on the memory cell array 41.
  • the semiconductor The integrated circuit includes an amplifying module 403; it also includes: a column decoding circuit 404; a decoding selection signal line CSL.
  • the decoding selection signal line CSL is electrically connected to the column decoding circuit 404 and the memory array, so that the column decoding circuit 404 performs an operation on the memory array. position.
  • the memory will be described in detail below with reference to the drawings.
  • the triangles in FIG. 10 indicate electrical connections, and in FIG. 10, only a single sense amplifier array 42 is shown as a dotted line to indicate the first data line Ldat connected to the sense amplifier array 42. And the first complementary data line Ldat#, the first data line connected to the other sense amplifier array 42 and the first complementary data line are not shown.
  • Each memory array includes a memory cell array 41 and a sense amplifier array 42.
  • the memory cell array 41 includes a plurality of storage elements for storing data; the sensitive amplifier array 42 is used for amplifying the output signal of the memory cell array. Since the second data lines are in a single-phase mode, the number of data lines required by the memory is reduced, and the number of required second data lines is reduced from 2N in the prior art to N.
  • the sense amplifier array includes a plurality of first group sense amplifier arrays 4011 located in odd columns and a plurality of second group sense amplifier arrays 4012 located in even columns.
  • 4011 illustrated in FIG. 10 includes a memory cell array 41 connected to the sense amplifier array 42 of odd columns
  • 4012 illustrated includes a memory cell array 41 connected to the sense amplifier array 42 of even columns.
  • the second data line YIO includes: the first type data line YIO1 corresponding to the first group of sense amplifier array 4011, the second type data line YIO2 corresponding to the second group of sense amplifier array 4012, and the first group of data Line YIO1 corresponds to the first data line Ldat connected to the first group of sense amplifier array 4011 and the first complementary data line Ldat#, and the second group data line YIO2 is connected to the first data line Ldat of the second group of sense amplifier array 4012. And the first complementary data line Ldat# corresponds.
  • the reference data line includes: a first reference data line YIO#1 for providing a first reference reference signal and a second reference data line YIO#2 for providing a second reference reference signal.
  • the dotted line indicates the first reference data line YIO#1, and the dotted line indicates the second reference data line YIO#2.
  • the reference reference module includes: a first reference reference unit, the first reference unit is adapted to output a first reference reference signal to the first reference data line YIO#1, the first reference reference signal is used as a reference for the data signal of the first type data line YIO1 Reference; a second reference reference unit, the second reference reference unit is adapted to output a second reference reference signal to the second reference data line YIO#2, the second reference reference signal as a reference reference for the data signal of the second type data line YIO2.
  • the amplifying module 403 includes: a first group of amplifying modules, receiving the first reference reference signal and the data signal of the first group of data lines YIO1, and amplifying the data signal of the first group of data lines YIO1; the second group of amplifying modules, receiving the second group of data signals With reference to the reference signal and the data signal of the second group of data lines YIO2, the data signal of the second group of data lines YIO2 is amplified.
  • the amplifying module 403 is connected to the second data line and the reference data line, and is configured to amplify and output the data signal of the second data line in response to the data signal of the second data line and the reference reference signal.
  • the first group of amplifying modules amplify the first group of data lines YIO1 connected to the multiple first group of sense amplifier arrays 4011 in odd columns; the second group of amplifying modules are connected to the multiple second group of sense amplifier arrays 4012 in even columns
  • the second set of data lines YIO2 is amplified.
  • FIG. 11 is a partial schematic diagram corresponding to FIG. 10 rotated 90° clockwise.
  • half of the plurality of second data lines YIO are located in the first One side of the reference data line YIO#1 and the second reference data line YIO#2, the other half of the plurality of second data lines YIO is located on the first reference data line YIO#1 and the second reference data line YIO#2 On the other side.
  • the first reference data line YIO#1 and the second parameter data line YIO#2 are arranged in the middle position of all the second data lines YIO, in this way, from the selected sense amplifier array 42 position to the second data line YIO
  • the path lengths of the amplifying modules 403 at the end are basically the same, which reduces the loss caused by inconsistent path lengths and the problems of inconsistent parasitic circuits, which is beneficial to further improve the performance of the memory.
  • the first group of amplifying modules corresponds to the sense amplifier array 42 of odd-numbered columns
  • the second group of amplifying modules corresponds to the sense amplifier array 42 of even-numbered columns.
  • the first group of amplification modules corresponding to the sense amplifier array 42 in the odd-numbered column share the same first reference data line YIO#1
  • the second group of amplification modules corresponding to the sense amplifier array 42 in the even-numbered column share the same first reference data line YIO#1.
  • the modules share the same second reference data line YIO#2.
  • the memory further includes: a global write control circuit 407, and the global write control circuit 407 is connected to the second data line. Specifically, one global write control circuit 407 is connected to the first group of data lines YIO1, and the other global write control circuit 407 is connected to the second group of data lines YIO2.
  • the memory provided in this embodiment may be a DRAM memory, such as DDR3 DRAM, DDR4 DRAM, or DDR5 DRAM.
  • the memory may also be SRAM, MRAM, FeRAM, PCRAM, NAND, NOR and other memories.

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Abstract

一种半导体集成电路以及存储器，涉及半导体技术领域。半导体集成电路包括：经由列选择模块（10）与位线（BL）连接的第一数据线（Ldat）以及经由列选择模块（10）与互补位线（BL#）连接的第一互补数据线（Ldat#），第二数据线（YIO），参考数据线（YIO#），参考数据线（YIO#）用于提供参考基准信号，还包括：本地读写转换模块（11），响应于读写控制信号，在读写操作期间，第一数据线（Ldat）与第二数据线（YIO）之间传输数据，第一互补数据线（Ldat#）与第二数据线（YIO）之间传输数据；放大模块（13），用于接收第二数据线（YIO）的数据信号以及参考基准信号，对第二数据线（YIO）的数据信号进行放大，参考基准信号作为放大第二数据线（YIO）的数据信号的参考基准。

Description

半导体集成电路以及存储器
交叉引用
本申请引用于2020年6月19日递交的名称为“半导体集成电路以及存储器”的第202010568039.9号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体技术领域，特别涉及一种半导体集成电路以及存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
DRAM分为双倍速率同步(Double Data Rate，DDR)动态随机存储器、GDDR(Graphics Double Data Rate)动态随机存储器、低功耗双倍速率同步(Low Power Double Data Rate，LPDDR)动态随机存储器。随着DRAM应用的领域越来越多，如DRAM越来越多地应用于移动领域，用户对于DRAM速度指标的要求越来越高。
然而，目前的DRAM的读写性能仍有待提高。
申请内容
本申请实施例提供一种半导体集成电路以及存储器，减少数据线数量。
为解决上述问题，本申请实施例提供一种半导体集成电路，经由列选择模块与位线连接的第一数据线以及经由列选择模块与互补位线连接的第一互补数据线，第二数据线，参考数据线，所述参考数据线用于提供参考基准信号，还包括：本地读写转换模块，响应于读写控制信号，在读写操作期间，所述第一数据线与所述第二数据线之间传输数据，所述第一互补数据线与所述第二数据线之间传输数据；放大模块，用于接收所述第二数据线的数据信号以及所述参考基准信号，对所述第二数据线的数据信号进行放大，所述参考基准信号作为放大所述第二数据线的数据信号的参考基准。
另外，所述参考数据线具有固定电位。
另外，还包括：参考基准模块，响应于所述读写控制信号中的读取控制信号，向所述参考数据线输出所述参考基准信号，在读操作期间，所述参考基准模块具有放电特性，以使所述参考基准信号的电位逐渐降低。
另外，在所述读操作期间，所述第二数据线由第一电平降低为第二电平的过程中，所述本地读写转换模块具有第一放电速度；在所述读操作期间，所述参考基准模块具有第二放电速度，且所述第二放电速度小于所述第一放电速度。
另外，还包括：用于提供参考控制信号的参考控制线，且所述参考基准模块与所述参考控制线连接，所述参考基准模块响应于所述读取控制信号以及 所述参考控制信号，向所述参考数据线输出所述参考基准信号。
另外，所述参考基准模块具有第一端口、第二端口、第三端口以及第四端口，所述第一端口接收所述读取控制信号，所述第二端口连接所述参考数据线，所述第三端口接地，所述第四端口接收所述参考控制信号，所述参考基准模块响应于所述读取控制信号以及所述参考控制信号，使第二端口与所述第三端口之间放电，以使所述参考数据线的电位逐渐降低。
另外，所述参考基准模块包括：第一开关单元，所述第一开关单元与所述第一端口以及所述第三端口连接，所述第一开关单元具有第一节点，所述第一开关单元响应于所述读取控制信号以导通使所述第一节点与所述第三端口连接；第二开关单元，所述第二开关单元与所述第二端口以及所述第四端口连接，所述第二开关单元具有第二节点，所述第二节点与所述第一节点连接，所述第二开关单元响应于所述参考控制信号以导通使所述第二端口与所述第二节点连接。
另外，所述本地读写转换模块包括：本地读取单元，响应于所述读写控制信号中的读取控制信号，在读取操作期间，将所述第一数据线或者所述第一互补数据线的数据信号传输至所述第二数据线；所述本地读取单元包括至少2个本地晶体管，所述参考基准模块包括至少1个参考晶体管，且至少一个参考晶体管的导通能力小于所述本地晶体管的导通能力。
另外，每一所述参考晶体管的沟道宽度均小于所述本地晶体管的沟道宽度。
另外，所述至少2个本地晶体管包括：本地读取控制管，响应于所述读取控制信号导通，且所述本地读取控制管的一个端口接地；本地读取传输管， 响应于所述第一互补数据线的数据信号导通，使所述第二数据线经由所述本地读取传输管以及所述本地读取控制管接地；所述至少1个参考晶体管包括：参考控制管，响应于所述读取控制信号导通，使所述参考数据线经由所述参考控制管接地，且所述参考控制管的沟道宽度小于所述本地读取控制管的沟道宽度。
另外，所述至少1个参考晶体管还包括：参考传输管，响应于所述参考控制信号导通，使所述参考数据线经由所述参考控制管以及所述参考传输管接地，且所述参考传输管的沟道宽度小于所述本地读取传输管的沟道宽度。
另外，所述参考控制管的沟道宽度小于或等于所述本地读取控制管的沟道宽度的2/3；所述参考传输管的沟道宽度小于或等于所述本地读取传输管的沟道宽度的2/3。
另外，所述参考控制管的沟道宽度为所述本地读取控制管的沟道宽度的1/2；所述参考传输管的沟道宽度为所述本地读取传输管的沟道宽度的1/2。
另外，所述放大模块包括差分放大器，所述差分放大器的第一输入端与所述第二数据线连接，所述差分放大器的第二输入端与所述参考数据线连接。
另外，还包括：本地放大模块，所述本地放大模块连接在所述第一数据线与所述第一互补数据线之间，用于对所述第一数据线的数据以及所述第一互补数据线的数据放大。
另外，所述本地放大模块包括：第一反相器，所述第一反相器的第一输入端与所述第一数据线电连接，所述第一反相器的第一输出端与所述第一互补数据线电连接；第二反相器，所述第二反相器的第二输入端与所述第一反相器的第一输出端以及所述第一互补数据线电连接，所述第二反相器的第二输出端与所述第一反相器的第一输入端以及所述第一数据线电连接。
相应的，本申请实施例还提供一种存储器，包括：交替排布的存储单元阵列以及感测放大器阵列，每一所述存储单元阵列与至少一所述感测放大器阵列连接构成存储阵列；上述的半导体集成电路，每一所述第一数据线以及所述第一互补数据线均与经由所述感测放大器阵列与相应的所述存储单元阵列连接，利用所述本地读写转换模块对所述存储单元阵列进行读写操作。
另外，所述感测放大器阵列包括：位于奇数列的多个第一组感测放大器阵列以及位于偶数列的多个第二组感测放大器阵列；所述第二数据线包括：与所述第一组感测放大器阵列对应的第一组数据线，与所述第二组感测放大器阵列对应的第二组数据线，且所述第一组数据线与所述第一组感测放大器阵列连接的所述第一数据线以及所述第一互补数据线对应，所述第二组数据线与所述第二组感测放大器阵列连接的所述第一数据线以及所述第一互补数据线对应；所述参考数据线包括：用于提供第一参考基准信号的第一参考数据线以及用于提供第二参考基准信号的第二参考数据线；所述放大模块包括：第一组放大模块，接收所述第一参考基准信号以及所述第一组数据线的数据信号，对所述第一组数据线的数据信号进行放大；第二组放大模块，接收所述第二参考基准信号以及所述第二组数据线的数据信号，对所述第二组数据线的数据信号进行放大。
另外，所述第一组放大模块与奇数列的所述感测放大器阵列对应，所述第二组放大模块与偶数列的所述感测放大器阵列对应；所述第一组放大模块共用同一根第一参考数据线，所述第二组放大模块共用同一根第二参考数据线。
另外，多根所述第二数据线中的一半位于所述第一参考数据线以及所述第二参考数据线的一侧，多根所述第二数据线中的另一半位于所述第一参考数 据线以及所述第二参考数据线的另一侧。
与现有技术相比，本申请提供的技术方案具有以下优点：
本申请实施例提供一种半导体集成电路，包括经由列选择模块与位线连接的第一数据线，经由列选择模块与互补位线连接的第一互补数据线，第二数据线，参考数据线；本地读写转换模块，响应于读写控制信号，在读写操作期间，第一数据线以及第一互补数据线与第二数据线之间传输数据。由于不再设置在读取操作期间与第二数据线相位相反的第二互补数据线，因此半导体集成电路中用到的数据线的数量减小，从而降低了功耗，减小了散热需求，因此有利于改善半导体集成电路的电学性能。
另外，且在读取操作期间，本地读写转换模块具有第一放电速度；参考基准模块，响应于读取控制信号，向参考数据线输出参考基准信号，该参考基准信号作为第二数据线的数据信号的参考基准，且在读取操作期间，参考基准模块具有放电特性，且参考基准模块具有第二放电速度，第二放电速度小于第一放电速度。由于参考基准模块具有放电特性，因此在读取操作期间，当第二数据线读1时，第二数据线的数据信号与参考数据信号的电位差逐渐增加，因而半导体集成电路读1的检测裕度逐渐增加；当第二数据线读0时，第二数据线的数据信号以及参考数据信号的电位均逐渐降低，且由于第二放电速度小于第一放电速度，使得第二数据线的数据信号的电位下降速度比参考数据信号的电位下降速度更快，使得第二数据线的数据信号与参考数据信号的电位差逐渐增加，因而半导体集成电路读0的检测裕度逐渐增加。因此，本申请实施例中，读0的检测裕度以及读1的检测裕度可基本保持一致；且读0的检测裕度以及读1的检测裕度均能随着时间的增加而增加，避免了读1的检测裕度不变而读 0的检测裕度增加的情况，从而改善了读取性能。
另外，半导体集成电路还包括：提供参考控制信号的参考数据线，且参考基准模块同时响应于读取控制信号以及参考控制信号数量与本地读写转换模块中本地读取单元的控制信号数量相同，有利于通过设计晶体管性能差异来控制第一放电速度和第二放电速度的差异，从而进一步地改善读取性能。
附图说明
图1为本申请一些实施例提供的半导体集成电路的功能模块示意图；
图2为本申请一些实施例提供的半导体集成电路中的本地读写转换模块的电路结构示意图
图3为图1中放大模块为单端放大器的等效电路图；
图4为本申请一些实施例在读取操作期间第二数据线的数据信号电位变化示意图；
图5为本申请另一些实施例提供的半导体集成电路的功能模块示意图；
图6为本申请另一些实施例在读取操作期间第二数据线以及参考数据线的电位变化示意图；
图7为本申请又一些实施例提供的半导体集成电路的结构示意图；
图8为本申请再一些实施例提供的半导体集成电路的电路结构示意图；
图9为本申请再一些实施例在读取操作期间第二数据线与参考数据线的电位变化示意图；
图10为本申请一实施例提供的存储器的结构示意图；
图11为图10的局部示意图。
具体实施方式
在DRAM读取操作中，选中的字线被激活后，对应存储单元中的数据会被传输至位线中，导致位线上的电压出现微弱地增加或减小。与位线连接的感测放大器，即第一级放大器(FSA，first sense amplifier)，会根据此微弱信号将位线信号拉至0或1。列选择模块会依据列选择信号将选中位线上的0或1信号传输至局部数据线(Local Data Line)上，接着通过半导体集成电路将局部数据线中的信号传输至全局数据线(Global Data Line)上，以完成读取操作。在DRAM写入操作中，信号的传输方向与前述读取操作中的传输方向相反，即，信号经由全局数据线传输至局部数据线，然后经由局部数据线传输至位线中，然后经由位线传输至对应的存储单元中，以完成写入操作。需要说明的是，前述0代表信号的电平为低电平，1代表信号的电平为高电平。
目前常用的信号传输方式为双端传输也可称为双相位传输，具体地，局部数据线包括至少一对第一数据线，对于一对第一数据线而言，在读写操作过程中其中一第一数据线为高电平时另一第一数据线为低电平；全局数据线包括至少一对第二数据线，对于一对第二数据线而言，在读写操作过程中其中一第二数据线为高电平时另一第二数据线为低电平。如此，由于高电平与低电平起到对比作用，当一对第二数据线中的一第二数据线变为高电平时，能够快速准确的识别定义出第二数据线为高电平。
然而，对于双相位的传输方式，由于第二数据线为成对出现，因此存储器中第二数据线的数量相对较多，这将带来功耗高、电阻大、散热需求大以及布线难度大等问题，影响存储器的性能。
为解决上述问题，本申请实施例提供一种半导体集成电路，该半导体集成电路的第二数据线为单相位传输方式，即第二数据线不再是成对出现，因此有利于减少第二数据线的数量，这样，在存储器的数据线的使用上可以减少接近一半的数据线的使用量，例如，按照传统的双端式传输方式需要136的2倍即272根第二数据线，但是采用单相位传输方式将只需要136根第二数据线。如此，可以解决数据线过多带来的功耗大、电阻大、散热需求大以及布线难度大的问题，使得半导体集成电路的功耗减小、散热需求降低且布线难度降低，从而改善半导体集成电路的电学性能。以下将结合附图对本申请实施例提供的半导体集成电路进行详细说明。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请一些实施例提供的半导体集成电路的功能模块示意图，图2为本申请一些实施例提供的半导体集成电路中的本地读写转换模块的电路结构示意图。
参考图1，本实施例中，半导体集成电路包括：经由列选择模块10与位线BL连接的第一数据线Ldat，经由列选择模块10与互补位线BL#连接的第一互补数据线Ldat#，第二数据线YIO，参考数据线YIO#，参考数据线YIO用于提供参考基准信号，还包括：本地读写转换模块11，响应于读写控制信号，在 读写操作期间，第一数据线Ldat与第二数据线YIO之间传输数据，第一互补数据线Ldat#与第二数据线YIO之间传输数据；放大模块13，用于接收第二数据线YIO的数据信号以及参考基准信号，对第二数据线YIO的数据信号进行放大，且参考基准信号作为放大第二数据线YIO的数据信号的参考基准。
以下将结合附图对本实施例提供的半导体集成电路进行详细说明。
本实施例中，半导体集成电路至少包括一对第一数据线Ldat以及第一互补数据线Ldat#，即第一数据线Ldat与第一互补数据线Ldat#为成对的。在进行读写操作期间，第一数据线Ldat与第一互补数据线Ldat#中一者的数据信号为高电平信号，则另一者的数据信号为低电平信号。
第一数据线Ldat为局部数据线(local data line，也称为本地数据线)，第一互补数据线Ldat#为互补局部数据线；第二数据线YIO为全局数据线(global data line)。
在一个实施例中，半导体集成电路应用于存储器中，存储器包括列选择模块10以及多个存储单元，通过列选择模块10选中进行读取操作或者写入操作的存储单元，相应的，与该选中的存储单元连接的位线BL与第一数据线Ldat之间传输信号，与该选中的存储单元连接的互补位线BL#与第一互补数据线Ldat#之间传输信号。
读写控制信号包括读取控制信号Rd和写入控制信号Wr。在读写操作期间，响应于读取控制信号Rd，读写转换模块11将第一数据线Ldat以及第一互补数据线Ldat#的数据传输至第二数据线YIO，或者，响应于写入控制信号Wr，读写转换模块11将第二数据线YIO的数据传输至第一数据线Ldat以及第一互 补数据线Ldat#。
结合参考图1及图2，本实施例中，本地读写转换模块11包括：本地读取单元311，响应于读写控制信号中的读取控制信号Rd，在读取操作期间，将第一数据线Ldat或者第一互补数据线Ldat#的数据信号传输至第二数据线YIO；本地写入单元312，响应于读写控制信号中的写入控制信号Wr，在写入操作期间，将第二数据线YIO的数据信号传输至第一数据线Ldat或者第一互补数据线Ldat#。
参考图2，本地读取单元311包括：本地读取控制管MN11，响应于读取控制信号Rd导通，且本地读取控制管MN11的一个端口接地；本地读取传输管MN21，响应于第一互补数据线Ldat#的数据信号导通，使第二数据线YIO经本地读取传输管MN21以及本地读取控制管MN11接地。在一个具体实施例中，本地读取控制管MN11的一个端口可以直接接地。在另一具体实施例中，本地读取控制管MN11的一个端口可以通过开关管接地，即开关管导通期间该端口接地，开关管截止期间该端口悬置。
更具体地，本地读取控制管MN11的源极接地，漏极与本地读取传输管MN21的源极连接，本地读取传输管MN21的漏极与第二数据线YIO连接。
本地写入单元312，响应于读写控制信号中的写入控制信号Wr，在写入操作期间，将第二数据线YIO的数据信号传输至第一数据线Ldat或者第一互补数据线Ldat#。
具体地，本地写入单元312包括：第一本地写入控制管MN31，第一本地写入控制管MN31的栅极接收写入控制信号Wr，第一本地写入控制管MN31 的一端口与第二数据线YIO连接，另一端口与第一数据线Ldat连接；第二本地写入控制管MN41，第二本地写入控制管MN41的栅极接收写入控制信号Wr，第二本地写入控制管MN41的一端口接地，另一端口与本地写入传输管MN51的一端口连接；本地写入传输管MN51，本地写入传输管MN51的栅极与第二数据线YIO连接，本地写入传输管MN51的另一端口与第一互补数据线Ldat#连接。
第一本地写入控制管MN31响应于写入控制信号Wr，电连接第二数据线YIO与第一数据线Ldat；第二本地写入控制信号MN41源极接地，漏极与本地写入传输管MN51的源极连接。
本实施例中，半导体集成电路还可以包括：本地放大模块15，本地放大模块15连接在第一数据线Ldat与第一互补数据线Ldat#之间，用于对第一数据线Ldat的数据以及第一互补数据线Ldat#的数据放大。
本地放大模块15构成了对第一数据线Ldat信号放大以及第一互补数据线Ldat#信号放大的电路，有助于加速区分第一数据线Ldat与第一互补数据线Ldat#，从而提高数据信号传输的速度，改善数据读写速度。此外，由于第一数据线Ldat和第一互补数据线Ldat#的数据信号得到放大，使得第一数据线Ldat和第一互补数据线Ldat#对于存储器中的第一级放大电路的驱动能力的需求降低，因而即使第一级放大电路的面积逐渐减小，该第一级放大电路对于第一数据线Ldat和第一互补数据线Ldat#而言仍具有足够的驱动能力，以便于在满足器件微型化发展趋势的同时，保证该半导体集成电路具有良好的电学性能，进而提高包含该半导体集成电路的存储器的存储性能。
参考图2，本地放大模块15包括：第一反相器151，第一反相器151的第一输入端in1与第一数据线Ldat电连接，第一反相器151的第一输出端out1与第一互补数据线Ldat#电连接；第二反相器152，第二反相器152的第二输入端in2与第一反相器151的第一输出端out1以及第一互补数据线Ldat#电连接，第二反相器152的第二输出端out2与第一反相器151的第一输入端in1以及第一数据线Ldat电连接。
第一反相器151包括：第一PMOS管MP1以及第一NMOS管MN1，第一PMOS管MP1栅极以及第一NMOS管MN1栅极电连接且作为第一反相器151的第一输入端in1，第一PMOS管MP1源极与工作电源VDD连接，第一PMOS管MP1漏极与第一NMOS管MN1漏极连接且作为第一反相器151的第一输出端out1。
第二反相器152包括：第二PMOS管MP2以及第二NMOS管MN2，第二PMOS管MP2栅极与第二NMOS管MN2栅极连接且作为第二反相器152的第二输入端in2，第二PMOS管MP2源极与工作电源VDD连接，第二PMOS管MP2漏极与第二NMOS管MN2漏极连接且作为第二反相器152的第二输出端out2。
第一PMOS管MP1、第一NMOS管MN1、第二PMOS管MP2以及第二NMOS管MN2构成本地放大模块15。
在读取操作期间，由于本地放大模块15的设置，使得数据从位线BL传输至第一数据线Ldat的传输速度得到提升，数据从互补位线BL#传输到第一互补数据线Ldat#的传输速度得到提升，因而存储器对第一级放大器的驱动需求 降低。
具体地，以位线BL的数据为高电平，互补位线BL#的数据为低电平为例，由于第一反相器151的第一输入端in1连接第二反相器152的第二输出端out2，第一反相器151的第一输出端out1连接第二反相器152的第二输入端in2，在位线BL以及互补位线BL#传输至第一数据线Ldat以及第一互补数据线Ldat#期间，第一数据线Ldat被上拉的速度得到提高使得第一数据线Ldat很快上拉为1，第一互补数据线Ldat#被下拉的速度也得到提高使得第一互补数据线Ldat#很快下拉为0，因而第一数据线Ldat以及第一互补数据线Ldat#对第一级放大器的驱动需求降低。
在读取期间，第一数据线Ldat与第一互补数据线Ldat#互补，即第一数据线Ldat与第一互补数据线Ldat#中的一者为高电平时另一种为低电平，由于本地放大模块15的设置，第一数据线Ldat以及第一互补数据线Ldat#的信号被放大，使得第一数据线Ldat与第一互补数据线Ldat#的差异被加速拉大，数据从第一数据线Ldat以及第一互补数据线Ldat#传输至第二数据线YIO的速度得到提升。举例来说，第一数据线Ldat为高电平，第一互补数据线Ldat#为低电平，当第一数据线Ldat为1以及第一互补数据线Ldat#为0时，第一数据线Ldat以及第一互补数据线Ldat#的数据将被传输至第二数据线YIO；由于本地放大模块15的设置，使得第一互补数据线Ldat#更快的趋近于0，即第一互补数据线Ldat#的低电平更低，从而有利于加速区分开第一数据线Ldat以及第一互补数据线Ldat#，提高第一数据线Ldat以及第一互补数据线Ldat#的速度，达到大信号的模式，这样在读出数据时，数据从第一数据线Ldat以及第一互补数据线Ldat#传输至第二数据线YIO的速度得以提高。
本实施例中，半导体集成电路还可以包括：使能NMOS管MN6，使能NMOS管MN6栅极接收使能信号En，且使能NMOS管MN6源极接地。第一反相器以及第二反相器还与使能NMOS管MN6漏极连接。具体地，第一NMOS管MN1源极以及第二NMOS管MN2源极与使能NMOS管MN6漏极连接，本地读取控制管MN11的一个端口通过使能NMOS管MN6接地。
本实施例中，半导体集成电路还可以包括：预充电模块307，预充电模块307连接在第一数据线Ldat与第一互补数据线Ldat#之间，用于响应于预充电控制信号Eq，对第一数据线Ldat以及第一互补数据线Ldat#线预充电。
具体地，预充电模块307包括：第三PMOS管MP3、第四PMOS管MP4以及第五PMOS管MP5；第三PMOS管MP3栅极、第四PMOS管MP4栅极以及第五PMOS管MP5栅极接收预充电控制信号Eq；第三PMOS管MP3源极以及第四PMOS管MP4源极接工作电源VDD，第三PMOS管MP3漏极与第一数据线Ldat电连接；第四PMOS管MP4漏极与第一互补数据线Ldat#电连接；第五PMOS管MN5响应于预充电控制信号Eq电连接第一数据线Ldat和第一互补数据线Ldat#。
图3为本实施例提供的放大模块13的等效电路结构示意图。
参考图3，本实施例中，为实现对第二数据线YIO的放大，放大模块13为具有固定参考基准信号的单端放大器SA，也就是说参考数据线YIO#具有固定电位，即参考基准信号为固定电位信号，该参考基准信号作为第二数据线YIO为0还是为1的参考基准，该参考基准信号用于检测1(sense 1)或者检测0(sense 0)。
本实施例中，参考数据线YIO#可内置于单端放大器SA内。
以下将结合读写操作的机理对半导体集成电路进行详细说明。
在读取操作期间，读取控制信号Rd为高电平，本地读取控制管MN11导通，第一互补数据线Ldat#为0时，相应第一数据线Ldat为1，且由于第二数据线YIO的电位在之前预充高，本地读取传输管MN21不导通，因而第二数据线YIO维持高电平，也为1。
在读取操作期间，第一互补数据线Ldat#为1时，本地读取传输管MN21导通，第二数据线YIO的电位将被下拉至0，放大模块13接收该第二数据线YIO的数据信号后，以参考基准信号为基准，对第二数据线YIO的数据信号进行放大并输出，也就是说，放大模块13输出的第二数据线YIO的数据信号为0。具体地，第二数据线YIO的电位被下拉的过程中，当第二数据线YIO的电位低于参考基准信号的电位某一阈值后，单端放大器将第二数据线YIO的数据信号进行放大，即第二数据线YIO下拉至0。该阈值由单端放大器SA的参数特性决定。
图4为采用单端放大器的方案中，在读取操作期间第二数据线的数据信号电位变化示意图，YIO(＝0)表示第二数据线变为0期间的电位随时间变化，YIO(＝1)表示第二数据线变为1或者保持为1的电位随时间变化，Ref表示参考基准信号，ideal sense margin for 1是指sense 1的理想检测裕度，ideal sense margin for 0是指sense 0的理想检测裕度，sense 1的sense margin为YIO(＝1)的电位与Ref的电位之差绝对值，sense 0的sense margin为YIO(＝0)的电位与Ref的电位之差绝对值。
参考图4，在第二数据线YIO变为1或者保持为1期间，参考基准信号Ref的电位始终低于第二数据线YIO的电位，因此单端放大器放大的第二数据线为1；在第二数据线YIO变为0期间，第二数据线YIO的电位逐渐降低，且当第二数据线YIO变化后的电位比参考基准信号Ref的电位低，单端放大器放大的第二数据线YIO为0。
本实施例提供的半导体集成电路的技术方案中，第二数据线采用单相位传输模式，即第二数据线不再是成对出现，无需设置在读取操作期间与第二数据线相位相反的第二互补数据线，因此半导体集成电路所需的数据线的数量明显减少，从而降低了半导体集成电路的功耗，减少了数据线产生的热量，且降低了数据线布线难度。
此外，放大模块可以为单端放大器，使得半导体集成电路能够对第二数据线的数据信号进行放大的同时，简化半导体集成电路的电路结构。
本申请另一些实施例还提供一种半导体集成电路，该半导体集成电路与前述实施例提供的半导体集成电路大致相同，主要区别在于：参考数据线提供的参考基准信号作为第二数据线的参考基准，且参考基准信号为变化的，因而sense 0和sense 1的检测裕度均随时间变化而变化，从而改善半导体集成电路在读取操作期间的读取性能。以下将结合附图对本申请另一些实施例提供的半导体集成电路进行详细说明，与前一实施例相同或相应的部分，可参考前述实施例的详细描述，以下将不再赘述。
图5为本申请另一些实施例提供的半导体集成电路的功能模块示意图。
参考图5，本实施例中，半导体集成电路包括：经由列选择模块100与 位线BL连接的第一数据线Ldat，经由列选择模块100与互补位线BL#连接的第一互补数据线Ldat#，第二数据线YIO，参考数据线YIO#，还包括：本地读写转换模块101，响应于读写控制信号，在读写操作期间，第一数据线Ldat与第二数据线YIO之间传输数据，第一互补数据线Ldat#与第二数据线YIO之间传输数据；参考基准模块102，响应于读写控制信号中的读取控制Rd，向参考数据线YIO#输出基准参考信号ref，参考基准信号ref作为第二数据线YIO的数据信号的参考基准，且在读取操作期间，参考基准模块102具有放电特性，以使参考基准信号ref的电位逐渐降低；放大模块103，用于接收第二数据线YIO的数据信号以及参考基准信号ref，对第二数据线YIO的数据线信号进行放大，参考基准信号ref作为放大第二数据线YIO的参考基准。
本实施例中，半导体集成电路中的第二数据线YIO以单根总线的形式出现，即第二数据线YIO的数据信号的传输方式为单端传输方式，由于参考基准模块102的设置，能够为第二数据线YIO是为1还是为0提供参考基准；并且，由于在读取操作期间，第二数据线YIO的数据信号由1变为0的过程为放电过程，参考基准模块102的放电速度小于读写转换模块101的放电速度。
以下将结合附图对本实施例提供的半导体集成电路进行详细说明。
在读取操作中，需要及时准确的读出第二数据线YIO是0还是1，参考基准模块102的设置，使得参考基准信号ref能够作为第二数据线YIO是0还是1的参考基准。可以理解的是，读出第二数据线YIO是0还是1，指的是放大模块103放大后的第二数据线YIO是0还是1。
本实施例中，由于在读取操作期间，具体地读“1”期间，参考基准模块 102具有放电特性，使得参考基准信号ref的电位逐渐降低，因此，在读取操作且第二数据线YIO为1的过程中，第二数据线YIO与参考基准信号ref之间的电位差值不再是固定不变的而是随时间的推移而变化；在读取操作期间且第二数据线YIO由1变为0的过程中，第二数据线YIO与参考基准信号ref之间的电位差值也是随着时间的推移而变化的。因此，本实施例中sense 0和sense 1的检测裕度均随时间变化而变化，有利于进一步的改善读取操作的读取准确性。
此外，本实施例中，在读取操作期间，具体地读“0”期间，第二数据线YIO由第一电平降低为第二电平的过程中(即第二数据线YIO由1变为0的过程中，第一电平(“1”)可以是预充高过程产生的)，本地读写转换模块101具有第一放电速度；在读取操作期间，参考基准模块102具有第二放电速度，且第二放电速度小于第一放电速度。如此，有利于保证在读取操作期间且第二数据线YIO由第一电平降低为第二电平的过程中，参考基准信号ref的电位始终高于第二数据线YIO的数据信号的电位，这样，能够进一步的提高第二数据线YIO由1变为0期间放大模块103放大第二数据线YIO的准确性。这是因为，若在第二数据线由1变为0期间，出现了参考基准信号的电位低于第二数据线的电位的情况，若在此时对第二数据线进行放大，那么第二数据线将被错误的放大为1，而实际上第二数据线为0。
图6为在读取操作期间，第二数据线YIO以及参考数据线YIO#的电位变化示意图，YIO(1)表示第二数据线YIO读1期间的电位变化，YIO(0)表示第二数据线YIO读0期间的电位变化，YIO#表示参考数据线的电位变化。以下将结合半导体集成电路的工作机理对半导体集成电路进行说明：
参考图6，对于需读出第二数据线YIO是1的情形而言，即对sense 1而言：第二数据线YIO保持为1或者变化为1，由于参考基准模块102具有放电性能，使得参考基准信号ref的电位逐渐减小，因此sense 1的检测裕度(sense margin for 1)随着时间的推移而增加，例如，sense 1的检测裕度由m11增加为m12。
继续参考图6，对于需要读出第二数据线YIO是0的情形而言，即对sense0而言：第二数据线YIO由1变为0，由于参考基准模块102具有放电性能，使得参考基准信号ref的电位逐渐减小，本地读写转换模块101也具有放电性能因而第二数据线YIO的电位也逐渐减小；由于参考基准模块102具有的第二放电速度小于本地读写转换模块101具有的第一放电速度，因此，第二数据线YIO的电位变化速度大于参考基准信号ref的电位变化速度，即比起参考数据线YIO#而言第二数据线YIO的电位更低，第二数据线YIO的电位将优先变为0，因此将第二数据线YIO读为0；此外，sense 0的检测裕度(sense margin for 0)随着时间的推移而增加，例如，sense 0的检测裕度由m01变为m02。
由上述分析可知，在读取操作中，sense 0和sense 1的检测裕度均随着时间的推移而增加，因此，有利于减小sense 0和sense 1之间的检测裕度的差距。
需要说明的是，在读取操作期间，第二数据线YIO由1变为0的过程，即为本地读写转换模块101的放电过程，在这一放电过程中本地读写转换模块101具有第一放电速度；在读取操作期间，参考数据线YIO#由1变为0的过程，即为参考基准模块102的放电过程中，在这一放电过程中参考基准模块102具 有第二放电速度。
Sense 0的检测裕度具有理想检测裕度(ideal sense margin for 0)，称为第一理想检测裕度m00，第一理想检测裕度m00为：在第二数据线YIO读0期间，当第二数据线YIO放电结束，参考基准线YIO#与第二数据线YIO之间的电位差值绝对值。sennse 1的检测裕度具有理想检测裕度(ideal sense margin for 1)，称为第二理想检测裕度m10，第二理想检测裕度m10为：在第二数据线YIO读1期间，当参考基准模块102放电适当时间后，参考数据线YIO#与第二数据线YIO之间的电位差值绝对值。
理想情况下，第一理想检测裕度m00与第二理想检测裕度m00可以相等。可以理解的是，可以通过调整参考基准模块102的具体电路结构以调整第二放电速度，通过调整本地读写转换模块101的具体电路结构以调整第一放电速度，从而实现第一理想检测裕度m00与第二理想检测裕度m00相等的目的。
可以理解的是，第一理想检测裕度m00还可以小于第二理想检测裕度m00，或者，第一理想检测裕度m00也可以大于第二理想检测裕度m00。
放大模块103可以为差分放大器，即具有2个输入端的差分放大器，2个输入端分别与第二数据线YIO以及参考数据线YIO#连接，输出对第二数据线YIO进行放大后的数据。
由前述分析，在读取操作期间，当第二数据线YIO由1变为0时，第二数据线YIO以及参考数据线YIO#的数据信号均被下拉，但是第二数据线YIO的数据信号的下拉速度比参考数据线YIO#的参考基准信号的下拉速度更快，因此差分放大器输出0。
可以理解的是，对于读取操作而言，若读“1”，第二数据线YIO为1，第二数据线YIO的电位始终高于参考数据线YIO#的电位；若读“0”，第二数据线YIO从1变为0期间，第二数据线YIO的电位始终低于参考数据线YIO#的电位。
在一个具体例子中，参考基准模块102包括至少一个晶体管。
本实施例中，半导体集成电路还包括：参考控制线Co，用于提供参考控制信号cnt，且参考基准模块102与参考控制线Co连接，参考基准模块102响应于读取控制信号Rd以及参考控制信号cnt，向参考数据线YIO#输出参考基准信号ref。
由于读取控制信号Rd以及参考控制信号cnt共同影响参考基准模块102，有利于更好的控制参考基准模块102具有的第二放电速度，从而便于更好的控制第一放电速度与第二放电速度之间的大小关系，进而由于进一步的改善sense margin不一致的问题。
需要说明的是，在其他实施例中，参考基准模块也可以仅响应于读取控制信号，或者参考基准模块除响应于读取控制信号以及参考控制信号外，还可响应于其他控制信号。
本实施例中，半导体集成电路还可以包括：虚拟模块104，虚拟模块104接收读写控制信号中的写入控制信号Wr，且与参考数据线YIO#连接，用于使得参考数据线YIO#与第二数据线YIO情形一致。情形一致指的是，参考数据线YIO#周围的电路结构与第二数据线YIO的电路结构一致，参考数据线YIO#受到的噪音等影响与第二数据线YIO受到的噪音等影响一致。
虚拟补偿模块104具有的晶体管数量可以与参考基准模块102具有的晶体管数量相同。
在半导体集成电路中，虚拟模块104无需参与数据传输，虚拟模块104的设置，能够减小或者抵消参考基准模块102带来的噪声问题，且有利于版图布局的对称性。
本实施例中，半导体集成电路还可以包括：本地放大模块105，本地放大模块105连接在第一数据线Ldat与第一互补数据线Ldat#之间，用于对第一数据线Ldat的数据以及第一互补数据线Ldat#的数据放大。
本实施例中，在读取操作期间，参考控制线Co提供的参考控制信号cnt为高电平时，参考基准模块102放电。可以理解的是，在其他实施例中，在读取操作期间，也可以为：参考控制线提供的参考控制信号为低电平时，参考基准模块放电。
本实施例提供的半导体集成电路，在减少第二数据线YIO的数量的同时，能够提供随着第二数据线YIO的数据信号变化而变化的参考基准信号，有利于保证sense 0的检测裕度与sense 1的检测裕度的一致性。更具体地，sense 0的sense margin和sense 1的sense margin均会随时间加大，因此sense 0和sense 1的检测裕度的差距小，从而有利于进一步的提高放大模块103放大第二数据线YIO的准确性。
并且，在读取操作期间且第二数据线YIO由1变为0的过程中，本地读写转换模块101具有第一放电速度；在读取操作期间，参考基准模块102具有第二放电速度，且第二放电速度小于第一放电速度。如此，有利于保证在 第二数据线YIO由1变为0的过程中，第二数据线YIO的电位始终低于参考基准信号ref的电位；那么，在这期间不管放大模块103何时对第二数据线YIO进行放大，均能够保证放大模块103放大的第二数据线YIO为0，从而进一步的提高了第二数据线YIO读0的准确性。
本申请又一些实施例还提供一种半导体集成电路该半导体集成电路与前述实施例的大致相同，主要区别在于：对参考基准模块进行了进一步的细分。以下将结合附图对本实施提供的半导体集成电路进行说明，需要说明的是，与前述实施例相同或者相应的部分，请参考前述实施例的详细说明，以下将不做详细赘述。
图7为本申请又一些实施例提供的半导体集成电路的结构示意图。
本实施例中，半导体集成电路包括：经由列选择模块200与位线BL连接的第一数据线Ldat、经由列选择模块200与互补位线BL#连接的第一互补数据线Ldat#、第二数据线YIO、参考控制线Co、参考数据线YIO#；本地读写转换模块201；参考基准模块202，响应于读写控制信号中的读取控制信号Rd以及参考控制线Co提供的参考控制信号cnt，向参考数据线YIO#输出参考基准信号ref，参考基准信号ref作为第二数据线YIO的数据信号的参考基准，且在读取操作期间，参考基准模块202具有放电特性以使参考基准信号ref的电位逐渐降低；放大模块203。
需要说明的是，以下将以半导体集成电路包括参考控制线Co作为示例进行详细说明，在其他实施例中，半导体集成电路也可以不包括参考控制线，即参考基准模块无需响应于参考控制信号。本实施例中，参考基准模块202具 有第一端口A、第二端口B、第三端口C以及第四端口D，第一端口A接收读取控制信号Rd，第二端口B连接参考数据线YIO#，第三端口C接地，第四端口D接收参考控制信号cnt，参考基准模块202响应于读取控制线信号Rd以及参考控制信号cnt，使第二端口B与第三端口C之间放电，以使参考数据线YIO#的电位逐渐降低。
具体地，关于参考基准模块202的工作机理，可以有如下几种情况：在读取操作期间，读取控制信号Rd为高电平且参考控制信号cnt为高电平，参考基准模块202导通，第二端口B与第三端口C之间放电，即参考数据线YIO#的电位下拉至0；或者，在读取操作期间，读取控制信号Rd为高电平且参考控制信号cnt为低电平，参考基准模块202导通，第二端口B与第三端口C之间放电，即参考数据线YIO#的电位下拉至0。
可以理解的是，上述关于工作机理的描述，均是基于进行读取操作的条件为读取控制信号Rd为高电平；当然，当进行读取操作的条件为读取控制信号为低电平时，可上述工作机理中关于“读取控制信号Rd为高电平”的描述替换为“读取控制信号Rd为低电平”。
具体地，参考基准模块202包括：第一开关单元211，第一开关单元211与第一端口A以及第三端口C连接，第一开关单元211具有第一节点a，第一开关单元211响应于读取控制信号Rd导通，以使第一节点a与第三端口C连接；第二开关单元212，第二开关单元212与第二端口B以及第四端口D连接，第二开关单元212具有第二节点b，第二节点b与第一节点a连接，第二开关单元212响应于参考控制信号cnt以导通，使第二端口B与第二节点b连 接。
如此，经由第一开关单元211以及第二开关单元212，可使第二端口B接地，因而参考数据线YIO#的信号下拉至0。
可以理解的是，在其他实施例中，参考基准模块也可以为：第一开关单元与第四端口以及第三端口连接，因而第一开关单元响应于参考控制信号导通；第二开关单元与第一端口以及第二端口连接，因而第二开关单元响应于读取控制信号导通。
第一开关单元211可包括至少一个晶体管，第二开关单元212可包括至少一个晶体管。该晶体管可以为PMOS晶体管或者NMOS晶体管。
需要说明的是，在其他实施例中，若参考基准模块仅响应于读取控制信号，则相应的，参考基准模块仅包括第一开关单元。
本实施例中，在读操作期间，第二数据线YIO由第一电平降低为第二电平的过程中(即第二数据线由1变为0的过程中)，本地读写转换模块201具有第一放电速度；在读操作期间，参考基准模块202具有第二放电速度，且第二放电速度小于第一放电速度，以使在读操作期间且第二数据线YIO由第一电平降低为第二电平的过程中，参考基准信号ref的电位高于第二数据线YIO的数据信号的电位。
本实施例中，本地读写转换模块201包括本地读取单元221，本地读写转换模块201具有的第一放电速度即为本地读取单元221具有的放电速度，本地读取单元221也可以包括多个晶体管。具体地，本地读取单元221响应于读写控制信号中的读取控制信号，在读取操作期间，将第一数据线Ldat或者第 一互补数据线Ldat#的数据信号传输至第二数据线YIO；本地读取单元221包括至少2个本地晶体管，参考基准模块202包括至少1个参考晶体管，且至少一个参考晶体管的导通能力小于本地晶体管的导通能力，以使参考基准模块202的放电速度小于本地读取单元221的放电速度。具体地，导通能力越强，相应放电速度越快；导通能力越弱，相应放电速度越慢。
本地读取单元221具有的晶体管为PMOS管或者NMOS管。可以理解的是，本地读取单元221具有的晶体管类型与参考基准模块202具有的晶体管类型相同，如均为PMOS管或者均为NMOS管。
本地读取单元221具有的第一放电速度与其内部的晶体管数量以及晶体管特性有关，且参考基准模块202具有的第二放电速度也与其内部的晶体管的数量以及晶体管特性有关，其中，晶体管特性包括晶体管的沟道宽度。参考基准模块202具有的晶体管的数量可以与本地读取单元221具有的晶体管的数量相同，且参考基准模块202具有的晶体管沟道宽度小于本地读取单元221具有的晶体管的沟道宽度。如此，有利于保证参考基准模块202具有的第二放电速度小于本地读写转换模块201具有的第一放电速度。当然，本领域内技术人员应应当理解，也可以通过设计阈值电压等性能的不同来设置不同的放电速度。
参考基准模块202具有的晶体管沟道宽度小于等于本地读取单元221具有的晶体管沟道宽度的2/3。具体地，参考基准模块202具有的晶体管沟道宽度可以为本地读取单元221具有的晶体管的沟道宽度的1/2。
相较于采用参考基准模块202仅响应于读取控制信号Rd的方案而言， 参考基准模块202响应于读取控制信号Rd以及参考控制信号cnt，有利于使参考基准模块202与本地读取单元221晶体管数量一致，从而更有效地控制第一放电速度和第二放电速度之间的差异，进而有利于更快对第二数据线YIO读1或者读0。
半导体集成电路还可以包括：虚拟模块204以及本地放大模块205。有关虚拟模块204以及本地放大模块205的详细说明可参考前述实施例，在此不再赘述。
为便于理解，以下将结合半导体集成电路的工作原理对半导体集成电路进行进一步说明：
在进行读取操作之前，可对参考基准线YIO#进行预充，以使参考基准线YIO#为高电平，即参考基准信号ref为高电平信号。
在读取操作过程中，第二数据线YIO由0变为1期间或者保持为1期间，参考基准模块202导通，第二端口B与第三端口C导通，第二端口B与第三端口C之间放电，参考数据线YIO#的电位被下拉至0，即参考基准信号ref下拉至0。在下拉过程中参考数据线YIO#与第二数据线YIO之间的电位差距逐渐增加，因此放大模块203的sense 1的检测裕度逐渐增加。且由于参考数据线YIO#与第二数据线YIO的电位差值越来越大，有了参考基准信号ref作为参考，使得第二数据线YIO被读出为1的难度降低。
在读取操作过程中，第二数据线YIO由0变为1期间，参考基准模块202导通，第二端口B与第三端口C导通，第二端口B与第三端口C之间放电，参考数据线YIO#的电位被下拉至0，即参考基准信号ref由1下拉至0； 且本地读写转换模块201也处于放电期间，即第二数据线YIO的电位从1下拉至0，且本地读写转换模块202的第一放电速度大于参考基准模块202的第二放电速度，因此相较于参考数据线YIO#而言第二数据线YIO的电位将更快的被下拉至0，参考数据线YIO#与第二数据线YIO的电位差值越来越大，有了参考基准信号ref作为参考，使得第二数据线YIO被读出为0的难度降低。并且，在下拉过程中参考数据线YIO#与第二数据线YIO之间的电位差距逐渐增加，因此sense 0的检测裕度逐渐增加。
因此，本实施例中，在读取操作期间，sense 0和sense 1的检测裕度均随着时间的推移而增加，从而避免了随着时间的推移sense 0与sense 1的检测裕度差值变得过大的问题。
关于本申请实施例中第二数据线YIO保持为1的描述，指的是，在进行读取操作之前，第二数据线YIO被预充至高电平，因而第二数据线YIO在进行读取操作之前已经为1，当第一数据线Ldat的数据传输至第二数据线YIO且第一数据线Ldat为1时，在读取操作过程中，第二数据线YIO保持为1。
本申请再一些实施例还提供一种半导体集成电路，该半导体集成电路与前述实施例的大致相同，主要区别在于对本地读取转换模块以及参考基准模块的具体结构进行了更详细的说明。以下将结合附图对本申请再一些实施例提供的半导体集成电路进行说明，需要说明的是，与前述实施例相同或者相应的部分，请参考前述实施例的详细说明，以下将不做详细赘述。
图8为本申请再一些实施例提供的半导体集成电路的电路结构示意图，图8中的部分电路与图2相同；图9为在读取操作期间第二数据线与参考 数据线的电压变化示意图。
参考图8，本实施例中，半导体集成电路包括：第一数据线Ldat、第一互补数据线Ldat#、第二数据线YIO、参考控制线Co、参考数据线YIO#；本地读写转换模块(未标示)，在读取操作期间，第二数据线YIO由第一电平降低为第二电平的过程中本地读写转换模块具有第一放电速度；参考基准模块302，响应于读写控制信号中的读取控制信号Rd以及参考控制线Co提供的参考控制信号cnt，向参考数据线YIO#输出参考基准信号ref，参考基准信号ref作为第二数据线YIO的数据信号的参考基准，且在读取操作期间，参考基准模块302具有放电特性，且参考基准模块302具有第二放电速度，第二放电速度小于第一放电速度；放大模块(未图示)。
以下将结合附图对本实施例提供的半导体集成电路进行详细说明，需要说明的是，图8中与图2相同的部分，可参考前述实施例的详细描述，以下将不再赘述。本实施例中，本地读写转换模块包括：本地读取单元311，响应于读写控制信号中的读取控制信号Rd，在读取操作期间，将第一数据线Ldat或者第一互补数据线Ldat#的数据信号传输至第二数据线YIO。
由于在读取操作期间，参考基准模块302与本地读取单元311均具有放电特性，且参考基准模块302具有的放电速度小于本地读取单元311具有的放电速度，为了简化电路降低版图设计难度，参考基准模块302具有的电路结构与本地读取单元311具有的电路结构类似，且保证参考基准模块302具有的电路结构的放电速度小于本地读取单元311具有的电路结构的放电速度。
具体地，本地读取单元311包括至少2个本地晶体管，参考基准模块 302包括至少1个参考晶体管，且至少一个参考晶体管的沟道宽度小于本地晶体管的沟道宽度。
本地晶体管的类型与参考晶体管的类型相同，本实施例中，本地晶体管的类型与参考晶体管的类型均为N型，即本地晶体管均为NMOS管，参考晶体管均为NMOS管。
本实施例中，每一参考晶体管的沟道宽度均小于本地晶体管的沟道宽度。例如，每一参考晶体管的沟道宽度为对应的本地晶体管的沟道宽度的1/2。需要说明的是，在其他实施例中，至少一个参考晶体管的沟道宽度也可以大于或等于本地晶体管的沟道宽度，保证参考基准模块的放电速度与本地读取单元的放电速度符合要求即可。
本实施例中，本地晶体管的数量与参考晶体管的数量相同。
具体地，本实施例中，至少2个本地晶体管包括：本地读取控制管MN11，响应于读取控制信号Rd导通，且本地读取控制管MN11的一个端口接地；本地读取传输管MN21，响应于第一互补数据线Ldat#的数据信号导通，使第二数据线YIO经本地读取传输管MN21以及本地读取控制管MN11接地。
更具体地，本地读取控制管MN11的源极接地，漏极与本地读取传输管MN21的源极连接，本地读取传输管MN21的漏极与第二数据线YIO连接。本地读取控制管MN11的源极可以直接接地，也可经由开关管接地。
至少1个参考晶体管包括：参考控制管MN12，响应于读取控制信号Rd导通，使参考数据线YIO#经由参考控制管MN12接地，且参考控制管MN12的沟道宽度小于本地读取控制管MN11的沟道宽度。
本实施例中，至少1个参考晶体管还包括：参考传输管MN22，响应于参考控制信号cnt导通，使参考数据线YIO#经由参考控制管MN12以及参考传输管MN22接地，且参考传输管MN22的沟道宽度小于本地读取传输管MN21的沟道宽度。
更具体地，参考控制管MN12的源极接地，漏极与参考传输管MN22的源极连接；参考传输管MN22栅极与参考控制线Co连接，漏极与参考数据线YIO#连接。
其中，参考控制管MN12以及本地读取控制管MN12均为NMOS晶体管，且参考控制管MN12的沟道宽度小于或等于本地读取控制管MN12的沟道宽度的2/3；参考传输管MN22的沟道宽度小于或等于本地传输管MN21的沟道宽度的2/3。
本实施例中，参考控制管MN12的沟道宽度为本地读取控制管MN11的沟道宽度的1/2；参考传输管MN22的沟道宽度为本地读取传输管MN21的沟道宽度的1/2。如此，基准参考模块302具有的第二放电速度为本地读取转换模块301具有的第一放电速度的1/2。
需要说明的是，在其他实施例中，可以根据实际需求合理调整第二放电速度与第一放电速度之间的比例关系，即，合理调整参考控制管的沟道宽度与本地读取控制管的沟道宽度的比例关系，合理调整参考传输管的沟道宽度与本地读取传输管的沟道宽度的比例关系，例如，参考控制管的沟道宽度可以为本地读取控制管的沟道宽度的1/3或1/4等，参考传输管的沟道宽度可以为本地读取传输管的沟道宽度的1/3或1/4。
还需要说明的是，本实施例中，参考控制管MN12以及参考传输管MN22在电路中所处的位置可以互换，即，参考控制管MN12栅极接收参考控制信号cnt且响应于参考控制信号cnt导通，参考传输管MN22栅极接收读取控制信号Rd且响应于读取控制信号Rd导通。
此外，还需要说明的是，在其他实施例中，参考基准模块也可以仅包括一个参考晶体管，该参考晶体管的栅极接收读取控制信号，通过合理设置参考晶体管的沟道宽度，保证参考基准模块具有的第二放电速度与本地读写转换模块具有的第一放电速度符合要求即可。
本实施例中，半导体集成电路还包括：虚拟模块304，虚拟模块304接收读写控制信号中的写入控制信号Wr，且与参考数据线YIO#连接，且虚拟模块304具有的晶体管数量与参考基准模块304具有的晶体管数量相同。
具体地，虚拟模块304包括：虚拟控制管MN32，虚拟控制管314的栅极接收写入控制信号Wr，且虚拟控制管MN32的一端口接地；虚拟传输管MN42，虚拟传输管MN42的栅极与参考数据线YIO#连接，且虚拟控制管MN32的另一端口与虚拟传输管MN42的一端口连接，虚拟传输管MN42的另一端口接地。
其中，虚拟控制管MN32以及虚拟传输管MN42均为NMOS管，不难发现，虚拟补偿模块304的电路结构与本地写入单元312中本地写入传输管MN51和第二本地写入控制管MN41的电路结构类似，且虚拟传输管以及虚拟控制管连接在2个地端之间，因而实际上虚拟补偿模块304并不参与数据信号的传输。虚拟补偿模块304的设置，可以使得参考数据线YIO#与第二数据线 YIO的情形基本一致，减小或者抵消噪声问题，提高放大模块的放大结果准确性，且使得版图布局时具有布局对称性，降低版图布局难度。
本实施例中，本地读写转换模块还包括：本地写入单元312，响应于读写控制信号中的写入控制信号Wr，在写入操作期间，将第二数据线YIO的数据信号传输至第一数据线Ldat或者第一互补数据线Ldat#。有关本地写入单元312的详细描述，可参考前述实施例的相应说明。
本实施例中，半导体集成电路还可以包括：本地放大模块306，本地放大模块306连接在第一数据线Ldat与第一互补数据线Ldat#之间，用于对第一数据线Ldat的数据以及第一互补数据线Ldat#的数据放大。
本实施例中，半导体集成电路还包括：使能NMOS管MN6，使能NMOS管MN6栅极接收使能信号En，且使能NMOS管MN6源极接地。第一反相器以及第二反相器还与使能NMOS管MN6漏极连接。具体地，第一NMOS管MN1源极以及第二NMOS管MN2源极与使能NMOS管MN6漏极连接。
本实施例中，半导体集成电路还可以包括：预充电模块307，预充电模块307连接在第一数据线Ldat与第一互补数据线Ldat#之间，用于响应于预充电控制信号Eq，对第一数据线Ldat以及第一互补数据线Ldat#线预充电。
有关本地放大模块306、使能NMOS管MN6以及预充电模块307的详细说明，可参考前述实施例的相应描述，在此不再赘述。
以下将结合本实施例中提供的半导体集成电路的工作原理对半导体集成电路进行说明：
在进行读取操作之前，第二数据线YIO以及参考数据线YIO#被预充至高电平；读取控制信号Rd为高电平期间进行读取操作，第一数据线Ldat为高电平且第一互补数据线Ldat#为低电平，本地读取控制管MN11导通，本地读取传输管MN21截止，第二数据线YIO#至地的通路断路，因而第二数据线YIO#保持高电平。参考控制线Co提供的参考控制信号cnt为高电平，参考控制管MN12导通，且参考传输管MN22导通，因而参考数据线YIO#至地的通路导通，参考数据线YIO#经由参考控制管MN12以及参考传输管MN22对地放电，因而参考数据线YIO#的电位越来越低逐渐变为0，参考数据线YIO#与第二数据线YIO之间的电位差越来越大，有了参考数据线YIO#的电位作为参考，因而放大模块能够及时准确的放大第二数据线YIO为1。并且，在放电期间，第二数据线YIO的sense 1的检测裕度越来越大，而不是固定不变的。
读取控制信号Rd为高电平期间进行读取操作，第一数据线Ldat为低电平且第一互补数据线Ldat#为高电平，本地读取控制管MN11以及本地读取传输管MN21均导通，第二数据线YIO与地的通路导通，因而第二数据线YIO经由本地读取控制管MN11以及本地读取传输管MN21对地放电，第二数据线YIO的电平越来越低直至变为0。参考控制线Co提供的参考控制信号cnt为高电平，参考控制管MN12以及参考传输管MN22导通，因而参考数据线YIO#至地的通路导通，参考数据线YIO#经由参考控制管MN12以及参考传输管MN22对地放电，因而参考数据线YIO#的电位越来越低逐渐变为0。由于参考数据线YIO#对地的放电速度小于第二数据线YIO对地的放电速度，因而第二数据线YIO始终较参考数据线YIO#而言更接近于0，即第二数据线YIO的电位始终低于参考数据线YIO#的电位；有了参考数据线YIO#的电位作为参考， 因而放大模块能够及时有效准确的放大第二数据线YIO为0。并且，在放电期间，第二数据线YIO的sense 0的检测裕度越来越大。因此，第二数据线YIO的sense 0和sense 1的检测裕度均越来越大，避免出现sense 0的检测裕度变大而sense 1的检测裕度不变的情形。
如图9所示，线条1为参考数据线YIO#随时间的电位变化示意图，线条2为第二数据线YIO读1期间随时间的电位变化示意图，线条3为第二数据线YIO读0期间随时间的电位变化示意图，线条1的斜率为第二放电速度，线条3的斜率为第一放电速度，从图9中可知，半导体集成电路读0(即sense 0)的检测裕度与半导体集成电路读1(即sense 1)的检测裕度均随时间的变化而增加，且sense 0的最大检测裕度为第一理想检测裕度(ideal sense margin for 0)，sense 1的最大检测裕度为第二理想检测裕度(ideal sense margin for 1)，通过调整第一放电速度以及第二放电速度，可以保证第一理想检测裕度与第二理想检测裕度相等，从而进一步的改善读取转换电路的读取性能。
需要说明的是，上述实施例是以半导体集成电路包括参考控制线Co作为示例进行详细说明，在其他实施例中，半导体集成电路也可以不包括参考控制线，即参考基准模块无需响应于参考控制信号，相应的参考晶体管可以不包括参考传输管。
本申请实施例还提供一种存储器，包括上述任一实施例中的半导体集成电路。图10为本申请一实施例提供的存储器的结构示意图，图11为图10顺时针旋转90°对应的局部示意图。
参考图10及图11，存储器包括：交替排布的存储单元阵列41以及 感测放大器阵列42，每一存储单元阵列41与至少一感测放大器阵列42连接构成存储阵列；前述实施例提供的半导体集成电路，每一第一数据线Ldat以及第一互补数据线Ldat#经由感测放大器阵列42与相应的存储单元阵列41连接，利用本地读写转换模块对存储单元阵列41进行读写操作，半导体集成电路包括放大模块403；还包括：列译码电路404；译码选择信号线CSL，译码选择信号线CSL电连接列译码电路404以及存储阵列，使列译码电路404对存储阵列进行定位。
以下将结合附图对存储器进行详细说明，图10中三角形表示电连接，且图10中仅在单个感测放大器阵列42上以虚线示意出与该感测放大器阵列42连接的第一数据线Ldat以及第一互补数据线Ldat#，与其他感测放大器阵列42连接的第一数据线以及第一互补数据线未示出。
每一存储阵列包括存储单元阵列41以及灵敏放大器阵列42。存储单元阵列41中包括多个存储元件，用于存储数据；灵敏放大器阵列42用于放大存储单元阵列的输出信号。由于第二数据线为单相位方式，因此存储器所需的数据线减少，对于所需第二数据线的数量而言，由现有技术的2N根减小至N根。
感测放大器阵列包括：位于奇数列的多个第一组感测放大器阵列4011以及位于偶数列的多个第二组感测放大器阵列4012。为方便示意，图10示意的4011包括与奇数列的感测放大器阵列42连接的存储单元阵列41，示意的4012包括与偶数列的感测放大器阵列42连接的存储单元阵列41。
第二数据线YIO包括：与第一组组感测放大器阵列4011对应的第一 类数据线YIO1，与第二组组感测放大器阵列4012对应的第二类数据线YIO2，且第一组数据线YIO1与第一组感测放大器阵列4011连接的第一数据线Ldat以及第一互补数据线Ldat#对应，第二组数据线YIO2与第二组感测放大器阵列4012连接的第一数据线Ldat以及第一互补数据线Ldat#对应。
参考数据线包括：用于提供第一参考基准信号的第一参考数据线YIO#1以及用于提供第二参考基准信号的第二参考数据线YIO#2，为了便于图示，图10中以点划线示意出第一参考数据线YIO#1，以虚线示意出第二参考数据线YIO#2。参考基准模块包括：第一参考基准单元，第一参考单元适于向第一参考数据线YIO#1输出第一参考基准信号，第一参考基准信号作为第一类数据线YIO1的数据信号的参考基准；第二参考基准单元，第二参考基准单元适于向第二参考数据线YIO#2输出第二参考基准信号，第二参考基准信号作为第二类数据线YIO2的数据信号的参考基准。
放大模块403包括：第一组放大模块，接收第一参考基准信号以及第一组数据线YIO1的数据信号，对第一组数据线YIO1的数据信号进行放大；第二组放大模块，接收第二参考基准信号以及第二组数据线YIO2的数据信号，对第二组数据线YIO2的数据信号进行放大。
放大模块403与第二数据线以及参考数据线连接，用于响应于第二数据线的数据信号以及基准参考信号，对第二数据线的数据信号进行放大并输出。第一组放大模块对奇数列的多个第一组感测放大器阵列4011连接的第一组数据线YIO1进行放大；第二组放大模块对偶数列的多个第二组感测放大器阵列4012连接的第二组数据线YIO2进行放大。
有关放大模块的详细描述，可参考前述实施例的相应说明。
本实施例中，如图11所示，图11为图10顺时针旋转90°对应的局部示意图，如图11所示，本实施例中，多根第二数据线YIO中的一半位于第一参考数据线YIO#1以及第二参考数据线YIO#2的一侧，多根第二数据线YIO中的另一半位于第一参考数据线YIO#1以及所述第二参考数据线YIO#2的另一侧。也就是说，第一参考数据线YIO#1以及第二参数据线YIO#2布局在所有第二数据线YIO的中间位置，这样，从选中的感测放大器阵列42位置到第二数据线YIO末端的放大模块403的路径长度基本一致，减小路径长度不一致带来的损耗以及寄生电路不一致的问题，有利于进一步的改善存储器的性能。
第一组放大模块与奇数列的感测放大器阵列42对应，第二组放大模块与偶数列的感测放大器阵列42对应。本实施例中，与处于奇数列的感测放大器阵列42对应的第一组放大模块共用同一根第一参考数据线YIO#1，与处于偶数列的感测放大器阵列42对应的第二组放大模块共用同一根第二参考数据线YIO#2。
存储器还包括：全局写控制电路407，全局写控制电路407与第二数据线连接。具体地，一全局写控制电路407与第一组数据线YIO1连接，另一全局写控制电路407与第二组数据线YIO2连接。
本实施例提供的存储器可以为DRAM存储器，如DDR3 DRAM、DDR4 DRAM或者DDR5 DRAM。在其他实施例中，存储器还可以为SRAM、MRAM、FeRAM、PCRAM、NAND、NOR等存储器。
有关读取操作期间的工作机理，可参考前述实施例的详细描述，在此 不再赘述。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种半导体集成电路，其特征在于，包括：经由列选择模块与位线连接的第一数据线，经由列选择模块与互补位线连接的第一互补数据线，第二数据线，参考数据线，所述参考数据线用于提供参考基准信号，还包括：
    本地读写转换模块，响应于读写控制信号，在读写操作期间，所述第一数据线与所述第二数据线之间传输数据，所述第一互补数据线与所述第二数据线之间传输数据；
    放大模块，用于接收所述第二数据线的数据信号以及所述参考基准信号，对所述第二数据线的数据信号进行放大，所述参考基准信号作为放大所述第二数据线的数据信号的参考基准。
  2. 如权利要求1所述的半导体集成电路，其特征在于，所述参考数据线具有固定电位。
  3. 如权利要求1所述的半导体集成电路，其特征在于，还包括：参考基准模块，响应于所述读写控制信号中的读取控制信号，向所述参考数据线输出所述参考基准信号，在读操作期间，所述参考基准模块具有放电特性，以使所述参考基准信号的电位逐渐降低。
  4. 如权利要求3所述的半导体集成电路，其特征在于，在所述读操作期间，所述第二数据线由第一电平降低为第二电平的过程中，所述本地读写转换模块具有第一放电速度；在所述读操作期间，所述参考基准模块具有第二放电速度，且所述第二放电速度小于所述第一放电速度。
  5. 如权利要求3所述的半导体集成电路，其特征在于，还包括：用于提供参考 控制信号的参考控制线，且所述参考基准模块与所述参考控制线连接，所述参考基准模块响应于所述读取控制信号以及所述参考控制信号，向所述参考数据线输出所述参考基准信号。
  6. 如权利要求5所述的半导体集成电路，其特征在于，所述参考基准模块具有第一端口、第二端口、第三端口以及第四端口，所述第一端口接收所述读取控制信号，所述第二端口连接所述参考数据线，所述第三端口接地，所述第四端口接收所述参考控制信号，所述参考基准模块响应于所述读取控制信号以及所述参考控制信号，使第二端口与所述第三端口之间放电，以使所述参考数据线的电位逐渐降低。
  7. 如权利要求6所述的半导体集成电路，其特征在于，所述参考基准模块包括：第一开关单元，所述第一开关单元与所述第一端口以及所述第三端口连接，所述第一开关单元具有第一节点，所述第一开关单元响应于所述读取控制信号以导通使所述第一节点与所述第三端口连接；第二开关单元，所述第二开关单元与所述第二端口以及所述第四端口连接，所述第二开关单元具有第二节点，所述第二节点与所述第一节点连接，所述第二开关单元响应于所述参考控制信号以导通使所述第二端口与所述第二节点连接。
  8. 如权利要求6所述的半导体集成电路，其特征在于，所述本地读写转换模块包括：本地读取单元，响应于所述读写控制信号中的读取控制信号，在读取操作期间，将所述第一数据线或者所述第一互补数据线的数据信号传输至所述第二数据线；所述本地读取单元包括至少2个本地晶体管，所述参考基准模块包括至少1个参考晶体管，且至少一个参考晶体管的导通能力小于所述 本地晶体管的导通能力。
  9. 如权利要求8所述的半导体集成电路，其特征在于，每一所述参考晶体管的沟道宽度均小于所述本地晶体管的沟道宽度。
  10. 如权利要求8所述的半导体集成电路，其特征在于，所述至少2个本地晶体管包括：本地读取控制管，响应于所述读取控制信号导通，且所述本地读取控制管的一个端口接地；本地读取传输管，响应于所述第一互补数据线的数据信号导通，使所述第二数据线经由所述本地读取传输管以及所述本地读取控制管接地；
    所述至少1个参考晶体管包括：参考控制管，响应于所述读取控制信号导通，使所述参考数据线经由所述参考控制管接地，且所述参考控制管的沟道宽度小于所述本地读取控制管的沟道宽度。
  11. 如权利要求10所述的半导体集成电路，其特征在于，所述至少1个参考晶体管还包括：参考传输管，响应于所述参考控制信号导通，使所述参考数据线经由所述参考控制管以及所述参考传输管接地，且所述参考传输管的沟道宽度小于所述本地读取传输管的沟道宽度。
  12. 如权利要求11所述的半导体集成电路，其特征在于，所述参考控制管的沟道宽度小于或等于所述本地读取控制管的沟道宽度的2/3；所述参考传输管的沟道宽度小于或等于所述本地读取传输管的沟道宽度的2/3。
  13. 如权利要求12所述的半导体集成电路，其特征在于，所述参考控制管的沟道宽度为所述本地读取控制管的沟道宽度的1/2；所述参考传输管的沟道宽度为所述本地读取传输管的沟道宽度的1/2。
  14. 如权利要求3所述的半导体集成电路，其特征在于，所述放大模块包括差分放大器，所述差分放大器的第一输入端与所述第二数据线连接，所述差分放大器的第二输入端与所述参考数据线连接。
  15. 如权利要求1所述的半导体集成电路，其特征在于，还包括：本地放大模块，所述本地放大模块连接在所述第一数据线与所述第一互补数据线之间，用于对所述第一数据线的数据以及所述第一互补数据线的数据放大。
  16. 如权利要求15所述的半导体集成电路，其特征在于，所述本地放大模块包括：第一反相器，所述第一反相器的第一输入端与所述第一数据线电连接，所述第一反相器的第一输出端与所述第一互补数据线电连接；第二反相器，所述第二反相器的第二输入端与所述第一反相器的第一输出端以及所述第一互补数据线电连接，所述第二反相器的第二输出端与所述第一反相器的第一输入端以及所述第一数据线电连接。
  17. 一种存储器，其特征在于，包括：
    交替排布的存储单元阵列以及感测放大器阵列，每一所述存储单元阵列与至少一所述感测放大器阵列连接构成存储阵列；
    如权利要求1所述的半导体集成电路，每一所述第一数据线以及所述第一互补数据线均与经由所述感测放大器阵列与相应的所述存储单元阵列连接，利用所述本地读写转换模块对所述存储单元阵列进行读写操作。
  18. 如权利要求17所述的存储器，其特征在于，所述感测放大器阵列包括：位于奇数列的多个第一组感测放大器阵列以及位于偶数列的多个第二组感测放大器阵列；
    所述第二数据线包括：与所述第一组感测放大器阵列对应的第一组数据线，与所述第二组感测放大器阵列对应的第二组数据线，且所述第一组数据线与所述第一组感测放大器阵列连接的所述第一数据线以及所述第一互补数据线对应，所述第二组数据线与所述第二组感测放大器阵列连接的所述第一数据线以及所述第一互补数据线对应；所述参考数据线包括：用于提供第一参考基准信号的第一参考数据线以及用于提供第二参考基准信号的第二参考数据线；
    所述放大模块包括：第一组放大模块，接收所述第一参考基准信号以及所述第一组数据线的数据信号，对所述第一组数据线的数据信号进行放大；第二组放大模块，接收所述第二参考基准信号以及所述第二组数据线的数据信号，对所述第二组数据线的数据信号进行放大。
  19. 如权利要求18所述的存储器，其特征在于，所述第一组放大模块与奇数列的所述感测放大器阵列对应，所述第二组放大模块与偶数列的所述感测放大器阵列对应；所述第一组放大模块共用同一根第一参考数据线，所述第二组放大模块共用同一根第二参考数据线。
  20. 如权利要求18所述的存储器，其特征在于，多根所述第二数据线中的一半位于所述第一参考数据线以及所述第二参考数据线的一侧，多根所述第二数据线中的另一半位于所述第一参考数据线以及所述第二参考数据线的另一侧。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116895310A (zh) * 2023-07-27 2023-10-17 合芯科技(苏州)有限公司 双端读写的存储装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116486853A (zh) * 2022-01-14 2023-07-25 长鑫存储技术有限公司 本地放大电路、数据读出方法和存储器
CN116486854A (zh) * 2022-01-14 2023-07-25 长鑫存储技术有限公司 本地放大电路、数据读出方法和存储器
CN114566207B (zh) * 2022-04-29 2022-07-19 长鑫存储技术有限公司 存储器的测试方法及测试装置
CN117542389B (zh) * 2024-01-10 2024-05-03 长鑫存储技术(西安)有限公司 半导体存储器
CN117577148B (zh) * 2024-01-15 2024-05-03 长鑫存储技术(西安)有限公司 半导体存储器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1637947A (zh) * 2004-01-07 2005-07-13 三星电子株式会社 半导体存储器件及其数据读取和写入方法
CN101952957A (zh) * 2008-02-19 2011-01-19 美光科技公司 具有本地数据线的存储器装置及其制造和操作方法
CN102405499A (zh) * 2009-04-20 2012-04-04 桑迪士克3D公司 具有数据线切换方案的存储器系统
CN104051008A (zh) * 2013-03-11 2014-09-17 旺宏电子股份有限公司 存储器装置及降低读取操作下位线上耦合噪声的方法
US20150078058A1 (en) * 2013-09-19 2015-03-19 Renesas Electronics Corporation Semiconductor storage device and test method thereof
CN212392000U (zh) * 2020-06-19 2021-01-22 长鑫存储技术(上海)有限公司 半导体集成电路以及存储器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1637947A (zh) * 2004-01-07 2005-07-13 三星电子株式会社 半导体存储器件及其数据读取和写入方法
CN101952957A (zh) * 2008-02-19 2011-01-19 美光科技公司 具有本地数据线的存储器装置及其制造和操作方法
CN102405499A (zh) * 2009-04-20 2012-04-04 桑迪士克3D公司 具有数据线切换方案的存储器系统
CN104051008A (zh) * 2013-03-11 2014-09-17 旺宏电子股份有限公司 存储器装置及降低读取操作下位线上耦合噪声的方法
US20150078058A1 (en) * 2013-09-19 2015-03-19 Renesas Electronics Corporation Semiconductor storage device and test method thereof
CN212392000U (zh) * 2020-06-19 2021-01-22 长鑫存储技术(上海)有限公司 半导体集成电路以及存储器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
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* Cited by examiner, † Cited by third party
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CN116895310A (zh) * 2023-07-27 2023-10-17 合芯科技(苏州)有限公司 双端读写的存储装置
CN116895310B (zh) * 2023-07-27 2024-02-27 合芯科技(苏州)有限公司 双端读写的存储装置

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