WO2022062556A1 - 集成电路 - Google Patents

集成电路 Download PDF

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Publication number
WO2022062556A1
WO2022062556A1 PCT/CN2021/104221 CN2021104221W WO2022062556A1 WO 2022062556 A1 WO2022062556 A1 WO 2022062556A1 CN 2021104221 W CN2021104221 W CN 2021104221W WO 2022062556 A1 WO2022062556 A1 WO 2022062556A1
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Prior art keywords
data line
local data
complementary
nmos transistor
integrated circuit
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PCT/CN2021/104221
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English (en)
French (fr)
Inventor
尚为兵
张凤琴
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长鑫存储技术有限公司
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Priority to EP21870935.0A priority Critical patent/EP4027346B1/en
Priority to US17/577,103 priority patent/US11900991B2/en
Publication of WO2022062556A1 publication Critical patent/WO2022062556A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to an integrated circuit.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line
  • the data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • DRAM can be divided into Double Data Rate (DDR) DRAM, GDDR (Graphics Double Data Rate) DRAM, and Low Power Double Data Rate (LPDDR) DRAM.
  • DDR Double Data Rate
  • GDDR Graphics Double Data Rate
  • LPDDR Low Power Double Data Rate
  • DRAM is applied in more and more fields, for example, DRAM is more and more used in the mobile field, users have higher and higher requirements for DRAM power consumption indicators.
  • a first data line group the first data line group includes a plurality of local data lines arranged in an array
  • a second data line group the second data line group includes a plurality of complementary local data lines arranged in an array, wherein , a plurality of the complementary local data lines respectively transmit signals with opposite phases to the plurality of the local data lines
  • a plurality of read circuits in response to a read control signal, are used to read the local data lines or the signals of the complementary local data lines, wherein a plurality of the read circuits are respectively electrically connected to the local data lines on the edge of the first data line group or with the complementary local data lines on the edge of the second data line group Local data line connection.
  • the integrated circuit during the operation of the integrated circuit, there is noise interference between adjacent data lines, which may even lead to errors in data transmission. Since the data lines are usually arranged in an array, Therefore, the data lines at the edge of the data line group will only be disturbed by one adjacent data line.
  • the complementary local data line connection of the integrated circuit enables the integrated circuit to use the data line less affected by noise as the output conversion, thereby improving the data reliability and reducing the power consumption of the integrated circuit, thereby improving the performance of the integrated circuit.
  • the first set of data lines includes 4 of the local data lines
  • the second set of data lines includes 4 of the complementary local data lines
  • the first data line group includes a first local data line, a second local data line, a third local data line, and a fourth local data line arranged in sequence
  • the second data line group includes sequentially arranged second complementary local data line, first complementary local data line, fourth complementary local data line and third complementary local data line, said first local data line, said fourth local data line, said second The complementary local data line and the third complementary local data line are respectively electrically connected to the read circuit; wherein the first local data line and the first complementary local data line, the second local data line and the The second complementary local data line, the third local data line and the third complementary local data line, and the fourth local data line and the fourth complementary local data line respectively transmit signals with opposite phases.
  • a plurality of the local data lines are arranged at equal intervals, and/or a plurality of the complementary local data lines are arranged at equal intervals.
  • the distance between the first local data line and the second local data line is greater than the distance between the second local data line and the third local data line, and/or all The distance between the third local data line and the fourth local data line is greater than the distance between the second local data line and the third local data line.
  • the capacitance between the data line and the second local data line and the capacitance between the third local data line and the fourth local data line further reduce the noise impact of the second local data line on the first local data line and the third
  • the noise influence of the local data line on the fourth local data line further reduces the power consumption of the integrated circuit.
  • the spacing between the second complementary local data line and the first complementary local data line is greater than the spacing between the first complementary local data line and the fourth complementary local data line
  • the spacing between the fourth complementary local data line and the third complementary local data line is greater than the spacing between the first complementary local data line and the fourth complementary local data line.
  • the capacitance between the second complementary local data line and the first complementary local data line and the capacitance between the fourth complementary local data line and the third complementary local data line are reduced, thereby further reducing the first complementary local data line to the second complementary local data line.
  • the noise effect of the complementary local data line and the noise effect of the fourth complementary local data line on the third complementary local data line further reduce the power consumption of the integrated circuit.
  • the integrated circuit further includes shielded lines between the first local data line and the second local data line, and/or the third local data line to the fourth local data line There are shielded wires between the wires. In this way, the shielded wire can shield the noise of the second local data line to the first local data line and the noise of the third local data line to the fourth local data line, thereby further reducing the power consumption of the integrated circuit.
  • the integrated circuit further includes shielded lines, the second complementary local data line and the first complementary local data line, and/or the fourth complementary local data line and the third complementary local data line There are shielded wires between the local data wires.
  • the shielded wire can shield the noise of the first complementary local data line to the second complementary local data line and the noise of the fourth complementary local data line to the third complementary local data line, thereby further reducing the integrated circuit power consumption.
  • the integrated circuit further includes a plurality of global data lines and a plurality of complementary global data lines, wherein the global data lines and the complementary global data lines transmit signals in opposite phases, and the read circuit is responsive to reading A control signal is fetched for transmitting the signal of the local data line or the complementary local data line to the global data line or the complementary global data line during a read operation.
  • the readout circuit includes a first NMOS transistor and a second NMOS transistor.
  • the source of the first NMOS transistor is grounded, the drain is electrically connected to the source of the second NMOS transistor, the gate receives the read control signal, and the gate of the second NMOS transistor
  • the local data line or the complementary local data line is electrically connected, and the drain is electrically connected to the complementary global data line or the global data line.
  • the source of the first NMOS transistor is grounded, the drain is electrically connected to the source of the second NMOS transistor, and the gate is electrically connected to the local data line or the complementary local data line, and the The gate of the second NMOS transistor receives the read control signal, and the drain is electrically connected to the complementary global data line or the global data line.
  • the integrated circuit further includes a plurality of amplifying units, respectively connected between the local data lines and the corresponding complementary local data lines, and configured to compare the signals of the local data lines and the corresponding complementary local data lines. Signal amplification of complementary local data lines.
  • the integrated circuit further includes a plurality of write units responsive to write control signals for transmitting signals of the global data line and/or the complementary global data line to the write operation during a write operation the local data line and/or the complementary local data line.
  • the writing unit includes a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, the source of the third NMOS transistor is grounded, the gate receives the writing control signal, and the drain
  • the source of the fourth NMOS transistor is electrically connected
  • the gate of the fourth NMOS transistor is electrically connected to the global data line
  • the drain is electrically connected to the complementary local data line
  • the source of the fifth NMOS transistor is electrically connected.
  • the global data line is connected, the gate receives the write control signal, and the drain is electrically connected to the local data line.
  • the writing unit includes a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor, the source of the sixth NMOS transistor is grounded, the gate receives the write control signal, and the drain
  • the source electrode of the seventh NMOS transistor is electrically connected
  • the gate electrode of the seventh NMOS transistor is electrically connected to the complementary global data line
  • the drain electrode is electrically connected to the local data line
  • the source electrode of the eighth NMOS transistor is electrically connected.
  • the complementary global data line is connected, the gate receives the write control signal, and the drain is electrically connected to the complementary local data line.
  • FIG. 1 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present disclosure
  • FIG. 2 is another schematic structural diagram of an integrated circuit provided by an embodiment of the present disclosure
  • FIG. 3 is another schematic structural diagram of an integrated circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another integrated circuit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another integrated circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another integrated circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of functional modules of an integrated circuit provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a circuit structure of an integrated circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of another circuit structure of an integrated circuit provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of another circuit structure of an integrated circuit provided by an embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of still another circuit structure of an integrated circuit provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a partially enlarged structure of the region A in FIG. 13 .
  • the inventors of the present disclosure found that for the same DRAM in the prior art, there is noise interference between adjacent data lines.
  • there is usually no shielding wire between the data lines to block noise which leads to a relatively large noise interference between the data lines and increases the power consumption of the integrated circuit. That is to say, at present, the data lines of the memory are greatly affected by noise, and the power consumption is large.
  • the present disclosure provides an integrated circuit, which is electrically connected to the local data lines on the edge of the first data line group or with the complementary local data lines on the edge of the second data line group through a plurality of reading circuits, so that the The integrated circuit uses a data line that is less affected by noise as the output conversion, thereby reducing the power consumption of the integrated circuit, thereby improving the performance of the integrated circuit.
  • FIG. 1 is an integrated circuit 100 according to an embodiment of the present disclosure.
  • the integrated circuit 100 includes: a first data line group 1 , the first data line group 1 includes a plurality of local data lines Ldat arranged in an array; a second data line group 2 , a second data line group 1
  • the line group 2 includes a plurality of complementary local data lines Ldat# arranged in an array, wherein the plurality of complementary local data lines Ldat# and the plurality of local data lines Ldat respectively transmit signals with opposite phases;
  • the plurality of reading circuits 3, in response to The read control signal is used to read the signal of the local data line Ldat or the complementary local data line Ldat# during the read operation, wherein the plurality of read circuits 3 are respectively electrically connected to the local data lines Ldat on the edge of the first data line group 1 Or connected with the complementary local data line Ldat# at the edge of the second data line group 2 .
  • the read data or the written data signals are in pairs, and each pair of data signals includes two pieces of data.
  • one of the two pieces of data is is a high-level signal, and the other data is a low-level signal. Therefore, the read-write conversion circuit at least includes a pair of local data lines Ldat and a complementary local data line Ldat#.
  • the local data line Ldat is a local data line (also called a local data line)
  • the complementary local data line Ldat# is a complementary local data line.
  • the reading circuit 3 in this embodiment is not electrically connected to the local data line Ldat or the complementary local data line Ldat# in the non-edge position in the first data line group 1 or the second data line group 2, It is only electrically connected with the local data line Ldat at the edge position of the first data line group 1 or the complementary local data line Ldat# at the edge position in the second data line group 2 .
  • the integrated circuit 100 uses the The data lines with less noise influence are used as output conversions, thereby improving data reliability and reducing power consumption of the integrated circuit 100 , thereby improving the performance of the integrated circuit 100 .
  • the first data line group 1 includes four local data lines Ldat
  • the second data line group 2 includes four complementary local data lines Ldat#.
  • this embodiment does not specifically limit the number of local data lines Ldat in the first data line group and the number of complementary local data lines Ldat# in the second data line group 2, which can be set according to actual requirements.
  • the first data line group 1 includes a first local data line Ldat1 , a second local data line Ldat2 , a third local data line Ldat3 and a fourth local data line Ldat4 arranged in sequence
  • the second data line group 2 It includes a second complementary local data line Ldat#2, a first complementary local data line Ldat#1, a fourth complementary local data line Ldat#4, a third complementary local data line Ldat#3, and a first complementary local data line Ldat1.
  • the fourth local data line Ldat4, the second complementary local data line Ldat#2 and the third complementary local data line Ldat#3 are respectively electrically connected to the reading circuit 3; wherein the first local data line Ldat1 and the first complementary local data line Ldat#1, the second local data line Ldat2 and the second complementary local data line Ldat#2, the third local data line Ldat3 and the third complementary local data line Ldat#3, and the fourth local data line Ldat4 and the fourth complementary local data
  • the lines Ldat#4 transmit signals with opposite phases, respectively.
  • a plurality of local data lines Ldat are arranged at equal intervals, and/or a plurality of complementary local data lines Ldat# are arranged at equal intervals.
  • the distance between the first local data line Ldat1 and the second local data line Ldat2 is greater than the distance between the second local data line Ldat2 and the third local data line Ldat3
  • the distance between the third local data line Ldat3 and the fourth local data line Ldat4 is greater than the distance between the second local data line Ldat2 and the third local data line Ldat3. Since the first local data line Ldat1 and the fourth local data line Ldat4 are located at the edge positions of the first data line group 1, that is to say, the two read circuits 3 are connected to the first local data line Ldat1 and the fourth local data line Ldat4 respectively.
  • the connection through the setting of this structure, can increase the distance between the first local data line Ldat1 and the second local data line Ldat2, and increase the distance between the third local data line Ldat3 and the fourth local data line Ldat4.
  • the distance between the first local data line Ldat1 and the second local data line Ldat2 and the capacitance between the third local data line Ldat3 and the fourth local data line Ldat4 are reduced, thereby further reducing the second local data line Ldat4
  • the noise influence of the line Ldat2 on the first local data line Ldat1 is reduced, and the noise influence of the third local data line Ldat3 on the fourth local data line Ldat4 is reduced, thereby further reducing noise interference.
  • the distance between the second local data line Ldat2 and the third local data line Ldat3 can be designed to be the smallest distance that can be achieved in the process, so that the first local data line Ldat1 and the second local data line Ldat1
  • the distance between the lines Ldat2, the distance between the third local data line Ldat3 and the fourth local data line Ldat4 is the largest, so that the noise influence of the second local data line Ldat2 on the first local data line Ldat1, and the third local data
  • the line Ldat3 has the least influence on the noise of the fourth local data line Ldat4.
  • the distance between the first local data line Ldat1 and the second local data line Ldat2 shown in FIG. 2 is greater than the distance between the second local data line Ldat2 and the third local data line Ldat3, the third local data line Ldat3
  • the spacing between the line Ldat3 and the fourth local data line Ldat4 is greater than the spacing between the second local data line Ldat2 and the third local data line Ldat3.
  • the distance between the first local data line Ldat1 and the second local data line Ldat2 may also be greater than the distance between the second local data line Ldat2 and the third local data line Ldat3, and the third local data line Ldat3
  • the distance from the fourth local data line Ldat4 is equal to the distance between the second local data line Ldat2 and the third local data line Ldat3; it can also be the distance between the first local data line Ldat1 and the second local data line Ldat2 equal to the distance between the second local data line Ldat2 and the third local data line Ldat3, and the distance between the third local data line Ldat3 and the fourth local data line Ldat4 is greater than the second local data line Ldat2 and the third local data line Ldat3
  • this embodiment does not specifically limit the relative positional relationship of the data lines in the first data line group 1 .
  • the distance between the second complementary local data line Ldat#2 and the first complementary local data line Ldat#1 is greater than that between the first complementary local data line Ldat#1 and the fourth complementary local data line Ldat#1
  • the spacing between the complementary local data lines Ldat#4 and the spacing between the fourth complementary local data line Ldat#4 and the third complementary local data line Ldat#3 are larger than the spacing between the first complementary local data line Ldat#1 and the fourth complementary local data line Ldat#1. Spacing between data lines Ldat#4.
  • the second complementary local data line Ldat#2 and the third complementary local data line Ldat#3 are located at the edge positions of the second data line group 2, that is to say, the two reading circuits 3 are connected to the second complementary local data line Ldat respectively.
  • #2 is connected to the third complementary local data line Ldat#3, through the arrangement of this structure, it is possible to increase the distance between the second complementary local data line Ldat#2 and the first complementary local data line Ldat#1, and By increasing the distance between the fourth complementary local data line Ldat#4 and the third complementary local data line Ldat#3, the distance between the second complementary local data line Ldat#2 and the first complementary local data line Ldat#1 is reduced.
  • the distance between the first complementary local data line Ldat#1 and the fourth complementary local data line Ldat#4 may be designed to be the smallest distance achievable in the process, so that the second complementary local data line Ldat#4 The distance between the line Ldat#2 and the first complementary local data line Ldat#1, and the distance between the fourth complementary local data line Ldat#4 and the third complementary local data line Ldat#3 are the largest, so that the first complementary local The noise influence of the data line Ldat#1 on the second complementary local data line Ldat#2 and the noise influence of the fourth complementary local data line Ldat#4 on the third complementary local data line Ldat#3 are minimal.
  • the distance between the second complementary local data line Ldat#2 and the first complementary local data line Ldat#1 shown in FIG. 3 is greater than that between the first complementary local data line Ldat#1 and the fourth complementary local data line
  • the spacing between Ldat#4 and the spacing between the fourth complementary local data line Ldat#4 and the third complementary local data line Ldat#3 is larger than that between the first complementary local data line Ldat#1 and the fourth complementary local data line Ldat Spacing between #4.
  • the distance between the second complementary local data line Ldat#2 and the first complementary local data line Ldat#1 may also be greater than the distance between the first complementary local data line Ldat#1 and the fourth complementary local data line Ldat# 4, the distance between the fourth complementary local data line Ldat#4 and the third complementary local data line Ldat#3 is equal to the distance between the first complementary local data line Ldat#1 and the fourth complementary local data line Ldat#4.
  • the distance between the second complementary local data line Ldat#2 and the first complementary local data line Ldat#1 is equal to the first complementary local data line Ldat#1 and the fourth complementary local data line Ldat#4 and the distance between the fourth complementary local data line Ldat#4 and the third complementary local data line Ldat#3 is greater than the distance between the first complementary local data line Ldat#1 and the fourth complementary local data line Ldat#4.
  • this embodiment does not specifically limit the relative positional relationship of the data lines in the second data line group 2 .
  • the distance between the first local data line Ldat1 and the second local data line Ldat2 is greater than the distance between the first local data line Ldat1 and the second local data line Ldat2 in combination with the arrangement positions of the data lines in FIGS. 2 to 3 .
  • the distance between the two local data lines Ldat2 and the third local data line Ldat3, and the distance between the third local data line Ldat3 and the fourth local data line Ldat4 is greater than that between the second local data line Ldat2 and the third local data line Ldat3
  • the distance between the second complementary local data line Ldat#2 and the first complementary local data line Ldat#1 is greater than the distance between the first complementary local data line Ldat#1 and the fourth complementary local data line Ldat#4
  • the distance between the fourth complementary local data line Ldat#4 and the third complementary local data line Ldat#3 is greater than the distance between the first complementary local data line Ldat#1 and the fourth complementary local data line Ldat#4, Therefore, the noise interference of the integrated circuit 100 can be further reduced, and the reliability of data transmission can be improved.
  • the integrated circuit 100 further includes a shielding line 4 , and shielding is provided between the first local data line Ldat1 and the second local data line Ldat2 and between the third local data line Ldat3 and the fourth local data line Ldat4 Line 4. Since the first local data line Ldat1 and the fourth local data line Ldat4 are located at the edge positions of the first data line group 1, that is to say, the two read circuits 3 are connected to the first local data line Ldat1 and the fourth local data line Ldat4 respectively.
  • the shielded wire 4 can shield the noise from the second local data wire Ldat2 to the first local data wire Ldat1 and the noise from the third local data wire Ldat3 to the fourth local data wire Ldat4, thereby further improving the data reliability.
  • shielded wires 4 are provided between the first local data line Ldat1 and the second local data line Ldat2 and between the third local data line Ldat3 and the fourth local data line Ldat4 shown in FIG. 5 . It is also possible to only set the shielding line 4 between the first local data line Ldat1 and the second local data line Ldat2, or only set the shielding line 4 between the third local data line Ldat3 to the fourth local data line Ldat4, but not make specific restrictions.
  • the integrated circuit 100 further includes a shielded line 4, between the second complementary local data line Ldat#2 and the first complementary local data line Ldat#1, and between the fourth complementary local data line Ldat#4 and the third complementary local data line Ldat#4 Shielded wires 4 are provided between the data wires Ldat#3. Since the second complementary local data line Ldat#2 and the third complementary local data line Ldat#3 are located at the edge positions of the second data line group 2, that is to say, the two reading circuits 3 are connected to the second complementary local data line Ldat respectively. #2 is connected to the third complementary local data line Ldat#3.
  • the shielding line 4 can be made to shield the noise from the first complementary local data line Ldat#1 to the second complementary local data line Ldat#2, as well as shield the second complementary local data line Ldat#2.
  • the fourth complementary local data line Ldat#4 and the third complementary local data line Ldat# 3 are provided with a shielded wire 4.
  • a shielded wire 4 may be provided only between the second complementary local data line Ldat#2 and the first complementary local data line Ldat#1, or only between the fourth complementary local data line.
  • a shield line 4 is arranged between Ldat#4 and the third complementary local data line Ldat#3, which is not specifically limited.
  • the third local Between the data line Ldat3 to the fourth local data line Ldat4, between the second complementary local data line Ldat#2 and the first complementary local data line Ldat#1, between the fourth complementary local data line Ldat#4 and the third complementary local data Lines Ldat#3 are provided with shielded lines 4 , so that data reliability can be further improved, and power consumption of the integrated circuit 100 is also reduced, so that the performance of the integrated circuit 100 is more superior.
  • the integrated circuit 100 further includes a plurality of global data lines Gdat and a plurality of complementary global data lines Gdat#, wherein the global data lines Gdat and the complementary global data lines Gdat# transmit signals with opposite phases, and the read circuit 3 responds to The read control signal is used to transmit the signal of the local data line Ldat or the complementary local data line Ldat# to the global data line Gdat or the complementary global data line Gdat# during the read operation.
  • the integrated circuit 100 further includes a plurality of amplifying units 102, which are respectively connected between the local data line Ldat and the corresponding complementary local data line Ldat#, and are used for the signal of the local data line Ldat and the signal of the complementary local data line Ldat#. enlarge.
  • the integrated circuit 100 includes a read/write conversion unit 101 , an amplifying unit 102 and a column selection unit 103 , the read circuit 3 belongs to the read/write conversion unit 101 , and the read/write conversion unit 101 further includes a write unit.
  • the write unit is connected to both the local data line Ldat and the complementary local data line Ldat#, and the write unit is responsive to the write control signal for switching the global data line Gdat and/or the complementary global data line Gdat# during a write operation.
  • the signal is transmitted to the local data line Ldat and/or the complementary local data line Ldat#.
  • the local data line Ldat is connected to the bit line BL via the column selection unit 103
  • the complementary local data line Ldat# is electrically connected to the complementary bit line BL# via the column selection unit 103 .
  • the read/write conversion unit 101 transmits data between the local data line Ldat and the global data line Gdat, and transmits data between the complementary local data line Ldat# and the complementary global data line Gdat# during the read/write operation.
  • the amplifying unit 102 is connected between the local data line Ldat and the complementary local data line Ldat#, and is used for amplifying the data of the local data line Ldat and the data of the complementary local data line Ldat#.
  • the read and write control signals include a read control signal Rd and a write control signal Wr.
  • the read-write conversion unit 101 transmits the data of the local data line Ldat and the complementary local data line Ldat# to the global data line Gdat and the complementary global data line Gdat#, or, in response to In response to the write control signal Wr, the read/write conversion unit 101 transmits the data of the global data line Gdat and the complementary global data line Gdat# to the local data line Ldat and the complementary local data line Ldat#.
  • the amplifying unit 102 constitutes a circuit for amplifying the signal of the local data line Ldat and the signal of the complementary local data line Ldat#, which helps to speed up the distinction between the local data line Ldat and the complementary local data line Ldat#, thereby increasing the speed of data signal transmission and improving the Data read and write speed.
  • the local data line Ldat and the complementary local data line Ldat# have lower requirements for the driving capability of the first-stage amplifying circuit in the memory, so even if The area of the first-stage amplifying circuit is gradually reduced, and the first-stage amplifying circuit still has sufficient driving capability for the local data line Ldat and the complementary local data line Ldat#, so as to meet the development trend of device miniaturization, It is ensured that the read-write conversion circuit has good electrical performance, thereby improving the storage performance of the memory including the read-write conversion circuit.
  • the reading circuit 3 includes a first NMOS transistor MN1 and a second NMOS transistor MN2.
  • the source of the first NMOS transistor MN1 is grounded, the drain is electrically connected to the source of the second NMOS transistor MN2, and the gate receives the read control signal Rd.
  • the gate of the second NMOS transistor MN2 is electrically connected to the local data line Ldat or the complementary local data line Ldat#, and the drain is electrically connected to the complementary global data line Gdat# or the global data line Gdat.
  • the reading circuit 3 includes a first NMOS transistor MN1 and a second NMOS transistor MN2.
  • the source of the first NMOS transistor MN1 is grounded, the drain is electrically connected to the source of the second NMOS transistor MN2, and the gate is electrically connected to the local data line Ldat or the complementary local data line Ldat#.
  • the gate of the second NMOS transistor MN2 receives the read control signal Rd, and the drain is electrically connected to the complementary global data line Gdat# or the global data line Gdat.
  • the writing unit includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5.
  • the source of the third NMOS transistor MN3 is grounded, the gate receives the write control signal Wr, and the drain is electrically connected to the source of the fourth NMOS transistor MN4.
  • the gate of the fourth NMOS transistor MN4 is electrically connected to the global data line Gdat, and the drain is electrically connected to the complementary local data line Ldat#.
  • the source of the fifth NMOS transistor MN5 is electrically connected to the global data line Gdat, the gate receives the write control signal Wr, and the drain is electrically connected to the local data line Ldat.
  • the writing unit includes a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8.
  • the source of the sixth NMOS transistor MN6 is grounded, the gate receives the write control signal Wr, and the drain is electrically connected to the source of the seventh NMOS transistor MN7.
  • the gate of the seventh NMO transistor MN7 is electrically connected to the complementary global data line Gdat#, and the drain is electrically connected to the local data line Ldat.
  • the source of the eighth NMOS transistor MN8 is electrically connected to the complementary global data line Gdat#, the gate receives the write control signal Wr, and the drain is electrically connected to the complementary local data line Ldat#.
  • FIG. 13 is a schematic structural diagram of a memory provided by an embodiment of the disclosure
  • FIG. 14 is a partially enlarged structural schematic diagram of area A in FIG. 13 .
  • the memory includes: a plurality of memory modules, each memory module includes a memory array 301 and a sense amplifier array 302, the sense amplifier array 302 includes a plurality of sense amplifiers 312, the memory array 301 includes a plurality of memory cells; Selection signal line CSL; word line WL; read-write conversion circuit 300, each read-write conversion circuit 300 is connected to the corresponding sense amplifier array 302, and the read-write conversion circuit 300 includes a local data line Ldat, a complementary local data line Ldat#, Global data line Gdat and complementary global data line Gdat#; row decoding circuit 303 ; column decoding circuit 304 ; driving circuit 305 .
  • the memory will be described below with reference to the working mechanism of the memory.
  • the data in the memory array 301 corresponding to the word line WL is transmitted to the sense amplifier 312, and the data is amplified by the sense amplifier 312, and then written back to the selected word line WL in the connected storage unit.
  • the column decoding circuit 304 selects the corresponding sense amplifier 312, and the data is transmitted from the global data line Gdat and the complementary global data line Gdat# to the local data line Ldat and the complementary local data line Ldat# through the read-write conversion circuit 300 , and then write into the corresponding sense amplifier 312 and the connected storage unit.
  • the read-write conversion circuit 300 not only has the function of signal transmission, but also can amplify the local data line Ldat and the complementary local data line Ldat#, which is beneficial to quickly connect the local data line Ldat and the complementary local data line Ldat# signal separately.
  • the column decoding circuit 304 selects the corresponding sense amplifier 312 and transmits the data to the local data line Ldat and the complementary local data line Ldat#, and then transmits the data to the global data line Gdat and the complementary global data line Gdat# through the read-write conversion circuit 300 .
  • the read-write conversion circuit 300 can greatly improve the discrimination speed between the local data line Ldat and the complementary local data line Ldat#, and the data passes through the sense amplifier 312, the local data line Ldat and the complementary local data line Ldat #The speed of transmission to the global data line Gdat and the complementary global data line Gdat# is increased.
  • the memory may have multiple pairs of global data lines and complementary global data lines;
  • the time memory may have multiple pairs of local data lines and complementary local data lines.
  • the memory can be DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND, NOR and other memories.
  • the memory provided in this embodiment has the advantage of fast data transmission speed and low requirement for the driving capability of the sense amplifier, which is beneficial to meet the development trend of device miniaturization.

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Abstract

本公开实施例涉及半导体技术领域，公开了一种集成电路，所述集成电路包括：第一数据线组，所述第一数据线组包括阵列排布的多条本地数据线；第二数据线组，所述第二数据线组包括阵列排布的多条互补本地数据线，其中，多条所述互补本地数据线分别与多条所述本地数据线传输相位相反的信号；多个读取电路，响应于读取控制信号，用于在读操作期间读取所述本地数据线或所述互补本地数据线的信号，其中，多个所述读取电路分别与所述第一数据线组边缘的所述本地数据线电连接或与所述第二数据线组边缘的所述互补本地数据线连接。

Description

集成电路
相关公开的交叉引用
本申请基于申请号为202011004212.9、申请日为2020年09月22日、发明名称为“集成电路”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开实施例涉及半导体技术领域，特别涉及一种集成电路。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
DRAM可以分为双倍速率同步(Double Data Rate，DDR)动态随机存储器、GDDR(Graphics Double Data Rate)动态随机存储器、低功耗双倍速率同步(Low Power Double Data Rate，LPDDR)动态随机存储器。随着DRAM应用的领域越来越多，如DRAM越来越多的应用于移动领域，用户对于DRAM功耗指标的要求越来越高。
然而，目前的DRAM性能仍有待提高。
发明内容
本公开的实施方式提供了一种集成电路，包括：
第一数据线组，所述第一数据线组包括阵列排布的多条本地数据线；第二数据线组，所述第二数据线组包括阵列排布的多条互补本地数据线，其中，多条所述互补本地数据线分别与多条所述本地数据线传输相位相反的信号；多个读取电路，响应于读取控制信号，用于在读操作期间读取所述本地数据线或所述互补本地数据线的信号，其中，多个所述读取电路分别与所述第一数据线组边缘的所述本地数据线电连接或与所述第二数据线组边缘的所述互补本地数据线连接。
本公开的实施方式相对于现有技术而言，在集成电路的工作过程中，相邻的数据线相互 之间存在噪声干扰，甚至可能导致数据传输发生错误，由于数据线通常为阵列排布，因此在数据线组边缘的数据线只会受到一根相邻数据线的干扰，通过将多个读取电路分别与第一数据线组边缘的本地数据线电连接或与第二数据线组边缘的互补本地数据线连接，使得集成电路使用的是受到噪声影响较小的数据线作为输出转换，从而提高了数据可靠性，同时也降低了集成电路的功耗，进而改善了集成电路的性能。
在一些实施例中，所述第一数据线组包括4条所述本地数据线，所述第二数据线组包括4条所述互补本地数据线。
在一些实施例中，所述第一数据线组包括依次排列的第一本地数据线、第二本地数据线、第三本地数据线和第四本地数据线，所述第二数据线组包括依次排列的第二互补本地数据线、第一互补本地数据线、第四互补本地数据线和第三互补本地数据线，所述第一本地数据线、所述第四本地数据线、所述第二互补本地数据线和所述第三互补本地数据线分别与所述读电路电连接；其中所述第一本地数据线与所述第一互补本地数据线、所述第二本地数据线与所述第二互补本地数据线、所述第三本地数据线与所述第三互补本地数据线以及所述第四本地数据线与所述第四互补本地数据线分别传输相位相反的信号。
在一些实施例中，多条所述本地数据线等间距排列，和/或多条所述互补本地数据线等间距排列。
在一些实施例中，所述第一本地数据线与所述第二本地数据线之间的间距大于所述第二本地数据线与所述第三本地数据线之间的间距，和/或所述第三本地数据线与所述第四本地数据线之间的间距大于所述第二本地数据线与所述第三本地数据线之间的间距。通过此种结构的设置，能够通过增大第一本地数据线与第二本地数据线之间的间距、第三本地数据线与第四本地数据线之间的间距的方式，减小第一本地数据线与第二本地数据线之间的电容以及第三本地数据线与第四本地数据线之间的电容，从而进一步减小第二本地数据线对第一本地数据线的噪声影响以及第三本地数据线对第四本地数据线的噪声影响，进而进一步减小了集成电路的功耗。
在一些实施例中，所述第二互补本地数据线与所述第一互补本地数据线之间的间距大于所述第一互补本地数据线与所述第四互补本地数据线之间的间距，和/或所述第四互补本地数据线与所述第三互补本地数据线之间的间距大于所述第一互补本地数据线与所述第四互补本地数据线之间的间距。通过此种结构的设置，能够通过增大第二互补本地数据线与第一互补本地数据线之间的间距、第四互补本地数据线与第三互补本地数据线之间的间距的方式，减小第二互补本地数据线与第一互补本地数据线之间的电容以及第四互补本地数据线与第三互补本地数据线之间的电容，从而进一步减小第一互补本地数据线对第二互补本地数据线的噪 声影响以及第四互补本地数据线对第三互补本地数据线的噪声影响，进而进一步减小了集成电路的功耗。
在一些实施例中，所述集成电路还包括屏蔽线，所述第一本地数据线与所述第二本地数据线之间，和/或所述第三本地数据线到所述第四本地数据线之间设有屏蔽线。通过此种方式，能够使屏蔽线屏蔽第二本地数据线对第一本地数据线的噪声、以及第三本地数据线对第四本地数据线的噪声，进而进一步减小了集成电路的功耗。
在一些实施例中，所述集成电路还包括屏蔽线，所述第二互补本地数据线与所述第一互补本地数据线，和/或所述第四互补本地数据线与所述第三互补本地数据线之间设有屏蔽线。通过此种方式，能够使屏蔽线屏蔽第一互补本地数据线对第二互补本地数据线的噪声、以及第四互补本地数据线对第三互补本地数据线的噪声，从而进一步减小了集成电路的功耗。
在一些实施例中，所述集成电路还包括多条全局数据线和多条互补全局数据线，其中所述全局数据线和互补全局数据线传输相位相反的信号，所述读取电路响应于读取控制信号，用于在读操作期间将所述本地数据线或互补本地数据线的信号传输至全局数据线或互补全局数据线。
在一些实施例中，所述读取电路包括第一NMOS管和第二NMOS管。
在一些实施例中，所述第一NMOS管的源极接地，漏极电连接所述第二NMOS管的源极，栅极接收所述读取控制信号，所述第二NMOS管的栅极电连接所述本地数据线或所述互补本地数据线，漏极电连接所述互补全局数据线或所述全局数据线。
在一些实施例中，所述第一NMOS管的源极接地，漏极电连接所述第二NMOS管的源极，栅极电连接所述本地数据线或所述互补本地数据线，所述第二NMOS管的栅极接收所述读取控制信号，漏极电连接所述互补全局数据线或所述全局数据线。
在一些实施例中，所述集成电路还包括多个放大单元，分别连接在所述本地数据线和对应的所述互补本地数据线之间，用于对所述本地数据线的信号和所述互补本地数据线的信号放大。
在一些实施例中，所述集成电路还包括多个写入单元，响应于写入控制信号，用于在写操作期间将所述全局数据线和/或所述互补全局数据线的信号传输至所述本地数据线和/或所述互补本地数据线。
在一些实施例中，所述写入单元包括第三NMOS管、第四NMOS管、第五NMOS管，所述第三NMOS管的源极接地，栅极接收所述写入控制信号，漏极电连接所述第四NMOS管的源极，所述第四NMOS管的栅极电连接所述全局数据线，漏极电连接所述互补本地数据线，所述第五NMOS管的源极电连接所述全局数据线，栅极接收所述写入控制信号，漏极电 连接所述本地数据线。
在一些实施例中，所述写入单元包括第六NMOS管、第七NMOS管、第八NMOS管，所述第六NMOS管的源极接地，栅极接收所述写入控制信号，漏极电连接所述第七NMOS管的源极，所述第七NMO管的栅极电连接所述互补全局数据线，漏极电连接所述本地数据线，所述第八NMOS管的源极电连接所述互补全局数据线，栅极接收所述写入控制信号，漏极电连接所述互补本地数据线。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本公开一实施例提供的集成电路的结构示意图；
图2为本公开一实施例提供的集成电路的另一种结构示意图；
图3为本公开一实施例提供的集成电路的又一种结构示意图；
图4为本公开一实施例提供的集成电路的再一种结构示意图；
图5为本公开一实施例提供的集成电路的还一种结构示意图；
图6为本公开一实施例提供的集成电路的还一种结构示意图；
图7为本公开一实施方式提供的集成电路的结构示意图；
图8为本公开一实施例提供的集成电路的功能模块示意图；
图9为本公开一实施例提供的集成电路的一种电路结构示意图；
图10为本公开一实施例提供的集成电路的另一种电路结构示意图；
图11为本公开一实施例提供的集成电路的又一种电路结构示意图；
图12为本公开一实施例提供的集成电路的再一种电路结构示意图；
图13为本公开一实施例提供的存储器的结构示意图；
图14为图13中区域A局部放大结构示意图。
具体实施方式
由背景技术可知，现有技术的DRAM性能仍有待提高。
本公开的发明人发现，现有技术中对同一DRAM而言，相邻的数据线相互之间存在噪声干扰。为了减小集成电路的面积，数据线之间通常没有屏蔽线阻隔噪声，导致数据线之间的噪声干扰比较大，使集成电路的功耗增加。也就是说，目前面临着存储器的数据线受噪声影 响较大，且功耗大的问题。
为解决上述问题，本公开实施提供一种集成电路，通过多个读取电路分别与第一数据线组边缘的本地数据线电连接或与第二数据线组边缘的互补本地数据线连接，使得集成电路使用的是受到噪声影响较小的数据线作为输出转换，从而降低了集成电路的功耗，进而改善了集成电路的性能。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施方式进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施方式中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施方式的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图1为本公开一实施例提供的集成电路100。
请参考图1，本实施例中，集成电路100包括：第一数据线组1，第一数据线组1包括阵列排布的多条本地数据线Ldat；第二数据线组2，第二数据线组2包括阵列排布的多条互补本地数据线Ldat#，其中，多条互补本地数据线Ldat#分别与多条本地数据线Ldat传输相位相反的信号；多个读取电路3，响应于读取控制信号，用于在读操作期间读取本地数据线Ldat或互补本地数据线Ldat#的信号，其中，多个读取电路3分别与第一数据线组1边缘的本地数据线Ldat电连接或与第二数据线组2边缘的互补本地数据线Ldat#连接。
具体的说，本实施例中，读取的数据或者写入的数据信号都是成对的，每对数据信号包括两个数据，在进行读写操作过程中，这两个数据中的一个数据为高电平信号，另一数据为低电平信号，因此，读写转换电路至少包括一对本地数据线Ldat以及互补本地数据线Ldat#。本地数据线Ldat为局部数据线(local data line，也称为本地数据线)，互补本地数据线Ldat#为互补局部数据线。
值得一提的是，本实施例中的读取电路3不与第一数据线组1或第二数据线组2中的非边缘位置的本地数据线Ldat或互补本地数据线Ldat#电连接，仅与第一数据线组1边缘位置的本地数据线Ldat或第二数据线组2中边缘位置的互补本地数据线Ldat#电连接。
本实施例相对现有技术而言，在集成电路100的工作过程中，相邻的数据线相互之间存在噪声干扰，甚至可能导致数据传输发生错误。由于数据线通常为阵列排布，因此在数据线组边缘的数据线只会受到一根相邻数据线的干扰。通过将多个读取电路3分别与第一数据线组1边缘的本地数据线Ldat电连接或与第二数据线组2边缘的互补本地数据线Ldat#连接，使得集成电路100使用的是受到噪声影响较小的数据线作为输出转换，从而提高了数据可靠性，同时也降低了集成电路100的功耗，进而改善了集成电路100的性能。
需要说明的是，图1所示的集成电路100中，第一数据线组1包括4条本地数据线Ldat， 第二数据线组2包括4条互补本地数据线Ldat#。在实际应用中，本实施例并不对第一数据线组中本地数据线Ldat的条数和第二数据线组2中互补本地数据线Ldat#的条数作具体限定，可以根据实际需求设置。
请继续参见图1，第一数据线组1包括依次排列的第一本地数据线Ldat1、第二本地数据线Ldat2、第三本地数据线Ldat3和第四本地数据线Ldat4，第二数据线组2包括依次排列的第二互补本地数据线Ldat#2、第一互补本地数据线Ldat#1、第四互补本地数据线Ldat#4和第三互补本地数据线Ldat#3，第一本地数据线Ldat1、第四本地数据线Ldat4、第二互补本地数据线Ldat#2和第三互补本地数据线Ldat#3分别与读取电路3电连接；其中第一本地数据线Ldat1与第一互补本地数据线Ldat#1、第二本地数据线Ldat2与第二互补本地数据线Ldat#2、第三本地数据线Ldat3与第三互补本地数据线Ldat#3以及第四本地数据线Ldat4与第四互补本地数据线Ldat#4分别传输相位相反的信号。
在一个可行的实施例中，多条本地数据线Ldat等间距排列，和/或多条互补本地数据线Ldat#等间距排列。
在另一个可行的实施例中，请参见图2，第一本地数据线Ldat1与第二本地数据线Ldat2之间的间距大于第二本地数据线Ldat2与第三本地数据线Ldat3之间的间距、第三本地数据线Ldat3与第四本地数据线Ldat4之间的间距大于第二本地数据线Ldat2与第三本地数据线Ldat3之间的间距。由于第一本地数据线Ldat1和第四本地数据线Ldat4位于第一数据线组1的边缘位置，也就是说，两个读取电路3分别与第一本地数据线Ldat1和第四本地数据线Ldat4连接，通过此种结构的设置，能够通过增大第一本地数据线Ldat1与第二本地数据线Ldat2之间的间距、以及增大第三本地数据线Ldat3与第四本地数据线Ldat4之间的间距的方式，减小第一本地数据线Ldat1与第二本地数据线Ldat2之间的电容以及第三本地数据线Ldat3与第四本地数据线Ldat4之间的电容，从而进一步减小第二本地数据线Ldat2对第一本地数据线Ldat1的噪声影响，以及减小第三本地数据线Ldat3对第四本地数据线Ldat4的噪声影响，进而进一步减小了噪声干扰。
需要说明的是，本实施例可以将第二本地数据线Ldat2和第三本地数据线Ldat3之间的间距设计为工艺上能够实现的最小间距，以使第一本地数据线Ldat1与第二本地数据线Ldat2之间的间距、第三本地数据线Ldat3与第四本地数据线Ldat4之间的间距最大，从而使第二本地数据线Ldat2对第一本地数据线Ldat1的噪声影响、以及第三本地数据线Ldat3对第四本地数据线Ldat4的噪声影响最小。
需要说明的是，图2所示的第一本地数据线Ldat1与第二本地数据线Ldat2之间的间距大于第二本地数据线Ldat2与第三本地数据线Ldat3之间的间距、第三本地数据线Ldat3与第 四本地数据线Ldat4之间的间距大于第二本地数据线Ldat2与第三本地数据线Ldat3之间的间距。在实际应用中，也可以是第一本地数据线Ldat1与第二本地数据线Ldat2之间的间距大于第二本地数据线Ldat2与第三本地数据线Ldat3之间的间距、第三本地数据线Ldat3与第四本地数据线Ldat4之间的间距等于第二本地数据线Ldat2与第三本地数据线Ldat3之间的间距；还可以是第一本地数据线Ldat1与第二本地数据线Ldat2之间的间距等于第二本地数据线Ldat2与第三本地数据线Ldat3之间的间距、第三本地数据线Ldat3与第四本地数据线Ldat4之间的间距大于第二本地数据线Ldat2与第三本地数据线Ldat3之间的间距，也就是说，本实施例并不对第一数据线组1中数据线的相对位置关系作具体限定。
在另一个可行的实施例中，请参见图3，第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间的间距大于第一互补本地数据线Ldat#1与第四互补本地数据线Ldat#4之间的间距、第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3之间的间距大于第一互补本地数据线Ldat#1与第四互补本地数据线Ldat#4之间的间距。由于第二互补本地数据线Ldat#2和第三互补本地数据线Ldat#3位于第二数据线组2的边缘位置，也就是说，两个读取电路3分别与第二互补本地数据线Ldat#2和第三互补本地数据线Ldat#3连接，通过此种结构的设置，能够通过增大第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间的间距、以及增大第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3之间的间距的方式，减小第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间的电容以及第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3之间的电容，从而进一步减小第一互补本地数据线Ldat#1对第二互补本地数据线Ldat#2的噪声影响，以及减小第四互补本地数据线Ldat#4对第三互补本地数据线Ldat#3的噪声影响，进而进一步减小了噪声干扰。
需要说明的是，本实施例可以将第一互补本地数据线Ldat#1和第四互补本地数据线Ldat#4之间的间距设计为工艺上能够实现的最小间距，以使第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间的间距、第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3之间的间距最大，从而使第一互补本地数据线Ldat#1对第二互补本地数据线Ldat#2的噪声影响、以及第四互补本地数据线Ldat#4对第三互补本地数据线Ldat#3的噪声影响最小。
需要说明的是，图3所示的第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间的间距大于第一互补本地数据线Ldat#1与第四互补本地数据线Ldat#4之间的间距、且第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3之间的间距大于第一互补本地数据线Ldat#1与第四互补本地数据线Ldat#4之间的间距。在实际应用中，也可以是第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间的间距大于第一互补本地数据线Ldat#1 与第四互补本地数据线Ldat#4之间的间距、第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3之间的间距等于第一互补本地数据线Ldat#1与第四互补本地数据线Ldat#4之间的间距；还可以是第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间的间距等于第一互补本地数据线Ldat#1与第四互补本地数据线Ldat#4之间的间距、且第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3之间的间距大于第一互补本地数据线Ldat#1与第四互补本地数据线Ldat#4之间的间距，也就是说，本实施例并不对第二数据线组2中数据线的相对位置关系作具体限定。
请参见图4，为了使集成电路100的噪声干扰更小，结合图2至图3中的数据线的设置位置，使第一本地数据线Ldat1与第二本地数据线Ldat2之间的间距大于第二本地数据线Ldat2与第三本地数据线Ldat3之间的间距、第三本地数据线Ldat3与第四本地数据线Ldat4之间的间距大于第二本地数据线Ldat2与第三本地数据线Ldat3之间的间距、第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间的间距大于第一互补本地数据线Ldat#1与第四互补本地数据线Ldat#4之间的间距、且第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3之间的间距大于第一互补本地数据线Ldat#1与第四互补本地数据线Ldat#4之间的间距，从而能够进一步降低集成电路100的噪声干扰，提高数据传输的可靠性。
请参见图5，集成电路100还包括屏蔽线4，第一本地数据线Ldat1与第二本地数据线Ldat2之间、以及第三本地数据线Ldat3到第四本地数据线Ldat4之间均设有屏蔽线4。由于第一本地数据线Ldat1和第四本地数据线Ldat4位于第一数据线组1的边缘位置，也就是说，两个读取电路3分别与第一本地数据线Ldat1和第四本地数据线Ldat4连接，通过此种方式，能够使屏蔽线4屏蔽第二本地数据线Ldat2对第一本地数据线Ldat1的噪声、以及屏蔽第三本地数据线Ldat3对第四本地数据线Ldat4的噪声，进而进一步提高了数据可靠性。
需要说明的是，图5所示的第一本地数据线Ldat1与第二本地数据线Ldat2之间、第三本地数据线Ldat3到第四本地数据线Ldat4之间均设有屏蔽线4，本实施还可以仅在第一本地数据线Ldat1与第二本地数据线Ldat2之间设置屏蔽线4，或仅在第三本地数据线Ldat3到第四本地数据线Ldat4之间设置屏蔽线4，并不对此作出具体限定。
请参见图6，集成电路100还包括屏蔽线4，第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间、第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3之间均设有屏蔽线4。由于第二互补本地数据线Ldat#2和第三互补本地数据线Ldat#3位于第二数据线组2的边缘位置，也就是说，两个读取电路3分别与第二互补本地数据线Ldat#2和第三互补本地数据线Ldat#3连接，通过此种方式，能够使屏蔽线4屏蔽第一互补本地数据线Ldat#1对第二互补本地数据线Ldat#2的噪声、以及屏蔽第四互补本地数据线Ldat#4对第三互补本 地数据线Ldat#3的噪声，从而进一步提高了数据可靠性。
需要说明的是，图6所示的第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间、第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3均设有屏蔽线4，本实施例还可以仅在第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间设置屏蔽线4，或仅在第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3之间设置屏蔽线4，并不对此作出具体限定。
请参见图7，为了使集成电路100的功耗更低，结合图5至图6中屏蔽线4的设置位置，在第一本地数据线Ldat1与第二本地数据线Ldat2之间、第三本地数据线Ldat3到第四本地数据线Ldat4之间、第二互补本地数据线Ldat#2与第一互补本地数据线Ldat#1之间、第四互补本地数据线Ldat#4与第三互补本地数据线Ldat#3均设有屏蔽线4，从而能够进一步提高了数据可靠性，同时也降低了集成电路100的功耗，进而使集成电路100的性能更优越。
请参见图8，集成电路100还包括多条全局数据线Gdat和多条互补全局数据线Gdat#，其中全局数据线Gdat和互补全局数据线Gdat#传输相位相反的信号，读取电路3响应于读取控制信号，用于在读操作期间将本地数据线Ldat或互补本地数据线Ldat#的信号传输至全局数据线Gdat或互补全局数据线Gdat#。
此外，集成电路100还包括多个放大单元102，分别连接在本地数据线Ldat和对应的互补本地数据线Ldat#之间，用于对本地数据线Ldat的信号和互补本地数据线Ldat#的信号放大。
具体的说，集成电路100包括读写转换单元101、放大单元102和列选择单元103，读取电路3属于读写转换单元101，读写转换单元101还包括写单元。写单元既与本地数据线Ldat连接，也与互补本地数据线Ldat#连接，写单元响应于写入控制信号，用于在写操作期间将全局数据线Gdat和/或互补全局数据线Gdat#的信号传输至本地数据线Ldat和/或互补本地数据线Ldat#。
更具体的，本地数据线Ldat经由列选择单元103与位线BL连接，互补本地数据线Ldat#经由列选择单元103与互补位线BL#电连接。读写转换单元101响应于读写控制信号，在读写操作期间，本地数据线Ldat与全局数据线Gdat之间传输数据，互补本地数据线Ldat#与互补全局数据线Gdat#之间传输数据。放大单元102连接在本地数据线Ldat与互补本地数据线Ldat#之间，用于对本地数据线Ldat的数据以及互补本地数据线Ldat#的数据放大。
读写控制信号包括读取控制信号Rd和写入控制信号Wr。在读写操作期间，响应于读取控制信号Rd，读写转换单元101将本地数据线Ldat以及互补本地数据线Ldat#的数据传输至全局数据线Gdat以及互补全局数据线Gdat#，或者，响应于写入控制信号Wr，读写转换单元101将全局数据线Gdat以及互补全局数据线Gdat#的数据传输至本地数据线Ldat以及互补本 地数据线Ldat#。
放大单元102构成了对本地数据线Ldat信号放大以及互补本地数据线Ldat#信号放大的电路，有助于加速区分本地数据线Ldat与互补本地数据线Ldat#，从而提高数据信号传输的速度，改善数据读写速度。此外，由于本地数据线Ldat和互补本地数据线Ldat#的数据信号得到放大，使得本地数据线Ldat和互补本地数据线Ldat#对于存储器中的第一级放大电路的驱动能力的需求降低，因而即使第一级放大电路的面积逐渐减小，该第一级放大电路对于本地数据线Ldat和互补本地数据线Ldat#而言仍具有足够的驱动能力，以便于在满足器件微型化发展趋势的同时，保证该读写转换电路具有良好的电学性能，进而提高包含该读写转换电路的存储器的存储性能。
请参见图9，读取电路3包括第一NMOS管MN1和第二NMOS管MN2。第一NMOS管MN1的源极接地，漏极电连接第二NMOS管MN2的源极，栅极接收读取控制信号Rd。第二NMOS管MN2的栅极电连接本地数据线Ldat或互补本地数据线Ldat#，漏极电连接互补全局数据线Gdat#或全局数据线Gdat。
请参见图10，读取电路3包括第一NMOS管MN1和第二NMOS管MN2。第一NMOS管MN1的源极接地，漏极电连接第二NMOS管MN2的源极，栅极电连接本地数据线Ldat或互补本地数据线Ldat#。第二NMOS管MN2的栅极接收读取控制信号Rd，漏极电连接互补全局数据线Gdat#或全局数据线Gdat。
请参见图11，写入单元包括第三NMOS管MN3、第四NMOS管MN4、第五NMOS管MN5。第三NMOS管MN3的源极接地，栅极接收写入控制信号Wr，漏极电连接第四NMOS管MN4的源极。第四NMOS管MN4的栅极电连接全局数据线Gdat，漏极电连接互补本地数据线Ldat#。第五NMOS管MN5的源极电连接全局数据线Gdat，栅极接收写入控制信号Wr，漏极电连接本地数据线Ldat。
请参见图12，写入单元包括第六NMOS管MN6、第七NMOS管MN7、第八NMOS管MN8。第六NMOS管MN6的源极接地，栅极接收写入控制信号Wr，漏极电连接第七NMOS管MN7的源极。第七NMO管MN7的栅极电连接互补全局数据线Gdat#，漏极电连接本地数据线Ldat。第八NMOS管MN8的源极电连接互补全局数据线Gdat#，栅极接收写入控制信号Wr，漏极电连接互补本地数据线Ldat#。
相应的，本公开实施例还提供一种存储器，包括上述任一实施例中的读写转换电路。图13为本公开一实施例提供的存储器的结构示意图，图14为图13中区域A的局部放大结构示意图。
参考图13及图14，存储器包括：若干个存储模块，每一存储模块包括存储器阵列301 以及灵敏放大器阵列302，灵敏放大器阵列302包括多个灵敏放大器312，存储器阵列301包括多个存储单元；列选择信号线CSL；字线WL；读写转换电路300，每一读写转换电路300与对应的灵敏放大器阵列302相连，且读写转换电路300包括本地数据线Ldat、互补本地数据线Ldat#、全局数据线Gdat以及互补全局数据线Gdat#；行译码电路303；列译码电路304；驱动电路305。
以下结合存储器的工作机理对存储器进行说明。
当一根字线WL经行译码电路303选中后，该字线WL对应的存储器阵列301中的数据传输至灵敏放大器312，数据经灵敏放大器312放大后，再回写至选中的字线WL连接的存储单元中。
数据需要写入时，列译码电路304选中相应的灵敏放大器312，数据由全局数据线Gdat以及互补全局数据线Gdat#经过读写转换电路300传输至本地数据线Ldat以及互补本地数据线Ldat#，再写入对应的灵敏放大器312以及相连接的存储单元。在写入期间，读写转换电路300不仅具有信号传输的作用，且还能够对本地数据线Ldat以及互补本地数据线Ldat#进行放大，有利于迅速将本地数据线Ldat以及互补本地数据线Ldat#的信号分开。如此，不仅有利于提高数据传输速度，且还降低了读写转换电路300对于灵敏放大器312驱动能力的要求，使得具有较小面积的灵敏放大器312即可满足驱动能力的要求，大大的降低了灵敏放大器312的工艺难度，且符合器件小型化微型化的发展趋势。
数据读出时，数据传输的方向与数据写入时的传输方向相反。列译码电路304选中相应的灵敏放大器312，数据传输至本地数据线Ldat以及互补本地数据线Ldat#，再经由读写转换电路300传输至全局数据线Gdat以及互补全局数据线Gdat#。同样的，在数据读出时，读写转换电路300可以极大的提升本地数据线Ldat以及互补本地数据线Ldat#的区分速度，数据经由灵敏放大器312、本地数据线Ldat和互补本地数据线Ldat#传输至全局数据线Gdat以及互补全局数据线Gdat#的速度得到提升。
可以理解的是，图13及图14中仅示意出一对全局数据线以及互补全局数据线，在实际使用时，存储器中可以具有多对全局数据线以及互补全局数据线；同样的，实际使用时存储器可以具有多对本地数据线以及互补本地数据线。
该存储器可以为DRAM，SRAM，MRAM，FeRAM，PCRAM，NAND，NOR等存储器。如前述分析可知，本实施例提供的存储器具有数据传输速度快的优势，对于感测放大器的驱动能力的需求低，有利于满足器件微型化的发展趋势。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。

Claims (16)

  1. 一种集成电路，包括：
    第一数据线组，所述第一数据线组包括阵列排布的多条本地数据线；
    第二数据线组，所述第二数据线组包括阵列排布的多条互补本地数据线，其中，多条所述互补本地数据线分别与多条所述本地数据线传输相位相反的信号；
    多个读取电路，响应于读取控制信号，用于在读操作期间读取所述本地数据线或所述互补本地数据线的信号，其中，多个所述读取电路分别与所述第一数据线组边缘的所述本地数据线电连接或与所述第二数据线组边缘的所述互补本地数据线连接。
  2. 根据权利要求1所述的集成电路，其中，所述第一数据线组包括4条所述本地数据线，所述第二数据线组包括4条所述互补本地数据线。
  3. 根据权利要求2所述的集成电路，其中，所述第一数据线组包括依次排列的第一本地数据线、第二本地数据线、第三本地数据线和第四本地数据线，所述第二数据线组包括依次排列的第二互补本地数据线、第一互补本地数据线、第四互补本地数据线和第三互补本地数据线，所述第一本地数据线、所述第四本地数据线、所述第二互补本地数据线和所述第三互补本地数据线分别与所述读取电路电连接；
    其中，所述第一本地数据线与所述第一互补本地数据线、所述第二本地数据线与所述第二互补本地数据线、所述第三本地数据线与所述第三互补本地数据线以及所述第四本地数据线与所述第四互补本地数据线分别传输相位相反的信号。
  4. 根据权利要求1所述的集成电路，其中，
    多条所述本地数据线等间距排列；
    和/或，
    多条所述互补本地数据线等间距排列。
  5. 根据权利要求3所述的集成电路，其中，
    所述第一本地数据线与所述第二本地数据线之间的间距，大于所述第二本地数据线与所述第三本地数据线之间的间距；
    和/或，
    所述第三本地数据线与所述第四本地数据线之间的间距，大于所述第二本地数据线与所述第三本地数据线之间的间距。
  6. 根据权利要求3所述的集成电路，其中，
    所述第二互补本地数据线与所述第一互补本地数据线之间的间距，大于所述第一互补本地数据线与所述第四互补本地数据线之间的间距；
    和/或，
    所述第四互补本地数据线与所述第三互补本地数据线之间的间距，大于所述第一互补本地数据线与所述第四互补本地数据线之间的间距。
  7. 根据权利要求3所述的集成电路，其中，所述集成电路还包括屏蔽线；
    所述第一本地数据线与所述第二本地数据线之间设置有所述屏蔽线；
    和/或，
    所述第三本地数据线到所述第四本地数据线之间设有所述屏蔽线。
  8. 根据权利要求3所述的集成电路，其中，所述集成电路还包括屏蔽线；
    所述第二互补本地数据线与所述第一互补本地数据线设有所述屏蔽线；
    和/或，
    所述第四互补本地数据线与所述第三互补本地数据线之间设有所述屏蔽线。
  9. 根据权利要求1所述的集成电路，其中，所述集成电路还包括多条全局数据线和多条互补全局数据线，其中，所述全局数据线和互补全局数据线传输相位相反的信号，所述读取电路响应于读取控制信号，用于在读操作期间将所述本地数据线或互补本地数据线的信号传输至全局数据线或互补全局数据线。
  10. 根据权利要求9所述的集成电路，其中，所述读取电路包括第一NMOS管和第二NMOS管。
  11. 根据权利要求10所述的集成电路，其中，
    所述第一NMOS管的源极接地，所述第一NMOS管的漏极电连接所述第二NMOS管的源极，所述第一NMOS管的栅极接收所述读取控制信号；
    所述第二NMOS管的栅极电连接所述本地数据线或所述互补本地数据线，所述第二NMOS管的漏极电连接所述互补全局数据线或所述全局数据线。
  12. 根据权利要求10所述的集成电路，其中，
    所述第一NMOS管的源极接地，所述第一NMOS管的漏极电连接所述第二NMOS管的源极，所述第一NMOS管的栅极电连接所述本地数据线或所述互补本地数据线；
    所述第二NMOS管的栅极接收所述读取控制信号，所述第二NMOS管的漏极电连接所述互补全局数据线或所述全局数据线。
  13. 根据权利要求1所述的集成电路，其中，所述集成电路还包括多个放大单元，分别连接在所述本地数据线和对应的所述互补本地数据线之间，用于对所述本地数据线的信号和所述互补本地数据线的信号放大。
  14. 根据权利要求9所述的集成电路，其中，所述集成电路还包括多个写入单元，响应 于写入控制信号，用于在写操作期间将所述全局数据线和/或所述互补全局数据线的信号传输至所述本地数据线和/或所述互补本地数据线。
  15. 根据权利要求14所述的集成电路，其中，所述写入单元包括第三NMOS管、第四NMOS管和第五NMOS管；
    所述第三NMOS管的源极接地，所述第三NMOS管的栅极接收所述写入控制信号，所述第三NMOS管的漏极电连接所述第四NMOS管的源极；
    所述第四NMOS管的栅极电连接所述全局数据线，所述第四NMOS管的漏极电连接所述互补本地数据线；
    所述第五NMOS管的源极电连接所述全局数据线，所述第五NMOS管的栅极接收所述写入控制信号，所述第五NMOS管的漏极电连接所述本地数据线。
  16. 根据权利要求14所述的集成电路，其中，所述写入单元包括第六NMOS管、第七NMOS管和第八NMOS管；
    所述第六NMOS管的源极接地，所述第六NMOS管的栅极接收所述写入控制信号，所述第六NMOS管的漏极电连接所述第七NMOS管的源极；
    所述第七NMO管的栅极电连接所述互补全局数据线，所述第七NMO管的漏极电连接所述本地数据线；
    所述第八NMOS管的源极电连接所述互补全局数据线，所述第八NMOS管的栅极接收所述写入控制信号，所述第八NMOS管的漏极电连接所述互补本地数据线。
PCT/CN2021/104221 2020-09-22 2021-07-02 集成电路 WO2022062556A1 (zh)

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