WO2021164032A1 - 读/写数据的方法、存储器、存储装置和终端 - Google Patents

读/写数据的方法、存储器、存储装置和终端 Download PDF

Info

Publication number
WO2021164032A1
WO2021164032A1 PCT/CN2020/076279 CN2020076279W WO2021164032A1 WO 2021164032 A1 WO2021164032 A1 WO 2021164032A1 CN 2020076279 W CN2020076279 W CN 2020076279W WO 2021164032 A1 WO2021164032 A1 WO 2021164032A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
bit line
target
storage
lines
Prior art date
Application number
PCT/CN2020/076279
Other languages
English (en)
French (fr)
Inventor
焦慧芳
赫然
范鲁明
潘越
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20919490.1A priority Critical patent/EP4092676A4/en
Priority to CN202080095326.0A priority patent/CN115039176A/zh
Priority to PCT/CN2020/076279 priority patent/WO2021164032A1/zh
Publication of WO2021164032A1 publication Critical patent/WO2021164032A1/zh
Priority to US17/893,067 priority patent/US20220406348A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals

Definitions

  • the present invention relates to the field of storage technology, and in particular to a method, memory, storage device and terminal for reading/writing data.
  • the relatively bloated unit memory array (usually 512 rows * 1024 columns of memory cells) is one of the main reasons for the high tRC delay.
  • tRC row cycle time
  • the embodiment of the present invention provides a method, memory, storage device and terminal for reading/writing data, which can solve the technical problem of high memory delay in current computer systems.
  • an embodiment of the present application provides a memory including S memory blocks, N global bit lines, and a signal amplifying circuit, each of the S memory blocks is connected to the N global bit lines, The N global bit lines are connected to the signal amplifying circuit, and the signal amplifying circuit is used to amplify the electrical signals in the N global bit lines, S and N are positive integers, and S ⁇ 2; each of the storages
  • the block includes N columns of memory cells, N local bit lines and N bit line switches, among which:
  • the i-th column of memory cells in the N columns of memory cells is connected to the i-th local bit line among the N local bit lines; the i-th local bit line passes through N
  • the i-th bit line switch in the bit line switches is connected to the i-th global bit line among the N global bit lines, where N is a positive integer, and i is a positive integer not greater than N.
  • the i-th local bit line in each memory block is connected to the same global bit line through a bit line switch, that is, the i-th global bit line.
  • the on and off of the bit line switch can control the on or off of the i-th local bit line and the i-th global bit line in each memory block, so that the i-th local bit line of the S memory blocks
  • a global bit line can be shared, and S memory blocks can share a signal amplifying circuit and a bit line driving circuit, so as to reduce the configuration of the signal amplifying circuit and the bit line driving circuit in the memory in the memory and reduce the manufacturing cost of the memory.
  • the fine-grained storage array can shorten the local bit line, reduce the parasitic capacitance caused by the local bit line, and reduce the delay of read and write operations.
  • the signal amplifying circuit includes N differential amplifiers, and the i-th differential signal amplifier of the N differential amplifiers is used to amplify the electrical signal on the i-th global bit line.
  • the above-mentioned memory can realize that the data in the memory cells located in different columns can be read at the same time, which improves the speed of the memory read operation.
  • the signal amplifying circuit includes P multiplexers and P differential amplifiers; the input end of the k-th multiplexer in the P multiplexers is connected At least two of the N global bit lines, the output of the k-th multiplexer in the P multiplexers is connected to the k-th one of the P differential amplifiers Differential amplifier, the k-th multiplexer of the P multiplexers is used to select an electrical signal transmitted by the global bit line from the electrical signals transmitted by the at least 2 global bit lines, and P is A positive integer not greater than N, and k is a positive integer not greater than P.
  • each memory block further includes N first control lines respectively connected to the control terminals of the N bit line switches, and the N first control lines are all connected to the first control circuit, The first control circuit is used to control the conduction of the N bit line switches.
  • the memory further includes a bit line drive circuit, and the bit line drive circuit is connected to the N global bit lines for inputting electrical signals to the N global bit lines.
  • the memory cells in each memory block are arranged into M rows*N columns of memory cells, each memory block further includes M word lines, and the M rows*N columns of memory cells
  • the memory cell in the j-th row in the middle is connected to the j-th word line of the M word lines, where M is a positive integer, and j is a positive integer not greater than M.
  • the memory further includes a word line drive circuit, the word line drive circuit is connected to the word lines in the S memory blocks, and the word line drive circuit is used to control the potential of the word line.
  • each storage block is divided into T storage sub-blocks, the storage sub-blocks in the memory are arranged into S rows and T-column storage sub-blocks, and each column of storage sub-blocks forms a storage domain ,
  • the memory includes T storage domains, the memory also includes W global word lines, T and W are positive integers, and T ⁇ 2; each of the T storage domains includes W rows of memory cells, W A local word line and W word line switches, of which:
  • the v-th row of memory cells in the W row of memory cells are connected to the v-th local word line among the W local word lines; the v-th local word line passes through W bits
  • the v-th word line switch in the line switch is connected to the v-th local word line in the W global word lines, W is a positive integer, and v is a positive integer not greater than W.
  • the above-mentioned memory through the fine-grained memory, not only shortens the local bit line, but also shortens the local word line, further reduces the operation delay of the memory, and improves the performance of the memory.
  • each storage domain further includes W second control lines respectively connected to the W word line switches, and the W second control lines are all connected to a second control circuit, and the second control circuit It is used to control the conduction of the W word line switches.
  • the memory further includes a word line drive circuit, the word line drive circuit is connected to the global word lines in the T storage domains, and the word line drive circuit is used to control the potential of the global word line.
  • an embodiment of the present application further provides a storage device, including: any one of the memory described in the first aspect and a storage controller, and the memory is coupled to the storage controller.
  • an embodiment of the present application also provides a terminal, including: a processor and any one of the memories described in the first aspect, the memory is coupled to the processor.
  • an embodiment of the present application also provides a method for reading data, which is applied to a memory.
  • the memory includes S memory blocks, N global bit lines, and a signal amplification circuit. Each of the S memory blocks The memory block is connected to the N global bit lines, and the N global bit lines are connected to the signal amplifying circuit.
  • the signal amplifying circuit is used to amplify the electrical signals in the N global bit lines, and S and N are positive.
  • each memory block includes N columns of memory cells, N local bit lines, and N bit line switches; wherein, in each memory block, the first column of the N columns of memory cells The i-th column of memory cells is connected to the i-th local bit line among the N local bit lines, and the i-th local bit line is connected to the N global bit lines through the i-th bit line switch among the N bit line switches.
  • N is a positive integer
  • i is a positive integer not greater than N; the method includes:
  • the electrical signal in the y-th global bit line is amplified by the signal amplifying circuit.
  • the signal amplifying circuit includes N differential amplifiers, the i-th differential signal amplifier of the N-differential amplifiers is connected to the i-th global bit line, and the signal amplifying circuit Amplifying the electrical signal in the y-th global bit line specifically includes:
  • the electrical signal in the yth global bit line is amplified by a target differential amplifier, where the target differential amplifier is a differential amplifier connected to the yth global bit line among the N differential amplifiers.
  • the signal amplifying circuit includes P multiplexers and P differential amplifiers; the input terminal of the k-th multiplexer in the P multiplexers At least two of the N global bit lines are connected, and the output terminal of the k-th multiplexer in the P multiplexers is connected to the k-th one of the P differential amplifiers.
  • a differential amplifier, and the k-th multiplexer of the P multiplexers is used to select an electrical signal transmitted by the global bit line from the electrical signals transmitted by the at least two global bit lines to output, P Is a positive integer not greater than N, and k is a positive integer not greater than P.
  • the amplifying the electrical signal in the y-th global bit line by the signal amplifying circuit specifically includes:
  • the electrical signal in the yth global bit line is amplified by the target differential amplifier.
  • each memory block further includes N first control lines respectively connected to the control terminals of the N bit line switches, and the yth bit in the target memory block is turned on.
  • Line switches include:
  • a control signal for turning on the y-th bit line switch is input to the first control line connected to the y-th bit line switch.
  • the memory cells in each memory block are arranged into M rows*N columns of memory cells, each memory block further includes M word lines, and the M rows*N columns of memory cells
  • the memory cell in the jth row in the middle is connected to the jth word line of the M word lines, M is a positive integer, j is a positive integer not greater than M, and the target memory cell is connected to the x1th word line in the target memory block.
  • Word line, x1 is a positive integer not greater than M, the
  • Strobe the target storage unit in the target storage block including:
  • a control signal for strobing the target memory cell is input to the x1th word line.
  • each storage block is divided into T storage sub-blocks, the storage sub-blocks in the memory are arranged into S rows and T-column storage sub-blocks, and each column of storage sub-blocks forms a storage domain
  • the memory includes T storage domains, the memory also includes W global word lines, T and W are positive integers, and T ⁇ 2; the storage domain includes W rows of memory cells, W local word lines, and W A word line switch; wherein the v-th row of memory cells in the W row of memory cells are connected to the v-th local word line of the W local word lines; the v-th local word line passes through the W bit line switches The v-th word line switch is connected to the v-th local word line of the W global word lines, W is a positive integer, v is a positive integer not greater than W, and the target storage unit is connected to the first in the target storage domain.
  • x2 local word lines, x2 is a positive integer not greater than W, and the target storage unit in the gated
  • a control signal for strobing the target memory cell is input to the x2th global word line among the W global word lines.
  • the storage domain further includes W second control lines respectively connected to the W word line switches, and the turning on the x2-th word line switch in the target storage domain includes:
  • a control signal for turning on the x2-th word line switch is input to a second control line connected to the x2-th word line switch.
  • an embodiment of the present application also provides a method for writing data, which is applied to a memory, and the memory includes S memory blocks, N global bit lines, and a signal amplification circuit.
  • the memory includes S memory blocks, N global bit lines, and a signal amplification circuit.
  • Each of the S memory blocks The memory block is connected to the N global bit lines, and the N global bit lines are connected to the signal amplifying circuit.
  • the signal amplifying circuit is used to amplify the electrical signals in the N global bit lines, and S and N are positive.
  • each memory block includes N columns of memory cells, N local bit lines, and N bit line switches; wherein, in each memory block, the first column of the N columns of memory cells The i-th column of memory cells is connected to the i-th local bit line among the N local bit lines, and the i-th local bit line is connected to the N global bit lines through the i-th bit line switch among the N bit line switches.
  • N is a positive integer
  • i is a positive integer not greater than N; the method includes:
  • the target storage unit is connected to the y-th local bit line in the target storage block, and y is a positive integer not greater than N;
  • the target electric signal is input to the y-th global bit line, so that the target electric signal is stored in the target storage unit.
  • each memory block further includes N first control lines respectively connected to the control terminals of the N bit line switches, and the yth bit in the target memory block is turned on.
  • Line switches include:
  • a control signal for turning on the y-th bit line switch is input to the first control line connected to the y-th bit line switch.
  • the memory cells in each memory block are arranged into M rows*N columns of memory cells, each memory block further includes M word lines, and the M rows*N columns of memory cells
  • the memory cell in the jth row in the middle is connected to the jth word line of the M word lines, M is a positive integer, j is a positive integer not greater than M, and the target memory cell is connected to the x1th word line in the target memory block.
  • Word lines, x1 is a positive integer not greater than M
  • the target memory cell in the gated target memory block includes:
  • a control signal for strobing the target memory cell is input to the x1th word line.
  • each storage block is divided into T storage sub-blocks, the storage sub-blocks in the memory are arranged into S rows and T-column storage sub-blocks, and each column of storage sub-blocks forms a storage domain
  • the memory includes T storage domains, the memory also includes W global word lines, T and W are positive integers, and T ⁇ 2; the storage domain includes W rows of memory cells, W local word lines, and W A word line switch; wherein the v-th row of memory cells in the W row of memory cells are connected to the v-th local word line of the W local word lines; the v-th local word line passes through the W bit line switches The v-th word line switch is connected to the v-th local word line of the W global word lines, W is a positive integer, v is a positive integer not greater than W, and the target storage unit is connected to the first in the target storage domain.
  • x2 word lines, x2 is a positive integer not greater than W, and the target storage unit in the strobe
  • a control signal for strobing the target memory cell is input to the x2th global word line among the W global word lines.
  • the storage domain further includes W second control lines respectively connected to the W word line switches, and the turning on the x2-th word line switch in the target storage domain includes:
  • a control signal for turning on the x2-th word line switch is input to the second control line connected to the x2-th word line switch.
  • an embodiment of the present application also provides a memory controller, which is applied to any type of memory as described in the first aspect, and includes any method for reading data as described in the fourth aspect.
  • an embodiment of the present application also provides a memory controller, which is applied to any type of memory as described in the first aspect, and includes any method for reading data as described in the fifth aspect.
  • an embodiment of the present application also provides a chip, including any one of the memories described in the first aspect.
  • FIG. 1 is a schematic circuit diagram of a memory provided by the prior art
  • FIG. 2 is a schematic circuit diagram of a memory provided by an embodiment of the present application.
  • FIG. 3 is a schematic circuit diagram of a storage unit provided by an embodiment of the present application.
  • FIG. 4 is a schematic circuit diagram of another memory provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the working principle of a storage unit provided by an embodiment of the present application.
  • FIG. 6 is a schematic circuit diagram of another memory provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the working principle of a storage unit provided by an embodiment of the present application.
  • FIG. 8 is a schematic circuit diagram of a signal method circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic circuit diagram of another signal method circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a storage device provided by an embodiment of the present application.
  • FIG. 11A is a schematic structural diagram of a computing device provided by an embodiment of the present application.
  • FIG. 11B is a schematic structural diagram of another computing device provided by an embodiment of the present application.
  • FIG. 12 is a schematic flowchart of a method for reading data provided by an embodiment of the present application.
  • FIG. 13 is a schematic flowchart of a method for writing data provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a storage controller provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of another storage controller provided by an embodiment of the present application.
  • the memory shown in the embodiments of the present application may be random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), Synchronous dynamic random access memory (SDRAM), double-rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), high bandwidth memory (HBM), read only memory, ROM), it can also be cache, flash memory, hard disk drive (HDD), solid state disk (solid state disk or solid state drive, SSD), etc.
  • RAM random access memory
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • SDRAM Synchronous dynamic random access memory
  • SDRAM double-rate synchronous dynamic random access memory
  • HDD hard disk drive
  • solid state disk solid state disk or solid state drive, SSD
  • FIG. 1 is a schematic structural diagram of a memory provided by an embodiment of the application.
  • the original memory array is divided into multiple small memory arrays in the memory, and logic circuits, such as bits, are configured for each small memory array.
  • bit line sense amplifier (BLSA) or differential amplifier (sense amplifier, SA) fine-grained the memory array, the bit line becomes shorter, thereby reducing the parasitic capacitance caused by the bit line and reducing the delay of the memory.
  • each unit storage array is reduced through fine-grained, more area is required to configure logic circuits, which leads to a reduction in storage capacity under the same chip area and a substantial increase in the cost per unit (bit).
  • the present application provides a memory that reduces the length of the bit line in the unit memory array by making the memory array in the memory fine-grained, reducing parasitic capacitance, and at the same time , Connect the bit lines (also called local bit lines) in each unit memory array to the global bit lines through switches, so that the bit lines in each unit memory array can share the global bit line, signal amplifier circuit, bit line drive circuit, etc. , To reduce the driving time of the circuit while reducing the cost of the memory.
  • a unit storage array is a storage array composed of storage cells. Each row of storage cells in the storage array is connected to a word line, and each column of storage cells is connected to a bit line.
  • the storage block or storage domain may be a unit storage array, or a plurality of unit storage arrays arranged along the bit line or word line direction.
  • LBL Local bitline
  • GBL global bitline
  • the location of the bit line it is divided into a local bit line and a global bit line.
  • the bit line located only in the unit storage array or the bit line connected only with the memory cell in the unit storage array is called the local bit line;
  • the storage unit located in the multiple unit storage array or connected to the multiple unit storage array The connected bit lines are called global bit lines.
  • the global bit line is not directly connected to the memory cell, but is connected to the local bit line through a switch, which is referred to as a bit line switch in this application. That is, the bit line switch is a switch for connecting the local bit line and the global word line.
  • LWL Local wordline
  • GWL global wordline
  • the word line According to the location of the word line, it is divided into local word lines and global word lines. Among them, word lines located only in a unit storage array or word lines connected only to memory cells in the unit storage array are called local word lines; memory cells located in multiple unit storage arrays or connected to multiple unit storage arrays The connected word line is called the global word line.
  • the global word line is not directly connected to the memory cell, but is connected to the local word line through a switch.
  • This switch is referred to as a word line switch in this application. That is, the word line switch is a switch for connecting the local word line and the global word line.
  • the memory may include S memory blocks, N global bit lines, signal amplification circuits, bit line drive circuits, word line drive circuits, and the like. Among them: each of the S memory blocks is connected to N global bit lines; N global bit lines are connected to the signal amplifying circuit and the bit line driving circuit; the signal amplifying circuit is used to amplify the electrical signals in the N global bit lines, S , N is a positive integer, S ⁇ 2.
  • the bit line drive circuit is used to select the global bit line corresponding to the memory cell to input an electrical signal to the global bit line when writing to the memory cell in the memory;
  • the word line drive circuit is used to store the memory in the memory When the unit is operated (read operation or write operation), the word line corresponding to the storage unit inputs an electrical signal.
  • FIG. 2 shows a bit line drive circuit, a word line drive circuit, etc.
  • the signal amplifier circuit, bit line drive circuit, and word line drive circuit are not necessary circuits for the memory of this application.
  • the memory may further include a bit line driving circuit, and the bit line driving circuit is connected to the above N global bit lines for inputting electrical signals in the N global bit lines. It should be understood that the bit line drive circuit plays a role when the memory is performing a write operation.
  • the bit line drive circuit when data needs to be written to a certain memory cell, the bit line drive circuit is used to input the electrical signal corresponding to the written data into the global bit line electrically connected to the memory cell, where the memory cell has " There are two states of 0" and "1". For example, when the memory cell needs to be set to the "1" state, the bit line drive circuit inputs a high potential to the global bit line connected to it. On the contrary, when the memory cell needs to be set to "0" In the state, the bit line drive circuit inputs a low potential to the global bit line to which it is connected.
  • each memory block For each of the S memory blocks, each memory block includes N columns of memory cells, N local bit lines, and N bit line switches.
  • the i-th column of memory cells in the N column is connected to the i-th local bit line of the N local bit lines; the i-th local bit line passes through the i-th one of the N bit line switches
  • the bit line switch is connected to the i-th global bit line among the N global bit lines, where N is a positive integer, and i is a positive integer not greater than N.
  • the value of i can be 1, 2, ..., N.
  • the S storage blocks are represented as storage block (1), storage block (2), ..., storage block (S).
  • the N global bit lines are represented as GBL(1), GBL(2),..., GBL(N), where GBL(i) is represented as the i-th global bit line among the N global bit lines.
  • N local bit lines are represented as LBL(1), LBL(2),..., LBL(N)
  • N bit line switches are represented as bit line switch 1, bit line switch 2, .... Bit line switch N, where LBL(i) represents the i-th local bit line in a memory block, and bit line switch i represents the i-th bit line switch in a memory block.
  • the N local bit lines and the N bit line switches in each memory block adopt the same representation, the LBL(i) in any two different memory blocks in the S memory blocks are actually two different ones. In the same way, the bit line switches i in any two different memory blocks are actually two different bit line switches.
  • each memory block is a memory cell array including N columns of memory cells. S memory blocks are arranged along the bit line direction to form a memory block array.
  • the memory block array also includes N columns of memory. Unit, at this time, the storage unit located in the i-th column in each storage block is still in the i-th column in the storage block array composed of S storage blocks.
  • each memory cell in the i-th column of memory cells is connected to the i-th local bit line, and the i-th local bit line is connected to the i-th global bit line through the i-th bit line switch.
  • the i-th local bit line in each memory block is connected to the same global bit line through a bit line switch, that is, the i-th global bit line.
  • the on and off of the line switch can control the on or off of the i-th local bit line and the i-th global bit line in each memory block, so that the i-th local bit line of the S memory blocks can be Sharing a global bit line
  • S memory blocks can share a signal amplifying circuit and a bit line driving circuit, so as to reduce the configuration of the signal amplifying circuit and the bit line driving circuit in the memory in the memory and reduce the manufacturing cost of the memory.
  • the fine-grained storage array can shorten the local bit line, reduce the parasitic capacitance caused by the local bit line, and reduce the delay of read and write operations.
  • the memory cell may be a 1T1C (1 Transistor-1 Capacitor) memory cell, which is composed of one transistor and one capacitor.
  • FIG. 3 is a schematic circuit diagram of a memory cell provided by an embodiment of the application.
  • the transistor T c and the capacitor C in the dashed frame in FIG. 3 form a storage unit, and the storage unit controls the capacitor C to charge/discharge through a transistor T c.
  • the gate of the transistor T c is connected to the word line, and the source and drain of the transistor are respectively connected to the local bit line and the capacitor C.
  • the transistor T c is an example of a field effect transistor.
  • the transistor T c may also be other types of transistors, such as a triode, etc., which is not limited here.
  • the storage unit may also be a storage unit with other structures.
  • the memory is an SRAM, and the storage unit includes a transistor and a latch, which is not limited here.
  • the bit line switch may include a switch having an on and off function formed by at least one transistor.
  • the bit line switch is a transistor.
  • the transistor in the memory cell or the transistor in the bit line switch may include a triode, a field effect transistor, etc.
  • FIG. 4 is a schematic circuit diagram of another memory provided by an embodiment of the application, and FIG. 4 uses a bit line switch It is a transistor T b and the memory cell can be 1T1C as an example.
  • each memory block may further include N first control lines respectively connected to the control terminals of the N bit line switches, and the N first control lines are all connected to the first control lines.
  • a control circuit (not shown in FIG. 2 or FIG. 4), the first control circuit is used to control the on and off of each bit line switch in the S memory blocks.
  • N first control lines are represented as SC1(1), SC1(2),..., SC1(N), where SC1(i) represents the i-th first control line in a memory block Control line. It should be understood that although the N first control lines in each memory block adopt the same representation, the SC1(i) in any two different memory blocks in the S memory blocks are actually two different first control lines. .
  • the memory cell when it is necessary to perform a read/write operation on a memory cell in a memory block, the memory cell needs to be turned on through the bit line switch connected to the local bit line.
  • the first control circuit can be connected to the A high potential is applied to the first control line of the bit line switch to make the bit line switch in the on state.
  • the memory cells that do not need to perform the read/write operation pass the local bit
  • the bit line switch connected to the line is turned off.
  • the first control circuit may apply a low potential to the first control line connected to the bit line switch, so that the bit line switch is in an off state. It should be understood that the above example is described by taking the bit line switch as an N-type MOS transistor.
  • a storage block may include multiple storage units arranged in an array, and each storage block includes N columns of storage units, but the number of rows of storage units in each storage block may be the same or different.
  • the memory cells in each memory block are arranged into M rows*N columns of memory cells.
  • the memory block also includes M word lines, and the j-th row of memory cells in the M rows*N columns of memory cells are connected to the j-th word line of the M word lines, and M is a positive integer.
  • j is a positive integer not greater than M.
  • FIG. 5 it is a schematic diagram of the working principle of a storage unit provided by an embodiment of this application.
  • the word line WL connecting the memory cell and the local bit line LBL need to be strobed.
  • the local bit line LBL strobe needs to be strobed to connect the local bit line LBL.
  • the global bit line GBL and SC1 connected to the local bit line LBL.
  • the transistor T b and the transistor T c are both N-type MOS transistors as an example to illustrate, the strobe WL refers to inputting a high potential in the WL to turn on the transistor T c , and the capacitor C can be charged/discharged; LBL gating means, the high potential in the LBL SCI connected to the transistor T b is turned on, the conduction GBL is connected to the LBL LBL, and selection of the input or output electrical signals GBL, respectively for read or Write operation.
  • the memory shown in FIG. 2 or FIG. 4 is described by taking the example that the total number of rows of storage units in each storage block is the same, that is, the total number of rows is M.
  • the total number of rows of storage units in different storage blocks may be different.
  • storage block 1 is an array of M1 rows*N columns of storage cells
  • storage block 2 is M2 rows*N columns of storage.
  • M1 is not equal to M2, so we will not give an example here, where M1 and M2 are both positive integers.
  • the memory further includes a word line drive circuit, which is connected to all word lines in the S memory blocks.
  • the word line drive circuit is used to control the potential of the word line connected to it, and further, control the The turn-on and turn-off of the transistors on each word line.
  • the transistor in the memory cell of the word line drive circuit is an N-type MOS transistor.
  • each of the S memory blocks is divided into T memory sub-blocks.
  • the storage sub-blocks in the memory are arranged into S rows and T columns of storage sub-blocks, and each column of storage sub-blocks forms a storage domain.
  • the memory may include T storage domains, and the memory may also include W global word lines.
  • T and W are positive Integer, T ⁇ 2; each of the T storage domains includes W rows of memory cells, W local word lines, and W word line switches, where:
  • the v-th row of memory cells in the W row of memory cells are connected to the v-th local word line of the W local word lines; the v-th local word line passes through the v-th word in the W bit line switches
  • the line switch is connected to the v-th local word line among the W global word lines, where W is a positive integer, and v is a positive integer not greater than W.
  • FIG. 7 it is a schematic diagram of the working principle of another storage unit provided in an embodiment of this application.
  • the word line LWL and the local bit line LBL connecting the memory cell need to be strobed.
  • the local bit line LBL strobe needs to be strobed to connect the local bit line LBL.
  • the global bit line GBL and SC1 connected to the local bit line LBL.
  • the gating of the local word line LWL requires the gating of the global word line GWL connected to the local word line LWL and SC2 connected to the local word line LWL.
  • the transistor T b, the transistor T c, T r transistors are N-type MOS transistor will be described as an example
  • the gate means LWL
  • the high potential in the SC2 LWL connected to the transistor T r is turned on
  • the The GWL connected to the LWL and the LWL is turned on
  • a high potential is input to the GWL, so that the transistor T c is turned on, and the capacitor C can be charged/discharged
  • strobing the LBL refers to inputting a high potential in the SCI connected to the LBL to the transistor T b is turned on, the conduction GBL is connected to the LBL LBL, and selection of the input or output electrical signals GBL to read or write operation, respectively.
  • the number of columns of storage units in each storage domain may be the same or different, which is not limited here.
  • the storage domain (1) includes n1 columns of memory cells, and the memory (T) includes N-n2 columns of memory cells, where n1 is a positive integer greater than 1, and n2 is a positive integer less than N.
  • N is a multiple of T, and each storage domain includes storage units with the same number of columns, that is, N/T columns.
  • the total number of rows of storage units in each storage block may be the same or different, which is not limited here.
  • the memory block (1) is an array of v1 rows*N columns of memory cells
  • the memory block (S) is an array of v2 rows*N columns of memory cells, and v1 is greater than 1.
  • V2 is a positive integer less than W.
  • the memory includes W rows*N columns of storage cells as an example for illustration, and W is a positive integer greater than 1.
  • T storage domains are represented as storage domain 1, storage domain 2, ..., storage domain T.
  • the W global word lines are represented as GWL(1), GWL(2), ..., GWL(W), where GWL(v) is represented as the v-th global word line among the W global word bit lines.
  • W local word lines are represented as LWL(1), LWL(2), ..., LWL(W)
  • W word line switches are represented as word line switch 1, word line switch 2, ... Word line switch W, where LWL(v) represents the v-th local word line in a storage domain, and word line switch v represents the v-th word line switch in a storage domain.
  • each memory block is a memory cell array including N columns of memory cells, and S memory blocks are arranged along the bit line direction to form a memory block array.
  • the memory block array also includes N columns of memory cells.
  • each storage block is divided into T storage sub-blocks, each storage sub-block is a matrix of storage units smaller than the storage block, and the storage unit in the t-th storage sub-block in each storage block The number of columns is the same. All storage sub-blocks in the memory are arranged into storage sub-blocks of S rows*T columns.
  • the area formed by a column of storage sub-blocks is called a storage domain, and the memory includes T storage domains.
  • each memory cell in the v-th row of memory cells is connected to the v-th local word line, and the v-th local word line is connected to the v-th global word line through the v-th word line switch.
  • the v-th local word line in each storage domain is connected to the same global word line through a word line switch, that is, the v-th global word line.
  • the on and off of the line switch can control the on or off of the v-th local word line and the v-th global word line in each storage domain, so that the v-th local word line of the T storage domains can be Sharing a global word line, T storage domains can share a word line driving circuit, so as to reduce the configuration of the word line driving circuit in the memory in the memory and reduce the manufacturing cost of the memory.
  • the fine-grained memory array can shorten the local word line, reduce the parasitic capacitance caused by the local word line, and the delay of read and write operations is also small.
  • each storage domain may further include W second control lines respectively connected to W word line switches, and the W second control lines are all connected to the second control circuit (FIG. (Not shown in 6), the second control circuit is used to control the on and off of each word line switch in the T storage domains.
  • W second control lines are represented as SC2(1), SC2(2), ..., SC2(W), where SC2(v) represents the v-th second control line in a storage domain Control line. It should be understood that although the W second control lines in each storage domain adopt the same representation, the SC2(v) in any two different storage domains in the T storage domains are actually two different second control lines. .
  • the memory further includes a word line drive circuit connected to the global word lines in the T storage domains, and the word line drive circuit is used to control all the global word lines in the T storage domains.
  • the potential It should be understood that the word line drive circuit controls the potential of the T local word lines connected to the global word line by controlling the potential of the global word line, and further, by turning on one of the T word line switches connected to the global word line or A plurality of word line switches select memory cells on the local word line connected to the one or more word line switches.
  • the memory cell needs to be turned on through the word line switch connected to the local word line.
  • the second control circuit can be connected to the word line switch.
  • a high potential is applied to the second control line to make the word line switch in an on state, and a high potential is applied to the global word line connected to the memory cell through the word line drive circuit.
  • the word line switch is connected to the memory cell.
  • the global word line and the local word line connected to the memory cell are turned on, and a high potential is applied to the control terminal of the transistor of the memory cell to gate the memory cell.
  • the memory cells that do not need to perform read/write operations are disconnected by the word line switch connected to the local word line.
  • the second control circuit can connect to the word line switch. A low potential is applied to the second control line to make the word line switch in an off state. It should be understood that the above description takes the word line switch as an N-type MOS transistor as an example.
  • the signal amplifying circuit works when the memory cell in the memory is read.
  • FIG. 8 and FIG. 9 the schematic diagrams of the two types of differential amplifier circuits provided by the embodiments of the present application.
  • the signal amplifying circuit may include N differential amplifiers, the N differential amplifiers correspond to N global bit lines one-to-one, and the i-th differential signal of the N differential amplifiers The amplifier is used to amplify the electrical signal on the i-th global bit line.
  • one input terminal of the i-th differential signal is connected to the i-th global bit line, and the electrical signal on the i-th global bit line is input.
  • the other input terminal is connected to the reference signal, and the output of the i-th differential signal amplifier is from The signal after the reference signal is removed from the electrical signal on the i-th global bit line, and further, the data corresponding to the output signal is identified.
  • the above-mentioned memory combined with the differential amplifier circuit shown in FIG. 8 can realize that the data in the memory cells located in different columns can be read at the same time, which improves the speed of the memory read operation.
  • the signal amplifying circuit may include P multiplexers and P differential amplifiers.
  • the multiplexer and the differential amplifier correspond one-to-one; the input end of the k-th multiplexer in the P multiplexers is connected to at least two of the above-mentioned N global bit lines ; The output end of the k-th multiplexer in the P multiplexers is connected to the k-th differential amplifier in the P differential amplifiers; the k-th multiplexer in the P multiplexers
  • the path gate is used to select an electrical signal transmitted by the global bit line from the electrical signal transmitted by the global bit line connected to the k-th multiplexer.
  • P is a positive integer not greater than N, and k is not greater than P. Positive integer.
  • the foregoing memory may also include a decoder, and other functional units for realizing reading and writing data of the memory, which is not limited herein.
  • FIG. 10 shows a storage device provided by an embodiment of the application.
  • the storage device 100 may include a memory 101 and a storage controller 102.
  • the storage controller 102 is coupled to the memory 101. Any of the memory types described in 6.
  • the storage device 100 may be a memory
  • the storage controller is a memory controller for receiving a request for a target storage unit sent by a processor, and further, responding to the request through the target storage unit in the storage device .
  • the request includes a read request and a write request.
  • the storage device may be other memory, such as a cache memory (cache), DRAM, etc., which is not limited here.
  • cache cache memory
  • DRAM dynamic random access memory
  • FIG. 11A shows a computing device provided by an embodiment of the application.
  • the computing device 110A may include a processor 111 and a memory 112, where the processor 111 and the memory 112 are coupled, for example, connected through a bus 113; the memory 112 may It is any one of the memory described in FIG. 2, FIG. 4, or FIG. 6 above.
  • FIG. 11B shows another computing device provided by an embodiment of the application.
  • the computing device 110B may include a processor 114, a storage controller 115, and a memory 116, where the processor 111 and the storage controller 115 are coupled, and the storage controller
  • the device 115 is coupled with the memory 116, and the memory 116 may be any one of the memories described in FIG. 2, FIG. 4, or FIG. 6 above.
  • Computing devices can be terminals, such as mobile phones, tablets, laptops, personal computers, smart TVs, set-top boxes, smart watches, smart bracelets, virtual reality (VR) devices, augmented reality (AR) devices, Smart speakers, etc.
  • computing devices can also be routers, servers, cloud servers, cloud computing devices, and other devices that include storage and have data processing functions.
  • the storage device described in 10 above, and the computing device described in FIG. 11A and FIG. The method is executed by a storage controller or a storage device or a computing device including the storage controller.
  • the method may include but is not limited to the following steps:
  • S12 Strobe the target storage unit in the target storage block, the target storage unit is connected to the y-th local bit line in the target storage block, and y is a positive integer not greater than N.
  • the strobe target memory cell guides the transistor in the target memory cell, such as the transistor T c in the memory cell in FIG.
  • the electrical signal can be transmitted to the local bit line, or the electrical signal in the local bit line can be transmitted to the target memory cell.
  • the storage controller receives a read request from the processor, and the read request is used to request to read data in the target storage unit in the target storage block, where the read request carries instructions for indicating The address information of the location of the target storage unit, after receiving the read request, the storage controller can determine the row address and column address of the target storage unit in the memory according to the address information.
  • the column address is used to indicate the identifier of the column where the target storage unit is located
  • the row address is used to indicate the identifier of the row where the target storage unit is located.
  • a local bit line and a word line in a memory block can determine the location of a memory cell, and the column address where the target memory cell is located may include the identification of the local bit line connected to the target memory cell. The same applies to the location of the target memory cell.
  • the row address of may include the identification of the word line or the local word line to which the target memory cell is connected.
  • the target memory cell is connected to the x1 word line and the y local bit line in the target memory block, x1 ⁇ W, y ⁇ N, and W is the storage The total number of rows of storage units in the block, and N is the total number of columns of storage addresses in the storage block.
  • the target memory cell is connected to the x2th local word line in the target memory domain, and the target memory cell is connected to the yth local bit line in the target memory block, x2 ⁇ W , Y ⁇ N, W is the total number of rows of storage units in the storage block, and N is the total number of columns of storage addresses in the storage block.
  • the memory controller may obtain the row address and column address of the target memory cell determined by the address information through a decoder, and further determine the local bit line, word line, or local word line to which the target memory cell is connected.
  • Two implementation methods of strobe target memory are described below for the memory shown in Fig. 2 and Fig. 6 and the memory shown in Fig. 6 respectively:
  • the first method of implementation is a first method of implementation:
  • the memory controller may input a control signal for gating the target memory cell to the x1 word line in the target memory block through the word line drive circuit.
  • the transistor in the memory cell is an N-type MOS tube.
  • the word line drive circuit applies a high potential on the x1 word line connected to the target memory cell.
  • the target memory block The memory cells in the x1th row in are all strobed, and the target memory cell is also strobed.
  • the memory controller can turn on the x2th word line switch in the target storage area to turn on the x2th local word line and the W global word line in the target storage area.
  • the x2th global word line of the W global word lines is furthermore inputted to the x2th global word line of the W global word lines through the word line drive circuit for a control signal for strobing the target memory cell.
  • an implementation manner of the memory controller turning on the x2 word line switch in the target storage domain may be: the memory controller inputs the SC2(x2) to the second control line connected to the x2 word line switch for A control signal that turns on the x2 word line switch. If the word line switch is an N-type MOS transistor, the control signal can be high.
  • the memory controller may also first input a control signal to the x2-th global word line among the W global word lines, and then turn on the x2-th word line switch.
  • the control signal can be a high potential.
  • the word line drive circuit applies a high potential on the x2 global word line, since the x2 word line switch in the target storage domain is turned on, at this time, the high potential on the x2 global word line passes through the target storage domain
  • the x2th local word line in is applied to all the memory cells in the x2th row in the target storage domain, all the memory cells in the x2th row in the target storage domain are strobed, and the target memory cell is also strobed.
  • the y-th bit line switch in the target memory block is turned on, the y-th local bit line in the target memory is transferred to the N global bit lines and the y-th global bit line is turned on.
  • an implementation manner for the memory controller to turn on the yth bit line switch in the target memory block may be: the memory controller sends the first control line SC1 (y ) Input a control signal for turning on the y-th bit line switch. If the bit line switch is an N-type MOS transistor, the control signal can be high.
  • S16 Amplify the electrical signal in the y-th global bit line by a signal amplifying circuit.
  • one implementation of S16 may be: the memory controller amplifies the electrical signal in the yth global bit line through the target differential amplifier, where, The target differential amplifier is a differential amplifier connected to the y-th global bit line among the N differential amplifiers.
  • an implementation of S16 can be: the memory controller connects the target of the yth global bit line The multiplexer inputs the electrical signal in the y-th global bit line to the target differential amplifier connected to the target multiplexer; the target multiplexer is the same as the y-th one among the P multiplexers The multiplexer connected to the global bit line is used to transmit only the electrical signal in the y-th global bit line to the differential amplifier connected to the target multiplexer (referred to here as the target differential amplifier), and further, through The target differential amplifier amplifies the electrical signal in the y-th global bit line.
  • the storage controller can read the data corresponding to the electrical signal, and send the read data to the processor.
  • the purpose of amplifying the electrical signal in the y-th global bit line is to remove the reference signal in the electrical signal, so that the amplified signal is closer to the signal stored in the target memory cell in the target memory block, so as to accurately identify the signal.
  • the data in the target storage unit is to remove the reference signal in the electrical signal, so that the amplified signal is closer to the signal stored in the target memory cell in the target memory block, so as to accurately identify the signal.
  • the storage device described in 10 and the computing device described in FIG. 11A and FIG. The method is executed by a storage controller or a storage device or a computing device including the storage controller.
  • the method may include but is not limited to the following steps:
  • S22 Strobe the target storage unit in the target storage block, the target storage unit is connected to the y-th local bit line in the target storage block, and y is a positive integer not greater than N.
  • the storage controller receives a write request from the processor, the write request is used to request to write target data in the target storage unit in the target storage block, where the write request carries Based on the address information indicating the location of the target memory block, after receiving the write request, the memory controller can determine the row address and column address of the target memory cell in the memory according to the address information.
  • the column address is used to indicate the identifier of the column where the target storage unit is located
  • the row address is used to indicate the identifier of the row where the target storage unit is located.
  • the method for determining the row address and column address of the target storage unit in the target storage block based on the address information carried in the write request and the read request is the same, which can be specifically described in the data reading method embodiment shown in FIG. 12, I won't repeat it here.
  • one local bit line and one word line in a memory block may determine the location of a memory cell, and the column address where the target memory cell is located may include the identification of the local bit line connected to the target memory cell. Similarly, the row address where the target memory cell is located may include the identification of the word line or the local word line to which the target memory cell is connected.
  • the target memory cell is connected to the x1-th word line and the y-th local bit line in the target memory block, x1 ⁇ W, y ⁇ N, and W is the storage The total number of rows of storage units in the block, and N is the total number of columns of storage addresses in the storage block.
  • the target memory cell is connected to the x2th local word line in the target memory domain, and the target memory cell is connected to the yth local bit line in the target memory block, x2 ⁇ W , Y ⁇ N, W is the total number of rows of storage units in the storage block, and N is the total number of columns of storage addresses in the storage block.
  • the positive integer actually referred to by y the positive integer actually referred to by x1, the positive integer actually referred to by x2, and the positive integer actually referred to by the target storage block
  • the storage block, the storage unit actually referred to by the target storage unit, and the storage domain actually referred to by the target storage domain may all be different.
  • the specific implementation of the strobe target storage unit may refer to the specific implementation of the strobe target storage unit in the embodiment of the method for reading data shown in FIG. 12, which will not be repeated here.
  • step S24 reference may be made to the related description in step S14 in the method embodiment shown in FIG. 12, which will not be repeated here.
  • S26 Input the electrical signal corresponding to the target data to the y-th global bit line, so that the electrical signal is stored in the target storage unit.
  • the data "1" corresponds to a high potential
  • the data "1” corresponds to a low potential
  • the electrical signal corresponding to the target data can be input to the yth global bit line through the bit line drive circuit. Since the yth bit line switch of the target memory block is turned on, the electrical signal The signal may be transmitted to the target memory cell through the y-th local bit line of the target memory block, and the electrical signal may be stored in a capacitor in the target memory cell.
  • FIG. 14 shows a storage controller provided by an embodiment of this application; the storage controller can be applied to the memory shown in FIG. 2, FIG. 4, or FIG. 6, the storage device described in 10 above, and FIG. 11A.
  • the storage controller 1400 may include the following functional units:
  • the strobe module 1401 is configured to strobe a target storage unit in a target storage block, wherein the target storage unit is connected to the yth local bit line in the target storage block, and y is a positive integer not greater than N;
  • the turn-on module 1402 is used to turn on the y-th bit line switch in the target memory block, so that the electrical signal in the target memory cell is transmitted to the N global bit lines through the y-th local bit line.
  • the amplifying module 1403 is configured to amplify the electrical signal in the y-th global bit line through the signal amplifying circuit.
  • the amplifying module 1403 is specifically configured to: amplify the electrical signal in the yth global bit line through a target differential amplifier, where ,
  • the target differential amplifier is a differential amplifier connected to the y-th global bit line among the N differential amplifiers.
  • the amplifying module 1403 is specifically configured to: The target multiplexer of the y-th global bit line inputs the electrical signal in the y-th global bit line to a target differential amplifier connected to the target multiplexer; The amplifier amplifies the electrical signal in the y-th global bit line.
  • each memory block further includes N first control lines respectively connected to the control terminals of the N bit line switches, and the conduction module 1402 is specifically configured to: The first control line of the y-th bit line switch inputs a control signal for turning on the y-th bit line switch.
  • the target storage unit is connected to the x1-th word line in the target storage block, and x1 is a positive integer not greater than M, so
  • the strobe module 1401 is specifically configured to: input a control signal for strobing the target memory cell into the x1-th word line.
  • the target storage unit is connected to the x2th local word line in the target storage domain, and x2 is a positive integer not greater than W, and the strobe module 1401 is specifically configured to: turn on the x2-th word line switch in the target storage domain to turn on the x2-th local word line and the x2-th global word line of the W global word line;
  • the x2th global word line of the W global word lines inputs a control signal for strobing the target memory cell.
  • the storage domain further includes W second control lines respectively connected to the W word line switches, and the conduction module 1402 is specifically configured to: The control line inputs a control signal for turning on the x2-th word line switch.
  • each module in the storage control 1400 may refer to the memory shown in FIGS. 2, 4, and 6 and related descriptions in the method embodiment shown in FIG. 12, which will not be repeated here.
  • FIG. 15 shows another storage controller provided by an embodiment of the application; this storage controller can be applied to the storage device shown in FIG. 2, FIG. 4, or FIG.
  • the storage controller 1500 may include the following functional units:
  • the strobe module 1501 is configured to strobe a target storage unit in a target storage block, the target storage unit is connected to the yth local bit line in the target storage block, and y is a positive integer not greater than N;
  • the turn-on module 1502 is used to turn on the y-th bit line switch in the target memory block to turn on the y-th local bit line and the y-th global bit line of the N global bit lines ;
  • the writing module 1503 is configured to input the electrical signal corresponding to the target data to the y-th global bit line, so that the electrical signal is stored in the target storage unit.
  • each memory block further includes N first control lines respectively connected to the control ends of the N bit line switches, and the conduction module 1502 is specifically configured to: The first control line of the bit line switch inputs a control signal for turning on the y-th bit line switch.
  • the target storage unit is connected to the x1-th word line in the target storage block, and x1 is a positive integer not greater than M, so
  • the strobe module 1501 is specifically configured to: input a control signal for strobing the target memory cell into the x1-th word line.
  • the target storage unit is connected to the x2-th word line in the target storage domain, and x2 is a positive integer not greater than W, and the strobe module 1501 It is specifically used to: turn on the x2-th word line switch in the target storage domain to turn on the global word line corresponding to the row address and the local word line corresponding to the row address;
  • the x2th global word line in the line inputs a strobe signal used to strobe the target memory cell.
  • the storage domain further includes W second control lines respectively connected to the W word line switches, and the conduction module 1502 is specifically configured to include: The second control line inputs a control signal for turning on the x2-th word line switch.
  • each module in the storage control 1500 may refer to the memory shown in FIGS. 2, 4, and 6 and related descriptions in the method embodiment shown in FIG. 13, which will not be repeated here.
  • control terminal of the transistor in this application can be the gate of the field effect tube, the base of the triode, etc., which are used to control the conduction of the source and drain of the field effect tube, and the collector and emitter. Conduction.
  • the computer-readable medium may include a computer-readable storage medium, which corresponds to a tangible medium, such as a data storage medium, or a communication medium that includes any medium that facilitates the transfer of a computer program from one place to another (for example, according to a communication protocol) .
  • a computer-readable medium may generally correspond to (1) a non-transitory tangible computer-readable storage medium, or (2) a communication medium, such as a signal or carrier wave.
  • Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and/or data structures for implementing the techniques described in this application.
  • the computer program product may include a computer-readable medium.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FPGA field programmable logic arrays
  • processor may refer to any of the foregoing structure or any other structure suitable for implementing the techniques described herein.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FPGA field programmable logic arrays
  • the term "processor” as used herein may refer to any of the foregoing structure or any other structure suitable for implementing the techniques described herein.
  • the functions described by the various illustrative logical blocks, modules, and steps described herein may be provided in dedicated hardware and/or software modules configured for encoding and decoding, or combined Into the combined codec.
  • the technology may be fully implemented in one or more circuits or logic elements.
  • the technology of this application can be implemented in a variety of devices or devices, including wireless handsets, integrated circuits (ICs), or a set of ICs (for example, chipsets).
  • ICs integrated circuits
  • a set of ICs for example, chipsets.
  • Various components, modules, or units are described in this application to emphasize the functional aspects of the device for implementing the disclosed technology, but they do not necessarily need to be implemented by different hardware units.
  • various units can be combined with appropriate software and/or firmware in the codec hardware unit, or by interoperating hardware units (including one or more processors as described above). supply.
  • references described in this specification to "one embodiment” or “some embodiments”, etc. mean that one or more embodiments of the present application include a specific feature, structure, or characteristic described in combination with the embodiment. Therefore, the sentences “in one embodiment”, “in some embodiments”, “in some other embodiments”, “in some other embodiments”, etc. appearing in different places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless it is specifically emphasized otherwise.
  • the terms “including”, “including”, “having” and their variations all mean “including but not limited to”, unless otherwise specifically emphasized.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

一种读/写数据的方法、存储器、存储装置和终端，该存储器，包括S个存储块、N条全局位线和信号放大电路，S个存储块中每个存储块均连接N条全局位线，N条全局位线连接信号放大电路，信号放大电路用于放大N条全局位线中的电信号；每个存储块包括N列存储单元、N条局部位线和N个位线开关，其中：在每个存储块中，第i列存储单元连接第i条局部位线；第i条局部位线通过N个位线开关中的第i个位线开关连接第i条全局位线。通过对存储阵列细粒度化，使得S个存储块的第i条局部位线可以共用一个全局位线，缩短局部位线，降低局部位线引起的寄生电容，减少存储器延时。

Description

读/写数据的方法、存储器、存储装置和终端 技术领域
本发明涉及存储技术领域，尤其涉及一种读/写数据的方法、存储器、存储装置和终端。
背景技术
随着计算机技术的发展，提升计算机系统的运行速度的瓶颈在于存储器，存储器的延时大部分来源于行周期时间(Row Cycle Time，tRC)延时。单位存储阵列相对臃肿(一般为512行*1024列存储单元)是高tRC延时的主要原因之一。在大尺寸的单元存储阵列中，每次字线上的晶体管开启和位线长距离的数据传输，都会造成存储器的延时。
如何降低存储器的延时是当下提升计算机性能亟需解决的技术问题。
发明内容
本发明实施例提供了一种读/写数据的方法、存储器、存储装置和终端，可以解决目前计算机系统中存储器高延时的技术问题。
第一方面，本申请实施例提供了一种存储器，包括S个存储块、N条全局位线和信号放大电路，所述S个存储块中每个存储块连接所述N条全局位线，所述N条全局位线连接所述信号放大电路，所述信号放大电路用于放大所述N条全局位线中的电信号，S、N为正整数，S≥2；所述每个存储块包括N列存储单元、N条局部位线和N个位线开关，其中：
在所述每个存储块中，所述N列存储单元中的第i列存储单元连接所述N条局部位线中的第i条局部位线；所述第i条局部位线通过N个位线开关中的第i个位线开关连接所述N条全局位线中的第i条全局位线，N为正整数，i为不大于N的正整数。
上述存储器，每个存储块中的第i条局部位线均通过一个位线开关连接到同一个全局位线，即第i条全局位线上，此时，通过控制各个存储块中第i个位线开关的导通和断开就可以控制各个存储块中的第i条局部位线与第i条全局位线的导通或断开，从而使得S个存储块的第i条局部位线可以共用一个全局位线，S个存储块可以共用一个信号放大电路和位线驱动电路，以减少存储器中信号放大电路和位线驱动电路在存储器中的配置，降低存储器的制备成本。而且，对存储阵列细粒度化，可以缩短局部位线，降低局部位线引起的寄生电容，读写操作延时也小。
在一种可能的实现中，所述信号放大电路包括N个差分放大器，所述N个差分放大器中的第i个差分信号放大器用于放大所述第i条全局位线上的电信号。
上述存储器，可以实现位于不同列的存储单元中的数据同时被读取，提高存储器读操作的速度。
在一种可能的实现中，所述信号放大电路包括P个多路选通器和P个差分放大器；所述P个多路选通器中的第k个多路选通器的输入端连接所述N条全局位线中的至少2条全局位线，所述P个多路选通器中的第k个多路选通器的输出端连接所述P个差分放大器中的第k个差分放大器，所述P个多路选通器中的第k个多路选通器用于从所述至少2条全局位线传输的电信号中选择一个全局位线传输的电信号输出，P为不大于N的正整数，k 为不大于P的正整数。
采用上述信号放大电路的存储器，与不同的多路选通器间接连接的多个存储单元中的数据可以被同时读取，可兼顾速度和成本。
在一种可能的实现中，所述每个存储块还包括分别连接所述N个位线开关的控制端的N条第一控制线，所述N条第一控制线均连接第一控制电路，所述第一控制电路用于控制所述N个位线开关的导通。
在一种可能的实现中，所述存储器还包括位线驱动电路，所述位线驱动电路连接所述N个全局位线，用于向所述N个全局位线中输入电信号。
在一种可能的实现中，所述每个存储块中的存储单元排列成M行*N列存储单元，所述每个存储块还包括M条字线，所述M行*N列存储单元中第j行存储单元连接所述M条字线中的第j条字线，M为正整数，j为不大于M的正整数。
可选地，所述存储器还包括字线驱动电路，所述字线驱动电路连接所述S个存储块中的字线，所述字线驱动电路用于控制所述字线的电位。
在一种可能的实现中，所述每个存储块被划分为T个存储子块，所述存储器中的存储子块排列成S行T列存储子块，每一列存储子块形成一个存储域，所述存储器包括T个存储域，所述存储器还包括W条全局字线，T、W为正整数，T≥2；所述T个存储域的每个存储域包括W行存储单元、W条局部字线和W个字线开关，其中：
在所述每个存储域中，所述W行存储单元中第v行存储单元连接所述W条局部字线中的第v条局部字线；所述第v条局部字线通过W个位线开关中的第v个字线开关连接所述W条全局字线中的第v条局部字线，W为正整数，v为不大于W的正整数。
上述存储器，通过细粒度化存储器，不仅缩短了局部位线，也缩短了局部字线，进一步降低存储器的操作延时，提升存储器的性能。
可选地，所述每个存储域还包括分别连接所述W个字线开关的W条第二控制线，所述W条第二控制线均连接第二控制电路，所述第二控制电路用于控制所述W个字线开关的导通。
可选地，所述存储器还包括字线驱动电路，所述字线驱动电路连接所述T个存储域中的全局字线，所述字线驱动电路用于控制所述全局字线的电位。
第二方面，本申请实施例还提供了一种存储装置，包括：如上述第一方面所述的任意一种存储器和存储控制器，所述存储器耦合所述存储控制器。
关于存储器的具体实现可以参见上述第一方面中相关描述，这里不再赘述。
第三方面，本申请实施例还提供了一种终端，包括：处理器和上述第一方面所述的任意一种存储器，所述存储器耦合所述处理器。
关于存储器的具体实现可以参见上述第一方面中相关描述，这里不再赘述。
第四方面，本申请实施例还提供了一种读数据的方法，应用于存储器，所述存储器包括S个存储块、N条全局位线和信号放大电路，所述S个存储块中每个存储块连接所述N条全局位线，所述N条全局位线连接所述信号放大电路，所述信号放大电路用于放大所述N条全局位线中的电信号，S、N为正整数，S≥2；所述每个存储块包括N列存储单元、N条局部位线和N个位线开关；其中，在所述每个存储块中，所述N列存储单元中的第i列 存储单元连接所述N条局部位线中的第i条局部位线，所述第i条局部位线通过N个位线开关中的第i个位线开关连接所述N条全局位线中的第i条全局位线，N为正整数，i为不大于N的正整数；所述方法包括：
选通目标存储块中的目标存储单元，其中，所述目标存储单元连接所述目标存储块中的第y条局部位线，y为不大于N的正整数；
导通所述目标存储块中的第y个位线开关，以使所述目标存储单元中的电信号通过所述第y条局部位线传输到所述N条全局位线中的第y条全局位线；
通过所述信号放大电路放大所述第y条全局位线中的电信号。
在一种可能的实现中，所述信号放大电路包括N个差分放大器，所述N差分放大器中的第i个差分信号放大器连接所述第i条全局位线，所述通过所述信号放大电路放大所述第y条全局位线中的电信号，具体包括：
通过目标差分放大器放大所述第y条全局位线中的电信号，其中，所述目标差分放大器为所述N个差分放大器中连接所述第y条全局位线的差分放大器。
在一种可能的实现中，，所述信号放大电路包括P个多路选通器和P个差分放大器；所述P个多路选通器中的第k个多路选通器的输入端连接所述N条全局位线中的至少2条全局位线，所述P个多路选通器中的第k个多路选通器的输出端连接所述P个差分放大器中的第k个差分放大器，所述P个多路选通器中的第k个多路选通器用于从所述至少2条全局位线传输的电信号中选择一个全局位线传输的电信号输出，P为不大于N的正整数，k为不大于P的正整数，所述通过所述信号放大电路放大所述第y条全局位线中的电信号，具体包括：
通过连接所述第y条全局位线的目标多路选通器将所述第y条全局位线中的电信号输入到与所述目标多路选通器连接的目标差分放大器；
通过所述目标差分放大器放大所述第y条全局位线中的电信号。
在一种可能的实现中，所述每个存储块还包括分别连接所述N个位线开关的控制端的N条第一控制线，所述导通所述目标存储块中的第y个位线开关包括：
向连接所述第y个位线开关的第一控制线输入用于使所述第y个位线开关导通的控制信号。
在一种可能的实现中，所述每个存储块中的存储单元排列成M行*N列存储单元，所述每个存储块还包括M条字线，所述M行*N列存储单元中第j行存储单元连接所述M条字线中的第j条字线，M为正整数，j为不大于M的正整数，所述目标存储单元连接所述目标存储块中的第x1条字线，x1为不大于M的正整数，所述
选通目标存储块中的目标存储单元，包括：
向所述第x1条字线中输入用于选通所述目标存储单元的控制信号。
在一种可能的实现中，所述每个存储块被划分为T个存储子块，所述存储器中的存储子块排列成S行T列存储子块，每一列存储子块形成一个存储域，所述存储器包括T个存储域，所述存储器还包括W条全局字线，T、W为正整数，T≥2；所述存储域包括W行存储单元、W条局部字线和W个字线开关；其中，所述W行存储单元中第v行存储单元连接所述W条局部字线中的第v条局部字线；所述第v条局部字线通过W个位线开关中 的第v个字线开关连接所述W条全局字线中的第v条局部字线，W为正整数，v为不大于W的正整数，所述目标存储单元连接目标存储域中的第x2条局部字线，x2为不大于W的正整数，所述选通目标存储块中的目标存储单元包括：
导通所述目标存储域中的第x2个字线开关，以导通所述第x2条局部字线和所述W全局字线中的第x2条全局字线；
向所述W条全局字线中的第x2条全局字线输入用于选通所述目标存储单元的控制信号。
可选地，所述存储域还包括分别连接所述W个字线开关的W条第二控制线，所述导通所述目标存储域中的第x2个字线开关包括：
向连接所述第x2个字线开关的第二控制线输入用于使所述第x2个字线开关导通的控制信号。
第五方面，本申请实施例还提供了一种写数据的方法，应用于存储器，所述存储器包括S个存储块、N条全局位线和信号放大电路，所述S个存储块中每个存储块连接所述N条全局位线，所述N条全局位线连接所述信号放大电路，所述信号放大电路用于放大所述N条全局位线中的电信号，S、N为正整数，S≥2；所述每个存储块包括N列存储单元、N条局部位线和N个位线开关；其中，在所述每个存储块中，所述N列存储单元中的第i列存储单元连接所述N条局部位线中的第i条局部位线，所述第i条局部位线通过N个位线开关中的第i个位线开关连接所述N条全局位线中的第i条全局位线，N为正整数，i为不大于N的正整数；所述方法包括：
选通目标存储块中的目标存储单元，所述目标存储单元连接所述目标存储块中的第y条局部位线，y为不大于N的正整数；
导通所述目标存储块中的第y个位线开关，以导通所述第y条局部位线和所述N条全局位线中的第y条全局位线；
将目标电信号输入到所述第y条全局位线，以使所述目标电信号被存储在所述目标存储单元中。
在一种可能的实现中，所述每个存储块还包括分别连接所述N个位线开关的控制端的N条第一控制线，所述导通所述目标存储块中的第y个位线开关包括：
向连接所述第y个位线开关的第一控制线输入用于使所述第y个位线开关导通的控制信号。
在一种可能的实现中，所述每个存储块中的存储单元排列成M行*N列存储单元，所述每个存储块还包括M条字线，所述M行*N列存储单元中第j行存储单元连接所述M条字线中的第j条字线，M为正整数，j为不大于M的正整数，所述目标存储单元连接所述目标存储块中的第x1条字线，x1为不大于M的正整数，所述选通目标存储块中的目标存储单元包括：
向所述第x1条字线中输入用于选通所述目标存储单元的控制信号。
在一种可能的实现中，所述每个存储块被划分为T个存储子块，所述存储器中的存储子块排列成S行T列存储子块，每一列存储子块形成一个存储域，所述存储器包括T个存储域，所述存储器还包括W条全局字线，T、W为正整数，T≥2；所述存储域包括W行 存储单元、W条局部字线和W个字线开关；其中，所述W行存储单元中第v行存储单元连接所述W条局部字线中的第v条局部字线；所述第v条局部字线通过W个位线开关中的第v个字线开关连接所述W条全局字线中的第v条局部字线，W为正整数，v为不大于W的正整数，所述目标存储单元连接目标存储域中的第x2条字线，x2为不大于W的正整数，所述选通目标存储块中的目标存储单元，包括：
导通所述目标存储域中的第x2个字线开关，以导通所述第x2条局部字线和所述W全局字线中的第x2条全局字线；
向所述W条全局字线中的第x2条全局字线输入用于选通所述目标存储单元的控制信号。
可选地，所述存储域还包括分别连接所述W个字线开关的W条第二控制线，所述导通所述目标存储域中的第x2个字线开关包括：
向连接所述第x2个字线开关应的第二控制线输入用于使所述第x2个字线开关导通的控制信号。
第六方面，本申请实施例还提供了一种存储控制器，应用于如第一方面所述的任意一种存储器，包括用于实现如第四方面所述的任意一种读数据的方法。
第七方面，本申请实施例还提供了一种存储控制器，应用于如第一方面所述的任意一种存储器，包括用于实现如第五方面所述的任意一种读数据的方法。
第八方面，本申请实施例还提供了一种芯片，包括如第一方面所述的任意一种存储器。
附图说明
为了更清楚地说明本发明实施例或背景技术中的技术方案，下面将对本发明实施例或背景技术中所需要使用的附图进行说明。
图1是现有技术提供的一种存储器的电路示意图；
图2是本申请实施例提供的一种存储器的电路示意图；
图3是本申请实施例提供的一种存储单元的电路示意图；
图4是本申请实施例提供的另一种存储器的电路示意图；
图5是本申请实施例提供的一种存储单元的工作原理的示意图；
图6是本申请实施例提供的又一种存储器的电路示意图；
图7是本申请实施例提供的一种存储单元的工作原理的示意图；
图8是本申请实施例提供的一种信号方法电路的电路示意图；
图9是本申请实施例提供的另一种信号方法电路的电路示意图；
图10是本申请实施例提供的一种存储装置的结构示意图；
图11A是本申请实施例提供的一种计算设备的结构示意图；
图11B是本申请实施例提供的另一种计算设备的结构示意图；
图12是本申请实施例提供的一种读数据的方法的流程示意图；
图13是本申请实施例提供的一种写数据的方法的流程示意图；
图14是本申请实施例提供的一种存储控制器的结构示意图；
图15是本申请实施例提供的另一种存储控制器的结构示意图。
具体实施方式
本申请实施例所示的存储器可以是随机存取存储器(random access memory，RAM)、动态随机存取存储器(dynamic random access memory，DRAM)、静态随机存取存储器(static random access memory，SRAM)、同步动态随机存储器(synchronous dynamic random access memory，SDRAM)、双倍速率同步动态随机存储器(double data rate SDRAM，DDR SDRAM)、高带宽存储器(high bandwidth memory，HBM)、只读存储器(read only memory，ROM)、还可以是高速缓冲存储器(cache)、闪速存储器(flash memory)、硬盘(hard disk drive，HDD)、固态硬盘(solid state disk或solid state drive，SSD)等。
为降低存储器的延时，可以采用将单位存储阵列的架构细粒度化的方法。如图1所示为本申请实施例提供的一种存储器的结构示意图，该存储器中将原来的存储阵列划为多个小的存储阵列，分别为每个小的存储阵列配置逻辑电路，如位线灵敏放大器(bit line sense amplifier，BLSA)或差分放大器(sense amplifier，SA)由于将存储阵列细粒度化后，位线变短，进而降低位线引起的寄生电容，降低存储器的延迟。
然而，虽然通过细粒度化降低了每个单位存储阵列的容量，但需要占用更多的面积去配置逻辑电路，导致同等芯片面积下的存储容量缩小，每单位(bit)的成本大幅增加。
为在减少存储器延迟的同时，既降低存储器的成本，本申请提供了一种存储器，该存储通过将存储器中的存储阵列细粒度化，缩短单位存储阵列内位线的长度，减少寄生电容，同时，将各个单位存储阵列内位线(也称为局部位线)分别通过开关连接到全局位线，使得各个单位存储阵列内的位线可以共用全局位线、信号放大电路、位线驱动电路等，降低电路驱动时间的同时降低存储器的成本。
首先介绍本申请涉及的关键术语。
(1)单位存储阵列
单位存储阵列是存储单元组成的存储阵列，该存储阵列中每行存储单元连接到一条字线上，每列存储单元连接到一条位线上。
(2)存储域、存储块
本申请中，存储块或存储域可以是单位存储阵列，也可以是多个沿位线或字线方向排列的多个单位存储阵列。
(3)局部位线(local bitline，LBL)、全局位线(global bitline，GBL)、位线开关
根据位线所在的位置不同将其划分为局部位线和全局位线。其中，仅位于单位存储阵列中的位线或仅与本单位存储阵列中的存储单元连接的位线称为局部位线；位于多个单位存储阵列中或者与多个单元存储阵列中的存储单元连接的位线称为全局位线。
应理解，本申请中全局位线不直接连接存储单元，而是通过一个开关连接局部位线，该开关在本申请中被称为位线开关。即，位线开关是用于连接局部位线和全局字线的开关。
(4)局部字线(local wordline，LWL)、全局字线(global wordline，GWL)、字线开关
根据字线所在的位置不同将其划分为局部字线和全局字线。其中，仅位于单位存储阵列中的字线或仅与本单位存储阵列中的存储单元连接的字线称为局部字线；位于多个单位 存储阵列中或者与多个单元存储阵列中的存储单元连接的字线称为全局字线。
应理解，本申请中全局字线不直接连接存储单元，而是通过一个开关连接局部字线。该开关在本申请中被称为字线开关。即，字线开关是用于连接局部字线和全局字线的开关。
下面结合附图描述本申请提供的存储器。
如图2所示，为本申请实施例提供的一种存储器的电路示意图，该存储器可以包括S个存储块、N条全局位线、信号放大电路、位线驱动电路、字线驱动电路等。其中：S个存储块中每个存储块连接N条全局位线；N条全局位线连接信号放大电路和位线驱动电路；信号放大电路用于放大N条全局位线中的电信号，S、N为正整数，S≥2。位线驱动电路用于在对存储器中的存储单元进行写操作时，选择该存储单元对应的全局位线，以向该全局位线输入电信号；字线驱动电路用于在对存储器中的存储单元进行操作(读操作或写操作)时，该存储单元对应的字线输入电信号。
需要说明的是，虽然图2示出了位线驱动电路、字线驱动电路等，但是信号放大电路、位线驱动电路、字线驱动电路不是本申存储器必须的电路。
在一些实施例中，存储器还可以包括位线驱动电路，位线驱动电路连接上述N个全局位线，用于N个全局位线中输入电信号。应理解，位线驱动电路是在存储器进行写操作时发挥作用的。
例如，当需要向对某一个存储单元写入数据时，则通过位线驱动电路对与该存储单元电连接的全局位线中输入该被写入数据对应的电信号，其中，存储单元具有“0”和“1”两种状态，如，当需要将存储单元置“1”状态时，位线驱动电路向其连接的全局位线中输入高电位，反之，当需要将存储单元置“0”状态时，位线驱动电路向其连接的全局位线中输入低电位。
针对S个存储块中的每个存储块，均包括N列存储单元、N条局部位线和N个位线开关。在每个存储块中，N列存储单元中的第i列存储单元连接N条局部位线中的第i条局部位线；第i条局部位线通过N个位线开关中的第i个位线开关连接N条全局位线中的第i条全局位线，N为正整数，i为不大于N的正整数。其中，i的取值可以是1、2、…、N。
如图2所示的存储器，S个存储块被表示为存储块(1)、存储块(2)、…、存储块(S)。N条全局位线被表示为GBL(1)、GBL(2)、…、GBL(N)，其中，GBL(i)表示为N条全局位线中的第i条全局位线。在每个存储块中，N条局部位线被表示为LBL(1)、LBL(2)、…、LBL(N)，N个位线开关被表示为位线开关1、位线开关2、…、位线开关N，其中，LBL(i)表示一个存储块中的第i条局部位线，位线开关i表示一个存储块中的第i个位线开关。应理解，虽然，各个存储块中N条局部位线和N个位线开关采用相同的表示方式，但S个存储块中任意两个不同的存储块中的LBL(i)实际为不同的两条局部位线；同理，任意两个不同的存储块中的位线开关i实际为不同的两个位线开关。
在本申请一实施例中，每一存储块是一个包括N列存储单元的存储单元阵列，S个存储块沿位线方向排列，形成的一个存储块阵列，该存储块阵列也包括N列存储单元，此时，各个存储块中的位于第i列的存储单元，在S个存储块组成的存储块阵列中依然处于第i列。对于一个存储块来说，第i列存储单元中每个存储单元均连接到第i条局部位线，第i 条局部位线通过第i个位线开关连接到第i条全局位线。
可见，每个存储块中的第i条局部位线均通过一个位线开关连接到同一个全局位线，即第i条全局位线上，此时，通过控制各个存储块中第i个位线开关的导通和断开就可以控制各个存储块中的第i条局部位线与第i条全局位线的导通或断开，从而使得S个存储块的第i条局部位线可以共用一个全局位线，S个存储块可以共用一个信号放大电路和位线驱动电路，以减少存储器中信号放大电路和位线驱动电路在存储器中的配置，降低存储器的制备成本。而且，对存储阵列细粒度化，可以缩短局部位线，降低局部位线引起的寄生电容，读写操作延时也小。
在一些实施例中，存储单元可以是1T1C(1 Transistor-1 Capacitor)存储单元，即由一个晶体管一个电容组成，如图3所示为本申请实施例提供的一种存储单元的电路示意图。在图3中虚线框内的晶体管T c和电容C组成一个存储单元，存储单元通过一个晶体管T c控制电容C进行充/放电。例如，对于一个存储单元来说，晶体管T c的栅极连接字线，晶体管的源极和漏极分别连接局部位线和电容C，这里以晶体管T c为场效应管为例来说明，应理解，晶体管T c还可以是其他类型的晶体管，如三极管等，此处不作限定。还应理解，存储单元还可以是其他结构的存储单元，例如存储器为SRAM，存储单元包括晶体管和锁存器，此处不作限定，
在一些实施例中，位线开关可以包括至少一个晶体管形成的具有导通和关闭功能的开关。例如，位线开关为一个晶体管。
应理解，存储单元中的晶体管或位线开关中的晶体管可以包括三极管、场效应管等，如图4所示为本申请实施例提供的另一种存储器的电路示意图，图4以位线开关为一个晶体管T b、存储单元可以是1T1C为例来说明。
在一些实施例中，如图2或图4所示的存储器，每个存储块还可以包括分别连接N个位线开关的控制端的N条第一控制线，N条第一控制线均连接第一控制电路(图2或图4中未示出)，第一控制电路用于控制S个存储块中各个位线开关的导通和断开。在每个存储块中，N条第一控制线被表示为SC1(1)、SC1(2)、…、SC1(N)，其中，SC1(i)表示一个存储块中的第i条第一控制线。应理解，虽然，各个存储块中N条第一控制线采用相同的表示方式，但S个存储块中任意两个不同的存储块中的SC1(i)实际为不同的两条第一控制线。
例如，当需要对某一存储块中某一存储单元进行读/写操作时，需要将该存储单元通过局部位线所连接的位线开关导通，此时，第一控制电路可以向连接该位线开关的第一控制线上施加高电位，以使得该位线开关处于导通状态，反之，若不需要进行读/写操作的，使得不需要进行读/写操作的存储单元通过局部位线所连接的位线开关断开，此时，第一控制电路可以向连接该位线开关的第一控制线上施加低电位，以使得该位线开关处于断开状态。应理解，上述以位线开关为N型MOS管例来说明。
本申请实施例中，一个存储块可以包括阵列排布的多个存储单元，每个存储块都包括N列存储单元，但各个存储块中存储单元的行数可以相同或不同。例如，如图2或图4所示，每一个存储块中的存储单元均排列成M行*N列存储单元。对于每一个存储块来说，存储块还包括M条字线，其M行*N列存储单元中第j行存储单元连接其M条字线中的第j条字线，M为正整数，j为不大于M的正整数。
如图5所示，为本申请实施例提供的一种存储单元的工作原理的示意图。在对该存储单元进行读操作或写操作据时，需要选通连接该存储单元的字线WL和局部位线LBL，进一步地，局部位线LBL选通需要选通连接该局部位线LBL的全局位线GBL和连接该局部位线LBL的SC1。
其中，以晶体管T b和晶体管T c都为N型MOS晶体管为例来说明，选通WL是指在该WL中输入高电位，以使晶体管T c导通,电容C可以进行充/放电；选通LBL是指，在该LBL连接的SCI中输入高电位以使晶体管T b导通，该LBL与该LBL连接的GBL导通，以及选择该GBL输出或输入电信号，以分别进行读或写操作。
需要说明的是，图2或图4所示的存储器以各个存储块中存储单元的总行数相同，即总行数为M为例来说明。在本申请另一实施例中，不同存储块中存储单元的总行数可以不同，例如，存储块1为M1行*N列的存储单元构成的阵列，存储块2为M2行*N列的存储单元构成的阵列，M1不等于M2，这里不再举例，其中M1和M2均为正整数。
在一些实施例中，存储器还包括字线驱动电路，该字线驱动电路连接S个存储块中的所有的字线，字线驱动电路用于控制其连接的字线的电位，进而，控制位于各个字线上的晶体管的导通和断开。例如，字线驱动电路存储单元中的晶体管为N型MOS管，在需要选通某一行存储单元时，字线驱动电路在该行存储单元连接的字线上施加高电位；反之，在不需要选通该行存储单元时，字线驱动电路在该行存储单元连接的字线上施加低电位。
在一些实施例中，如图6所示，为本申请实施例提供的又一种存储器的电路示意图，该存储器中，S个存储块中每个存储块均被划分为T个存储子块，存储器中的存储子块排列成S行T列存储子块，每一列存储子块形成一个存储域，则，存储器可以包括T个存储域，存储器还包括W条全局字线，T、W为正整数，T≥2；该T个存储域中每个存储域包括W行存储单元、W条局部字线和W个字线开关，其中：
在每个存储域中，W行存储单元中第v行存储单元连接W条局部字线中的第v条局部字线；第v条局部字线通过W个位线开关中的第v个字线开关连接W条全局字线中的第v条局部字线，W为正整数，v为不大于W的正整数。
如图7所示，为本申请实施例提供的另一种存储单元的工作原理的示意图。在对该存储单元进行读操作或写操作据时，需要选通连接该存储单元的字线LWL和局部位线LBL，进一步地，局部位线LBL选通需要选通连接该局部位线LBL的全局位线GBL和连接该局部位线LBL的SC1。局部字线LWL选通需要选通连接该局部字线LWL的全局字线GWL和连接该局部字线LWL的SC2。
其中，以晶体管T b、晶体管T c、晶体管T r都为N型MOS晶体管为例来说明，选通LWL是指，在该LWL连接的SC2中输入高电位以使晶体管T r导通，该LWL与该LWL连接的GWL导通，以及向该GWL输入高电位,使得晶体管T c导通，电容C可以进行充/放电；选通LBL是指，在该LBL连接的SCI中输入高电位以使晶体管T b导通，该LBL与该LBL连接的GBL导通，以及选择该GBL输出或输入电信号，以分别进行读或写操作。
应理解，各个存储域中存储单元的列数可以相同或不同，此处不做限定。如图6所示，存储域(1)中包括n1列存储单元，存储器(T)中包括N-n2列存储单元，其中，n1为大于1的正整数，n2为小于N的正整数。可选地，N为T的倍数，各个存储域中包括相同列 数的存储单元，即N/T列。还应理解，各个存储块中存储单元的总行数可以相同或不同，此处不做限定。例如，如图5所示的存储器，存储块(1)为v1行*N列的存储单元构成的阵列，存储块(S)为v2行*N列的存储单元构成的阵列，v1为大于1的正整数，v2为小于W的正整数，这里以存储器包括W行*N列存储单元为例来说明，W为大于1的正整数。
如图6所示的存储器，T个存储域被表示为存储域1、存储域2、…、存储域T。W条全局字线被表示为GWL(1)、GWL(2)、…、GWL(W)，其中，GWL(v)表示为W条全局字位线中的第v条全局字线。在每个存储域中，W条局部字线被表示为LWL(1)、LWL(2)、…、LWL(W)，W个字线开关被表示为字线开关1、字线开关2、…、字线开关W，其中，LWL(v)表示一个存储域中的第v条局部字线，字线开关v表示一个存储域中的第v个字线开关。应理解，虽然，各个存储域中W条局部字线和W个字线开关采用相同的表示方式，但T个存储域中任意两个不同的存储域中的LWL(v)实际为不同的两条局部字线；同理，任意两个不同的存储域中的字线开关v实际为不同的两个字线开关。
在一些实施例中，每一存储块是一个包括N列存储单元的存储单元阵列，S个存储块沿位线方向排列，形成的一个存储块阵列，该存储块阵列也包括N列存储单元，此时，将每个存储块划分成T个存储子块，每一个存储子块都是一个比存储块更小的存储单元矩阵，且每一个存储块中的第t个存储子块中存储单元的列数相同。存储器中所有的存储子块排列成为S行*T列的存储子块，这里，将一列存储子块形成的区域称为一个存储域，则存储器包括T个存储域。各个存储域中的位于第v行的存储单元，在T个存储域组成的存储阵列中依然处于第v行。对于一个存储域来说，第v行存储单元中每个存储单元均连接到第v条局部字线，第v条局部字线通过第v个字线开关连接到第v条全局字线。
可见，每个存储域中的第v条局部字线均通过一个字线开关连接到同一个全局字线，即第v条全局字线上，此时，通过控制各个存储域中第v个字线开关的导通和断开就可以控制各个存储域中的第v条局部字线与第v条全局字线的导通或断开，从而使得T个存储域的第v条局部字线可以共用一个全局字线，T个存储域可以共用一个字线驱动电路，以减少存储器中字线驱动电路在存储器中的配置，降低存储器的制备成本。而且，对存储阵列细粒度化，可以缩短局部字线，降低局部字线引起的寄生电容，读写操作延时也小。
可选地，如图6所示的存储器，每个存储域还可以包括分别连接W个字线开关的W条第二控制线，所述W条第二控制线均连接第二控制电路(图6中未示出)，第二控制电路用于控制T个存储域中各个字线开关的导通和断开。
在每个存储域中，W条第二控制线被表示为SC2(1)、SC2(2)、…、SC2(W)，其中，SC2(v)表示一个存储域中的第v条第二控制线。应理解，虽然，各个存储域中W条第二控制线采用相同的表示方式，但T个存储域中任意两个不同的存储域中的SC2(v)实际为不同的两条第二控制线。
在一些实施例中，存储器还包括可以字线驱动电路，该字线驱动电路连接上述T个存储域中的全局字线，该字线驱动电路用于控制T个存储域中所有的全局字线的电位。应理解，字线驱动电路通过控制全局字线的电位来控制连接该全局字线的T条局部字线的电位，进而，通过导通该全局字线连接的T个字线开关中的一个或多个字线开关，选通上述一个或多个字线开关连接的局部字线上的存储单元。
例如，当需要对某一存储单元进行读/写操作时，需要将该存储单元通过局部字线所连接的字线开关导通，此时，第二控制电路可以向连接该字线开关的第二控制线上施加高电位，以使得该字线开关处于导通状态，并且，通过字线驱动电路对与该存储单元连接的全局字线中施加高电位，此时，与该存储单元连接的全局字线和与该存储单元连接的局部字线导通，高电位施加到该存储单元的晶体管的控制端，以选通该存储单元。反之，若不需要进行读/写操作的，使得不需要进行读/写操作的存储单元通过局部字线所连接的字线开关断开，此时，第二控制电路可以向连接该字线开关的第二控制线上施加低电位，以使得该字线开关处于断开状态。应理解，上述以字线开关为N型MOS晶体管为例来说明。
应理解，在对存储器中的存储单元进行读操作时，信号放大电路工作。如图8和图9,所示，为本申请实施例提供的两种差分放大电路的电路示意图。
如图8所示的一种差分放大电路，该信号放大电路可以包括N个差分放大器，该N个差分放大器与N条全局位线一一对应，该N个差分放大器中的第i个差分信号放大器用于放大第i条全局位线上的电信号。
在实际应用中，第i个差分信号的一个输入端连接第i条全局位线，输入第i条全局位线上的电信号，另一个输入端连接参考信号，第i个差分信号放大器输出从第i条全局位线上的电信号中去除参考信号后的信号，进而，识别该输出的信号对应的数据。
上述存储器结合图8所示的差分放大电路，可以实现位于不同列的存储单元中的数据同时被读取，提高存储器读操作的速度。
在一些实施例中，该信号放大电路可以包括P个多路选通器和P个差分放大器。其中，多路选通器和差分放大器一一对应；该P个多路选通器中的第k个多路选通器的输入端连接上述N条全局位线中的至少2条全局位线；该P个多路选通器中的第k个多路选通器的输出端连接该P个差分放大器中的第k个差分放大器；该P个多路选通器中的第k个多路选通器用于从第k个多路选通器连接的全局位线传输的电信号中选择一个全局位线传输的电信号输出，P为不大于N的正整数，k为不大于P的正整数。
采用上述信号放大电路的存储器，与不同的多路选通器间接连接的多个存储单元中的数据可以被同时读取，可兼顾速度和成本。
如图9所示的另一种差分放大电路，P＝1。此时，所有全局位线共用一个差分放大器。存储器一次读操作只能读取一个存储单元中的数据。
应理解，上述存储器还可以包括译码器、等其他用于实现存储器的读写数据的功能单元，此处不作限定。
如图10所示为本申请实施例提供的一种存储装置，该存储装置100可以包括存储器101和存储控制器102，存储控制器102耦合存储器101，存储器可以是上述图2、图4或图6所述的任意一种存储器。
在一些实施例中，存储装置100可以是内存，存储控制器即为内存控制器，用于接收处理器发送的针对目标存储单元的请求，进而，通过存储装置中的目标存储单元响应该该请求。其中，请求包括读请求和写请求。
在一些实施例中，存储装置可以是其他存储器，如高速缓存存储器(cache)、DRAM 等，此处不做限定。
如图11A所示为本申请实施例提供的一种计算设备，该计算设备110A可以包括处理器111和存储器112，其中，处理器111和存储器112耦合，例如，通过总线113连接；存储器112可以是上述图2、图4或图6所述的任意一种存储器。
如图11B所示为本申请实施例提供的另一种计算设备，该计算设备110B可以包括处理器114、存储控制器115和存储器116，其中，处理器111和存储控制器115耦合，存储控制器115和存储器116耦合，存储器116可以是上述图2、图4或图6所述的任意一种存储器。
计算设备可以是终端，如手机、平板电脑、笔记本电脑、个人计算机、智能电视、机顶盒、智能手表、智能手环、虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备、智能音响等，计算设备还可以是路由器、服务器、云服务器、云计算设备等包括存储器且具备数据处理功能的设备。
结合上述图2、图4或图6所述的存储器，上述10所述的存储装置和上述图11A、图11B所述的计算设备，下面介绍本申请实施例涉及的一种读数据的方法，该方法由存储控制器或包括存储控制器的存储装置、计算设备执行，该方法可包括但不限于如下步骤：
S12：选通目标存储块中的目标存储单元，目标存储单元连接所述目标存储块中的第y条局部位线，y为不大于N的正整数。
可选地，选通目标存储单元指导通目标存储单元中的晶体管，如图3中存储单元中的晶体管T c，向目标存储单元连接的字线中输入高电位信号，以使目标存储单元存储的电信号可以传输到局部位线，或局部位线中的电信号可以传输到目标存储单元中。
在本申请实施例的一种实现中，存储控制器接收来自处理器的读请求，该读请求用于请求读取目标存储块中的目标存储单元中的数据，其中，读请求携带用于指示该目标存储单元的位置的地址信息，存储控制器在接收到该读请求后，可以根据该地址信息确定目标存储单元在存储器中的行地址和列地址。其中，列地址用于指示该目标存储单元所在的列的标识，行地址用于指示该目标存储单元所在的行的标识。
应理解，一个存储块中一条局部位线和一条字线可以决定一个存储单元的位置，目标存储单元所在的列地址可以包括该目标存储单元连接的局部位线的标识，同理目标存储单元所在的行地址可以包括该目标存储单元连接的字线或局部字线的标识。
例如，在存储器为如图2或如4所示的存储器时，目标存储单元在目标存储块中连接第x1条字线、第y条局部位线，x1≤W，y≤N，W为存储块中存储单元的总行数，N为存储块中存储地址的总列数。
又例如，在存储器为如图6所示的存储器时，目标存储单元在目标存储域中连接第x2条局部字线，目标存储单元在目标存储块中连接第y条局部位线，x2≤W，y≤N，W为存储块中存储单元的总行数，N为存储块中存储地址的总列数。
可选的，存储控制器可以通过译码器得到地址信息确定的目标存储单元所在的行地址和列地址，进而，确定目标存储单元所连接的局部位线、字线或局部字线。下面分别针对图2、图6所示的存储器，和图6所示的存储器来说明选通目标存储器的两种实现方法：
第一种实现方法：
在存储器为如图2、图4所示的存储器时，存储控制器可以通过字线驱动电路向目标存储块中的第x1条字线中输入用于选通目标存储单元的控制信号。
例如，存储单元中的晶体管为N型MOS管，在需要选通某一行存储单元时，字线驱动电路在该目标存储单元连接的第x1条字线上施加高电位，此时，目标存储块中的位于第x1行的存储单元均被选通，目标存储单元也被选通。
第二种实现方法：
在存储器为如图6所示的存储器时，存储控制器可以导通目标存储域中的第x2个字线开关，以导通目标存储域中的第x2条局部字线和W全局字线中的第x2条全局字线，进而，通过字线驱动电路向W条全局字线中的第x2条全局字线输入用于选通目标存储单元的控制信号。
其中，存储控制器导通目标存储域中的第x2个字线开关的一种实现方式可以是：存储控制器向连接第x2个字线开关的第二控制线即SC2(x2)输入用于使第x2个字线开关导通的控制信号。若字线开关为N型MOS晶体管，则控制信号可以是高电位。
应理解，存储控制器也可以先向W条全局字线中的第x2条全局字线输入控制信号再导通第x2个字线开关。
若存储单元中的晶体管为N型MOS晶体管，控制信号可以是高电位。当字线驱动电路在第x2条全局字线上施加高电位时，由于目标存储域中的第x2个字线开关导通，此时，第x2条全局字线上的高电位通过目标存储域中的第x2条局部字线施加到目标存储域中位于第x2行所有的存储单元，目标存储域中位于第x2行所有的存储单元均被选通，目标存储单元也被选通。
S14：导通目标存储块中的第y个位线开关，以使目标存储器中的目标存储单元中的电信号通过第y条局部位线传输到N条全局位线中的第y条全局位线。
可以理解，在导通目标存储块中的第y个位线开关后，目标存储器中的第y条局部位线传输到N条全局位线与第y条全局位线导通。
其中，存储控制器导通目标存储块中的第y个位线开关的一种实现方式可以是：存储控制器向连接目标存储块中的第y个位线开关的第一控制线SC1(y)输入用于使该第y个位线开关导通的控制信号。若位线开关为N型MOS晶体管，则该控制信号可以是高电位。
S16：通过信号放大电路放大所述第y条全局位线中的电信号。
对于包括N个差分放大器的信号放大电路(如图8所示)来说，S16的一种实现方式可以是：存储控制器通过目标差分放大器放大第y条全局位线中的电信号，其中，目标差分放大器为N个差分放大器中连接第y条全局位线的差分放大器。
对于包括P个差分放大器和P个多路选通器的信号放大电路(如图9所示)来说，S16的一种实现方式可以是：存储控制器通过连接第y条全局位线的目标多路选通器将第y条全局位线中的电信号输入到与目标多路选通器连接的目标差分放大器；目标多路选通器为P个多路选通器中与第y条全局位线连接的多路选通器，用于仅将第y条全局位线中的电信号传输到与目标多路选通器连接的差分放大器(这里称为目标差分放大器)，进而，通过该目标差分放大器放大所述第y条全局位线中的电信号。
进一步地，存储控制器可以读取该电信号对应的数据，将该读取到的数据发送给处理器。
应理解，放大第y条全局位线中的电信号的目的是为了去除该电信号中的参考信号，进而放大后的信号更接近目标存储块中目标存储单元内存储的信号，以准确识别该目标存储单元中的数据。
结合上述图2、图4或图6所述的存储器，上述10所述的存储装置和上述图11A、图11B所述的计算设备，下面介绍本申请实施例涉及的一种写数据的方法，该方法由存储控制器或包括存储控制器的存储装置、计算设备执行，该方法可包括但不限于如下步骤：
S22：选通目标存储块中的目标存储单元，目标存储单元连接目标存储块中的第y条局部位线，y为不大于N的正整数。
在本申请实施例的一种实现中，存储控制器接收来自处理器的写请求，该写请求用于请求在目标存储块中的目标存储单元中的写入目标数据，其中，写请求携带用于指示该目标存储块的位置的地址信息，存储控制器在接收到该写请求后，可以根据该地址信息确定目标存储单元在存储器中的行地址和列地址。其中，列地址用于指示该的目标存储单元所在的列的标识，行地址用于指示该目标存储单元所在的行的标识。
基于写请求和读请求携带的地址信息确定目标存储块中的目标存储单元的所在的行地址和列地址的实现方式相同，具体可上述图12所示的读数据的方法实施例中相关描述，这里不再赘述。
应理解，一个存储块中一条局部位线和一条字线可以决定一个存储单元的位置，目标存储单元所在的列地址可以包括该目标存储单元连接的局部位线的标识。同理，目标存储单元所在的行地址可以包括该目标存储单元连接的字线或局部字线的标识。
例如，在存储器为如图2或图4所示的存储器时，目标存储单元在目标存储块中连接第x1条字线、第y条局部位线，x1≤W，y≤N，W为存储块中存储单元的总行数，N为存储块中存储地址的总列数。
又例如，在存储器为如图6所示的存储器时，目标存储单元在目标存储域中连接第x2条局部字线，目标存储单元在目标存储块中连接第y条局部位线，x2≤W，y≤N，W为存储块中存储单元的总行数，N为存储块中存储地址的总列数。
应理解，虽然在图12所示的读数据的方法实施例中和在图13所示的写数据的方法实施例中都采用了y、x1、x2、目标存储块、目标存储单元、目标存储域等描述，应当理解，在上述两种方法实施例中y所实际指代的正整数、x1所实际指代的正整数、x2所实际指代的正整数、目标存储块所实际指代的存储块、目标存储单元所实际指代的存储单元、目标存储域所实际指代的存储域均可以不同。
选通目标存储单元的具体实现可以参见上述图12所示的读数据的方法实施例中选通目标存储单元的具体实现，这里不再赘述。
S24：导通目标存储块中的第y个位线开关，以导通第y条局部位线和所述N条全局位线中的第y条全局位线。
S24的具体实现可以参见上述图12所示的方法实施例中步骤S14中相关描述，这里不 再赘述。
S26：将目标数据对应的电信号输入到第y条全局位线，以使所述电信号被存储在所述目标存储单元中。
其中，以存储单元仅包括“0”、“1”两种状态为例，数据“1”对应高电位，数据“1”对应低电位。
应理解，在上述目标存储单元被选通，可以通过位线驱动电路向将目标数据对应的电信号输入到第y条全局位线，由于目标存储块第y个位线开关导通，该电信号可以通过目标存储块的第y条局部位线传输到目标存储单元中，该电信号可以被存储在目标存储单元中的电容中。
如图14所示为本申请实施例提供的一种存储控制器；该存储控制器可以应用于上述图2、图4或图6所示的存储器，上述10所述的存储装置和上述图11A、图11B所述的计算设备，该存储控制器1400可以包括如下功能单元：
选通模块1401，用于选通目标存储块中的目标存储单元，其中，所述目标存储单元连接所述目标存储块中的第y条局部位线，y为不大于N的正整数；
导通模块1402，用于导通所述目标存储块中的第y个位线开关，以使所述目标存储单元中的电信号通过所述第y条局部位线传输到所述N条全局位线中的第y条全局位线；
放大模块1403，用于通过所述信号放大电路放大所述第y条全局位线中的电信号。
在一种可选的实现中，对应于包括上述图8所示的信号放大电路的存储器，放大模块1403具体用于：通过目标差分放大器放大所述第y条全局位线中的电信号，其中，所述目标差分放大器为所述N个差分放大器中连接所述第y条全局位线的差分放大器。
在一种可选的实现中，对应于上述包括P个多路选通器和P个差分放大器的存储器(上述图9所示的信号放大电路的存储器)，放大模块1403具体用于：通过连接所述第y条全局位线的目标多路选通器将所述第y条全局位线中的电信号输入到与所述目标多路选通器连接的目标差分放大器；通过所述目标差分放大器放大所述第y条全局位线中的电信号。
在一种可选的实现中，所述每个存储块还包括分别连接所述N个位线开关的控制端的N条第一控制线，所述导通模块1402具体用于：向连接所述第y个位线开关的第一控制线输入用于使所述第y个位线开关导通的控制信号。
在一种可选的实现中，对应于图2或图4所示的存储器，所述目标存储单元连接所述目标存储块中的第x1条字线，x1为不大于M的正整数，所述选通模块1401具体用于：向所述第x1条字线中输入用于选通所述目标存储单元的控制信号。
在一种可选的实现中，对应于图6所示的存储器，所述目标存储单元连接目标存储域中的第x2条局部字线，x2为不大于W的正整数，所述选通模块1401具体用于：导通所述目标存储域中的第x2个字线开关，以导通所述第x2条局部字线和所述W全局字线中的第x2条全局字线；向所述W条全局字线中的第x2条全局字线输入用于选通所述目标存储单元的控制信号。
可选的，所述存储域还包括分别连接所述W个字线开关的W条第二控制线，所述导通模块1402具体用于：向连接所述第x2个字线开关的第二控制线输入用于使所述第x2个 字线开关导通的控制信号。
需要说明的是，上述存储控制1400中各个模块的具体实现可以参见上述图2、图4和图6所示的存储器，及图12所示的方法实施例中相关描述，这里不再赘述。
如图15所示为本申请实施例提供的另一种存储控制器；该存储控制器可以应用于上述图2、图4或图6所示的存储器，上述10所述的存储装置和上述图11A、图11B所述的计算设备，该存储控制器1500可以包括如下功能单元：
选通模块1501，用于选通目标存储块中的目标存储单元，所述目标存储单元连接所述目标存储块中的第y条局部位线，y为不大于N的正整数；
导通模块1502，用于导通所述目标存储块中的第y个位线开关，以导通所述第y条局部位线和所述N条全局位线中的第y条全局位线；
写入模块1503，用于将所述目标数据对应的电信号输入到所述第y条全局位线，以使所述电信号被存储在所述目标存储单元中。
在一种可选的实现中，每个存储块还包括分别连接所述N个位线开关的控制端的N条第一控制线，所述导通模块1502具体用于：向连接所述第y个位线开关的第一控制线输入用于使所述第y个位线开关导通的控制信号。
在一种可选的实现中，对应于图2或图4所示的存储器，所述目标存储单元连接所述目标存储块中的第x1条字线，x1为不大于M的正整数，所述选通模块1501具体用于：向所述第x1条字线中输入用于选通所述目标存储单元的控制信号。
在一种可选的实现中，对应于图6所示的存储器，所述目标存储单元连接目标存储域中的第x2条字线，x2为不大于W的正整数，所述选通模块1501具体用于：导通所述目标存储域中的第x2个字线开关，以导通所述行地址对应的全局字线和所述行地址对应的局部字线；向所述W条全局字线中的第x2条全局字线输入用于选通所述目标存储单元的选通制信号。
可选的，所述存储域还包括分别连接所述W个字线开关的W条第二控制线，所述导通模块1502具体用于包括：向连接所述第x2个字线开关应的第二控制线输入用于使所述第x2个字线开关导通的控制信号。
需要说明的是，上述存储控制1500中各个模块的具体实现可以参见上述图2、图4和图6所示的存储器，及上述图13所示的方法实施例中相关描述，这里不再赘述。
以上述晶体管都为N型MOS管为例来说明。应理解，不同类型的晶体管，控制其导通和截止的方式不同，具体实现为现有技术，这里不再赘述。另外，本申请中称“晶体管的控制端”可以是场效应管的栅极、三极管的基极等，分别用于控制场效应管的源极和漏极的导通、集电极和发射极的导通。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本领域技术人员能够领会，结合本文公开描述的各种说明性逻辑框、模块和算法步骤 所描述的功能可以硬件、软件、固件或其任何组合来实施。如果以软件来实施，那么各种说明性逻辑框、模块、和步骤描述的功能可作为一或多个指令或代码在计算机可读媒体上存储或传输，且由基于硬件的处理单元执行。计算机可读媒体可包含计算机可读存储媒体，其对应于有形媒体，例如数据存储媒体，或包括任何促进将计算机程序从一处传送到另一处的媒体(例如，根据通信协议)的通信媒体。以此方式，计算机可读媒体大体上可对应于(1)非暂时性的有形计算机可读存储媒体，或(2)通信媒体，例如信号或载波。数据存储媒体可为可由一或多个计算机或一或多个处理器存取以检索用于实施本申请中描述的技术的指令、代码和/或数据结构的任何可用媒体。计算机程序产品可包含计算机可读媒体。
可通过例如一或多个数字信号处理器(DSP)、通用微处理器、专用集成电路(ASIC)、现场可编程逻辑阵列(FPGA)或其它等效集成或离散逻辑电路等一或多个处理器来执行指令。因此，如本文中所使用的术语“处理器”可指前述结构或适合于实施本文中所描述的技术的任一其它结构中的任一者。另外，在一些方面中，本文中所描述的各种说明性逻辑框、模块、和步骤所描述的功能可以提供于经配置以用于编码和解码的专用硬件和/或软件模块内，或者并入在组合编解码器中。而且，所述技术可完全实施于一或多个电路或逻辑元件中。
本申请的技术可在各种各样的装置或设备中实施，包含无线手持机、集成电路(IC)或一组IC(例如，芯片组)。本申请中描述各种组件、模块或单元是为了强调用于执行所揭示的技术的装置的功能方面，但未必需要由不同硬件单元实现。实际上，如上文所描述，各种单元可结合合适的软件和/或固件组合在编码解码器硬件单元中，或者通过互操作硬件单元(包含如上文所描述的一或多个处理器)来提供。
以上实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。还应当理解，在本申请以下各实施例中，“至少一个”、“一个或多个”是指一个、两个或两个以上。术语“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系；例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A、B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
以上所述，仅为本申请示例性的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应该以权利要求的保护范围为准。

Claims (24)

  1. 一种存储器，其特征在于，包括S个存储块、N条全局位线和信号放大电路，所述S个存储块中每个存储块连接所述N条全局位线，所述N条全局位线连接所述信号放大电路，所述信号放大电路用于放大所述N条全局位线中的电信号，S、N为正整数，S≥2；所述每个存储块包括N列存储单元、N条局部位线和N个位线开关，其中：
    在所述每个存储块中，所述N列存储单元中的第i列存储单元连接所述N条局部位线中的第i条局部位线；所述第i条局部位线通过N个位线开关中的第i个位线开关连接所述N条全局位线中的第i条全局位线，N为正整数，i为不大于N的正整数。
  2. 如权利要求1所述的存储器，其特征在于，所述信号放大电路包括N个差分放大器，所述N个差分放大器中的第i个差分信号放大器用于放大所述第i条全局位线上的电信号。
  3. 如权利要求1所述的存储器，其特征在于，所述信号放大电路包括P个多路选通器和P个差分放大器；所述P个多路选通器中的第k个多路选通器的输入端连接所述N条全局位线中的至少2条全局位线，所述P个多路选通器中的第k个多路选通器的输出端连接所述P个差分放大器中的第k个差分放大器，所述P个多路选通器中的第k个多路选通器用于从所述至少2条全局位线传输的电信号中选择一个全局位线传输的电信号输出，P为不大于N的正整数，k为不大于P的正整数。
  4. 如权利要求1-3任一项所述的存储器，其特征在于，所述每个存储块还包括分别连接所述N个位线开关的控制端的N条第一控制线，所述N条第一控制线均连接第一控制电路，所述第一控制电路用于控制所述N个位线开关的导通。
  5. 如权利要求1-4任一项所述的存储器，其特征在于，所述存储器还包括位线驱动电路，所述位线驱动电路连接所述N个全局位线，用于向所述N个全局位线中输入电信号。
  6. 如权利要求1-5任一项所述的存储器，其特征在于，所述每个存储块中的存储单元排列成M行*N列存储单元，所述每个存储块还包括M条字线，所述M行*N列存储单元中第j行存储单元连接所述M条字线中的第j条字线，M为正整数，j为不大于M的正整数。
  7. 如权利要求6所述的存储器，其特征在于，所述存储器还包括字线驱动电路，所述字线驱动电路连接所述S个存储块中的字线，所述字线驱动电路用于控制所述字线的电位。
  8. 如权利要求1-5任一项所述的存储器，其特征在于，所述每个存储块被划分为T个存储子块，所述存储器中的存储子块排列成S行T列存储子块，每一列存储子块形成一个 存储域，所述存储器包括T个存储域，所述存储器还包括W条全局字线，T、W为正整数，T≥2；所述T个存储域的每个存储域包括W行存储单元、W条局部字线和W个字线开关，其中：
    在所述每个存储域中，所述W行存储单元中第v行存储单元连接所述W条局部字线中的第v条局部字线；所述第v条局部字线通过W个位线开关中的第v个字线开关连接所述W条全局字线中的第v条局部字线，W为正整数，v为不大于W的正整数。
  9. 如权利要求8所述的存储器，其特征在于，所述每个存储域还包括分别连接所述W个字线开关的W条第二控制线，所述W条第二控制线均连接第二控制电路，所述第二控制电路用于控制所述W个字线开关的导通。
  10. 如权利要求8或9所述的存储器，其特征在于，所述存储器还包括字线驱动电路，所述字线驱动电路连接所述T个存储域中的全局字线，所述字线驱动电路用于控制所述全局字线的电位。
  11. 一种存储装置，其特征在于，包括：如权利要求1-10任一项所述的存储器和存储控制器，所述存储器耦合所述存储控制器。
  12. 一种终端，其特征在于，包括：处理器和如权利要求1-10任一项所述的存储器，所述存储器耦合所述处理器。
  13. 一种读数据的方法，其特征在于，应用于存储器，所述存储器包括S个存储块、N条全局位线和信号放大电路，所述S个存储块中每个存储块连接所述N条全局位线，所述N条全局位线连接所述信号放大电路，所述信号放大电路用于放大所述N条全局位线中的电信号，S、N为正整数，S≥2；所述每个存储块包括N列存储单元、N条局部位线和N个位线开关；其中，在所述每个存储块中，所述N列存储单元中的第i列存储单元连接所述N条局部位线中的第i条局部位线，所述第i条局部位线通过N个位线开关中的第i个位线开关连接所述N条全局位线中的第i条全局位线，N为正整数，i为不大于N的正整数；所述方法包括：
    选通目标存储块中的目标存储单元，其中，所述目标存储单元连接所述目标存储块中的第y条局部位线，y为不大于N的正整数；
    导通所述目标存储块中的第y个位线开关，以使所述目标存储单元中的电信号通过所述第y条局部位线传输到所述N条全局位线中的第y条全局位线；
    通过所述信号放大电路放大所述第y条全局位线中的电信号。
  14. 如权利要求13所述的方法，其特征在于，所述信号放大电路包括N个差分放大器，所述N差分放大器中的第i个差分信号放大器连接所述第i条全局位线，所述通过所述信号放大电路放大所述第y条全局位线中的电信号，具体包括：
    通过目标差分放大器放大所述第y条全局位线中的电信号，其中，所述目标差分放大器为所述N个差分放大器中连接所述第y条全局位线的差分放大器。
  15. 如权利要求13所述的方法，其特征在于，所述信号放大电路包括P个多路选通器和P个差分放大器；所述P个多路选通器中的第k个多路选通器的输入端连接所述N条全局位线中的至少2条全局位线，所述P个多路选通器中的第k个多路选通器的输出端连接所述P个差分放大器中的第k个差分放大器，所述P个多路选通器中的第k个多路选通器用于从所述至少2条全局位线传输的电信号中选择一个全局位线传输的电信号输出，P为不大于N的正整数，k为不大于P的正整数，所述通过所述信号放大电路放大所述第y条全局位线中的电信号，具体包括：
    通过连接所述第y条全局位线的目标多路选通器将所述第y条全局位线中的电信号输入到与所述目标多路选通器连接的目标差分放大器；
    通过所述目标差分放大器放大所述第y条全局位线中的电信号。
  16. 如权利要求13-15任一项所述的方法，其特征在于，所述每个存储块还包括分别连接所述N个位线开关的控制端的N条第一控制线，所述导通所述目标存储块中的第y个位线开关包括：
    向连接所述第y个位线开关的第一控制线输入用于使所述第y个位线开关导通的控制信号。
  17. 如权利要求13-16任一项所述的方法，其特征在于，所述每个存储块中的存储单元排列成M行*N列存储单元，所述每个存储块还包括M条字线，所述M行*N列存储单元中第j行存储单元连接所述M条字线中的第j条字线，M为正整数，j为不大于M的正整数，所述目标存储单元连接所述目标存储块中的第x1条字线，x1为不大于M的正整数，所述选通目标存储块中的目标存储单元，包括：
    向所述第x1条字线中输入用于选通所述目标存储单元的控制信号。
  18. 如权利要求13-16任一项所述的方法，其特征在于，所述每个存储块被划分为T个存储子块，所述存储器中的存储子块排列成S行T列存储子块，每一列存储子块形成一个存储域，所述存储器包括T个存储域，所述存储器还包括W条全局字线，T、W为正整数，T≥2；所述存储域包括W行存储单元、W条局部字线和W个字线开关；其中，所述W行存储单元中第v行存储单元连接所述W条局部字线中的第v条局部字线；所述第v条局部字线通过W个位线开关中的第v个字线开关连接所述W条全局字线中的第v条局部字线，W为正整数，v为不大于W的正整数，所述目标存储单元连接目标存储域中的第x2条局部字线，x2为不大于W的正整数，所述选通目标存储块中的目标存储单元包括：
    导通所述目标存储域中的第x2个字线开关，以导通所述第x2条局部字线和所述W全局字线中的第x2条全局字线；
    向所述W条全局字线中的第x2条全局字线输入用于选通所述目标存储单元的控制信 号。
  19. 如权利要求18所述的方法，其特征在于，所述存储域还包括分别连接所述W个字线开关的W条第二控制线，所述导通所述目标存储域中的第x2个字线开关包括：
    向连接所述第x2个字线开关的第二控制线输入用于使所述第x2个字线开关导通的控制信号。
  20. 一种写数据的方法，其特征在于，应用于存储器，所述存储器包括S个存储块、N条全局位线和信号放大电路，所述S个存储块中每个存储块连接所述N条全局位线，所述N条全局位线连接所述信号放大电路，所述信号放大电路用于放大所述N条全局位线中的电信号，S、N为正整数，S≥2；所述每个存储块包括N列存储单元、N条局部位线和N个位线开关；其中，在所述每个存储块中，所述N列存储单元中的第i列存储单元连接所述N条局部位线中的第i条局部位线，所述第i条局部位线通过N个位线开关中的第i个位线开关连接所述N条全局位线中的第i条全局位线，N为正整数，i为不大于N的正整数；所述方法包括：
    选通目标存储块中的目标存储单元，所述目标存储单元连接所述目标存储块中的第y条局部位线，y为不大于N的正整数；
    导通所述目标存储块中的第y个位线开关，以导通所述第y条局部位线和所述N条全局位线中的第y条全局位线；
    将目标电信号输入到所述第y条全局位线，以使所述目标电信号被存储在所述目标存储单元中。
  21. 如权利要求20所述的方法，其特征在于，所述每个存储块还包括分别连接所述N个位线开关的控制端的N条第一控制线，所述导通所述目标存储块中的第y个位线开关包括：
    向连接所述第y个位线开关的第一控制线输入用于使所述第y个位线开关导通的控制信号。
  22. 如权利要求20或21任一项所述的方法，其特征在于，所述每个存储块中的存储单元排列成M行*N列存储单元，所述每个存储块还包括M条字线，所述M行*N列存储单元中第j行存储单元连接所述M条字线中的第j条字线，M为正整数，j为不大于M的正整数，所述目标存储单元连接所述目标存储块中的第x1条字线，x1为不大于M的正整数，所述选通目标存储块中的目标存储单元包括：
    向所述第x1条字线中输入用于选通所述目标存储单元的控制信号。
  23. 如权利要求20或21所述的方法，其特征在于，所述每个存储块被划分为T个存储子块，所述存储器中的存储子块排列成S行T列存储子块，每一列存储子块形成一个存储域，所述存储器包括T个存储域，所述存储器还包括W条全局字线，T、W为正整数， T≥2；所述存储域包括W行存储单元、W条局部字线和W个字线开关；其中，所述W行存储单元中第v行存储单元连接所述W条局部字线中的第v条局部字线；所述第v条局部字线通过W个位线开关中的第v个字线开关连接所述W条全局字线中的第v条局部字线，W为正整数，v为不大于W的正整数，所述目标存储单元连接目标存储域中的第x2条字线，x2为不大于W的正整数，所述选通目标存储块中的目标存储单元，包括：
    导通所述目标存储域中的第x2个字线开关，以导通所述第x2条局部字线和所述W全局字线中的第x2条全局字线；
    向所述W条全局字线中的第x2条全局字线输入用于选通所述目标存储单元的控制信号。
  24. 如权利要求23所述的方法，其特征在于，所述存储域还包括分别连接所述W个字线开关的W条第二控制线，所述导通所述目标存储域中的第x2个字线开关包括：
    向连接所述第x2个字线开关应的第二控制线输入用于使所述第x2个字线开关导通的控制信号。
PCT/CN2020/076279 2020-02-21 2020-02-21 读/写数据的方法、存储器、存储装置和终端 WO2021164032A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP20919490.1A EP4092676A4 (en) 2020-02-21 2020-02-21 DATA READ/WRITE METHOD, MEMORY, STORAGE DEVICE, AND TERMINAL
CN202080095326.0A CN115039176A (zh) 2020-02-21 2020-02-21 读/写数据的方法、存储器、存储装置和终端
PCT/CN2020/076279 WO2021164032A1 (zh) 2020-02-21 2020-02-21 读/写数据的方法、存储器、存储装置和终端
US17/893,067 US20220406348A1 (en) 2020-02-21 2022-08-22 Data reading/writing method, memory, storage apparatus, and terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/076279 WO2021164032A1 (zh) 2020-02-21 2020-02-21 读/写数据的方法、存储器、存储装置和终端

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/893,067 Continuation US20220406348A1 (en) 2020-02-21 2022-08-22 Data reading/writing method, memory, storage apparatus, and terminal

Publications (1)

Publication Number Publication Date
WO2021164032A1 true WO2021164032A1 (zh) 2021-08-26

Family

ID=77390388

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/076279 WO2021164032A1 (zh) 2020-02-21 2020-02-21 读/写数据的方法、存储器、存储装置和终端

Country Status (4)

Country Link
US (1) US20220406348A1 (zh)
EP (1) EP4092676A4 (zh)
CN (1) CN115039176A (zh)
WO (1) WO2021164032A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023165002A1 (zh) * 2022-03-03 2023-09-07 长鑫存储技术有限公司 数据写入电路、数据写入方法和存储器
WO2024000618A1 (zh) * 2022-06-27 2024-01-04 长鑫存储技术有限公司 存储单元的检测方法及设备
US12009024B2 (en) 2022-03-03 2024-06-11 Changxin Memory Technologies, Inc. Circuit for reading out data, method for reading out data and memory

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1516195A (zh) * 1996-08-06 2004-07-28 ������������ʽ���� 半导体装置和半导体存储装置
CN1591689A (zh) * 2003-08-19 2005-03-09 三星电子株式会社 非易失性半导体存储器件
CN101221540A (zh) * 2007-01-09 2008-07-16 国际商业机器公司 用于减少存储器访问时延的方法和设备以及数据处理系统
WO2016209542A1 (en) * 2015-06-26 2016-12-29 Intel Corporation Method and apparatus for reducing read latency for a block erasable non-volatile memory
CN107799141A (zh) * 2016-09-06 2018-03-13 补丁科技股份有限公司 存储器结构
US20190361820A1 (en) * 2018-05-25 2019-11-28 Rambus Inc. Low latency memory access

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917744A (en) * 1997-12-18 1999-06-29 Siemens Aktiengesellschaft Semiconductor memory having hierarchical bit line architecture with interleaved master bitlines
US6411557B2 (en) * 2000-02-02 2002-06-25 Broadcom Corporation Memory architecture with single-port cell and dual-port (read and write) functionality

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1516195A (zh) * 1996-08-06 2004-07-28 ������������ʽ���� 半导体装置和半导体存储装置
CN1591689A (zh) * 2003-08-19 2005-03-09 三星电子株式会社 非易失性半导体存储器件
CN101221540A (zh) * 2007-01-09 2008-07-16 国际商业机器公司 用于减少存储器访问时延的方法和设备以及数据处理系统
WO2016209542A1 (en) * 2015-06-26 2016-12-29 Intel Corporation Method and apparatus for reducing read latency for a block erasable non-volatile memory
CN107799141A (zh) * 2016-09-06 2018-03-13 补丁科技股份有限公司 存储器结构
US20190361820A1 (en) * 2018-05-25 2019-11-28 Rambus Inc. Low latency memory access

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4092676A4 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023165002A1 (zh) * 2022-03-03 2023-09-07 长鑫存储技术有限公司 数据写入电路、数据写入方法和存储器
US12009024B2 (en) 2022-03-03 2024-06-11 Changxin Memory Technologies, Inc. Circuit for reading out data, method for reading out data and memory
WO2024000618A1 (zh) * 2022-06-27 2024-01-04 长鑫存储技术有限公司 存储单元的检测方法及设备

Also Published As

Publication number Publication date
EP4092676A1 (en) 2022-11-23
CN115039176A (zh) 2022-09-09
US20220406348A1 (en) 2022-12-22
EP4092676A4 (en) 2023-01-25

Similar Documents

Publication Publication Date Title
US11024365B1 (en) Time interleaved sampling of sense amplifier circuits, memory devices and methods of operating memory devices
KR102434162B1 (ko) 데이터 캐싱
US20220406348A1 (en) Data reading/writing method, memory, storage apparatus, and terminal
US9767885B2 (en) Semiconductor systems for fast sensing speed and correct amplification
US10409741B2 (en) Semiconductor memory apparatus and data input/output method thereof
US7283388B2 (en) Memory device using multiple layer nano tube cell
TWI764344B (zh) 用來在記憶體模組中增加資料預取數量的裝置
US8966153B2 (en) Semiconductor memory device and information data processing apparatus including the same
US11900991B2 (en) Integrated circuit for memory
CN110838310A (zh) 半导体存储器设备
KR100668513B1 (ko) 반도체 메모리 장치
CN116580730B (zh) 数据传输电路以及存储器
US20110096585A1 (en) Semiconductor device having hierarchical data line structure and control method thereof
US10811061B1 (en) Reduced die size and improved memory cell restore using shared common source driver
TWI533324B (zh) 記憶體架構
US20220406344A1 (en) Programmable column access
WO2021168839A1 (zh) 一种存储器和电子设备
KR20150052632A (ko) 반도체장치
JP2013041657A (ja) 共通の列マルチプレクサ及びセンスアンプハードウェアを有するランダムアクセスメモリコントローラ
KR102409969B1 (ko) 다른 메모리 셀들을 포함하는 하이브리드 dram 어레이
US6597040B2 (en) Semiconductor device having MOS transistor for coupling two signal lines
WO2022193249A1 (zh) 一种存储器及电子设备
WO2023202166A1 (zh) 一种位线读取电路、存储器及电子设备
US20210103533A1 (en) Memory system and memory chip
US20230352084A1 (en) Latch-based storage circuits having efficient integrated circuit layouts

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20919490

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020919490

Country of ref document: EP

Effective date: 20220817

NENP Non-entry into the national phase

Ref country code: DE