WO2022048074A1 - 灵敏放大器、存储器和灵敏放大器的控制方法 - Google Patents

灵敏放大器、存储器和灵敏放大器的控制方法 Download PDF

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Publication number
WO2022048074A1
WO2022048074A1 PCT/CN2020/139653 CN2020139653W WO2022048074A1 WO 2022048074 A1 WO2022048074 A1 WO 2022048074A1 CN 2020139653 W CN2020139653 W CN 2020139653W WO 2022048074 A1 WO2022048074 A1 WO 2022048074A1
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Prior art keywords
switch
sense amplifier
transistor
bit line
pmos transistor
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PCT/CN2020/139653
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English (en)
French (fr)
Inventor
蔺智挺
温光雷
何军
应战
李新
曹堪宇
卢文娟
彭春雨
吴秀龙
陈军宁
Original Assignee
安徽大学
长鑫存储技术有限公司
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Application filed by 安徽大学, 长鑫存储技术有限公司 filed Critical 安徽大学
Priority to US17/472,157 priority Critical patent/US11929111B2/en
Publication of WO2022048074A1 publication Critical patent/WO2022048074A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Definitions

  • the present disclosure relates to the technical field of semiconductor memory, and in particular, to a sense amplifier, a memory and a control method of the sense amplifier.
  • DRAM Dynamic Random Access Memory, dynamic random access memory
  • SRAM Static Random-Access Memory, static random access memory
  • each bit line in a different array of memory cells is connected in pairs to a sense amplifier having one bit line BL (read bit line) input and one bit line BLB (reference bit line) input.
  • the function of the sense amplifier is to read the voltage difference between the bit line BL and the reference bit line BLB, and amplify the voltage difference between the two bit lines.
  • Sense amplifiers include metal-oxide semiconductor field effect transistors (MOSFETs).
  • MOSFETs metal-oxide semiconductor field effect transistors
  • two MOSFETs that are the same theoretically may be mismatched, that is, have different characteristics, making sense amplifiers. Offset noise is generated, and the offset noise can seriously affect the performance of semiconductor memory.
  • the purpose of the present disclosure is to provide a sense amplifier, a memory and a control method for the sense amplifier, thereby at least to a certain extent overcome the problem that the performance of semiconductor memory is affected by the mismatch of transistors in the sense amplifier.
  • a sense amplifier comprising: an amplification module; data for a storage unit; a control module, electrically connected to the amplification module; wherein, in the first offset compensation stage of the sense amplifier, the control module uses Because the amplifying module is configured to include a first inverter and a second inverter, the first inverter and the second inverter are both inverters whose input and output are connected; in the second offset compensation stage of the sense amplifier, The control module is used to configure the amplification module to include a current mirror structure.
  • the amplification module includes: a first PMOS transistor; a second PMOS transistor; a first NMOS transistor, the gate of the first NMOS transistor is connected to the first bit line, and the drain of the first NMOS transistor is connected to the The drain of a PMOS transistor is connected; the second NMOS transistor, the gate of the second NMOS transistor is connected to the second bit line, and the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor through the second node; wherein, In the first offset compensation stage of the sense amplifier, the first PMOS transistor and the first NMOS transistor are configured as a first inverter, and the second PMOS transistor and the second NMOS transistor are configured as a second inverter.
  • the control module includes: a first switch, a first end of the first switch is connected to the first node, and a second end of the first switch is connected to the gate of the first PMOS transistor; The first end is connected to the gate of the first PMOS tube, the second end of the second switch is connected to the second node; the third switch, the first end of the third switch is connected to the gate of the second PMOS tube, the third switch The second end of the fourth switch is connected to the first node; the fourth switch, the first end of the fourth switch is connected to the second node, and the second end of the fourth switch is connected to the gate of the second PMOS transistor; the fifth switch, the fifth The first end of the switch is connected to the first bit line, the second end of the fifth switch is connected to the first node; the sixth switch, the first end of the sixth switch is connected to the second bit line, and the second end of the sixth switch is connected to the second node; wherein, in the first offset compensation stage of the sense amplifier, the first switch, the fourth switch, the fifth switch
  • the sources of the first PMOS transistor and the second PMOS transistor receive the first voltage, and the sources of the first NMOS transistor and the second NMOS transistor are grounded.
  • the first switch, the third switch and the sixth switch are closed, and the second switch and the fourth switch are closed. and the fifth switch are disconnected; wherein, when the first switch and the third switch are closed, the first PMOS transistor and the second PMOS transistor are configured as a first current mirror structure.
  • the first switch, the third switch and the sixth switch are turned off, and the second switch, the fourth switch and the fourth switch are turned off.
  • the switch and the fifth switch are closed; wherein, when the second switch and the fourth switch are closed, the first PMOS transistor and the second PMOS transistor are configured as a second current mirror structure.
  • control module in the case of reading the data in the storage unit on the first bit line, in the first amplification stage of the sense amplifier, the control module is configured to configure the amplification module as a third inverter.
  • the second PMOS transistor and the second NMOS transistor are controlled to be in the cut-off region, and the first PMOS transistor and the second NMOS transistor are controlled to be in the cut-off region.
  • the first NMOS transistor is configured as a third inverter.
  • control module is configured to configure the amplification module as a fourth inverter.
  • the first PMOS transistor and the first NMOS transistor are controlled to be in the cut-off region, and the second PMOS transistor and The second NMOS transistor is configured as a fourth inverter.
  • control module further includes: a seventh switch, the first end of the seventh switch is connected to the first line, the second end of the seventh switch is connected to the second node; the eighth switch, the first end of the eighth switch is connected to the second node; The terminal is connected to the second bit line, and the second terminal of the eighth switch is connected to the first node; wherein, in the first offset compensation stage and the second offset compensation stage of the sense amplifier, the seventh switch and the eighth switch are disconnected; In the first amplification stage of the sense amplifier, the first switch, the fourth switch, the fifth switch and the sixth switch are turned off, and the second switch, the third switch, the seventh switch and the eighth switch are turned on.
  • the source of the first PMOS transistor receives the first voltage
  • the source of the first NMOS transistor is grounded
  • the source electrode of the second PMOS transistor and the source electrode of the second NMOS transistor receive a second voltage; wherein the second voltage is lower than the first voltage
  • the source of the second PMOS transistor receives the first voltage, and the source of the second NMOS transistor is grounded,
  • the source electrode of the first PMOS transistor and the source electrode of the first NMOS transistor receive a second voltage; wherein the second voltage is lower than the first voltage.
  • control module is configured to configure the amplification module as a cross-coupled amplification structure.
  • the first switch, the fourth switch, the fifth switch and the sixth switch are turned off, and the second switch, the third switch, the seventh switch and the eighth switch are turned on.
  • the sources of the first PMOS transistor and the second PMOS transistor receive the first voltage, and the sources of the first NMOS transistor and the second NMOS transistor are grounded.
  • the sense amplifier further includes: a precharge module for precharging the first bit line and the second bit line in a precharge stage before the first offset compensation stage of the sense amplifier.
  • a memory including the sense amplifier as described above.
  • a control method for a sense amplifier includes an amplification module and a control module
  • the control method for the sense amplifier includes: in a first offset compensation stage of the sense amplifier, the control module configures the amplification module as Including a first inverter and a second inverter, the first inverter and the second inverter are both inverters connected with input and output; in the second offset compensation stage of the sense amplifier, the control module configures the amplification module to include a current mirror structure.
  • the amplification module is configured to include a first inverter and a second inverter, the first Both the inverter and the second inverter are inverters whose input and output are connected, and in the second offset compensation stage of the sense amplifier, the amplifying module is configured to include a current mirror structure.
  • the voltages of the bit lines on both sides of the sense amplifier can be adjusted, thereby compensating for the effect of offset noise on the voltages of the bit lines on both sides of the sense amplifier, thereby improving the performance of the semiconductor memory.
  • FIG. 1 schematically shows a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure
  • FIG. 2 schematically shows a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure
  • FIG. 3 schematically shows a circuit diagram of a specific configuration of a sense amplifier according to an embodiment of the present disclosure
  • FIG. 5 schematically shows a circuit diagram of a sense amplifier in a precharge stage when reading data in a memory cell on a first bit line according to an embodiment of the present disclosure
  • FIG. 6 schematically shows a circuit diagram of a sense amplifier in a first offset compensation stage when reading data in a memory cell on a first bit line according to an embodiment of the present disclosure
  • FIG. 7 schematically shows a circuit diagram of a sense amplifier in a second offset compensation stage when reading data in a memory cell on the first bit line according to an embodiment of the present disclosure
  • FIG. 8 schematically shows a circuit diagram of a sense amplifier in a first amplification stage when reading data in a memory cell on a first bit line according to an embodiment of the present disclosure
  • FIG. 9 schematically shows a circuit diagram of a sense amplifier in a second amplifying stage when reading data in a memory cell on a first bit line according to an embodiment of the present disclosure
  • FIG. 11 schematically shows a circuit diagram of a sense amplifier in a precharge stage when reading data in a memory cell on the second bit line according to an embodiment of the present disclosure
  • FIG. 12 schematically shows a circuit diagram of a sense amplifier in a first offset compensation stage when reading data in a memory cell on a second bit line according to an embodiment of the present disclosure
  • FIG. 13 schematically shows a circuit diagram of a sense amplifier in a second offset compensation stage when reading data in a memory cell on a second bit line according to an embodiment of the present disclosure
  • FIG. 14 schematically shows a circuit diagram of a sense amplifier in a first amplifying stage when reading data in a memory cell on a second bit line according to an embodiment of the present disclosure
  • FIG. 15 schematically shows a circuit diagram of a sense amplifier in a second amplification stage when reading data in a memory cell on a second bit line according to an embodiment of the present disclosure
  • FIG. 16 schematically shows a flowchart of a control method of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • connection mentioned in the present disclosure may include direct connection and indirect connection.
  • direct connection there are no components between the terminals.
  • the first terminal of switch A is connected to the first terminal of switch B, which can be the connection line between the first terminal of switch A and the first terminal of switch B.
  • wires eg, metal wires
  • the indirect connection other components may exist between the terminals.
  • the first terminal of switch C is connected to the first terminal of switch D, which may be the connection between the first terminal of switch C and the first terminal of switch D.
  • connection line in addition to the connection line, there is at least one other component (eg, switch E, etc.) on the connection line.
  • a sense amplifier includes two symmetrically configured NMOS transistors. Ideally, it is hoped that the performance of the two NMOS transistors is exactly the same. However, in practice, the threshold voltages of the two NMOS transistors may be different, which will result in circuit imbalance. If no measures are taken at this time, when reading data from the storage unit, it is possible to read the originally stored "1" as a "0" error output, or read the originally stored "0" as a "1" error output .
  • the present disclosure provides a new sense amplifier.
  • FIG. 1 schematically shows a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • the sense amplifier 1 may include an amplification module 11 and a control module 12 .
  • the amplifying module 11 can be used to read the data of the storage unit on the first bit line or the second bit line;
  • the control module 12 is electrically connected to the amplification module 11 .
  • control module 12 is configured to configure the amplifying module 11 to include a first inverter and a second inverter, and the first inverter and the second inverter are both connected to input and output the inverter.
  • control module 12 is used to configure the amplification module 11 to include a current mirror structure.
  • the voltages of the bit lines on both sides of the sense amplifier can be adjusted, thereby compensating for the effect of offset noise on the voltages of the bit lines on both sides of the sense amplifier, thereby improving the performance of the semiconductor memory.
  • the offset noise described in the present disclosure refers to the voltage difference generated by the inconsistency between at least two transistors (or components) in the amplifying module 11 .
  • the offset noise refers to the offset noise of the entire amplifying module 11 .
  • the amplifying module 11 may include a first PMOS transistor (hereinafter referred to as transistor P1), a second PMOS transistor (hereinafter referred to as transistor P2), a first NMOS transistor (hereinafter referred to as transistor N1), and a second NMOS transistor (hereinafter referred to as transistor N2).
  • the offset noise may be the offset voltage of the transistor P1 and the transistor P2, the offset voltage of the transistor N1 and the transistor N2, or the combined offset voltage of the two, which is not limited in the present disclosure .
  • FIG. 2 schematically shows a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • the drain of the transistor P1 is connected to the drain of the transistor N1, and the drain of the transistor P2 is connected to the drain of the transistor N2.
  • the gate of the transistor N1 is connected to the first bit line BL, and the gate of the transistor N2 is connected to the second bit line BLB.
  • the first node nL and the second node nR may be defined in the sense amplifier.
  • the drain of the transistor P1 and the drain of the transistor N1 are connected to the first node nL, and the drain of the transistor P2 and the drain of the transistor N2 are connected to the second node nR.
  • the working stage of the sense amplifier of the exemplary embodiment of the present disclosure may be at least divided into: a first offset compensation stage, a second offset compensation stage, a first amplification stage, and a second amplification stage.
  • transistor P1 and transistor N1 are configured as a first inverter, and transistor P2 and transistor N2 are configured as a second inverter.
  • the control module may include a first switch (hereinafter referred to as switch K1), a second switch (hereinafter referred to as switch K2), a third switch (hereinafter referred to as switch K3), a fourth switch (hereinafter referred to as switch K4), a fifth switch The switch (hereinafter referred to as switch K5) and the sixth switch (hereinafter referred to as switch K6).
  • switch K1 a first switch
  • switch K2 hereinafter referred to as switch K2
  • switch K3 a third switch
  • switch K4 hereinafter referred to as switch K4
  • switch K5 a fifth switch
  • switch K6 the sixth switch
  • the first end of the switch K1 is connected to the first node nL, the second end of the switch K1 is connected to the gate of the transistor P1; the first end of the switch K2 is connected to the gate of the transistor P1, and the second end of the switch K2 is connected to the second The node nR is connected; the first end of the switch K3 is connected to the gate of the transistor P2, the second end of the switch K3 is connected to the first node nL; the first end of the switch K4 is connected to the second node nR, and the second end of the switch K4 It is connected to the gate of the transistor P2; the first end of the switch K5 is connected to the first bit line BL, the second end of the switch K5 is connected to the first node nL; the first end of the switch K6 is connected to the second bit line BLB, the switch The second end of K6 is connected to the second node nR.
  • the switch K1, the switch K4, the switch K5 and the switch K6 are closed, and the switch K2 and the switch K3 are opened.
  • the present disclosure does not limit the types of switch K1 , switch K2 , switch K3 , switch K4 and switch K5 .
  • the switch K1 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K2 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K3 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K4 can be a PMOS transistor , NMOS transistor or CMOS transmission gate
  • switch K5 can be PMOS transistor, NMOS transistor or CMOS transmission gate
  • switch K6 can be PMOS transistor, NMOS transistor or CMOS transmission gate.
  • the switch K1 may include a control terminal for controlling the switch state of the switch K1 in response to a first control signal (denoted as a control signal CONAZ); the switch K2 may also include a control terminal for responding to the control signal CONAZ controls the switching state of switch K2. That is to say, both the control terminals of the switch K1 and the switch K2 can receive the control signal CONAZ.
  • the control signals of the switch K1 and the switch K2 may also be different, which is related to the types of the switch K1 and the switch K2, which is not limited in the present disclosure.
  • the switch K3 may include a control terminal for controlling the switch state of the switch K3 in response to the second control signal (referred to as control signal CONAZ1); the switch K4 may also include a control terminal for controlling the switch state of the switch K4 in response to the control signal CONAZ1. That is to say, both the control terminals of the switch K3 and the switch K4 can receive the control signal CONAZ1.
  • the control signals of the switch K3 and the switch K4 may also be different, which is related to the types of the switch K3 and the switch K4, which is not limited in the present disclosure.
  • the switch K5 may include a control terminal for controlling the switch state of the switch K5 in response to the third control signal (denoted as control signal CONCZ1); the switch K6 may also include a control terminal for responding to the fourth control signal (denoted as control signal CONCZ) Control the switch state of switch K6.
  • the source of transistor P1 can receive a fourth control signal (denoted as control signal ACT1)
  • the source of transistor P2 can receive a fifth control signal (denoted as control signal ACT2)
  • the source of transistor N1 can receive a sixth control signal signal (denoted as control signal NLAT1)
  • the source of transistor N2 can receive a seventh control signal (denoted as control signal NLAT2).
  • the sources of the transistor P1 and the transistor P2 are both connected to a first voltage, where the first voltage may be the power supply voltage VCC. That is, at this stage, both the control signal ACT1 and the control signal ACT2 are configured as the first voltage.
  • the sources of the transistor N1 and the transistor N2 are grounded (GND), that is, the voltages received by the control signal NLAT1 and the control signal NLAT2 are zero.
  • whether the data of the memory cell on the first bit line BL or the data of the memory cell on the second bit line BLB is read may be determined based on the least significant bit of the row address. For example, the low level of the lowest bit A0 of the row address is an even address, and a high level is an odd address. It can be specified that the memory cell connected to the first bit line BL is opened by the even address after address decoding, and the memory cell connected to the second bit line BLB is opened by the odd address. It should be noted that the determination of an even address or an odd address is not limited to identification by the lowest bit A0 of the row address, or identification by other bits in the row address, or by performing a specific relationship to at least one bit in the row address. It is not limited in the present disclosure, and can be set by those skilled in the art as needed.
  • the switch K1, the switch K3 and the switch K6 are closed, and the switch K2, the switch K4 and the switch K5 are opened.
  • the transistor P1 and the transistor P2 are configured as a first current mirror structure.
  • the transistor P1 is configured as a diode structure.
  • control module In the case of reading the data in the memory cells on the first bit line BL, in the first amplification stage of the sense amplifier, the control module is used to configure the amplification module as a third inverter.
  • the transistor P2 and the transistor N2 may be controlled to be in the cut-off region, and the transistor P1 and the transistor N1 may be configured as a third inverter.
  • the sense amplifier of the present disclosure may further include a seventh switch (hereinafter referred to as switch K7 ) and an eighth switch (hereinafter referred to as switch K8 ), the first end of switch K7 is connected to the first bit line BL The second end of the switch K7 is connected to the second node nR; the first end of the switch K8 is connected to the second bit line BLB, and the second end of the switch K8 is connected to the first node nL.
  • switch K7 a seventh switch
  • switch K8 hereinafter referred to as switch K8
  • the present disclosure does not limit the types of switch K7 and switch K8.
  • the switch K7 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K8 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate.
  • the switch K7 may include a control terminal for controlling the switch state of the switch K7 in response to an eighth control signal (referred to as a control signal CONBZ); the switch K8 may also include a control terminal for responding to the control signal CONBZ controls the switch state of switch K8. That is to say, both the control terminals of the switch K7 and the switch K8 can receive the control signal CONBZ.
  • the control signals of the switch K7 and the switch K8 may also be different, which is related to the types of the switch K7 and the switch K8, which is not limited in the present disclosure.
  • the switch K7 and the switch K8 are disconnected; in the first amplifying stage of the sense amplifier, the switch K1, the switch K4, the switch K5 and the switch K6 are disconnected, and the switches K2, Switch K3, switch K7 and switch K8 are closed.
  • the source of the transistor P1 receives the first voltage; the source of the transistor N1 is grounded; the sources of the transistors P2 and N2 The terminal receives a second voltage that causes transistors P2 and N2 to be in the cut-off region, wherein the second voltage is less than the first voltage.
  • the second voltage may be VCC/2.
  • the switch K1 and the transistor P2 are configured as a second current mirror structure.
  • the transistor P2 is configured as a diode structure.
  • control module In the case of reading the data in the memory cells on the second bit line BLB, in the first amplification stage of the sense amplifier, the control module is configured to configure the amplification module as a fourth inverter.
  • the transistor P1 and the transistor N1 may be controlled to be in the cut-off region, and the transistor P2 and the transistor N2 may be configured as a fourth inverter.
  • the circuit configuration of the first amplification stage is realized in combination with the way of configuring the switch K7 and the switch K8.
  • the source of transistor P2 receives the first voltage; the source of transistor N2 is grounded; the sources of transistor P1 and transistor N1 The pole receives the above-mentioned second voltage.
  • control module is further configured to configure the amplification module as a cross-coupled amplification structure.
  • the switch K1, the switch K4, the switch K5 and the switch K6 are turned off, and the switch K2, the switch K3, the switch K7 and the switch K8 are turned on.
  • the sources of the transistor P1 and the transistor P2 receive the first voltage, that is, the control signal ACT1 and the control signal ACT2 are VCC.
  • the sources of transistor N1 and transistor N2 are grounded, that is, control signal NLAT1 and control signal NLAT2 are zero.
  • the operation stage of the sense amplifier may further include a precharge stage to precharge the first bit line BL and the second bit line BLB.
  • switch K1 and switch K4 are closed, and switch K2, switch K3, switch K5, switch K6, switch K7 and switch K8 are open.
  • the sources of transistor P1, transistor P2, transistor N1 and transistor N2 all receive the second voltage.
  • switch K2, switch K3, switch K5, switch K6, switch K7, switch K8 may be in a closed state.
  • the switch K1 and the switch K4 may also be in an off state, which is not limited in the present disclosure.
  • FIG. 3 schematically shows a circuit diagram of a sense amplifier according to an embodiment of the present disclosure.
  • the switch K1 is configured as a transistor P3, and the switch state is controlled in response to the control signal CONAZ;
  • the switch K2 is configured as a transistor N3, and the switch state is controlled in response to the control signal CONAZ;
  • the switch K3 is configured as a transistor N4, which controls the switch state in response to the control signal CONAZ1;
  • the switch K4 is configured as a transistor P4, which controls the switch state in response to the control signal CONAZ1;
  • the switch K5 is configured as a transistor N5, which controls the switch state in response to the control signal CONCZ1;
  • the switch K6 is configured as The transistor N6 controls the switch state in response to the control signal CONCZ;
  • the switch K7 is configured as a transistor N7 and controls the switch state in response to the control signal CONBZ;
  • the switch K8 is configured as the transistor N8 and controls the switch state in response to the control signal CONBZ.
  • the pre-charge module may include transistor N9, transistor N10, and transistor N11.
  • the gates of transistor N9, transistor N10 and transistor N11 may each receive a precharge control signal BLP.
  • the source of the transistor N9 is connected to the second bit line BLB, the drain of the transistor N9 is connected to the first bit line BL; the source of the transistor N10 is connected to the first bit line BL, and the drain of the transistor N10 is connected to the source of the transistor N11 connected to the precharge voltage Veq, wherein the precharge voltage Veq can be configured as VCC/2; the drain of the transistor N11 is connected to the second bit line BLB.
  • the memory cell corresponding to the first bit line BL is configured to include a transistor N12 and a capacitor C1, and the transistor N12 controls the switch state in response to the word line control signal WL;
  • the memory cell corresponding to the second bit line BLB is configured to include a transistor N13 and a capacitor C2, the transistor N13 controls the switch state in response to the word line control signal WLB.
  • FIG. 4 schematically shows a timing diagram of each control signal involved in the sense amplifier when reading data in the memory cells on the first bit line BL according to an embodiment of the present disclosure.
  • FIG. 5 is for the precharge stage of the sense amplifier when reading the data in the memory cells on the first bit line BL.
  • the voltages of the precharge control signal BLP, control signal ACT1, control signal ACT2, control signal NLAT1, and control signal NLAT2 can be respectively VCC , Veq, Veq, Veq, Veq.
  • the transistor N9, the transistor N10, and the transistor N11 are turned on (corresponding to the closed state of the switch).
  • the first bit line BL and the second bit line BLB are connected to the precharge voltage through the transistor N10 and the transistor N11, respectively. Veq, and are connected to each other through transistor N9, so that the first bit line BL and the second bit line BLB are precharged to Veq.
  • FIG. 6 is directed to the first offset compensation stage of the sense amplifier when reading data in the memory cells on the first bit line BL.
  • the voltages of control signal ACT1, control signal NLAT1, control signal ACT2, control signal NLAT2, control signal CONAZ, control signal CONAZ1, control signal CONCZ1, control signal CONCZ, control signal CONBZ are VCC, 0 (connected to GND), VCC, 0 , 0, 0, VCC, VCC, 0.
  • the transistor P3, the transistor P4, the transistor N5 and the transistor N6 are turned on, and the transistor N3, the transistor N4, the transistor N7 and the transistor N8 are turned off (corresponding to the off state of the switches).
  • the transistor P1 and the transistor N1 are configured as a first inverter whose input and output are connected, and the transistor P2 and the transistor N2 are configured as a second inverter whose input and output are connected.
  • the voltage across the bit line can be stabilized to the inversion point of the inverter.
  • FIG. 7 is directed to the second offset compensation stage of the sense amplifier when reading data in the memory cells on the first bit line BL.
  • the voltages of control signal ACT1, control signal NLAT1, control signal ACT2, control signal NLAT2, control signal CONAZ, control signal CONAZ1, control signal CONCZ1, control signal CONCZ, control signal CONBZ are VCC, 0, VCC, 0, 0, VCC respectively , 0, VCC, 0.
  • the transistor P3, the transistor N4 and the transistor N6 are turned on, and the transistor N3, the transistor P4, the transistor N5, the transistor N7 and the transistor N8 are turned off.
  • the transistor P1 and the transistor P2 form a first current mirror structure in which the transistor P1 is configured as a diode structure. Therefore, the currents on the branch formed by the transistor P1 and the transistor N1 and the branch formed by the transistor P2 and the transistor N2 are made equal, so as to realize the compensation of the voltage difference on the first bit line BL and the second bit line BLB.
  • FIG. 8 is for the first amplification stage of the sense amplifier when reading data in the memory cells on the first bit line BL, control signal ACT1, control signal NLAT1, control signal ACT2, control signal NLAT2, control signal CONAZ, control signal CONAZ1, control signal
  • the voltages of CONCZ1, control signal CONCZ, and control signal CONBZ are VCC, 0, Veq, Veq, VCC, VCC, 0, 0, and VCC, respectively.
  • the transistor N3, the transistor N4, the transistor N7, and the transistor N8 are turned on, and the transistor P3, the transistor P4, the transistor N5, and the transistor N6 are turned off.
  • the transistor P1 and the transistor N1 form an inverter
  • the input terminal of the inverter is the first bit line BL
  • the output terminal is the second bit line BLB.
  • the voltages of the control signal ACT2 and the control signal NLAT2 are both Veq(VCC/2)
  • the transistor P2 and the transistor N2 are in the off region, that is, the transistor P2 and the transistor N2 do not work.
  • the word line control signal WL is at a high level, and the voltage of the first bit line BL is lower than the voltage of the second bit line BLB, that is, by the transistor P1 and the transistor
  • the input of the inverter composed of N1 is low level. Due to the action of the inverter, the voltage of the output terminal of the inverter is continuously increased in the first amplification stage, that is, the voltage of the second bit line BLB is continuously increased.
  • the word line control signal WL is at a high level, and the voltage of the first bit line BL is higher than the voltage of the second bit line BLB, that is, by the transistor P1 and the transistor
  • the input of the inverter composed of N1 is at a high level. Due to the action of the inverter, the voltage of the output terminal of the inverter is continuously reduced in the first amplification stage, that is, the voltage of the second bit line BLB is continuously reduced.
  • the voltage difference between the first bit line BL and the second bit line BLB will be greatly increased, which is helpful to further amplify the voltage difference between the two.
  • FIG. 9 is directed to the second amplification stage of the sense amplifier when reading data in the memory cells on the first bit line BL. Similar to the circuit connection state of the first amplification stage, the difference is that the voltages of the control signal ACT2 and the control signal NLAT2 are configured as VCC and 0, respectively.
  • the transistor N2 and the transistor N7 are turned on, which can turn the first bit line BL
  • the voltage on bit line BL is discharged to ground through transistor N2.
  • transistor P1 is turned on, raising the voltage on the second bit line BLB to VCC.
  • the sense amplifier reads 1 for the memory cell of the first bit line BL
  • the voltage on the first bit line BL is higher than the voltage on the second bit line BLB
  • the transistor N1 and the transistor N8 are turned on, and the second bit line
  • the voltage on line BLB is discharged to ground through transistor N1.
  • transistor P2 is turned on, raising the voltage on first bit line BL to VCC.
  • a transition phase may also be included between the second offset compensation phase and the first amplification phase.
  • the word line is in an open state
  • the control signal CONBZ is in a low state
  • transistors N7 and N8 are in an off state. , which is beneficial to fully share the charge in the memory cell to the first bit line or the second bit line after the word line is turned on.
  • it is not limited to this, and can be set according to needs.
  • FIG. 10 schematically shows a timing diagram of various control signals involved in the sense amplifier when reading data in the memory cells on the second bit line BLB according to an embodiment of the present disclosure.
  • FIG. 11 is directed to the precharge phase of the sense amplifier when reading data in the memory cells on the second bit line BLB.
  • the precharging process is the same as the process described in FIG. 5 above, and is not repeated here.
  • FIG. 12 is directed to the first offset compensation stage of the sense amplifier when reading data in the memory cells on the second bit line BL. The process is the same as that described above in FIG. 6 , and will not be repeated here.
  • control signal ACT1, control signal NLAT1, control signal ACT2, control signal NLAT2, control signal CONAZ, control signal CONAZ1, control signal CONCZ1, control signal CONCZ, control signal CONBZ are VCC, 0, VCC, 0, VCC, 0 respectively , VCC, 0, 0.
  • the transistor N3, the transistor P4 and the transistor N5 are turned on, and the transistor P3, the transistor N4, the transistor N6, the transistor N7 and the transistor N8 are turned off.
  • the transistor P1 and the transistor P2 form a second current mirror structure in which the transistor P2 is configured as a diode structure. Therefore, the currents on the branch formed by the transistor P1 and the transistor N1 and the branch formed by the transistor P2 and the transistor N2 are made equal, thereby realizing the compensation of the voltage difference on the first bit line BL and the second bit line BLB.
  • FIG. 14 is for the first amplification stage of the sense amplifier when reading data in the memory cells on the second bit line BL, control signal ACT1, control signal NLAT1, control signal ACT2, control signal NLAT2, control signal CONAZ, control signal CONAZ1, control signal
  • the voltages of CONCZ1, control signal CONCZ, and control signal CONBZ are Veq, Veq, VCC, 0, VCC, VCC, 0, 0, and VCC, respectively.
  • the transistor N3, the transistor N4, the transistor N7, and the transistor N8 are turned on, and the transistor P3, the transistor P4, the transistor N5, and the transistor N6 are turned off.
  • the transistor P2 and the transistor N2 form an inverter
  • the input terminal of the inverter is the second bit line BLB
  • the output terminal is the first bit line BL.
  • the voltages of the control signal ACT1 and the control signal NLAT1 are both Veq(VCC/2)
  • the transistor P1 and the transistor N1 are in the off region, that is, the transistor P1 and the transistor N1 do not work.
  • the word line control signal WLB is at a high level, and the voltage of the second bit line BLB is lower than the voltage of the first bit line BL, that is, the transistor P2 and the transistor
  • the input of the inverter composed of N2 is low level. Due to the action of the inverter, the voltage of the output terminal of the inverter is continuously increased in the first amplification stage, that is, the voltage of the first bit line BL is continuously increased.
  • the word line control signal WLB is at a high level, and the voltage of the second bit line BLB is higher than the voltage of the first bit line BL, that is, the transistor P2 and the transistor
  • the input of the inverter composed of N2 is a high level. Due to the action of the inverter, the voltage at the output terminal of the inverter is continuously reduced in the first amplification stage, that is, the voltage of the first bit line BL is continuously reduced.
  • the voltage difference between the first bit line BL and the second bit line BLB will be greatly increased, which is helpful to further amplify the voltage difference between the two.
  • FIG. 15 is directed to the second amplification stage of the sense amplifier when reading data in the memory cells on the second bit line BL.
  • the second enlargement stage of FIG. 15 is the same as the process of FIG. 9 described above, and will not be repeated here.
  • a transition phase may also be included between the second offset compensation phase and the first amplification phase.
  • the word line is in an open state
  • the control signal CONBZ is in a low state
  • transistors N7 and N8 are in an off state. , which is beneficial to fully share the charge in the memory cell to the first bit line or the second bit line after the word line is turned on.
  • it is not limited to this, and can be set according to needs.
  • the present disclosure also provides a control method for a sense amplifier.
  • FIG. 16 schematically shows a flowchart of a control method of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • the sense amplifier may include an amplification module and a control module.
  • control method of the sense amplifier may include the following steps:
  • the control module configures the amplifying module to include a first inverter and a second inverter, and the first inverter and the second inverter are both inverters whose input and output are connected phase device;
  • control module configures the amplification module to include a current mirror structure.
  • the control module in the case of reading the data in the memory cell on the first bit line, in the first amplification stage of the sense amplifier, the control module is used to configure the amplification module as a third inverter; In the case of taking the data in the storage unit on the second bit line, in the first amplification stage of the sense amplifier, the control module is used to configure the amplification module as a fourth inverter.
  • the amplification module in the second amplification stage after the first amplification stage of the sense amplifier, is configured as a cross-coupled amplification structure by the control module.
  • the sense amplifier may also include a pre-charge stage. It should be understood, however, that a priming phase is not necessary for the approach described in this disclosure.
  • the voltages of the bit lines on both sides of the sense amplifier can be adjusted respectively according to the difference between the data on the first bit line and the data on the second bit line, so as to compensate for the offset noise The impact on the bit line voltage on both sides of the sense amplifier, thereby improving the performance of the semiconductor memory.
  • the present disclosure also provides a memory including the above-mentioned sense amplifier.
  • the memory according to the exemplary embodiment of the present disclosure better realizes offset compensation and has a low read error rate, the memory performance is greatly improved.

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Abstract

一种灵敏放大器、存储器和灵敏放大器的控制方法，涉及半导体存储器技术领域。灵敏放大器（1）包括：放大模块（11），用于读取存储单元的数据；控制模块（12），与放大模块（11）电连接；其中，在灵敏放大器（1）的第一失调补偿阶段，控制模块（12）用于将放大模块（11）配置为包括第一反相器和第二反相器，第一反相器和第二反相器均为输入输出相连的反相器；在灵敏放大器（1）的第二失调补偿阶段，控制模块（12）用于将放大模块（11）配置为包括电流镜结构。该结构可以实现灵敏放大器（1）的失调补偿，进而提高半导体存储器的性能。

Description

灵敏放大器、存储器和灵敏放大器的控制方法
相关申请的交叉引用
本申请要求于2020年09月01日提交的申请号为202010902476.X、名称为“灵敏放大器、存储器和灵敏放大器的控制方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体存储器技术领域，具体而言，涉及一种灵敏放大器、存储器和灵敏放大器的控制方法。
背景技术
随着手机、平板、个人计算机等电子设备的普及，半导体存储器技术也得到了快速的发展。例如DRAM(Dynamic Random Access Memory，动态随机存取存储器)、SRAM(Static Random-Access Memory，静态随机存取存储器)的存储器由于高密度、低功耗、低价格等优点，已广泛应用于各种电子设备中。
在DRAM中，不同存储单元阵列中的每一个位线都成对地连接到具有一个位线BL(读取位线)输入端和一个位线BLB(参考位线)输入端的灵敏放大器中。在读取操作(或刷新操作)中，灵敏放大器的作用就是读取位线BL和参考位线BLB之间的电压差，并放大两个位线间的电压差。
灵敏放大器中包括金属-氧化物半导体场效应晶体管(MOSFET)，然而，在半导体技术中，由于工艺和温度的变化，理论上相同的两个MOSFET可能失配，即具有不同的特性，使灵敏放大器产生失调噪声，而失调噪声会严重影响半导体存储器的性能。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种灵敏放大器、存储器和灵敏放大器的控制方法，进而至少在一定程度上克服由于灵敏放大器中晶体管的失配而影响半导体存储器性能的问题。
根据本公开的第一方面，提供一种灵敏放大器，包括：放大模块；用于存储单元的数据；控制模块，与放大模块电连接；其中，在灵敏放大器的第一失调补偿阶段，控制模块用于将放大模块配置为包括第一反相器和第二反相器，第一反相器和第二反相器均为输入输出相连的反相器；在灵敏放大器的第二失调补偿阶段，控制模块用于将放大模块配置为包括电流镜结构。
可选地，放大模块包括：第一PMOS管；第二PMOS管；第一NMOS管，第一NMOS 管的栅极与第一位线连接，第一NMOS管的漏极通过第一节点与第一PMOS管的漏极连接；第二NMOS管，第二NMOS管的栅极与第二位线连接，第二NMOS管的漏极通过第二节点与第二PMOS管的漏极连接；其中，在灵敏放大器的第一失调补偿阶段，第一PMOS管和第一NMOS管被配置为第一反相器，第二PMOS管和第二NMOS管被配置为第二反相器。
可选地，控制模块包括：第一开关，第一开关的第一端与第一节点连接，第一开关的第二端与第一PMOS管的栅极连接；第二开关，第二开关的第一端与第一PMOS管的栅极连接，第二开关的第二端与第二节点连接；第三开关，第三开关的第一端与第二PMOS管的栅极连接，第三开关的第二端与第一节点连接；第四开关，第四开关的第一端与第二节点连接，第四开关的第二端与第二PMOS管的栅极连接；第五开关，第五开关的第一端与第一位线连接，第五开关的第二端与第一节点连接；第六开关，第六开关的第一端与第二位线连接，第六开关的第二端与第二节点连接；其中，在灵敏放大器的第一失调补偿阶段，第一开关、第四开关、第五开关和第六开关闭合，第二开关和第三开关断开。
可选地，在灵敏放大器的第一失调补偿阶段，第一PMOS管和第二PMOS管的源极接收第一电压，第一NMOS管和第二NMOS管的源极接地。
可选地，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第二失调补偿阶段，第一开关、第三开关和第六开关闭合，第二开关、第四开关和第五开关断开；其中，在第一开关和第三开关闭合时，第一PMOS管和第二PMOS管被配置为第一电流镜结构。
可选地，在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第二失调补偿阶段，第一开关、第三开关和第六开关断开，第二开关、第四开关和第五开关闭合；其中，在第二开关和第四开关闭合时，第一PMOS管和第二PMOS管被配置为第二电流镜结构。
可选地，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，控制模块用于将放大模块配置为第三反相器。
可选地，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，第二PMOS管和第二NMOS管被控制为处于截止区，第一PMOS管和第一NMOS管被配置为第三反相器。
可选地，在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，控制模块用于将放大模块配置为第四反相器。
可选地，在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，第一PMOS管和第一NMOS管被控制为处于截止区，第二PMOS管和第二NMOS管被配置为第四反相器。
可选地，控制模块还包括：第七开关，第七开关的第一端与第一位线连接，第七开关的第二端与第二节点连接；第八开关，第八开关的第一端与第二位线连接，第八开关的第二端与第一节点连接；其中，在灵敏放大器的第一失调补偿阶段和第二失调补偿阶段，第七开关和第八开关断开；在灵敏放大器的第一放大阶段，第一开关、第四开关、第五开关 和第六开关断开，第二开关、第三开关、第七开关和第八开关闭合。
可选地，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，第一PMOS管的源极接收第一电压，第一NMOS管的源极接地，第二PMOS管的源极和第二NMOS管的源极接收第二电压；其中，第二电压小于第一电压。
可选地，在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，第二PMOS管的源极接收第一电压，第二NMOS管的源极接地，第一PMOS管的源极和第一NMOS管的源极接收第二电压；其中，第二电压小于第一电压。
可选地，在灵敏放大器的第一放大阶段之后的第二放大阶段，控制模块用于将放大模块配置为交叉耦合放大结构。
可选地，在灵敏放大器的第二放大阶段，第一开关、第四开关、第五开关和第六开关断开，第二开关、第三开关、第七开关和第八开关闭合。
可选地，在灵敏放大器的第二放大阶段，第一PMOS管和第二PMOS管的源极接收第一电压，第一NMOS管和第二NMOS管的源极接地。
可选地，灵敏放大器还包括：预充模块，用于在灵敏放大器的第一失调补偿阶段之前的预充阶段，对第一位线和第二位线进行预充电。
根据本公开的第二方面，提供一种存储器，包括如上述任意一项的灵敏放大器。
根据本公开的第三方面，提供一种灵敏放大器的控制方法，灵敏放大器包括放大模块和控制模块，灵敏放大器的控制方法包括：在灵敏放大器的第一失调补偿阶段，控制模块将放大模块配置为包括第一反相器和第二反相器，第一反相器和第二反相器均为输入输出相连的反相器；在灵敏放大器的第二失调补偿阶段，控制模块将放大模块配置为包括电流镜结构。
在本公开的一些实施例所提供的技术方案中，通过控制模块的控制，在灵敏放大器的第一失调补偿阶段，将放大模块配置为包括第一反相器和第二反相器，第一反相器和第二反相器均为输入输出相连的反相器，并且在灵敏放大器的第二失调补偿阶段，将放大模块配置为包括电流镜结构。基于本公开的电路配置，可以调节灵敏放大器两边位线的电压，从而补偿由于失调噪声给灵敏放大器两边位线电压带来的影响，进而提高半导体存储器的性能。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1示意性示出了根据本公开的示例性实施方式的灵敏放大器的框图；
图2示意性示出了根据本公开的示例性实施方式的灵敏放大器的电路图；
图3示意性示出了根据本公开一实施例的灵敏放大器的具体配置方式的电路图；
图4示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时灵敏放大器中所涉各控制信号的时序图；
图5示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时在预充阶段灵敏放大器的电路图；
图6示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时在第一失调补偿阶段灵敏放大器的电路图；
图7示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时在第二失调补偿阶段灵敏放大器的电路图；
图8示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时在第一放大阶段灵敏放大器的电路图；
图9示意性示出了根据本公开实施例的读取第一位线上存储单元中数据时在第二放大阶段灵敏放大器的电路图；
图10示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时灵敏放大器中所涉各控制信号的时序图；
图11示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时在预充阶段灵敏放大器的电路图；
图12示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时在第一失调补偿阶段灵敏放大器的电路图；
图13示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时在第二失调补偿阶段灵敏放大器的电路图；
图14示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时在第一放大阶段灵敏放大器的电路图；
图15示意性示出了根据本公开实施例的读取第二位线上存储单元中数据时在第二放大阶段灵敏放大器的电路图；
图16示意性示出了根据本公开的示例性实施方式的灵敏放大器的控制方法的流程图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到， 可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。“第一”、“第二”、“第三”、“第四”、“第五”、“第六”、“第七”、“第八”的描述仅是为了区分，不应作为本公开的限制。
需要说明的是，本公开所说的术语“连接”，可以包括直接连接和间接连接。在直接连接中，端与端之间没有元器件，例如，开关A的第一端与开关B的第一端连接，可以是在开关A的第一端与开关B的第一端的连接线路上，只有连接线(如，金属线)，而不存在其他元器件。在间接连接中，端与端之间可以存在其他元器件，例如，开关C的第一端与开关D的第一端连接，可以是在开关C的第一端与开关D的第一端的连接线路上，除连接线外，连接线上还存在至少一个其他元器件(如，开关E等)。
在灵敏放大器中，由于制程上的差异以及工作环境的影响，可能导致晶体管的尺寸、迁移率、阈值电压等存在差别，各晶体管的性能通常不可能完全相同，这就会造成灵敏放大器失调，相当于出现了失调噪声，严重影响存储器读取数据的正确性。
例如，灵敏放大器包括两个对称配置的NMOS管，理想状态下，希望这两个NMOS管的性能完全相同。然而，在实际中，这两个NMOS管的阈值电压可能不同，这就会出现电路失调的情况。此时若不采取任何措施，在从存储单元读取数据时，就有可能将原本存储的“1”读成“0”错误输出，或者将原本存储的“0”读成“1”错误输出。
鉴于此，本公开提供了一种新的灵敏放大器。
图1示意性示出了根据本公开的示例性实施方式的灵敏放大器的框图。如图1所示，灵敏放大器1可以包括放大模块11和控制模块12。
放大模块11可以用于读取第一位线或第二位线上存储单元的数据；
控制模块12与放大模块11电连接。
在灵敏放大器的第一失调补偿阶段，控制模块12用于将放大模块11配置为包括第一反相器和第二反相器，第一反相器和第二反相器均为输入输出相连的反相器。
在灵敏放大器的第二失调补偿阶段，控制模块12用于将放大模块11配置为包括电流镜结构。
基于本公开的电路配置，可以调节灵敏放大器两边位线的电压，从而补偿由于失调噪声给灵敏放大器两边位线电压带来的影响，进而提高半导体存储器的性能。
应当理解的是，本公开所述的失调噪声指的是放大模块11中至少两个晶体管(或元器件)之间的不一致而产生的电压差。在综合所有晶体管(或元器件)之间的电压差的情况下，失调噪声指代整个放大模块11的失调噪声。
放大模块11可以包括第一PMOS管(下面简称晶体管P1)、第二PMOS管(下面简称晶体管P2)、第一NMOS管(下面简称晶体管N1)、第二NMOS管(下面简称晶体管 N2)。
在这种情况下，失调噪声可以是晶体管P1与晶体管P2的失调电压，也可以是晶体管N1与晶体管N2的失调电压，还可以是这二者综合后的失调电压，本公开对此不做限制。
图2示意性示出了根据本公开的示例性实施方式的灵敏放大器的电路图。
参考图2，晶体管P1的漏极与晶体管N1的漏极连接，晶体管P2的漏极与晶体管N2的漏极连接。另外，晶体管N1的栅极与第一位线BL连接，晶体管N2的栅极与第二位线BLB连接。
为了随后描述方便，可以在灵敏放大器中定义第一节点nL和第二节点nR。晶体管P1的漏极与晶体管N1的漏极连接于第一节点nL，晶体管P2的漏极与晶体管N2的漏极连接于第二节点nR。
本公开示例性实施方式的灵敏放大器的工作阶段可以至少被划分为：第一失调补偿阶段、第二失调补偿阶段、第一放大阶段和第二放大阶段。
在灵敏放大器的第一失调补偿阶段，晶体管P1和晶体管N1被配置为第一反相器，晶体管P2和晶体管N2被配置为第二反相器。
本公开示例性实施方式通过控制模块来实现上述配置。参考图2，控制模块可以包括第一开关(下面简称开关K1)、第二开关(下面简称开关K2)、第三开关(下面简称开关K3)、第四开关(下面简称开关K4)、第五开关(下面简称开关K5)和第六开关(下面简称开关K6)。
开关K1的第一端与第一节点nL连接，开关K1的第二端与晶体管P1的栅极连接；开关K2的第一端与晶体管P1的栅极连接，开关K2的第二端与第二节点nR连接；开关K3的第一端与晶体管P2的栅极连接，开关K3的第二端与第一节点nL连接；开关K4的第一端与第二节点nR连接，开关K4的第二端与晶体管P2的栅极连接；开关K5的第一端与第一位线BL连接，开关K5的第二端与第一节点nL连接；开关K6的第一端与第二位线BLB连接，开关K6的第二端与第二节点nR连接。
在灵敏放大器的第一失调补偿阶段，开关K1、开关K4、开关K5和开关K6闭合，开关K2和开关K3断开。
其中，本公开对开关K1、开关K2、开关K3、开关K4和开关K5的类型不做限制。例如，开关K1可以是PMOS管、NMOS管或CMOS传输门；开关K2可以是PMOS管、NMOS管或CMOS传输门；开关K3可以是PMOS管、NMOS管或CMOS传输门；开关K4可以是PMOS管、NMOS管或CMOS传输门；开关K5可以是PMOS管、NMOS管或CMOS传输门；开关K6可以是PMOS管、NMOS管或CMOS传输门。
在本公开的一些实施例中，开关K1可以包括控制端，用于响应第一控制信号(记为控制信号CONAZ)控制开关K1的开关状态；开关K2也可以包括控制端，用于响应控制信号CONAZ控制开关K2的开关状态。也就是说，开关K1与开关K2的控制端均可 以接收控制信号CONAZ。然而，应当理解的是，开关K1与开关K2的控制信号也可以不同，这与开关K1和开关K2的类型有关，本公开对此不做限制。
开关K3可以包括控制端，用于响应第二控制信号(记为控制信号CONAZ1)控制开关K3的开关状态；开关K4也可以包括控制端，用于响应控制信号CONAZ1控制开关K4的开关状态。也就是说，开关K3与开关K4的控制端均可以接收控制信号CONAZ1。然而，应当理解的是，开关K3与开关K4的控制信号也可以不同，这与开关K3和开关K4的类型有关，本公开对此不做限制。
开关K5可以包括控制端，用于响应第三控制信号(记为控制信号CONCZ1)控制开关K5的开关状态；开关K6也可以包括控制端，用于响应第四控制信号(记为控制信号CONCZ)控制开关K6的开关状态。
此外，晶体管P1的源极可以接收第四控制信号(记为控制信号ACT1)，晶体管P2的源极可以接收第五控制信号(记为控制信号ACT2)，晶体管N1的源极可以接收第六控制信号(记为控制信号NLAT1)，晶体管N2的源极可以接收第七控制信号(记为控制信号NLAT2)。
在灵敏放大器的第一失调补偿阶段，晶体管P1和晶体管P2的源极均接第一电压，其中，第一电压可以是电源电压VCC。也就是说，在此阶段，控制信号ACT1和控制信号ACT2均被配置为第一电压。
在此阶段，晶体管N1与晶体管N2的源极接地(GND)，也就是说，控制信号NLAT1和控制信号NLAT2接收的电压是0。
在本公开的示例性实施方式中，可以基于行地址最低位来判断读取的是第一位线BL上存储单元的数据还是第二位线BLB上存储单元的数据。例如，行地址最低位A0低电平为偶地址，高电平为奇地址。可以规定经地址译码后的偶地址打开的是连接在第一位线BL上的存储单元，奇地址打开的是连接在第二位线BLB上的存储单元。需要注意的是，确定偶地址还是奇地址也不限定是通过行地址最低位A0来识别，也可以是通过行地址中其他位来识别，还可以是通过对行地址中至少一位进行特定关系的处理后得出的结果来识别，本公开对此不做限定，本领域内技术人员可根据需要自行设定。
在读取第一位线BL上存储单元中数据的情况下，在灵敏放大器的第二失调补偿阶段，开关K1、开关K3和开关K6闭合，开关K2、开关K4和开关K5断开。在这种情况下，鉴于开关K1和开关K3闭合，晶体管P1和晶体管P2被配置为第一电流镜结构。在第一电流镜结构中，晶体管P1被配置为二极管结构。
在读取第一位线BL上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，控制模块用于将放大模块配置为第三反相器。
在实现上，晶体管P2和晶体管N2可以被控制为处于截止区，晶体管P1和晶体管N1可以被配置为第三反相器。
在这种情况下，参考图2，本公开的灵敏放大器还可以包括第七开关(下面简称开关 K7)和第八开关(下面简称开关K8)，开关K7的第一端与第一位线BL连接，开关K7的第二端与第二节点nR连接；开关K8的第一端与第二位线BLB连接，开关K8的第二端与第一节点nL连接。
类似地，本公开对开关K7和开关K8的类型不做限制。例如，开关K7可以是PMOS管、NMOS管或CMOS传输门；开关K8可以是PMOS管、NMOS管或CMOS传输门。
在本公开的一些实施例中，开关K7可以包括控制端，用于响应第八控制信号(记为控制信号CONBZ)控制开关K7的开关状态；开关K8也可以包括控制端，用于响应控制信号CONBZ控制开关K8的开关状态。也就是说，开关K7与开关K8的控制端均可以接收控制信号CONBZ。然而，应当理解的是，开关K7与开关K8的控制信号也可以不同，这与开关K7与开关K8的类型有关，本公开对此不做限制。
在灵敏放大器的第一失调补偿阶段和第二失调补偿阶段，开关K7和开关K8断开；在灵敏放大器的第一放大阶段，开关K1、开关K4、开关K5和开关K6断开，开关K2、开关K3、开关K7和开关K8闭合。
在读取第一位线BL上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，晶体管P1的源极接收第一电压；晶体管N1的源极接地；晶体管P2和晶体管N2的源极接收第二电压，该第二电压使得晶体管P2和晶体管N2处于截止区，其中，第二电压小于第一电压。在一个实施例中，第二电压可以是VCC/2。
在读取第二位线BLB上存储单元中数据的情况下，在灵敏放大器的第二失调补偿阶段，开关K1、开关K3和开关K6断开，开关K2、开关K4和开关K5闭合。在这种情况下，鉴于开关K2和开关K4闭合，晶体管P1和晶体管P2被配置为第二电流镜结构。在第二电流镜结构中，晶体管P2被配置为二极管结构。
在读取第二位线BLB上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，控制模块用于将放大模块配置为第四反相器。
在实现上，晶体管P1和晶体管N1可以被控制为处于截止区，晶体管P2和晶体管N2可以被配置为第四反相器。
具体的，如上所述，结合配置开关K7和开关K8的方式来实现第一放大阶段的电路配置。
在读取第二位线BLB上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，晶体管P2的源极接收第一电压；晶体管N2的源极接地；晶体管P1和晶体管N1的源极接收上述第二电压。
在灵敏放大器的第一放大阶段之后的第二放大阶段，控制模块还用于将放大模块配置为交叉耦合放大结构。
具体的，在第二放大阶段，开关K1、开关K4、开关K5和开关K6断开，开关K2、开关K3、开关K7和开关K8闭合。并且，晶体管P1和晶体管P2的源极接收第一电压，即控制信号ACT1和控制信号ACT2为VCC。晶体管N1和晶体管N2的源极接地，即控 制信号NLAT1和控制信号NLAT2为0。
另外，在一些实施例中，在第一失调补偿阶段之前，灵敏放大器的工作阶段还可以包括预充阶段，以对第一位线BL和第二位线BLB进行预充电。
在预充阶段，在一个实施例中，开关K1和开关K4闭合，开关K2、开关K3、开关K5、开关K6、开关K7和开关K8断开。另外，晶体管P1、晶体管P2、晶体管N1和晶体管N2的源极均接收第二电压。然而，应当理解的是，在预充阶段，开关K2、开关K3、开关K5、开关K6、开关K7、开关K8中的一个或多个可以处于闭合状态。而开关K1和开关K4也可以处于断开状态，本公开对此不做限制。
图3示意性示出了根据本公开一实施例的灵敏放大器的电路图。
在图3所示的实施例中，开关K1被配置为晶体管P3，响应控制信号CONAZ来控制开关状态；开关K2被配置为晶体管N3，响应控制信号CONAZ来控制开关状态；开关K3被配置为晶体管N4，响应控制信号CONAZ1来控制开关状态；开关K4被配置为晶体管P4，响应控制信号CONAZ1来控制开关状态；开关K5被配置为晶体管N5，响应控制信号CONCZ1来控制开关状态；开关K6被配置为晶体管N6，响应控制信号CONCZ来控制开关状态；开关K7被配置为晶体管N7，响应控制信号CONBZ来控制开关状态；开关K8被配置为晶体管N8，响应控制信号CONBZ来控制开关状态。
在包括预充模块的实施例中，预充模块可以包括晶体管N9、晶体管N10和晶体管N11。
晶体管N9、晶体管N10和晶体管N11的栅极均可以接收预充控制信号BLP。晶体管N9的源极与第二位线BLB连接，晶体管N9的漏极与第一位线BL连接；晶体管N10的源极与第一位线BL连接，晶体管N10的漏极与晶体管N11的源极连接，且连接于预充电压Veq，其中，预充电压Veq可以被配置为VCC/2；晶体管N11的漏极与第二位线BLB连接。
与第一位线BL对应的存储单元被配置为包括晶体管N12和电容C1，晶体管N12响应字线控制信号WL控制开关状态；与第二位线BLB对应的存储单元被配置为包括晶体管N13和电容C2，晶体管N13响应字线控制信号WLB控制开关状态。
下面将分别对读取第一位线BL上数据的过程和读取第二位线BLB上数据的过程进行说明。
图4示意性示出了根据本公开实施例的读取第一位线BL上存储单元中数据时灵敏放大器中所涉各控制信号的时序图。
下面将结合图4的时序图，对本公开实施例的读取第一位线BL上存储单元中数据时灵敏放大器的工作阶段进行说明。
图5针对读取第一位线BL上存储单元中数据时灵敏放大器的预充阶段，预充控制信号BLP、控制信号ACT1、控制信号ACT2、控制信号NLAT1、控制信号NLAT2的电压可以分别为VCC、Veq、Veq、Veq、Veq。对应的，晶体管N9，晶体管N10、晶体管N11 导通(对应开关的闭合状态)，在这种情况下，第一位线BL和第二位线BLB分别通过晶体管N10和晶体管N11连接至预充电压Veq，并通过晶体管N9彼此相连，从而第一位线BL和第二位线BLB被预充至Veq。
图6针对读取第一位线BL上存储单元中数据时灵敏放大器的第一失调补偿阶段。控制信号ACT1、控制信号NLAT1、控制信号ACT2、控制信号NLAT2、控制信号CONAZ、控制信号CONAZ1、控制信号CONCZ1、控制信号CONCZ、控制信号CONBZ的电压分别为VCC、0(接GND)、VCC、0、0、0、VCC、VCC、0。对应的，晶体管P3、晶体管P4、晶体管N5和晶体管N6导通，晶体管N3、晶体管N4、晶体管N7和晶体管N8关断(对应开关的断开状态)。
在这种情况下，晶体管P1和晶体管N1被配置为输入输出相连的第一反相器，晶体管P2和晶体管N2被配置为输入输出相连的第二反相器。由此，使位线两端电压可以稳定到反相器的翻转点。
图7针对读取第一位线BL上存储单元中数据时灵敏放大器的第二失调补偿阶段。控制信号ACT1、控制信号NLAT1、控制信号ACT2、控制信号NLAT2、控制信号CONAZ、控制信号CONAZ1、控制信号CONCZ1、控制信号CONCZ、控制信号CONBZ的电压分别为VCC、0、VCC、0、0、VCC、0、VCC、0。对应的，晶体管P3、晶体管N4和晶体管N6导通，晶体管N3、晶体管P4、晶体管N5、晶体管N7和晶体管N8关断。
在这种情况下，晶体管P1和晶体管P2形成第一电流镜结构，在第一电流镜结构中，晶体管P1被配置为二极管结构。由此，使得晶体管P1和晶体管N1形成的支路与晶体管P2和晶体管N2形成的支路上电流相等，从而实现第一位线BL与第二位线BLB上电压差的补偿。
图8针对读取第一位线BL上存储单元中数据时灵敏放大器的第一放大阶段，控制信号ACT1、控制信号NLAT1、控制信号ACT2、控制信号NLAT2、控制信号CONAZ、控制信号CONAZ1、控制信号CONCZ1、控制信号CONCZ、控制信号CONBZ的电压分别为VCC、0、Veq、Veq、VCC、VCC、0、0、VCC。对应的，晶体管N3、晶体管N4、晶体管N7和晶体管N8导通，晶体管P3、晶体管P4、晶体管N5、晶体管N6关断。
在这种情况下，晶体管P1与晶体管N1构成一个反相器，该反相器的输入端为第一位线BL，输出端为第二位线BLB。另外，鉴于控制信号ACT2、控制信号NLAT2的电压均为Veq(VCC/2)，由此，晶体管P2和晶体管N2处于截止区，也就是说，晶体管P2和晶体管N2不工作。
在灵敏放大器针对第一位线BL的存储单元读0时，字线控制信号WL为高电平，第一位线BL的电压低于第二位线BLB的电压，即，由晶体管P1和晶体管N1组成的反相器的输入为低电平，由于反相器的作用，使得反相器输出端的电压在第一放大阶段不断升高，即第二位线BLB的电压不断升高。
在灵敏放大器针对第一位线BL的存储单元读1时，字线控制信号WL为高电平，第 一位线BL的电压高于第二位线BLB的电压，即，由晶体管P1和晶体管N1组成的反相器的输入为高电平，由于反相器的作用，使得反相器输出端的电压在第一放大阶段不断降低，即第二位线BLB的电压不断降低。
因此，在本公开灵敏放大器的第一放大阶段，第一位线BL与第二位线BLB之间的电压差会大幅度增大，有助于对二者电压差进行进一步放大。
图9针对读取第一位线BL上存储单元中数据时灵敏放大器的第二放大阶段。与第一放大阶段的电路连接状态类似，区别在于，控制信号ACT2和控制信号NLAT2的电压分别被配置为VCC和0。
在灵敏放大器针对第一位线BL的存储单元读0时，第一位线BL上的电压低于第二位线BLB上的电压，此时，晶体管N2和晶体管N7导通，可以将第一位线BL上的电压通过晶体管N2放电至地。另外，晶体管P1导通，将第二位线BLB上的电压升高至VCC。
在灵敏放大器针对第一位线BL的存储单元读1时，第一位线BL上的电压高于第二位线BLB上的电压，此时，晶体管N1和晶体管N8导通，将第二位线BLB上的电压通过晶体管N1放电至地。另外，晶体管P2导通，将第一位线BL上的电压升高至VCC。
由此，通过这种交叉耦合放大结构，可以实现位线从存储单元中读取出来的小电压差放大至全摆幅(0或1)的目的。
需要注意的是，在第二失调补偿阶段与第一放大阶段之间还可以包括过渡阶段，在过渡阶段，字线处于打开状态，控制信号CONBZ处于低状态，晶体管N7和晶体管N8处于断开状态，有利于字线打开后，存储单元中的电荷充分分享至第一位线或第二位线。但也不限定于此，可根据需要自行设置。
图10示意性示出了根据本公开实施例的读取第二位线BLB上存储单元中数据时灵敏放大器中所涉各控制信号的时序图。
下面将结合图10的时序图，对本公开实施例的读取第二位线BLB上存储单元中数据时灵敏放大器的工作阶段进行说明。
图11针对读取第二位线BLB上存储单元中数据时灵敏放大器的预充阶段。预充过程与上面描述图5的过程相同，在此不再赘述。另外，需要说明的是，无论是读取第一位线BL还是读取第二位线BL，都可以不存在预充阶段。
图12针对读取第二位线BL上存储单元中数据时灵敏放大器的第一失调补偿阶段。与上述描述图6的过程相同，在此不再赘述。
图13针对读取第二位线BL上存储单元中数据时灵敏放大器的第二失调补偿阶段。控制信号ACT1、控制信号NLAT1、控制信号ACT2、控制信号NLAT2、控制信号CONAZ、控制信号CONAZ1、控制信号CONCZ1、控制信号CONCZ、控制信号CONBZ的电压分别为VCC、0、VCC、0、VCC、0、VCC、0、0。对应的，晶体管N3、晶体管P4和晶体管N5导通，晶体管P3、晶体管N4、晶体管N6、晶体管N7和晶体管N8关断。
在这种情况下，晶体管P1和晶体管P2形成第二电流镜结构，在第二电流镜结构中， 晶体管P2被配置为二极管结构。由此，使得晶体管P1和晶体管N1形成的支路与晶体管P2和晶体管N2形成的支路上电流相等，从而实现第一位线BL与第二位线BLB上电压差的补偿。
图14针对读取第二位线BL上存储单元中数据时灵敏放大器的第一放大阶段，控制信号ACT1、控制信号NLAT1、控制信号ACT2、控制信号NLAT2、控制信号CONAZ、控制信号CONAZ1、控制信号CONCZ1、控制信号CONCZ、控制信号CONBZ的电压分别为Veq、Veq、VCC、0、VCC、VCC、0、0、VCC。对应的，晶体管N3、晶体管N4、晶体管N7和晶体管N8导通，晶体管P3、晶体管P4、晶体管N5、晶体管N6关断。
在这种情况下，晶体管P2与晶体管N2构成一个反相器，该反相器的输入端为第二位线BLB，输出端为第一位线BL。另外，鉴于控制信号ACT1、控制信号NLAT1的电压均为Veq(VCC/2)，由此，晶体管P1和晶体管N1处于截止区，也就是说，晶体管P1和晶体管N1不工作。
在灵敏放大器针对第二位线BLB的存储单元读0时，字线控制信号WLB为高电平，第二位线BLB的电压低于第一位线BL的电压，即，由晶体管P2和晶体管N2组成的反相器的输入为低电平，由于反相器的作用，使得反相器输出端的电压在第一放大阶段不断升高，即第一位线BL的电压不断升高。
在灵敏放大器针对第二位线BLB的存储单元读1时，字线控制信号WLB为高电平，第二位线BLB的电压高于第一位线BL的电压，即，由晶体管P2和晶体管N2组成的反相器的输入为高电平，由于反相器的作用，使得反相器输出端的电压在第一放大阶段不断降低，即第一位线BL的电压不断降低。
因此，在本公开灵敏放大器的第一放大阶段，第一位线BL与第二位线BLB之间的电压差会大幅度增大，有助于对二者电压差进行进一步放大。
图15针对读取第二位线BL上存储单元中数据时灵敏放大器的第二放大阶段。图15的第二放大阶段与上面描述图9的过程相同，在此不再赘述。
需要注意的是，在第二失调补偿阶段与第一放大阶段之间还可以包括过渡阶段，在过渡阶段，字线处于打开状态，控制信号CONBZ处于低状态，晶体管N7和晶体管N8处于断开状态，有利于字线打开后，存储单元中的电荷充分分享至第一位线或第二位线。但也不限定于此，可根据需要自行设置。
进一步的，本公开还提供了一种灵敏放大器的控制方法。
图16示意性示出了根据本公开的示例性实施方式的灵敏放大器的控制方法的流程图。如上所述，灵敏放大器可以包括放大模块和控制模块。
参考图16，灵敏放大器的控制方法可以包括以下步骤：
S162.在灵敏放大器的第一失调补偿阶段，控制模块将放大模块配置为包括第一反相器和第二反相器，第一反相器和第二反相器均为输入输出相连的反相器；
S164.在灵敏放大器的第二失调补偿阶段，控制模块将放大模块配置为包括电流镜结 构。
根据本公开的示例性实施例，在读取第一位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，利用控制模块将放大模块配置为第三反相器；在读取第二位线上存储单元中数据的情况下，在灵敏放大器的第一放大阶段，利用控制模块将放大模块配置为第四反相器。
根据本公开的示例性实施例，在灵敏放大器的第一放大阶段之后的第二放大阶段，利用控制模块将放大模块配置为交叉耦合放大结构。
在本公开的一些实施例中，灵敏放大器还可以包括预充阶段。然而，应当理解的是，预充阶段并非本公开所述方案所必须的。
这些阶段的细节在上面描述灵敏放大器的配置的过程中均已说明，在此不再赘述。
通过本公开示例性实施方式的灵敏放大器的控制方法，可以根据读取第一位线上数据与第二位线上数据的不同，来分别调节灵敏放大器两边位线的电压，从而补偿由于失调噪声给灵敏放大器两边位线电压带来的影响，进而提高半导体存储器的性能。
进一步的，本公开还提供了一种存储器，该存储器包括上述灵敏放大器。
本公开示例性实施方式的存储器由于较好地实现了失调补偿，读取错误率低，因此，存储器性能得到了较大幅度的提升。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。

Claims (19)

  1. 一种灵敏放大器，包括：
    放大模块，用于读取存储单元的数据；
    控制模块，与所述放大模块电连接；
    其中，在所述灵敏放大器的第一失调补偿阶段，所述控制模块用于将所述放大模块配置为包括第一反相器和第二反相器，所述第一反相器和所述第二反相器均为输入输出相连的反相器；在所述灵敏放大器的第二失调补偿阶段，所述控制模块用于将所述放大模块配置为包括电流镜结构。
  2. 根据权利要求1所述的灵敏放大器，其中，所述放大模块包括：
    第一PMOS管；
    第二PMOS管；
    第一NMOS管，所述第一NMOS管的栅极与第一位线连接，所述第一NMOS管的漏极通过第一节点与所述第一PMOS管的漏极连接；
    第二NMOS管，所述第二NMOS管的栅极与第二位线连接，所述第二NMOS管的漏极通过第二节点与所述第二PMOS管的漏极连接；
    其中，在所述灵敏放大器的第一失调补偿阶段，所述第一PMOS管和所述第一NMOS管被配置为所述第一反相器，所述第二PMOS管和所述第二NMOS管被配置为所述第二反相器。
  3. 根据权利要求2所述的灵敏放大器，其中，所述控制模块包括：
    第一开关，所述第一开关的第一端与所述第一节点连接，所述第一开关的第二端与所述第一PMOS管的栅极连接；
    第二开关，所述第二开关的第一端与所述第一PMOS管的栅极连接，所述第二开关的第二端与所述第二节点连接；
    第三开关，所述第三开关的第一端与所述第二PMOS管的栅极连接，所述第三开关的第二端与所述第一节点连接；
    第四开关，所述第四开关的第一端与所述第二节点连接，所述第四开关的第二端与所述第二PMOS管的栅极连接；
    第五开关，所述第五开关的第一端与所述第一位线连接，所述第五开关的第二端与所述第一节点连接；
    第六开关，所述第六开关的第一端与所述第二位线连接，所述第六开关的第二端与所述第二节点连接；
    其中，在所述灵敏放大器的第一失调补偿阶段，所述第一开关、所述第四开关、所述第五开关和所述第六开关闭合，所述第二开关和所述第三开关断开。
  4. 根据权利要求3所述的灵敏放大器，其中，在所述灵敏放大器的第一失调补偿阶 段，所述第一PMOS管和所述第二PMOS管的源极接收第一电压，所述第一NMOS管和所述第二NMOS管的源极接地。
  5. 根据权利要求4所述的灵敏放大器，其中，在读取所述第一位线上存储单元中数据的情况下，在所述灵敏放大器的第二失调补偿阶段，所述第一开关、所述第三开关和所述第六开关闭合，所述第二开关、所述第四开关和所述第五开关断开；
    其中，在所述第一开关和所述第三开关闭合时，所述第一PMOS管和所述第二PMOS管被配置为第一电流镜结构。
  6. 根据权利要求4所述的灵敏放大器，其中，在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的第二失调补偿阶段，所述第一开关、所述第三开关和所述第六开关断开，所述第二开关、所述第四开关和所述第五开关闭合；
    其中，在所述第二开关和所述第四开关闭合时，所述第一PMOS管和所述第二PMOS管被配置为第二电流镜结构。
  7. 根据权利要求5所述的灵敏放大器，其中，在读取所述第一位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，所述控制模块用于将所述放大模块配置为第三反相器。
  8. 根据权利要求7所述的灵敏放大器，其中，在读取所述第一位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，所述第二PMOS管和所述第二NMOS管被控制为处于截止区，所述第一PMOS管和所述第一NMOS管被配置为第三反相器。
  9. 根据权利要求6所述的灵敏放大器，其中，在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，所述控制模块用于将所述放大模块配置为第四反相器。
  10. 根据权利要求9所述的灵敏放大器，其中，在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，所述第一PMOS管和所述第一NMOS管被控制为处于截止区，所述第二PMOS管和所述第二NMOS管被配置为第四反相器。
  11. 根据权利要求7所述的灵敏放大器，其中，所述控制模块还包括：
    第七开关，所述第七开关的第一端与所述第一位线连接，所述第七开关的第二端与所述第二节点连接；
    第八开关，所述第八开关的第一端与所述第二位线连接，所述第八开关的第二端与所述第一节点连接；
    其中，在所述灵敏放大器的第一失调补偿阶段和第二失调补偿阶段，所述第七开关和所述第八开关断开；在所述灵敏放大器的第一放大阶段，所述第一开关、所述第四开关、所述第五开关和所述第六开关断开，所述第二开关、所述第三开关、所述第七开关和所述第八开关闭合。
  12. 根据权利要求8所述的灵敏放大器，其中，在读取所述第一位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，所述第一PMOS管的源极接收所述第 一电压，所述第一NMOS管的源极接地，所述第二PMOS管的源极和所述第二NMOS管的源极接收第二电压；
    其中，所述第二电压小于所述第一电压。
  13. 根据权利要求10所述的灵敏放大器，其中，在读取所述第二位线上存储单元中数据的情况下，在所述灵敏放大器的第一放大阶段，所述第二PMOS管的源极接收所述第一电压，所述第二NMOS管的源极接地，所述第一PMOS管的源极和所述第一NMOS管的源极接收第二电压；
    其中，所述第二电压小于所述第一电压。
  14. 根据权利要求11所述的灵敏放大器，其中，在所述灵敏放大器的第一放大阶段之后的第二放大阶段，所述控制模块用于将所述放大模块配置为交叉耦合放大结构。
  15. 根据权利要求14所述的灵敏放大器，其中，在所述灵敏放大器的第二放大阶段，所述第一开关、所述第四开关、所述第五开关和所述第六开关断开，所述第二开关、所述第三开关、所述第七开关和所述第八开关闭合。
  16. 根据权利要求15所述的灵敏放大器，其中，在所述灵敏放大器的第二放大阶段，所述第一PMOS管和所述第二PMOS管的源极接收所述第一电压，所述第一NMOS管和所述第二NMOS管的源极接地。
  17. 根据权利要求16所述的灵敏放大器，其中，所述灵敏放大器还包括：
    预充模块，用于在所述灵敏放大器的第一失调补偿阶段之前的预充阶段，对所述第一位线和所述第二位线进行预充电。
  18. 一种存储器，包括如权利要求1所述的灵敏放大器。
  19. 一种灵敏放大器的控制方法，所述灵敏放大器包括放大模块和控制模块，所述灵敏放大器的控制方法包括：
    在所述灵敏放大器的第一失调补偿阶段，所述控制模块将所述放大模块配置为包括第一反相器和第二反相器，所述第一反相器和所述第二反相器均为输入输出相连的反相器；
    在所述灵敏放大器的第二失调补偿阶段，所述控制模块将所述放大模块配置为包括电流镜结构。
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