WO2022021773A1 - 灵敏放大器、存储器和灵敏放大器的控制方法 - Google Patents

灵敏放大器、存储器和灵敏放大器的控制方法 Download PDF

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Publication number
WO2022021773A1
WO2022021773A1 PCT/CN2020/139365 CN2020139365W WO2022021773A1 WO 2022021773 A1 WO2022021773 A1 WO 2022021773A1 CN 2020139365 W CN2020139365 W CN 2020139365W WO 2022021773 A1 WO2022021773 A1 WO 2022021773A1
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WIPO (PCT)
Prior art keywords
switch
sense amplifier
transistor
offset
bit line
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PCT/CN2020/139365
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English (en)
French (fr)
Inventor
彭春雨
赵阳扩
卢文娟
吴秀龙
蔺智挺
陈军宁
李新
季汝敏
何军
应战
Original Assignee
安徽大学
长鑫存储技术有限公司
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Priority to US17/441,780 priority Critical patent/US11894047B2/en
Publication of WO2022021773A1 publication Critical patent/WO2022021773A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the present disclosure relates to the technical field of semiconductor memory, and in particular, to a sense amplifier, a memory and a control method of the sense amplifier.
  • DRAM Dynamic Random Access Memory, dynamic random access memory
  • SRAM Static Random-Access Memory, static random access memory
  • SA Sense Amplifier
  • the purpose of the present disclosure is to provide a sense amplifier, a memory and a control method for the sense amplifier, thereby at least to a certain extent overcome the problem that the performance of semiconductor memory is affected by the mismatch of transistors in the sense amplifier.
  • a sense amplifier comprising: an amplifying module; an offset voltage storage unit electrically connected to the amplifying module; wherein, in an offset cancellation stage of the sense amplifier, the sense amplifier is configured to include a current mirror structure to store the offset voltage of the amplifying module in the offset voltage storage unit.
  • the amplifying module includes: a first PMOS tube; a second PMOS tube, the source of the second PMOS tube is connected to the source of the first PMOS tube; the first NMOS tube, the drain of the first NMOS tube is connected to the first PMOS tube.
  • the drain of the PMOS transistor is connected to the first end of the offset voltage storage unit, the gate of the first NMOS transistor is connected to the gate of the first PMOS transistor; the drain of the second NMOS transistor, the drain of the second NMOS transistor is connected to the second PMOS transistor
  • the drain of the tube is connected, the source of the second NMOS tube is connected to the source of the first NMOS tube, and the gate of the second NMOS tube is connected to the second end of the offset voltage storage unit; the offset voltage storage unit, The first end of the offset voltage storage unit is connected to the drain of the first NMOS transistor, and the second end of the offset voltage storage unit is connected to the gate of the second NMOS transistor; wherein, in the offset elimination stage of the sense amplifier
  • the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected to the first node, and the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to the second node;
  • the sense amplifier further includes : the first switch, the first end of the first switch is connected to the first node, the second end of the first switch is connected to the gate of the first NMOS transistor; the second switch, the first end of the second switch is connected to the second node connection, the second end of the second switch is connected to the gate of the second NMOS tube; for the third switch, the first end of the third switch is connected to the gate of the first PMOS tube, and the second end of the third switch is connected to the second The gate of the PMOS transistor is connected; wherein, in the offset elimination stage of the sense amplifier, the first switch, the second switch and the third switch are all in a closed state.
  • the sense amplifier further includes: a pull-up unit for controlling the connection state between the source electrode of the first PMOS transistor and the power supply voltage in response to the pull-up control signal; a pull-down unit for controlling the first NMOS in response to the pull-down control signal Whether the source of the tube is grounded; wherein, in the offset cancellation stage of the sense amplifier, the source of the first PMOS tube is connected to the power supply voltage, and the source of the first NMOS tube is grounded.
  • the first switch further includes a control terminal for controlling the switch state of the first switch in response to the first control signal; the second switch further includes a control terminal for controlling the switch state of the second switch in response to the second control signal; The third switch further includes a control terminal for controlling the switching state of the third switch in response to the second control signal.
  • the sense amplifier further includes: a fourth switch, the first end of the fourth switch is connected to the gate of the first NMOS transistor, the second end of the fourth switch is connected to the second node; the fifth switch, the fifth switch The first end of the switch is connected to the gate of the second PMOS tube, and the second end of the fifth switch is connected to the gate of the second NMOS tube; wherein, in the offset elimination stage of the sense amplifier, the fourth switch and the fifth switch are both disconnect.
  • the fourth switch further includes a control terminal for controlling the switch state of the fourth switch in response to the third control signal; the fifth switch further includes a control terminal for controlling the switch state of the fifth switch in response to the third control signal.
  • the sense amplifier further includes: a sixth switch, a first end of the sixth switch is connected to the first line, and a second end of the sixth switch is connected to the first node; a seventh switch, the first end of the seventh switch The terminal is connected to the second bit line, and the second terminal of the seventh switch is connected to the second node; wherein, in the offset elimination stage of the sense amplifier, both the sixth switch and the seventh switch are turned off.
  • the sixth switch further includes a control terminal for controlling the switch state of the sixth switch in response to the fourth control signal; the seventh switch further includes a control terminal for controlling the switch state of the seventh switch in response to the fourth control signal.
  • the memory cell corresponding to the first bit line or the memory cell corresponding to the second bit line is turned on, the first switch is turned off, and the second switch and the third switch are turned off , the source of the first PMOS transistor is disconnected from the power supply voltage, the source of the first NMOS transistor is disconnected from the ground, the fourth switch and the fifth switch are closed, and the sixth switch and the seventh switch are closed to connect the first line The voltage difference with the second bit line is input to the sense amplifier.
  • the source of the first PMOS transistor is connected to the power supply voltage, and the source of the first NMOS transistor is grounded, so as to The voltage difference is amplified.
  • the sense amplifier further includes: a precharge unit configured to precharge the first bit line and the second bit line when the sense amplifier is in a precharge phase.
  • the priming phase and the offset cancellation phase are configured to be performed concurrently.
  • a memory including any one of the above-mentioned sense amplifiers.
  • a control method of a sense amplifier includes an amplification module and an offset voltage storage unit, and the control method of the sense amplifier includes: in an offset elimination stage of the sense amplifier, the sense amplifier is It is configured to include a current mirror structure to control the offset voltage of the amplifying module to be stored in the offset voltage storage unit to realize offset compensation.
  • control method of the sense amplifier further includes: in the voltage sensing stage of the sense amplifier, generating a voltage based on the storage data read from the memory cell corresponding to the first bit line or the memory cell corresponding to the second bit line. Difference.
  • the working stage of the sense amplifier further includes a voltage difference amplification stage; wherein, the control method of the sense amplifier further includes: in the voltage difference amplification stage of the sense amplifier, amplifying the voltage difference, and storing the voltage difference based on the offset voltage in the storage unit.
  • the offset voltage of the amplifier module prevents the voltage difference from being erroneously amplified due to the inconsistency of at least two transistors in the amplifying module.
  • the transistors in the sense amplifier at least include a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a second PMOS transistor.
  • the working stage of the sense amplifier further includes a precharge stage; wherein, the control method of the sense amplifier further includes: in the precharge stage of the sense amplifier, precharging the first bit line and the second bit line.
  • control method for the sense amplifier further includes: when the sense amplifier is in the offset cancellation phase, controlling to perform a precharge operation in the precharge phase.
  • the offset voltage storage unit in the sense amplifier in the offset elimination stage of the sense amplifier, the offset voltage of the amplifying module in the sense amplifier can be stored in the sense amplifier. offset voltage in the memory cell. Therefore, when the bit line data needs to be read, the offset compensation of the sense amplifier can be realized by means of the offset voltage stored in the offset voltage storage unit, which greatly reduces the offset voltage caused by the mismatch of the transistors. The impact on the read bit line data, thereby improving the performance of the semiconductor memory.
  • FIG. 1 schematically shows a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure
  • FIG. 2 schematically shows a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure
  • FIG. 3 schematically shows a circuit diagram of a specific configuration of a sense amplifier according to an embodiment of the present disclosure
  • FIG. 4 schematically shows a timing diagram of each control signal involved in the sense amplifier according to an embodiment of the present disclosure
  • FIG. 5 schematically shows a circuit diagram of a sense amplifier in an offset cancellation stage according to an embodiment of the present disclosure
  • FIG. 6 schematically shows a circuit diagram of a sense amplifier in a voltage sensing stage according to an embodiment of the present disclosure
  • FIG. 7 schematically shows an equivalent circuit diagram of a sense amplifier in a voltage difference amplification stage according to an embodiment of the present disclosure
  • FIG. 8 schematically shows a timing diagram of each control signal involved in a sense amplifier according to another embodiment of the present disclosure
  • FIG. 9 schematically shows a circuit diagram of a sense amplifier in a voltage balancing stage according to an embodiment of the present disclosure
  • FIG. 10 schematically shows a flowchart of a control method of a sense amplifier according to an exemplary embodiment of the present disclosure
  • FIG. 11 shows a comparison graph of the offset voltage simulation results of the sense amplifier of an exemplary embodiment of the present disclosure and the sense amplifier of some technologies
  • FIG. 12 shows a graph comparing the read time of the sense amplifier of an exemplary embodiment of the present disclosure and the sense amplifier of some technologies
  • FIG. 13 shows a graph comparing the average power consumption of a sense amplifier of an exemplary embodiment of the present disclosure and a sense amplifier of some technologies.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • connection mentioned in the present disclosure may include direct connection and indirect connection.
  • direct connection there are no components between the terminals.
  • the first terminal of switch A is connected to the first terminal of switch B, which can be the connection line between the first terminal of switch A and the first terminal of switch B.
  • wires eg, metal wires
  • the indirect connection other components may exist between the terminals.
  • the first terminal of switch C is connected to the first terminal of switch D, which may be the connection between the first terminal of switch C and the first terminal of switch D.
  • connection line in addition to the connection line, there is at least one other component (eg, switch E, etc.) on the connection line.
  • a sense amplifier includes two symmetrically configured NMOS transistors. Ideally, it is hoped that the performance of the two NMOS transistors is exactly the same. However, in practice, the threshold voltages of the two NMOS transistors may be different, which will result in circuit imbalance. If no measures are taken at this time, when reading data from the storage unit, it is possible to read the originally stored "1" as a "0" error output, or read the originally stored "0" as a "1" error output .
  • an offset cancellation sense amplifier (Offset-Cancellation Sense Amplifier, OCSA) is provided, and the sensing margin is improved by offset cancellation.
  • This scheme needs to configure an offset compensation stage before reading data, and the reading speed is slow.
  • this kind of sense amplifier will use the bit line capacitance for adjustment, and the bit line capacitance is usually large, and the power consumption is relatively large in the process of adjustment.
  • the present disclosure provides a new sense amplifier.
  • FIG. 1 schematically shows a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • the sense amplifier 1 may include an amplification module 10 and an offset voltage storage unit 11 .
  • the amplifying module 10 is used to read the data of the storage unit on the first bit line or the second bit line;
  • the offset voltage storage unit 11 is electrically connected to the amplification module 10 .
  • the sense amplifier 1 is configured to include a current mirror structure to store the offset voltage of the amplifying module 10 in the offset voltage storage unit 11 .
  • the offset voltage of the amplifying module 10 may refer to the offset voltage between various components included in the amplifying module 10 . That is to say, the offset voltage of the amplifying module 10 may represent a voltage difference caused by inconsistency between at least two components in the amplifying module 10 . In the case of synthesizing the voltage differences between all components, the offset voltage refers to the offset voltage of the entire amplifying module 10 .
  • the amplifying module 10 may include a first PMOS transistor (hereinafter referred to as transistor P1), a second PMOS transistor (hereinafter referred to as transistor P2), a first NMOS transistor (hereinafter referred to as transistor N1), and a second NMOS transistor (hereinafter referred to as transistor N2).
  • the offset voltage storage unit may be configured as a capacitor.
  • any device or unit with a voltage storage function can be used as the offset voltage storage unit described in the present disclosure, and the present disclosure does not limit the configuration form of the offset voltage storage unit.
  • FIG. 2 schematically shows a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • a first node nL may be defined in the sense amplifier, and the drain of the transistor P1 and the drain of the transistor N1 are connected to the first node nL.
  • the drain of the transistor N2 is connected to the drain of the transistor P2, and the source of the transistor N2 is connected to the source of the transistor N1.
  • a second node nR may be defined in the sense amplifier, and the drain of the transistor N2 and the drain of the transistor P2 are connected to the second node nR.
  • the first terminal of the offset voltage memory cell is connected to the drain of the transistor N1, that is, connected to the first node nL.
  • the second terminal of the offset voltage storage unit is connected to the gate of the transistor N2.
  • the operation stage of the sense amplifier of the exemplary embodiment of the present disclosure can be divided into an offset cancellation stage, a voltage sensing stage, and a voltage difference amplification stage.
  • the sense amplifier may store offset voltages of at least two transistors among the transistors N1, N2, P1, and P2 in the offset voltage storage unit, the offset voltage being due to the size of the transistors, due to differences in mobility, threshold voltage, etc.
  • the sense amplifier can suppress the influence of transistor performance imbalance on data amplification according to the offset voltage stored in the offset voltage storage unit, so that the data on the bit line can be accurately read.
  • the transistors P1 and P2 can be configured as a current mirror, and both the transistors N1 and N2 can be configured as a diode connection, so as to store the offset voltage of the amplifying module in the offset voltage storage unit middle.
  • the offset voltage of the amplifying module refers to the offset voltage of at least two transistors (or components) in the amplifying module. Specifically, it may be the offset voltage of the transistors P1 and P2, or the offset voltage of the transistors N1 and N2, or the integrated offset voltage of the two, which is not limited in the present disclosure.
  • the sense amplifier further includes a first switch (hereinafter referred to as switch K1), a second switch (hereinafter referred to as switch K2), and a third switch (hereinafter referred to as switch K3), so as to realize the offset elimination stage transistor N1 of the above-mentioned sense amplifier , N2, P1, P2 configuration.
  • switch K1 a first switch
  • switch K2 a second switch
  • switch K3 a third switch
  • the first end of the switch K1 is connected to the first node nL, the second end of the switch K1 is connected to the gate of the transistor N1; the first end of the switch K2 is connected to the second node nR, and the second end of the switch K2 is connected to the gate of the transistor N2.
  • the gate is connected; the first end of the switch K3 is connected to the gate of the transistor P1, and the second end of the switch K3 is connected to the gate of the transistor P2.
  • the switch K1, the switch K2, and the switch K3 are all in a closed state.
  • the present disclosure does not limit the types of the switch K1, the switch K2, and the switch K3.
  • the switch K1 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K2 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K3 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate.
  • the switch K1 may include a control terminal for controlling the switch state of the switch K1 in response to the first control signal; the switch K2 may also include a control terminal for controlling the switch of the switch K2 in response to the second control signal The switch K3 may also include a control terminal for controlling the switch state of the switch K3 in response to the second control signal. That is to say, both the control terminals of the switch K2 and the switch K3 can receive the second control signal.
  • the sense amplifier of the exemplary embodiment of the present disclosure further includes a pull-up unit and a pull-down unit.
  • the pull-up unit is used to connect the source of the transistor P1 to the power supply voltage VDD in response to the pull-up control signal.
  • the pull-down unit is used to ground the source of the transistor N1 in response to the pull-down control signal.
  • the pull-up unit may include a pull-up PMOS transistor, and the pull-down unit may include a pull-down NMOS transistor.
  • the pull-up unit can also be implemented using NMOS transistors, the pull-down unit can also be implemented using PMOS transistors, and the pull-up unit or pull-down unit can include more than one device, and can also include multiple devices that are turned on or off through different control signals. device, which is not limited in the present disclosure.
  • the sense amplifier of the present disclosure may further include a fourth switch (hereinafter referred to as switch K4 ) and a fifth switch (hereinafter referred to as switch K5 ).
  • switch K4 a fourth switch
  • switch K5 a fifth switch
  • the first end of the switch K4 is connected to the gate of the transistor N1, the second end of the switch K4 is connected to the second node nR; the first end of the switch K5 is connected to the gate of the transistor P2, and the second end of the switch K5 is connected to the transistor N2 gate connection.
  • the present disclosure does not limit the types of switch K4 and switch K5.
  • the switch K4 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K5 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate.
  • the switch K4 may include a control terminal for controlling the switch state of the switch K4 in response to the third control signal; the switch K5 may also include a control terminal for controlling the switch of the switch K5 in response to the third control signal state. That is to say, both the control terminals of the switch K4 and the switch K5 can receive the third control signal.
  • both switch K4 and switch K5 are in an open state.
  • the sense amplifier of the present disclosure may further include a sixth switch (hereinafter referred to as switch K6) and a seventh switch (hereinafter referred to as switch K7).
  • switch K6 a sixth switch
  • switch K7 a seventh switch
  • the first end of the switch K6 is connected to the first bit line (denoted as BLL), the second end of the switch K6 is connected to the first node nL; the first end of the switch K7 is connected to the second bit line (denoted as BLR), the switch The second end of K7 is connected to the second node nR.
  • BLL first bit line
  • BLR second bit line
  • the present disclosure does not limit the types of switch K6 and switch K7.
  • the switch K6 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate
  • the switch K7 can be a PMOS transistor, an NMOS transistor or a CMOS transmission gate.
  • the switch K6 may include a control terminal for controlling the switch state of the switch K6 in response to the fourth control signal; the switch K7 may also include a control terminal for controlling the switch of the switch K7 in response to the fourth control signal state. That is to say, the control terminals of the switch K6 and the switch K7 can both receive the fourth control signal.
  • both switch K6 and switch K7 are in an open state.
  • the offset voltage of the amplifying module in the offset cancellation stage of the sense amplifier, can be stored in the offset voltage storage unit.
  • the memory cell corresponding to the first bit line BLL or the memory cell corresponding to the second bit line BLR is turned on, the switch K1 is turned off, the switch K2 and the switch K3 are turned off,
  • the source of the transistor P1 and the source of the transistor P2 are disconnected from the power supply voltage
  • the source of the transistor N1 and the source of the transistor N2 are disconnected from the ground
  • the switch K4 and the switch K5 are closed
  • the switch K6 and the switch K7 are closed.
  • the voltage difference between the bit line BLL and the second bit line BLR is input to the sense amplifier. Since the offset voltage storage unit stores the offset voltage of the transistor N1 and the transistor N2, it can suppress the inconsistency between the transistor N1 and the transistor N2. A data read error occurred.
  • turning on the memory cell means that the word line of the memory cell is activated, so that the data (0 or 1) stored in the memory cell is transmitted to the bit line.
  • the source of the transistor P1 is connected to the power supply voltage, and the source of the transistor N1 is grounded, so that the sense amplifier can detect the voltage difference. enlarge.
  • the sense amplifier of the exemplary embodiment of the present disclosure further includes a pre-charge unit configured to, when the sense amplifier is in the pre-charge phase, charge the first bit line BLL and the second bit line BLR Precharge.
  • the first bit line BLL and the second bit line BLR are pre-processed. While charging, the operation of storing the offset voltages of the transistors N1 and N2 in the offset voltage storage unit will not be affected. Therefore, in an exemplary embodiment of the present disclosure, the priming phase and the offset cancellation phase described above may be configured to be performed simultaneously.
  • FIG. 3 schematically shows a circuit diagram of a sense amplifier according to an embodiment of the present disclosure.
  • the offset voltage storage unit is configured as a capacitor C0.
  • the switch K1 is configured as a transistor N3 to control the switch state in response to the first control signal S1; the switch K2 is configured as a transistor N4 to control the switch state in response to the second control signal S2; the switch K3 is configured as a transistor N5 and responds to the second control signal Signal S2 to control the switch state.
  • the pull-up unit is configured as a transistor P3 and controls the switch state in response to the pull-up control signal Sense_P; the pull-down unit is configured as a transistor N6 and controls the switch state in response to the pull-down control signal Sense_N.
  • the switch K4 is configured as a transistor N7 and controls the switch state in response to the third control signal S3;
  • the switch K5 is configured as a transistor N8 and controls the switch state in response to the third control signal S3.
  • the switch K6 is configured as a transistor N9 and controls the switch state in response to the fourth control signal S4;
  • the switch K7 is configured as a transistor N10 and controls the switch state in response to the fourth control signal S4.
  • the precharging unit may include a transistor N11, a transistor N12, and a transistor N13.
  • the gates of the transistor N11 , the transistor N12 and the transistor N13 may all receive the precharge control signal BLP.
  • the source of the transistor N11 is connected to the first bit line BLL, the drain of the transistor N11 is connected to the second bit line BLR; the source of the transistor N12 is connected to the first bit line BLL, and the drain of the transistor N12 is connected to the precharge voltage VBLP , wherein the precharge voltage VBLP can be configured as VDD/2; the source of the transistor N13 is connected to the second bit line BLR, and the drain of the transistor N13 is connected to the precharge voltage VBLP.
  • the memory cell corresponding to the first bit line BLL is configured to include a transistor N14 and a capacitor C1, and the transistor N14 controls the switching state in response to the first word line control signal WL1;
  • the memory cell corresponding to the second bit line BLR is configured to include a transistor N15 And the capacitor C2, the transistor N15 controls the switch state in response to the second word line control signal WL2.
  • FIG. 4 schematically shows a timing diagram of each control signal according to an embodiment of the present disclosure.
  • Fig. 5 is for the offset elimination stage of the sense amplifier, the first control signal S1 is high level, transistor N3 is turned on (corresponding to the closed state of the switch); the second control signal S2 is high level, transistor N4 and transistor N5 are turned on ; The third control signal S3 is low level, transistor N7 and transistor N8 are turned off (corresponding to the off state of the switch); the fourth control signal S4 is low level, transistor N9 and transistor N10 are turned off.
  • the transistor P3 When the pull-up control signal Sense_P is at a low level, the transistor P3 is turned on; when the pull-down control signal Sense_N is at a high level, the transistor N6 is turned on.
  • the transistors P1 and P2 are configured as current mirrors, and the transistors N1 and N2 are both configured as diode-connected.
  • the offset voltage of the transistor N1 and the transistor N2 will be stored on the capacitor C0, and the voltage on the side of the capacitor C0 close to the first bit line BLL can be recorded as VL , and the voltage on the side close to the second bit line BLR can be recorded as VL .
  • the voltage is noted as VR .
  • the word lines WL1/WL2 are at a low level, and the corresponding transistors are in an off state. That is, there is no data to be read on the bit line.
  • the precharge control signal BLP is at a high level, that is, precharge is performed, and both the first bit line BLL and the second bit line BLR are precharged to the precharge voltage VBLP.
  • Fig. 6 is for the voltage sensing stage of the sense amplifier, the first control signal S1 is low level, the transistor N3 is turned off; the second control signal S2 is low level, the transistor N4 and the transistor N5 are turned off; the third control signal S3 is high level, the transistor N7 and the transistor N8 are turned on; the fourth control signal S4 remains at a low level and then jumps to a high level, and the transistor N9 and the transistor N10 are turned off first and then turned on.
  • the transistor P3 When the pull-up control signal Sense_P is at a high level, the transistor P3 is turned off; when the pull-down control signal Sense_N is at a low level, the transistor N6 is turned off.
  • the precharge control signal BLP is at a low level, and the precharge has ended.
  • the word lines WL1/WL2 are at a high level, the corresponding transistors are turned on, and the data stored in the capacitors are transferred to the bit lines.
  • the second word line control signal WL2 is at a high level, the transistor N15 is turned on, and the data stored in the capacitor C2 is transferred to the second bit line BLR. Due to the influence of data on the bit lines, a small voltage difference is formed between the first bit line BLL and the second bit line BLR.
  • the fourth control signal S4 jumps to a high level, and the transistor N9 and the transistor N10 are turned on, so that this small voltage difference is transmitted to the inside of the sense amplifier. Due to the action of the capacitor C0, it is actually transmitted to the gate of the transistor N2
  • the voltage of the pole is VBLL +VR - VL , where VBLL is the voltage on the first bit line.
  • Figure 7 is aimed at the voltage difference amplification stage of the sense amplifier, referring to the timing diagram of Figure 4, compared with the voltage sensing stage, the pull-up control signal Sense_P is at a low level, and the transistor P3 is turned on; the pull-down control signal Sense_N is at a high level, and the transistor P3 is turned on. N6 is turned on.
  • transistor P1, transistor P2, transistor N1 and transistor N2 form two cross-coupled inverter positive feedback circuits, so that the voltage difference on the bit line can be quickly amplified and written back to the corresponding memory cell .
  • the offset compensation of the sense amplifier can be realized, the influence of the offset voltage caused by the mismatch of the transistors on the read bit line data can be greatly reduced, and the semiconductor memory can be improved. performance.
  • a voltage balance phase between the offset cancellation phase and the voltage sensing phase of the sense amplifier, there may be a voltage balance phase, so that the voltage of the first node nL is consistent with the voltage of the second node nR .
  • Figure 8 shows a timing diagram of the various control signals including the voltage balancing phase.
  • the second control signal S2 is at a low level, and the transistor N4 and the transistor N5 are turned off; the third control signal S3 is at a high level, and the transistor N7 and the transistor N8 are turned on. Pass.
  • the transistor P3 When the pull-up control signal Sense_P is at a high level, the transistor P3 is turned off; when the pull-down control signal Sense_N is at a low level, the transistor N6 is turned off.
  • the voltage of the first node nL in the sense amplifier is consistent with the voltage of the second node nR, so as to achieve the purpose of charge balance, and eliminate the influence of the voltage difference formed in the offset elimination stage on the data read-in.
  • the precharging phase may be performed while the offset cancellation phase is being performed, alternatively, the precharging phase may be performed while performing the voltage balancing phase, alternatively, the precharging phase may be performed while performing the offset cancellation phase and the voltage balancing phase is performed.
  • the present disclosure also provides a control method for a sense amplifier.
  • FIG. 10 schematically shows a flowchart of a control method of a sense amplifier according to an exemplary embodiment of the present disclosure.
  • the sense amplifier may include a first NMOS transistor, a second NMOS transistor and an offset voltage storage unit.
  • control method of the sense amplifier may include the following steps:
  • the offset voltage of the control amplifier module is stored in the offset voltage storage unit.
  • the sense amplifier may also include a voltage difference amplification stage to amplify the voltage difference on the bit line and to write the voltage back to the memory cell. Additionally, in other embodiments, the sense amplifier may further include a voltage balancing stage. The details of these have been explained in the process of describing the sense amplifier above, and will not be repeated here.
  • the offset compensation of the sense amplifier can be realized, which greatly reduces the problem caused by the mismatch of the transistors.
  • the effect of offset voltage on reading bit line data thereby improving the performance of semiconductor memory.
  • FIG. 11 shows a graph comparing the offset voltage simulation results of the sense amplifier of an exemplary embodiment of the present disclosure and the sense amplifier of some technologies.
  • the standard deviation of the offset voltage of the sense amplifier of the exemplary embodiment of the present disclosure increases from 3.44279 mV to 4.18693 mV compared with the OCSA in some technologies, and the difference between the two is relatively small.
  • the read speed and power consumption performance of the sense amplifier of the exemplary embodiment of the present disclosure can be greatly improved.
  • FIG. 12 shows a graph comparing the read time of the sense amplifier of an exemplary embodiment of the present disclosure and the sense amplifier of some technologies.
  • Exemplary embodiments of the present disclosure may store the offset voltage in a capacitive storage manner, and the pre-charging phase of the sense amplifier may be performed simultaneously with the offset cancellation phase, thus, the sense amplifier of the exemplary embodiments of the present disclosure may be compared to some technologies in the sense amplifier. OCSA, reading speed increased by 20.5%.
  • FIG. 13 shows a graph comparing the average power consumption of a sense amplifier of an exemplary embodiment of the present disclosure and a sense amplifier of some technologies.
  • the sense amplifier of the exemplary embodiment of the present disclosure has a simple circuit structure, and eliminates the offset by means of capacitive storage, which improves the reading speed and greatly reduces the reading speed compared with some technologies. power consumption.
  • the present disclosure also provides a memory including the above-mentioned sense amplifier.
  • the read error rate of the memory is reduced, the read speed is increased, and the read power consumption is reduced. As a result, the performance of the memory is greatly improved.

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Abstract

一种灵敏放大器、存储器和灵敏放大器的控制方法，涉及半导体存储器技术领域。该灵敏放大器（1）包括：放大模块（10）；偏移电压存储单元（11），与放大模块（10）电连接；其中，在灵敏放大器（1）的偏移消除阶段，灵敏放大器（1）被配置为包含电流镜结构，以将放大模块（10）的偏移电压存储在偏移电压存储单元（11）中。该方案可以实现灵敏放大器的偏移消除。

Description

灵敏放大器、存储器和灵敏放大器的控制方法
相关申请的交叉引用
本申请要求于2020年07月27日提交的申请号为202010733140.5、名称为“灵敏放大器、存储器和灵敏放大器的控制方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体存储器技术领域，具体而言，涉及一种灵敏放大器、存储器和灵敏放大器的控制方法。
背景技术
随着手机、平板、个人计算机等电子设备的普及，半导体存储器技术也得到了快速的发展。例如DRAM(Dynamic Random Access Memory，动态随机存取存储器)、SRAM(Static Random-Access Memory，静态随机存取存储器)的存储器由于高密度、低功耗、低价格等优点，已广泛应用于各种电子设备中。
灵敏放大器(Sense Amplifier，简称SA)是半导体存储器的一个重要组成部分，其主要作用是将位线上的小信号进行放大，从而执行读取或写入操作。
随着技术的不断进步，半导体存储器的尺寸不断减小，在这种情况下，灵敏放大器中，由于晶体管的失配造成的失调电压越来越大，会严重影响半导体存储器的性能。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种灵敏放大器、存储器和灵敏放大器的控制方法，进而至少在一定程度上克服由于灵敏放大器中晶体管的失配而影响半导体存储器性能的问题。
根据本公开的第一方面，提供一种灵敏放大器，包括：放大模块；偏移电压存储单元，与放大模块电连接；其中，在灵敏放大器的偏移消除阶段，灵敏放大器被配置为包含电流镜结构，以将放大模块的偏移电压存储在偏移电压存储单元中。
可选地，放大模块包括：第一PMOS管；第二PMOS管，第二PMOS管的源极与第一PMOS管的源极连接；第一NMOS管，第一NMOS管的漏极与第一PMOS管的漏极、偏移电压存储单元的第一端连接，第一NMOS管的栅极与第一PMOS管的栅极连接；第二NMOS管，第二NMOS管的漏极与第二PMOS管的漏极连接，第二NMOS管的源极与第一NMOS管的源极连接，第二NMOS管的栅极与所述偏移电压存储单元的第二端连接；偏移电压存储单元，偏移电压存储单元的第一端与第一NMOS管的漏极连接，偏移 电压存储单元的第二端与第二NMOS管的栅极连接；其中，在灵敏放大器的偏移消除阶段，第一PMOS管和第二PMOS管被配置为电流镜，第一NMOS管和第二NMOS管均被配置为二极管连接方式，以将放大模块的偏移电压存储在偏移电压存储单元中。
可选地，第一PMOS管的漏极与第一NMOS管的漏极连接于第一节点，第二PMOS管的漏极与第二NMOS管的漏极连接于第二节点；灵敏放大器还包括：第一开关，第一开关的第一端与第一节点连接，第一开关的第二端与第一NMOS管的栅极连接；第二开关，第二开关的第一端与第二节点连接，第二开关的第二端与第二NMOS管的栅极连接；第三开关，第三开关的第一端与第一PMOS管的栅极连接，第三开关的第二端与第二PMOS管的栅极连接；其中，在灵敏放大器的偏移消除阶段，第一开关、第二开关、第三开关均处于闭合状态。
可选地，灵敏放大器还包括：上拉单元，用于响应上拉控制信号，控制第一PMOS管的源极与电源电压的连接状态；下拉单元，用于响应下拉控制信号，控制第一NMOS管的源极是否接地；其中，在灵敏放大器的偏移消除阶段，第一PMOS管的源极与电源电压连接，第一NMOS管的源极接地。
可选地，第一开关还包括控制端，用于响应第一控制信号控制第一开关的开关状态；第二开关还包括控制端，用于响应第二控制信号控制第二开关的开关状态；第三开关还包括控制端，用于响应第二控制信号控制第三开关的开关状态。
可选地，灵敏放大器还包括：第四开关，第四开关的第一端与第一NMOS管的栅极连接，第四开关的第二端与第二节点连接；第五开关，第五开关的第一端与第二PMOS管的栅极连接，第五开关的第二端与第二NMOS管的栅极连接；其中，在灵敏放大器的偏移消除阶段，第四开关和第五开关均断开。
可选地，第四开关还包括控制端，用于响应第三控制信号控制第四开关的开关状态；第五开关还包括控制端，用于响应第三控制信号控制第五开关的开关状态。
可选地，灵敏放大器还包括：第六开关，第六开关的第一端与第一位线连接，第六开关的第二端与第一节点连接；第七开关，第七开关的第一端与第二位线连接，第七开关的第二端与第二节点连接；其中，在灵敏放大器的偏移消除阶段，第六开关和第七开关均断开。
可选地，第六开关还包括控制端，用于响应第四控制信号控制第六开关的开关状态；第七开关还包括控制端，用于响应第四控制信号控制第七开关的开关状态。
可选地，在灵敏放大器的偏移消除阶段之后，与第一位线对应的存储单元或与第二位线对应的存储单元开启，第一开关断开，第二开关和第三开关断开，第一PMOS管的源极与电源电压断开，第一NMOS管的源极与地断开，第四开关和第五开关闭合，第六开关和第七开关闭合，以将第一位线与第二位线之间的电压差输入灵敏放大器。
可选地，在第一位线与第二位线之间的电压差被输入灵敏放大器的情况下，第一PMOS管的源极与电源电压连接，第一NMOS管的源极接地，以对电压差进行放大。
可选地，灵敏放大器还包括：预充单元，被配置为当灵敏放大器处于预充阶段时，对第一位线和第二位线进行预充电。
可选地，预充阶段与偏移消除阶段被配置为同时执行。
根据本公开的第二方面，提供一种存储器，包括如上述任意一种灵敏放大器。
根据本公开的第三方面，提供一种灵敏放大器的控制方法，灵敏放大器包括放大模块和偏移电压存储单元，灵敏放大器的控制方法包括：在灵敏放大器的偏移消除阶段，将所述灵敏放大器配置为包含电流镜结构，以控制放大模块的偏移电压存储在偏移电压存储单元中，实现偏移补偿。
可选地，灵敏放大器的控制方法还包括：在灵敏放大器的电压感应阶段，基于从与第一位线对应的存储单元或与第二位线对应的存储单元读取到的存储数据，生成电压差。
可选地，灵敏放大器的工作阶段还包括电压差放大阶段；其中，灵敏放大器的控制方法还包括：在灵敏放大器的电压差放大阶段，对电压差进行放大，并基于偏移电压存储单元中存储的偏移电压，抑制由于放大模块中至少两个晶体管的不一致而导致的电压差被错误放大。灵敏放大器中的晶体管至少包括第一NMOS管、第二NMOS管、第一PMOS管和第二PMOS管。
可选地，灵敏放大器的工作阶段还包括预充电阶段；其中，灵敏放大器的控制方法还包括：在灵敏放大器的预充电阶段，对第一位线和第二位线进行预充电。
可选地，灵敏放大器的控制方法还包括：在灵敏放大器处于偏移消除阶段时，控制执行预充电阶段的预充电操作。
在本公开的一些实施例所提供的技术方案中，通过在灵敏放大器中配置偏移电压存储单元，在灵敏放大器的偏移消除阶段，可以将灵敏放大器中的放大模块的偏移电压存储在该偏移电压存储单元中。由此，在需要读取位线数据时，借助于偏移电压存储单元中存储的偏移电压，可以实现灵敏放大器的偏移补偿，极大程度降低了由于晶体管的失配而造成的失调电压对读取位线数据的影响，进而提高半导体存储器的性能。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1示意性示出了根据本公开的示例性实施方式的灵敏放大器的框图；
图2示意性示出了根据本公开的示例性实施方式的灵敏放大器的电路图；
图3示意性示出了根据本公开一实施例的灵敏放大器的具体配置方式的电路图；
图4示意性示出了根据本公开实施例的灵敏放大器中所涉各控制信号的时序图；
图5示意性示出了根据本公开实施例的在偏移消除阶段灵敏放大器的电路图；
图6示意性示出了根据本公开实施例的在电压感应阶段灵敏放大器的电路图；
图7示意性示出了根据本公开实施例的在电压差放大阶段灵敏放大器的等效电路图；
图8示意性示出了根据本公开另一实施例的灵敏放大器中所涉各控制信号的时序图；
图9示意性示出了根据本公开实施例的在电压平衡阶段灵敏放大器的电路图；
图10示意性示出了根据本公开的示例性实施方式的灵敏放大器的控制方法的流程图；
图11示出了本公开示例性实施方式的灵敏放大器与一些技术的灵敏放大器的失调电压仿真结果的对比图；
图12示出了本公开示例性实施方式的灵敏放大器与一些技术的灵敏放大器的读取时间的对比图；
图13示出了本公开示例性实施方式的灵敏放大器与一些技术的灵敏放大器的平均功耗的对比图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。“第一”、“第二”、“第三”、“第四”、“第五”、“第六”、“第七”的描述仅是为了区分，不应作为本公开的限制。
需要说明的是，本公开所说的术语“连接”，可以包括直接连接和间接连接。在直接连接中，端与端之间没有元器件，例如，开关A的第一端与开关B的第一端连接，可以是在开关A的第一端与开关B的第一端的连接线路上，只有连接线(如，金属线)，而不存在其他元器件。在间接连接中，端与端之间可以存在其他元器件，例如，开关C的第一端与开关D的第一端连接，可以是在开关C的第一端与开关D的第一端的连接线路上，除连接线外，连接线上还存在至少一个其他元器件(如，开关E等)。
另外，在下面的描述中，本领域技术人员容易理解的是，术语“偏移”与“失调”含义相同，均表示由于晶体管的差异而导致的偏差。
在灵敏放大器中，由于制程上的差异以及工作环境的影响，可能导致晶体管的尺寸、 迁移率、阈值电压等存在差别，各晶体管的性能通常不可能完全相同，这就会造成灵敏放大器失调，相当于出现了失调噪声，严重影响存储器读取数据的正确性。
例如，灵敏放大器包括两个对称配置的NMOS管，理想状态下，希望这两个NMOS管的性能完全相同。然而，在实际中，这两个NMOS管的阈值电压可能不同，这就会出现电路失调的情况。此时若不采取任何措施，在从存储单元读取数据时，就有可能将原本存储的“1”读成“0”错误输出，或者将原本存储的“0”读成“1”错误输出。
为了解决这个问题，在一些技术中，提供了一种偏移消除灵敏放大器(Offset-Cancellation Sense Amplifier，OCSA)，通过偏移抵消来提高感测裕度。该方案需要在读取数据之前专门配置一个偏移补偿的阶段，读取速度慢。另外，这种灵敏放大器会利用位线电容进行调节，而位线电容通常较大，在调节的过程中功耗比较大。
鉴于此，本公开提供了一种新的灵敏放大器。
图1示意性示出了根据本公开的示例性实施方式的灵敏放大器的框图。如图1所示，灵敏放大器1可以包括放大模块10和偏移电压存储单元11。
放大模块10用于读取第一位线或第二位线上存储单元的数据；
偏移电压存储单元11与放大模块10电连接。
在灵敏放大器的偏移消除阶段，灵敏放大器1被配置为包含电流镜结构，以将放大模块10的偏移电压存储在所述偏移电压存储单元11中。
应当注意的是，放大模块10的偏移电压可以指代放大模块10所包括的各元器件之间的偏移电压。也就是说，放大模块10的偏移电压可以表示放大模块10中至少两个元器件之间的不一致而产生的电压差。在综合所有元器件之间的电压差的情况下，该偏移电压指代整个放大模块10的偏移电压。
放大模块10可以包括第一PMOS管(下面简称晶体管P1)、第二PMOS管(下面简称晶体管P2)、第一NMOS管(下面简称晶体管N1)、第二NMOS管(下面简称晶体管N2)。
在本公开的一些实施例中，偏移电压存储单元可以被配置为一个电容。然而，具有电压存储功能的器件、单元均可以作为本公开所述的偏移电压存储单元，本公开对偏移电压存储单元的配置形式不做限制。
图2示意性示出了根据本公开的示例性实施方式的灵敏放大器的电路图。
参考图2，晶体管P1的源极与晶体管P2的源极连接，晶体管P1的漏极与晶体管N1的漏极连接，晶体管P1的栅极与晶体管N1的栅极连接。其中，为了随后描述方便，可以在灵敏放大器中定义第一节点nL，晶体管P1的漏极与晶体管N1的漏极连接于第一节点nL。
晶体管N2的漏极与晶体管P2的漏极连接，晶体管N2的源极与晶体管N1的源极连接。其中，为了随后描述方便，可以在灵敏放大器中定义第二节点nR，晶体管N2的漏极与晶体管P2的漏极连接于第二节点nR。
偏移电压存储单元的第一端与晶体管N1的漏极连接，即，连接于第一节点nL。偏移电压存储单元的第二端与晶体管N2的栅极连接。
本公开示例性实施方式的灵敏放大器的工作阶段可以被划分为：偏移消除阶段、电压感应阶段和电压差放大阶段。
在偏移消除阶段，灵敏放大器可以将晶体管N1、晶体管N2、晶体管P1、晶体管P2中的至少两个晶体管的偏移电压存储在偏移电压存储单元中，该偏移电压是由于晶体管的尺寸、迁移率、阈值电压等存在差异而产生的。在电压差放大阶段，灵敏放大器可以根据偏移电压存储单元中存储的偏移电压，来抑制晶体管性能失调对数据放大的影响，使得能够准确读取出位线上的数据。
针对灵敏放大器的偏移消除阶段，晶体管P1和晶体管P2可以被配置为电流镜，晶体管N1和晶体管N2均可以被配置为二极管连接方式，以将放大模块的偏移电压存储在偏移电压存储单元中。
应当注意的是，放大模块的偏移电压指的是，放大模块中至少两个晶体管(或元器件)的偏移电压。具体的，可以是晶体管P1与晶体管P2的偏移电压，也可以是晶体管N1与晶体管N2的偏移电压，还可以是这二者综合后的偏移电压，本公开对此不做限制。
参考图2，灵敏放大器还包括第一开关(下面简称开关K1)、第二开关(下面简称开关K2)、第三开关(下面简称开关K3)，以实现上述灵敏放大器的偏移消除阶段晶体管N1、N2、P1、P2的配置。
开关K1的第一端与第一节点nL连接，开关K1的第二端与晶体管N1的栅极连接；开关K2的第一端与第二节点nR连接，开关K2的第二端与晶体管N2的栅极连接；开关K3的第一端与晶体管P1的栅极连接，开关K3的第二端与晶体管P2的栅极连接。
在灵敏放大器的偏移消除阶段，开关K1、开关K2、开关K3均处于闭合状态。
其中，本公开对开关K1、开关K2、开关K3的类型不做限制。例如，开关K1可以是PMOS管、NMOS管或CMOS传输门；开关K2可以是PMOS管、NMOS管或CMOS传输门；开关K3可以是PMOS管、NMOS管或CMOS传输门。
在本公开的一些实施例中，开关K1可以包括控制端，用于响应第一控制信号控制开关K1的开关状态；开关K2也可以包括控制端，用于响应第二控制信号控制开关K2的开关状态；开关K3也可以包括控制端，用于响应第二控制信号控制开关K3的开关状态。也就是说，开关K2与开关K3的控制端均可以接收第二控制信号。
本公开示例性实施方式的灵敏放大器还包括上拉单元和下拉单元。其中，上拉单元用于响应上拉控制信号将晶体管P1的源极与电源电压VDD连接。下拉单元用于响应下拉控制信号将晶体管N1的源极接地。
在本公开的一个实施例中，上拉单元可以包括上拉PMOS管，下拉单元可以包括下拉NMOS管。然而，上拉单元也可以使用NMOS管实现，下拉单元也可以使用PMOS管实现，并且上拉单元或下拉单元可以包含不止一个器件，也可以包括通过不同的控制信 号控制导通或关断的多个器件，本公开对此不做限制。
继续参考图2，本公开的灵敏放大器还可以包括第四开关(下面简称开关K4)和第五开关(下面简称开关K5)。
开关K4的第一端与晶体管N1的栅极连接，开关K4的第二端与第二节点nR连接；开关K5的第一端与晶体管P2的栅极连接，开关K5的第二端与晶体管N2的栅极连接。
类似地，本公开对开关K4和开关K5的类型不做限制。例如，开关K4可以是PMOS管、NMOS管或CMOS传输门；开关K5可以是PMOS管、NMOS管或CMOS传输门。
在本公开的一些实施例中，开关K4可以包括控制端，用于响应第三控制信号控制开关K4的开关状态；开关K5也可以包括控制端，用于响应第三控制信号控制开关K5的开关状态。也就是说，开关K4与开关K5的控制端均可以接收第三控制信号。
在灵敏放大器的偏移消除阶段，开关K4和开关K5均处于断开状态。
另外，本公开的灵敏放大器还可以包括第六开关(下面简称开关K6)和第七开关(下面简称开关K7)。
开关K6的第一端与第一位线(记为BLL)连接，开关K6的第二端与第一节点nL连接；开关K7的第一端与第二位线(记为BLR)连接，开关K7的第二端与第二节点nR连接。本领域技术人员容易理解的是，第一位线BLL与第二位线BLR上均分别对应有存储单元。
类似地，本公开对开关K6和开关K7的类型不做限制。例如，开关K6可以是PMOS管、NMOS管或CMOS传输门；开关K7可以是PMOS管、NMOS管或CMOS传输门。
在本公开的一些实施例中，开关K6可以包括控制端，用于响应第四控制信号控制开关K6的开关状态；开关K7也可以包括控制端，用于响应第四控制信号控制开关K7的开关状态。也就是说，开关K6与开关K7的控制端均可以接收第四控制信号。
在灵敏放大器的偏移消除阶段，开关K6和开关K7均处于断开状态。
结合上述示例性的电路配置，在灵敏放大器的偏移消除阶段，可以将放大模块的偏移电压存储在偏移电压存储单元中。
在灵敏放大器的偏移消除阶段之后的电压感应阶段，与第一位线BLL对应的存储单元或与第二位线BLR对应的存储单元开启，开关K1断开，开关K2和开关K3断开，晶体管P1的源极和晶体管P2的源极与电源电压断开，晶体管N1的源极和晶体管N2的源极与地断开，开关K4和开关K5闭合，开关K6和开关K7闭合，以将第一位线BLL与第二位线BLR之间的电压差输入灵敏放大器，由于偏移电压存储单元中存储有晶体管N1与晶体管N2的偏移电压，因此，可以抑制由于晶体管N1与晶体管N2不一致而产生的数据读出错误。
其中，本领域技术人员可以理解的是，存储单元开启指的是，存储单元的字线激活，使存储单元中存储的数据(0或1)传输到位线上。
在第一位线BLL与第二位线BLR之间的电压差输入灵敏放大器的情况下，晶体管 P1的源极与电源电压连接，晶体管N1的源极接地，以使灵敏放大器对该电压差进行放大。
此外，仍参考图2，本公开示例性实施方式的灵敏放大器还包括预充单元，该预充单元被配置为当灵敏放大器处于预充阶段时，对第一位线BLL和第二位线BLR进行预充电。
可以看出，针对本公开的示例性实施方式的灵敏放大器结构，由于在偏移消除阶段，开关K6和开关K7均处于断开状态，在对第一位线BLL和第二位线BLR进行预充电的同时，不会影响到将晶体管N1与晶体管N2的偏移电压存储至偏移电压存储单元的操作。因此，在本公开的示例性实施方式中，预充阶段和上述偏移消除阶段可以被配置为同时执行。
图3示意性示出了根据本公开一实施例的灵敏放大器的电路图。
在图3所示的实施例中，偏移电压存储单元被配置为电容C0。
开关K1被配置为晶体管N3，响应第一控制信号S1来控制开关状态；开关K2被配置为晶体管N4，响应第二控制信号S2来控制开关状态；开关K3被配置为晶体管N5，响应第二控制信号S2来控制开关状态。
上拉单元被配置为晶体管P3，响应上拉控制信号Sense_P来控制开关状态；下拉单元被配置为晶体管N6，响应下拉控制信号Sense_N来控制开关状态。
开关K4被配置为晶体管N7，响应第三控制信号S3来控制开关状态；开关K5被配置为晶体管N8，响应第三控制信号S3来控制开关状态。
开关K6被配置为晶体管N9，响应第四控制信号S4来控制开关状态；开关K7被配置为晶体管N10，响应第四控制信号S4来控制开关状态。
预充单元可以包括晶体管N11、晶体管N12和晶体管N13。晶体管N11、晶体管N12和晶体管N13的栅极均可以接收预充控制信号BLP。晶体管N11的源极与第一位线BLL连接，晶体管N11的漏极与第二位线BLR连接；晶体管N12的源极与第一位线BLL连接，晶体管N12的漏极连接于预充电压VBLP，其中，预充电压VBLP可以被配置为VDD/2；晶体管N13的源极与第二位线BLR连接，晶体管N13的漏极连接于预充电压VBLP。
与第一位线BLL对应的存储单元被配置为包括晶体管N14和电容C1，晶体管N14响应第一字线控制信号WL1控制开关状态；与第二位线BLR对应的存储单元被配置为包括晶体管N15和电容C2，晶体管N15响应第二字线控制信号WL2控制开关状态。
图4示意性示出了根据本公开实施例的各控制信号的时序图。
结合图4的时序图，分别参考图5、图6和图7对本公开一些实施例的灵敏放大器的工作阶段进行说明。
图5针对灵敏放大器的偏移消除阶段，第一控制信号S1为高电平，晶体管N3导通(对应开关的闭合状态)；第二控制信号S2为高电平，晶体管N4和晶体管N5导通；第三控制信号S3为低电平，晶体管N7和晶体管N8关断(对应开关的断开状态)；第四控制信号S4为低电平，晶体管N9和晶体管N10关断。
上拉控制信号Sense_P为低电平，晶体管P3导通；下拉控制信号Sense_N为高电平，晶体管N6导通。
由此，晶体管P1与晶体管P2被配置为电流镜，晶体管N1和晶体管N2均被配置为二极管连接方式。在这种情况下，晶体管N1与晶体管N2的偏移电压会存储在电容C0上，可以将电容C0靠近第一位线BLL一侧的电压记为V L，靠近第二位线BLR一侧的电压记为V R。
另外，在偏移消除阶段，字线WL1/WL2为低电平，对应的晶体管处于关断状态。也就是说，位线上不存在待读取的数据。
而预充控制信号BLP为高电平，也就是说，预充被执行，第一位线BLL和第二位线BLR均被预充电至预充电压VBLP。
图6针对灵敏放大器的电压感应阶段，第一控制信号S1为低电平，晶体管N3关断；第二控制信号S2为低电平，晶体管N4和晶体管N5关断；第三控制信号S3为高电平，晶体管N7和晶体管N8导通；第四控制信号S4持续低电平后再跳转至高电平，晶体管N9和晶体管N10先处于关断状态再导通。
上拉控制信号Sense_P为高电平，晶体管P3关断；下拉控制信号Sense_N为低电平，晶体管N6关断。
另外，预充控制信号BLP为低电平，预充已结束。
首先，字线WL1/WL2为高电平，对应的晶体管导通，电容中存储的数据被传送至位线。例如，第二字线控制信号WL2为高电平，晶体管N15导通，存储于电容C2上的数据被传送至第二位线BLR。由于数据对位线的影响，在第一位线BLL与第二位线BLR之间会形成一个较小的电压差。
接下来，第四控制信号S4跳转至高电平，晶体管N9和晶体管N10的导通，使这个较小的电压差被传输至灵敏放大器的内部，由于电容C0的作用，实际传输到晶体管N2栅极的电压为V BLL+V R-V L，其中，V BLL为第一位线上的电压。由此，抑制了由于放大模块中至少两个晶体管的不一致而导致的电压差被错误放大，减小了读错率。
图7针对灵敏放大器的电压差放大阶段，参考图4的时序图，相比于电压感应阶段，上拉控制信号Sense_P为低电平，晶体管P3导通；下拉控制信号Sense_N为高电平，晶体管N6导通。
在这种情况下，晶体管P1、晶体管P2、晶体管N1和晶体管N2形成两个交叉耦合的反相器正反馈电路，从而可以快速放大位线上的电压差，并回写到相应的存储单元中。
通过本公开示例性实施方式的灵敏放大器配置方式，可以实现灵敏放大器的偏移补偿，极大程度降低了由于晶体管的失配而造成的失调电压对读取位线数据的影响，进而提高半导体存储器的性能。
此外，在本公开的另一些实施例中，在灵敏放大器的偏移消除阶段与电压感应阶段之间，还可以存在电压平衡阶段，以使第一节点nL的电压与第二节点nR的电压一致。
图8示出了包含电压平衡阶段的各控制信号的时序图。
结合图8的时序图，参考图9对本公开另一些实施例中的电压平衡阶段进行说明。
相比于偏移消除阶段，在灵敏放大器的电压平衡阶段，第二控制信号S2为低电平，晶体管N4和晶体管N5关断；第三控制信号S3为高电平，晶体管N7和晶体管N8导通。
上拉控制信号Sense_P为高电平，晶体管P3关断；下拉控制信号Sense_N为低电平，晶体管N6关断。
由此，使得灵敏放大器中第一节点nL的电压与第二节点nR的电压一致，达到电荷平衡的目的，消除了由于偏移消除阶段形成的电压差对数据读入的影响。
在包括电压平衡阶段的实施例中，预充阶段可以在执行偏移消除阶段时执行，或者，预充阶段可以在执行电压平衡阶段时执行，亦或者，预充阶段可以在执行偏移消除阶段和电压平衡阶段执行。
进一步的，本公开还提供了一种灵敏放大器的控制方法。
图10示意性示出了根据本公开的示例性实施方式的灵敏放大器的控制方法的流程图。如上所述，灵敏放大器可以包括第一NMOS管、第二NMOS管和偏移电压存储单元。
参考图10，灵敏放大器的控制方法可以包括以下步骤：
S102.在灵敏放大器的偏移消除阶段，控制放大模块的偏移电压存储在偏移电压存储单元中。
S104.在灵敏放大器的电压感应阶段，基于从与第一位线对应的存储单元或与第二位线对应的存储单元读取到的存储数据，生成电压差，并基于偏移电压存储单元中存储的偏移电压，抑制由于放大模块中至少两个晶体管的不一致而导致的电压差被错误放大。
如上所述，灵敏放大器还可以包括电压差放大阶段，以放大位线上的电压差，以及将电压回写至存储单元。另外，在另一些实施例中，灵敏放大器还可以包括电压平衡阶段。这些的细节在上述描述灵敏放大器的过程中均已说明，在此不再赘述。
通过本公开示例性实施方式的灵敏放大器的控制方法，借助于偏移电压存储单元中存储的偏移电压，可以实现灵敏放大器的偏移补偿，极大程度降低了由于晶体管的失配而造成的失调电压对读取位线数据的影响，进而提高半导体存储器的性能。
图11示出了本公开示例性实施方式的灵敏放大器与一些技术的灵敏放大器的失调电压仿真结果的对比图。
如图11所示，本公开示例性实施方式的灵敏放大器相比于一些技术中的OCSA，失调电压的标准差从3.44279mV上升4.18693mV，二者差距较小。然而，本公开示例性实施方式的灵敏放大器的读取速度和功耗性能均能得到大幅提升。
图12示出了本公开示例性实施方式的灵敏放大器与一些技术的灵敏放大器的读取时间的对比图。
本公开示例性实施方式可以采用电容存储的方式存储偏移电压，灵敏放大器的预充阶段可以与偏移消除阶段同时执行，由此，本公开示例性实施方式的灵敏放大器相比于一些 技术中的OCSA，读取速度提升20.5％。
图13示出了本公开示例性实施方式的灵敏放大器与一些技术的灵敏放大器的平均功耗的对比图。
通过实验比对，由于本公开示例性实施方式采用电容来存储偏移电压，节省了大量的能量，相比于一些技术中的OCSA，功耗降低了43％至61％。
综上所述，本公开示例性实施方式的灵敏放大器，电路结构简单，通过电容存储的方式，在消除偏移的同时，相比于一些技术，提高了读取速度，并大幅减少了读取功耗。
进一步的，本公开还提供了一种存储器，该存储器包括上述灵敏放大器。
借助于本公开示例性实施方式的灵敏放大器，降低了存储器的读取错误率，提高了读取速度，减少了读取功耗。由此，存储器的性能得到了较大幅度的提升。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。

Claims (19)

  1. 一种灵敏放大器，包括：
    放大模块；
    偏移电压存储单元，与所述放大模块电连接；
    其中，在所述灵敏放大器的偏移消除阶段，所述灵敏放大器被配置为包含电流镜结构，以将所述放大模块的偏移电压存储在所述偏移电压存储单元中。
  2. 根据权利要求1所述的灵敏放大器，其中，所述放大模块包括：
    第一PMOS管；
    第二PMOS管，所述第二PMOS管的源极与所述第一PMOS管的源极连接；
    第一NMOS管，所述第一NMOS管的漏极与所述第一PMOS管的漏极、所述偏移电压存储单元的第一端连接，所述第一NMOS管的栅极与所述第一PMOS管的栅极连接；
    第二NMOS管，所述第二NMOS管的漏极与所述第二PMOS管的漏极连接，所述第二NMOS管的源极与所述第一NMOS管的源极连接，所述第二NMOS管的栅极与所述偏移电压存储单元的第二端连接；
    其中，在所述灵敏放大器的偏移消除阶段，所述第一PMOS管和所述第二PMOS管被配置为电流镜，所述第一NMOS管和所述第二NMOS管均被配置为二极管连接方式，以将所述放大模块的偏移电压存储在所述偏移电压存储单元中。
  3. 根据权利要求2所述的灵敏放大器，其中，所述第一PMOS管的漏极与所述第一NMOS管的漏极连接于第一节点，所述第二PMOS管的漏极与所述第二NMOS管的漏极连接于第二节点；所述灵敏放大器还包括：
    第一开关，所述第一开关的第一端与所述第一节点连接，所述第一开关的第二端与所述第一NMOS管的栅极连接；
    第二开关，所述第二开关的第一端与所述第二节点连接，所述第二开关的第二端与所述第二NMOS管的栅极连接；
    第三开关，所述第三开关的第一端与所述第一PMOS管的栅极连接，所述第三开关的第二端与所述第二PMOS管的栅极连接；
    其中，在所述灵敏放大器的偏移消除阶段，所述第一开关、所述第二开关、所述第三开关均处于闭合状态。
  4. 根据权利要求3所述的灵敏放大器，其中，所述灵敏放大器还包括：
    上拉单元，用于响应上拉控制信号，控制所述第一PMOS管的源极与电源电压的连接状态；
    下拉单元，用于响应下拉控制信号，控制所述第一NMOS管的源极是否接地；
    其中，在所述灵敏放大器的偏移消除阶段，所述第一PMOS管的源极与所述电源电压连接，所述第一NMOS管的源极接地。
  5. 根据权利要求3所述的灵敏放大器，其中，所述第一开关还包括控制端，用于响应第一控制信号控制所述第一开关的开关状态；
    所述第二开关还包括控制端，用于响应第二控制信号控制所述第二开关的开关状态；
    所述第三开关还包括控制端，用于响应所述第二控制信号控制所述第三开关的开关状态。
  6. 根据权利要求4所述的灵敏放大器，其中，所述灵敏放大器还包括：
    第四开关，所述第四开关的第一端与所述第一NMOS管的栅极连接，所述第四开关的第二端与所述第二节点连接；
    第五开关，所述第五开关的第一端与所述第二PMOS管的栅极连接，所述第五开关的第二端与所述第二NMOS管的栅极连接；
    其中，在所述灵敏放大器的偏移消除阶段，所述第四开关和所述第五开关均断开。
  7. 根据权利要求6所述的灵敏放大器，其中，所述第四开关还包括控制端，用于响应第三控制信号控制所述第四开关的开关状态；
    所述第五开关还包括控制端，用于响应所述第三控制信号控制所述第五开关的开关状态。
  8. 根据权利要求7所述的灵敏放大器，其中，所述灵敏放大器还包括：
    第六开关，所述第六开关的第一端与第一位线连接，所述第六开关的第二端与所述第一节点连接；
    第七开关，所述第七开关的第一端与第二位线连接，所述第七开关的第二端与所述第二节点连接；
    其中，在所述灵敏放大器的偏移消除阶段，所述第六开关和所述第七开关均断开。
  9. 根据权利要求8所述的灵敏放大器，其中，所述第六开关还包括控制端，用于响应第四控制信号控制所述第六开关的开关状态；
    所述第七开关还包括控制端，用于响应所述第四控制信号控制所述第七开关的开关状态。
  10. 根据权利要求9所述的灵敏放大器，其中，在所述灵敏放大器的偏移消除阶段之后，与所述第一位线对应的存储单元或与所述第二位线对应的存储单元开启，所述第一开关断开，所述第二开关和所述第三开关断开，所述第一PMOS管的源极与电源电压断开，所述第一NMOS管的源极与地断开，所述第四开关和所述第五开关闭合，所述第六开关和所述第七开关闭合，以将所述第一位线与所述第二位线之间的电压差输入所述灵敏放大器。
  11. 根据权利要求10所述的灵敏放大器，其中，在所述第一位线与所述第二位线之间的电压差被输入所述灵敏放大器的情况下，所述第一PMOS管的源极与所述电源电压连接，所述第一NMOS管的源极接地，以对所述电压差进行放大。
  12. 根据权利要求8所述的灵敏放大器，其中，所述灵敏放大器还包括：
    预充单元，被配置为当所述灵敏放大器处于预充阶段时，对所述第一位线和所述第二位线进行预充电。
  13. 根据权利要求12所述的灵敏放大器，其中，所述预充阶段与所述偏移消除阶段被配置为同时执行。
  14. 一种存储器，包括如权利要求1所述的灵敏放大器。
  15. 一种灵敏放大器的控制方法，所述灵敏放大器包括放大模块和偏移电压存储单元，所述灵敏放大器的控制方法包括：
    在所述灵敏放大器的偏移消除阶段，将所述灵敏放大器配置为包含电流镜结构，以控制放大模块的偏移电压存储在所述偏移电压存储单元中，实现偏移补偿。
  16. 根据权利要求15所述的灵敏放大器的控制方法，其中，所述灵敏放大器的控制方法还包括：
    在所述灵敏放大器的电压感应阶段，基于从与第一位线对应的存储单元或与第二位线对应的存储单元读取到的存储数据，生成电压差。
  17. 根据权利要求16所述的灵敏放大器的控制方法，其中，所述灵敏放大器的工作阶段还包括电压差放大阶段；其中，所述灵敏放大器的控制方法还包括：
    在所述灵敏放大器的电压差放大阶段，对所述电压差进行放大，并基于所述偏移电压存储单元中存储的所述偏移电压，抑制由于所述放大模块中至少两个晶体管的不一致而导致的所述电压差被错误放大。
  18. 根据权利要求17所述的灵敏放大器的控制方法，其中，所述灵敏放大器的工作阶段还包括预充电阶段；其中，所述灵敏放大器的控制方法还包括：
    在所述灵敏放大器的预充电阶段，对所述第一位线和所述第二位线进行预充电。
  19. 根据权利要求18所述的灵敏放大器的控制方法，其中，所述灵敏放大器的控制方法还包括：
    在所述灵敏放大器处于所述偏移消除阶段时，控制执行所述预充电阶段的预充电操作。
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