WO2023093095A1 - 感测放大电路以及数据读出方法 - Google Patents

感测放大电路以及数据读出方法 Download PDF

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Publication number
WO2023093095A1
WO2023093095A1 PCT/CN2022/107640 CN2022107640W WO2023093095A1 WO 2023093095 A1 WO2023093095 A1 WO 2023093095A1 CN 2022107640 W CN2022107640 W CN 2022107640W WO 2023093095 A1 WO2023093095 A1 WO 2023093095A1
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Prior art keywords
bit line
active layer
write
gate layer
unit
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PCT/CN2022/107640
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English (en)
French (fr)
Inventor
杨桂芬
池性洙
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长鑫存储技术有限公司
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Priority to US18/149,675 priority Critical patent/US20230162762A1/en
Publication of WO2023093095A1 publication Critical patent/WO2023093095A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the present disclosure relates to the technical field of integrated circuits, in particular to a sense amplifier circuit and a data readout method.
  • a voltage difference between a bit line and a complementary bit line is usually sensed and amplified by a sense amplifier.
  • the sense amplifier usually uses two N-type transistors and two P-type transistors to form a latch-up large circuit structure, so as to amplify signals on the bit line and the compensation bit line connected at both ends of the sense amplifier.
  • the conduction capabilities of N-type transistors and P-type transistors formed under current process conditions are usually different, which may lead to read failure.
  • a sense amplifier circuit and a data readout method are provided.
  • a sense amplifier circuit comprising:
  • a first P-type transistor connected between a first signal terminal and a second complementary read bit line, and having a control terminal connected to a first read bit line connected to a bit line ;
  • the second P-type transistor is connected between the second signal terminal and the second readout bit line, and has a control terminal connected to the first complementary readout bit line, the first complementary readout bit line and the complementary bit line line connection;
  • a first N-type transistor connected between a third signal terminal and the second complementary read bit line, and having a control terminal connected to the first read bit line;
  • a second N-type transistor connected between a fourth signal terminal and said second sense bit line, and having a control terminal connected to said first complementary sense bit line;
  • a first offset cancellation unit configured to connect the first sense bit line to the second complementary sense bit line in response to a first offset cancellation signal
  • a second offset cancellation unit configured to connect the first complementary sense bit line to the second sense bit line in response to a second offset cancellation signal
  • a first write-back unit configured to connect the first complementary read bit line to the second complementary read bit line in response to a first write-back signal.
  • a data readout method applied to the above sense amplifier circuit comprising:
  • the bit line, the first read bit line, the complementary bit line, and the first complementary read bit line are pre-charged
  • a high level signal and a low level signal are respectively provided for the first signal terminal and the third signal terminal, and at the same time, the first offset elimination unit is turned on, so as to connect the first readout bit line to the a second complementary read bit line;
  • the first offset elimination unit is turned off, the storage unit is turned on, and the first write-back unit is turned on, thereby connecting the first complementary read bit line to the second complementary read bit line;
  • a high-level signal is provided for the first signal terminal and the second signal terminal, and a low-level signal is provided for the third signal terminal and the fourth signal terminal, and at the same time, the second write-back unit is turned on, so that the first A sense bit line is connected to the second sense bit line.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the third signal terminal connected to the second P-type transistor is independent of the first signal terminal connected to the first P-type transistor
  • the fourth signal terminal connected to the second N-type transistor is independent of the second signal terminal connected to the first N-type transistor
  • the first offset canceling unit and the second offset canceling unit respectively respond to different offset canceling signals. Therefore, in the phase of offset elimination, only the first P-type transistor and the first N-type transistor or the second P-type transistor and the second N-type transistor can be offset-eliminated, so that both the P-type transistor and the N-type transistor can be effectively eliminated. Offset noise caused by different turn-on capabilities of type transistors can effectively reduce offset cancellation power consumption.
  • FIG. 1 is a schematic circuit diagram of a sense amplifier circuit provided in an embodiment
  • FIG. 2 is a schematic circuit diagram of a sense amplifier circuit provided in another embodiment
  • FIG. 3 is a timing diagram of various control signals of the sense amplifier circuit when reading a memory cell according to an embodiment
  • 4 to 11 are structural schematic diagrams corresponding to the schematic circuit diagram of the sense amplifier circuit shown in FIG. 1 in different embodiments;
  • FIG. 12 is a schematic circuit diagram of a sense amplifier circuit provided in another embodiment
  • FIG. 13 to FIG. 24 are structural schematic diagrams corresponding to the schematic circuit diagram of the sense amplifier circuit shown in FIG. 12 in different embodiments;
  • FIG. 25 is a schematic circuit diagram of a sense amplifier circuit provided in yet another embodiment.
  • 26 to 37 are structural schematic diagrams corresponding to the circuit diagram of the sense amplifier circuit shown in FIG. 25 in different embodiments.
  • a sense amplifier circuit including a first P-type transistor 110, a second P-type transistor 120, a first N-type transistor 130, and a second N-type transistor 140. , the first offset elimination unit 210 , the second offset elimination unit 220 , the first write-back unit 310 and the second write-back unit 320 .
  • the first P-type transistor 110 , the second P-type transistor 120 , the first N-type transistor 130 and the second N-type transistor 140 form an amplification unit.
  • the first P-type transistor 110 is connected between the first signal terminal and the second complementary sense bit line ISABLB, and has a control terminal connected to the first sense bit line SABL.
  • the first signal terminal is used for receiving the first level signal PCS_UP.
  • the first N-type transistor 130 is connected between the third signal terminal and the second complementary sense bit line ISABLB, and has a control terminal connected to the first sense bit line SABL.
  • the third signal terminal is used for receiving the third level signal NCS_UP.
  • the first sense bit line SABL is connected to the bit line BL.
  • the second P-type transistor 120 is connected between the second signal terminal and the second sense bit line ISABL, and has a control terminal connected to the first complementary sense bit line SABLB.
  • the second signal terminal is used for receiving the second level signal PCS_DN.
  • the second N-type transistor is connected between the fourth signal terminal NCS_DN and the second sense bit line ISABL, and has a control terminal connected to the first complementary sense bit line SABLB.
  • the fourth signal terminal is used for receiving the fourth level signal NCS_DN.
  • the first complementary sense bit line SABLB is connected to the complementary bit line BLB.
  • the first offset cancel unit 210 is configured to connect the first sense bit line SABL to the second complementary sense bit line ISABLB in response to the first offset cancel signal OC1_UP.
  • the second offset cancel unit 220 is configured to connect the first complementary sense bit line SABLB to the second sense bit line ISABL in response to the second offset cancel signal OC1_DN.
  • the first write-back unit 310 is configured to connect the first complementary sense bit line SABLB to the second complementary sense bit line ISABLB in response to the first write-back signal OC2_UP.
  • the second write-back unit 320 is configured to connect the first sense bit line SABL to the second sense bit line ISABL in response to the second write-back signal OC2_DN.
  • the first P-type transistor 110 and the second P-type transistor 120 are respectively connected to different first signal terminals and second signal terminals, so as to receive high-level signals at different times.
  • the first N-type transistor 130 and the second N-type transistor 140 are respectively connected to different third signal terminals and fourth signal terminals, so as to receive low-level signals at different times.
  • the first offset canceling unit 210 and the second offset canceling unit 220 respond to the first offset canceling signal OC1_UP and the second offset canceling signal OC1_DN respectively, so that they can be controlled independently.
  • the first write-back unit 310 and the second write-back unit 320 respectively respond to the first write-back signal OC2_UP and the second write-back signal OC2_DN, so that they can be independently controlled. Therefore, this embodiment can effectively reduce energy consumption caused by offset cancellation.
  • the process of reading the data of the storage unit by the sense amplifier circuit of this embodiment may include:
  • bit line BL, the first read bit line SABL, the complementary bit line BLB, and the first complementary read bit line SABLB are pre-charged;
  • a high level signal and a low level signal are respectively provided for the first signal terminal and the third signal terminal, and at the same time, the first offset elimination unit 210 is turned on, thereby connecting the first readout bit line SABL to the second Complementary read bit line ISABLB, which makes the gate and drain of the first N-type transistor electrically connected;
  • the first offset canceling unit 210 is turned off, the storage unit is turned on, and the first write-back unit 310 is turned on, so as to connect the first complementary read bit line SABLB to the second complementary read bit line ISABLB;
  • a high-level signal and a low-level signal are respectively provided for the second signal terminal and the fourth signal terminal, and at the same time, the first write-back unit 310 and the second write-back unit 320 are turned on, so that the first read bit line SABL connected to the second sense bit line ISABL, and the first mutual sense bit line SABLB is connected to the second complementary sense bit line ISABLB.
  • the first signal terminal, the second signal terminal, the third signal terminal and the fourth signal terminal can also be pre-charged at the same time.
  • the precharge voltage can be
  • a high-level signal and a low-level signal are respectively provided for the first signal terminal and the third signal terminal, that is, the first level signal PCS_UP can be a high-level signal, and the third level signal NCS_UP is a low-level signal.
  • the third level signal NCS_UP may be 0, and the first level signal PCS_UP may be VDD.
  • the first offset cancellation signal OC1_UP is provided, thereby turning on the first offset cancellation unit 210 .
  • the potential of the second complementary read bit line ISABLB between the first P-type transistor 110 and the first N-type transistor 130 is pulled down at this time.
  • the second complementary read bit line ISABLB is connected to the first read bit line SABL when the first offset canceling unit 210 is turned on, that is, the gate and drain of the first N-type transistor are electrically connected, so that the first read The potential of the bit line SABL is pulled low.
  • the first read bit line SABL is connected to the control terminals of the first P-type transistor 110 and the first N-type transistor 130, and the first read bit line SABL is connected to the bit line BL, thereby effectively canceling the connection between the first N-type transistor and the first N-type transistor. Offset noise caused by different conduction capabilities of the first P-type transistors.
  • the third signal terminal is independent of the first signal terminal
  • the fourth signal terminal is independent of the second signal terminal
  • the first offset canceling unit 210 and the second offset canceling unit 220 respectively respond to different The offset-cancelled signal.
  • the third signal terminal and the fourth signal terminal may not be provided with electrical signals, but maintained at the precharge voltage, for example.
  • the first offset cancellation signal OC1_UP is provided to turn on the first offset cancellation unit 210
  • the second offset cancellation signal OC1_DN is not provided to turn on the second offset cancellation unit 220 . Therefore, at this time, offset cancellation may not be performed on the side of the complementary bit line BLB, thereby effectively reducing energy consumption caused by offset cancellation.
  • the first offset cancellation signal OC1_UP may be stopped to turn off the first offset cancellation unit 210 , thereby disconnecting the first sense bit line SABL from the second complementary sense bit line ISABLB.
  • the word line WL signal is provided to select and turn on the memory cell, so that the data signal stored in the memory cell is read out to the bit line BL, and transmitted to the first read bit line SABL through the bit line BL.
  • the memory cell when the memory cell stores a low-level signal corresponding to logic "0", the low-level signal corresponding to logic "0" will be superimposed on the signal on the first read bit line SABL, so as to The signal on the first sense bit line SABL is pulled low.
  • high-level signals are provided for the first signal terminal and the second signal terminal, and low-level signals are respectively provided for the third signal terminal and the fourth signal terminal, that is, the first-level signal PCS_UP and the second-level signal can be
  • the flat signal PCS_DN is a high-level signal
  • the third-level signal NCS_UP and the fourth-level signal NCS_DN are low-level signals.
  • the third level signal NCS_UP and the fourth level signal NCS_DN may be 0, and the first level signal PCS_UP and the second level signal PCS_DN may be VDD.
  • the first write-back signal OC1_UP and the second write-back signal OC2_DN may be provided at a high level to turn on the first write-back unit 310 and the second write-back unit 320 .
  • the first read bit line SABL is connected to the second read bit line ISABL and the bit line BL, so that the signal on the bit line BL is effectively amplified, and the memory cell is written back so that the stored potential is at Returns to the original value after charge sharing.
  • the second complementary sense bit line ISABLB is connected to the first complementary sense bit line SABLB and the complementary bit line BLB, so that the signal on the complementary bit line BLB is effectively amplified.
  • the amplified signal on the bit line BL repeatedly acts on the gates of the first P-type transistor 110 and the first N-type transistor 130 , thereby continuously amplifying the signal on the complementary bit line BLB.
  • the amplified signal on the complementary bit line BLB repeatedly acts on the gates of the second P-type transistor 120 and the second N-type transistor 140 , thereby continuously amplifying the signal on the bit line BL.
  • the pre-charging stage can be entered again, so as to read data next time.
  • the process of reading the data of the storage unit by the sense amplifier circuit of the present embodiment has been listed above.
  • the sense amplifier circuit of the present embodiment is used to read the data of the complementary memory unit, in the phase of offset elimination, by Provide a high-level signal and a low-level signal for the second signal terminal and the fourth signal terminal respectively, and provide the second offset cancellation signal OC1_DN at the same time, so as to open the second offset cancellation unit 220, thereby effectively canceling the second N-type
  • the offset noise caused by the different conduction capabilities of the transistor and the second P-type transistor can further reduce power consumption.
  • the process of reading the data of the complementary storage unit is similar to the process of reading the data of the storage unit, and will not be repeated here.
  • the third signal terminal connected to the second P-type transistor 120 is independent from the first signal terminal connected to the first P-type transistor 110
  • the fourth signal terminal connected to the second N-type transistor 140 is independent from the first N-type transistor 140.
  • the second signal terminal connected to the type transistor 130 , and the first offset canceling unit 210 and the second offset canceling unit 220 respectively respond to different offset canceling signals. Therefore, in the phase of offset elimination, only the first P-type transistor 110 and the first N-type transistor 130 or the second P-type transistor 120 and the second N-type transistor 140 can be eliminated, so that the P The offset noise caused by the different conduction capabilities of the N-type transistor and the N-type transistor can effectively reduce the offset elimination power consumption.
  • the sense amplifier circuit further includes a first isolation unit 410 and a second isolation unit 420 .
  • the first isolation unit 410 is configured to connect the bit line BL to the first sense bit line SABL in response to the first isolation signal ISO_UP.
  • the second isolation unit 420 is configured to connect the complementary bit line BLB to the first complementary sense bit line SABLB in response to the second isolation signal ISO_DN.
  • the first isolation signal ISO_UP may be provided all the time, so that the first isolation unit 410 is always on.
  • the bit line BL is always connected to the first read bit line SABL. Therefore, in the phase of offset cancellation, when the potential of the first readout bit line SABL is pulled down, the potential of the bit line BL is also pulled down, so that the offset cancellation can be performed more reliably.
  • the second isolation signal ISO_DN can be provided during the pre-charging phase and the amplification phase, so as to turn on the second isolation unit 420 .
  • the precharge phase the second isolation unit 420 is turned on, so that the complementary bit line BLB and the first complementary sense bit line SABLB can be precharged.
  • the second isolation unit 420 is turned on, so that the voltages on the complementary bit line BLB and the bit line BL can be amplified simultaneously.
  • the layout of the sense amplifier circuit has a first device area A1 and a second device area A2 .
  • the first device region A1 includes a first P-type active layer 111 , a first gate layer 112 , a first N-type active layer 131 and a third gate layer 132 .
  • the first gate layer 112 is disposed on the first P-type active layer 111 and used to form the first P-type transistor 110 with the first P-type active layer 111 .
  • the third gate layer 132 is disposed on the first N-type active layer 131 and used to form the first N-type transistor 130 with the first N-type active layer 131 .
  • the second device region A2 includes a second P-type active layer 121 , a second gate layer 122 , a second N-type active layer 141 and a fourth gate layer 142 .
  • the second gate layer 122 is disposed on the second P-type active layer 121 and used to form the second P-type transistor 120 with the second P-type active layer 121 .
  • the fourth gate layer 142 is disposed on the second N-type active layer 141 and used to form the second N-type transistor 140 together with the second N-type active layer 141 .
  • the first P-type transistor 110 and the first N-type transistor 130 are formed in the same device region, so as to facilitate the first offset elimination unit 210 to correct the first
  • the P-type transistor 110 and the first N-type transistor 130 perform an offset cancellation operation.
  • the second P-type transistor 120 and the second N-type transistor 140 are formed in the same device region, so that the second P-type transistor 120 and the second N-type transistor 140 can be compared with the second P-type transistor 120 through the second offset elimination unit 220 during the process of reading the complementary memory cells.
  • the two N-type transistors 140 perform an offset cancellation operation.
  • the first P-type active layer 111 and the second P-type active layer 121 are located on the first N-type active layer. Between the layer 131 and the second N-type active layer 141, or the first N-type active layer 131 and the second N-type active layer 141 are located between the first P-type active layer 111 and the second P-type active layer 121 between.
  • the layout of the sense amplifier circuit structure further has a third device area A3 and a fourth device area A4 .
  • the third device region A3 includes the first active layer 10 and the first isolation gate layer 411 .
  • the first isolation gate layer 411 is disposed on the first active layer 10 .
  • the first isolation gate layer 411 is used to form a first isolation unit 410 with the first active layer 10 .
  • the fourth device region A4 includes the second active layer 20 and the second isolation gate layer 421 , and the second isolation gate layer 421 is disposed on the second active layer 20 . Moreover, the second isolation gate layer 421 is used to form a second isolation unit 420 with the second active layer 20 .
  • the first device region A1 and the second device region A2 are located between the third device region A3 and the fourth device region A4. That is, the third device region A3 and the fourth device region A4 are located on both sides, so that it is convenient to connect the first isolation unit 410 to the bit line BL, and it is convenient to connect the second isolation unit 420 to the complementary bit line BLB, thereby reducing Small trace length saves layout space.
  • the third device region A3 further includes a first offset elimination gate layer 211 and a first write-back gate layer 311 . Both the first offset elimination gate layer 211 and the first write-back gate layer 311 are disposed on the first active layer 10 .
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the first active layer 10 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the first active layer 10 .
  • the first offset canceling unit 210 , the first write-back unit 310 and the first isolation unit 410 can be connected through the first active layer 10 , thereby effectively saving the circuit area.
  • the fourth device region A4 further includes a second offset elimination gate layer 221 and a second write-back gate layer 321 . Both the second offset elimination gate layer 221 and the second write-back gate layer 321 are disposed on the second active layer 20 .
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the second active layer 20
  • the second write-back gate layer 321 is used to form a second write-back unit with the second active layer 20 320.
  • the second offset canceling unit 220 , the second write-back unit 320 and the second isolation unit 420 can be connected through the second active layer 20 , thereby effectively saving the circuit area.
  • the first device region A1 further includes a third active layer 30 , a first offset elimination gate layer 211 and a first write-back gate layer 311 .
  • the first offset elimination gate layer 211 and the first write-back gate layer 311 are disposed on the third active layer 30 .
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the third active layer 30 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the third active layer 30 .
  • the first offset canceling unit 210 may be connected to the first write-back unit 310 through the third active layer 30 .
  • the third active layer 30 is located between the first P-type active layer 111 and the first N-type active layer 131, so that the first offset canceling unit 210 and the first write-back unit 310 are located in the first P-type active layer 111 and the first N-type active layer 131. between the transistor 110 and the first N-type transistor 130, so as to facilitate connecting the first offset canceling unit 210, the first write-back unit 310, the first P-type transistor 110 and the first N-type transistor 130 to the second complementary readout bit line ISABLB.
  • the second device region A2 further includes a fourth active layer 40 , a second offset elimination gate layer 221 and a second write-back gate layer 321 .
  • the second offset elimination gate layer 221 and the second write-back gate layer 321 are disposed on the fourth active layer 40 .
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the fourth active layer 40 .
  • the second write-back gate layer 321 and the fourth active layer 40 are used to form the second write-back unit 320 .
  • the second offset canceling unit 220 may be connected to the second write-back unit 320 through the fourth active layer 40 .
  • the fourth active layer 40 is located between the second P-type active layer 121 and the second N-type active layer 141, so that the second offset canceling unit 220 and the second write-back unit 320 are located in the second P-type active layer 121 and the second N-type active layer 141. between the transistor 120 and the second N-type transistor 140, so as to facilitate connecting the second offset canceling unit 220, the second write-back unit 320, the second P-type transistor 120 and the second N-type transistor 140 to the second readout position Line ISABL.
  • the layout of the sense amplifier circuit further has a fifth device region A5 .
  • the fifth device region A5 is located between the first device region A1 and the second device region A2, and includes a fifth active layer 50, a first offset elimination gate layer 211, a first write-back gate layer 311, a second The offset elimination gate layer 221 and the second write-back gate layer 321 .
  • the first offset elimination gate layer 211, the first write-back gate layer 311, and the second offset elimination gate layer 221 and the second write-back gate layer 321 are sequentially disposed on the fifth active layer 50 at intervals.
  • FIG. 9 or FIG. 11 along the direction from the first device region A1 to the second device region A2, the first write-back gate layer 311, the first offset elimination gate layer 211, and the second write-back gate layer 321 And the second offset elimination gate layer 221 is successively disposed on the fifth active layer 50 at intervals.
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the fifth active layer 50 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the fifth active layer 50 .
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the fifth active layer 50 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the fifth active layer 50 .
  • the first offset cancellation unit 210 , the first write-back unit 310 , the second offset cancellation unit 220 and the second write-back unit 320 may be connected through the fifth active layer 50 .
  • the first isolation unit 410 includes a first isolation transistor.
  • the number of first isolation transistors in the first isolation unit 410 may be multiple, or of course one.
  • the gate of the first isolation transistor is used to receive the first isolation signal ISO_UP.
  • the source of the first isolation transistor is connected to one of the bit line BL and the first read bit line SABL.
  • the drain of the first isolation transistor is connected to the other of the bit line BL and the first sense bit line SABL.
  • the second isolation unit 420 includes a second isolation transistor.
  • the number of the second isolation transistors in the second isolation unit 420 may be multiple, and certainly may be one.
  • the gate of the second isolation transistor is used to receive the second isolation signal ISO_DN, the source of the second isolation transistor is connected to one of the complementary bit line BLB and the first complementary read bit line SABLB, and the drain of the second isolation transistor
  • the complementary bit line BLB is connected to the other of the first complementary sense bit line SABLB.
  • first isolation transistor and/or the second isolation transistor may be an N-type transistor or a P-type transistor, which is not limited in this embodiment.
  • the sense amplifier circuit further includes a first pre-charge unit 510 , a second pre-charge unit 520 and a balance unit 530 .
  • the first precharge unit 510 is configured to connect the first sense bit line SABL to the precharge signal terminal in response to the precharge signal PRE.
  • the second precharge unit 520 is configured to connect the first complementary sense bit line SABLB to the precharge signal terminal in response to the precharge signal PRE.
  • the precharge signal terminal is used to receive the precharge voltage VBLP. Specifically, VBLP can be equal to
  • the balance unit 530 is configured to connect the first sense bit line SABL to the first complementary sense bit line SABLB in response to the balance signal EQ, thereby balancing the voltage therebetween.
  • the balance signal EQ and the precharge signal PRE may be provided to precharge the first sense bit line SABL and the first complementary sense bit line SABLB and balance the voltage between them.
  • the first pre-charging unit 510 includes a first pre-charging transistor.
  • the number of first pre-charging transistors in the first pre-charging unit 510 may be multiple or one.
  • the gate of the first pre-charge transistor is used for receiving the pre-charge signal PRE.
  • the source of the first pre-charge transistor is connected to one of the first read bit line SABL and the pre-charge signal terminal.
  • the drain of the first isolation transistor is connected to the other one of the first readout bit line SABL and the precharge signal terminal.
  • the second precharge unit 520 includes a second precharge transistor.
  • the number of second pre-charging transistors in the second pre-charging unit 520 may be multiple or one.
  • the gate of the second pre-charge transistor is used to receive the pre-charge signal PRE.
  • the source of the second pre-charge transistor is connected to one of the first complementary readout bit line SABLB and the pre-charge signal terminal.
  • the drain of the first pre-charge transistor is connected to the other one of the first complementary readout bit line SABLB and the pre-charge signal terminal.
  • the balancing unit 530 includes balancing transistors.
  • the number of balancing transistors in the balancing unit 530 may be multiple or one.
  • the gate of the balance transistor is used to receive the balance signal EQ.
  • the source of the first pre-fill transistor is connected to one of the first read bit line SABL and the first complementary read bit line SABLB, and the drain of the first isolation transistor is connected to the first read bit line SABL and the first complementary read bit line. The other of the bit lines SABLB is sensed.
  • the gates of the first precharge transistor, the second precharge transistor, and the balance transistor 530 are connected to the same control terminal, so that the precharge can be obtained through the control terminal at the same time.
  • Charge signal PRE and balance signal EQ. In this case, circuit control can be simplified.
  • the gates of the first pre-charging transistor, the second pre-charging transistor, and the balancing transistor 530 may also be connected to different control terminals, and there is no limitation here.
  • the third device region A3 further includes first The isolation gate layer 411 , the first offset elimination gate layer 211 , the first write-back gate layer 311 , the balance gate layer 531 , the first pre-charge gate layer 511 and the second pre-charge gate layer 521 .
  • the first isolation gate layer 411 is used to form a first isolation unit 410 with the first active layer 10 .
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the first active layer 10 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the first active layer 10 .
  • the balanced gate layer 531 is used to form a balanced unit 530 with the first active layer 10 .
  • the first pre-charged gate layer 511 is used to form a first pre-charged unit 510 with the first active layer 10 .
  • the second pre-charged gate layer 521 is used to form a second pre-charged unit 520 with the first active layer 10 .
  • the fourth device region A4 further includes a second isolation gate layer 421, a second offset elimination gate layer and a second offset elimination gate layer that are sequentially disposed on the second active layer 20 at intervals. 221 and the second write-back gate layer 321.
  • the second isolation gate layer 421 is used to form a second isolation unit 420 with the second active layer 20 .
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the second active layer 20 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the second active layer 20 .
  • the third device region A3 further includes first The isolation gate layer 411 , the first offset elimination gate layer 211 , the first write-back gate layer 311 , the first pre-charge gate layer 511 and the second pre-charge gate layer 521 .
  • the first isolation gate layer 411 is used to form a first isolation unit 410 with the first active layer 10 .
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the first active layer 10 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the first active layer 10 .
  • the first pre-charged gate layer 511 is used to form a first pre-charged unit 510 with the first active layer 10 .
  • the second pre-charged gate layer 521 is used to form a second pre-charged unit 520 with the first active layer 10 .
  • the fourth device region A4 further includes a second isolation gate layer 421, a second offset elimination gate layer and a second offset elimination gate layer that are sequentially disposed on the second active layer 20 at intervals. 221 , the second write-back gate layer 321 and the balance gate layer 531 .
  • the second isolation gate layer 421 is used to form a second isolation unit 420 with the second active layer 20 .
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the second active layer 20 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the second active layer 20 .
  • the balanced gate layer 531 is used to form a balanced unit 530 with the second active layer 20 .
  • the first device region A1 further includes a third active layer 30 , a first pre-charged gate layer 511 , a balanced gate layer 531 and a second pre-charged gate layer 521 .
  • the first pre-charged gate layer 511, the balanced gate layer 531 and the second pre-charged gate layer 521 are sequentially arranged on the third on the active layer 30.
  • the third active layer 30 is located between the first P-type active layer 111 and the first N-type active layer 131 .
  • the first pre-charged gate layer 511 is used to form a first pre-charged unit 510 with the third active layer 30 .
  • the balanced gate layer 531 is used to form a balanced unit 530 with the third active layer 30 .
  • the second pre-charge gate layer 521 is used to form a second pre-charge unit 520 with the third active layer 30 .
  • the third device region A3 further includes a first isolation gate layer 411, a first offset elimination gate layer and a first offset elimination gate layer that are sequentially disposed on the first active layer 10 at intervals. 211 and the first write-back gate layer 311.
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the first active layer 10 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the first active layer 10 .
  • the fourth device region A4 further includes a second isolation gate layer 421, a second offset elimination gate layer and a second offset elimination gate layer that are sequentially disposed on the second active layer 20 at intervals. 221 and the second write-back gate layer 321.
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the second active layer 20 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the second active layer 20 .
  • the layout of the sense amplifier circuit further has a fifth device area A5 .
  • the fifth device region A5 is located between the first device region A1 and the second device region A2.
  • the fifth device region A5 includes a fifth active layer 50 , a first pre-charge gate layer 511 , a balance gate layer 531 and a second pre-charge gate layer 521 .
  • the first pre-charge gate layer 511 , the balance gate layer 531 and the second pre-charge gate layer 521 are sequentially disposed on the fifth active layer 50 at intervals.
  • the first pre-charged gate layer 511 is used to form a first pre-charged unit 510 with the fifth active layer 50 .
  • the balanced gate layer 531 is used to form a balanced unit 530 with the fifth active layer 50 .
  • the second pre-charged gate layer 521 is used to form a second pre-charged unit 520 with the fifth active layer 50 .
  • the third device region A3 further includes a first isolation gate layer 411, a first offset elimination gate layer and a first offset elimination gate layer that are sequentially disposed on the first active layer 10 at intervals. 211 and the first write-back gate layer 311.
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the first active layer 10 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the first active layer 10 .
  • the fourth device region A4 further includes a second isolation gate layer 421, a second offset elimination gate layer and a second offset elimination gate layer that are sequentially disposed on the second active layer 20 at intervals. 221 and the second write-back gate layer 321.
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the second active layer 20 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the second active layer 20 .
  • the first device region A1 further includes a third active layer 30 , a first offset elimination gate layer 211 , a first write-back gate layer 311 , and a balance gate layer 531 , the second write-back gate layer 321 and the second offset elimination gate layer 221, along the direction of the first P-type active layer 111 pointing to the first N-type active layer 131, the first offset elimination gate layer 211 , the first write-back gate layer 311 , the balance gate layer 531 , the second write-back gate layer 321 and the second offset-elimination gate layer 221 are sequentially arranged on the third active layer 30 at intervals.
  • the third active layer 30 is located between the first P-type active layer 111 and the first N-type active layer 131 .
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the third active layer 30 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the third active layer 30 .
  • the balanced gate layer 531 is used to form a balanced unit 530 with the third active layer 30 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the third active layer 30 .
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the third active layer 30 .
  • the third device region A3 also includes a first pre-charged gate layer 511 disposed on the first active layer 10 .
  • the first pre-charged gate layer 511 is used to form a first pre-charged unit 510 with the first active layer 10 .
  • the fourth device region A4 also includes a second pre-charged gate layer 521 disposed on the second active layer 20 .
  • the second pre-charged gate layer 521 is used to form a second pre-charged unit 520 with the second active layer 20 .
  • the layout of the sense amplifier circuit further has a fifth device area A5 .
  • the fifth device region A5 is located between the first device region A1 and the second device region A2.
  • the fifth device region A5 includes a fifth active layer 50, a first offset elimination gate layer 211, a first write-back gate layer 311, a balance gate layer 531, a second write-back gate layer 321, and a first write-back gate layer 321.
  • Two offset elimination gate layers 221 Two offset elimination gate layers 221 .
  • the first offset elimination gate layer 211, the first write-back gate layer 311, the balance gate layer 531, the second write-back gate layer 321 and the first are sequentially disposed on the fifth active layer 50 at intervals.
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the fifth active layer 50 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the fifth active layer 50 .
  • the balanced gate layer 531 is used to form a balanced unit 530 with the fifth active layer 50 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the fifth active layer 50 .
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the fifth active layer 50 .
  • the third device region A3 also includes a first pre-charged gate layer 511 disposed on the first active layer 10 .
  • the first pre-charged gate layer 511 is used to form a first pre-charged unit 510 with the first active layer 10 .
  • the fourth device region A4 also includes a second pre-charged gate layer 521 disposed on the second active layer 20 .
  • the second pre-charged gate layer 521 is used to form a second pre-charged unit 520 with the second active layer 20 .
  • the first device region A1 further includes a third active layer 30, a first write-back gate layer 311, a first offset elimination gate layer 211, a balance gate layer 531 and the second pre-charged gate layer 521 .
  • the first write-back gate layer 311, the first offset elimination gate layer 211, the balance gate layer 531 and the second pre-charge gate layer 521 are sequentially spaced disposed on the third active layer 30 .
  • the third active layer 30 is located between the first P-type active layer 111 and the first N-type active layer 131 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the third active layer 30 .
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the third active layer 30 .
  • the balanced gate layer 531 is used to form a balanced unit 530 with the third active layer 30 .
  • the second pre-charged gate layer 511 is used to form a second pre-charged unit 510 with the third active layer 30 .
  • the second device region A2 also includes a fourth active layer 40, a second offset elimination gate layer 221, a second write-back gate layer 321, and a first pre-charge gate layer 511, pointing to the second device region A2 along the second device region A2.
  • the second offset elimination gate layer 221 , the second write-back gate layer 321 and the first pre-charge gate layer 511 are successively disposed on the fourth active layer 40 at intervals.
  • the fourth active layer 40 is located between the second P-type active layer 121 and the second N-type active layer 141 .
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the fourth active layer 40 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the fourth active layer 40 .
  • the first pre-charged gate layer 511 is used to form a first pre-charged unit 510 with the fourth active layer 40 .
  • the layout of the sense amplifier circuit further has a fifth device region A5 .
  • the fifth device region A5 is located between the first device region A1 and the second device region A2.
  • the fifth device region A5 includes a fifth active layer 50, a first write-back gate layer 311, a first offset elimination gate layer 211, a balance gate layer 531, a second pre-charge gate layer 521, a first A precharge gate layer 511 , a second write-back gate layer 321 and a second offset elimination gate layer 221 .
  • the first write-back gate layer 311, the first offset elimination gate layer 211, the balance gate layer 531, the second pre-charge gate layer 521, the first A pre-charge gate layer 511 , a second write-back gate layer 321 and a second offset-elimination gate layer 221 are disposed on the fifth active layer 50 at intervals in sequence.
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the fifth active layer 50 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the fifth active layer 50 .
  • the balanced gate layer 531 is used to form a balanced unit 530 with the fifth active layer 50 .
  • the first pre-charged gate layer 511 is used to form a first pre-charged unit 510 with the fifth active layer 50 .
  • the second pre-charged gate layer 521 is used to form a second pre-charged unit 520 with the fifth active layer 50 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the fifth active layer 50 .
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the fifth active layer 50 .
  • the sense amplifier circuit further includes a third pre-charge unit 540 and a balance unit 530 .
  • the third precharge unit 540 is configured to connect the first complementary sense bit line SABLB or the first sense bit line SABL to the precharge signal terminal in response to the precharge signal PRE.
  • the balance unit 520 is configured to connect the first sense bit line SABL to the first complementary sense bit line SABLB in response to the balance signal EQ.
  • a precharge signal PRE may be provided to turn on the third precharge unit 540 to precharge the first complementary sense bit line SABLB or the first sense bit line SABL.
  • the precharging for the first complementary read bit line SABLB by turning on the third precharging unit 540 is taken as an example for illustration.
  • the balance signal EQ is provided to turn on the balance unit 530 .
  • the first sense bit line SABL is connected to the first complementary sense bit line SABLB, so that the precharge is also performed while the first complementary sense bit line SABLB is being precharged, and the first sense bit line SABL It is balanced with the potential of the first complementary read bit line SABLB.
  • the third pre-charging unit 540 includes a third pre-charging transistor.
  • the number of third pre-charging transistors in the third pre-charging unit 540 may be multiple or one.
  • the gate of the third pre-fill transistor is used to receive the pre-fill signal, the source of the third pre-fill transistor is connected to one of the first read bit line SABL and the pre-fill signal terminal, and the drain of the third pre-fill transistor
  • the first sense bit line SABL is connected to the other one of the precharge signal terminals.
  • the gate of the third pre-fill transistor is used to receive the pre-charge signal
  • the source of the third pre-fill transistor is connected to one of the first complementary readout bit line SABLB and the pre-charge signal terminal
  • the third pre-fill transistor The drain of the first complementary readout bit line SABLB is connected to the other one of the precharge signal terminal.
  • the balancing unit 530 includes balancing transistors.
  • the gate of the balance transistor is used to receive the balance signal EQ.
  • the source of the balance transistor is connected to one of the first read bit line SABL and the first complementary read bit line SABLB, and the drain of the first isolation transistor is connected to the first read bit line SABL and the first complementary read bit The other in line SABLB.
  • the gate of the third pre-charge transistor and the gate of the balance transistor are connected to the same control terminal, so that the pre-charge signal PRE and the balance signal EQ can be obtained through the control terminal at the same time.
  • circuit control can be simplified.
  • the gate of the third pre-charge transistor and the gate of the balance transistor 530 may also be connected to different control terminals, and there is no limitation here.
  • the third device region A3 further includes a first offset elimination gate layer 211 disposed on the first active layer 10, a first back gate layer Write the gate layer 311 and the third pre-charged gate layer 541 .
  • the third device region A3 includes a first isolation gate layer 411 and a first offset elimination gate layer 211 which are sequentially disposed on the first active layer 10 at intervals. , the first write-back gate layer 311 and the third pre-charge gate layer 541 .
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the first active layer 10 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the first active layer 10 .
  • the first pre-charged gate layer is used to form a third pre-charged unit 540 with the first active layer 10 .
  • the fourth device region A4 further includes a second offset elimination gate layer 221 , a second write-back gate layer 321 and a balance gate layer 531 disposed on the second active layer 20 .
  • the fourth device region A4 includes a second isolation gate layer 421, a second isolation gate layer 421, and a Two offset elimination gate layers 221 , a second write-back gate layer 321 and a balance gate layer 531 .
  • the fourth device region A4 includes a second isolation gate layer 421, a balance layer, and a balance layer arranged on the second active layer 20 in sequence.
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the second active layer 20 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the second active layer 20 .
  • the balanced gate layer 531 is used to form a balanced unit with the second active layer 20 .
  • the first device region A1 further includes a third active layer 30, a first offset elimination gate layer 211, a first write-back gate layer 311 , the third pre-charged gate layer 541 .
  • the first offset elimination gate layer 211, the first write-back gate layer 311 and the third pre-charge gate layer 541 are disposed on the third active layer 30 at intervals in sequence.
  • the third pre-charge gate layer 541, the first write-back gate layer 311 and the first offset elimination gate layer 211 are disposed on the third active layer 30 at intervals in sequence.
  • the third active layer 30 is located between the first P-type active layer 111 and the first N-type active layer 131 .
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the third active layer 30 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the third active layer 30 .
  • the third pre-charged gate layer 541 is used to form a third pre-charged unit 540 with the third active layer 30 .
  • the second device region A2 further includes a fourth active layer 40 , a second offset elimination gate layer 221 , a second write-back gate layer 321 and a balance gate layer 531 .
  • a fourth active layer 40 along the direction from the second device region A2 to the first device region A1, the second offset elimination gate layer 221 , the second write-back gate layer 321 and the balance gate layer 531 are sequentially arranged at intervals. on the fourth active layer 40 .
  • the balance gate layer 531 , the second write-back gate layer 321 and the second offset elimination gate layer 221 are sequentially arranged at intervals. on the fourth active layer 40 .
  • the fourth active layer 40 is located between the second P-type active layer 121 and the second N-type active layer.
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the fourth active layer 40 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the fourth active layer 40 .
  • the balanced gate layer 531 is used to form a balanced unit with the fourth active layer 40 .
  • the first device region A1 further includes a third active layer 30, a first offset elimination gate layer 211, a first write-back gate Layer 311 and balanced gate layer 531 .
  • the first offset elimination gate layer 211, the first write-back gate layer 311 and the balance gate layer 531 are sequentially arranged at intervals on the third active layer 30 .
  • the balance gate layer 531, the first write-back gate layer 311, and the first offset elimination gate layer 211 are sequentially arranged at intervals on the third active layer 30 .
  • the third active layer 30 is located between the first P-type active layer 111 and the first N-type active layer 131 .
  • the first offset elimination gate layer 211 is used to form a first offset elimination unit 210 with the third active layer 30 .
  • the first write-back gate layer 311 is used to form a first write-back unit 310 with the third active layer 30 .
  • the balanced gate layer 531 is used to form a balanced unit with the third active layer 30 .
  • the second device region further includes a fourth active layer 40 , a second offset elimination gate layer 221 , a second write-back gate layer 321 and a third precharge gate layer 541 .
  • the second offset elimination gate layer 221 , the second write-back gate layer 321 and the third precharge gate layer 541 are disposed on the fourth active layer 40 .
  • the third pre-charge gate layer 541, the second offset elimination gate layer 221 and the second write-back gate layer 321 They are sequentially disposed on the fourth active layer 40 at intervals.
  • the second write-back gate layer 321, the second offset elimination gate layer 221 and the third pre-charge gate layer 541 They are sequentially disposed on the fourth active layer 40 at intervals.
  • the fourth active layer 40 is located between the second P-type active layer 121 and the second N-type active layer 141 .
  • the second offset elimination gate layer 221 is used to form a second offset elimination unit 220 with the fourth active layer 40 .
  • the second write-back gate layer 321 is used to form a second write-back unit 320 with the fourth active layer 40 .
  • the third pre-charge gate layer 541 is used to form a third pre-charge unit 540 with the fourth active layer 40 .
  • the first offset cancellation unit 210 includes a first offset cancellation transistor.
  • the number of first offset elimination transistors in the first offset elimination unit 210 may be multiple or one.
  • the gate of the first offset cancellation transistor is used to receive the first offset cancellation signal OC1_UP, and the source of the first offset cancellation transistor is connected to one of the first read bit line SABL and the second complementary read bit line ISABLB Alternatively, the drain of the first offset cancellation transistor is connected to the other of the first sense bit line SABL and the second complementary sense bit line ISABLB.
  • the second offset canceling unit 220 includes a second offset canceling transistor.
  • the number of second offset elimination transistors in the second offset elimination unit 220 can be multiple or one.
  • the gate of the second offset cancellation transistor is used to receive the second offset cancellation signal OC1_DN, and the source of the second offset cancellation transistor is connected to one of the first complementary read bit line SABLB and the second read bit line ISABL Alternatively, the drain of the second offset cancellation transistor is connected to the other one of the first complementary sense bit line SABLB and the second sense bit line ISABL.
  • the first write-back unit 310 includes a first write-back transistor.
  • the number of first write-back transistors in the first write-back unit 310 may be multiple or one.
  • the gate of the first write-back transistor is used to receive the first write-back signal OC2_UP, the source of the first write-back transistor is connected to one of the first complementary read bit line SABLB and the second complementary read bit line ISABLB, The drain of the first write-back transistor is connected to the other of the first complementary read bit line SABLB and the second complementary read bit line ISABLB.
  • the second write-back unit 320 includes a second write-back transistor.
  • the number of second write-back transistors in the second write-back unit 320 may be multiple or one.
  • the gate of the second write-back transistor is used to receive the second write-back signal OC2_DN, the source of the second write-back transistor is connected to one of the first read bit line SABL and the second read bit line ISABL, and the second The drain of the write-back transistor is connected to the other one of the first sense bit line SABL and the second sense bit line ISABL.
  • a data readout method including:
  • bit line BL, the first read bit line SABL, the complementary bit line BLB, and the first complementary read bit line SABLB are pre-charged;
  • a high level signal and a low level signal are respectively provided for the first signal terminal and the third signal terminal, and at the same time, the first offset elimination unit 210 is turned on, thereby connecting the first readout bit line SABL to the second complementary sense bit line ISABLB;
  • the first offset canceling unit 210 is turned off, the storage unit is turned on, and the first write-back unit 310 is turned on, so as to connect the first complementary read bit line SABLB to the second complementary read bit line ISABLB;
  • a high-level signal is provided for the first signal terminal and the second signal terminal
  • a low-level signal is provided for the third signal terminal and the fourth signal terminal
  • the second write-back unit 320 is turned on at the same time, so that the first read-out
  • the bit line SABL is connected to the second sense bit line ISABL.

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Abstract

本公开涉及一种感测放大电路及数据读出方法。其中，感测放大电路，包括：第一P型晶体管，其连接在第一信号端；第二P型晶体管，其连接在第二信号端；第一N型晶体管，其连接在第三信号端；第二N型晶体管，其连接在第四信号端；第一偏移消除单元，其被构造为响应于第一偏移消除信号将第一读出位线连接到第二互补读出位线；第二偏移消除单元，其被构造为响应于第二偏移消除信号将第一互补读出位线连接到第二读出位线；第一回写单元，其被构造为响应于第一回写信号将第一互补读出位线连接到第二互补读出位线；第二回写单元，其被构造为响应于第二回写信号将第一读出位线连接到第二读出位线。本公开可以有效降低偏移消除而产生的能耗。

Description

感测放大电路以及数据读出方法
相关申请的交叉引用
本公开要求于2021年11月24日提交中国专利局、申请号为2021114054257、发明名称为“感测放大电路以及数据读出方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及集成电路技术领域，特别是涉及一种感测放大电路以及数据读出方法。
背景技术
在对存储器件的存储单元进行读取操作时，通常通过感测放大器读出并放大位线与互补位线之间的电压差。感测放大器通常通过两个N型晶体管与两个P型晶体管构成锁存放大电路结构，从而对其两端连接的位线与补偿位线上的信号进行放大。但是，当前工艺条件下形成的N型晶体管和P型晶体管的导通能力通常存在差异，从而可能会导致读取失败。
相关技术中，有在打开字线而读取存储单元内的数据之前对各个晶体管进行偏移消除的方式，从而防止读取错误。然而，目前的偏移消除方式通常会产生较大能耗。
发明内容
根据本公开的各种实施例，提供一种感测放大电路以及数据读出方法。
根据本公开的各种实施例，提供一种感测放大电路，包括：
第一P型晶体管，其连接在第一信号端和第二互补读出位线之间，并且具有连接到第一读出位线的控制端子，所述第一读出位线与位线连接；
第二P型晶体管，其连接在第二信号端和第二读出位线之间，并且具有连接到第一互补读出位线的控制端子，所述第一互补读出位线与互补位线连接；
第一N型晶体管，其连接在第三信号端和所述第二互补读出位线之间，并且具有连接到所述第一读出位线的控制端子；
第二N型晶体管，其连接在第四信号端和所述第二读出位线之间，并且具有连接到所述第一互补读出位线的控制端子；
第一偏移消除单元，其被构造为响应于第一偏移消除信号将所述第一读出位线连接到所述第二互补读出位线；
第二偏移消除单元，其被构造为响应于第二偏移消除信号将所述第一互补读出位线连接到所述第二读出位线；
第一回写单元，其被构造为响应于第一回写信号将所述第一互补读出位线连接到所述第二互补读出位线。
一种数据读出方法，应用于上述的感测放大电路，包括：
预充阶段，对位线、第一读出位线、互补位线、第一互补读出位线进行预充；
偏移消除阶段，为第一信号端与第三信号端分别提供高电平信号与低电平信号，同时打开第一偏移消除单元，从而将所述第一读出位线连接到所述第二互补读出位线；
电荷共享阶段，关断第一偏移消除单元，打开存储单元，且打开第一回写单元，从而 将第一互补读出位线连接到所述第二互补读出位线；
放大阶段，为所述第一信号端和第二信号端提供高电平信号，为所述第三信号端和第四信号端低电平信号，同时打开第二回写单元，从而将第一读出位线连接到所述第二读出位线。
本公开实施例可以/至少具有以下优点：
第二P型晶体管连接的第三信号端独立于第一P型晶体管连接的第一信号端，第二N型晶体管连接的第四信号端独立于第一N型晶体管连接的第二信号端，且第一偏移消除单元与第二偏移消除单元分别响应于不同的偏移消除信号。因此，在偏移消除阶段，可以只对第一P型晶体管与第一N型晶体管或第二P型晶体管与第二N型晶体管进行偏移消除，从而既可以有效地消除P型晶体管与N型晶体管导通能力不同造成的偏移噪声，又可以有效降低偏移消除功耗。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中提供的感测放大电路的电路示意图；
图2为另一实施例中提供的感测放大电路的电路示意图；
图3为一实施例对存储单元进行读取时，感测放大电路的各个控制信号的时序示意图；
图4至图11为不同实施例中，对应图1所示感测放大电路的电路示意图的结构示意图；
图12为又一实施例中提供的感测放大电路的电路示意图；
图13至图24为不同实施例中，对应图12所示感测放大电路的电路示意图的结构示意图；
图25为再一实施例中提供的感测放大电路的电路示意图；
图26至图37为不同实施例中，对应图25所示感测放大电路的电路示意图的结构示意图。
附图标记说明：110-第一P型晶体管，111-第一P型有源层，112-第一栅极层，120-第二P型晶体管，121-第二P型有源层，122-第二栅极层，130-第一N型晶体管，131-第一N型有源层，132-第三栅极层，140-第二N型晶体管，141-第二N型有源层，142-第四栅极层，210-第一偏移消除单元，211-第一偏移消除栅极层，220-第二偏移消除单元，221-第二偏移消除栅极层，310-第一回写单元，311-第一回写栅极层，320-第二回写单元，321-第二回写栅极层，410-第一隔离单元，411-第一隔离栅极层，420-第二隔离单元，421-第二隔离栅极层，510-第一预充单元，511-第一预充栅极层，520-第二预充单元，521-第二预充栅极层，530-平衡单元，531-平衡栅极层，540-第三预充单元，541-第三预充栅极层，10-第一有源层，20-第二有源层，30-第三有源层，40-第四有源层，50-第五有源层。
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本公开的公开内容更加透彻全面。
在一个实施例中，请参阅图1或图2，提供一种感测放大电路，包括第一P型晶体管110、第二P型晶体管120、第一N型晶体管130、第二N型晶体管140、第一偏移消除单元210、第二偏移消除单元220、第一回写单元310以及第二回写单元320。
第一P型晶体管110、第二P型晶体管120、第一N型晶体管130、第二N型晶体管140形成放大单元。
其中，第一P型晶体管110连接在第一信号端和第二互补读出位线ISABLB之间，并且具有连接到第一读出位线SABL的控制端子。第一信号端用于接收第一电平信号PCS_UP。
第一N型晶体管130连接在第三信号端和第二互补读出位线ISABLB之间，并且具有连接到第一读出位线SABL的控制端子。第三信号端用于接收第三电平信号NCS_UP。
第一读出位线SABL与位线BL连接。
第二P型晶体管120连接在第二信号端和第二读出位线ISABL之间，并且具有连接到第一互补读出位线SABLB的控制端子。第二信号端用于接收第二电平信号PCS_DN。
第二N型晶体管连接在第四信号端NCS_DN和第二读出位线ISABL之间，并且具有连接到第一互补读出位线SABLB的控制端子。第四信号端用于接收第四电平信号NCS_DN。
第一互补读出位线SABLB与互补位线BLB连接。
第一偏移消除单元210被构造为响应于第一偏移消除信号OC1_UP将第一读出位线SABL连接到第二互补读出位线ISABLB。
第二偏移消除单元220被构造为响应于第二偏移消除信号OC1_DN将第一互补读出位线SABLB连接到第二读出位线ISABL。
第一回写单元310被构造为响应于第一回写信号OC2_UP将第一互补读出位线SABLB连接到第二互补读出位线ISABLB。
第二回写单元320被构造为响应于第二回写信号OC2_DN将第一读出位线SABL连接到第二读出位线ISABL。
在本实施例中，第一P型晶体管110与第二P型晶体管120分别连接至不同的第一信号端与第二信号端，从而可以在不同的时间接收高电平信号。同时，第一N型晶体管130与第二N型晶体管140分别连接至不同的第三信号端与第四信号端，从而可以在不同的时间接收低电平信号。
同时，第一偏移消除单元210与第二偏移消除单元220分别响应于第一偏移消除信号OC1_UP与第二偏移消除信号OC1_DN，从而可以分别独立控制。同时，第一回写单元310与第二回写单元320分别响应于第一回写信号OC2_UP与第二回写信号OC2_DN，从而可以分别独立控制。因此，本实施例可以有效降低偏移消除而产生的能耗。
作为示例，请参阅图2以及图3，利用本实施例的感测放大电路对存储单元的数据的读取过程可以包括：
预充阶段，对位线BL、第一读出位线SABL、互补位线BLB、第一互补读出位线SABLB进行预充；
偏移消除阶段，为第一信号端与第三信号端分别提供高电平信号与低电平信号，同时打开第一偏移消除单元210，从而将第一读出位线SABL连接到第二互补读出位线ISABLB，即使得第一N型晶体管的栅极和漏极电连接；
电荷共享阶段，关断第一偏移消除单元210，打开存储单元，且打开第一回写单元310，从而将第一互补读出位线SABLB连接到第二互补读出位线ISABLB；
放大阶段，为第二信号端与第四信号端分别提供高电平信号与低电平信号，同时打开第一回写单元310和第二回写单元320，从而将第一读出位线SABL连接到第二读出位线ISABL，将第一互读出位线SABLB连接到第二互补读出位线ISABLB。
在预充阶段，还可以同时对第一信号端、第二信号端、第三信号端以及第四信号端进行预充。具体地预充电压可以为
Figure PCTCN2022107640-appb-000001
在偏移消除阶段，为第一信号端与第三信号端分别提供高电平信号与低电平信号，即可以使得第一电平信号PCS_UP为高电平信号，而第三电平信号NCS_UP为低电平信号。第三电平信号NCS_UP具体地可以为0，而第一电平信号PCS_UP可以为VDD。同时，提供第一偏移消除信号OC1_UP，从而打开第一偏移消除单元210。
由于N型晶体管的导通能力大于P型晶体管的导通能力，因此此时第一P型晶体管110与第一N型晶体管130之间的第二互补读出位线ISABLB的电位被拉低。而第二互补读出位线ISABLB在第一偏移消除单元210打开时与第一读出位线SABL连接，即第一N型晶体管的栅极和漏极电连接，从而使得第一读出位线SABL的电位被拉低。
同时第一读出位线SABL连接第一P型晶体管110与第一N型晶体管130的控制端子，且第一读出位线SABL与位线BL连接，从而可以有效取消第一N型晶体管与第一P型晶体管的导通能力不同导致的偏移噪声。
同时，在本实施例中，第三信号端独立于第一信号端，第四信号端独立于第二信号端，且第一偏移消除单元210与第二偏移消除单元220分别响应于不同的偏移消除信号。
因此，在偏移消除阶段，可以不为第三信号端与第四信号端提供电信号，而使其维持在预充电压，例如为
Figure PCTCN2022107640-appb-000002
且在提供第一偏移消除信号OC1_UP而打开第一偏移消除单元210的同时，不提供第二偏移消除信号OC1_DN而不打开第二偏移消除单元220。因此，此时可以不对互补位线BLB一侧进行偏移消除，从而可以有效降低偏移消除而产生的能耗。
在电荷共享阶段，可以停止提供第一偏移消除信号OC1_UP，从而关断第一偏移消除单元210，从而将第一读出位线SABL与第二互补读出位线ISABLB断开。同时，提供字线WL信号，以选中打开存储单元，以将该存储单元存储的数据信号读出到位线BL，并经过位线BL传输至第一读出位线SABL。
具体地，作为示例，当存储单元存储的对应逻辑“0”的低电平信号时，对应逻辑“0”的低电平信号会与第一读出位线SABL上的信号叠加，从而以将第一读出位线SABL上的信号拉低。
在放大阶段，为第一信号端、第二信号端提供高电平信号，为第三信号端和第四信号端分别提供低电平信号，即可以使得第一电平信号PCS_UP和第二电平信号PCS_DN为高电平信号，而第三电平信号NCS_UP第四电平信号NCS_DN为低电平信号。第三电平信号NCS_UP和第四电平信号NCS_DN具体地可以为0，而第一电平信号PCS_UP和第二电平信号PCS_DN可以为VDD。
同时，可以提供第一回写信号OC1_UP和第二回写信号OC2_DN为高电平打开第一回写单元310和第二回写单元320。此时，第一读出位线SABL连接到第二读出位线ISABL以及位线BL，从而使得位线BL上的信号被有效放大，且对存储单元进行回写，使其存储的电位在电荷共享之后回复至原有值。此时，第二互补读出位线ISABLB连接至第一互补读出位线SABLB以及互补位线BLB，从而使得互补位线BLB上的信号被有效放大。
被放大后的位线BL上的信号反复作用于第一P型晶体管110与第一N型晶体管130 的栅极，从而持续放大互补位线BLB上的信号。于此同时，与被放大后的互补位线BLB上的信号反复作用于第二P型晶体管120与第二N型晶体管140的栅极，从而持续放大位线BL上的信号。
可以理解的是，在经过放大阶段之后，可以再次进入预充阶段，以便于进行下一次数据读取。
以上列举了利用本实施例的感测放大电路对存储单元的数据的读取过程，利用本实施例的感测放大电路对互补存储单元的数据的进行读取时，在偏移消除阶段，通过为第二信号端与第四信号端分别提供高电平信号与低电平信号，同时提供第二偏移消除信号OC1_DN，从而打开第二偏移消除单元220，从而可以有效取消第二N型晶体管与第二P型晶体管的导通能力不同导致的偏移噪声，进而能够降低功耗。本领域技术人员可以理解，对互补存储单元的数据的进行读取的过程与对存储单元的数据的读取过程类似，在此不再过多赘述。
在本实施例中，第二P型晶体管120连接的第三信号端独立于第一P型晶体管110连接的第一信号端，第二N型晶体管140连接的第四信号端独立于第一N型晶体管130连接的第二信号端，且第一偏移消除单元210与第二偏移消除单元220分别响应于不同的偏移消除信号。因此，在偏移消除阶段，可以只对第一P型晶体管110和第一N型晶体管130或者第二P型晶体管120和第二N型晶体管140进行偏移消除，从而既可以有效地消除P型晶体管与N型晶体管导通能力不同造成的偏移噪声，又可以有效降低偏移消除功耗。
在一个实施例中，请参阅图1或图2，感测放大电路还包括第一隔离单元410以及第二隔离单元420。
第一隔离单元410被构造为响应于第一隔离信号ISO_UP将位线BL连接到第一读出位线SABL。第二隔离单元420其被构造为响应于第二隔离信号ISO_DN将互补位线BLB连接到第一互补读出位线SABLB。
请参阅图3，利用本实施例的感测放大电路对存储单元的数据的读取的过程中，可以一直提供第一隔离信号ISO_UP，从而使得第一隔离单元410一直打开。此时，位线BL始终与第一读出位线SABL连接。因此，在偏移消除阶段，当第一读出位线SABL的电位被拉低时，位线BL电位也被拉低，从而可以更加可靠地进行偏移消除。
而第二隔离信号ISO_DN可以在预充阶段以及放大阶段被提供，从而打开第二隔离单元420。在预充阶段，第二隔离单元420打开，从而可以对互补位线BLB与第一互补读出位线SABLB进行预充电。在放大阶段打开第二隔离单元420，从而可以使得互补位线BLB与位线BL上的电压同时被放大。
在一个实施例中，请参阅图4-图11、图13-图24以及图26-图37，感测放大电路的布局具有第一器件区A1以及第二器件区A2。
第一器件区A1包括第一P型有源层111、第一栅极层112、第一N型有源层131以及第三栅极层132。第一栅极层112设置在第一P型有源层111上，且用于与第一P型有源层111形成第一P型晶体管110。第三栅极层132设置在第一N型有源层131上，且用于与第一N型有源层131形成第一N型晶体管130。
第二器件区A2包括第二P型有源层121、第二栅极层122、第二N型有源层141以及第四栅极层142。第二栅极层122设置在第二P型有源层121上，且用于与第二P型有源层121形成第二P型晶体管120。第四栅极层142设置在第二N型有源层141上，且用于与第二N型有源层141形成第二N型晶体管140。
在本实施例中，将第一P型晶体管110与第一N型晶体管130形成在同一器件区，从而便于在对存储单元进行读取的过程中，通过第一偏移消除单元210对第一P型晶体管110与第一N型晶体管130进行偏移消除操作。第二P型晶体管120与第二N型晶体管 140形成在同一器件区，从而便于在对互补存储单元进行读取的过程中，通过第二偏移消除单元220对第二P型晶体管120与第二N型晶体管140进行偏移消除操作。
在一个实施例中，请参阅图4-图11、图13-图24以及图26-图37，第一P型有源层111与第二P型有源层121位于第一N型有源层131和第二N型有源层141之间，或第一N型有源层131与第二N型有源层141位于第一P型有源层111和第二P型有源层121之间。
在一个实施例中，请继续参阅图4，感测放大电路结构的布局还具有第三器件区A3与第四器件区A4。
第三器件区A3包括第一有源层10以及第一隔离栅极层411。第一隔离栅极层411设置在第一有源层10上。并且，第一隔离栅极层411用于与第一有源层10形成第一隔离单元410。
第四器件区A4包括第二有源层20以及第二隔离栅极层421，第二隔离栅极层421设置在第二有源层20上。并且，第二隔离栅极层421用于与第二有源层20形成第二隔离单元420。
第一器件区A1以及第二器件区A2位于第三器件区A3与第四器件区A4之间。即第三器件区A3与第四器件区A4位于两侧的位置，从而便于将第一隔离单元410与位线BL连接，且便于将第二隔离单元420与互补位线BLB连接，从而能够减小走线长度，节约布局空间。
在一个实施例中，请参阅图4或图5，第三器件区A3还包括第一偏移消除栅极层211以及第一回写栅极层311。第一偏移消除栅极层211与第一回写栅极层311均设置在第一有源层10上。第一偏移消除栅极层211用于与第一有源层10形成第一偏移消除单元210。第一回写栅极层311用于与第一有源层10形成第一回写单元310。
此时，可以通过第一有源层10而将第一偏移消除单元210、第一回写单元310以及第一隔离单元410连接，从而有效节省电路面积。
第四器件区A4还包括第二偏移消除栅极层221以及第二回写栅极层321。第二偏移消除栅极层221与第二回写栅极层321均设置在第二有源层20上。第二偏移消除栅极层221用于与第二有源层20形成第二偏移消除单元220，第二回写栅极层321用于与第二有源层20形成第二回写单元320。
此时，可以通过第二有源层20而将第二偏移消除单元220、第二回写单元320以及第二隔离单元420连接，从而有效节省电路面积。
在一个实施例中，请参阅图6或图7，第一器件区A1还包括第三有源层30、第一偏移消除栅极层211以及第一回写栅极层311。第一偏移消除栅极层211与第一回写栅极层311设置在第三有源层30上。
第一偏移消除栅极层211用于与第三有源层30形成第一偏移消除单元210。第一回写栅极层311用于与第三有源层30形成第一回写单元310。此时，可以通过第三有源层30而将第一偏移消除单元210与第一回写单元310连接。
同时，第三有源层30位于第一P型有源层111与第一N型有源层131之间，从而使得第一偏移消除单元210以及第一回写单元310位于第一P型晶体管110与第一N型晶体管130之间，从而便于将第一偏移消除单元210、第一回写单元310、第一P型晶体管110以及第一N型晶体管130连接至第二互补读出位线ISABLB。
第二器件区A2还包括第四有源层40、第二偏移消除栅极层221以及第二回写栅极层321。第二偏移消除栅极层221以及第二回写栅极层321设置在第四有源层40上。第二偏移消除栅极层221用于与第四有源层40形成第二偏移消除单元220。第二回写栅极层321与第四有源层40用于形成第二回写单元320。此时，可以通过第四有源层40而将第二偏移消除单元220与第二回写单元320连接。
同时，第四有源层40位于第二P型有源层121与第二N型有源层141之间，从而使得第二偏移消除单元220以及第二回写单元320位于第二P型晶体管120与第二N型晶体管140之间，从而便于将第二偏移消除单元220、第二回写单元320、第二P型晶体管120以及第二N型晶体管140连接至第二读出位线ISABL。
在一个实施例中，请参阅图8或图9或图10或图11，感测放大电路的布局还具有第五器件区A5。第五器件区A5位于第一器件区A1和第二器件区A2之间，其包括第五有源层50、第一偏移消除栅极层211、第一回写栅极层311、第二偏移消除栅极层221以及第二回写栅极层321。
请参阅图8或图10，沿第一器件区A1指向第二器件区A2的方向，第一偏移消除栅极层211、第一回写栅极层311、第二偏移消除栅极层221以及第二回写栅极层321依次间隔设置在第五有源层50上。请参阅图9或图11，沿第一器件区A1指向第二器件区A2的方向，第一回写栅极层311、第一偏移消除栅极层211、第二回写栅极层321以及第二偏移消除栅极层221依次间隔设置在第五有源层50上。
第一偏移消除栅极层211用于与第五有源层50形成第一偏移消除单元210。第一回写栅极层311用于与第五有源层50形成第一回写单元310。第二偏移消除栅极层221用于与第五有源层50形成第二偏移消除单元220。第二回写栅极层321用于与第五有源层50形成第二回写单元320。
此时，可以通过第五有源层50而将第一偏移消除单元210、第一回写单元310、第二偏移消除单元220以及第二回写单元320连接。
在一个实施例中，第一隔离单元410包括第一隔离晶体管。第一隔离单元410中的第一隔离晶体管的数量可以为多个，当然也可以为一个。
第一隔离晶体管的栅极用于接收第一隔离信号ISO_UP。第一隔离晶体管的源极连接位线BL与第一读出位线SABL中的其中一者。第一隔离晶体管的漏极连接位线BL与第一读出位线SABL中的另一者。
第二隔离单元420包括第二隔离晶体管。第二隔离单元420中的第二隔离晶体管的数量可以为多个，当然也可以为一个。
第二隔离晶体管的栅极用于接收第二隔离信号ISO_DN，第二隔离晶体管的源极连接互补位线BLB与第一互补读出位线SABLB中的其中一者，第二隔离晶体管的漏极连接互补位线BLB与第一互补读出位线SABLB中的另一者。
这里可以理解的是，第一隔离晶体管和/或第二隔离晶体管可以为N型晶体管，也可以为P型晶体管，本实施例对此并没有限制。
在一个实施例中，请参阅图12或图2，感测放大电路还包括第一预充单元510、第二预充单元520以及平衡单元530。
第一预充单元510被构造为响应于预充信号PRE将第一读出位线SABL连接到预充信号端。第二预充单元520被构造为响应于预充信号PRE将第一互补读出位线SABLB连接到预充信号端。预充信号端用于接收预充电压VBLP。具体地，VBLP可以等于
Figure PCTCN2022107640-appb-000003
平衡单元530其被构造为响应于平衡信号EQ将第一读出位线SABL连接到第一互补读出位线SABLB，从而平衡二者之间的电压。
在预充阶段，可以提供平衡信号EQ以及预充信号PRE，从而对第一读出位线SABL以及第一互补读出位线SABLB进行预充，且平衡二者之间的电压。
在一个实施例中，第一预充单元510包括第一预充晶体管。第一预充单元510中的第一预充晶体管的数量可以为多个，也可以为一个。
第一预充晶体管的栅极用于接收预充信号PRE。第一预充晶体管的源极连接第一读出 位线SABL与预充信号端中的其中一者。第一隔离晶体管的漏极连接第一读出位线SABL与预充信号端中的另一者。
第二预充单元520包括第二预充晶体管。第二预充单元520中的第二预充晶体管的数量可以为多个，也可以为一个。
第二预充晶体管的栅极用于接收预充信号PRE。第二预充晶体管的源极连接第一互补读出位线SABLB与预充信号端中的其中一者。第一预充晶体管的漏极连接第一互补读出位线SABLB与预充信号端中的另一者。
平衡单元530包括平衡晶体管。平衡单元530中的平衡晶体管的数量可以为多个，也可以为一个。
平衡晶体管的栅极用于接收平衡信号EQ。第一预充晶体管的源极连接第一读出位线SABL与第一互补读出位线SABLB中的其中一者，第一隔离晶体管的漏极连接第一读出位线SABL与第一互补读出位线SABLB中的另一者。
在一个实施例中，请参阅图2，第一预充晶体管的栅极、第二预充晶体管的栅极以及平衡晶体管530的栅极连接至同一控制端，从而可以同时通过该控制端子获取预充信号PRE以及平衡信号EQ。此时，可以简化电路控制。
当然，在其他实施例中，第一预充晶体管的栅极、第二预充晶体管的栅极以及平衡晶体管530的栅极也可以连接至不同的控制端，这里对此并没有限制。
在一个实施例中，请参阅图13或图14，沿第三器件区A3指向第一器件区A1的方向，第三器件区A3还包括依次间隔设置在第一有源层10上的第一隔离栅极层411、第一偏移消除栅极层211、第一回写栅极层311、平衡栅极层531、第一预充栅极层511以及第二预充栅极层521。
第一隔离栅极层411用于与第一有源层10形成第一隔离单元410。第一偏移消除栅极层211用于与第一有源层10形成第一偏移消除单元210。第一回写栅极层311用于与第一有源层10形成第一回写单元310。平衡栅极层531用于与第一有源层10形成平衡单元530。第一预充栅极层511用于与第一有源层10形成第一预充单元510。第二预充栅极层521用于与第一有源层10形成第二预充单元520。
沿第四器件区A4指向第二器件区A2的方向，第四器件区A4还包括依次间隔设置在第二有源层20上的第二隔离栅极层421、第二偏移消除栅极层221以及第二回写栅极层321。第二隔离栅极层421用于与第二有源层20形成第二隔离单元420。第二偏移消除栅极层221用于与第二有源层20形成第二偏移消除单元220。第二回写栅极层321用于与第二有源层20形成第二回写单元320。
在一个实施例中，请参阅图15或图16，沿第三器件区A3指向第一器件区A1的方向，第三器件区A3还包括依次间隔设置在第一有源层10上的第一隔离栅极层411、第一偏移消除栅极层211、第一回写栅极层311、第一预充栅极层511以及第二预充栅极层521。
第一隔离栅极层411用于与第一有源层10形成第一隔离单元410。第一偏移消除栅极层211用于与第一有源层10形成第一偏移消除单元210。第一回写栅极层311用于与第一有源层10形成第一回写单元310。第一预充栅极层511用于与第一有源层10形成第一预充单元510。第二预充栅极层521用于与第一有源层10形成第二预充单元520。
沿第四器件区A4指向第二器件区A2的方向，第四器件区A4还包括依次间隔设置在第二有源层20上的第二隔离栅极层421、第二偏移消除栅极层221、第二回写栅极层321以及平衡栅极层531。第二隔离栅极层421用于与第二有源层20形成第二隔离单元420。第二偏移消除栅极层221用于与第二有源层20形成第二偏移消除单元220。第二回写栅极层321用于与第二有源层20形成第二回写单元320。平衡栅极层531用于与第二有源层20形成平衡单元530。
在一个实施例中，请参阅图17，第一器件区A1还包括第三有源层30、第一预充栅极 层511、平衡栅极层531以及第二预充栅极层521。沿第一P型有源层111指向第一N型有源层131的方向，第一预充栅极层511、平衡栅极层531以及第二预充栅极层521依次间隔设置在第三有源层30上。
第三有源层30位于第一P型有源层111与第一N型有源层131之间。第一预充栅极层511用于与第三有源层30形成第一预充单元510。平衡栅极层531用于与第三有源层30形成平衡单元530。第二预充栅极层521用于与第三有源层30形成第二预充单元520。
沿第三器件区A3指向第一器件区A1的方向，第三器件区A3还包括依次间隔设置在第一有源层10上的第一隔离栅极层411、第一偏移消除栅极层211以及第一回写栅极层311。第一偏移消除栅极层211用于与第一有源层10形成第一偏移消除单元210。第一回写栅极层311用于与第一有源层10形成第一回写单元310。
沿第四器件区A4指向第二器件区A2的方向，第四器件区A4还包括依次间隔设置在第二有源层20上的第二隔离栅极层421、第二偏移消除栅极层221以及第二回写栅极层321。第二偏移消除栅极层221用于与第二有源层20形成第二偏移消除单元220。第二回写栅极层321用于与第二有源层20形成第二回写单元320。
在一个实施例中，所请参阅图18，感测放大电路的布局还具有第五器件区A5。第五器件区A5位于第一器件区A1与第二器件区A2之间。并且，第五器件区A5包括第五有源层50、第一预充栅极层511、平衡栅极层531以及第二预充栅极层521。沿第一器件区A1指向第二器件区A2的方向，第一预充栅极层511、平衡栅极层531以及第二预充栅极层521依次间隔设置在第五有源层50上。
第一预充栅极层511用于与第五有源层50形成第一预充单元510。平衡栅极层531用于与第五有源层50形成平衡单元530。第二预充栅极层521用于与第五有源层50形成第二预充单元520。
沿第三器件区A3指向第一器件区A1的方向，第三器件区A3还包括依次间隔设置在第一有源层10上的第一隔离栅极层411、第一偏移消除栅极层211以及第一回写栅极层311。第一偏移消除栅极层211用于与第一有源层10形成第一偏移消除单元210。第一回写栅极层311用于与第一有源层10形成第一回写单元310。
沿第四器件区A4指向第二器件区A2的方向，第四器件区A4还包括依次间隔设置在第二有源层20上的第二隔离栅极层421、第二偏移消除栅极层221以及第二回写栅极层321。第二偏移消除栅极层221用于与第二有源层20形成第二偏移消除单元220。第二回写栅极层321用于与第二有源层20形成第二回写单元320。
在一个实施例中，所请参阅图19，第一器件区A1还包括第三有源层30、第一偏移消除栅极层211、第一回写栅极层311、平衡栅极层531、第二回写栅极层321以及第二偏移消除栅极层221，沿第一P型有源层111指向第一N型有源层131的方向，第一偏移消除栅极层211、第一回写栅极层311、平衡栅极层531、第二回写栅极层321以及第二偏移消除栅极层221依次间隔设置在第三有源层30上。
第三有源层30位于第一P型有源层111与第一N型有源层131之间。第一偏移消除栅极层211用于与第三有源层30形成第一偏移消除单元210。第一回写栅极层311用于与第三有源层30形成第一回写单元310。平衡栅极层531用于与第三有源层30形成平衡单元530。第二回写栅极层321用于与第三有源层30形成第二回写单元320。第二偏移消除栅极层221用于与第三有源层30形成第二偏移消除单元220。
第三器件区A3还包括设置在第一有源层10上的第一预充栅极层511。第一预充栅极层511用于与第一有源层10形成第一预充单元510。
第四器件区A4还包括设置在第二有源层20上的第二预充栅极层521。第二预充栅极层521用于与第二有源层20形成第二预充单元520。
在一个实施例中，所请参阅图20，感测放大电路的布局还具有第五器件区A5。第五 器件区A5位于第一器件区A1与所诉第二器件区A2之间。并且，第五器件区A5包括第五有源层50、第一偏移消除栅极层211、第一回写栅极层311、平衡栅极层531、第二回写栅极层321以及第二偏移消除栅极层221。沿第一器件区A1指向第二器件区A2的方向，第一偏移消除栅极层211、第一回写栅极层311、平衡栅极层531、第二回写栅极层321以及第二偏移消除栅极层221依次间隔设置在第五有源层50上。
第一偏移消除栅极层211用于与第五有源层50形成第一偏移消除单元210。第一回写栅极层311用于与第五有源层50形成第一回写单元310。平衡栅极层531用于与第五有源层50形成平衡单元530。第二回写栅极层321用于与第五有源层50形成第二回写单元320。第二偏移消除栅极层221用于与第五有源层50形成第二偏移消除单元220。
第三器件区A3还包括设置在第一有源层10上的第一预充栅极层511。第一预充栅极层511用于与第一有源层10形成第一预充单元510。
第四器件区A4还包括设置在第二有源层20上的第二预充栅极层521。第二预充栅极层521用于与第二有源层20形成第二预充单元520。
在一个实施例，所请参阅图21或图22，第一器件区A1还包括第三有源层30、第一回写栅极层311、第一偏移消除栅极层211、平衡栅极层531以及第二预充栅极层521。沿第一器件区A1指向第二器件区A2的方向，第一回写栅极层311、第一偏移消除栅极层211、平衡栅极层531以及第二预充栅极层521依次间隔设置在第三有源层30上。
第三有源层30位于第一P型有源层111与第一N型有源层131之间。第一回写栅极层311用于与第三有源层30形成第一回写单元310。第一偏移消除栅极层211用于与第三有源层30形成第一偏移消除单元210。平衡栅极层531用于与第三有源层30形成平衡单元530。第二预充栅极层511用于与第三有源层30形成第二预充单元510。
第二器件区A2还包括第四有源层40、第二偏移消除栅极层221、第二回写栅极层321以及第一预充栅极层511，沿第二器件区A2指向第一器件区A1的方向，第二偏移消除栅极层221、第二回写栅极层321以及第一预充栅极层511依次间隔设置在第四有源层40上。
第四有源层40位于第二P型有源层121与第二N型有源层141之间。第二偏移消除栅极层221用于与第四有源层40形成第二偏移消除单元220。第二回写栅极层321用于与第四有源层40形成第二回写单元320。第一预充栅极层511用于与第四有源层40形成第一预充单元510。
在一个实施例中，所所请参阅图23或图24，感测放大电路的布局还具有第五器件区A5。第五器件区A5位于第一器件区A1与第二器件区A2之间。并且，第五器件区A5包括第五有源层50、第一回写栅极层311、第一偏移消除栅极层211、平衡栅极层531、第二预充栅极层521、第一预充栅极层511、第二回写栅极层321以及第二偏移消除栅极层221。沿第一器件区A1指向第二器件区A2的方向，第一回写栅极层311、第一偏移消除栅极层211、平衡栅极层531、第二预充栅极层521、第一预充栅极层511、第二回写栅极层321以及第二偏移消除栅极层221依次间隔设置在第五有源层50上。
第一偏移消除栅极层211用于与第五有源层50形成第一偏移消除单元210。第一回写栅极层311用于与第五有源层50形成第一回写单元310。平衡栅极层531用于与第五有源层50形成平衡单元530。第一预充栅极层511用于与第五有源层50形成第一预充单元510。第二预充栅极层521用于与第五有源层50形成第二预充单元520。第二回写栅极层321用于与第五有源层50形成第二回写单元320。第二偏移消除栅极层221用于与第五有源层50形成第二偏移消除单元220。
在一个实施例中，请参阅图25，感测放大电路还包括第三预充单元540以及平衡单元530。第三预充单元540被构造为响应于预充信号PRE将第一互补读出位线SABLB或第一读出位线SABL连接到预充信号端。平衡单元520被构造为响应于平衡信号EQ将第 一读出位线SABL连接到第一互补读出位线SABLB。
此时，在预充阶段，可以提供预充信号PRE，从而打开第三预充单元540，从而为第一互补读出位线SABLB或第一读出位线SABL进行预充电。
这里以打开第三预充单元540而为第一互补读出位线SABLB进行预充电为例进行说明。当打开第三预充单元540的同时，提供平衡信号EQ，从而打开平衡单元530。此时，第一读出位线SABL与第一互补读出位线SABLB连接，从而在第一互补读出位线SABLB进行预充电的同时，也进行预充电，并且第一读出位线SABL与第一互补读出位线SABLB的电位平衡。
在本实施例中，通过只设置一个第三预充单元540，从而有效简化电路结构。
在一个实施例中，第三预充单元540包括第三预充晶体管。第三预充单元540中的第三预充晶体管的数量可以为多个，也可以为一个。
第三预充晶体管的栅极用于接收预充信号，第三预充晶体管的源极连接第一读出位线SABL与预充信号端中的其中一者，第三预充晶体管的漏极连接第一读出位线SABL与预充信号端中的另一者。
或者，第三预充晶体管的栅极用于接收预充信号，第三预充晶体管的源极连接第一互补读出位线SABLB与预充信号端中的其中一者，第三预充晶体管的漏极连接第一互补读出位线SABLB与预充信号端中的另一者。
平衡单元530包括平衡晶体管。平衡晶体管的栅极用于接收平衡信号EQ。平衡晶体管的源极连接第一读出位线SABL与第一互补读出位线SABLB中的其中一者，第一隔离晶体管的漏极连接第一读出位线SABL与第一互补读出位线SABLB中的另一者。
在一个实施例中，第三预充晶体管的栅极与平衡晶体管的栅极连接至同一控制端，从而可以同时通过该控制端子获取预充信号PRE以及平衡信号EQ。此时，可以简化电路控制。
当然，在其他实施例中，第三预充晶体管的栅极以及平衡晶体管530的栅极也可以连接至不同的控制端，这里对此并没有限制。
在一个实施例中，请参阅图26或图27或图28或图29，第三器件区A3还包括设置在第一有源层10上的第一偏移消除栅极层211、第一回写栅极层311以及第三预充栅极层541。
沿第三器件区A3指向第一器件区A1的方向，第三器件区A3包括依次间隔设置在第一有源层10上的第一隔离栅极层411、第一偏移消除栅极层211、第一回写栅极层311以及第三预充栅极层541。第一偏移消除栅极层211用于与第一有源层10形成第一偏移消除单元210。第一回写栅极层311用于与第一有源层10形成第一回写单元310。第一预充栅极层用于与第一有源层10形成第三预充单元540。
第四器件区A4还包括设置在第二有源层20上的第二偏移消除栅极层221、第二回写栅极层321以及平衡栅极层531。
请参阅图26或图27，沿第四器件区A4指向第二器件区A2的方向，第四器件区A4包括依次间隔设置在第二有源层20上的第二隔离栅极层421、第二偏移消除栅极层221、第二回写栅极层321以及平衡栅极层531。
请参阅图28或图29，沿第四器件区A4指向第二器件区A2的方向，第四器件区A4包括依次间隔设置在第二有源层20上的第二隔离栅极层421、平衡栅极层531、第二回写栅极层321以及第二偏移消除栅极层221。
第二偏移消除栅极层221用于与第二有源层20形成第二偏移消除单元220。第二回写栅极层321用于与第二有源层20形成第二回写单元320。平衡栅极层531用于与第二有源层20形成平衡单元。
在一个实施例中，请参阅图30或图31或图32或图33，第一器件区A1还包括第三 有源层30、第一偏移消除栅极层211、第一回写栅极层311、第三预充栅极层541。请参阅图30或图31，沿第一器件区A1指向第二器件区A2的方向，第一偏移消除栅极层211、第一回写栅极层311以及第三预充栅极层541依次间隔设置在第三有源层30上。请参阅图32或图33，沿第一器件区A1指向第二器件区A2的方向，第三预充栅极层541、第一回写栅极层311以及第一偏移消除栅极层211依次间隔设置在第三有源层30上。
第三有源层30位于第一P型有源层111与第一N型有源层131之间。第一偏移消除栅极层211用于与第三有源层30形成第一偏移消除单元210。第一回写栅极层311用于与第三有源层30形成第一回写单元310。第三预充栅极层541用于与第三有源层30形成第三预充单元540。
第二器件区A2还包括第四有源层40、第二偏移消除栅极层221、第二回写栅极层321以及平衡栅极层531。请参阅图30或图31，沿第二器件区A2指向第一器件区A1的方向，第二偏移消除栅极层221、第二回写栅极层321以及平衡栅极层531依次间隔设置在第四有源层40上。请参阅图32或图33，沿第二器件区A2指向第一器件区A1的方向，平衡栅极层531、第二回写栅极层321以及第二偏移消除栅极层221依次间隔设置在第四有源层40上。
第四有源层40位于第二P型有源层121与第二N型有源层之间。第二偏移消除栅极层221用于与第四有源层40形成第二偏移消除单元220。第二回写栅极层321用于与第四有源层40形成第二回写单元320。平衡栅极层531用于与第四有源层40形成平衡单元。
在一个实施例中，请参阅图34或图35或图36或图37，第一器件区A1还包括第三有源层30、第一偏移消除栅极层211、第一回写栅极层311以及平衡栅极层531。
请参阅图34或图35，沿第一器件区A1指向第二器件区A2的方向，第一偏移消除栅极层211、第一回写栅极层311以及平衡栅极层531依次间隔设置在第三有源层30上。
请参阅图36或图37，沿第一器件区A1指向第二器件区A2的方向，平衡栅极层531、第一回写栅极层311以及第一偏移消除栅极层211依次间隔设置在第三有源层30上。
第三有源层30位于第一P型有源层111与第一N型有源层131之间。第一偏移消除栅极层211用于与第三有源层30形成第一偏移消除单元210。第一回写栅极层311用于与第三有源层30形成第一回写单元310。平衡栅极层531用于与第三有源层30形成平衡单元。
第二器件区还包括第四有源层40、第二偏移消除栅极层221、第二回写栅极层321以及第三预充栅极层541。第二偏移消除栅极层221、第二回写栅极层321以及第三预充栅极层541设置在第四有源层40上。
请参阅图34或图35，沿第一器件区A1指向第二器件区A2的方向，第三预充栅极层541、第二偏移消除栅极层221以及第二回写栅极层321依次间隔设置在第四有源层40上。
请参阅图36或图37，沿第一器件区A1指向第二器件区A2的方向，第二回写栅极层321、第二偏移消除栅极层221以及第三预充栅极层541依次间隔设置在第四有源层40上。
第四有源层40位于第二P型有源层121与第二N型有源层141之间。第二偏移消除栅极层221用于与第四有源层40形成第二偏移消除单元220。第二回写栅极层321用于与第四有源层40形成第二回写单元320。第三预充栅极层541用于与第四有源层40形成第三预充单元540。
在一个实施例中，第一偏移消除单元210包括第一偏移消除晶体管。第一偏移消除单元210中的第一偏移消除晶体管的数量可以为多个，也可以为一个。
第一偏移消除晶体管的栅极用于接收第一偏移消除信号OC1_UP，第一偏移消除晶体管的源极连接第一读出位线SABL与第二互补读出位线ISABLB中的其中一者，第一偏移消除晶体管的漏极连接第一读出位线SABL与第二互补读出位线ISABLB中的另一者。
第二偏移消除单元220包括第二偏移消除晶体管。第二偏移消除单元220中的第二偏 移消除晶体管的数量可以为多个，也可以为一个。
第二偏移消除晶体管的栅极用于接收第二偏移消除信号OC1_DN，第二偏移消除晶体管的源极连接第一互补读出位线SABLB与第二读出位线ISABL中的其中一者，第二偏移消除晶体管的漏极连接第一互补读出位线SABLB与第二读出位线ISABL中的另一者。
第一回写单元310包括第一回写晶体管。第一回写单元310中的第一回写晶体管的数量可以为多个，也可以为一个。
第一回写晶体管的栅极用于接收第一回写信号OC2_UP，第一回写晶体管的源极连接第一互补读出位线SABLB与第二互补读出位线ISABLB中的其中一者，第一回写晶体管的漏极连接第一互补读出位线SABLB与第二互补读出位线ISABLB中的另一者。
第二回写单元320包括第二回写晶体管。第二回写单元320中的第二回写晶体管的数量可以为多个，也可以为一个。
第二回写晶体管的栅极用于接收第二回写信号OC2_DN，第二回写晶体管的源极连接第一读出位线SABL与第二读出位线ISABL中的其中一者，第二回写晶体管的漏极连接第一读出位线SABL与第二读出位线ISABL中的另一者。
在一个实施例中，还提供一种数据读出方法，其中，包括：
预充阶段，对位线BL、第一读出位线SABL、互补位线BLB、第一互补读出位线SABLB进行预充；
偏移消除阶段，为第一信号端与第三信号端分别提供高电平信号与低电平信号，同时打开第一偏移消除单元210，从而将第一读出位线SABL连接到第二互补读出位线ISABLB；
电荷共享阶段，关断第一偏移消除单元210，打开存储单元，且打开第一回写单元310，从而将第一互补读出位线SABLB连接到第二互补读出位线ISABLB；
放大阶段，为第一信号端、第二信号端提供高电平信号，为第三信号端和第四信号端提供低电平信号，同时打开第二回写单元320，从而将第一读出位线SABL连接到第二读出位线ISABL。
在本说明书的描述中，参考术语“一个实施例”、“其他实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种感测放大电路，包括：
    第一P型晶体管，其连接在第一信号端和第二互补读出位线之间，并且具有连接到第一读出位线的控制端子，所述第一读出位线与位线连接；
    第二P型晶体管，其连接在第二信号端和第二读出位线之间，并且具有连接到第一互补读出位线的控制端子，所述第一互补读出位线与互补位线连接；
    第一N型晶体管，其连接在第三信号端和所述第二互补读出位线之间，并且具有连接到所述第一读出位线的控制端子；
    第二N型晶体管，其连接在第四信号端和所述第二读出位线之间，并且具有连接到所述第一互补读出位线的控制端子；
    第一偏移消除单元，其被构造为响应于第一偏移消除信号将所述第一读出位线连接到所述第二互补读出位线；
    第二偏移消除单元，其被构造为响应于第二偏移消除信号将所述第一互补读出位线连接到所述第二读出位线；
    第一回写单元，其被构造为响应于第一回写信号将所述第一互补读出位线连接到所述第二互补读出位线；
    第二回写单元，其被构造为响应于第二回写信号将所述第一读出位线连接到所述第二读出位线。
  2. 根据权利要求1所述的感测放大电路，其中，所述感测放大电路还包括：
    第一隔离单元，其被构造为响应于第一隔离信号将所述位线连接到所述第一读出位线；
    第二隔离单元，其被构造为响应于第二隔离信号将所述互补位线连接到所述第一互补读出位线。
  3. 根据权利要求2所述的感测放大电路，其中，所述感测放大电路的布局中，所述第一P型晶体管和所述第一N型晶体管位于第一器件区，所述第二P型晶体管和所述第二N型晶体管位于第二器件区；其中
    所述第一器件区包括第一P型有源层以及设置在所述第一P型有源层上的第一栅极层，所述第一栅极层用于与所述第一P型有源层形成所述第一P型晶体管；
    第一N型有源层以及设置在所述第一N型有源层上的第三栅极层，所述第三栅极层用于与所述第一N型有源层形成所述第一N型晶体管，
    所述第二器件区包括第二P型有源层以及设置在所述第二P型有源层上的第二栅极层，所述第三栅极层用于与所述第二P型有源层形成所述第二P型晶体管；
    第二N型有源层以及设置在所述第二N型有源层上的第四栅极层，所述第四栅极层用于与所述第二N型有源层形成所述第二N型晶体管。
  4. 根据权利要求3所述的感测放大电路，其中，所述感测放大电路的布局中，所述第一隔离单元位于第三器件区，所述第二隔离单元位于第四器件区：其中
    所述第三器件区包括第一有源层以及设置在所述第一有源层上的第一隔离栅极层，所述第一隔离栅极层用于与所述第一有源层形成所述第一隔离单元；
    所述第四器件区包括第二有源层以及设置在所述第二有源层上的第二隔离栅极层，所述第二隔离栅极层用于与所述第二有源层形成所述第二隔离单元；
    所述第一器件区以及所述第二器件区位于所述第三器件区与所述第四器件区之间。
  5. 根据权利要求4所述的感测放大电路，其中，
    所述第三器件区还包括设置在所述第一有源层上的第一偏移消除栅极层以及第一回写栅极层，所述第一偏移消除栅极层用于与所述第一有源层形成所述第一偏移消除单元，所述第一回写栅极层用于与所述第一有源层形成所述第一回写单元；
    所述第四器件区还包括设置在所述第二有源层上的第二偏移消除栅极层以及第二回写栅极层，所述第二偏移消除栅极层用于与所述第二有源层形成所述第二偏移消除单元，所述第二回写栅极层用于与所述第二有源层形成所述第二回写单元。
  6. 根据权利要求4所述的感测放大电路，其中，
    所述第一器件区还包括第三有源层、第一偏移消除栅极层以及第一回写栅极层，所述第一偏移消除栅极层与所述第一回写栅极层设置在所述第三有源层上，所述第三有源层位于所述第一P型有源层与所述第一N型有源层之间，所述第一偏移消除栅极层用于与所述第三有源层形成所述第一偏移消除单元，所述第一回写栅极层用于与所述第三有源层形成所述第一回写单元；
    所述第二器件区还包括第四有源层、第二偏移消除栅极层以及第二回写栅极层，所述第二偏移消除栅极层以及所述第二回写栅极层设置在所述第四有源层上，所述第四有源层位于所述第二P型有源层与所述第二N型有源层之间，所述第二偏移消除栅极层用于与所述第四有源层形成所述第二偏移消除单元，所述第二回写栅极层与所述第四有源层用于形成所述第二回写单元。
  7. 根据权利要求4所述的感测放大电路，其中，所述感测放大电路的布局中，所述第二偏移消除单元、所述第一偏移消除单元、所述第一回写单元和所述第二回写单元位于第五器件区：其中
    所述第五器件区位于所述第一器件区与所述第二器件区之间，包括第五有源层、第一偏移消除栅极层、第一回写栅极层、第二偏移消除栅极层以及第二回写栅极层，所述第一偏移消除栅极层、所述第一回写栅极层、所述第二偏移消除栅极层以及所述第二回写栅极层设置在所述第五有源层上，所述第一偏移消除栅极层用于与所述第五有源层形成所述第一偏移消除单元，所述第一回写栅极层用于与所述第五有源层形成所述第一回写单元，所述第二偏移消除栅极层用于与所述第五有源层形成所述第二偏移消除单元，所述第二回写栅极层用于与所述第五有源层形成所述第二回写单元。
  8. 根据权利要求2-7任一项所述的感测放大电路，其中，所述第一隔离单元包括至少一个第一隔离晶体管，所述第二隔离单元包括至少一个第二隔离晶体管。
  9. 根据权利要求2至4任一项所述的感测放大电路，其中，所述感测放大电路还包括：
    第一预充单元，其被构造为响应于预充信号将所述第一读出位线连接到预充信号端；
    第二预充单元，其被构造为响应于预充信号将所述第一互补读出位线连接到预充信号端；
    平衡单元，其被构造为响应于平衡信号将所述第一读出位线连接到第一互补读出位线。
  10. 根据权利要求9所述的感测放大电路，其中，所述第一预充单元包括至少一个第一预充晶体管，所述第二预充单元包括至少一个第二预充晶体管，所述平衡单元包括至少一个平衡晶体管。
  11. 根据权利要求10所述的感测放大电路，其中，所述第一预充晶体管的栅极、所述第二预充晶体管的栅极以及所述平衡晶体管的栅极连接至同一控制端。
  12. 根据权利要求2至4任一项所述的感测放大电路，其中，所述感测放大电路还包括：
    第三预充单元，其被构造为响应于预充信号将所述第一互补读出位线或所述第一读出位线连接到预充信号端；
    平衡单元，其被构造为响应于平衡信号将所述第一读出位线连接到第一互补读出位线。
  13. 根据权利要求12所述的感测放大电路，其中，所述第三预充单元包括至少一个第三预充晶体管，所述平衡单元包括至少一个平衡晶体管。
  14. 根据权利要求13所述的感测放大电路，其中，所述第三预充晶体管的栅极与所述平衡晶体管的栅极连接至同一控制端。
  15. 根据权利要求1所述的感测放大电路，其中，所述第一偏移消除单元包括至少一个第一偏移消除晶体管，所述第二偏移消除单元包括至少一个第二偏移消除晶体管，所述第一回写单元包括至少一个第一回写晶体管，所述第二回写单元包括至少一个第二回写晶体管。
  16. 一种数据读出方法，应用于权利要求1-15任一项所述的感测放大电路，包括：
    预充阶段，对位线、第一读出位线、互补位线、第一互补读出位线进行预充；
    偏移消除阶段，为第一信号端与第三信号端分别提供高电平信号与低电平信号，同时打开第一偏移消除单元，从而将所述第一读出位线连接到所述第二互补读出位线；
    电荷共享阶段，关断第一偏移消除单元，打开存储单元，且打开第一回写单元，从而将第一互补读出位线连接到所述第二互补读出位线；
    放大阶段，为所述第一信号端和第二信号端提供高电平信号，为所述第三信号端和第四信号端低电平信号，同时打开第二回写单元，从而将第一读出位线连接到所述第二读出位线。
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