WO2023082548A1 - 读出电路的版图结构和数据读出方法 - Google Patents

读出电路的版图结构和数据读出方法 Download PDF

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Publication number
WO2023082548A1
WO2023082548A1 PCT/CN2022/088090 CN2022088090W WO2023082548A1 WO 2023082548 A1 WO2023082548 A1 WO 2023082548A1 CN 2022088090 W CN2022088090 W CN 2022088090W WO 2023082548 A1 WO2023082548 A1 WO 2023082548A1
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Prior art keywords
bit line
readout
isolation
complementary
mos transistor
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PCT/CN2022/088090
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English (en)
French (fr)
Inventor
池性洙
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长鑫存储技术有限公司
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Priority to US17/813,998 priority Critical patent/US11594264B1/en
Publication of WO2023082548A1 publication Critical patent/WO2023082548A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Definitions

  • Embodiments of the present disclosure relate to but are not limited to a layout structure of a readout circuit and a data readout method.
  • Dynamic Random Access Memory is a semiconductor storage device commonly used in computers, consisting of many repeated storage units. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • DRAM can be divided into Double Data Rate (DDR) DRAM, GDDR (Graphics Double Data Rate) DRAM, and Low Power Double Data Rate (LPDDR) DRAM.
  • DDR Double Data Rate
  • GDDR Graphics Double Data Rate
  • LPDDR Low Power Double Data Rate
  • DRAM is applied in more and more fields, such as DRAM is more and more used in the mobile field, users have higher and higher requirements for DRAM power consumption indicators.
  • Embodiments of the present disclosure provide a layout structure of a readout circuit and a data readout method.
  • a new readout circuit is designed to ensure sufficient time for the potential amplification of the sensing amplifier module, thereby improving the efficiency of memory data readout.
  • Speed and accuracy at the same time, the first and second readout circuit structures are arranged adjacent to each other, and each part is arranged in an orderly manner, so as to ensure that the area occupied by the readout circuit structure is the smallest, and the connection between the devices is the shortest.
  • An embodiment of the present disclosure provides a readout circuit layout structure, including: a first readout circuit structure and a second readout circuit structure having the same structure, and both the first readout circuit structure and the second readout circuit structure include:
  • the first isolation module is used for conducting according to the first isolation signal, electrically connecting the bit line and the first readout bit line, and electrically connecting the complementary bit line and the first complementary readout bit line;
  • the second isolation module is used for according to the first isolation signal
  • the two isolation signals are turned on, electrically connected to the first read bit line and the second read bit line, and electrically connected to the first complementary read bit line and the second complementary read bit line;
  • the sense amplification module is used for the first isolation When the module and the second isolation module are turned on, the data signal of the memory array is sensed and read out;
  • the offset elimination module is used to electrically connect the first complementary readout bit line and the second readout bit line according to the offset elimination signal ;
  • the first readout circuit structure is coupled to the first adjacent storage array through the
  • the second isolation module includes: a first isolation MOS transistor and a second isolation MOS transistor; one of the source or drain of the first isolation MOS transistor is connected to the first readout bit line, and the other One of the source or drain of the second isolated MOS transistor is connected to the first complementary read bit line, and the other is connected to the second complementary read bit line. Out of the bit line, the gate is used to receive the second isolated signal.
  • the first isolation module includes: a third isolation MOS transistor and a fourth isolation MOS transistor; one of the source or the drain of the third isolation MOS transistor is connected to the first readout bit line, and the other One of the source or drain of the fourth isolated MOS transistor is connected to the first complementary readout bit line, the other is connected to the complementary bit line, and the gate is used for A first isolated signal is received.
  • the sense amplifier module includes: a first sense amplifier N transistor, the gate of which is connected to the first readout bit line, and one of the source or the drain is connected to the second complementary readout bit line, The other is connected to the second signal terminal, and the second signal terminal is used to provide the second voltage;
  • the second sense amplifier N-tube the gate is connected to the first complementary readout bit line, and one of the source or the drain is connected to the second Read out the bit line, the other is connected to the second signal terminal;
  • the first sense amplifier P tube the gate is connected to the second read out bit line, one of the source or the drain is connected to the second complementary read out bit line, and the other One is connected to the first signal terminal, the first signal terminal is used to provide the first voltage, the first voltage is greater than the second voltage;
  • the second sense amplifier P tube the gate is connected to the second complementary readout bit line, the source or the drain One of the poles is connected to the second readout bit line, and the other is connected to the first signal terminal.
  • the readout circuit further includes: a precharge module, configured to switch the bit line, the first read bit line, the second read bit line, the complementary bit line, the first complementary read bit line according to the precharge signal
  • the output bit line and the second complementary read bit line are precharged to a preset voltage; the equalization module is used to keep the voltage of the second read bit line consistent with the voltage of the second complementary read bit line according to the equalization signal.
  • the pre-charging module includes a pre-charging MOS tube
  • the balancing module includes a balancing MOS tube
  • the gate of the pre-charging MOS tube is used to receive a pre-charging signal, and one of the source or the drain is connected to the second read
  • the output bit line or the second complementary read bit line, the other is used to receive the preset voltage
  • the balanced MOS transistor gate is used to receive the balanced signal, and one of the source or the drain is connected to the second read bit line, The other is connected to the second complementary read bit line.
  • the readout circuit further includes: a first precharge module, connected to the bit line or the first read bit line, for precharging the bit line, the first read bit line and the second read bit line according to the precharge signal.
  • the second read bit line is to a preset voltage;
  • the second precharge module is connected to the complementary bit line or the first complementary read bit line, and is used to precharge the complementary bit line, the first complementary read bit line and the second complementary bit line according to the precharge signal Two complementary sense bit lines to preset voltages.
  • the first precharging module includes a first precharging MOS transistor
  • the second precharging module includes a second precharging MOS transistor
  • the gate of the first precharging MOS transistor is used to receive the precharging signal
  • the source One of the electrode or the drain is connected to the bit line or the first read bit line, and the other is used to receive the preset voltage
  • the gate of the second precharge MOS transistor is used to receive the precharge signal, and the source or drain One of them is connected to the complementary bit line or the first complementary read bit line, and the other is used to receive a preset voltage.
  • the offset elimination module includes a first offset elimination MOS transistor and a second offset elimination MOS transistor; the gate of the first offset elimination MOS transistor is used to receive the offset elimination signal, and the source or drain One of the poles is connected to the second complementary readout bit line, and the other is connected to the first readout bit line; the gate of the second offset elimination MOS transistor is used to receive the offset elimination signal, and one of the source or the drain One is connected to the second readout bit line, and the other is connected to the first complementary readout bitline.
  • the third isolation MOS transistor of the first readout circuit structure is connected to the first bit line and the first read bit line through a contact plug, and is used to electrically connect the first The bit line and the first read bit line of the first read circuit structure; the fourth isolation MOS transistor of the first read circuit structure is connected with the first complementary bit line and the first complementary read bit line through a contact plug, According to the first isolation signal, the first complementary read bit line of the first read circuit structure is electrically connected to the first complementary bit line; the third isolated MOS transistor of the second read circuit structure is connected to the second bit through the contact plug.
  • the line is connected to the second readout bit line, and is used to electrically connect the second bit line and the first readout bit line of the second readout circuit structure according to the first isolation signal; the fourth isolation MOS of the second readout circuit structure
  • the tube is connected to the second complementary bit line and the second complementary read bit line through the contact plug, and is used to electrically connect the first complementary read bit line and the second complementary bit line of the second read circuit structure according to the first isolation signal. Wire.
  • the third isolation MOS transistor of the first readout circuit structure in the extending direction of the bit line, is arranged on the side of the first region away from the second region; in the extending direction of the word line, the second readout circuit structure The third isolation MOS transistor of the output circuit structure is arranged adjacent to the third isolation MOS transistor of the first readout circuit structure; in the extending direction of the bit line, the fourth isolation MOS transistor of the second readout circuit structure is arranged in the second area On the side away from the first region; in the extending direction of the word line, the fourth isolation MOS transistor of the first readout circuit structure is adjacent to the fourth isolation MOS transistor of the second readout circuit structure.
  • the third isolation MOS transistor of the first readout circuit structure in the extending direction of the bit line, is disposed on the side of the first region away from the second region; in the extending direction of the bit line, the first readout The fourth isolation MOS transistor of the output circuit structure is arranged on the side of the first region close to the second region; in the extending direction of the bit line, the third isolation MOS transistor of the second readout circuit structure is arranged on the second region away from the first region on one side of the second region; in the extending direction of the bit line, the fourth isolation MOS transistor of the second readout circuit structure is arranged on the side of the second region close to the first region.
  • the fourth isolation MOS transistor of the first readout circuit structure is arranged close to the first region, and the third isolation MOS transistor of the second readout circuit structure is arranged close to the second region.
  • the fourth isolation MOS transistor of the first readout circuit structure is arranged close to the second region, and the third isolation MOS transistor of the second readout circuit structure is arranged close to the first region.
  • the pre-charging module includes a first pre-charging MOS transistor and a second pre-charging MOS transistor;
  • the second isolation module includes a first isolation MOS transistor and a second isolation MOS transistor;
  • the equalization module includes an equalization MOS transistor;
  • the offset elimination module includes a first offset elimination MOS transistor and a second offset elimination MOS transistor; in the first region in the direction where the bit line extends and is close to the second region, the first readout circuit structure is sequentially arranged.
  • An embodiment of the present disclosure also provides a data readout method, which refers to the layout structure of the above readout circuit, and has three readout stages, including: in the first readout stage, providing an equalization signal, a first isolation signal, a bias Shift and cancel the signal, precharge the bit line, the first read bit line, the second read bit line, the complementary bit line, the first complementary read bit line and the second complementary read bit line to a preset voltage; At the beginning of the second readout stage, the offset elimination signal of the preset duration is maintained, and the offset elimination is performed on the sense amplifier module through the first voltage and the second voltage applied to both ends of the sense amplifier module, and at the same time, the word line of the memory array is Open, based on the potential of the bit line and the memory cell in the memory array for charge sharing; during the execution of the second readout phase, the first isolation signal and the second isolation signal are provided, and the stored data is transferred from the bit line to the first readout
  • the bit line and the complementary bit line maintain a preset voltage, and
  • the second readout phase includes a first sub-phase, a second sub-phase, and a third sub-phase performed in sequence; in the first sub-phase, the first voltage and The second voltage, and provide the read command and the offset cancellation signal; in the second sub-phase, restore the first voltage and the second voltage to the preset voltage; in the third sub-phase, provide the first isolation signal and the second isolation signal .
  • the second sub-stage further includes: providing the equalized signal.
  • bit line and the first readout bit line are isolated by the first isolation module, and the complementary bit line and the first complementary readout bit line are blocked to avoid the bit line and the first readout bit line.
  • the potential change of the complementary bit line will affect the sense amplifier module, so that the word line can be turned on in advance without affecting the sense amplifier module, and the word line can be turned on in advance to synchronize the potential on the memory cell to the initial bit line or the initial complementary bit line, thereby increasing the word
  • the interval time from the opening of the line to the opening of the bit line increases the interval time from the opening of the word line to the opening of the bit line, so that there is sufficient time for the potential amplification of the sensing amplifier module, thereby improving the speed and accuracy of memory data readout, and at the same time
  • the first and second readout circuit structures are arranged adjacent to each other, and the parts are arranged in an orderly manner to ensure that the area occupied by the readout circuit structure is the smallest and the connection between the devices is the shortest.
  • FIG. 1 is a schematic structural diagram of a readout circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a readout sequence of a readout circuit provided by an embodiment of the present disclosure
  • FIG. 3 and FIG. 4 are structural schematic diagrams of a readout circuit with a precharge function provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a readout circuit layout provided by an embodiment of the present disclosure.
  • 6 to 7 are specific structural schematic diagrams of a readout circuit layout provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic circuit structure diagram of a first readout circuit structure provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic circuit structure diagram of a second readout circuit structure provided by an embodiment of the present disclosure.
  • FIG. 10 is a specific readout circuit layout corresponding to FIG. 8 and FIG. 9 provided by an embodiment of the present disclosure.
  • BL bit line
  • BL bit line
  • BL bit line
  • BLB complementary bit line
  • BLB1 first complementary bit line
  • BLB2 second complementary bit line
  • SABL first readout bit line
  • ISABL second read bit line
  • SABLB first complementary read bit line
  • ISO1 first isolation signal
  • OC offset cancellation signal
  • PCS the first signal terminal
  • NCS the second signal terminal
  • ⁇ N1402> the first isolated MOS tube; ⁇ N1403>, the second isolated MOS tube; ⁇ N1408>, the third isolated MOS tube; ⁇ N1428>, the fourth isolated MOS tube; ⁇ N1406>, the pre-charged MOS tube; ⁇ N1400>, the first sense amplifier N tube; ⁇ N1401>, the first offset cancellation MOS tube; ⁇ N1404>, the second offset cancellation MOS tube; ⁇ P1401>, the first sense amplifier P tube; ⁇ P1400> , the second sense amplifier P tube;
  • ⁇ N1422> the first isolated MOS tube; ⁇ N1423>, the second isolated MOS tube; ⁇ N1409>, the third isolated MOS tube; ⁇ N1429>, the fourth isolated MOS tube; ⁇ N1427>, the pre-charged MOS tube; ⁇ N1420>, the first sense amplifier N tube; ⁇ N1421>, the first offset cancellation MOS tube; ⁇ N1424>, the second offset cancellation MOS tube; ⁇ P1421>, the first sense amplifier P tube; ⁇ P1420> , The second sense amplifier P tube.
  • the existing sense amplifier module with the offset compensation function needs a certain amount of time to perform the offset elimination process, and then transmit the stored data to the sense amplifier module, resulting in the sense amplifier module processing the readout process.
  • the overall time consumption of the data becomes longer and the power consumption increases, making it impossible to further increase the data processing speed.
  • An embodiment of the present disclosure provides a layout structure of a readout circuit.
  • the data in the memory cell is transmitted to the bit line connected to the sense amplifier module in advance, reducing the sense amplifier module.
  • the overall time for the measurement and amplification module to process the stored data, while ensuring sufficient time for the potential amplification of the sensing and amplification module, thereby improving the speed and accuracy of memory data readout, and at the same time, the structure of the first and second readout circuits is the same Adjacent to each other, each part is distributed in an orderly manner, ensuring that the area occupied by the readout circuit structure is the smallest, and the connection between each device is the shortest.
  • Fig. 1 is a schematic structural diagram of the readout circuit provided by this embodiment
  • Fig. 2 is a schematic diagram of the readout timing of the readout circuit provided by this embodiment
  • Fig. 3 and Fig. 4 are the readout circuit with pre-charge function provided by this embodiment
  • the structural diagram of the circuit Fig. 5 is a schematic structural diagram of the readout circuit layout provided by this embodiment
  • Fig. 6 to Fig. 7 are the specific structural diagrams of the readout circuit layout provided by this embodiment
  • Fig. 8 is the first schematic diagram of the readout circuit layout provided by this embodiment
  • FIG. 9 is a schematic diagram of the circuit structure of the second readout circuit structure provided by this embodiment
  • FIG. 10 is a specific readout circuit layout corresponding to FIG. 8 and FIG. 9 provided by this embodiment.
  • the layout structure of the readout circuit provided in this embodiment will be further described in detail in conjunction with the accompanying drawings, specifically as follows:
  • the readout circuit is arranged between adjacent memory arrays 100, is coupled to one memory array 100 through a bit line BL, and is coupled to another memory array 100 through a complementary bit line BLB, including:
  • the first isolation module 201 is arranged between the bit line BL and the first read bit line SABL, and is used to electrically connect the bit line BL and the first read bit line SABL according to the first isolation signal ISO1, and is also arranged in the complementary bit line
  • the line BLB and the first complementary read bit line SABLB are used for conducting according to the first isolation signal ISO1 and electrically connecting the complementary bit line BLB and the first complementary read bit line SABLB.
  • the second isolation module 202 is connected between the first read bit line SABL and the second read bit line ISABL, and is used for conducting according to the second isolation signal ISO2, and electrically connecting the first read bit line SABL and the second read bit line.
  • the output bit line ISABL is also connected between the first complementary read bit line SABLB and the second complementary read bit line ISABLB, and is used for conducting according to the second isolation signal ISO2, and electrically connecting the first complementary read bit line SABLB with A second complementary sense bit line ISABLB.
  • the sense amplification module is connected with the first read bit line SABL and the first complementary read bit line SABLB, and is also connected with the second read bit line ISABL and the second complementary read bit line ISABLB, for the first isolation
  • the module 201 and the second isolation module 202 are turned on, the data signal of the memory array 100 is sensed and read out.
  • the offset canceling module 203 is connected between the first read bit line SABL and the second complementary read bit line ISABLB, and is used to electrically connect the first read bit line SABL and the second complementary read bit line according to the offset cancel signal OC.
  • the output bit line ISABLB is also connected between the first complementary read bit line SABLB and the second read bit line ISABL, and is used to electrically connect the first complementary read bit line SABLB with the second read bit line according to the offset cancel signal. bit line ISABL.
  • the first isolation module 201 isolates the bit line BL and the first read bit line SABL, and blocks the complementary bit line BLB and the first complementary read bit line SABLB, so as to prevent the potential change of the bit line BL and the complementary bit line BLB from affecting
  • the sense amplifier module so that the word line WL is turned on in advance without affecting the sense amplifier module, and the word line WL is turned on in advance to synchronize the potential on the memory cell 100 to the initial bit line BL or the initial complementary bit line BLB, so that there is sufficient time It is used to sense the potential amplification of the amplification module, thereby improving the speed and accuracy of memory data readout.
  • the first readout circuit structure 301 is coupled to a memory array between adjacent memory arrays through the first bit line BL1, and is coupled to another memory array between adjacent memory arrays through the first complementary bit line BLB1.
  • the second readout circuit structure 302 couples a storage array between adjacent storage arrays through the second bit line BL2, and couples another storage array between adjacent storage arrays through the second complementary bit line BLB2; the first readout circuit structure
  • the second isolation module, the sense amplification module and the offset elimination module in 301 are arranged in the first region, and in the extending direction of the bit line BL, the first isolation module in the first readout circuit structure 301 is arranged in the first region
  • the second isolation module, the sense amplification module and the offset elimination module in the second readout circuit structure 302 are arranged in the second region, and in the extending direction of the bit line BL, the second readout circuit structure 302
  • the first isolation module is disposed on both sides of the second region, wherein the first region and the second region are adjacently disposed in
  • the first and second readout circuit structures are arranged adjacent to each other, and the parts are arranged in an orderly manner to ensure that the area occupied by the readout circuit structure is the smallest and the connection between the devices is the shortest.
  • the first isolation module 201 includes: a third isolation MOS transistor ⁇ 23> and a fourth isolation MOS transistor ⁇ 24>; one of the source or drain of the third isolation MOS transistor ⁇ 23> is connected to the first One reads the bit line SABL, the other is connected to the bit line BL, and the gate is used to receive the first isolation signal ISO1; one of the source or drain of the fourth isolation MOS transistor ⁇ 24> is connected to the first complementary read bit line SABLB, the other is connected to the complementary bit line BLB, and the gate is used to receive the first isolation signal ISO1.
  • the specific connection mode of "source” and “drain” does not constitute a limitation to this embodiment, and in other implementations In this example, “drain” can be used to replace “source”, and “source” can be used to replace “drain”.
  • this embodiment does not limit the types of the third isolation MOS transistor ⁇ 23> and the fourth isolation MOS transistor ⁇ 24>.
  • the third isolation MOS transistor ⁇ 23> and the fourth isolation MOS transistor ⁇ 24> can be an NMOS tube or a PMOS tube.
  • the first isolation module includes a third isolation MOS transistor ⁇ 23> and a fourth isolation MOS transistor ⁇ 24>.
  • the third isolation MOS transistor ⁇ 23> of the first readout circuit structure 301 is connected to the first bit line BL1 and the first readout bit line (not shown) of the first readout circuit structure 301 through a contact plug
  • the first The fourth isolation MOS transistor ⁇ 24> of the readout circuit structure 301 is connected to the first complementary bit line BLB1 and the first complementary readout bit line (not shown) of the first readout circuit structure 301 through a contact plug
  • the second The third isolation MOS transistor ⁇ 23> of the readout circuit structure 302 is connected to the second bit line BL2 and the first readout bit line (not shown) of the second readout circuit structure 302 through a contact plug
  • the second readout The fourth isolated MOS transistor ⁇ 24> of the circuit structure 302 is connected to the second complementary bit line BLB2 and the first complementary read bit line (not shown) of the second read circuit structure 302 through a contact plug.
  • the third isolation MOS transistor ⁇ 23> of the first readout circuit structure 301 is arranged on the side of the first region away from the second region, and on the side of the word line WL
  • the third isolation MOS transistor ⁇ 23> of the second readout circuit structure 302 is arranged adjacent to the third isolation MOS transistor ⁇ 23> of the first readout circuit structure 301
  • the third isolation MOS transistor ⁇ 23> of the first readout circuit structure 301 is arranged adjacently.
  • the fourth isolation MOS transistor ⁇ 24> of the second readout circuit structure 302 is arranged on the side of the second region far away from the first region, and in the extending direction of the word line WL, the fourth isolation MOS transistor ⁇ 24> of the first readout circuit structure 301 ⁇ 24> is arranged adjacent to the fourth isolation MOS transistor ⁇ 24> of the second readout circuit structure 302 .
  • the third isolation MOS transistor ⁇ 23> of the first readout circuit structure 301 is arranged on the side of the first region away from the second region;
  • the fourth isolated MOS transistor ⁇ 24> of the first readout circuit structure 301 is arranged on the side of the first area close to the second area;
  • the second readout circuit structure The third isolation MOS transistor ⁇ 23> of 302 is arranged on the side of the second region away from the first region; in the extending direction of the bit line BL, the fourth isolation MOS transistor ⁇ 24> of the second readout circuit structure 302 is arranged on the second region The second area is close to the side of the first area.
  • the fourth isolation MOS transistor ⁇ 24> of the first readout circuit structure 301 is arranged close to the first region, and the third isolation MOS transistor ⁇ 23> of the second readout circuit structure is arranged close to the first area.
  • the fourth isolation MOS transistor ⁇ 24> of the first readout circuit structure 301 is arranged close to the second region, and the third isolation MOS transistor ⁇ 23> of the second readout circuit structure is arranged close to the second area. A locale.
  • the second isolation module 202 includes: a first isolation MOS transistor ⁇ 21> and a second isolation MOS transistor ⁇ 22>; one of the source or drain of the first isolation MOS transistor ⁇ 21> is connected to the second One read bit line SABL, the other is connected to the second read bit line ISABL, the gate is used to receive the second isolation signal ISO2; one of the source or drain of the second isolated MOS transistor ⁇ 22> is connected to the first
  • the complementary read bit line SABLB is connected to the second complementary read bit line ISABLB, and the gate is used to receive the second isolation signal ISO2.
  • the specific connection mode of "source” and “drain” does not constitute a limitation to this embodiment, and in other implementations In this example, “drain” can be used to replace “source”, and “source” can be used to replace “drain”.
  • this embodiment does not limit the types of the first isolation MOS transistor ⁇ 21> and the second isolation MOS transistor ⁇ 22>.
  • the first isolation MOS transistor ⁇ 21> and the second isolation MOS transistor ⁇ 22> it can also be a PMOS tube.
  • the sense amplifier module includes: a first sense amplifier N transistor ⁇ N1>, the gate of which is connected to the first read bit line SABL, and one of the source or the drain is connected to the second complementary read bit Line ISABLB, the other is connected to the second signal terminal NCS, and the second signal terminal NCS is used to provide the second voltage;
  • the second sense amplifier N-tube ⁇ N2> the gate is connected to the first complementary readout bit line SABLB, and the source is One of the or drains is connected to the second read bit line ISABL, and the other is connected to the second signal terminal NCS;
  • the first sense amplifier P transistor ⁇ P1> the gate is connected to the second read bit line ISABL, and the source or One of the drains is connected to the second complementary read bit line ISABLB, and the other is connected to the first signal terminal PCS, the first signal terminal PCS is used to provide a first voltage, and the first voltage is greater than the second voltage;
  • the second sense amplifier The gate of the P transistor ⁇ P2>
  • the precharge module includes a first precharge MOS transistor and a second precharge MOS transistor
  • the equalization module includes an equalization MOS transistor
  • the second isolation module includes a first isolation The MOS transistor and the second isolation MOS transistor
  • the offset elimination module includes a first offset elimination MOS transistor and a second offset elimination MOS transistor.
  • the first pre-charge MOS transistor, the first sense amplifier N transistor, and the first offset canceller of the first readout circuit structure 301 are sequentially arranged.
  • the first pre-charge MOS transistor, the first sense amplifier N transistor, and the first offset canceller of the second readout circuit structure 302 are sequentially arranged.
  • the third isolation MOS transistor is ⁇ N1408>
  • the fourth isolation MOS transistor is ⁇ N1428> (refer to Figure 9)
  • the pre-charge MOS transistor is ⁇ N1406 >
  • the first sense amplifier N tube is ⁇ N1400>
  • the first offset cancellation MOS tube is ⁇ N1401>
  • the first isolation MOS tube is ⁇ N1402>
  • the second sense amplifier P tube is ⁇ P1400>
  • the first The sense amplifier P tube is ⁇ P1401>
  • the second isolation MOS tube is ⁇ N1403>
  • the second offset cancellation MOS tube is ⁇ N1404>.
  • the third isolation MOS transistor is ⁇ N1409> (refer to Figure 8)
  • the fourth isolation MOS transistor is ⁇ N1429>
  • the pre-charge MOS transistor is ⁇ N1427 >
  • the first sense amplifier N tube is ⁇ N1420>
  • the first offset cancellation MOS tube is ⁇ N1421>
  • the first isolation MOS tube is ⁇ N1422>
  • the second sense amplifier P tube is ⁇ P1420>
  • the first The sense amplifier P tube is ⁇ P1421>
  • the second isolation MOS tube is ⁇ N1423>
  • the second offset cancellation MOS tube is ⁇ N1424>.
  • the sense amplifier circuits connected to the bit lines BL3 and BL4 and the complementary bit lines BLB3 and BLB4 that is, they are arranged adjacent to the first sense amplifier structure 301 and the second sense amplifier structure 302 in the direction in which the word line WL extends.
  • the measurement and amplification circuit will not be described in detail in this embodiment.
  • a precharge MOS transistor in this figure is taken as an example for illustration.
  • a precharge function for precharging the complementary bit line BLB can be added in FIG. Charging MOS tube.
  • a precharge MOS transistor for precharging the bit line BL can be added in FIG. precharge time.
  • the left figure in FIG. 10 corresponds to the layout of FIG. 8
  • the right figure in FIG. 10 corresponds to the layout of FIG. 9
  • the oblique frame area is the layout layout of the active layer
  • the white frame area is the layout layout of the gate layer.
  • the shaded area is the layout of the contact layer.
  • the solid arrows pass through the layout of the contact layer, indicating that the structure represented by the solid arrows is in contact with the contact layer; any region passed by the dotted arrows does not contact each other.
  • the first readout circuit structure and the second circuit structure can be arranged in the same area, the transistors are regularly arranged, occupying the smallest area, multiple transistors can be prepared by the same process, and the process preparation cost is reduced.
  • the voltage of the first voltage is greater than the voltage of the second voltage, that is, the first voltage is a high level corresponding to logic "1", and the second voltage is a low level corresponding to logic "0"; in other embodiments , it can also be set that the voltage of the first voltage is lower than the voltage of the second voltage, that is, the first voltage is a low level corresponding to logic "0", and the second voltage is a high level corresponding to logic "1".
  • the precharge stage it is used to precharge the readout circuit, so as to precharge the potential of each line in the readout circuit to a preset voltage;
  • the second isolation signal ISO2 in the S1 stage may also be at a high level.
  • the S2 stage consists of three parts: the pre-S2 stage, the middle stage of S2 and the post-S2 stage.
  • the word line WL is turned on, and the stored data potential is transmitted from the memory cell to the bit line BL or the complementary bit line BLB.
  • the first isolation signal ISO1 is not received, and the first read bit line SABL and The bit line BL is isolated, and the first complementary readout bit line SABLB is isolated from the complementary bit line BLB.
  • the first signal terminal PCS of the sense amplifier module provides the first voltage, supplies the second voltage to the second signal terminal NCS, and continuously provides the offset elimination signal OC, and connects the first sense amplifier N transistor ⁇ N1> and the second sense
  • the offset voltage difference formed by the amplification difference of the sense amplifier N transistor ⁇ N2> and the amplification difference of the first sense amplifier P transistor ⁇ P1> and the second sense amplifier P transistor ⁇ P2> is transferred to the second readout bit line
  • the potentials of the second sense bit line ISABL and the second complementary sense bit line ISABLB are set to have a difference in offset voltage, and at the same time due to the offset cancel signal OC, the second An offset elimination MOS transistor ⁇ 31> and a second offset elimination MOS transistor ⁇ 32> are turned on, the second read bit line ISABL is connected to the first read
  • the signals received by the first signal terminal PCS and the second signal terminal NCS are restored to a preset voltage.
  • the bit line BL is electrically connected to the first read bit line SABL
  • the complementary bit line BLB is electrically connected to the first complementary read bit line SABLB
  • the bit line BL and the first read bit line SABL perform charge sharing, or the complementary bit line BLB and the first complementary read bit line SABLB are electrically connected to perform charge sharing, so that the potential of the memory cell turned on by the word line WL is synchronized to the first
  • the read bit line SABL or the first complementary read bit line SABLB, and the synchronized potential of the first read bit line SABL or the first complementary read bit line SABLB has an offset voltage difference to cross-synchronize the offset potential (
  • the offset voltage on the second read bit line ISABL is synchronized to the first complementary read bit line SABLB, and at this stage will be synchronized to the first read bit line (SABL) to compensate for the first complementary read bit line
  • SABL the first read bit line
  • the sense amplifier module reads out the stored data after sensing and amplifying the potentials of the first readout bit line SABL and the first complementary readout bit line SABLB, and performs a check on the potential of the memory cell. Data Recovery.
  • the potential of each line in the readout circuit is precharged to a preset voltage by precharging to prepare for the next readout of data.
  • the readout circuit is precharged, the first isolation signal ISO1, the offset elimination signal OC and the external preset voltage VBLP are provided, and the bit line BL, the first readout bit line SABL, and the second readout bit line
  • the potentials of SABLB, bit line BL, first read bit line SABL, and second read bit line SABLB are precharged to a preset voltage VBLP;
  • the word line WL is turned on, and the memory cell performs charge sharing with the bit line BL. Since the stored data is 0, the potential of the bit line BL will be lower than the preset voltage VBLP after the charge sharing. At the same time, the offset cancellation signal OC is maintained, and the sense amplifier module executes the offset cancellation process. After the offset voltage difference is transferred, assuming that the potential of the second complementary read bit line ISABLB is lower than the potential of the second read bit line ISABL, the first The potential of the sense bit line SABL is lower than the potential of the first complementary sense bit line SABLB.
  • the first isolation signal ISO1 and the second isolation signal ISO2 are provided, the bit line BL shares charge with the first read bit line SABL, the potential of the first read bit line SABLB is further pulled down, and the potential of the bit line BL then partially recovered. After the complementary bit line BL is connected to the first complementary read bit line SABLB, the potential remains unchanged.
  • the sense amplifier module senses and amplifies the stored data according to the potentials of the first read bit line SABL and the first complementary read bit line SABLB, and restores the potential in the memory cell.
  • the readout circuit further includes: a precharge module 320 and an equalization module 310; the precharge module 320 is used to connect the bit line BL to , the first sense bit line ISABL, the second sense bit line ISABL, the complementary bit line BLB, the first complementary sense bit line ISBALB and the second complementary sense bit line ISABLB are precharged to a preset voltage.
  • the equalization module 310 is configured to keep the voltage of the second sense bit line ISABL consistent with the voltage of the second complementary sense bit line ISABLB according to the equalization signal EQ.
  • the pre-charging module 320 includes a pre-charging MOS transistor ⁇ 12>
  • the equalization module 310 includes an equalizing MOS transistor ⁇ 11>
  • the gate of the pre-charging MOS transistor ⁇ 12> is used to receive the pre-charging signal PRE, and one of the source or the drain Connect the second read bit line ISABL or the second complementary read bit line ISABLB
  • the equalized MOS transistor ⁇ 11> is used to receive the equalized signal EQ, one of the source or the drain is connected to the second read bit line ISABL, and the other One is connected to the second complementary sense bit line ISABLB.
  • this embodiment does not limit the types of the equalizing MOS transistor ⁇ 11> and the pre-charging MOS transistor ⁇ 12>.
  • the equalizing MOS transistor ⁇ 11> and the pre-charging MOS transistor ⁇ 12> may be NMOS transistors , can also be a PMOS tube.
  • the readout circuit further includes: a first precharge module 401 and a second precharge module 402; the first precharge module 401 is connected to the bit line BL or the first read bit line SABL , for precharging the bit line BL, the first sense bit line SABL and the second sense bit line ISABL to a preset voltage according to the precharge signal PRE.
  • the second precharge module 402 is connected to the complementary bit line BLB or the first complementary read bit line SABLB, and is used to precharge the complementary bit line BLB, the first complementary read bit line SABLB and the second complementary read bit line according to the precharge signal PRE bit line ISABLB to a preset voltage.
  • the first pre-charging module 401 includes a first pre-charging MOS transistor ⁇ 41>
  • the second pre-charging module includes a second pre-charging MOS transistor ⁇ 42>
  • the gate of the first pre-charging MOS transistor ⁇ 41> is used to receive a pre-charging signal PRE, one of the source or the drain is connected to the bit line BL or the first read bit line SABL, and the other is used to receive a preset voltage.
  • the gate of the second precharge MOS transistor ⁇ 42> is used to receive the precharge signal PRE, one of the source or the drain is connected to the complementary bit line BLB or the first complementary read bit line SABLB, and the other is used to receive the precharge signal PRE Set the voltage.
  • connection mode of "source” and “drain” does not constitute a limitation to this embodiment. In other embodiments, the connection manner of “drain” replacing “source” and “source” replacing “drain” may be used.
  • this embodiment does not limit the types of the first pre-charge MOS transistor ⁇ 41> and the second pre-charge MOS transistor ⁇ 42>.
  • the first pre-charge MOS transistor ⁇ 41> and the second pre-charge MOS transistor ⁇ 41> can be an NMOS tube or a PMOS tube.
  • the "preset voltage” mentioned above is the voltage required for pre-charging in the pre-charging phase of the memory, and the specific voltage is set according to the pre-charging voltage required for the normal operation of the memory.
  • the preset voltage VBLP 1/2VDD, wherein, VDD is the internal power supply voltage of the chip; in some embodiments, the pre-charge voltage VBLP can be set according to specific application scenarios.
  • the offset elimination module 203 includes a first offset elimination MOS transistor ⁇ 31> and a second offset elimination MOS transistor ⁇ 32>; the gate of the first offset elimination MOS transistor ⁇ 31> The pole is used to receive the offset cancellation signal OC, one of the source or the drain is connected to the second complementary read bit line ISABLB, and the other is connected to the first read bit line SABL; the second offset cancel MOS transistor ⁇ 32 > The gate is used to receive the offset cancellation signal OC, one of the source or the drain is connected to the second read bit line ISABL, and the other is connected to the first complementary read bit line SABLB.
  • the specific connection mode of "source” and “drain” does not constitute a limitation to this embodiment , in other embodiments, the connection manner of "drain” replacing “source” and “source” replacing “drain” may be adopted.
  • this embodiment does not limit the types of the first offset elimination MOS transistor ⁇ 31> and the second offset elimination MOS transistor ⁇ 32>.
  • the first offset elimination MOS transistor ⁇ 31> and the second offset elimination MOS transistor ⁇ 31> can be an NMOS transistor or a PMOS transistor.
  • the first isolation module 201 isolates the bit line BL and the first read bit line SABL, and blocks the complementary bit line BLB and the first complementary read bit line SABLB, so as to prevent the potential change of the bit line BL and the complementary bit line BLB from affecting
  • the sense amplifier module so that the word line WL is turned on in advance without affecting the sense amplifier module, and the word line WL is turned on in advance to synchronize the potential on the memory cell 100 to the initial bit line BL or the initial complementary bit line BLB, so that there is sufficient time It is used to sense the potential amplification of the amplification module, thereby improving the speed and accuracy of memory data readout.
  • Another embodiment of the present disclosure provides a data readout method, which is applied to the layout structure of the readout circuit provided by the above-mentioned embodiments.
  • the data readout method provided by this embodiment will be further described in detail below in conjunction with the accompanying drawings, specifically as follows:
  • the data readout method has three readout stages, including:
  • an equalizing signal (Equalizing Signal, EQ)
  • the first isolation signal Isolation Signal 1, ISO1
  • an offset canceling signal offset canceling signal, OC
  • the bit line BL and the first read
  • the output bit line ISABL, the second sensing bit line SABL, the complementary bit line BLB, the first complementary sensing bit line ISABLB and the second complementary sensing bit line SABLB are precharged to a preset voltage.
  • an equalization signal EQ to electrically connect the second read bit line ISABL and the second complementary read bit line ISABLB, provide the first isolation signal ISO1 to electrically connect the bit line BL and the first read bit line SABL, and electrically connect the complementary bit line BLB and the first complementary read bit line SABLB, provide an offset cancel signal OC, electrically connect the second read bit line ISABL and the first complementary read bit line SABLB, and electrically connect the second complementary read bit line ISABLB and the first Read the bit line SABL, and then provide a precharge signal (Precharge Signal, PRE), the bit line BL, the first read bit line ISABL, the second read bit line SABL, the complementary bit line BLB, the first complementary read bit
  • the line ISABLB and the second complementary sense bit line SABLB are precharged to a preset voltage.
  • the second isolation signal ISO2 may also be at a high level in the first readout phase S1.
  • the preset voltage VBLP 1/2VDD, where VDD is the internal power supply voltage of the chip; in other embodiments, the preset voltage VBLP can be set according to specific application scenarios.
  • the offset cancellation signal OC is maintained for a preset duration, and the offset cancellation is performed on the sense amplifier module through the first voltage and the second voltage applied to both ends of the sense amplifier module, and at the same time, the storage array
  • the word line WL is turned on, and charge sharing is performed based on the potential of the bit line BL and the memory cells in the memory array.
  • the first isolation signal ISO1 and the second isolation signal ISO2 are provided, the stored data is transmitted from the bit line BL to the first readout bit line SABL, and the complementary bit line BL maintains a preset voltage, and the first The potential of the sense bit line SABL is charge-shared with the potential of the second sense bit line ISABL.
  • the stored data can also be transmitted from the complementary bit line BLB to the first complementary read bit line SABLB, the bit line BL maintains a preset voltage, and the point of the first complementary read bit line SABLB Charge sharing with the potential of the second complementary readout bit line ISABLB; in addition, in some embodiments, stored data can be simultaneously transmitted through the bit line BL and the complementary bit line BLB.
  • the sense amplifier module is based on the second readout bit line ISABL through the first voltage and the second voltage applied to both ends of the sense amplifier module. Sensing and amplifying the stored data with the potential of the second complementary read bit line ISABLB, reading the stored data, and recovering the stored data in the memory cell.
  • the second read-out phase includes a first sub-phase, a second sub-phase and a third sub-phase performed in sequence.
  • the first voltage and the second voltage are applied to both ends of the sense amplification module, and a read command and an offset cancellation signal are provided.
  • the first sub-stage is the stage before S2, the word line WL is opened based on the read command of the memory, and is used to synchronize the potential of the memory cell to the bit line BL or the complementary bit line BLB; in addition, in the stage before S2, the sense amplifier module
  • the first signal terminal PCS provides the first voltage, provides the second voltage to the second signal terminal NCS, and continuously provides the offset cancellation signal OC, and the first sense amplifier N tube ⁇ N1> and the second sense amplifier N tube
  • the amplification difference of ⁇ N2>, and the offset voltage difference formed by the amplification difference of the first sense amplifier P transistor ⁇ P1> and the second sense amplifier P transistor ⁇ P2> is transferred to the second readout bit line ISABL and the second
  • the potentials of the second sense bit line ISABL and the second complementary sense bit line ISABLB are set to have a difference in offset voltage, and at the same time due to the offset cancel signal OC, the first offset cancel MOS transistor ⁇ 31> and the
  • the first voltage and the second voltage are restored to preset voltages.
  • a first isolated signal ISO1 and a second isolated signal ISO2 are provided.
  • the third sub-stage is the stage after S2, providing the first isolation signal ISO1 and the second isolation signal ISO2, electrically connecting the bit line BL and the first read bit line SABL, and connecting the complementary bit line BLB and the first complementary bit line SABLB is electrically connected, and the bit line BL is electrically connected to the first read bit line SABL for charge sharing, or the complementary bit line BLB is electrically connected to the first complementary read bit line SABLB for charge sharing, so that the potential of the memory cell opened by the word line WL Synchronized to the first read bit line SABL or the first complementary read bit line SABLB, and the potential of the synchronized first read bit line SABL or the first complementary read bit line SABLB has an offset voltage difference that will be offset Potential cross synchronization (during the offset elimination process, the offset voltage on the second read bit line ISABL is synchronized to the first complementary read bit line SABLB, and will be synchronized to the first read bit line SABL at this stage) , to compensate the amplification difference of the first sense amplifier
  • the second sub-stage further includes: providing the equalization signal to balance the voltage between the second read bit line ISABL and the second complementary read bit line ISABLB difference.
  • the potential changes of the bit line BL and the complementary bit line BLB are prevented from affecting the sense amplification module, In this way, the word line WL is turned on in advance without affecting the sense amplifier module, and the word line WL is turned on in advance to synchronize the potential on the memory cell 100 to the initial bit line BL or the initial complementary bit line BLB, so that there is sufficient time for sense amplification The potential of the module is amplified, thereby improving the speed and accuracy of memory data readout.
  • the layout structure and data readout method of the readout circuit provide a new readout circuit that ensures sufficient time for the potential amplification of the sense amplifier module, thereby improving the memory data readout efficiency.
  • Speed and accuracy at the same time, the first and second readout circuit structures are arranged adjacent to each other, and each part is arranged in an orderly manner, so as to ensure that the area occupied by the readout circuit structure is the smallest, and the connection between the devices is the shortest.

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Abstract

本公开涉及半导体电路设计领域，涉及一种读出电路的版图结构和数据读出方法，包括：具有相同构造的第一读出电路结构和第二读出电路结构，第一读出电路结构和第二读出电路结构均包括：第一隔离模块，用于根据第一隔离信号导通，电连接位线和第一读出位线，电连接互补位线和第一互补读出位线；第二隔离模块，用于根据第二隔离信号导通，电连接第一读出位线和第二读出位线，电连接第一互补读出位线和第二互补读出位线；感测放大模块，用于第一隔离模块和第二隔离模块导通时，感测并读出存储阵列的数据信号；偏移消除模块，用于根据偏移消除信号，电连接第一互补读出位线与第二读出位线，以提高数据读出的准确性。

Description

读出电路的版图结构和数据读出方法
本公开基于申请号为202111347655.2、申请日为2021年11月15日、申请名称为“读出电路的版图结构和数据读出方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及但不限于一种读出电路的版图结构和数据读出方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
DRAM可以分为双倍速率同步(Double Data Rate，DDR)动态随机存储器、GDDR(Graphics Double Data Rate)动态随机存储器、低功耗双倍速率同步(Low Power Double Data Rate，LPDDR)动态随机存储器。随着DRAM应用的领域越来越多，如DRAM越来越多的应用于移动领域，用户对于DRAM功耗指标的要求越来越高。
然而，目前的DRAM性能仍有待提高。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种读出电路的版图结构和数据读出方法，设计一种新的读出电路，保证有充足的时间用于感测放大模块的电位放大，从而提高存储器数据读出的速度和准确性，同时将第一和第二读出电路结构相邻设置，各部分有序分布，保证读出电路结构所占面积最小，各器件之间的连接最短。
本公开实施例提供了一种读出电路版图结构，包括：具有相同构造的第一读出电路结构和第二读出电路结构，第一读出电路结构和第二读出电路结构均包括：第一隔离模块，用于根据第一隔离信号导通，电连接位线和第一读出位线，电连接互补位线和第一互补读出位线；第二隔离模块，用于根据第二隔离信号导通，电连接第一读出位线和第二读出位线，电连接第一互补读出位线和第二互补读出位线；感测放大模块，用于第一隔离模块和第二隔离模块导通时，感测并读出存储阵列的数据信号；偏移消除模块，用于根据偏移消除信号，电连接第一互补读出位线与第二读出位线；第一读出电路结构通过第一位线及第一互补位线耦合第一相邻存储阵列；第二读出电路结构通过第二位线耦合及第二互补位线耦合第二相邻存储阵列；第一读出电路结构中第二隔离模块、感测放大模块和偏移消除模块设置在第一区域中；在位线延伸方向上，第一读出电路结构中的第一隔离模块设置在第一区域两侧；第二读出电路结构中第二隔离模块、感测放大模块和偏移消除模块设置在第二区域中；在位线延伸方向上，第二读出电路结构中的第一隔离模块设置在第二区域两侧；其中，第一区域和第二区域在位线延伸方向上相邻设置。
根据本公开的一些实施例，第二隔离模块包括：第一隔离MOS管和第二隔离MOS管；第一隔离MOS管源极或漏极的其中一者连接第一读出位线，另一者连接第二读出位线，栅极用于接收第二隔离信号；第二隔离MOS管源极或漏极的其中一者 连接第一互补读出位线，另一者连接第二互补读出位线，栅极用于接收第二隔离信号。
根据本公开的一些实施例，第一隔离模块包括：第三隔离MOS管和第四隔离MOS管；第三隔离MOS管源极或漏极的其中一者连接第一读出位线，另一者连接位线，栅极用于接收第一隔离信号；第四隔离MOS管源极或漏极的其中一者连接第一互补读出位线，另一者连接互补位线，栅极用于接收第一隔离信号。
根据本公开的一些实施例，感测放大模块，包括：第一感测放大N管，栅极连接第一读出位线，源极或漏极的一者连接第二互补读出位线，另一者连接第二信号端，第二信号端用于提供第二电压；第二感测放大N管，栅极连接第一互补读出位线，源极或漏极的一者连接第二读出位线，另一者连接第二信号端；第一感测放大P管，栅极连接第二读出位线，源极或漏极的一者连接第二互补读出位线，另一者连接第一信号端，第一信号端用于提供第一电压，第一电压大于第二电压；第二感测放大P管，栅极连接第二互补读出位线，源极或漏极的一者连接第二读出位线，另一者连接第一信号端。
根据本公开的一些实施例，读出电路还包括：预充电模块，用于根据预充电信号将位线、第一读出位线、第二读出位线、互补位线、第一互补读出位线和第二互补读出位线预充电至预设电压；均衡模块，用于根据均衡信号，保持第二读出位线的电压和第二互补读出位线的电压一致。
根据本公开的一些实施例，预充电模块包括预充电MOS管，均衡模块包括均衡MOS管；预充电MOS管栅极用于接收预充电信号，源极或漏极的其中一者连接第二读出位线或第二互补读出位线，另一者用于接收预设电压；均衡MOS管栅极用于接收均衡信号，源极或漏极的其中一者连接第二读出位线，另一者连接第二互补读出位线。
根据本公开的一些实施例，读出电路还包括：第一预充电模块，连接位线或第一读出位线，用于根据预充电信号预充位线、第一读出位线和第二读出位线至预设电压；第二预充电模块，连接互补位线或第一互补读出位线，用于根据预充电信号预充互补位线、第一互补读出位线和第二互补读出位线至预设电压。
根据本公开的一些实施例，第一预充电模块包括第一预充电MOS管，第二预充电模块包括第二预充电MOS管；第一预充电MOS管栅极用于接收预充电信号，源极或漏极的其中一者连接位线或第一读出位线，另一者用于接收预设电压；第二预充电MOS管栅极用于接收预充电信号，源极或漏极的其中一者连接互补位线或第一互补读出位线，另一者用于接收预设电压。
根据本公开的一些实施例，偏移消除模块包括第一偏移消除MOS管和第二偏移消除MOS管；第一偏移消除MOS管栅极用于接收偏移消除信号，源极或者漏极的其中一者连接第二互补读出位线，另一者连接第一读出位线；第二偏移消除MOS管栅极用于接收偏移消除信号，源极或者漏极的其中一者连接第二读出位线，另一者连接第一互补读出位线。
根据本公开的一些实施例，第一读出电路结构的第三隔离MOS管通过接触插塞与第一位线和第一读出位线连接，用于根据第一隔离信号，电连接第一位线和第一读出电路结构的第一读出位线；第一读出电路结构的第四隔离MOS管通过接触插塞与第一互补位线和第一互补读出位线连接，用于根据第一隔离信号，电连接第一读出电路结构的第一互补读出位线与第一互补位线；第二读出电路结构的第三隔离MOS管通过接触插塞与第二位线和第二读出位线连接，用于根据第一隔离信号，电连接第二位线和第二读出电路结构的第一读出位线；第二读出电路结构的第四隔离MOS管通过接触插塞与第二互补位线和第二互补读出位线连接，用于根据第一隔离 信号，电连接第二读出电路结构的第一互补读出位线与第二互补位线。
根据本公开的一些实施例，在位线延伸方向上，第一读出电路结构的第三隔离MOS管设置在第一区域远离第二区域的一侧；在字线延伸方向上，第二读出电路结构的第三隔离MOS管与第一读出电路结构的第三隔离MOS管相邻设置；在位线延伸方向上，第二读出电路结构的第四隔离MOS管设置在第二区域远离第一区域的一侧；在字线延伸方向上，第一读出电路结构的第四隔离MOS管于第二读出电路结构的第四隔离MOS管相邻设置。
根据本公开的一些实施例，在位线延伸方向上，第一读出电路结构的第三隔离MOS管设置在第一区域远离第二区域的一侧；在位线延伸方向上，第一读出电路结构的第四隔离MOS管设置在第一区域靠近第二区域的一侧；在位线延伸方向上，第二读出电路结构的第三隔离MOS管设置在第二区域远离第一区域的一侧；在位线延伸方向上，第二读出电路结构的第四隔离MOS管设置在第二区域靠近第一区域的一侧。
根据本公开的一些实施例，第一读出电路结构的第四隔离MOS管靠近第一区域设置，第二读出电路结构的第三隔离MOS管靠近第二区域设置。
根据本公开的一些实施例，第一读出电路结构的第四隔离MOS管靠近第二区域设置，第二读出电路结构的第三隔离MOS管靠近第一区域设置。
根据本公开的一些实施例，预充电模块包括第一预充电MOS管和第二预充电MOS管；第二隔离模块包括第一隔离MOS管和第二隔离MOS管；均衡模块包括均衡MOS管；偏移消除模块包括第一偏移消除MOS管和第二偏移消除MOS管；在位线延伸方向且靠近第二区域的方向上的第一区域中，依次设置第一读出电路结构的第一预充电MOS管、第一感测放大N管、第一偏移消除MOS管、第一隔离MOS管、第二感测放大P管、第一感测放大P管、第二隔离MOS管、第二偏移消除MOS管、第二预充电MOS管；在位线延伸方向且靠近第一区域的方向上的第二区域中，依次设置第二读出电路结构的第一预充电MOS管、第一感测放大N管、第一偏移消除MOS管、第一隔离MOS管、第二感测放大P管、第一感测放大P管、第二隔离MOS管、第二偏移消除MOS管、第二预充电MOS管。
本公开实施例还提供了一种数据读出方法，引用于上述读出电路的版图结构，具有三个读出阶段，包括：在第一读出阶段，提供均衡信号、第一隔离信号、偏移消除信号，对位线、第一读出位线、第二读出位线、互补位线、第一互补读出位线和第二互补读出位线预充电至预设电压；在第二读出阶段开始阶段，维持预设时长的偏移消除信号，通过施加在感测放大模块两端的第一电压和第二电压，对感测放大模块进行偏移消除，同时存储阵列的字线打开，基于位线与存储阵列中存储单元内的电位进行电荷分享；在第二读出阶段执行过程中，提供第一隔离信号和第二隔离信号，存储数据由位线传输至第一读出位线，互补位线维持预设电压，第一读出位线的电位与第二读出位线的电位进行电荷分享；在第三读出阶段，维持第一隔离信号和第二隔离信号，通过施加在感测放大模块两端的第一电压和第二电压，感测放大模块根据第二读出位线和第二互补读出位线的电位感测放大存储数据，读出存储数据，并恢复存储单元内存储数据。
根据本公开的一些实施例，第二读出阶段包括依次执行的第一子阶段、第二子阶段、第三子阶段；在第一子阶段，向感测放大模块两端施加第一电压和第二电压，并提供读命令和偏移消除信号；在第二子阶段，将第一电压和第二电压恢复至预设电压；在第三子阶段，提供第一隔离信号和第二隔离信号。
根据本公开的一些实施例，在第二子阶段还包括：提供所述均衡信号。
本公开实施例提供的读出电路及数据读出方法，通过第一隔离模块隔离位线和第 一读出位线，并阻断互补位线和第一互补读出位线，避免位线和互补位线的电位变化会影响感测放大模块，从而实现提前开启字线但不影响感测放大模块，提前打开字线将存储单元上的电位同步至初始位线或初始互补位线，增大字线打开至位线打开的间隔时间，增大字线打开至位线打开的间隔时间，使得有充足的时间用于感测放大模块的电位放大，从而提高存储器数据读出的速度和准确性，同时将第一和第二读出电路结构相邻设置，各部分有序分布，保证读出电路结构所占面积最小，各器件之间的连接最短。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的读出电路的结构示意图；
图2为本公开一实施例提供的读出电路的读出时序示意图；
图3和图4为本公开一实施例提供的具备预充电功能的读出电路的结构示意图；
图5为本公开一实施例提供的读出电路版图的结构示意图；
图6～图7为本公开一实施例提供的读出电路版图的具体结构示意图；
图8为本公开一实施例提供的第一读出电路结构的电路结构示意图；
图9为本公开一实施例提供的第二读出电路结构的电路结构示意图；
图10为本公开一实施例提供的对应图8和图9的具体读出电路版图。
附图标记：
100、存储阵列；201、第一隔离模块；202、第二隔离模块；203、偏移消除模块；310、均衡模块；320、预充电模块；301、第一读出电路结构；302、第二读出电路结构；401、第一预充电模块；402、第二预充电模块；
<11>、均衡MOS管；<12>、预充电MOS管；<21>、第一隔离MOS管；<22>、第二隔离MOS管；<23>、第三隔离MOS管；<24>、第四隔离MOS管；<31>、第一偏移消除MOS管；<32>、第二偏移消除MOS管；<N1>、第一感测放大N管；<N2>、第二感测放大N管；<P1>、第一感测放大P管；<P2>、第二感测放大P管；<41>、第一预充电MOS管；<42>、第二预充电MOS管；
BL、位线；BL1、第一位线；BL2、第二位线；BLB、互补位线；BLB1、第一互补位线；BLB2、第二互补位线；SABL、第一读出位线；ISABL、第二读出位线；SABLB、第一互补读出位线；ISABLB、第二互补读出位线；ISO1、第一隔离信号；ISO2、第二隔离信号；OC、偏移消除信号；PCS、第一信号端；NCS、第二信号端；
<N1402>、第一隔离MOS管；<N1403>、第二隔离MOS管；<N1408>、第三隔离MOS管；<N1428>、第四隔离MOS管；<N1406>、预充电MOS管；<N1400>、第一感测放大N管；<N1401>、第一偏移消除MOS管；<N1404>、第二偏移消除MOS管；<P1401>、第一感测放大P管；<P1400>、第二感测放大P管；
<N1422>、第一隔离MOS管；<N1423>、第二隔离MOS管；<N1409>、第三隔离MOS管；<N1429>、第四隔离MOS管；<N1427>、预充电MOS管；<N1420>、第一感测放大N管；<N1421>、第一偏移消除MOS管；<N1424>、第二偏移消除MOS管；<P1421>、第一感测放大P管；<P1420>、第二感测放大P管。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
DRAM性能的提高，对DRAM内部电路提出了更高的信号处理速度要求。
现有具备失调补偿功能的感测放大模块在读出存储数据的过程中，需要一定的时间执行偏移消除过程，再将存储数据传输至感测放大模块，导致感测放大模块在处理读取数据的整体时间消耗变长，功耗增加，无法进一步提高数据处理速度。
本公开实施例提供了一种读出电路的版图结构，在感测放大模块执行偏移消除过程中，将存储单元内的数据提前传输至与感测放大模块连接的位线中，减小感测放大模块处理存储数据的整体时间，同时保证有充足的时间用于感测放大模块的电位放大，从而提高存储器数据读出的速度和准确性，同时将第一和第二读出电路结构相邻设置，各部分有序分布，保证读出电路结构所占面积最小，各器件之间的连接最短。
本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图1为本实施例提供的读出电路的结构示意图，图2为本实施例提供的读出电路的读出时序示意图，图3和图4为本实施例提供的具备预充电功能的读出电路的结构示意图，图5为本实施例提供的读出电路版图的结构示意图，图6～图7为本实施例提供的读出电路版图的具体结构示意图，图8为本实施例提供的第一读出电路结构的电路结构示意图，图9为本实施例提供的第二读出电路结构的电路结构示意图，图10为本实施例提供的对应图8和图9的具体读出电路版图，以下结合附图对本实施例提供的读出电路的版图结构作进一步详细说明，具体如下：
参考图1，读出电路，设置在相邻存储阵列100之间，通过位线BL耦合一存储阵列100，通过互补位线BLB耦合另一存储阵列100，包括：
第一隔离模块201，设置在位线BL和第一读出位线SABL之间，用于根据第一隔离信号ISO1，电连接位线BL和第一读出位线SABL，还设置在互补位线BLB和第一互补读出位线SABLB之间，用于根据第一隔离信号ISO1导通，电连接互补位线BLB和第一互补读出位线SABLB。
第二隔离模块202，连接在第一读出位线SABL和第二读出位线ISABL之间，用于根据第二隔离信号ISO2导通，电连接第一读出位线SABL与第二读出位线ISABL，还连接在第一互补读出位线SABLB和第二互补读出位线ISABLB之间，用于根据第二隔离信号ISO2导通，电连接第一互补读出位线SABLB与第二互补读出位线ISABLB。
感测放大模块，与第一读出位线SABL和第一互补读出位线SABLB相连接，还与第二读出位线ISABL和第二互补读出位线ISABLB连接，用于第一隔离模块201和第二隔离模块202导通时，感测并读出存储阵列100的数据信号。
偏移消除模块203，连接在第一读出位线SABL与第二互补读出位线ISABLB之间，用于根据偏移消除信号OC，电连接第一读出位线SABL与第二互补读出位线ISABLB，还连接在第一互补读出位线SABLB与第二读出位线ISABL之间，用于根据偏移消除信号，电连接第一互补读出位线SABLB与第二读出位线ISABL。
通过第一隔离模块201隔离位线BL和第一读出位线SABL，并阻断互补位线BLB和第一互补读出位线SABLB，避免位线BL和互补位线BLB的电位变化会影响 感测放大模块，从而实现提前开启字线WL但不影响感测放大模块，提前打开字线WL将存储单元100上的电位同步至初始位线BL或初始互补位线BLB，使得有充足的时间用于感测放大模块的电位放大，从而提高存储器数据读出的速度和准确性。
参考图5，第一读出电路结构301通过第一位线BL1耦合相邻存储阵列之间的一存储阵列，通过第一互补位线BLB1耦合相邻存储阵列之间的另一存储阵列，第二读出电路结构302通过第二位线BL2耦合相邻存储阵列之间的一存储阵列，通过第二互补位线BLB2耦合相邻存储阵列之间的另一存储阵列；第一读出电路结构301中的第二隔离模块、感测放大模块和偏移消除模块设置在第一区域中，在位线BL延伸方向上，第一读出电路结构301中的第一隔离模块设置在第一区域两侧，第二读出电路结构302中的第二隔离模块、感测放大模块和偏移消除模块设置在第二区域中，在位线BL延伸方向上，第二读出电路结构302中的第一隔离模块设置在第二区域两侧，其中，第一区域和第二区域在位线延伸方向上相邻设置。
将第一和第二读出电路结构相邻设置，各部分有序分布，保证读出电路结构所占面积最小，各器件之间的连接最短。
在一些实施例中，第一隔离模块201包括：第三隔离MOS管<23>和第四隔离MOS管<24>；第三隔离MOS管<23>源极或漏极的其中一者连接第一读出位线SABL，另一者连接位线BL，栅极用于接收第一隔离信号ISO1；第四隔离MOS管<24>源极或漏极的其中一者连接第一互补读出位线SABLB，另一者连接互补位线BLB，栅极用于接收第一隔离信号ISO1。
需要说明的是，对于第三隔离MOS管<23>和第四隔离MOS管<24>，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式。
另外，本实施例并不对第三隔离MOS管<23>和第四隔离MOS管<24>的类型进行限定，在具体的应用中，第三隔离MOS管<23>和第四隔离MOS管<24>可以为NMOS管，也可以为PMOS管。
参考图5～图7，第一隔离模块包括第三隔离MOS管<23>和第四隔离MOS管<24>。
第一读出电路结构301的第三隔离MOS管<23>通过接触插塞与第一位线BL1和第一读出电路结构301的第一读出位线(未图示)连接，第一读出电路结构301的第四隔离MOS管<24>通过接触插塞与第一互补位线BLB1和第一读出电路结构301的第一互补读出位线(未图示)连接，第二读出电路结构302的第三隔离MOS管<23>通过接触插塞与第二位线BL2和第二读出电路结构302的第一读出位线(未图示)连接，第二读出电路结构302的第四隔离MOS管<24>通过接触插塞与第二互补位线BLB2和第二读出电路结构302的第一互补读出位线(未图示)连接。
在一个例子中，参考图5，在位线BL延伸方向上，第一读出电路结构301的第三隔离MOS管<23>设置在第一区域远离第二区域的一侧，在字线WL延伸方向上，第二读出电路结构302的第三隔离MOS管<23>与第一读出电路结构301的第三隔离MOS管<23>相邻设置，在位线BL延伸方向上，第二读出电路结构302的第四隔离MOS管<24>设置在第二区域远离第一区域的一侧，在字线WL延伸方向上，第一读出电路结构301的第四隔离MOS管<24>与第二读出电路结构302的第四隔离MOS管<24>相邻设置。
在一个例子中，参考图6和图7，在位线BL延伸方向上，第一读出电路结构301的第三隔离MOS管<23>设置在第一区域远离第二区域的一侧；在位线BL延伸方向上，第一读出电路结构301的第四隔离MOS管<24>设置在第一区域靠近第二区域的一侧；在位线BL延伸方向上，第二读出电路结构302的第三隔离MOS管<23>设置 在第二区域远离第一区域的一侧；在位线BL延伸方向上，第二读出电路结构302的第四隔离MOS管<24>设置在第二区域靠近第一区域的一侧。
在一个具体的例子中，参考图6，第一读出电路结构301的第四隔离MOS管<24>靠近第一区域设置，第二读出电路结构的第三隔离MOS管<23>靠近第二区域设置。
在一个具体的例子中，参考图7，第一读出电路结构301的第四隔离MOS管<24>靠近第二区域设置，第二读出电路结构的第三隔离MOS管<23>靠近第一区域设置。
在一些实施例中，第二隔离模块202包括：第一隔离MOS管<21>和第二隔离MOS管<22>；第一隔离MOS管<21>源极或漏极的其中一者连接第一读出位线SABL，另一者连接第二读出位线ISABL，栅极用于接收第二隔离信号ISO2；第二隔离MOS管<22>源极或漏极的其中一者连接第一互补读出位线SABLB，另一者连接第二互补读出位线ISABLB，栅极用于接收第二隔离信号ISO2。
需要说明的是，对于第一隔离MOS管<21>和第二隔离MOS管<22>，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式。
另外，本实施例并不对第一隔离MOS管<21>和第二隔离MOS管<22>的类型进行限定，在具体的应用中，第一隔离MOS管<21>和第二隔离MOS管<22>，也可以为PMOS管。
在一些实施例中，感测放大模块，包括：第一感测放大N管<N1>，栅极连接第一读出位线SABL，源极或漏极的一者连接第二互补读出位线ISABLB，另一者连接第二信号端NCS，第二信号端NCS用于提供第二电压；第二感测放大N管<N2>，栅极连接第一互补读出位线SABLB，源极或漏极的一者连接第二读出位线ISABL，另一者连接第二信号端NCS；第一感测放大P管<P1>，栅极连接第二读出位线ISABL，源极或漏极的一者连接第二互补读出位线ISABLB，另一者连接第一信号端PCS，第一信号端PCS用于提供第一电压，第一电压大于第二电压；第二感测放大P管<P2>，栅极连接第二互补读出位线ISABLB，源极或漏极的一者连接第二读出位线ISABL，另一者连接第一信号端PCS。
对于第一读出电路结构301和第二读出电路结构302，预充电模块包括第一预充电MOS管和第二预充电MOS管，均衡模块包括均衡MOS管；第二隔离模块包括第一隔离MOS管和第二隔离MOS管子，偏移消除模块包括第一偏移消除MOS管和第二偏移消除MOS管。
在位线BL延伸方向且靠近第二区域的方向上的第一区域中，依次设置第一读出电路结构301的第一预充电MOS管、第一感测放大N管、第一偏移消除MOS管、第一隔离MOS管、第二感测放大P管、第一感测放大P管、第二隔离MOS管、第二偏移消除MOS管、第二预充电MOS管。
在位线BL延伸方向且靠近第一区域的方向上的第二区域中，依次设置第二读出电路结构302的第一预充电MOS管、第一感测放大N管、第一偏移消除MOS管、第一隔离MOS管、第二感测放大P管、第一感测放大P管、第二隔离MOS管、第二偏移消除MOS管、第二预充电MOS管。
对于第一感测放大结构301，第一区域的电路图参考图8，第三隔离MOS管即<N1408>，第四隔离MOS管即<N1428>(参考图9)，预充电MOS管即<N1406>，第一感测放大N管即<N1400>，第一偏移消除MOS管即<N1401>，第一隔离MOS管即<N1402>，第二感测放大P管即<P1400>，第一感测放大P管即<P1401>，第二隔离MOS管即<N1403>，第二偏移消除MOS管即<N1404>。
对于第二感测放大结构302，第二区域的电路图参考图9，第三隔离MOS管即<N1409>(参考图8)，第四隔离MOS管即<N1429>，预充电MOS管即<N1427>， 第一感测放大N管即<N1420>，第一偏移消除MOS管即<N1421>，第一隔离MOS管即<N1422>，第二感测放大P管即<P1420>，第一感测放大P管即<P1421>，第二隔离MOS管即<N1423>，第二偏移消除MOS管即<N1424>。
对于位线BL3和BL4以及互补位线BLB3和BLB4上所连接的感测放大电路即在字线WL延伸方向上与第一感测放大结构301和第二感测放大结构302相邻设置在感测放大电路，本实施例不再进行过多赘述。
需要说明的是，对于第一感测放大结构301，本附图一个预充电MOS管为例进行附图说明，在其他实施例中，可以在图9新增对互补位线BLB预充电的预充电MOS管。同理，对于第二感测放大结构302，可以在图8新增对位线BL预充电的预充电MOS管，采用贴近位线或互补位线的预充电设置，保证电压传输消耗最少，节约预充电时间。
图10中左图即对应于图8的版图，图10中右图即对应于图9的版图，其中，斜框区域为有源层的版图布局，白框区域为栅极层的版图布局，阴影区域为接触层的版图布局。在该图中，实线箭头经过接触层的版图布局，说明实线箭头所表征的结构与接触层相互接触；虚线箭头所经过的任何区域都不相互接触。采用该种版图设计，能够将第一读出电路结构和第二电路结构设置于同一区域，各晶体管规则排布，所占面积最小，能够采用相同的工序制备多个晶体管，降低工艺制备成本。
在实施例中，第一电压的电压大于第二电压的电压，即第一电压为对应逻辑“1”的高电平，第二电压为对应逻辑“0”的低电平；在其他实施例中，同样可以设置为，第一电压的电压小于第二电压的电压，即第一电压为对应逻辑“0”的低电平，第二电压为对应逻辑“1”的高电平。
结合图2，对于本实施例提供的读出电路，在S1阶段，即预充电阶段，用于对读出电路进行预充电，以将读出电路中各线路的电位预充至预设电压；需要说明的是，在一些实施例中，S1阶段中第二隔离信号ISO2也可以为高电平。
S2阶段包括三个部分：依次为S2前阶段、S2中阶段和S2后阶段。
在S2前阶段，打开字线WL，存储数据电位由存储单元传输至位线BL或互补位线BLB上，在该阶段中并未接收到第一隔离信号ISO1，第一读出位线SABL和位线BL隔离，第一互补读出位线SABLB和互补位线BLB隔离，此时位线BL和互补位线BLB上的电位无法同步至感测放大模块中；另外，在S2前阶段，向感测放大模块的第一信号端PCS提供第一电压，向第二信号端NCS提供第二电压，并持续提供偏移消除信号OC，将第一感测放大N管<N1>和第二感测放大N管<N2>的放大差异，以及第一感测放大P管<P1>和第二感测放大P管<P2>的放大差异形成的偏移电压差转移至第二读出位线ISABL和第二互补读出位线ISABLB上，第二读出位线ISABL和第二互补读出位线ISABLB的电位被设置为具有偏移电压的差，同时由于具有偏移消除信号OC，第一偏移消除MOS管<31>和第二偏移消除MOS管<32>导通，第二读出位线ISABL与第一读出位线SABL连接，第二互补读出位线ISABLB与第一互补读出位线SABLB连接，第一读出位线SABL和第一互补读出位线SABLB的电位同样被设置为具有偏移电压的差。因此，感测放大模块的偏移噪声被消除。
在S2中阶段，将第一信号端PCS和第二信号端NCS所接收的信号恢复至预设电压。
在S2后阶段，提供第一隔离信号ISO1和第二隔离信号ISO2，将位线BL和第一读出位线SABL电连接，将互补位线BLB和第一互补读出位线SABLB电连接，位线BL和第一读出位线SABL进行电荷分享，或互补位线BLB和第一互补读出位线SABLB电连接进行电荷分享，以通过字线WL打开的存储单元的电位同步至第一读出位线SABL或第一互补读出位线SABLB，且同步后的第一读出位线SABL或第一 互补读出位线SABLB的电位具有偏移电压的差将偏移电位交叉同步(偏移消除过程中，第二读出位线ISABL上的偏移电压同步至第一互补读出位线SABLB上，在这一阶段会同步至第一读出位线SABL)后，以补偿第一感测放大N管<N1>和第二感测放大N管<N2>的放大差异，并补偿第一感测放大P管<P1>和第二感测放大P管<P2>的放大差异。
在S3阶段，即信号读出阶段，感测放大模块根据第一读出位线SABL和第一互补读出位线SABLB的电位感测放大后，读出存储数据，并对存储单元的电位进行数据恢复。
在S4阶段，即信号复位阶段，通过预充电，将读出电路中各线路的电位预充至预设电压，准备下一次读出数据。
以与位线BL连接的存储单元存储的数据为“0”为例，结合图2对读出电路中信号电位变化过程进行示例性说明：
在S1阶段，对读出电路进行预充电，提供第一隔离信号ISO1、偏移消除信号OC和外部预设电压VBLP，将位线BL、第一读出位线SABL、第二读出位线SABLB、位线BL、第一读出位线SABL、第二读出位线SABLB的电位预充至预设电压VBLP；
在S2前阶段，打开字线WL，存储单元与位线BL进行电荷分享，由于存储的数据为0，电荷分享后位线BL的电位会低于预设电压VBLP。同时维持偏移消除信号OC，感测放大模块执行偏移消除过程，偏移电压差转移后，假设第二互补读出位线ISABLB的电位低于第二读出位线ISABL电位，则第一读出位线SABL的电位会低于第一互补读出位线SABLB电位。
在S2后阶段，提供第一隔离信号ISO1和第二隔离信号ISO2，位线BL与第一读出位线SABL电荷分享，第一读出位线SABLB的电位被进一步拉低，位线BL电位则部分回升。互补位线BL与第一互补读出位线SABLB连接后，电位维持不变。
在S3阶段，感测放大模块根据第一读出位线SABL和第一互补读出位线SABLB的电位感测放大后读出存储数据，并恢复存储单元内电位。
对于读出电路的预充电，在一些实施例中，参考图3，读出电路，还包括：预充电模块320和均衡模块310；预充电模块320，用于根据预充电信号PRE将位线BL、第一读出位线ISABL、第二读出位线ISABL、互补位线BLB、第一互补读出位线ISBALB和第二互补读出位线ISABLB预充电至预设电压。均衡模块310，用于根据均衡信号EQ，保持第二读出位线ISABL的电压和第二互补读出位线ISABLB的电压一致。
预充电模块320包括预充电MOS管<12>，均衡模块310包括均衡MOS管<11>，预充电MOS管<12>栅极用于接收预充电信号PRE，源极或漏极的其中一者连接第二读出位线ISABL或第二互补读出位线ISABLB；均衡MOS管<11>用于接收均衡信号EQ，源极或漏极的其中一者连接第二读出位线ISABL，另一者连接第二互补读出位线ISABLB。
需要说明的是，对于均衡MOS管<11>和预充电MOS管<12>，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式。
另外，本实施例并不对均衡MOS管<11>和预充电MOS管<12>的类型进行限定，在具体的应用中，均衡MOS管<11>和预充电MOS管<12>可以为NMOS管，也可以为PMOS管。
在一些实施例中，参考图4，读出电路，还包括：第一预充电模块401和第二预充电模块402；第一预充电模块401，连接位线BL或第一读出位线SABL，用于根据 预充电信号PRE预充位线BL、第一读出位线SABL和第二读出位线ISABL至预设电压。第二预充电模块402，连接互补位线BLB或第一互补读出位线SABLB，用于根据预充电信号PRE预充互补位线BLB、第一互补读出位线SABLB和第二互补读出位线ISABLB至预设电压。
第一预充电模块401包括第一预充电MOS管<41>，第二预充电模块包括第二预充电MOS管<42>，第一预充电MOS管<41>栅极用于接收预充电信号PRE，源极或漏极的其中一者连接位线BL或第一读出位线SABL，另一者用于接收预设电压。第二预充电MOS管<42>栅极用于接收预充电信号PRE，源极或漏极的其中一者连接互补位线BLB或第一互补读出位线SABLB，另一者用于接收预设电压。
需要说明的是，对于第一预充电MOS管<41>和第二预充电MOS管<42>，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式。
另外，本实施例并不对第一预充电MOS管<41>和第二预充电MOS管<42>的类型进行限定，在具体的应用中，第一预充电MOS管<41>和第二预充电MOS管<42>可以为NMOS管，也可以为PMOS管。
需要说明的是，上文提及的“预设电压”即存储器预充电阶段中的预充电所需电压，具体电压大小根据存储器正常工作所需的预充电电压进行设定，在本实施例中，预设电压VBLP＝1/2VDD，其中，VDD为芯片内部电源电压；在一些实施例中，预充电电压VBLP可以根据具体应用场景进行设置。
继续参考图1，在本实施例中，偏移消除模块203包括第一偏移消除MOS管<31>和第二偏移消除MOS管<32>；第一偏移消除MOS管<31>栅极用于接收偏移消除信号OC，源极或漏极的其中一者连接第二互补读出位线ISABLB，另一者连接第一读出位线SABL；第二偏移消除MOS管<32>栅极用于接收偏移消除信号OC，源极或漏极的其中一者连接第二读出位线ISABL，另一者连接第一互补读出位线SABLB。
需要说明的是，对于第一偏移消除MOS管<31>和第二偏移消除MOS管<32>，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式。
另外，本实施例并不对第一偏移消除MOS管<31>和第二偏移消除MOS管<32>的类型进行限定，在具体的应用中，第一偏移消除MOS管<31>和第二偏移消除MOS管<32>可以为NMOS管，也可以为PMOS管。
通过第一隔离模块201隔离位线BL和第一读出位线SABL，并阻断互补位线BLB和第一互补读出位线SABLB，避免位线BL和互补位线BLB的电位变化会影响感测放大模块，从而实现提前开启字线WL但不影响感测放大模块，提前打开字线WL将存储单元100上的电位同步至初始位线BL或初始互补位线BLB，使得有充足的时间用于感测放大模块的电位放大，从而提高存储器数据读出的速度和准确性。
需要说明的是，为了突出本公开的创新部分，本实施例中并没有将与解决本公开所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元；本领域的普通技术人员可以理解，上述各实施例是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。
本公开另一实施例提供了一种数据读出方法，应用于上述实施例提供的读出电路的版图结构，以下结合附图对本实施例提供的数据读出方法作进一步详细说明，具体如下：
参考图2，数据读出方法，具有三个读出阶段，包括：
在第一读出阶段S1，提供均衡信号(Equalizing Signal，EQ)、第一隔离信号(Isolation Signal 1，ISO1)、偏移消除信号(offset canceling signal，OC)、对位线BL、第一读出位线ISABL、第二读出位线SABL、互补位线BLB、第一互补读出位线ISABLB和第二互补读出位线SABLB预充电至预设电压。
提供均衡信号EQ电连接第二读出位线ISABL和第二互补读出位线ISABLB，提供第一隔离信号ISO1电连接位线BL和第一读出位线SABL，并电连接互补位线BLB和第一互补读出位线SABLB，提供偏移消除信号OC，电连接第二读出位线ISABL和第一互补读出位线SABLB，并电连接第二互补读出位线ISABLB和第一读出位线SABL，然后提供预充电信号(Precharge Signal，PRE)，将位线BL、第一读出位线ISABL、第二读出位线SABL、互补位线BLB、第一互补读出位线ISABLB和第二互补读出位线SABLB预充电至预设电压。
需要说明的是，在一些实施例中，在第一读出阶段S1中第二隔离信号ISO2也可以为高电平。另外，在本实施例中，预设电压VBLP＝1/2VDD，其中，VDD为芯片内部电源电压；在其他实施例中，预设电压VBLP可以根据具体应用场景进行设置。
在第二读出阶段开始阶段，维持预设时长的偏移消除信号OC，通过施加在感测放大模块两端的第一电压和第二电压，对感测放大模块进行偏移消除，同时存储阵列的字线WL打开，基于位线BL与存储阵列中存储单元内的电位进行电荷分享。
在第二读出阶段执行过程中，提供第一隔离信号ISO1和第二隔离信号ISO2，存储数据由位线BL传输至第一读出位线SABL，互补位线BL维持预设电压，第一读出位线SABL的电位与第二读出位线ISABL的电位进行电荷分享。
需要说明的是，在一些实施例中，存储数据也可以由互补位线BLB传输至第一互补读出位线SABLB，位线BL维持预设电压，第一互补读出位线SABLB的点位与第二互补读出位线ISABLB的电位进行电荷分享；另外，在一些实施例中，存储数据可以通过位线BL和互补位线BLB同时传输。
在第三读出阶段S3，维持第一隔离信号ISO1和第二隔离信号ISO2，通过施加在感测放大模块两端的第一电压和第二电压，感测放大模块根据第二读出位线ISABL和第二互补读出位线ISABLB的电位感测放大存储数据，读出存储数据，并恢复存储单元内存储数据。
第二读出阶段包括依次执行的第一子阶段、第二子阶段和第三子阶段。
在第一子阶段，向感测放大模块两端施加第一电压和第二电压，并提供读命令和偏移消除信号。
第一子阶段即S2前阶段，字线WL基于存储器的读命令打开，用于将存储单元的电位同步至位线BL或互补位线BLB上；另外，在S2前阶段，向感测放大模块的第一信号端PCS提供第一电压，向第二信号端NCS提供第二电压，并持续提供偏移消除信号OC，将第一感测放大N管<N1>和第二感测放大N管<N2>的放大差异，以及第一感测放大P管<P1>和第二感测放大P管<P2>的放大差异形成的偏移电压差转移至第二读出位线ISABL和第二互补读出位线ISABLB上，第二读出位线ISABL和第二互补读出位线ISABLB的电位被设置为具有偏移电压的差，同时由于具有偏移消除信号OC，第一偏移消除MOS管<31>和第二偏移消除MOS管<32>导通，第二读出位线ISABL与第一读出位线SABL连接，第二互补读出位线ISABLB与第一互补读出位线SABLB连接，第一读出位线SABL和第一互补读出位线SABLB的电位同样被设置为具有偏移电压的差。因此，感测放大模块的偏移噪声被消除。
在第二子阶段，将第一电压和第二电压恢复至预设电压。
在第三子阶段，提供第一隔离信号ISO1和第二隔离信号ISO2。
第三子阶段即S2后阶段，提供第一隔离信号ISO1和第二隔离信号ISO2，将位 线BL和第一读出位线SABL电连接，将互补位线BLB和第一互补读出位线SABLB电连接，位线BL和第一读出位线SABL进行电荷分享，或互补位线BLB和第一互补读出位线SABLB电连接进行电荷分享，以通过字线WL打开的存储单元的电位同步至第一读出位线SABL或第一互补读出位线SABLB，且同步后的第一读出位线SABL或第一互补读出位线SABLB的电位具有偏移电压的差将偏移电位交叉同步(偏移消除过程中，第二读出位线ISABL上的偏移电压同步至第一互补读出位线SABLB上，在这一阶段会同步至第一读出位线SABL)后，以补偿第一感测放大N管<N1>和第二感测放大N管<N2>的放大差异，并补偿第一感测放大P管<P1>和第二感测放大P管<P2>的放大差异。
需要说明的是，参考图2，在一些实施例中，在第二子阶段还包括：提供所述均衡信号，以平衡第二读出位线ISABL第二互补读出位线ISABLB之间的电压差异。
通过隔离位线BL和第一读出位线SABL，并阻断互补位线BLB和第一互补读出位线SABLB，避免位线BL和互补位线BLB的电位变化会影响感测放大模块，从而实现提前开启字线WL但不影响感测放大模块，提前打开字线WL将存储单元100上的电位同步至初始位线BL或初始互补位线BLB，使得有充足的时间用于感测放大模块的电位放大，从而提高存储器数据读出的速度和准确性。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的读出电路的版图结构和数据读出方法，提供一种新的读 出电路，保证有充足的时间用于感测放大模块的电位放大，从而提高存储器数据读出的速度和准确性，同时将第一和第二读出电路结构相邻设置，各部分有序分布，保证读出电路结构所占面积最小，各器件之间的连接最短。

Claims (18)

  1. 一种读出电路的版图结构，包括：
    具有相同构造的第一读出电路结构和第二读出电路结构，所述第一读出电路结构和第二读出电路结构均包括：
    第一隔离模块，用于根据第一隔离信号导通，电连接位线和第一读出位线，电连接互补位线和第一互补读出位线；
    第二隔离模块，用于根据第二隔离信号导通，电连接所述第一读出位线和第二读出位线，电连接所述第一互补读出位线和第二互补读出位线；
    感测放大模块，用于所述第一隔离模块和所述第二隔离模块导通时，感测并读出存储阵列的数据信号；
    偏移消除模块，用于根据偏移消除信号，电连接所述第一互补读出位线与所述第二读出位线；
    所述第一读出电路结构通过第一位线及第一互补位线耦合第一相邻存储阵列；所述第二读出电路结构通过第二位线耦合及第二互补位线耦合第二相邻存储阵列；
    所述第一读出电路结构中第二隔离模块、感测放大模块和偏移消除模块设置在第一区域中；在位线延伸方向上，所述第一读出电路结构中的第一隔离模块设置在所述第一区域两侧；所述第二读出电路结构中第二隔离模块、感测放大模块和偏移消除模块设置在第二区域中；在位线延伸方向上，所述第二读出电路结构中的第一隔离模块设置在所述第二区域两侧；
    其中，所述第一区域和所述第二区域在位线延伸方向上相邻设置。
  2. 根据权利要求1所述的读出电路的版图结构，其中，所述第二隔离模块包括：第一隔离MOS管和第二隔离MOS管；
    所述第一隔离MOS管源极或漏极的其中一者连接所述第一读出位线，另一者连接所述第二读出位线，栅极用于接收所述第二隔离信号；
    所述第二隔离MOS管源极或漏极的其中一者连接所述第一互补读出位线，另一者连接所述第二互补读出位线，栅极用于接收所述第二隔离信号。
  3. 根据权利要求1所述的读出电路的版图结构，其中，所述第一隔离模块包括：第三隔离MOS管和第四隔离MOS管；
    所述第三隔离MOS管源极或漏极的其中一者连接所述第一读出位线，另一者连接所述位线，栅极用于接收所述第一隔离信号；
    所述第四隔离MOS管源极或漏极的其中一者连接所述第一互补读出位线，另一者连接所述互补位线，栅极用于接收所述第一隔离信号。
  4. 根据权利要求1所述的读出电路的版图结构，其中，所述感测放大模块，包括：
    第一感测放大N管，栅极连接所述第一读出位线，源极或漏极的一者连接所述第二互补读出位线，另一者连接第二信号端，所述第二信号端用于提供第二电压；
    第二感测放大N管，栅极连接所述第一互补读出位线，源极或漏极的一者连接 所述第二读出位线，另一者连接所述第二信号端；
    第一感测放大P管，栅极连接所述第二读出位线，源极或漏极的一者连接所述第二互补读出位线，另一者连接第一信号端，所述第一信号端用于提供第一电压，所述第一电压大于所述第二电压；
    第二感测放大P管，栅极连接所述第二互补读出位线，源极或漏极的一者连接所述第二读出位线，另一者连接所述第一信号端。
  5. 根据权利要求1所述的读出电路的版图结构，还包括：
    预充电模块，用于根据预充电信号将所述位线、所述第一读出位线、所述第二读出位线、所述互补位线、所述第一互补读出位线和所述第二互补读出位线预充电至预设电压；
    均衡模块，用于根据均衡信号，保持所述第二读出位线的电压和所述第二互补读出位线的电压一致。
  6. 根据权利要求5所述的读出电路的版图结构，其中，所述预充电模块包括预充电MOS管，所述均衡模块包括均衡MOS管；
    所述预充电MOS管栅极用于接收所述预充电信号，源极或漏极的其中一者连接所述第二读出位线或所述第二互补读出位线，另一者用于接收所述预设电压；
    所述均衡MOS管栅极用于接收所述均衡信号，源极或漏极的其中一者连接所述第二读出位线，另一者连接所述第二互补读出位线。
  7. 根据权利要求1所述的读出电路的版图结构，还包括：
    第一预充电模块，连接所述位线或所述第一读出位线，用于根据预充电信号预充所述位线、所述第一读出位线和所述第二读出位线至预设电压；
    第二预充电模块，连接所述互补位线或所述第一互补读出位线，用于根据所述预充电信号预充所述互补位线、所述第一互补读出位线和所述第二互补读出位线至所述预设电压。
  8. 根据权利要求7所述的读出电路的版图结构，其中，所述第一预充电模块包括第一预充电MOS管，所述第二预充电模块包括第二预充电MOS管；
    所述第一预充电MOS管栅极用于接收所述预充电信号，源极或漏极的其中一者连接所述位线或所述第一读出位线，另一者用于接收所述预设电压；
    所述第二预充电MOS管栅极用于接收所述预充电信号，源极或漏极的其中一者连接所述互补位线或所述第一互补读出位线，另一者用于接收所述预设电压。
  9. 根据权利要求1所述的读出电路的版图结构，其中，所述偏移消除模块包括第一偏移消除MOS管和第二偏移消除MOS管；
    所述第一偏移消除MOS管栅极用于接收所述偏移消除信号，源极或者漏极的其中一者连接所述第二互补读出位线，另一者连接所述第一读出位线；
    所述第二偏移消除MOS管栅极用于接收所述偏移消除信号，源极或者漏极的其中一者连接所述第二读出位线，另一者连接所述第一互补读出位线。
  10. 根据权利要求3所述的读出电路的版图结构，包括：
    所述第一读出电路结构的第三隔离MOS管通过接触插塞与所述第一位线和第一读出位线连接，用于根据第一隔离信号，电连接所述第一位线和所述第一读出电路结构的所述第一读出位线；
    所述第一读出电路结构的第四隔离MOS管通过接触插塞与所述第一互补位线和第一互补读出位线连接，用于根据第一隔离信号，电连接所述第一读出电路结构的所述第一互补读出位线与所述第一互补位线；
    所述第二读出电路结构的第三隔离MOS管通过接触插塞与所述第二位线和第二读出位线连接，用于根据第一隔离信号，电连接所述第二位线和所述第二读出电路结构的所述第一读出位线；
    所述第二读出电路结构的第四隔离MOS管通过接触插塞与第二互补位线和所述第二互补读出位线连接，用于根据第一隔离信号，电连接所述第二读出电路结构的所述第一互补读出位线与所述第二互补位线。
  11. 根据权利要求10所述的读出电路的版图结构，包括：
    在位线延伸方向上，所述第一读出电路结构的第三隔离MOS管设置在所述第一区域远离所述第二区域的一侧；
    在字线延伸方向上，所述第二读出电路结构的第三隔离MOS管与所述第一读出电路结构的第三隔离MOS管相邻设置；
    在位线延伸方向上，所述第二读出电路结构的第四隔离MOS管设置在所述第二区域远离所述第一区域的一侧；
    在字线延伸方向上，所述第一读出电路结构的第四隔离MOS管于所述第二读出电路结构的第四隔离MOS管相邻设置。
  12. 根据权利要求10所述的读出电路的版图结构，包括：
    在位线延伸方向上，所述第一读出电路结构的第三隔离MOS管设置在所述第一区域远离所述第二区域的一侧；
    在位线延伸方向上，所述第一读出电路结构的第四隔离MOS管设置在所述第一区域靠近所述第二区域的一侧；
    在位线延伸方向上，所述第二读出电路结构的第三隔离MOS管设置在所述第二区域远离所述第一区域的一侧；
    在位线延伸方向上，所述第二读出电路结构的第四隔离MOS管设置在所述第二区域靠近所述第一区域的一侧。
  13. 根据权利要求12所述的读出电路的版图结构，其中，所述第一读出电路结构的第四隔离MOS管靠近所述第一区域设置，所述第二读出电路结构的第三隔离MOS管靠近所述第二区域设置。
  14. 根据权利要求12所述的读出电路的版图结构，其中，所述第一读出电路结构的第四隔离MOS管靠近所述第二区域设置，所述第二读出电路结构的第三隔离MOS管靠近所述第一区域设置。
  15. 根据权利要求4所述的读出电路的版图结构，包括：
    所述预充电模块包括第一预充电MOS管和第二预充电MOS管；
    所述第二隔离模块包括第一隔离MOS管和第二隔离MOS管；
    所述均衡模块包括均衡MOS管；
    所述偏移消除模块包括第一偏移消除MOS管和第二偏移消除MOS管；
    在位线延伸方向且靠近所述第二区域的方向上的所述第一区域中，依次设置所述第一读出电路结构的所述第一预充电MOS管、所述第一感测放大N管、所述第一偏移消除MOS管、所述第一隔离MOS管、所述第二感测放大P管、所述第一感测放大P管、所述第二隔离MOS管、所述第二偏移消除MOS管、所述第二预充电MOS管；
    在位线延伸方向且靠近所述第一区域的方向上的所述第二区域中，依次设置所述第二读出电路结构的所述第一预充电MOS管、所述第一感测放大N管、所述第一偏移消除MOS管、所述第一隔离MOS管、所述第二感测放大P管、所述第一感测放大P管、所述第二隔离MOS管、所述第二偏移消除MOS管、所述第二预充电MOS管。
  16. 一种数据读出方法，应用于权利要求1～15任一项所述的读出电路的版图结构，具有三个读出阶段，包括：
    在第一读出阶段，提供均衡信号、第一隔离信号、偏移消除信号，对位线、第一读出位线、第二读出位线、互补位线、第一互补读出位线和第二互补读出位线预充电至预设电压；
    在第二读出阶段开始阶段，维持预设时长的偏移消除信号，通过施加在感测放大模块两端的第一电压和第二电压，对所述感测放大模块进行偏移消除，同时存储阵列的字线打开，基于所述位线与所述存储阵列中存储单元内的电位进行电荷分享；
    在第二读出阶段执行过程中，提供所述第一隔离信号和第二隔离信号，存储数据由位线传输至第一读出位线，互补位线维持预设电压，第一读出位线的电位与第二读出位线的电位进行电荷分享；
    在第三读出阶段，维持第一隔离信号和第二隔离信号，通过施加在所述感测放大模块两端的所述第一电压和所述第二电压，感测放大模块根据第二读出位线和第二互补读出位线的电位感测放大存储数据，读出所述存储数据，并恢复所述存储单元内所述存储数据。
  17. 根据权利要求16所述的数据读出方法，其中，所述第二读出阶段包括依次执行的第一子阶段、第二子阶段、第三子阶段；
    在所述第一子阶段，向所述感测放大模块两端施加所述第一电压和所述第二电压，并提供读命令和所述偏移消除信号；
    在所述第二子阶段，将所述第一电压和所述第二电压恢复至预设电压；
    在所述第三子阶段，提供所述第一隔离信号和所述第二隔离信号。
  18. 根据权利要求17所述的数据读出方法，其中，在所述第二子阶段还包括：提供所述均衡信号。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241749A (zh) * 2006-12-22 2008-08-13 三星电子株式会社 半导体存储器设备的读出放大器电路及其操作方法
CN108257631A (zh) * 2016-12-28 2018-07-06 三星电子株式会社 具有偏移消除的读出放大器和存储器装置
CN111739566A (zh) * 2019-03-25 2020-10-02 爱思开海力士有限公司 具有位线感测放大器的存储器
US11024365B1 (en) * 2020-02-05 2021-06-01 Samsung Electronics Co., Ltd. Time interleaved sampling of sense amplifier circuits, memory devices and methods of operating memory devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241749A (zh) * 2006-12-22 2008-08-13 三星电子株式会社 半导体存储器设备的读出放大器电路及其操作方法
CN108257631A (zh) * 2016-12-28 2018-07-06 三星电子株式会社 具有偏移消除的读出放大器和存储器装置
CN111739566A (zh) * 2019-03-25 2020-10-02 爱思开海力士有限公司 具有位线感测放大器的存储器
US11024365B1 (en) * 2020-02-05 2021-06-01 Samsung Electronics Co., Ltd. Time interleaved sampling of sense amplifier circuits, memory devices and methods of operating memory devices

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