WO2023024608A1 - 感测放大结构和存储器架构 - Google Patents

感测放大结构和存储器架构 Download PDF

Info

Publication number
WO2023024608A1
WO2023024608A1 PCT/CN2022/094359 CN2022094359W WO2023024608A1 WO 2023024608 A1 WO2023024608 A1 WO 2023024608A1 CN 2022094359 W CN2022094359 W CN 2022094359W WO 2023024608 A1 WO2023024608 A1 WO 2023024608A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
signal
complementary
initial
isolation
Prior art date
Application number
PCT/CN2022/094359
Other languages
English (en)
French (fr)
Inventor
池性洙
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/812,032 priority Critical patent/US12033688B2/en
Publication of WO2023024608A1 publication Critical patent/WO2023024608A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Definitions

  • the present disclosure relates to, but is not limited to, a sense amplifier structure and memory architecture.
  • Dynamic Random Access Memory writes data through the charge in the cell capacitor; the cell capacitor is connected to the bit line and the complementary bit line.
  • DRAM Dynamic Random Access Memory
  • the output amplifier senses and amplifies the voltage difference between the bit line and the complementary bit line.
  • Semiconductor devices constituting a sense amplifier may have different device characteristics (eg, threshold voltage) due to process variations, temperature, and the like. Different device characteristics lead to offset noise in the sense amplifier, which reduces the effective read margin of the sense amplifier and degrades the performance of the DRAM.
  • device characteristics eg, threshold voltage
  • Different device characteristics lead to offset noise in the sense amplifier, which reduces the effective read margin of the sense amplifier and degrades the performance of the DRAM.
  • the bit line is electrically connected to the complementary read bit line
  • the complementary bit line is electrically connected to the read bit line
  • the voltage difference between the bit line and the complementary bit line is used to offset Offset noise
  • the voltage of the complementary bit line reduces the accuracy of DRAM readout and reduces the performance of DRAM.
  • the present disclosure provides a sense amplification structure and memory architecture.
  • a first aspect of the present disclosure provides a sense amplification structure disposed between adjacent memory arrays, comprising:
  • the first PMOS transistor the gate of which is connected to the second complementary readout bit line, and the source of which is connected to the first signal terminal;
  • the first NMOS transistor the gate of which is connected to the initial bit line, and the source of which is connected to the second signal terminal;
  • the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected to the first complementary read bit line, wherein the first signal terminal is used to receive the first level signal, and the second signal terminal is used to receive the second level signal Signal;
  • a second PMOS transistor the gate of which is connected to the second complementary readout bit line, and the source of which is connected to the first signal terminal;
  • the gate of the second NMOS transistor is connected to the initial complementary bit line, and its source is connected to the second signal terminal;
  • the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to the first complementary readout bit line, wherein the initial bit line is connected to the memory cells of a memory array in the adjacent memory array, and the initial complementary bit line is connected to the adjacent memory array. memory cells of another memory array in the array;
  • the offset elimination module is partly connected between the initial bit line and the first complementary readout bit line, and partly connected between the initial complementary bit line and the first readout bit line, and is used to make the The initial bit line is electrically connected to the first complementary read bit line, and the initial complementary bit line is electrically connected to the first read bit line;
  • the control module is connected to the second read bit line and the second complementary read bit line, and is used for providing bias voltage to the first PMOS transistor and the second PMOS transistor according to the control signal.
  • control signal is the same as the offset cancellation signal.
  • control signal includes a first control signal and a second control signal
  • control module includes:
  • a first control unit one end of which is connected to the second readout bit line, and the other end of which is used to receive the bias voltage, and is used to provide the bias to the first PMOS transistor according to the first control signal Voltage;
  • a second control unit one end of which is connected to the second complementary readout bit line, and the other end of which is used to receive the bias voltage, and is used to provide the bias voltage to the second PMOS transistor according to the second control signal. set the voltage.
  • the first control unit includes a first control MOS transistor
  • the second control unit includes a second control MOS transistor
  • the source of the first control MOS transistor is connected to the second read bit line, the gate is used to receive the first control signal, and the drain is used to receive the bias voltage;
  • the source of the second control MOS transistor is connected to the second complementary read bit line, the gate is used to receive the second control signal, and the drain is used to receive the bias voltage.
  • the sense amplification structure also includes:
  • a first isolation unit one end of which is connected to the first readout bit line, and the other end of which is connected to the second readout bit line, for connecting the first readout bit line to the second readout bit line according to a first isolation signal
  • Two sense bit lines are electrically connected;
  • a second isolation unit one end of which is connected to the first complementary readout bit line, and the other end of which is connected to the second complementary readout bit line, for making the first complementary readout bit line according to the first isolation signal line is electrically connected to the second complementary sense bit line.
  • the first isolation unit includes a first isolation MOS transistor
  • the second isolation unit includes a second isolation MOS transistor
  • the source of the first isolation MOS transistor is connected to the first readout bit line, the drain is connected to the second readout bit line, and the gate is used to receive the first isolation signal;
  • the source of the second isolation MOS transistor is connected to the first complementary readout bit line, the drain is connected to the second complementary readout bit line, and the gate is used to receive the first isolation signal.
  • the sense amplification structure further includes: a third isolation unit, one end of which is connected to the initial bit line, and the other end of which is connected to the first readout bit line, for making the initial bit line according to the second isolation signal a line electrically connected to the first readout bit line;
  • a fourth isolation unit one end of which is connected to the initial complementary bit line, and the other end of which is connected to the first complementary readout bit line, for making the initial complementary bit line and the first complementary bit line according to the second isolation signal Complementary read bit lines are electrically connected.
  • the third isolation unit includes a third isolation MOS transistor
  • the fourth isolation unit includes a fourth isolation MOS transistor
  • the source of the third isolation MOS transistor is connected to the initial bit line, the drain is connected to the first read bit line, and the gate is used to receive the second isolation signal;
  • the source of the fourth isolation MOS transistor is connected to the initial complementary bit line, the drain is connected to the first complementary readout bit line, and the gate is used to receive the second isolation signal.
  • the sense amplification structure further includes: an equalization unit, one end of which is connected to the first readout bit line, and the other end is connected to the first complementary readout bit line, for making the first readout bit line according to the equalization signal
  • a sense bit line has the same voltage as the first complementary sense bit line.
  • the equalization unit includes an equalization MOS transistor, the source of the equalization MOS transistor is connected to the first readout bit line, the drain is connected to the first complementary readout bitline, and the gate is used to receive the equalization Signal.
  • the offset elimination module includes:
  • the first offset canceling MOS transistor its source is connected to the initial bit line, its drain is connected to the first complementary readout bit line, and its gate is used to receive the offset canceling signal, for according to the The offset elimination signal electrically connects the initial bit line to the first complementary read bit line;
  • the second offset elimination MOS transistor its source is connected to the initial complementary bit line, its drain is connected to the first readout bit line, and its gate is used to receive the offset elimination signal, and is used to receive the offset elimination signal according to the An offset cancellation signal electrically connects the initial complementary bit line to the first sense bit line.
  • a second aspect of the present disclosure provides a memory architecture comprising:
  • a plurality of memory arrays are arranged in the extending direction of the initial bit line and the extending direction of the word line, and the extending direction of the initial bit line and the extending direction of the word line are perpendicular to each other;
  • the sense amplification structure according to any one of the first aspect, arranged between adjacent memory arrays in the extending direction of the initial bit line;
  • the sense amplifying structure connects the memory cells of one memory array in the adjacent memory array through the initial bit line, and connects the memory cell of another memory array in the adjacent memory array through the initial complementary bit line;
  • the control module is arranged between adjacent memory arrays in the extending direction of the word lines, and the control module is used for providing data readout signals, control signals and bias voltages to the sense amplifier structure.
  • the data readout signal includes at least one of an offset cancellation signal, a first isolation signal, a second isolation signal, and an equalization signal
  • the control module includes:
  • a signal control unit configured to provide the data readout signal and the control signal to the sense amplification structure
  • a bias control unit configured to provide the bias voltage to the sense amplification structure.
  • the signal control unit and the bias control unit are arranged on opposite sides of the sense amplification structure.
  • control signal is the same as the offset cancellation signal.
  • control module also includes:
  • a column selection control unit configured to provide a column selection signal for turning on part of the initial bit lines or the initial complementary bit lines in the memory array
  • the row selection control unit is used to provide a row selection signal, and the row selection signal is used to turn on some of the word lines in the memory array.
  • the control module when the control module is turned on based on the control signal, a bias voltage is provided to the gate of the first PMOS transistor and the gate of the second PMOS transistor, and the first PMOS transistor Based on the bias voltage conduction, the first signal terminal is electrically connected to the first complementary readout bit line, the first level signal is transmitted to the first complementary readout bit line, the second PMOS transistor is conducted based on the bias voltage, and the first The signal terminal is electrically connected to the first readout bit line, and the first level signal is transmitted to the first readout bit line, thereby realizing the offset elimination of the PMOS transistor; when the offset elimination module is turned on based on the offset elimination signal, the initial The bit line is electrically connected to the first complementary read bit line and shares a voltage, the initial complementary bit line is electrically connected to the first read bit line and shares a voltage, and the voltage of the initial bit line is used as the gate voltage of the first NMOS transistor to conduct The first NMOS transistor, the second signal
  • FIG. 1 is a schematic diagram of a circuit structure of a sense amplifier structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural layout diagram of a memory architecture provided by another embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a memory architecture provided by another embodiment of the present disclosure.
  • the bit line is electrically connected to the complementary read bit line
  • the complementary bit line is electrically connected to the read bit line
  • the offset noise is offset by the voltage difference between the bit line and the complementary bit line.
  • the gates of the PMOS transistors in the sense amplifier circuit are respectively connected to the read bit line and the complementary read bit line, it is easy to cause voltage fluctuations of the read bit line and the complementary read bit line, thereby affecting the voltage of the bit line and the complementary bit line. Therefore, how to stably eliminate the offset noise in the sense amplifier circuit while avoiding voltage fluctuations on the bit line and the complementary bit line is an urgent problem to be solved. question.
  • An embodiment of the present disclosure provides a sense amplification structure, which is arranged between adjacent memory arrays, and includes: a first PMOS transistor, the gate of which is connected to the second complementary readout bit line, and the source of which is connected to the first signal terminal ; the first NMOS transistor, the gate of which is connected to the initial bit line, and its source is connected to the second signal terminal; the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected to the first complementary readout bit line, wherein the first One signal terminal is used to receive the first level signal, and the second signal terminal is used to receive the second level signal; the gate of the second PMOS transistor is connected to the second complementary readout bit line, and its source is connected to the first signal terminal ; the second NMOS transistor, its gate is connected to the initial complementary bit line, and its source is connected to the second signal terminal; the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to the first complementary readout bit line, wherein, The initial bit line is connected to the storage
  • FIG. 1 is a schematic diagram of the circuit structure of the sense amplifier structure provided by this embodiment.
  • the sense amplifier structure provided by each embodiment of the present disclosure will be further described in detail below in conjunction with the accompanying drawings, specifically as follows:
  • the sense amplification structure is arranged between adjacent memory arrays 400, including:
  • the gate of the first PMOS transistor ⁇ P1> is connected to the second readout bit line ISABL, and the source is connected to the first signal terminal; wherein, the first signal terminal is used to receive a first level signal (Positive Cell Storing Signal, PCS).
  • PCS Personal Cell Storing Signal
  • the gate of the first NMOS transistor ⁇ N1> is connected to the initial bit line BL, and the source is connected to the second signal terminal, wherein the second signal terminal is used to receive the second level signal (Negative Cell Storing Signal, NCS).
  • NCS Native Cell Storing Signal
  • the drains of the first PMOS transistor ⁇ P1> and the first NMOS transistor ⁇ N1> are connected to the first complementary read bit line SABLB.
  • the voltage of the first level signal PCS is greater than the voltage of the second level signal NCS, that is, the first level signal PCS is a high level corresponding to logic "1", and the second level signal NCS is a corresponding Low level of logic "0".
  • the gate of the second PMOS transistor ⁇ P2> is connected to the second complementary readout bit line ISABLB, and the source is connected to the first signal terminal.
  • the gate of the second NMOS transistor ⁇ N2> is connected to the initial complementary bit line BLB, and the source is connected to the second signal terminal.
  • the drain of the second PMOS transistor ⁇ P2> and the drain of the second NMOS transistor ⁇ N2> are connected to the first read bit line SABL.
  • the initial bit line BL is connected to the memory cells of a memory array 400 in the adjacent memory array 400, and the initial complementary bit line is connected to the memory cells of another memory array 400 in the adjacent memory array 400 .
  • the initial bit line BL is connected to the first storage unit through the first switch ⁇ 01>, and the initial complementary bit line BLB is connected to the second storage unit through the second switch ⁇ 02>.
  • the gate of the first switch tube ⁇ 01> is connected to the word line WL
  • the source is connected to the initial bit line BL
  • the drain is connected to the first memory cell
  • the second switch The gate of the transistor ⁇ 02> is connected to the word line WL
  • the source is connected to the initial complementary BLB
  • the drain is connected to the second storage unit.
  • the word line WL is used for turning on based on the row selection signal, when the word line WL is turned on, the switch connected to the word line WL is turned on, and the charge of the memory cells is shared to the initial bit line BL or the initial complementary bit line BLB , the initial bit line BL or the initial complementary bit line BLB is turned on based on the column selection signal, and when the initial bit line BL or the initial complementary bit line BLB is turned on, the memory reads out data.
  • the offset elimination module is partially connected between the initial bit line BL and the first complementary read bit line SABLB, and partially connected between the initial complementary bit line BLB and the first read bit line SABL, and is used to eliminate the signal according to the offset (Offset Canceling Signal, OC), electrically connecting the initial bit line BL to the first complementary read bit line SABLB, and electrically connecting the initial complementary bit line BLB to the first read bit line SABL.
  • offset Offset Canceling Signal, OC
  • the control module 100 is connected to the second read bit line ISABL and the second read bit line ISABLB, and is used for providing a bias voltage VBIAS to the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P2> according to the control signal.
  • the bias voltage VBIAS is provided to the gate of the first PMOS transistor ⁇ P1> and the gate of the second PMOS transistor ⁇ P2>, and the first PMOS transistor ⁇ P1> is based on the bias voltage VBIAS is turned on, the first signal terminal is electrically connected to the first complementary read bit line SABLB, the first level signal PCS is transmitted to the first complementary read bit line SABLB, and the second PMOS transistor ⁇ P2> conducts based on the bias voltage VBIAS connected, the first signal terminal is electrically connected to the first read bit line SABL, and the first level signal PCS is transmitted to the first read bit line SABL, thereby realizing offset elimination of the PMOS transistor; when the offset elimination module is based on the offset After the cancellation signal OC is turned on, the initial bit line BL is electrically connected to the first complementary read bit line SABLB and shares a voltage, the initial complementary bit line BLB is electrically connected to the first read bit line SABL and shares a voltage, the initial complementary bit line BLB is electrically connected
  • the control module includes: a first control unit 101, one end of which is connected to the second readout bit line ISABL, and the other end is used to receive a bias voltage VBIAS, which is used to send a signal to the first PMOS transistor according to the control signal.
  • ⁇ P1> provides the bias voltage VBIAS.
  • the second control unit 102 has one end connected to the second complementary read bit line ISABLB, and the other end is used to receive the bias voltage VBIAS, and is used to provide the bias voltage VBIAS to the second PMOS transistor ⁇ P2> according to the control signal.
  • control signal is the same as the offset cancellation signal OC, that is, the control module 100 is turned on according to the offset cancellation signal OC.
  • the control module 100 and the offset elimination module are synchronized, so as to realize the offset elimination of the sense amplifier circuit, as shown in FIG. 1 .
  • the control signal includes a first control signal and a second control signal, wherein the first control unit 101 is turned on based on the first control signal, and the second control unit 102 is turned on based on the second control signal. That is, the first control unit 101 provides the bias voltage VBIAS to the first PMOS transistor ⁇ P1> through the first control signal; the second control unit 102 provides the bias voltage VBIAS to the second PMOS transistor ⁇ P2> through the second control signal; The separate control of the first control unit and the second control unit by different control signals further realizes precise control of the control module 100 .
  • the first control unit 101 includes a first control MOS transistor ⁇ 11>, the source of the first control MOS transistor ⁇ 11> is connected to the second readout bit line ISABL, and the gate is used to receive the first control signal , the drain is used to receive the bias voltage VBIAS;
  • the second control unit 102 includes a second control MOS transistor ⁇ 12>, the source of the second control MOS transistor ⁇ 12> is connected to the second complementary readout bit line ISABLB, and the gate is used for For receiving the second control signal, the drain is used for receiving the bias voltage VBIAS.
  • control module can also provide the bias voltage VBIAS to the first PMOS transistor ⁇ P1> and the second PMOS transistor ⁇ P2> simultaneously through the same control unit.
  • the bias voltage VBIAS is provided by the same control unit to reduce the layout area of the sense amplifier circuit structure, which is beneficial to improve the integration level of the memory.
  • the offset elimination module includes: the first offset elimination MOS transistor ⁇ 31>, the source is connected to the initial bit line BL, the drain is connected to the first complementary read bit line SABLB, and the gate is used For receiving the offset elimination signal OC, it is used to electrically connect the initial bit line BL to the first complementary readout bit line SABLB according to the offset elimination signal OC; the second offset elimination MOS transistor ⁇ 32>, the source is connected to the initial complementary bit The drain of the line BLB is connected to the first read bit line SABL, and the gate is used to receive the offset cancel signal OC, and is used to electrically connect the initial complementary bit line BLB to the first read bit line SABL according to the offset cancel signal OC.
  • the sense amplification structure further includes: a first isolation unit 201, one end of which is connected to the first readout bit line SABL, and the other end is connected to the second readout bit line Signal 1, ISO1) electrically connects the first read bit line SABL to the second read bit line ISABL; the second isolation unit 202, one end is connected to the first complementary read bit line SABLB, and the other end is connected to the second complementary read bit
  • the line ISABLB is used to electrically connect the first complementary read bit line SABLB to the second complementary read bit line ISABLB according to a first isolation signal (Isolation Signal 1, ISO1).
  • the first isolation unit 201 includes a first isolation MOS transistor ⁇ 21>, the source of the first isolation MOS transistor ⁇ 21> is connected to the first read bit line SABL, and the drain is connected to the second read bit line ISABL, the gate is used to receive the first isolation signal ISO1;
  • the second isolation unit 202 includes a second isolation MOS transistor ⁇ 22>, the source of the second isolation MOS transistor ⁇ 22> is connected to the first complementary readout bit line SABLB, and the drain The pole is connected to the second complementary readout bit line ISABLB, and the gate is used to receive the first isolation signal ISO1.
  • the sense amplifier circuit provides the first isolation signal ISO1 in the precharging stage to precharge the second readout bit line ISABL and the second complementary readout bitline ISABLB, and provides the first isolation signal ISO1 in the sense amplifier stage,
  • the gate of the first PMOS transistor ⁇ P1> is connected to the first read bit line SABL, and the gate of the first PMOS transistor ⁇ P1> is connected to the first complementary read bit line SABLB.
  • the first signal terminal when the second PMOS transistor ⁇ P2> is turned on, the first signal terminal is connected to the first read bit line SABL, thereby pulling the first read bit line SABL up to the first level signal PCS , and then pull up the initial bit line BL to the first level signal PCS, so that the data read by the memory through the initial bit line BL is the high level of the logic "1" corresponding to the first level signal PCS;
  • the first NMOS After the tube ⁇ N1> when the first NMOS After the tube ⁇ N1> is turned on, the second signal end is connected to the first complementary read bit line SABLB, thereby pulling the first complementary read bit line SABLB down to the second level signal NCS, and then the initial complementary bit line BLB Pull down to the second level signal NCS, so that the data read by the memory through the initial complementary bit line BLB is the low level of the second level signal NCS corresponding to logic "0";
  • the first PMOS transistor ⁇ P1> when the first PMOS transistor ⁇ P1
  • Level signal PCS so that the data read by the memory through the initial complementary bit line BLB is the high level of logic "1" corresponding to the first level signal PCS; when the second NMOS transistor ⁇ N2> is turned on, the second signal terminal It is connected with the first read bit line SABL, so that the first read bit line SABL is pulled down to the second level signal NCS, and then the initial bit line BL is pulled down to the second level signal NCS, so that the memory passes the initial The data read from the bit line BL is the low level of the second level signal NCS corresponding to logic "0".
  • the sense amplification structure further includes: a third isolation unit 203, one end of which is connected to the initial bit line BL, and the other end is connected to the first readout bit line SABL, which is used for according to the second isolation signal (Isolation Signal 2, ISO2)
  • the initial bit line BL is electrically connected to the first read bit line SABL
  • the fourth isolation unit 204 one end is connected to the initial complementary bit line BLB, and the other end is connected to the first complementary read bit line SABLB, which is used for isolation according to the second
  • the signal (Isolation Signal 2, ISO2) electrically connects the initial complementary bit line BLB to the first complementary sense bit line SABLB.
  • the third isolation unit 203 includes a third isolation MOS transistor ⁇ 23>, the source of the third isolation MOS transistor ⁇ 23> is connected to the initial bit line BL, the drain is connected to the first read bit line SABL, and the gate is used to receive the second Isolation Signal 2 (ISO2).
  • the fourth isolation unit 204 includes a fourth isolation MOS transistor ⁇ 24>, the source of the fourth isolation MOS transistor ⁇ 24> is connected to the initial complementary bit line BLB, the drain is connected to the first complementary read bit line SABLB, and the gate is used to receive The second isolation signal (Isolation Signal 2, ISO2).
  • the sense amplifier circuit provides the second isolation signal ISO2 during the offset elimination stage and the amplification stage to realize charge sharing between the initial bit line BL and the first read bit line SABL, the initial complementary bit line BLB and the first complementary bit line SABLB .
  • the sense amplification structure further includes: an equalization unit 401, one end of which is connected to the first readout bit line SABL, and the other end is connected to the first complementary readout bit line SABLB, which is used for equalizing signals (Equalizing Signal, EQ ), so that the voltage of the first sense bit line SABL is the same as the voltage of the first complementary sense bit line SABLB.
  • an equalization unit 401 one end of which is connected to the first readout bit line SABL, and the other end is connected to the first complementary readout bit line SABLB, which is used for equalizing signals (Equalizing Signal, EQ ), so that the voltage of the first sense bit line SABL is the same as the voltage of the first complementary sense bit line SABLB.
  • the equalization unit 401 includes an equalization MOS transistor ⁇ 41>, its source is connected to the first read bit line SABL, its drain is connected to the first complementary read bit line SABLB, and its gate is used to receive the equalization signal EQ.
  • the control module When the control module is turned on based on the control signal, a bias voltage is provided to the gate of the first PMOS transistor and the gate of the second PMOS transistor, the first PMOS transistor is turned on based on the bias voltage, and the first signal terminal is complementary to the first
  • the read bit line is electrically connected, the first level signal is transmitted to the first complementary read bit line, the second PMOS transistor is turned on based on the bias voltage, the first signal terminal is electrically connected to the first read bit line, and the first electrical The flat signal is transmitted to the first read bit line, thereby realizing the offset elimination of the PMOS transistor;
  • the offset elimination module when the offset elimination module is turned on based on the offset elimination signal, the initial bit line is electrically connected to the first complementary read bit line and shares a voltage , the initial complementary bit line is electrically connected to the first readout bit line and shares a voltage, the voltage of the initial bit line is used as the gate voltage of the first NMOS transistor to turn on the first NMOS transistor, and the second signal terminal is connected
  • Another embodiment of the present disclosure provides a memory architecture, including: a plurality of memory arrays arranged in the extending direction of the initial bit line and the extending direction of the word line, and the extending direction of the initial bit line and the extending direction of the word line are perpendicular to each other; the above embodiment provides The sense amplification structure of the initial bit line is arranged between adjacent memory arrays in the extending direction of the initial bit line; wherein, the sense amplification structure is connected to the memory cells of a memory array in the adjacent memory array through the initial bit line, and the initial complementary bit The memory cells of another memory array in the adjacent memory array are connected by wires; the control module is arranged between the adjacent memory arrays in the word line extension direction, and the control module is used to provide data readout signals and control to the sense amplifier structure. signal and bias voltages.
  • FIG. 2 is a schematic diagram of the structural layout of the memory architecture provided by this embodiment
  • FIG. 3 is a schematic diagram of the specific structure of the memory architecture provided by this embodiment.
  • the memory architecture includes:
  • a plurality of memory arrays 400 are arranged in the extending direction of the initial bit line BL and the extending direction of the word line WL.
  • the extending direction of the initial bit line BL is perpendicular to the extending direction of the word line WL. In this embodiment, referring to FIG. 3 , the extending direction of the initial bit line BL is vertical, and the extending direction of the word line WL is horizontal.
  • the sense amplifier structure 402 provided in the above-mentioned embodiment is arranged between adjacent memory arrays 400 in the extending direction of the initial bit line BL, wherein the sense amplifier structure 402 is connected to the adjacent memory arrays through the initial bit line BL.
  • the memory cells of one memory array 400 are connected to the memory cells of another memory array 400 in the adjacent memory array 400 through the initial complementary bit line BLB.
  • the control module 100 is disposed between adjacent memory arrays 400 in the extending direction of the word line WL, and the control module 100 is used for providing data readout signals, control signals and bias voltages to the sense amplifier structure.
  • control signal is used to turn on the first control MOS transistor ⁇ 11> and the second control MOS transistor ⁇ 12>;
  • the bias voltage VBIAS is used to conduct the first control MOS transistor ⁇ 11> and the second control MOS transistor ⁇ 12>
  • the gate turn-on voltage is provided to the PMOS transistor of the sense amplifier circuit.
  • the data readout signal includes at least one of an offset cancellation signal OC, a first isolation signal ISO1 , a second isolation signal ISO2 , and an equalization signal EQ.
  • the first isolation signal ISO1 is used to turn on the first isolation MOS transistor ⁇ 21> and the second isolation MOS transistor ⁇ 22>;
  • the second isolation signal ISO2 is used to turn on the third isolation MOS transistor ⁇ 23> and the fourth isolation MOS transistor ⁇ 24>;
  • the offset elimination signal OC is used to turn on the first offset elimination MOS transistor ⁇ 31> and the second offset elimination MOS transistor ⁇ 32>;
  • the equalization signal EQ is used to turn on the equalization MOS transistor ⁇ 11> .
  • control signal is the same as the offset cancellation signal OC, that is, the control module 100 is turned on according to the offset cancellation signal OC.
  • the control module 100 includes: a signal control unit 413 for providing a readout signal and a control signal to the sense amplifier structure; a bias control unit 414 for providing the sense amplifier structure structure provides the bias voltage.
  • the signal control unit 413 and the bias control unit 414 are disposed on opposite sides of the sense amplifier structure 402 .
  • the control module 100 further includes: a column selection control unit 412, configured to provide a column selection signal, and the column selection signal is used to turn on part of the initial bit line BL or the initial complementary bit line BLB in the memory array 400;
  • the selection control unit 411 is used to provide a row selection signal, and the row selection signal is used to turn on part of the word lines WL in the memory array 400; that is, the column selection control unit 412 is used to select the corresponding bit line BL according to the column selection signal so as to select the corresponding memory cell , the row selection control unit 411 is used for selecting the corresponding word line WL according to the row selection signal so as to select the corresponding memory cell.
  • a bias voltage is provided to the gate of the first PMOS transistor and the gate of the second PMOS transistor, and the first PMOS The transistor is turned on based on the bias voltage, the first signal terminal is electrically connected to the first complementary read bit line, the first level signal is transmitted to the first complementary read bit line, the second PMOS transistor is turned on based on the bias voltage, and the second PMOS transistor is turned on based on the bias voltage.
  • a signal terminal is electrically connected to the first readout bit line, and the first level signal is transmitted to the first readout bit line, thereby realizing the offset elimination of the PMOS transistor; when the offset elimination module is turned on based on the offset elimination signal,
  • the initial bit line is electrically connected to the first complementary read bit line and shares a voltage
  • the initial complementary bit line is electrically connected to the first read bit line and shares a voltage
  • the voltage of the initial bit line is used as the gate voltage of the first NMOS transistor to conduct
  • the second signal terminal is electrically connected to the first complementary read bit line, the second level signal is transmitted to the first complementary read bit line, and the voltage of the initial complementary bit line is used as the gate of the second NMOS transistor voltage to turn on the second NMOS transistor
  • the second signal terminal is electrically connected to the first readout bit line, and the second level signal is transmitted to the first readout bit line, thereby realizing the offset elimination of the NMOS transistor; since the first PMOS The transistor and the second PMOS transistor are turned on

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

本公开提供一种感测放大结构和存储器架构，包括：第一PMOS管，栅极连接第二互补读出位线，源极连接第一信号端；第一NMOS管，栅极连接初始位线；第一PMOS管的漏极和第一NMOS管的漏极连接第一互补读出位线；第二PMOS管，栅极连接第二互补读出位线；第二NMOS管，栅极连接初始互补位线，源极连接第二信号端；第二PMOS管的漏极和第二NMOS管的漏极连接第一互补读出位线；偏移消除模块，连接初始位线和第一互补读出位线，且连接初始互补位线和第一读出位线；控制模块，连接第二读出位线和第二互补读出位线，用于根据控制信号，向第一PMOS管和第二PMOS管提供偏置电压。

Description

感测放大结构和存储器架构
本公开基于申请号为202110998262.1、申请日为2021年08月27日、申请名称为“感测放大结构和存储器架构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种感测放大结构和存储器架构。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)通过单元电容中的电荷来写入数据；单元电容连接至位线和互补位线，在DRAM中，当执行读取操作或刷新操作时，读出放大器读出并放大位线和互补位线之间的电压差。
构成读出放大器的半导体器件可能由于工艺变化、温度等因素的影响从而具有不同的器件特性(例如，阈值电压)。不同的器件特性会导致读出放大器中的产生偏移噪声，而偏移噪声会降低读出放大器的有效读出裕度，并且会降低DRAM的性能。
申请人发现，目前对DRAM的偏移噪声的消除过程中，位线和互补读出位线电连接，互补位线和读出位线电连接，通过位线和互补位线的电压差来抵消偏移噪声，然而由于感测放大电路中PMOS管的栅极分别连接读出位线和互补读出位线，容易造成读出位线和互补读出位线的电压波动，从而影响位线和互补位线的电压，降低DRAM读出的准确性，并且降低DRAM的性能。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种感测放大结构和存储器架构。
本公开的第一方面提供了一种感测放大结构，设置在相邻存储阵列之间，包括：
第一PMOS管，其栅极连接第二互补读出位线，其源极连接第一信号端；
第一NMOS管，其栅极连接初始位线，其源极连接第二信号端；
第一PMOS管的漏极和第一NMOS管的漏极连接第一互补读出位线，其中，第一信号端用于接收第一电平信号，第二信号端用于接收第二电平信号；
第二PMOS管，其栅极连接第二互补读出位线，其源极连接第一信号端；
第二NMOS管，其栅极连接初始互补位线，其源极连接第二信号端；
第二PMOS管的漏极和第二NMOS管的漏极连接第一互补读出位线，其中，初始位线连接相邻存储阵列中一存储阵列的存储单元，初始互补位线连接相邻存储阵列中另一存储阵列的存储单元；
偏移消除模块，部分连接在初始位线与第一互补读出位线之间，部分连接在初始互补位线和第一读出位线之间，用于根据偏移消除信号，使所处初始位线与第一互补读出位线电连接，并使初始互补位线与第一读出位线电连接；
控制模块，连接第二读出位线和第二互补读出位线，用于根据控制信号，向第一PMOS管和第二PMOS管提供偏置电压。
其中，所述控制信号与所述偏移消除信号相同。
其中，所述控制信号包括第一控制信号和第二控制信号，所述控制模块包括：
第一控制单元，其一端连接所述第二读出位线，其另一端用于接收所述偏置电压， 用于根据所述第一控制信号向所述第一PMOS管提供所述偏置电压；
第二控制单元，其一端连接所述第二互补读出位线，其另一端用于接收所述偏置电压，用于根据所述第二控制信号向所述第二PMOS管提供所述偏置电压。
其中，所述第一控制单元包括第一控制MOS管，所述第二控制单元包括第二控制MOS管；
所述第一控制MOS管的源极连接所述第二读出位线，栅极用于接收所述第一控制信号，漏极用于接收所述偏置电压；
所述第二控制MOS管的源极连接所述第二互补读出位线，栅极用于接收所述第二控制信号，漏极用于接收所述偏置电压。
其中，所述感测放大结构还包括：
第一隔离单元，其一端连接所述第一读出位线，其另一端连接所述第二读出位线，用于根据第一隔离信号使所述第一读出位线与所述第二读出位线电连接；
第二隔离单元，其一端连接所述第一互补读出位线，其另一端连接所述第二互补读出位线，用于根据所述第一隔离信号使所述第一互补读出位线与所述第二互补读出位线电连接。
其中，所述第一隔离单元包括第一隔离MOS管，所述第二隔离单元包括第二隔离MOS管；
所述第一隔离MOS管的源极连接所述第一读出位线，漏极连接所述第二读出位线，栅极用于接收所述第一隔离信号；
所述第二隔离MOS管的源极连接所述第一互补读出位线，漏极连接所述第二互补读出位线，栅极用于接收所述第一隔离信号。
其中，所述感测放大结构还包括：第三隔离单元，其一端连接所述初始位线，其另一端连接所述第一读出位线，用于根据第二隔离信号使所述初始位线与所述第一读出位线电连接；
第四隔离单元，其一端连接所述初始互补位线，其另一端连接所述第一互补读出位线，用于根据所述第二隔离信号使所述初始互补位线与所述第一互补读出位线电连接。
其中，所述第三隔离单元包括第三隔离MOS管，所述第四隔离单元包括第四隔离MOS管，
所述第三隔离MOS管的源极连接所述初始位线，漏极连接所述第一读出位线，栅极用于接收所述第二隔离信号；
所述第四隔离MOS管的源极连接所述初始互补位线，漏极连接所述第一互补读出位线，栅极用于接收所述第二隔离信号。
其中，所述感测放大结构还包括：均衡单元，其一端连接所述第一读出位线，其另一端连接所述第一互补读出位线，用于根据均衡信号，使所述第一读出位线的电压与所述第一互补读出位线的电压相同。
其中，所述均衡单元包括均衡MOS管，所述均衡MOS管的源极连接所述第一读出位线，漏极连接所述第一互补读出位线，栅极用于接收所述均衡信号。
其中，所述偏移消除模块，包括：
第一偏移消除MOS管，其源极连接所述初始位线，其漏极连接所述第一互补读出位线，其栅极用于接收所述偏移消除信号，用于根据所述偏移消除信号使所处初始位线与所述第一互补读出位线电连接；
第二偏移消除MOS管，其源极连接所述初始互补位线，其漏极连接所述第一读出位线，其栅极用于接收所述偏移消除信号，用于根据所述偏移消除信号使所述初始互补位线与所述第一读出位线电连接。
本公开的第二方面提供了一种存储器架构，包括：
多个存储阵列，在初始位线延伸方向和字线延伸方向排列，初始位线延伸方向和字线延伸方向相垂直；
如第一方面任一所述的感测放大结构，在初始位线延伸方向上，设置在相邻存储阵列之间；
其中，感测放大结构通过初始位线连接相邻存储阵列中一存储阵列的存储单元，通过初始互补位线连接相邻存储阵列中另一存储阵列的存储单元；
控制模块，在字线延伸方向上，设置在相邻存储阵列之间，控制模块用于向感测放大结构提供数据读出信号、控制信号和偏置电压。
其中，所述数据读出信号包括偏移消除信号、第一隔离信号、第二隔离信号、均衡信号的至少一者，所述控制模块包括：
信号控制单元，用于向所述感测放大结构提供所述数据读出信号和所述控制信号；
偏压控制单元，用于向所述感测放大结构提供所述偏置电压。
其中，所述信号控制单元和所述偏压控制单元设置在所述感测放大结构的相对两侧。
其中，所述控制信号和所述偏移消除信号相同。
其中，所述控制模块，还包括：
列选控制单元，用于提供列选择信号，所述列选择信号用于导通所述存储阵列中的部分所述初始位线或所述初始互补位线；
行选控制单元，用于提供行选择信号，所述行选择信号用于导通所述存储阵列中的部分所述字线。
本公开实施例所提供感测放大结构和存储器架构中，当控制模块基于控制信号导通时，向第一PMOS管的栅极和第二PMOS管的栅极提供偏置电压，第一PMOS管基于偏置电压导通，第一信号端与第一互补读出位线电连接，第一电平信号传输至第一互补读出位线，第二PMOS管基于偏置电压导通，第一信号端与第一读出位线电连接，第一电平信号传输至第一读出位线，从而实现PMOS管的偏移消除；当偏移消除模块基于偏移消除信号导通后，初始位线与第一互补读出位线电连接并共享电压，初始互补位线与第一读出位线电连接并共享电压，初始位线的电压作为第一NMOS管的栅极电压以导通第一NMOS管，第二信号端与第一互补读出位线电连接，第二电平信号传输至第一互补读出位线，初始互补位线的电压作为第二NMOS管的栅极电压以导通第二NMOS管，第二信号端与第一读出位线电连接，第二电平信号传输至第一读出位线，从而实现NMOS管的偏移消除；由于第一PMOS管和第二PMOS管基于稳定的偏置电压导通，即保持第一读出位线和第一互补读出位线的电压稳定，进一步稳定初始位线和初始互补位线的电压，以避免位线和互补位线上的电压波动，稳定地消除感测放大电路中的偏移噪声。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的感测放大结构的电路结构示意图；
图2为本公开另一实施例提供的存储器架构的结构布局示意图；
图3为本公开另一实施例提供的存储器架构的具体结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
目前对DRAM的偏移噪声的消除过程中，位线和互补读出位线电连接，互补位线和读出位线电连接，通过位线和互补位线的电压差来抵消偏移噪声，然而由于感测放大电路中PMOS管的栅极分别连接读出位线和互补读出位线，容易造成读出位线和互补读出位线的电压波动，从而影响位线和互补位线的电压，降低DRAM读出的准确性，并且降低DRAM的性能，因此，如何稳定地消除感测放大电路中的偏移噪声，同时避免位线和互补位线上的电压波动，是当下亟待解决的问题。
本公开一实施例提供了一种感测放大结构，设置在相邻存储阵列之间，包括：第一PMOS管，其栅极连接第二互补读出位线，其源极连接第一信号端；第一NMOS管，其栅极连接初始位线，其源极连接第二信号端；第一PMOS管的漏极和第一NMOS管的漏极连接第一互补读出位线，其中，第一信号端用于接收第一电平信号，第二信号端用于接收第二电平信号；第二PMOS管，其栅极连接第二互补读出位线，其源极连接第一信号端；第二NMOS管，其栅极连接初始互补位线，其源极连接第二信号端；第二PMOS管的漏极和第二NMOS管的漏极连接第一互补读出位线，其中，初始位线连接相邻存储阵列中一存储阵列的存储单元，初始互补位线连接相邻存储阵列中另一存储阵列的存储单元；偏移消除模块，部分连接在初始位线与第一互补读出位线之间，部分连接在初始互补位线和第一读出位线之间，用于根据偏移消除信号，使所处初始位线与第一互补读出位线电连接，并使初始互补位线与第一读出位线电连接；控制模块，连接第二读出位线和第二互补读出位线，用于根据控制信号，向第一PMOS管和第二PMOS管提供偏置电压。
图1为本实施例提供的感测放大结构的电路结构示意图，以下结合附图对本公开各实施例提供的感测放大结构作进一步详细说明，具体如下：
参考图1，感测放大结构，设置在相邻存储阵列400之间，包括：
第一PMOS管<P1>，栅极连接第二读出位线ISABL，源极连接第一信号端；其中，第一信号端用于接收第一电平信号(Positive Cell Storing Signal，PCS)。
第一NMOS管<N1>，栅极连接初始位线BL，源极连接第二信号端，其中，第二信号端用于接收第二电平信号Negative Cell Storing Signal，NCS)。
第一PMOS管<P1>的漏极和第一NMOS管<N1>的漏极连接第一互补读出位线SABLB。
在本实施例中，第一电平信号PCS的电压大于第二电平信号NCS的电压，即第一电平信号PCS为对应逻辑“1”的高电平，第二电平信号NCS为对应逻辑“0”的低电平。
第二PMOS管<P2>，栅极连接第二互补读出位线ISABLB，源极连接第一信号端。
第二NMOS管<N2>，栅极连接初始互补位线BLB，源极连接第二信号端。
第二PMOS管<P2>的漏极和第二NMOS管<N2>的漏极连接第一读出位线SABL。
对于初始位线BL和初始互补位线BLB，初始位线BL连接相邻存储阵列400中一存储阵列400的存储单元，初始互补位线连接相邻存储阵列400中另一存储阵列400的存储单元。
在本实施例中，参考图1，初始位线BL通过第一开关管<01>连接第一存储单元，初始互补位线BLB通过第二开关管<02>连接第二存储单元。
对于第一开关管<01>和第二开关管<02>，第一开关管<01>栅极连接字线WL，源极连接初始位线BL，漏极连接第一存储单元，第二开关管<02>栅极连接字线WL，源极连接初始互补BLB，漏极连接第二存储单元。
其中，字线WL用于基于行选择信号导通，字线WL导通时，字线WL所连接的开关管导通，将存储单元的电荷共享至初始位线BL或初始互补位线BLB上，初始位线BL或初始互补位线BLB基于列选择信号导通，初始位线BL或初始互补位线BLB导通时，存储器将数据读出。
偏移消除模块，部分连接在初始位线BL和第一互补读出位线SABLB之间，部分连接在初始互补位线BLB和第一读出位线SABL之间，用于根据偏移消除信号(Offset Cancelling Signal，OC)，使初始位线BL与第一互补读出位线SABLB电连接，并使初始互补位线BLB与第一读出位线SABL电连接。
控制模块100，连接第二读出位线ISABL和第二读出位线ISABLB，用于根据控制信号，向第一PMOS管<P1>和第二PMOS管<P2>提供偏置电压VBIAS。
当控制模块100基于控制信号导通时，向第一PMOS管<P1>的栅极和第二PMOS管<P2>的栅极提供偏置电压VBIAS，第一PMOS管<P1>基于偏置电压VBIAS导通，第一信号端与第一互补读出位线SABLB电连接，第一电平信号PCS传输至第一互补读出位线SABLB，第二PMOS管<P2>基于偏置电压VBIAS导通，第一信号端与第一读出位线SABL电连接，第一电平信号PCS传输至第一读出位线SABL，从而实现PMOS管的偏移消除；当偏移消除模块基于偏移消除信号OC导通后，初始位线BL与第一互补读出位线SABLB电连接并共享电压，初始互补位线BLB与第一读出位线SABL电连接并共享电压，初始位线BL的电压作为第一NMOS管<N1>的栅极电压以导通第一NMOS管<N1>，第二信号端与第一互补读出位线SABLB电连接，第二电平信号NCS传输至第一互补读出位线SABLB，初始互补位线BL的电压作为第二NMOS管<N2>的栅极电压以导通第二NMOS管<N2>，第二信号端与第一读出位线SABL电连接，第二电平信号NCS传输至第一读出位线SABL，从而实现NMOS管的偏移消除；由于第一PMOS管<P1>和第二PMOS管<P2>基于稳定的偏置电压VBIAS导通，即保持第一读出位线SABL和第一互补读出位线SABLB的电压稳定，进一步稳定初始位线BL和初始互补位线BLB的电压，以避免位线和互补位线上的电压波动，稳定地消除感测放大电路中的偏移噪声。
对于控制模块，在一个例子中，控制模块包括：第一控制单元101，一端连接第二读出位线ISABL，另一端用于接收偏置电压VBIAS，用于根据控制信号，向第一PMOS管<P1>提供偏置电压VBIAS。第二控制单元102，一端连接第二互补读出位线ISABLB，另一端用于接收偏置电压VBIAS，用于根据控制信号，向第二PMOS管<P2>提供偏置电压VBIAS。
在一个例子中，控制信号与偏移消除信号OC相同，即控制模块100根据偏移消除信号OC导通。通过设置控制信号与偏移消除信号OC相同，以同步控制模块100和偏移消除模块，从而实现对感测放大电路的偏移消除，如图1所示电路。
在一个例子中，控制信号包括第一控制信号和第二控制信号，其中，第一控制单元101基于第一控制信号导通，第二控制单元102基于第二控制信号导通。即第一控制单元101通过第一控制信号向第一PMOS管<P1>提供偏置电压VBIAS；第二控制单元102通过第二控制信号向第二PMOS管<P2>提供偏置电压VBIAS；通过不同控制信号对第一控制单元和第二控制单元的分别控制，进一步实现对控制模块100的精准控制。
在一些实施例中，第一控制单元101包括第一控制MOS管<11>，第一控制MOS管<11>的源极连接第二读出位线ISABL，栅极用于接收第一控制信号，漏极用于接收偏置电压VBIAS；第二控制单元102包括第二控制MOS管<12>，第二控制MOS管<12>的源极连接第二互补读出位线ISABLB，栅极用于接收第二控制信号，漏极用于接收偏置电压VBIAS。
在一个例子中，控制模块也可以通过相同控制单元，同时向第一PMOS管<P1>和第二PMOS管<P2>提供偏置电压VBIAS。通过同一控制单元提供偏置电压VBIAS，以缩小感测放大电路结构的布局面积，有利于提高存储器的集成度。
对于偏移消除模块，参考图1，偏移消除模块包括：第一偏移消除MOS管<31>，源极连接初始位线BL，漏极连接第一互补读出位线SABLB，栅极用于接收偏移消除信号OC，用于根据偏移消除信号OC使初始位线BL与第一互补读出位线SABLB电连接；第二偏移消除MOS管<32>，源极连接初始互补位线BLB，漏极连接第一读出位线SABL，栅极用于接收偏移消除信号OC，用于根据偏移消除信号OC使初始互补位线BLB与第一读出位线SABL电连接。
在本实施例中，感测放大结构，还包括：第一隔离单元201，一端连接第一读出位线SABL，另一端连接第二读出位线ISABL，用于根据第一隔离信号(Isolation Signal 1，ISO1)使第一读出位线SABL与第二读出位线ISABL电连接；第二隔离单元202，一端连接第一互补读出位线SABLB，另一端连接第二互补读出位线ISABLB，用于根据第一隔离信号(Isolation Signal 1，ISO1)使第一互补读出位线SABLB与第二互补读出位线ISABLB电连接。
在一些实施例中，第一隔离单元201包括第一隔离MOS管<21>，第一隔离MOS管<21>的源极连接第一读出位线SABL，漏极连接第二读出位线ISABL，栅极用于接收第一隔离信号ISO1；第二隔离单元202包括第二隔离MOS管<22>，第二隔离MOS管<22>的源极连接第一互补读出位线SABLB，漏极连接第二互补读出位线ISABLB，栅极用于接收第一隔离信号ISO1。
感测放大电路在预充电阶段，提供第一隔离信号ISO1，以对第二读出位线ISABL和第二互补读出位线ISABLB预充电，在感测放大阶段，提供第一隔离信号ISO1，以使第一PMOS管<P1>的栅极连接至第一读出位线SABL，第一PMOS管<P1>的栅极连接至第一互补读出位线SABLB。
此时，对于第一PMOS管<P1>和第一NMOS管<N1>，由于第一PMOS管<P1>栅极和第一NMOS管<N1>栅极的连接关系相同，即基于第二读出位线ISABL的不同电平，第一PMOS管<P1>或第一NMOS管<N1>导通时，第一PMOS管<P1>和第一NMOS管<N1>中仅存在一个导通的MOS管；对于第二PMOS管<P2>和第二NMOS管<N2>，由于第二PMOS管<P2>栅极和第二NMOS管<N2>栅极的连接关系相同，即基于第二互补位线ISABLB的不同电平，第二PMOS管<P2>或第二NMOS管<N2>导通时，第二PMOS管<P2>和第二NMOS管<N2>中仅存在一个导通的MOS管。
在一些实施例中，当第二PMOS管<P2>导通后，第一信号端与第一读出位线SABL连通，从而将第一读出位线SABL拉高至第一电平信号PCS，进而将初始位线BL拉高至第一电平信号PCS，从而使存储器通过初始位线BL读出的数据为第一电平信号PCS对应逻辑“1”的高电平；当第一NMOS管<N1>导通后，第二信号端与第一互补读出位线SABLB连通，从而将第一互补读出位线SABLB拉低至第二电平信号NCS，进而将初始互补位线BLB拉低至第二电平信号NCS，从而使存储器通过初始互补位线BLB读出的数据为第二电平信号NCS对应逻辑“0”的低电平；当第一PMOS管<P1>导通后，第一信号端与第一互补读出位线SABLB连通，从而将第一互补读出位线SABLB拉高至第一电平信号PCS，进而将初始互补位线BLB拉高至第一电平信 号PCS，从而使存储器通过初始互补位线BLB读出的数据为第一电平信号PCS对应逻辑“1”的高电平；当第二NMOS管<N2>导通后，第二信号端与第一读出位线SABL连通，从而将第一读出位线SABL拉低至第二电平信号NCS，进而将初始位线BL拉低至第二电平信号NCS，从而使存储器通过初始位线BL读出的数据为第二电平信号NCS对应逻辑“0”的低电平。
在本实施例中，感测放大结构，还包括：第三隔离单元203，一端连接初始位线BL，另一端连接第一读出位线SABL，用于根据第二隔离信号(Isolation Signal 2，ISO2)使初始位线BL与第一读出位线SABL电连接；第四隔离单元204，一端连接初始互补位线BLB，另一端连接第一互补读出位线SABLB，用于根据第二隔离信号(Isolation Signal 2，ISO2)使初始互补位线BLB与第一互补读出位线SABLB电连接。
第三隔离单元203包括第三隔离MOS管<23>，第三隔离MOS管<23>的源极连接初始位线BL，漏极连接第一读出位线SABL，栅极用于接收第二隔离信号(Isolation Signal 2，ISO2)。第四隔离单元204包括第四隔离MOS管<24>，第四隔离MOS管<24>的源极连接初始互补位线BLB，漏极连接第一互补读出位线SABLB，栅极用于接收第二隔离信号(Isolation Signal 2，ISO2)。
感测放大电路在偏移消除阶段和放大阶段，提供第二隔离信号ISO2，以实现初始位线BL和第一读出位线SABL、初始互补位线BLB和第一互补位线SABLB的电荷共享。
在本实施例中，感测放大结构，还包括：均衡单元401，一端连接第一读出位线SABL，另一端连接第一互补读出位线SABLB，用于根据均衡信号(Equalizing Signal，EQ)，使第一读出位线SABL的电压与第一互补读出位线SABLB的电压相同。
在一些实施例中，均衡单元401包括均衡MOS管<41>，源极连接第一读出位线SABL，漏极连接第一互补读出位线SABLB，栅极用于接收均衡信号EQ。
需要说明的是，上述各个晶体管定义的具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式。
当控制模块基于控制信号导通时，向第一PMOS管的栅极和第二PMOS管的栅极提供偏置电压，第一PMOS管基于偏置电压导通，第一信号端与第一互补读出位线电连接，第一电平信号传输至第一互补读出位线，第二PMOS管基于偏置电压导通，第一信号端与第一读出位线电连接，第一电平信号传输至第一读出位线，从而实现PMOS管的偏移消除；当偏移消除模块基于偏移消除信号导通后，初始位线与第一互补读出位线电连接并共享电压，初始互补位线与第一读出位线电连接并共享电压，初始位线的电压作为第一NMOS管的栅极电压以导通第一NMOS管，第二信号端与第一互补读出位线电连接，第二电平信号传输至第一互补读出位线，初始互补位线的电压作为第二NMOS管的栅极电压以导通第二NMOS管，第二信号端与第一读出位线电连接，第二电平信号传输至第一读出位线，从而实现NMOS管的偏移消除；由于第一PMOS管和第二PMOS管基于稳定的偏置电压导通，即保持第一读出位线和第一互补读出位线的电压稳定，进一步稳定初始位线和初始互补位线的电压，以避免位线和互补位线上的电压波动，稳定地消除感测放大电路中的偏移噪声。
本公开另一实施例提供了一种存储器架构，包括：多个存储阵列，在初始位线延伸方向和字线延伸方向排列，初始位线延伸方向和字线延伸方向相垂直；上述实施例提供的感测放大结构，在初始位线延伸方向上，设置在相邻存储阵列之间；其 中，感测放大结构通过初始位线连接相邻存储阵列中一存储阵列的存储单元，通过初始互补位线连接相邻存储阵列中另一存储阵列的存储单元；控制模块，在字线延伸方向上，设置在相邻存储阵列之间，控制模块用于向感测放大结构提供数据读出信号、控制信号和偏置电压。
图2本实施例提供的存储器架构的结构布局示意图，图3本实施例提供的存储器架构的具体结构示意图，以下结合附图对本公开各实施例提供的存储器架构作进一步详细说明，具体如下：
参考图2和图3，存储器架构包括：
多个存储阵列400，在初始位线BL延伸方向和字线WL延伸方向上排列。
在一些实施例中，初始位线BL延伸方向和字线WL延伸方向相垂直，在本实施例中，参考图3，初始位线BL延伸方向为纵向，字线WL延伸方向为横向。
上述实施例提供的感测放大结构402，在初始位线BL延伸方向上，设置在相邻存储阵列400之间，其中，感测放大结构402通过初始位线BL连接相邻存储真累阵列中一存储阵列400的存储单元，通过初始互补位线BLB连接相邻存储阵列400中另一存储阵列400的存储单元。
控制模块100，在字线WL延伸方向上，设置在相邻存储阵列400之间，控制模块100用于向感测放大结构提供数据读出信号、控制信号和偏置电压。
其中，控制信号用于导通第一控制MOS管<11>和第二控制MOS管<12>；偏置电压VBIAS用于第一控制MOS管<11>和第二控制MOS管<12>导通时，向感测放大电路的PMOS管提供栅极导通电压。
在一些实施例中，参考图1，数据读出信号包括偏移消除信号OC、第一隔离信号ISO1、第二隔离信号ISO2、均衡信号EQ的至少一者。
其中，第一隔离信号ISO1用于导通第一隔离MOS管<21>和第二隔离MOS管<22>；第二隔离信号ISO2用于导通第三隔离MOS管<23>和第四隔离MOS管<24>；偏移消除信号OC用于导通第一偏移消除MOS管<31>和第二偏移消除MOS管<32>；均衡信号EQ用于导通均衡MOS管<11>。
在一个例子中，控制信号与偏移消除信号OC相同，即控制模块100根据偏移消除信号OC导通。通过设置控制信号与偏移消除信号OC相同，以同步控制模块100和偏移消除模块，从而实现对感测放大电路的偏移消除。
在一些实施例中，参考图2和图3，控制模块100包括：信号控制单元413，用于向感测放大结构提供读出信号和控制信号；偏压控制单元414，用于向感测放大结构提供偏置电压。
其中，在字线WL延伸方向上，信号控制单元413和偏压控制单元414设置在感测放大结构402的相对两侧。
在本实施例中，控制模块100还包括：列选控制单元412，用于提供列选择信号，列选择信号用于导通存储阵列400中的部分初始位线BL或者初始互补位线BLB；行选控制单元411，用于提供行选择信号，行选择信号用于导通存储阵列400中部分字线WL；即列选控制单元412用于根据列选择信号选中相应位线BL从而选中相应存储单元，行选控制单元411用于根据行选择信号选中相应字线WL从而选中相应存储单元。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的感测放大结构和存储器架构中，当控制模块基于控制信号导通时，向第一PMOS管的栅极和第二PMOS管的栅极提供偏置电压，第一PMOS管基于偏置电压导通，第一信号端与第一互补读出位线电连接，第一电平信号传输至第一互补读出位线，第二PMOS管基于偏置电压导通，第一信号端与第一读出位线电连接，第一电平信号传输至第一读出位线，从而实现PMOS管的偏移消除；当偏移消除模块基于偏移消除信号导通后，初始位线与第一互补读出位线电连接并共享电压，初始互补位线与第一读出位线电连接并共享电压，初始位线的电压作为第一NMOS管的栅极电压以导通第一NMOS管，第二信号端与第一互补读出位线电连接，第二电平信号传输至第一互补读出位线，初始互补位线的电压作为第二NMOS管的栅极电压以导通第二NMOS管，第二信号端与第一读出位线电连接，第二电平信号传输至第一读出位线，从而实现NMOS管的偏移消除；由于第一PMOS管和第二PMOS管基于稳定的偏置电压导通，即保持第一读出位线和第一互补读出位线的电压稳定，进一步稳定初始位线和初始互补位线的电压，以避免位线和互补位线上的电压波动，稳定地消除感测放大电路中的偏移噪声。

Claims (16)

  1. 一种感测放大结构，设置在相邻存储阵列之间，包括：
    第一PMOS管，其栅极连接第二读出位线，其源极连接第一信号端；
    第一NMOS管，其栅极连接初始位线，其源极连接第二信号端；
    所述第一PMOS管的漏极和所述第一NMOS管的漏极连接第一互补读出位线，其中，所述第一信号端用于接收第一电平信号，所述第二信号端用于接收第二电平信号；
    第二PMOS管，其栅极连接第二互补读出位线，其源极连接所述第一信号端；
    第二NMOS管，其栅极连接初始互补位线，其源极连接所述第二信号端；
    所述第二PMOS管的漏极和所述第二NMOS管的漏极连接第一读出位线，其中，所述初始位线连接相邻所述存储阵列中一所述存储阵列的存储单元，所述初始互补位线连接相邻所述存储阵列中另一所述存储阵列的存储单元；
    偏移消除模块，部分连接在所述初始位线与所述第一互补读出位线之间，部分连接在所述初始互补位线和所述第一读出位线之间，用于根据偏移消除信号，使所处初始位线与所述第一互补读出位线电连接，并使所述初始互补位线与所述第一读出位线电连接；
    控制模块，连接所述第二读出位线和所述第二互补读出位线，用于根据控制信号，向所述第一PMOS管和所述第二PMOS管提供偏置电压。
  2. 根据权利要求1所述的感测放大结构，其中，所述控制信号与所述偏移消除信号相同。
  3. 根据权利要求1或2所述的感测放大结构，其中，所述控制信号包括第一控制信号和第二控制信号，所述控制模块包括：
    第一控制单元，其一端连接所述第二读出位线，其另一端用于接收所述偏置电压，用于根据所述第一控制信号向所述第一PMOS管提供所述偏置电压；
    第二控制单元，其一端连接所述第二互补读出位线，其另一端用于接收所述偏置电压，用于根据所述第二控制信号向所述第二PMOS管提供所述偏置电压。
  4. 根据权利要求3所述的感测放大结构，其中，所述第一控制单元包括第一控制MOS管，所述第二控制单元包括第二控制MOS管；
    所述第一控制MOS管的源极连接所述第二读出位线，栅极用于接收所述第一控制信号，漏极用于接收所述偏置电压；
    所述第二控制MOS管的源极连接所述第二互补读出位线，栅极用于接收所述第二控制信号，漏极用于接收所述偏置电压。
  5. 根据权利要求1所述的感测放大结构，还包括：
    第一隔离单元，其一端连接所述第一读出位线，其另一端连接所述第二读出位线，用于根据第一隔离信号使所述第一读出位线与所述第二读出位线电连接；
    第二隔离单元，其一端连接所述第一互补读出位线，其另一端连接所述第二互补读出位线，用于根据所述第一隔离信号使所述第一互补读出位线与所述第二互补读出位线 电连接。
  6. 根据权利要求5所述的感测放大结构，其中，所述第一隔离单元包括第一隔离MOS管，所述第二隔离单元包括第二隔离MOS管；
    所述第一隔离MOS管的源极连接所述第一读出位线，漏极连接所述第二读出位线，栅极用于接收所述第一隔离信号；
    所述第二隔离MOS管的源极连接所述第一互补读出位线，漏极连接所述第二互补读出位线，栅极用于接收所述第一隔离信号。
  7. 根据权利要求1所述的感测放大结构，还包括：
    第三隔离单元，其一端连接所述初始位线，其另一端连接所述第一读出位线，用于根据第二隔离信号使所述初始位线与所述第一读出位线电连接；
    第四隔离单元，其一端连接所述初始互补位线，其另一端连接所述第一互补读出位线，用于根据所述第二隔离信号使所述初始互补位线与所述第一互补读出位线电连接。
  8. 根据权利要求7所述的感测放大结构，其中，所述第三隔离单元包括第三隔离MOS管，所述第四隔离单元包括第四隔离MOS管，
    所述第三隔离MOS管的源极连接所述初始位线，漏极连接所述第一读出位线，栅极用于接收所述第二隔离信号；
    所述第四隔离MOS管的源极连接所述初始互补位线，漏极连接所述第一互补读出位线，栅极用于接收所述第二隔离信号。
  9. 根据权利要求1所述的感测放大结构，还包括：均衡单元，其一端连接所述第一读出位线，其另一端连接所述第一互补读出位线，用于根据均衡信号，使所述第一读出位线的电压与所述第一互补读出位线的电压相同。
  10. 根据权利要求9所述的感测放大结构，其中，所述均衡单元包括均衡MOS管，所述均衡MOS管的源极连接所述第一读出位线，漏极连接所述第一互补读出位线，栅极用于接收所述均衡信号。
  11. 根据权利要求1所述的感测放大结构，其中，所述偏移消除模块，包括：
    第一偏移消除MOS管，其源极连接所述初始位线，其漏极连接所述第一互补读出位线，其栅极用于接收所述偏移消除信号，用于根据所述偏移消除信号使所处初始位线与所述第一互补读出位线电连接；
    第二偏移消除MOS管，其源极连接所述初始互补位线，其漏极连接所述第一读出位线，其栅极用于接收所述偏移消除信号，用于根据所述偏移消除信号使所述初始互补位线与所述第一读出位线电连接。
  12. 一种存储器架构，包括：
    多个存储阵列，在初始位线延伸方向和字线延伸方向排列，所述初始位线延伸方向和所述字线延伸方向相垂直；
    根据权利要求1～11任一项所述的感测放大结构，在所述初始位线延伸方向上，设置在相邻所述存储阵列之间；
    其中，所述感测放大结构通过初始位线连接相邻所述存储阵列中一所述存储阵列的存储单元，通过初始互补位线连接相邻所述存储阵列中另一所述存储阵列的存储单元；
    控制模块，在所述字线延伸方向上，设置在相邻所述存储阵列之间，所述控制模块用于向所述感测放大结构提供数据读出信号、控制信号和偏置电压。
  13. 根据权利要求12所述的存储器架构，其中，所述数据读出信号包括偏移消除信号、第一隔离信号、第二隔离信号、均衡信号的至少一者，所述控制模块包括：
    信号控制单元，用于向所述感测放大结构提供所述数据读出信号和所述控制信号；
    偏压控制单元，用于向所述感测放大结构提供所述偏置电压。
  14. 根据权利要求13所述的存储器架构，其中，所述信号控制单元和所述偏压控制单元设置在所述感测放大结构的相对两侧。
  15. 根据权利要求13所述的存储器架构，其中，所述控制信号和所述偏移消除信号相同。
  16. 根据权利要求12所述的存储器架构，所述控制模块，还包括：
    列选控制单元，用于提供列选择信号，所述列选择信号用于导通所述存储阵列中的部分所述初始位线或所述初始互补位线；
    行选控制单元，用于提供行选择信号，所述行选择信号用于导通所述存储阵列中的部分所述字线。
PCT/CN2022/094359 2021-08-27 2022-05-23 感测放大结构和存储器架构 WO2023024608A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/812,032 US12033688B2 (en) 2021-08-27 2022-07-12 Sense amplification structure and memory architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110998262.1A CN115910148A (zh) 2021-08-27 2021-08-27 感测放大结构和存储器架构
CN202110998262.1 2021-08-27

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/812,032 Continuation US12033688B2 (en) 2021-08-27 2022-07-12 Sense amplification structure and memory architecture

Publications (1)

Publication Number Publication Date
WO2023024608A1 true WO2023024608A1 (zh) 2023-03-02

Family

ID=85322397

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/094359 WO2023024608A1 (zh) 2021-08-27 2022-05-23 感测放大结构和存储器架构

Country Status (2)

Country Link
CN (1) CN115910148A (zh)
WO (1) WO2023024608A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150357021A1 (en) * 2014-06-05 2015-12-10 Micron Technology, Inc. Performing logical operations using sensing circuitry
CN112712837A (zh) * 2021-01-05 2021-04-27 长鑫存储技术有限公司 灵敏放大器、灵敏放大器的控制方法及存储器
CN112767975A (zh) * 2021-02-10 2021-05-07 长鑫存储技术有限公司 灵敏放大器及其控制方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150357021A1 (en) * 2014-06-05 2015-12-10 Micron Technology, Inc. Performing logical operations using sensing circuitry
CN112712837A (zh) * 2021-01-05 2021-04-27 长鑫存储技术有限公司 灵敏放大器、灵敏放大器的控制方法及存储器
CN112767975A (zh) * 2021-02-10 2021-05-07 长鑫存储技术有限公司 灵敏放大器及其控制方法

Also Published As

Publication number Publication date
CN115910148A (zh) 2023-04-04

Similar Documents

Publication Publication Date Title
KR100843139B1 (ko) 오픈 비트 라인 구조를 갖는 멀티레벨 동적 메모리 장치 및그 구동 방법
US7616510B2 (en) Dynamic semiconductor storage device and method for operating same
TWI489455B (zh) 不具專用通閘電晶體之差動感測放大器
EP4243021A1 (en) Sense amplification circuit and data readout method
WO2021196841A1 (zh) 灵敏放大器、存储器和数据读出方法
US7969794B2 (en) One-transistor type DRAM
WO2024007544A1 (zh) 存储单元、阵列读写方法、控制芯片、存储器和电子设备
US7593282B2 (en) Memory core with single contacts and semiconductor memory device having the same
WO2023273554A1 (zh) 读出电路结构
CN114400029B (zh) 读出电路及其方法
US6049492A (en) Interleaved sense amplifier with a single-sided precharge device
WO2023024608A1 (zh) 感测放大结构和存储器架构
WO2023082548A1 (zh) 读出电路的版图结构和数据读出方法
WO2023000490A1 (zh) 感测放大电路和数据读出方法
KR20170035189A (ko) 비트라인 이퀄라이저
WO2023024640A1 (zh) 感测放大电路和数据读出方法
US7474549B2 (en) Bit-line equalizer, semiconductor memory device including the same, and method for manufacturing bit-line equalizer
US12033688B2 (en) Sense amplification structure and memory architecture
US5177708A (en) Dynamic random access memory and method for equalizing sense amplifier drive signal lines
CN115411035A (zh) 读出电路版图、结构以及存储器版图
CN115411028A (zh) 读出电路版图、结构以及存储器版图
WO2023134009A1 (zh) 一种读出电路架构和感测放大电路
WO2023040158A1 (zh) 读出电路架构
JPH09320280A (ja) 半導体記憶装置
WO2023133975A1 (zh) 读出电路版图

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22859956

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22859956

Country of ref document: EP

Kind code of ref document: A1