WO2024007544A1 - 存储单元、阵列读写方法、控制芯片、存储器和电子设备 - Google Patents

存储单元、阵列读写方法、控制芯片、存储器和电子设备 Download PDF

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WO2024007544A1
WO2024007544A1 PCT/CN2022/140811 CN2022140811W WO2024007544A1 WO 2024007544 A1 WO2024007544 A1 WO 2024007544A1 CN 2022140811 W CN2022140811 W CN 2022140811W WO 2024007544 A1 WO2024007544 A1 WO 2024007544A1
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electrode
transistor
read
data
voltage
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PCT/CN2022/140811
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English (en)
French (fr)
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朱正勇
康卜文
赵超
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北京超弦存储器研究院
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Publication of WO2024007544A1 publication Critical patent/WO2024007544A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Some embodiments of the present disclosure relate to the field of semiconductor technology, particularly a memory unit, an array reading and writing method, a control chip, a memory and an electronic device.
  • the traditional traditional unit used in dynamic random access memory includes a transistor and a capacitor (as shown in Figure 1, where SN is the Storage Node storage node, BL is the Bit-line bit line, and WL is the Word-line word. line, C is the capacitor, G is the gate of the transistor, S is the source of the transistor, and D is the drain of the transistor).
  • SN is the Storage Node storage node
  • BL bit-line bit line
  • WL the Word-line word. line
  • C is the capacitor
  • G the gate of the transistor
  • S is the source of the transistor
  • D drain of the transistor
  • Some embodiments of the present disclosure provide a memory unit, an array reading and writing method, a control chip, a memory and an electronic device, which have very low leakage, can solve the problems of high refresh frequency and high power consumption of current memory units, and improve readability.
  • the performance of write operations is conducive to the setting of peripheral devices and provides a technical basis for solving crosstalk problems.
  • Some embodiments provide a storage unit, including:
  • a first transistor configured as a read transistor
  • a second transistor configured as a write transistor
  • the first transistor includes a first electrode, a second electrode, a third electrode and a fourth electrode; the third electrode is a first gate, and the fourth electrode is a second gate;
  • the second transistor includes a fifth electrode, a sixth electrode and a seventh electrode; the seventh electrode is a third gate;
  • the first electrode is configured to be connected to the read bit line
  • the second electrode is configured to be a reference voltage terminal for connecting a reference signal
  • the first gate is configured to be connected to the read word line
  • the second electrode is configured to be connected to the read word line.
  • the gate is configured to be connected to the fifth electrode;
  • the sixth electrode is configured to be connected to the write bit line, and the third gate electrode is configured to be connected to the write word line.
  • a storage array includes:
  • the memory unit includes: a first transistor and a second transistor; the first transistor includes a first electrode, a second electrode, a third electrode and a fourth electrode; the third electrode is a first gate electrode, so The fourth electrode is the second gate;
  • the second transistor includes a fifth electrode, a sixth electrode and a seventh electrode; the seventh electrode is a third gate;
  • the first electrode is connected to the readout bit line
  • the second electrode can be set as a reference voltage terminal for connecting a reference signal
  • the first gate is connected to the readout word line
  • the third electrode is connected to the readout word line.
  • the second gate is connected to the fifth electrode;
  • the sixth electrode is connected to the write bit line, and the third gate electrode is connected to the write word line.
  • a storage array including:
  • the memory unit includes: a first transistor and a second transistor; the first transistor includes a first electrode, a second electrode, a third electrode and a fourth electrode; the third electrode is a first gate electrode, so The fourth electrode is the second gate;
  • the second transistor includes a fifth electrode, a sixth electrode and a seventh electrode; the seventh electrode is a third gate;
  • the first electrode and the sixth electrode are jointly connected to the common bit line, the second electrode can be set as a reference voltage terminal for connecting a reference signal, and the first gate is connected to the read word The second gate is connected to the fifth electrode;
  • the third gate is connected to the write word line.
  • a storage system including:
  • each of the amplifiers is an amplifier shared by two adjacent storage arrays; the amplifier is configured to amplify the storage data read from the storage cells in the storage array sensed during the sensing phase, and during the refreshing phase , writing the amplified storage data back to the storage node of the storage unit.
  • a data writing method is provided, based on the above-mentioned storage array, and the method includes:
  • the gate voltage of the second transistor of the memory cell is input through the write word line of the memory cell, so that the second transistor serving as the write transistor conduction;
  • a write voltage is input to the conductive second transistor through the write bit line of the memory cell or the common bit line, so that the write voltage is stored in the second gate of the first transistor connected to the second transistor.
  • electrode wherein the second gate is configured as a storage node of the memory cell, and the first transistor is a read transistor.
  • a data reading method is provided, based on the above-mentioned storage array, and the method includes:
  • the read word line connected to the first transistor of the memory cell to be read data in the memory array inputs a first voltage; wherein the first voltage is between the first threshold voltage and the second threshold voltage.
  • the first threshold voltage is the turn-on threshold voltage of the first transistor when the memory unit stores data "1"
  • the second threshold voltage is the corresponding threshold voltage when the memory unit stores data "0". the turn-on threshold voltage of the first transistor;
  • the read data of the memory cell is 1.
  • the first When the voltage of the read bit line connected to the transistor has no change or the change value is less than or equal to the preset second voltage change threshold, it is determined that the read data of the memory cell is 0.
  • a control chip of a storage array is provided, and the control chip is configured to execute the above data writing method.
  • a control chip of a storage array is provided, and the control chip is configured to perform the above data reading method.
  • a memory including the storage array.
  • an electronic device including the memory.
  • the read transistor includes a first gate and a second gate, and the second gate is connected to an electrode of the write transistor, and the write transistor stores the write voltage in the electrode, eliminating the need for The capacitor is removed, thereby solving the problem of the need for large capacitance, and accordingly reducing the refresh frequency and power consumption; and because the gate of the read transistor has a back-gate effect, by setting two gates, it is beneficial for the first gate to adjust according to the second gate.
  • the voltage of the second gate (can be regarded as the auxiliary gate) adjusts the applied voltage to ensure the conduction between the source and drain of the first transistor, improves the performance of read and write operations, and is conducive to the setting of peripheral devices. It provides a technical basis for solving crosstalk problems.
  • Figure 1 is a schematic diagram of a memory unit with a 1T1C structure in the prior art
  • Figure 2 is a schematic diagram of a traditional 2T0C structure memory unit in the prior art
  • Figure 3 is a schematic diagram of a memory unit in a 2TOC structure according to some embodiments of the present disclosure
  • Figure 4 is a schematic diagram of the threshold voltage shift of a transistor gate caused by the back gate effect in the related art
  • Figure 5 is a schematic diagram of a memory cell in a 2TOC structure when the first electrode and the sixth electrode are combined into one electrode according to some embodiments of the present disclosure
  • Figure 6 is a flow chart of a data writing method in a storage unit according to some embodiments of the present disclosure.
  • Figure 7 is a flow chart of a data reading method of a storage unit according to some embodiments of the present disclosure.
  • Figure 8 is a schematic structural diagram of a memory array composed of memory cells with a 2TOC structure according to some embodiments of the present disclosure
  • Figure 9a is a schematic structural diagram of a memory array composed of 2TOC structure memory cells when the first electrode and the sixth electrode are combined into one electrode according to some embodiments of the present disclosure
  • Figure 9b is a schematic diagram of the memory array structure when the first electrode and the sixth electrode are not merged into one electrode, and the connected read bit line and write bit line are combined outside the memory array according to some embodiments of the present disclosure;
  • Figure 10a is a schematic structural diagram of a storage system according to some embodiments of the present disclosure.
  • Figure 10b is a partially enlarged schematic diagram of another storage system structure according to some embodiments of the present disclosure.
  • Figure 10c is a schematic connection diagram when the amplifier is a current amplifier according to some embodiments of the present disclosure.
  • Figure 11 is a flow chart of a data writing method for a storage array according to some embodiments of the present disclosure.
  • Figure 12 is a flow chart of a data reading method for a storage array according to some embodiments of the present disclosure.
  • Figure 13 is a flow chart of a data writing method of a storage system according to some embodiments of the present disclosure.
  • Figure 14 is a flow chart of a data reading method of a storage system according to some embodiments of the present disclosure.
  • Some embodiments of the present disclosure provide a new logic circuit and related structural design, process flow and other solutions.
  • the read transistor has a double-gate structure, one of which is a control gate and the other is used as a storage node of the storage capacitor.
  • a suitable voltage is given to the read transistor, so that the read transistor is turned on when data "1" is stored in the storage capacitor node, and remains off when data "0" is input.
  • the read operation of the above scheme is non-destructive, so that a write transistor with a lower leakage current can be used but the storage node must be required to store a higher capacitance to maintain the validity of the data.
  • the write transistor may be a metal oxide semiconductor field effect transistor.
  • FIG. 1 Some embodiments of the present disclosure provide a storage unit 1, as shown in Figure 3, which may include:
  • the first transistor TR_R is configured as a read transistor
  • the second transistor TR_W is set as a write transistor
  • the first transistor TR_R includes a first electrode P1, a second electrode P2, a third electrode P3 and a fourth electrode P4; the third electrode P3 is a first gate electrode G1, and the fourth electrode P4 is a first gate electrode G1.
  • Two gates G2 (referred to as back gate);
  • One of the first electrode P1 and the second electrode P2 is a source electrode, and the other is a drain electrode.
  • the second transistor TR_W includes a fifth electrode P5, a sixth electrode P6 and a seventh electrode P7; the seventh electrode P7 is a third gate G3;
  • One of the fifth electrode P5 and the sixth electrode P6 is a source electrode, and the other is a drain electrode.
  • the first electrode P1 is set to be connected to the read bit line R_BL, the second electrode P2 can be set to input the reference voltage Vrefn, used to connect the reference signal; the first gate G1 is set to be connected to the read word line R_WL is connected, and the second gate G2 is set to be connected to the fifth electrode P5;
  • the sixth electrode P6 is configured to be connected to the write bit line W_BL, and the third gate G3 is configured to be connected to the write word line W_WL.
  • the memory cell 1 is also a 2TOC structure.
  • Tr_w is a write transistor and Tr_r is a read transistor
  • the read operation of the above scheme is non-destructive. In this way, lower leakage current write transistors can be used but the storage node must be required to store higher capacitance to maintain the validity of the data.
  • capacitance storage can be achieved through the back gate, and the refresh frequency and power consumption of the memory cell can be reduced at the same time through the low-leakage write transistor.
  • the first transistor TR_R includes two gates, that is, an auxiliary gate (ie, a second gate, also called a back gate) is added, and the second gate is connected to the write transistor.
  • the fifth electrode P5 of the second transistor TR_W is connected to the fifth electrode P5, and the voltage provided by the fifth electrode P5 is set as the write voltage of the storage write transistor.
  • the first gate G1 and the second gate G2 are independent gates, and the first gate G1 is used to control the read operation of the read transistor TR_R;
  • the second gate G2 is configured as a storage node of the memory cell, and data is written at the storage node through the write transistor TR_W.
  • the gate of the transistor Since the gate of the transistor has a back-gate effect, as the write transistor writes voltage to the fifth electrode P5, the auxiliary gate of the read transistor obtains the corresponding write voltage, and depending on the write voltage of the auxiliary gate (for example, high voltage or low voltage), the gate of the read transistor will exhibit a different threshold voltage (V TH ). As shown in Figure 4, for the N-type read transistor TR_R, when the voltage of the auxiliary gate is high voltage (for example, the written data is "1"), V TH will shift negatively; when the voltage of the auxiliary gate is At low voltages (e.g., writing data as "0"), V TH will shift forward.
  • the read transistor BL bit line
  • the voltage on the read transistor BL does not change significantly. There may be a slight change when considering leakage, but the change value is smaller than the preset threshold.
  • a corresponding high voltage is given to the auxiliary gate, which causes the threshold voltage of the read transistor to be negatively biased, and the read transistor is turned on. At this time, the BL of the read transistor is affected by the high voltage, the voltage changes, and the change value exceeds the threshold.
  • the SA circuit (data reading circuit) is connected to the read bit line and determines whether the read data is 1 or 0 by analyzing the voltage change on the read bit line; during the process of reading 0 and 1, the control gate of the read transistor ( The voltage on the first gate) is constant, and the voltage written on the auxiliary gate changes the threshold voltage of the read transistor so that the read transistor automatically turns on or remains off.
  • the first transistor TR_R is an N-type transistor
  • the second transistor TR_W is an N-type transistor or a P-type transistor.
  • the first transistor TR_R and the second transistor TR_W may both be N-type transistors, or both may be P-type transistors, or either one may be an N-type transistor and the other may be a P-type transistor, where There is no restriction on the selection of the first transistor TR_R and the second transistor TR_W, and they can be defined according to the requirements.
  • the first electrode P1, the second electrode P2, the fifth electrode P5, and the sixth electrode P6 may be set according to the type of the selected transistor.
  • the first electrode P1 the second electrode
  • the electrode P2, the fifth electrode P5, and the sixth electrode P6 are drain electrodes or source electrodes, and can be defined according to different scenarios and needs.
  • the first electrode P1 and the sixth electrode P6 share one electrode in the logic circuit and are configured to be connected to different bit lines or to the same bit line. wire connection.
  • the different bit lines are the read bit line and the write bit line; the same bit line serves as the read bit line and the write bit line simultaneously.
  • bit lines bit lines
  • WL word lines
  • the BL connected to the first electrode P1 and the sixth electrode P6 shares a line in the memory array area.
  • the BL connecting the first electrode P1 and the sixth electrode P6 may be two lines in the memory array area, but is one line in the peripheral area. Wherein, via holes are provided in the array area or peripheral area, and the via holes connect the two lines.
  • each memory cell in some embodiments of the present disclosure has only 3 signals, including 2 word line signals and 1 bit line signal, which is beneficial to Layout design, especially layout design in small spaces, improves the practicality of the storage unit 1 of some embodiments of the present disclosure.
  • the data writing method of the storage unit may include steps S101-S102:
  • the voltage to be written may correspond to a voltage that stores data “1” or “0”, the write word line W_WL is applied to the turn-on voltage of the second transistor, and the second transistor TR_W There is conduction between the fifth electrode P5 and the sixth electrode P6, then after the voltage is written through the write bit line W_BL, the voltage at the end of the fifth electrode P5 is the same as the voltage at the end of the sixth electrode P6 (connected to the write bit line W_BL). are the write voltages.
  • the method may further include:
  • a voltage different from the conduction voltage of the third gate G3 is input to the write word line W_WL of the memory cell that does not need to be written, so that the second transistor TR_W of the memory cell 1 that does not need to be written is turned off. .
  • the write bit needs to be controlled.
  • the write word line W_WL connected to the gates of other memory cells 1 connected to the line W_BL applies a voltage different from the turn-on voltage input to the third gate G3 of the memory cell 1 to which data needs to be written, so that writing is required.
  • the second transistor TR_W (write transistor) of the memory unit 1 into which data is input is turned on, while the second transistor TR_W of other memory cells that do not need to be written into is turned off, ensuring that the write data is only written into the memory unit that needs to be written into. storage unit.
  • the data reading method of the storage unit may include steps S201-S204:
  • the first transistor TR_R serves as a read transistor.
  • a voltage can be input to the first gate G1 of the first transistor TR_R so that the first The first electrode P1 and the second electrode P2 of the transistor TR_R are turned off, so that whether the gate stores a high voltage or a low voltage is determined based on the change in the signal on the read bit line. If the change exceeds the threshold, the read data is "1", if there is no change, the read data is "0".
  • the first gate G1 of the first transistor TR_R is connected to the read word line R_WL, and the voltage of the first gate G1 can be provided through the read word line R_WL.
  • the gate of the first transistor TR_R has a backgate effect. Therefore, when the stored write voltage is provided to the second gate G2 (auxiliary gate) of the first transistor TR_R through the fifth electrode P5, the first transistor TR_R will The threshold voltage of the gate is shifted, and the shift is also different depending on the data written on the fifth electrode P5 (such as "1" or "0").
  • the first gate of the first transistor TR_R When G1 applies a voltage, it can be implemented according to the voltage of the second gate G2 to ensure that the first electrode P1 and the second electrode P2 of the first transistor TR_R are turned off, so that the first electrode P1 can read the stored voltage. .
  • the voltage applied to the first gate G1 of the first transistor TR_R may be between the first threshold voltage and the second threshold voltage to supplement the voltage of the auxiliary gate, so that the first transistor TR_R is turned off.
  • the first threshold voltage is the activation threshold voltage of the first transistor when the storage unit stores data "1"; the second threshold voltage is the activation threshold of the first transistor when the storage unit stores data "0" Voltage.
  • the readout bit line R_BL connected to the first electrode P1 may be precharged with a voltage (ie, the second voltage) when initially reading data, and the precharge voltage may be a voltage smaller than that of the memory device.
  • the voltage of the power supply voltage VDD for example, can include but is not limited to VDD/4, VDD/3, VDD/2, etc. The detailed values can be defined according to different application scenarios and requirements.
  • the reference voltage Vrefn may include but is not limited to 0V.
  • the first voltage change threshold can be defined according to different needs or accuracy requirements, and is not limited in detail here.
  • the second voltage change threshold can be defined according to different needs or accuracy requirements, and is not limited in detail here.
  • the method may further include:
  • the read word line input of the memory cell that does not need to read data and the first transistor TR_R of the memory cell that needs to read data are connected.
  • the read word lines input voltages with different voltages, so that the first transistor of the memory cell that does not need to read data is turned off.
  • Tr_w write transistor
  • Tr_r read transistor
  • W-WL write word line
  • W-BL write bit line
  • R-WL read word line
  • R-BL read bit line
  • the method may further include:
  • the write word line W_WL in the memory array inputs the turn-on voltage of the third gate G3 of the memory cell
  • the read voltage value is input to the write bit line W_BL corresponding to the memory cell to which data needs to be written, so as to refresh the voltage value stored in the second transistor TR_W.
  • the write voltage in order to avoid leakage causing the written voltage to change, can be rewritten into the write transistor in time after each readout to save the write voltage, so as to realize storage Timely refresh of voltage.
  • the method may further include:
  • the write word line of the memory cell that does not need to refresh data in the memory array inputs a voltage different from the turn-on voltage of the third gate G3 , so that the second transistor TR_W of the memory unit 1 that does not need to write data is turned off.
  • the write bit line needs to be controlled.
  • the write word line W_WL connected to the gates of other memory cells 1 connected to W_BL applies a voltage different from the input voltage of the third gate G3 of the memory cell 1 to which data needs to be written, thereby enabling the storage of data to be written.
  • the second transistor TR_W (write transistor) of unit 1 is turned on, while the second transistors TR_W of other memory cells that do not need to be written with data are turned off, ensuring that write data is only written into the memory unit 1 that needs to be written with data.
  • Some embodiments of the present disclosure also provide a storage array 2, as shown in Figure 8, which may include:
  • the memory unit 1 includes: a first transistor TR_R and a second transistor TR_W; the first transistor TR_R includes a first electrode P1, a second electrode P2, a third electrode P3 and a fourth electrode P4; The three electrodes P3 are the first gate electrode G1, and the fourth electrode P4 is the second gate electrode G2;
  • the second transistor TR_W includes a fifth electrode P5, a sixth electrode P6 and a seventh electrode P7; the seventh electrode P7 is a third gate G3;
  • the first electrode P1 is connected to the read bit line R_BL, the second electrode P2 is set to input the reference voltage Vrefn, the first gate G1 is connected to the read word line R_WL, and the second The gate G2 is connected to the fifth electrode P5;
  • the sixth electrode P6 is connected to the write bit line W_BL, and the third gate G3 is connected to the write word line W_WL.
  • the write word line W_WL and the read word line R_WL may include multiple rows, for example, may include: W_WL_1, W_WL_2, W_WL_3, ..., W_WL_m, and R_WL_1, R_WL_2, R_WL_3, ... , R_WL_m, etc.
  • the read bit line R_BL and the write bit line W_BL may include multiple columns, for example, may include: R_BL_1, R_BL_2, R_BL_3, ..., R_BL_n, and W_BL_1, W_BL_2, W_BL_3, ... , W_BL_n, etc.
  • each memory unit 1 in the memory array 2 is a 2TOC structure.
  • the read operation is Lossless, with very low leakage, and without the need for large capacitance capacitors, indium gallium zinc oxide (IGZO) transistors can be used in this structure. Therefore, the 2TOC structure of the memory cell 1 of some embodiments of the present disclosure solves the problem of large capacitance.
  • the demand for capacitors reduces the refresh frequency and power consumption accordingly.
  • the read transistor (ie, the first transistor TR_R) in the memory cell of the 2TOC structure in some embodiments of the present disclosure includes two gates, namely , an auxiliary gate (second gate) is added, the second gate is connected to the fifth electrode P5 of the write transistor (ie, the second transistor TR_W), the voltage is provided by the fifth electrode P5, and the fifth electrode P5 is set to Stores the write voltage of the write transistor.
  • the gate of the transistor Since the gate of the transistor has a back-gate effect, as the write transistor writes voltage to the fifth electrode P5, the auxiliary gate of the read transistor obtains the corresponding write voltage, and depending on the write voltage of the auxiliary gate (for example, High voltage or low voltage), the gate of the read transistor will show different threshold voltages (V TH ), as shown in Figure 4.
  • V TH threshold voltages
  • the read transistor BL bit line
  • the voltage on the read transistor BL does not change significantly. There may be a slight change when considering leakage, but the change value is smaller than the preset threshold.
  • a corresponding high voltage is given to the auxiliary gate, which causes the threshold voltage of the read transistor to be negatively biased, and the read transistor is turned on. At this time, the BL of the read transistor is affected by the high voltage, the voltage changes, and the change value exceeds the threshold.
  • the SA circuit (data reading circuit) is connected to the read bit line and determines whether the read data is "1" or "0” by analyzing the voltage change on the read bit line; during the process of reading "0" and “1” , the voltage on the control gate (first gate) of the read transistor is constant, and the voltage written on the auxiliary gate (second gate) changes the threshold voltage of the read transistor so that the read transistor automatically turns on or Stay closed.
  • the first transistor TR_R is an N-type transistor or a P-type transistor
  • the second transistor TR_W is an N-type transistor or a P-type transistor.
  • the first transistor TR_R and the second transistor TR_W may both be N-type transistors, or both may be P-type transistors, or either one may be an N-type transistor and the other may be a P-type transistor, where There is no restriction on the selection of the first transistor TR_R and the second transistor TR_W, and they can be defined according to the requirements.
  • the first electrode P1, the second electrode P2, the fifth electrode P5, and the sixth electrode P6 may be set according to the type of the selected transistor.
  • the first electrode P1 the second electrode
  • the electrode P2, the fifth electrode P5, and the sixth electrode P6 are drain electrodes or source electrodes, and can be defined according to different scenarios and needs.
  • the storage array 2 may further include: a row decoder (Row decoder) and a column decoder (Column decoder);
  • the write word line and the read word line may be connected to the row decoder
  • the write bit line and the read bit line may be connected to the column decoder.
  • Some embodiments of the present disclosure also provide a storage array, which may include:
  • the memory unit 1 includes: a first transistor TR_R and a second transistor TR_W; the first transistor TR_R includes a first electrode P1, a second electrode P2, a third electrode P3 and a fourth electrode P4; the third The electrode P3 is the first gate, and the fourth electrode P4 is the second gate;
  • the second transistor TR_W includes a fifth electrode P5 and a sixth electrode P6; the seventh electrode P7 is a third gate G3;
  • the first electrode P1 and the sixth electrode P6 are jointly connected to the common bit line BL, the second electrode P2 is set as a reference voltage terminal, the first gate G1 and the readout word line R_WL Connected, the second gate G2 is connected to the fifth electrode P5;
  • the third gate G3 is connected to the write word line W_WL.
  • the write bit line and the read bit line can be combined and used as the common bit line BL, which can include but is not limited to the following two solutions.
  • the first electrode P1 and the sixth electrode P6 are merged into one electrode, and the write bit line W_BL and the read bit line R_BL are merged. It is a common bit line, and the electrode obtained after merging is connected to the common bit line obtained after merging.
  • the first electrode P1 and the sixth electrode P6 are not combined into one electrode in the memory cell, and the write bit line W_BL and the read bit line W_BL are not combined into one electrode in the memory cell.
  • the outgoing bit lines R_BL are combined into a common bit line outside the memory array.
  • the second gate of the memory cell in FIGS. 9a and 9b is represented by a capacitor symbol, but this does not mean that it is a capacitor.
  • the write word line W_WL and the read word line R_WL may include multiple rows, for example, may include: W_WL_1, W_WL_2, W_WL_3, ..., W_WL_m, and R_WL_1, R_WL_2, R_WL_3, ... , R_WL_m, etc.
  • the common bit line BL may include multiple columns, for example, may include: BL1, BL2, BL3, ..., BLn, etc.
  • bit lines bit lines
  • WL word lines
  • the first electrode P1 connected to the read bit line R_BL may be connected to the sixth electrode P6 connected to the write bit line W_BL, so that the first electrode P1 and the sixth electrode P6 are combined into one electrode, so that only one common bit line can be connected, and outside the memory cell 1, the read bit line R_BL and the write bit line W_BL are combined into one common bit line BL, so that
  • the memory cell 1 is connected to an external structure from the original two bit lines (read bit line R_BL and write bit line W_BL) to a common bit line (BL) connected to the external structure, so that The two bit lines (read bit line R_BL and write bit line W_BL) can be combined together in the outer area of the memory array where the current memory cell 1 is located.
  • the arrangement of the two bit lines requires at least two vias to be connected to the top of the silicon, which requires more area. Even if the memory cell is made small, the external circuit is too large. It is impossible to make a high-density memory, which may affect the productization of the memory unit 1 in some embodiments of the present disclosure.
  • some embodiments of the present disclosure merge the read bit line R_BL and the write bit line W_BL into one bit line BL. It only requires one via hole and two bit lines overlap, which improves the storage density.
  • each memory cell in some embodiments of the present disclosure has only 3 signals, including 2 word line signals and 1 bit line signal, which is beneficial to Layout design, especially layout design in small spaces, improves the practicality of the storage unit 1 of some embodiments of the present disclosure.
  • Some embodiments of the present disclosure also provide a storage system 3, as shown in Figures 10a, 10b, and 10c, which may include:
  • each of the amplifiers 4 is an amplifier 4 shared by two adjacent storage arrays; the amplifier 4 is configured to process the storage data read from the storage unit 1 in the storage array 2 that is sensed during the induction phase. Amplification, in the refresh phase, the amplified storage data is written back to the storage node of the storage unit 1.
  • the plurality of memory arrays 2 include: a first memory array 21 and a second memory array 22; each readout bit line R_BL in the first memory array 21 and the A different read bit line R_BL on the second memory array 22 is commonly connected to the same amplifier 4, so that the memory cells 1 connected to the two read bit lines R_BL connected to the same amplifier 4 share the same amplifier 4;
  • the two readout bit lines R_BL connected to the same amplifier 4 are respectively connected to different signal input terminals of the amplifier 4;
  • the write bit lines W_BL corresponding to the two read bit lines R_BL connected to the same amplifier 4 are respectively connected to different signal output terminals of the amplifier 4, and the storage voltage read and amplified by the amplifier 4 is refreshed to Storage is performed in the second transistor TR_W of the memory cell.
  • the first memory array 21 and the second memory array 22 when both the first memory array 21 and the second memory array 22 store n (n is a positive integer) readout bit lines R_BL, then the first memory array 21 and the second memory array 22 n amplifiers 4 can be shared between the arrays 22, wherein the first read bit line R_BL in the first memory array 21 and the first read bit line R_BL in the second memory array 22 can be connected to the same amplifier, The second read bit line R_BL in the first memory array 21 may be connected to the same amplifier 4 as the second read bit line R_BL in the second memory array 22,..., and so on, the first memory array 21 The nth readout bit line R_BL in may be connected to the same amplifier 4 as the nth readout bitline R_BL in the second memory array 22 .
  • each amplifier 4 is configured to amplify the signal of the stored data read by the connected read bit line R_BL.
  • the storage system 3 may further include: a plurality of pre-charging devices; the plurality of pre-charging devices (Pre-chargers) may include a first pre-charging device and a second pre-charging device. device;
  • the write bit line W_BL and the read bit line R_BL corresponding to the first memory array 21 are both connected to the first precharge device;
  • the write bit line W_BL and the read bit line R_BL corresponding to the second memory array 22 are both connected to the second precharge device.
  • the readout bit line R_BL may be precharged first, and Precharge the corresponding read bit line R_BL in the second memory array 22 that shares the same amplifier 4 with the read bit line R_BL, wherein the corresponding read bit line R_BL in the second memory array 22 has a precharge voltage
  • the precharge voltage value for example, the precharge voltage value of the sense bit line R_BL in the first memory array 21 may be VDD, and the precharge voltage value of the sense bit line R_BL in the second memory array 22 may include but is not limited to VDD/2.
  • the readout bit line R_BL may be preliminarily performed. charge, and the corresponding read bit line R_BL in the first memory array 21 that shares the same amplifier 4 with the read bit line R_BL is precharged, wherein the corresponding read bit line R_BL in the first memory array 21 is precharged.
  • the charging voltage serves as a reference voltage for the sense bit line R_BL in the second memory array 22 , and the corresponding sense bit line R_BL precharge voltage value in the first memory array 21 is smaller than the sense bit line in the second memory array 22
  • the precharge voltage value of R_BL for example, the precharge voltage value of the sense bit line R_BL in the second memory array 22 may be VDD, and the precharge voltage value of the sense bit line R_BL in the first memory array 21 may include but Not limited to VDD/2.
  • a start switch 41 may be provided in each amplifier 4. After precharging the read bit line R_BL, the read bit line R_BL to be signal amplified may be used to read the read bit line R_BL. The stored data of the memory cell to be read on the bit line R_BL is read, and the start switch 41 is turned on, so that the voltage on the two read bit lines R_BL is used as a differential signal input to the two signal input terminals of the amplifier 4, through The signal amplifier amplifies the signal on the readout bit line R_BL to be signal amplified.
  • the read transistor TR_R connected to the first transistor TR_R of the memory cell of the data to be read may be controlled before the read bit line R_BL reads the storage data of the memory cell of the data to be read.
  • the output word line R_WL inputs a high voltage
  • the read word line R_WL connected to the first transistor TR_R of the memory cell that does not need to read data inputs a low voltage, so that the first transistor TR_R of the memory cell that does not need to read data is turned off. Interruption, thus solving the current crosstalk and current sharing problems that exist in the traditional 2T0C structure when reading data. That is, the current sharing and crosstalk issues in 2T0C cells can be easily solved by applying low voltage to the read word line R_WL of the unselected row.
  • the amplified signal after amplifying the signal of the read data on the read bit line R_BL, the amplified signal can also be input to the storage of the data to be read through the signal output terminal of the amplifier.
  • the write bit line W_BL connected to unit 1 is used to rewrite the amplified read data into the second transistor TR_W of the memory unit 1 of the data to be read through the write bit line W_BL, so as to achieve the purpose of writing the data to be read.
  • the data stored in the second transistor TR_W of the memory unit 1 for fetching data is refreshed to avoid errors in the stored data due to leakage.
  • the writing of the second transistor TR_W of the memory unit 1 of data to be read is controlled before the data stored in the second transistor TR_W of the memory unit 1 of data to be read is refreshed.
  • the input word line W_WL inputs a high voltage, and controls the second transistor TR_W of the memory cell 1 that does not need to read data.
  • the write word line W_WL inputs a low voltage, so that the second transistor TR_W of the memory cell 1 that does not need to read data is input.
  • the memory array in the memory system may be composed of 2TOC structure memory cells after the electrodes are merged in some embodiments of the present disclosure (as shown in Figure 10a), or may be composed of 2TOC structure memory cells when the electrodes are not merged.
  • the memory cell composition of the 2T0C structure (the overall picture is not drawn here, the structure is similar to Figure 10a, except that the first electrode P1 and the sixth electrode P6 of each memory cell are not merged, you can refer to the corresponding memory array, the partial schematic diagram is as follows As shown in Figure 10b), in addition, the memory array can also be such that the electrodes of each memory cell are not combined, but the bit lines connected to the first electrode and the sixth electrode outside the memory array are combined (no diagram is shown here, For a storage system, refer to Figure 9b and Figure 10a, and use the storage array in Figure 9b to replace the storage array in Figure 10a).
  • the amplifier may be a voltage amplifier or a current amplifier
  • the input terminals of the two differential input signals of the amplifier are respectively connected to two different read bit lines, and the two different read bit lines are respectively from the adjacent memory arrays;
  • one is an input terminal for reading the stored data read by the read bit line
  • the other input terminal is a reference signal terminal for the differential input signal of the amplifier.
  • the amplifier 4 can be a voltage amplifier or a current amplifier, which can be selected according to requirements.
  • Figure 10c is a schematic connection diagram when the amplifier is a current amplifier, where I REF is a reference current. Similar to the example shown in Figure 10b, the reference current can be provided by another memory array.
  • the above three storage arrays can be used in any combination, and there is no limit on the detailed combination scheme and the number of combinations.
  • the second gate of the memory cell in FIGS. 10a and 10b is represented by a capacitor.
  • Some embodiments of the present disclosure provide a data writing method based on the storage array. As shown in Figure 11, the method may include steps S301-S302:
  • the first transistor is a read transistor.
  • the write voltage may be a high voltage or a low voltage
  • the corresponding storage data is "1" or "0”
  • the write word line W_WL is applied to the high voltage (ie, the third gate (the turn-on voltage of pole G3)
  • the fifth electrode P5 and the sixth electrode P6 of the second transistor TR_W are turned on, then after the voltage is written through the write bit line W_BL, the voltage at the fifth electrode P5 terminal and the sixth electrode P6
  • the voltage at the terminal (connected to write bit line W_BL) is the same, which is the write voltage.
  • the method may further include:
  • the write word line W_WL of each unselected row of memory cells 1 in the memory array 2 inputs a voltage different from the turn-on voltage of the third gate G3 of the selected row of memory cells, so that the The second transistor TR_W of the memory cell 1 that does not need to be written with data is turned off.
  • the write word line W_WL connected to the gates of other memory cells 1 connected to the write bit line W_BL applies a voltage different from the turn-on voltage input to the third gate G3 of the memory cell 1 to which data needs to be written, As a result, the second transistor TR_W (write transistor) of the memory cell 1 that needs to be written with data is turned on, while the second transistor TR_W of other memory cells that do not need to be written with data is turned off, ensuring that the write data is only written into the memory unit that needs to be written.
  • Some embodiments of the present disclosure provide a data reading method based on the storage array. As shown in Figure 12, the method may include steps S401-S402:
  • the readout word line connected to the first transistor TR_R of the memory cell 1 of the selected row of memory cells in the memory array 2 that needs to read data inputs the first voltage; wherein, the The first voltage is between a first threshold voltage and a second threshold voltage.
  • the first threshold voltage and the second threshold voltage are respectively the threshold voltages at which the first transistor can be turned on when data "1" and "0" are stored.
  • the first transistor TR_R serves as a read transistor.
  • a voltage can be input to the first gate G1 of the first transistor TR_R so that the first transistor
  • the first electrode P1 and the second electrode P2 of TR_R are turned off, so that based on the voltage (and/or current) of the first electrode P1, it is determined whether the fifth electrode P5 stores high voltage or low voltage, or the stored data. Is it "1" or "0".
  • the first gate G1 of the first transistor TR_R is connected to the read word line R_WL, and the voltage of the first gate G1 (first voltage) can be provided through the read word line R_WL, by It can be seen from the previous discussion that the gate of the first transistor TR_R has a back-gate effect. Therefore, when the stored write voltage is provided to the second gate G2 (auxiliary gate) of the first transistor TR_R through the fifth electrode P5, it will cause The threshold voltage of the gate of the first transistor TR_R is shifted, and the shift is also different depending on the data written on the fifth electrode P5 (such as "1" or "0").
  • the first transistor TR_R When a voltage is applied to the first gate G1, it can be implemented according to the voltage of the second gate G2 to ensure that the first electrode P1 and the second electrode P2 of the first transistor TR_R are turned off, so that the first electrode P1 reads out of the stored data.
  • the voltage applied to the first gate G1 of the first transistor TR_R may be between a low voltage and a high voltage (“0”-“1”) to supplement the voltage of the auxiliary gate. , causing the first transistor TR_R to turn on.
  • a precharge phase is also included before the data read operation phase, and the method may further include:
  • the sense bit line or the common bit line is precharged such that the voltage on the sense bit line is higher than the voltage provided by the reference signal terminal in the differential input signal input terminal of the amplifier.
  • the readout bit line R_BL connected to the first electrode P1 may be precharged with a voltage (ie, the second voltage) when initially reading data, and the precharge voltage may be a voltage smaller than the memory device power supply.
  • the voltage of VDD may, for example, include but is not limited to VDD/4, VDD/3, VDD/2, etc. The detailed values can be defined according to different application scenarios and requirements.
  • the reference voltage may include, but is not limited to, 0V.
  • the change value is greater than or equal to the preset first voltage change threshold
  • the voltage stored at the fifth electrode terminal of the second transistor of the memory cell to be read is the first storage voltage value, and the first storage voltage value is read.
  • the first voltage change threshold can be defined according to different needs or accuracy requirements, and is not limited in detail here.
  • data “1” is previously written to the fifth electrode P5, it can be measured between the reference voltage Vrefn (such as 0 potential or ground) and the selected readout bit line R_BL Significant change in conductance (on-current) and it can be sensed at the selected sense bit line R_BL. Therefore, when it is detected that the voltage of the first electrode P1 of the first transistor TR_R changes, and the change value is greater than or equal to the preset first voltage change threshold, it can be determined that the stored writing voltage is a high voltage, that is, writing The input data is "1".
  • Vrefn such as 0 potential or ground
  • the second voltage stored at the fifth electrode P5 of the transistor TR_W is a second stored voltage value, and the second stored voltage value is read; the second voltage change threshold is smaller than the first voltage change threshold.
  • the second voltage change threshold can be defined according to different needs or accuracy requirements, and is not limited in detail here.
  • the method may further include:
  • the read word line of the memory cell that does not need to read data and the read word line of the first transistor of the memory cell that needs to read data are different word lines.
  • Tr_w write transistor
  • Tr_r read transistor
  • It requires 4 signals, namely the write-WL (write word line) signal and the write-BL (write bit line) signal required for the write operation.
  • the read operation requires the read-WL (read word line) signal and the read- BL (read bit line) signal.
  • the 2T0C structure in some embodiments of the present disclosure does not need to be too large between Tr_w and Tr_r due to the non-destructive read characteristics. of capacitance.
  • the read word line R_WL of the first transistor TR_R of the memory cell 1 that does not need to read data in the memory array 2 to the first transistor TR_R of the memory cell 1 that needs to read data.
  • the input voltage of the read word line R_WL is different, so that the first transistor TR_R of the memory cell 1 that does not need to read data is turned off, thus solving the current crosstalk and current sharing that exist in the traditional 2T0C structure when reading data. question.
  • current sharing and crosstalk issues in 2T0C cells can be easily solved by applying low voltage to the read word line R_WL of the unselected row.
  • the method may further include: performing data refresh in the refresh phase;
  • Refreshing data during the refresh stage may include: sensing the storage data in the storage unit, amplifying the storage data through the amplifier, and writing the amplified storage data back into the storage node of the storage unit.
  • the write word line W_WL in the memory array inputs the The turn-on voltage of the third gate G3 of the memory cell;
  • the read voltage value is input to the write bit line W_BL corresponding to the memory cell 1 to which data needs to be written, so as to refresh the voltage value stored in the second transistor TR_W.
  • the write voltage in order to avoid leakage causing the written voltage to change, can be rewritten into the write transistor in time after each readout to save the write voltage, so as to realize storage Timely refresh of voltage.
  • the method may further include:
  • the input voltage of the write word line W_WL of the memory cell 1 that does not need to be refreshed in the memory array 2 makes the memory cell 1 that does not need to be written with data input voltage.
  • the second transistor TR_W is turned off;
  • the writing word lines connected to the memory cells that need to be refreshed and the writing word lines of the memory cells that do not need to be refreshed to store data are different word lines.
  • the write bit line needs to be controlled.
  • the write word line W_WL connected to the gates of other memory cells 1 connected to W_BL applies a voltage different from the input voltage of the third gate G3 of the memory cell 1 to which data needs to be written, thereby enabling the storage of data to be written.
  • the second transistor TR_W (write transistor) of unit 1 is turned on, while the second transistors TR_W of other memory cells that do not need to be written with data are turned off, ensuring that write data is only written into the memory unit 1 that needs to be written with data.
  • Some embodiments of the present disclosure provide a data writing method. Based on the storage system, as shown in Figure 13, the method may include steps S501-S502:
  • the data to be written may be "1" or "0”
  • the write word line W_WL is applied to a high voltage (ie, the turn-on voltage of the third gate G3), and the second The fifth electrode P5 and the sixth electrode P6 of the transistor TR_W are turned on.
  • the voltage at the end of the fifth electrode P5 is equal to the voltage at the end of the sixth electrode P6 (connected to the write bit line W_BL).
  • the voltages are the same, both are the write voltage.
  • the method may further include:
  • the write word line W_WL of the memory cell 1 that does not need to write data inputs a voltage different from the conduction voltage of the third gate G3, so that the write data does not need to be written.
  • the second transistor TR_W of the memory cell 1 is turned off.
  • the write word line W_WL connected to the gates of other memory cells 1 connected to the write bit line W_BL applies a voltage different from the turn-on voltage input to the third gate G3 of the memory cell 1 to which data needs to be written, As a result, the second transistor TR_W (write transistor) of the memory cell 1 that needs to be written with data is turned on, while the second transistor TR_W of other memory cells that do not need to be written with data is turned off, ensuring that the write data is only written into the memory unit that needs to be written.
  • Some embodiments of the present disclosure provide a data reading method. Based on the storage system, as shown in Figure 14, the method may include steps S601-S605:
  • the read word line R_WL corresponding to the first transistor TR_R of the memory cell 1 whose data needs to be read inputs a third voltage; the third voltage is located at the first threshold voltage. and the second threshold voltage; the first threshold voltage is the threshold voltage that causes the read transistor to turn on when the storage node stores data as 1; the second threshold voltage is the threshold voltage that causes the read transistor to turn on when the storage node stores data as 0. The threshold voltage at which the transistor turns on.
  • the first transistor TR_R serves as a read transistor.
  • a voltage can be input to the first gate G1 of the first transistor TR_R so that the first transistor
  • the first electrode P1 and the second electrode P2 of TR_R are turned on, so that based on the voltage (and/or current) of the first electrode P1, it is determined whether the fifth electrode P5 stores high voltage or low voltage, or whether the stored data Is it "1" or "0".
  • the first gate G1 of the first transistor TR_R is connected to the read word line R_WL, and the voltage of the first gate G1 (third voltage) can be provided through the read word line R_WL. It can be seen from the previous discussion that the gate of the first transistor TR_R has a back-gate effect. Therefore, when the stored write voltage is provided to the second gate G2 (auxiliary gate) of the first transistor TR_R through the fifth electrode P5, it will cause The threshold voltage of the gate of the first transistor TR_R is shifted, and the shift is also different according to the different data (such as 1 or 0) written by the fifth electrode P5.
  • the threshold voltage of the first gate of the first transistor TR_R is When a voltage is applied to the electrode G1, it can be implemented according to the voltage of the second gate G2 to ensure that the first electrode P1 and the second electrode P2 of the first transistor TR_R are turned off, so that the first electrode P1 reads the stored Voltage.
  • the voltage applied to the first gate G1 of the first transistor TR_R may be between a low voltage and a high voltage (“0”-“1”) to supplement the voltage of the auxiliary gate. , causing the first transistor TR_R to turn on.
  • the readout bit line R_BL may be precharged to obtain The fourth voltage, the voltage value of the fourth voltage may be VDD.
  • the corresponding readout bit line R_BL in the second memory array 22 that shares the same amplifier 4 as the precharged readout bitline R_BL in the first memory array 21 is precharged to obtain The fifth voltage; the precharge voltage of the corresponding sense bit line R_BL in the second memory array 22 serves as the reference voltage of the sense bit line R_BL in the first memory array 21.
  • the voltage value of the fifth voltage may include but not Limited to VDD/2.
  • the precharged fourth voltage when the data stored in the second transistor TR_W is 0, the precharged fourth voltage will not change after reading the data.
  • the precharged fourth voltage When the data stored in the second transistor TR_W is 1 , after reading the data, the precharged fourth voltage will first decrease. When the fourth voltage no longer decreases, the voltage will reach a stable state. It is determined that the data reading is completed. At this time, the start switch of the amplifier 4 can be turned on. When it is turned on, the voltages on the current two read bit lines are input to the amplifier 4, and the reduced and stabilized fourth voltage (as read data) is amplified by the amplifier 4.
  • the read transistor TR_R connected to the first transistor TR_R of the memory cell of the data to be read may be controlled before the read bit line R_BL reads the storage data of the memory cell of the data to be read.
  • the output word line R_WL inputs a high voltage
  • the read word line R_WL connected to the first transistor TR_R of the memory cell that does not need to read data inputs a low voltage, so that the first transistor TR_R of the memory cell that does not need to read data is turned off. Interruption, thus solving the current crosstalk and current sharing problems that exist in the traditional 2T0C structure when reading data. That is, the current sharing and crosstalk problems in the 2T0C circuit of some embodiments of the present disclosure can be easily solved by applying a low voltage to the read word line R_WL of the unselected row.
  • S605 Read the amplified voltage through the first signal output terminal of the amplifier 4 as the storage voltage of the memory cell in the first memory array 21 that needs to read data.
  • the method may further include:
  • the turn-on voltage of the third gate G3 of the second transistor TR_W is input to the write word line corresponding to the memory cell whose data needs to be read in the first memory array 21;
  • the read amplified voltage is input to the write bit line corresponding to the second transistor TR_W of the memory cell that needs to read data, so as to store the voltage value of the second transistor TR_W of the memory cell that needs to read data. Refresh.
  • the amplified signal after amplifying the signal of the read data on the read bit line R_BL, the amplified signal can also be input to the storage of the data to be read through the signal output terminal of the amplifier.
  • the write bit line W_BL connected to unit 1 is used to rewrite the amplified read data into the second transistor TR_W of the memory unit 1 of the data to be read through the write bit line W_BL, so as to achieve the purpose of writing the data to be read.
  • the data stored in the second transistor TR_W of the memory unit 1 for fetching data is refreshed to avoid errors in the stored data due to leakage.
  • the method may further include:
  • the write word line W_WL input of the memory cell that does not need to refresh data in the first memory array 21 is connected to the input of the write word line W_WL.
  • the turn-on voltage of the third gate G3 of the second transistor TR_W is a different voltage, so that the second transistor TR_W of the memory unit 1 that does not need to write data is turned off.
  • the writing of the second transistor TR_W of the memory unit 1 of data to be read is controlled before the data stored in the second transistor TR_W of the memory unit 1 of data to be read is refreshed.
  • the input word line W_WL inputs a high voltage, and controls the second transistor TR_W of the memory cell 1 that does not need to read data.
  • the write word line W_WL inputs a low voltage, so that the second transistor TR_W of the memory cell 1 that does not need to read data is input.
  • control chip for a storage array.
  • the control chip is configured to perform a data writing method based on the storage array and a data reading method based on the storage array.
  • any of the aforementioned memory unit, memory array and data writing and data reading method embodiments thereof are applicable to the control chip embodiment of the memory array, and are not used here. Let’s go over them one by one.
  • Some embodiments of the present disclosure provide a control chip of a storage system, and the control chip is configured to execute a data writing method based on the storage array.
  • Some embodiments of the present disclosure provide a control chip of a storage system, and the control chip is configured to execute a data reading method based on the storage array.
  • any of the aforementioned memory unit, memory array and data writing and data reading method embodiments thereof are applicable to the control chip embodiment of the storage system, and are not used here. Let’s go over them one by one.
  • Some embodiments of the present disclosure provide a memory, including the storage array.
  • any of the aforementioned memory unit, memory array and data writing and data reading method embodiments thereof are applicable to the control chip embodiment of the storage system, and are not used here. Let’s go over them one by one.
  • Some embodiments of the present disclosure provide an electronic device including the memory.
  • any of the aforementioned memory unit, memory array and data writing and data reading method embodiments thereof are applicable to the control chip embodiment of the storage system, and are not used here. Let’s go over them one by one.
  • computer storage media includes volatile and nonvolatile media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. removable, removable and non-removable media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disk (DVD) or other optical disk storage, magnetic cassettes, tapes, disk storage or other magnetic storage devices, or may Any other medium used to store the desired information and that can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

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  • Read Only Memory (AREA)

Abstract

一种存储单元、阵列读写方法、控制芯片、存储器和电子设备，涉及半导体技术领域。该存储单元包括：第一晶体管（TR_R ）和第二晶体管（TR_W），第一晶体管（TR_R）包括第一电极（P1）、第二电极（P2）、第三电极（P3）和第四电极（P4）；第三电极（P3）为第一栅极（G1），第四电极（P4）为第二栅极（G2）；第二晶体管（TR_W）包括第五电极（P5）、第六电极（P6）和第七电极（P7）；第七电极（P7）为第三栅极（G3）；第一电极（P1）与读出位线（R_BL）相连，第二电极（P2）连接参考信号，第一栅极（G1）与读出字线（R_WL）相连，第二栅极（G2）与第五电极（P5）相连；第六电极（P6）与写入位线（W_BL）相连，第三栅极（G3）与写入字线（W_WL）相连。该存储单元至少可以降低已有技术存储器功耗较高的问题。

Description

存储单元、阵列读写方法、控制芯片、存储器和电子设备 技术领域
本公开一些实施例涉及半导体技术领域，尤指一种存储单元、阵列读写方法、控制芯片、存储器和电子设备。
背景技术
传统的用于动态随机存取存储器(DRAM)的传统单元包括一个晶体管和一个电容器(如图1所示，其中SN为Storage Node存储节点，BL为Bit-line位线，WL为Word-line字线，C为电容器，G为晶体管的栅极，S为晶体管的源极，D为晶体管的漏极)，然而由于沟道间的泄漏，存储的数据需要频繁刷新，因此它显著地增加了功耗。
发明概述
以下是对本文详细描述的主题的概述，本概述并非是为了限制保护范围。
本公开一些实施例提供了一种存储单元、阵列读写方法、控制芯片、存储器和电子设备，具有非常低的漏电，能够解决当前存储单元存在的刷新频率高和功耗高的问题，提升读写操作的性能，有利于外围器件的设置，为解决串扰问题提供技术基础。
一些实施方式中提供一种存储单元，包括：
第一晶体管，设置为读晶体管；以及，
第二晶体管，设置为写晶体管；
其中，所述第一晶体管包括第一电极、第二电极、第三电极和第四电极；所述第三电极为第一栅极，所述第四电极为第二栅极；
所述第二晶体管包括第五电极、第六电极和第七电极；所述第七电极为第三栅极；
所述第一电极设置为与读出位线相连，所述第二电极设置为参考电压端， 用于连接参考信号，所述第一栅极设置为与读出字线相连，所述第二栅极设置为与所述第五电极相连；
所述第六电极设置为与写入位线相连，所述第三栅极设置为与写入字线相连。
一些实施方式中，一种存储阵列，包括：
写入字线；
读出字线；
写入位线；
读出位线；以及，
多个存储单元；
其中，所述存储单元包括：第一晶体管和第二晶体管；所述第一晶体管包括第一电极、第二电极、第三电极和第四电极；所述第三电极为第一栅极，所述第四电极为第二栅极；
所述第二晶体管包括第五电极、第六电极和第七电极；所述第七电极为第三栅极；
所述第一电极与所述读出位线相连，所述第二电极可以设置为参考电压端，用于连接参考信号，所述第一栅极与所述读出字线相连，所述第二栅极与所述第五电极相连；
所述第六电极与所述写入位线相连，所述第三栅极与所述写入字线相连。
一些实施方式中，提供一种存储阵列，包括：
写入字线；
读出字线；
共用位线；以及，
多个存储单元；
其中，所述存储单元包括：第一晶体管和第二晶体管；所述第一晶体管包括第一电极、第二电极、第三电极和第四电极；所述第三电极为第一栅极，所述第四电极为第二栅极；
所述第二晶体管包括第五电极、第六电极和第七电极；所述第七电极为第三栅极；
所述第一电极与所述第六电极共同与所述共用位线相连，所述第二电极可以设置为参考电压端，用于连接参考信号，所述第一栅极与所述读出字线相连，所述第二栅极与所述第五电极相连；
所述第三栅极与所述写入字线相连。
一些实施方式中，提供一种存储系统，包括：
多个上述的存储阵列；以及，
多个放大器；
其中，每个所述放大器为相邻两个所述存储阵列共用的放大器；所述放大器设置为对感应阶段感应的所述存储阵列中的存储单元中读取的存储数据进行放大，在刷新阶段，将放大后的存储数据回写到所述存储单元的存储节点。
一些实施方式中，提供一种数据写入方法，基于上述存储阵列，所述方法包括：
在所述存储阵列中需写入数据的存储单元，通过所述存储单元的写入字线输入到所述存储单元的第二晶体管的栅极电压，以使得作为写晶体管的所述第二晶体管导通；
通过所述存储单元的写入位线或所述共用位线向导通的第二晶体管输入写入电压，使得所述写入电压存储在与所述第二晶体管连接的第一晶体管的第二栅极中，其中，所述第二栅极配置为作为所述存储单元的存储节点，所述第一晶体管为读晶体管。
一些实施方式中，提供一种数据读取方法，基于上述存储阵列，所述方法包括：
在数据读操作阶段，在所述存储阵列中需读取数据的存储单元的第一晶体管连接的读出字线输入第一电压；其中，所述第一电压位于第一阈值电压和第二阈值电压之间，所述第一阈值电压为所述存储单元存储数据“1”时对所述第一晶体管的开启阈值电压；所述第二阈值电压为所述存储单元存储数 据“0”时对应的所述第一晶体管的开启阈值电压；
当检测到所述第一晶体管连接的读出位线的电压变化且变化数值大于或等于预设的第一电压变化阈值时确定所述存储单元的读出的数据为1，当所述第一晶体管的连接的读出位线的电压无变化或者变化数值小于或等于预设的第二电压变化阈值时，则确定所述存储单元的读出数据为0。
一些实施方式中，提供了一种存储阵列的控制芯片，所述控制芯片设置为执行上述数据写入方法。
一些实施方式中，提供了一种存储阵列的控制芯片，所述控制芯片设置为执行上述数据读取方法。
一些实施方式中，提供了一种存储器，包括所述的存储阵列。
一些实施方式中，提供了一种电子设备，包括所述的存储器。
本公开一些实施例的有益效果包括：读晶体管包括第一栅极和第二栅极，并且第二栅极与写晶体管的一个电极相连，写晶体管将写入电压存储在该电极内，省去了电容器，从而解决了对大电容的需求问题，相应地降低了刷新频率和功耗；并且由于读晶体管的栅极具有背栅效应，通过设置两个栅极，有利于第一栅极根据第二栅极(可以视为辅助栅极)的电压大小调整施加的电压，确保第一晶体管源极和漏极之间的导通，提升了读写操作的性能,有利于外围器件的设置，为解决串扰问题提供了技术基础。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为现有技术中1T1C结构的存储单元示意图；
图2为现有技术中传统的2T0C结构的存储单元示意图；
图3为本公开一些实施例的2T0C结构的存储单元示意图；
图4为相关技术中晶体管栅极由于背栅效应引起的阈值电压偏移示意图；
图5为本公开一些实施例的第一电极和第六电极合并为一个电极时的2T0C结构的存储单元示意图；
图6为本公开一些实施例的存储单元的数据写入方法流程图；
图7为本公开一些实施例的存储单元的数据读取方法流程图；
图8为本公开一些实施例的2T0C结构的存储单元组成的存储阵列结构示意图；
图9a为本公开一些实施例的第一电极和第六电极合并为一个电极时的2T0C结构的存储单元组成的存储阵列结构示意图；
图9b为本公开一些实施例的第一电极和第六电极未合并为一个电极，所连接的读出位线和写入位线在存储阵列外部合时的存储阵列结构示意图；
图10a为本公开一些实施例的一种存储系统结构示意图；
图10b为本公开一些实施例的另一种存储系统结构的局部放大示意图；
图10c为本公开一些实施例的放大器为电流放大器时的连接示意图；
图11为本公开一些实施例的存储阵列的数据写入方法流程图；
图12为本公开一些实施例的存储阵列的数据读取方法流程图；
图13为本公开一些实施例的存储系统的数据写入方法流程图；
图14为本公开一些实施例的存储系统的数据读取方法流程图。
本公开一些实施例目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
详述
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说显而易见的是，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的 任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的独特的发明方案。任何实施例的任何特征或元件也可以与来自其它发明方案的特征或元件组合，以形成另一个由权利要求限定的独特的发明方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
此外，在描述具有代表性的实施例时，说明书可能已经将方法和/或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法和/或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开一些实施例的精神和范围内。
本公开一些实施例提供了一种新的逻辑电路以及相关的结构设计，工艺流程等方案。
所述逻辑电路为2T0C的基本框架下，读晶体管为双栅结构，其中一个栅极为控制栅极，另一个栅极用于存储电容的存储节点。同时在向写晶体管写入数据之前，给读晶体管一个合适的电压，使得该读晶体管在存储电容节点存入数据“1”时开启，在输入数据“0”时依然保持关闭。
上述方案读操作是非破坏性的，这样，可以使用较低漏电流的写晶体管而必须要求存储节点存储有较高的电容以维持数据的有效性。
一些实施方式中，所述写晶体管可以为金属氧化物半导体场效应管。
以下将通过不同的实施例详细说明上述发明。
本公开一些实施例提供了一种存储单元1，如图3所示，可以包括：
第一晶体管TR_R，设置为读晶体管；以及，
第二晶体管TR_W，设置为写晶体管；
其中，所述第一晶体管TR_R包括第一电极P1、第二电极P2、第三电极P3和第四电极P4；所述第三电极P3为第一栅极G1，所述第四电极P4为第二栅极G2(简称背栅)；
第一电极P1、第二电极P2其中之一为源极，另一为漏极。
所述第二晶体管TR_W包括第五电极P5、第六电极P6和第七电极P7；所述第七电极P7为第三栅极G3；
第五电极P5、第六电极P6其中之一为源极，另一为漏极。
所述第一电极P1设置为与读出位线R_BL相连，所述第二电极P2可以设置为输入参考电压Vrefn，用于连接参考信号；所述第一栅极G1设置为与读出字线R_WL相连，所述第二栅极G2设置为与所述第五电极P5相连；
所述第六电极P6设置为与写入位线W_BL相连，所述第三栅极G3设置为与写入字线W_WL相连。
在本公开的示例性实施例中，存储单元1也是2T0C结构，与图2所示(其中，Tr_w为写晶体管，Tr_r为读晶体管)的传统的2T0C结构相比，上述方案读操作是非破坏性的，这样，可以使用较低漏电流的写晶体管而必须要求存储节点存储有较高的电容以维持数据的有效性。另外，通过背栅可以实现电容存储，通过低漏电的写晶体管可以同时降低对存储单元的刷新频率和功耗。
在本公开的示例性实施例中，第一晶体管TR_R，包含有两个栅极，即，增加了一个辅助栅极(即第二栅极，也称背栅)，第二栅极与写晶体管(即第二晶体管TR_W)的第五电极P5相连，由第五电极P5提供电压，并且第五电极P5提供的电压设置为存储写晶体管的写入电压。
在本公开的示例性实施例中，所述第一栅极G1和第二栅极G2为相互独立的栅极，且所述第一栅极G1用于控制所述读晶体管TR_R的读操作；所述第二栅极G2配置为作为所述存储单元的存储节点，通过所述写晶体管 TR_W在所述存储节点写入数据。
由于晶体管的栅极具有背栅效应，随着写晶体管向第五电极P5写入电压，则读晶体管的辅助栅极获取相应的写入电压，并且根据辅助栅极写入电压的不同(例如，高电压或低电压)，读晶体管的栅极将呈现出不同的阈值电压(V TH)。如图4所示，对于N型读晶体管TR_R来说，当辅助栅极的电压为高电压(如，写入数据为“1”)时，V TH将负移；当辅助栅极的电压为低电压(如，写入数据为“0”)时，V TH将正移。
在本公开的示例性实施例中，读晶体管上的第一栅极给定一个合适的电压后，可以保证读晶体管不开启；在辅助栅极写入数据“0”时为低电压，读晶体管阈值电压正偏，该读晶体管更无法开启，因此，读晶体管BL(位线)上的电压没有大的变化，考虑漏电时可能有微小的变化，但变化值小于预设的阈值。在写入数据“1”时，对应高电压给辅助栅极，辅助栅极使得读晶体管的阈值电压负偏，且读晶体管开启。此时读晶体管的BL受高电压的影响，电压发生变化，且变化值超过阈值。SA电路(数据读取电路)与读出位线连接，靠分析读出位线上的电压变化量确定读取的数据是1还是0；读0和1过程中，读晶体管的控制栅极(第一栅极)上的电压是不变的，靠辅助栅极上被写入的电压改变读晶体管的阈值电压使得读晶体管自动开启或保持关闭。
在本公开的一些示例性实施例中，所述第一晶体管TR_R为N型晶体管；以及，
所述第二晶体管TR_W为N型晶体管或P型晶体管。
在本公开的示例性实施例中，第一晶体管TR_R和第二晶体管TR_W可以均为N型晶体管，或者均为P型晶体管，或者任意一个为N型晶体管，另一个为P型晶体管，在此对于第一晶体管TR_R和第二晶体管TR_W的选型不做限定，可以根据需求自行定义。
在本公开的示例性实施例中，第一电极P1、第二电极P2、第五电极P5、第六电极P6可以根据所选择的晶体管的类型进行设置，在此对于第一电极P1、第二电极P2、第五电极P5、第六电极P6为漏极或源极不做限定，可以根据不同的场景和需求自行定义。
在本公开的示例性实施例中，如图5所示，在逻辑电路中所述第一电极P1和所述第六电极P6共用一个电极，配置为与不同的位线连接或与同一条位线连接。
在本公开的示例性实施例中，所述不同的位线为所述读出位线和写入位线；所述同一条位线同时作为所述读出位线和写入位线。
在本公开的示例性实施例中，对于存储结构布局设计，总是希望减少BL(位线)和WL(字线)的数量，特别是位线BL，以实现更高的存储密度。
一些实施例中，在版图设计中，所述第一电极P1和所述第六电极P6连接的BL在存储阵列区域共用一根线。
一些实施例中，在版图设计中，所述第一电极P1和所述第六电极P6连接的BL在存储阵列区域可以是两根线，但是在外围区域为一根线。其中，在array(阵列)区域或外围区域设置有过孔，所述过孔连接所述两根线。
在本公开的示例性实施例中，与传统的2T0C结构相比，本公开一些实施例方案中的每个存储单元只有3个信号，包括2个字线信号和1个位线信号，有利于版图设计，特别是狭小空间的版图设计，提高了本公开一些实施例的存储单元1的实用性。
在本公开的示例性实施例中，下面对本公开一些实施例方案的存储单元的数据写入和读取方法进行详细介绍。
在本公开的示例性实施例中，如图6所示，存储单元的数据写入方法可以包括步骤S101-S102：
S101、通过写入字线W_WL向存储单元1的第二晶体管TR_W的第三栅极G3输入导通电压；
S102、通过写入位线W_BL输入待写入电压，并将写入电压保存在第一晶体管TR_R的栅极。
在本公开的示例性实施例中，该待写入电压可以对应存储数据“1”或“0”的电压，写入字线W_WL被施加到第二晶体管的导通电压，第二晶体管TR_W的第五电极P5和第六电极P6之间导通，则通过写入位线W_BL写入电压后，第五电极P5端的电压与第六电极P6(与写入位线W_BL连接)端 的电压相同，均为该写入电压。
在本公开的示例性实施例中，所述方法还可以包括：
在无需写入数据的存储单元的写入字线W_WL输入与所述第三栅极G3的导通电压不同的电压，以使得所述无需写入数据的存储单元1的第二晶体管TR_W关断。
在本公开的示例性实施例中，对于连接同一写入位线W_BL的多个存储单元1，当任意一个存储单元1需要通过该写入位线W_BL写入数据时，需要控制该写入位线W_BL上连接的其它存储单元1的栅极所连接的写入字线W_WL施加一个与需要写入数据的存储单元1的第三栅极G3输入的导通电压不同的电压，从而使得需要写入数据的存储单元1的第二晶体管TR_W(写晶体管)导通，而其他的无需写入数据的存储单元的第二晶体管TR_W关断，确保了写入数据仅写入该需要写入数据的存储单元。
在本公开的示例性实施例中，如图7所示，存储单元的数据读取方法可以包括步骤S201-S204：
S201、在存储单元的第一晶体管TR_R对应的读出字线输入第一电压；所述第一电压处于第一阈值电压和第二阈值电压之间，该第一阈值电压和第二阈值电压分别为存数据“1”和“0”时第一晶体管可以开启的阈值电压。
在本公开的示例性实施例中，第一晶体管TR_R作为读晶体管，在需要读取背栅存储的电压或数据信号时，可以对第一晶体管TR_R的第一栅极G1输入一个电压使得第一晶体管TR_R的第一电极P1和第二电极P2关断，从而根据读出位线上信号的变化量来判断栅极存储的为高电压还是低电压。如果变化量超过阈值，则读出的数据为“1”，如果无变化时读出的数据为“0”。
在本公开的示例性实施例中，第一晶体管TR_R的第一栅极G1与读出字线R_WL相连，可以通过读出字线R_WL提供第一栅极G1的电压，通过前面的论述可知，第一晶体管TR_R的栅极存在背栅效应，因此，通过第五电极P5对第一晶体管TR_R的第二栅极G2(辅助栅极)提供存储的写入电压时，会使得第一晶体管TR_R的栅极的阈值电压发生偏移，而且根据第五电极P5所写入的数据的不同(如“1”或“0”)，偏移也不同，因此，对 第一晶体管TR_R的第一栅极G1施加电压时可以根据第二栅极G2的电压大小来实施，以确保第一晶体管TR_R的第一电极P1和第二电极P2之间关断，从而使得第一电极P1读出所存储的电压。
在本公开的示例性实施例中，对第一晶体管TR_R的第一栅极G1施加的电压可以位于第一阈值电压和第二阈值电压之间，以补充辅助栅极的电压，使得第一晶体管TR_R关断。所述第一阈值电压为存储单元存储数据“1”时对所述第一晶体管的启动阈值电压；所述第二阈值电压为存储单元存储数据“0”时对所述第一晶体管的启动阈值电压。
S202、在所述第一晶体管TR_R的第一电极P1输入第二电压，并在第一晶体管TR_R的第二电极P2输入参考电压Vrefn。
在本公开的示例性实施例中，第一电极P 1连接的读出位线R_BL在初始读取数据时可以预充一个电压(即该第二电压)，预充电压可以是一个小于存储器件电源电压VDD的电压，例如，可以包括但不限于VDD/4、VDD/3以及VDD/2等，详细数值可以根据不同的应用场景和需求自行定义。
在本公开的示例性实施例中，该参考电压Vrefn可以包括但不限于0V。
S203、当检测到所述第一晶体管TR_R的第一电极P1的电压发生变化，且变化数值大于或等于预设的第一电压变化阈值时，确认所述存储阵列中需读取数据的存储单元的第二晶体管TR_W的第五电极P5端储存的电压为第一存储电压值，并读取所述第一存储电压值对应的存储数据。
在本公开的示例性实施例中，该第一电压变化阈值可以根据不同的需求或精度要求自行定义，在此不做详细限制。
在本公开的示例性实施例中，如果之前将数据“1”写入第五电极P5对应的栅极，则可以在Vrefn和选定的读出位线R_BL之间测量显著的电导变化量(导通电流)，并且可以在选定的读出位线R_BL处感测到它。因此，当检测到所述第一晶体管TR_R的第一电极P1的电压发生变化，且变化数值大于或等于预设的第一电压变化阈值时，可以确定存储的写入电压为高电压，即写入数据为“1”。
S204、当检测到所述第一晶体管TR_R的第一电极P1的电压未发生变 化，或者变化数值小于或等于预设的第二电压变化阈值时，确认所述第二晶体管TR_W的第五电极P5端储存的电压为第二存储电压值，并读取所述第二存储电压值；所述第二电压变化阈值小于所述第一电压变化阈值。
在本公开的示例性实施例中，该第二电压变化阈值可以根据不同的需求或精度要求自行定义，在此不做详细限制。
在本公开的示例性实施例中，如果之前将数据“0”写入第五电极P5，则不会在Vrefn和选定的读出位线R_BL之间感测到电导的变化。因此，当检测到所述第一晶体管TR_R的第一电极P1的电压未发生变化，或者变化数值小于或等于预设的第二电压变化阈值时，可以确定存储的写入电压为低电压，即写入数据为“0”。
在本公开的示例性实施例中，所述方法还可以包括：
在对所述第二晶体管存储的电压值进行读取过程中，在所述存储阵列中无需读取数据的存储单元的读出字线输入与需读取数据的存储单元的第一晶体管TR_R的读出字线输入电压不同的电压，以使得所述无需读取数据的存储单元的第一晶体管关断。
已知传统的2T0C单元结构(如图2所示)的数据写入和数据读取也是分开的，分别用两个晶体管Tr_w(写晶体管)和Tr_r(读晶体管)来实现。它需要4个信号，分别为写操作需要的W-WL(写入字线)信号和W-BL(写入位线)信号，读操作需要R-WL(读取字线)信号和R-BL(读出位线)信号，与传统的1T1C结构的DRAM单元相比，本公开一些实施例中的2T0C结构由于非破坏性的读取特性，在Tr_w和Tr_r之间也不需要太大的电容。然而，在传统2T0C结构的存储阵列中，由于每个2T0C存储单元所连接的R-WLs(读取字线)和R-BLs(读出位线)上连接的全部2T0C存储单元之间存在串扰或均流问题，执行读操作时是一个挑战，DRAM界仍在努力解决这个问题。
在本公开的示例性实施例中，通过将存储阵列中无需读取数据的存储单元的第一晶体管TR_R的读出字线输入与需读取数据的存储单元的第一晶体管TR_R的读出字线输入电压不同的电压，实现了仅保持需读取数据的存储单元的第一晶体管TR_R的导通，而无需读取数据的存储单元的第一晶体管 TR_R关断，从而解决了传统的2T0C结构在读取数据时存在的电流串扰和均流问题。例如，2T0C电池中的电流共享和串扰问题可以通过对未选择行的读出字线R_WL施加低电压来轻松解决。
在本公开的示例性实施例中，在所述第一晶体管TR_R读出所述第一存储电压值对应的数据或所述第二存储电压值对应的数据以后，所述方法还可以包括：
在所述存储阵列中的写入字线W_WL输入所述存储单元的第三栅极G3的导通电压；
将读取的电压值输入需写入数据的存储单元对应的写入位线W_BL，以对所述第二晶体管TR_W存储的电压值进行刷新。
在本公开的示例性实施例中，为了避免泄露使得写入的电压发生变化，可以在每次读取出写入电压之后及时将该写入电压重新写入写晶体管进行保存，以实现对存储电压的及时刷新。
在本公开的示例性实施例中，所述方法还可以包括：
在对所述第二晶体管TR_W存储的电压值进行刷新过程中，在所述存储阵列中无需刷新数据的存储单元的写入字线输入与所述第三栅极G3的导通电压不同的电压，以使得所述无需写入数据的存储单元1的第二晶体管TR_W关断。
在本公开的示例性实施例中，对于连接同一写入位线的多个存储单元1，当任意一个存储单元1需要通过该写入位线W_BL写入数据时，需要控制该写入位线W_BL上连接的其它存储单元1的栅极所连接的写入字线W_WL施加一个与需要写入数据的存储单元1的第三栅极G3输入电压不同的电压，从而使得需要写入数据的存储单元1的第二晶体管TR_W(写晶体管)导通，而其他的无需写入数据的存储单元的第二晶体管TR_W关断，确保了写入数据仅写入该需要写入数据的存储单元1。
本公开一些实施例还提供了一种存储阵列2，如图8所示，可以包括：
写入字线W_WL；
读出字线R_WL；
写入位线W_BL；
读出位线R_BL；以及，
多个所述的存储单元1；
其中，所述的存储单元1包括：第一晶体管TR_R和第二晶体管TR_W；所述第一晶体管TR_R包括第一电极P1、第二电极P2、第三电极P3和第四电极P4；所述第三电极P3为第一栅极G1，所述第四电极P4为第二栅极G2；
所述第二晶体管TR_W包括第五电极P5、第六电极P6和第七电极P7；所述第七电极P7为第三栅极G3；
所述第一电极P1与所述读出位线R_BL相连，所述第二电极P2设置为输入参考电压Vrefn，所述第一栅极G1与所述读出字线R_WL相连，所述第二栅极G2与所述第五电极P5相连；
所述第六电极P6与所述写入位线W_BL相连，所述第三栅极G3与所述写入字线W_WL相连。
在本公开的示例性实施例中，写入字线W_WL和读出字线R_WL可以包括多行，例如，可以包括：W_WL_1、W_WL_2、W_WL_3、……、W_WL_m以及R_WL_1、R_WL_2、R_WL_3、……、R_WL_m等。
在本公开的示例性实施例中，读出位线R_BL和写入位线W_BL可以包括多列，例如，可以包括：R_BL_1、R_BL_2、R_BL_3、……、R_BL_n以及W_BL_1、W_BL_2、W_BL_3、……、W_BL_n等。
在本公开的示例性实施例中，存储阵列2中的每个存储单元1均为2T0C结构，与图2所示的传统的2T0C结构相比，保持了传统的2T0C结构的优点，读操作是无损的，具有非常低的漏电，不需要大电容的电容器，铟镓锌氧化物(IGZO)晶体管可以用于该结构中，因此，本公开一些实施例的存储单元1的2T0C结构解决了对大电容的需求问题，相应地降低了刷新频率和功耗。
在本公开的示例性实施例中，与传统的2T0C结构不同的是，本公开一些实施例的2T0C结构的存储单元中的读晶体管(即第一晶体管TR_R)，包 含有两个栅极，即，增加了一个辅助栅极(第二栅极)，第二栅极与写晶体管(即第二晶体管TR_W)的第五电极P5相连，由第五电极P5提供电压，并且第五电极P5设置为存储写晶体管的写入电压。由于晶体管的栅极具有背栅效应，随着写晶体管向第五电极P5写入电压，则读晶体管的辅助栅极获取相应的写入电压，并且根据辅助栅极写入电压的不同(例如，高电压或低电压)，读晶体管的栅极将呈现出不同的阈值电压(V TH)，如图4所示，对于N型读晶体管TR_R来说，当辅助栅极的电压为高电压(如，写入数据为“1”)时，V TH将负移；当辅助栅极的电压为低电压(如，写入数据为“0”)时，V TH将正移。
在本公开的示例性实施例中，读晶体管上的第一栅极给定一个合适的电压后，可以保证读晶体管不开启；在辅助栅极写入数据“0”时为低电压，读晶体管阈值电压正偏，该读晶体管更无法开启，因此，读晶体管BL(位线)上的电压没有大的变化，考虑漏电时可能有微小的变化，但变化值小于预设的阈值。在写入数据“1”时，对应高电压给辅助栅极，辅助栅极使得读晶体管的阈值电压负偏，且读晶体管开启。此时读晶体管的BL受高电压的影响，电压发生变化，且变化值超过阈值。SA电路(数据读取电路)与读出位线连接，靠分析读出位线上的电压变化量确定读取的数据是“1”还是“0”；读数“0”和“1”过程中，读晶体管的控制栅极(第一栅极)上的电压是不变的，靠辅助栅极(第二栅极)上被写入的电压改变读晶体管的阈值电压从而使得读晶体管自动开启或保持关闭。
在本公开的示例性实施例中，所述第一晶体管TR_R为N型晶体管或P型晶体管；以及，
所述第二晶体管TR_W为N型晶体管或P型晶体管。
在本公开的示例性实施例中，第一晶体管TR_R和第二晶体管TR_W可以均为N型晶体管，或者均为P型晶体管，或者任意一个为N型晶体管，另一个为P型晶体管，在此对于第一晶体管TR_R和第二晶体管TR_W的选型不做限定，可以根据需求自行定义。
在本公开的示例性实施例中，第一电极P1、第二电极P2、第五电极P5、第六电极P6可以根据所选择的晶体管的类型进行设置，在此对于第一电极 P1、第二电极P2、第五电极P5、第六电极P6为漏极或源极不做限定，可以根据不同的场景和需求自行定义。
在本公开的示例性实施例中，该存储阵列2还可以包括：行解码器(Row decoder)和列解码器(Column decoder)；
在一些实施例中，所述写入字线和所述读出字线可以与所述行解码器相连；
在一些实施例中，所述写入位线和所述读出位线可以与所述列解码器相连。
本公开一些实施例还提供了一种存储阵列，可以包括：
写入字线W_WL；
读出字线R_WL；
共用位线BL；以及，
多个所述的存储单元1；
其中，所述存储单元1包括：第一晶体管TR_R和第二晶体管TR_W；所述第一晶体管TR_R包括第一电极P1、第二电极P2、第三电极P3和第四电极P4；所述第三电极P3为第一栅极，所述第四电极P4为第二栅极；
所述第二晶体管TR_W包括第五电极P5、第六电极P6；所述第七电极P7为第三栅极G3；
所述第一电极P1与所述第六电极P6共同与所述共用位线BL相连，所述第二电极P2设置为参考电压端，所述第一栅极G1与所述读出字线R_WL相连，所述第二栅极G2与所述第五电极P5相连；
所述第三栅极G3与所述写入字线W_WL相连。
在本公开的示例性实施例中，为了节省占用面积，写入位线和读出位线可以合并使用，作为共用位线BL，可以包括但不限于下述两种方案。
在本公开的示例性实施例中，如图9a所示，所述第一电极P1和所述第六电极P6合并为一个电极，所述写入位线W_BL和所述读出位线R_BL合 并为一条共用位线，合并后获得的电极与合并后获得的共用位线相连。
在本公开的示例性实施例中，如图9b所示，所述第一电极P1和所述第六电极P6在存储单元内未合并为一个电极，所述写入位线W_BL和所述读出位线R_BL在存储阵列外部合并为一条共用位线。
在本公开的示例性实施例中，为了便于画图，在图9a和图9b中的存储单元的第二栅极均用一个电容符号来表示，但并不代表该处为电容。
在本公开的示例性实施例中，写入字线W_WL和读出字线R_WL可以包括多行，例如，可以包括：W_WL_1、W_WL_2、W_WL_3、……、W_WL_m以及R_WL_1、R_WL_2、R_WL_3、……、R_WL_m等。
在本公开的示例性实施例中，共用位线BL可以包括多列，例如，可以包括：BL1、BL2、BL3、……、BLn等。
在本公开的示例性实施例中，对于存储结构布局设计，总是希望减少BL(位线)和WL(字线)的数量，特别是位线BL，以实现更高的存储密度。
在本公开的示例性实施例中，为了减少位线BL的数量，可以将连接读出位线R_BL的第一电极P1与连接写入位线W_BL的第六电极P6相连，从而使得第一电极P1与第六电极P6合并为一个电极，从而可以仅连接一条共用位线即可，并且在存储单元1之外，读出位线R_BL和写入位线W_BL合并为一条共用位线BL，使得本公开一些实施例的存储单元1由原来的两条位线(读出位线R_BL和写入位线W_BL)连接到外部结构，改为了一条共用位线(BL)连接到外部结构，从而使得两条位线(读出位线R_BL和写入位线W_BL)可以在当前存储单元1所在的存储阵列的外部区域组合在一起。
在本公开的示例性实施例中，两条位线的设置方式至少需要两个过孔连接到硅上方，则需要更多的面积，即使存储单元做的很小，但外部电路太大，也做不成高密度存储器，从而可能对本公开一些实施例的存储单元1的产品化造成影响，而本公开一些实施例方案通过将读出位线R_BL和写入位线W_BL合并为一条位线BL，实现了仅需一个过孔，两个位线交叠，提高了存储密度。
在本公开的示例性实施例中，与传统的2T0C结构相比，本公开一些实 施例方案中的每个存储单元只有3个信号，包括2个字线信号和1个位线信号，有利于版图设计，特别是狭小空间的版图设计，提高了本公开一些实施例的存储单元1的实用性。
本公开一些实施例还提供了一种存储系统3，如图10a、10b、10c所示，可以包括：
多个所述的存储阵列2；以及，
多个放大器4；
其中，每个所述放大器4为相邻两个所述存储阵列共用的放大器4；所述放大器4设置为对感应阶段感应的所述存储阵列2中的存储单元1中读取的存储数据进行放大，在刷新阶段，将放大后的存储数据回写到所述存储单元1的存储节点。
在本公开的示例性实施例中，多个所述存储阵列2包括：第一存储阵列21和第二存储阵列22；所述第一存储阵列21中的每条读出位线R_BL分别和所述第二存储阵列22上的一条不同的读出位线R_BL共同连接到同一个放大器4，以使得连接同一放大器4的两条读出位线R_BL所连接的存储单元1共用同一放大器4；
连接同一放大器4的两条读出位线R_BL分别与所述放大器4的不同的信号输入端相连；
连接同一放大器4的两条读出位线R_BL对应的写入位线W_BL分别与所述放大器4的不同的信号输出端相连，将读取的并经所述放大器4放大后的存储电压刷新到存储单元的第二晶体管TR_W内进行存储。
在本公开的示例性实施例中，当第一存储阵列21和第二存储阵列22均存储在n(n为正整数)条读出位线R_BL时，则第一存储阵列21和第二存储阵列22之间可以共用n个放大器4，其中，第一存储阵列21中的第一条读出位线R_BL可以与第二存储阵列22中的第一条读出位线R_BL连接同一个放大器，第一存储阵列21中的第二条读出位线R_BL可以与第二存储阵列22中的第二条读出位线R_BL连接同一个放大器4，……，依此类推，第一 存储阵列21中的第n条读出位线R_BL可以与第二存储阵列22中的第n条读出位线R_BL连接同一个放大器4。
在本公开的示例性实施例中，每一个放大器4设置为对所连接的读出位线R_BL读取的存储数据的信号进行放大。
在本公开的示例性实施例中，所述的存储系统3还可以包括：多个预充电装置；多个所述预充电装置(Pre-charger)可以包括第一预充电装置和第二预充电装置；
所述第一存储阵列21对应的写入位线W_BL和读出位线R_BL均与所述第一预充电装置连接；
所述第二存储阵列22对应的写入位线W_BL和读出位线R_BL均与所述第二预充电装置连接。
在本公开的示例性实施例中，在对第一存储阵列21的任意一条读出位线R_BL上连接的存储单元1进行信号放大之前，可以先对该读出位线R_BL进行预充电，并对与该条读出位线R_BL共用同一放大器4的第二存储阵列22中的相应读出位线R_BL进行预充电，其中，第二存储阵列22中的该相应读出位线R_BL预充电电压作为第一存储阵列21中的读出位线R_BL的参考电压，并且第二存储阵列22中的该相应读出位线R_BL预充电电压值小于第一存储阵列21中的读出位线R_BL的预充电电压值，例如，第一存储阵列21中的读出位线R_BL的预充电电压值可以为VDD，第二存储阵列22中的读出位线R_BL的预充电电压值可以包括但不限于VDD/2。
在本公开的示例性实施例中，同理，在对第二存储阵列22的任意一条读出位线R_BL上连接的存储单元1进行信号放大之前，可以先对该读出位线R_BL进行预充电，并与该条读出位线R_BL共用同一放大器4的第一存储阵列21中的相应读出位线R_BL进行预充电，其中，第一存储阵列21中的该相应读出位线R_BL预充电电压作为第二存储阵列22中的读出位线R_BL的参考电压，并且第一存储阵列21中的该相应读出位线R_BL预充电电压值小于第二存储阵列22中的读出位线R_BL的预充电电压值，例如，第二存储阵列22中的读出位线R_BL的预充电电压值可以为VDD，第一存储阵列21中的读出位线R_BL的预充电电压值可以包括但不限于VDD/2。
在本公开的示例性实施例中，每个放大器4中可以设置有启动开关41，在对读出位线R_BL进行预充电以后，可以采用待进行信号放大的读出位线R_BL对该读出位线R_BL上的待读取数据的存储单元的存储数据进行读取，打开启动开关41，以将两条读出位线R_BL上的电压作为差分信号输入放大器4的两个信号输入端，通过信号放大器对待进行信号放大的读出位线R_BL上的信号进行放大。
在本公开的示例性实施例中，在读出位线R_BL对待读取数据的存储单元的存储数据进行读取之前，可以控制该待读取数据的存储单元的第一晶体管TR_R所连接的读出字线R_WL输入高电压，而不需要读取数据的存储单元的第一晶体管TR_R所连接的读出字线R_WL输入低电压，从而使得不需要读取数据的存储单元的第一晶体管TR_R关断，从而解决了传统的2T0C结构在读取数据时存在的电流串扰和均流问题。即，2T0C电池中的电流共享和串扰问题可以通过对未选择行的读出字线R_WL施加低电压来轻松解决。
在本公开的示例性实施例中，在对读出位线R_BL上的读取数据的信号进行放大以后，还可以将该放大后的信号通过放大器的信号输出端输入到待读取数据的存储单元1所连接的写入位线W_BL，以通过写入位线W_BL将放大后的读出数据重新写入该待读取数据的存储单元1的第二晶体管TR_W内，以实现对该待读取数据的存储单元1的第二晶体管TR_W内存储数据的刷新，避免由于泄露造成存储数据发生错误。
在本公开的示例性实施例中，在对该待读取数据的存储单元1的第二晶体管TR_W内存储数据进行刷新之前，控制该待读取数据的存储单元1的第二晶体管TR_W的写入字线W_WL输入高电压，并控制不需要读取数据的存储单元1的第二晶体管TR_W的写入字线W_WL输入低电压，以使得不需要读取数据的存储单元1的第二晶体管TR_W关断，从而避免在进行数据刷新过程中对不需要读取数据的存储单元1的第二晶体管TR_W刷新入该待读取数据的存储单元1的第二晶体管TR_W的存储数据，提高了数据存储可靠性。
在本公开的示例性实施例中，该存储系统中的存储阵列可以由本公开一 些实施例的电极合并后的2T0C结构的存储单元组成(如图10a所示)，也可以由电极未合并时的2T0C结构的存储单元组成(在此未画出全貌图，结构与图10a相似，仅是每个存储单元的第一电极P1和第六电极P6未合并，可以参考相应的存储阵列，局部示意图如图10b所示)，另外，该存储阵列还可以是每个存储单元的电极未合，而在存储阵列外部第一电极和第六电极所连接的位线进行合并(在此未画出示意图，对于一个存储系统来说，可以参考图9b和图10a，采用图9b的存储阵列替换图10a中的存储阵列即可)。
在本公开的示例性实施例中，所述放大器可以为电压放大器或电流放大器；
所述放大器的两个差分输入信号的输入端分别连接两条不同的读出位线，所述两条不同的读出位线分别来自相邻的所述存储阵列；
所述两个差分输入信号的输入端中，其中一个为读出位线读取的所述存储数据的输入端，另一个输入端为放大器差分输入信号的参考信号端。
在本公开的示例性实施例中，放大器4可以为电压放大器，也可以为电流放大器，可以根据需求自行选择。如图10c所示为放大器为电流放大器时的连接示意图，其中，I REF为参考电流，与图10b所示实例相似，该参考电流可以通过另一存储阵列提供。
在本公开的示例性实施例中，在一个存储系统中，上述的三种存储阵列可以任意组合使用，对于详细组合方案以及组合数量不做限制。
在本公开的示例性实施例中，为了便于画图，在图10a和图10b中的存储单元的第二栅极均用一个电容来表示。
本公开一些实施例提供了一种数据写入方法，基于所述的存储阵列，如图11所示，所述方法可以包括步骤S301-S302：
S301、对于所述存储阵列2中被选中的一行存储单元中需写入数据的存储单元1，通过所述存储单元的写入字线W_WL输入存储单元1的第二晶体管TR_W的栅极电压，以使得作为写晶体管的所述第二晶体管导通；
S302、通过所述存储单元2的写入位线或共用位线向导通的第二晶体管输入写入电压，使得所述写入电压存储在与所述第二晶体管连接的第一晶体 管的第二栅极中，其中，所述第二栅极配置为作为所述存储单元的存储节点，所述第一晶体管为读晶体管。
在本公开的示例性实施例中，该写入电压可以为高电压或低电压，对应的存储数据为“1”或“0”，写入字线W_WL被施加到高电压(即第三栅极G3的导通电压)，第二晶体管TR_W的第五电极P5和第六电极P6之间导通，则通过写入位线W_BL写入电压后，第五电极P5端的电压与第六电极P6(与写入位线W_BL连接)端的电压相同，均为该写入电压。
在本公开的示例性实施例中，所述方法还可以包括：
在所述存储阵列2中未被选中的每行存储单元1的写入字线W_WL输入与被选中的该行存储单元的所述第三栅极G3的导通电压不同的电压，以使得所述无需写入数据的存储单元1的第二晶体管TR_W关断。
在本公开的示例性实施例中，对于存储阵列2中连接同一写入位线W_BL的多个存储单元1，当任意一个存储单元1需要通过该写入位线W_BL写入数据时，需要控制该写入位线W_BL上连接的其它存储单元1的栅极所连接的写入字线W_WL施加一个与需要写入数据的存储单元1的第三栅极G3输入的导通电压不同的电压，从而使得需要写入数据的存储单元1的第二晶体管TR_W(写晶体管)导通，而其他的无需写入数据的存储单元的第二晶体管TR_W关断，确保了写入数据仅写入该需要写入数据的存储单元。
本公开一些实施例提供了一种数据读取方法，基于所述的存储阵列，如图12所示，所述方法可以包括步骤S401-S402：
S401、在数据读操作阶段，在所述存储阵列2中被选中的一行存储单元中需读取数据的存储单元1的第一晶体管TR_R连接的读出字线输入第一电压；其中，所述第一电压处于第一阈值电压和第二阈值电压之间，该第一阈值电压和第二阈值电压分别为存数据“1”和“0”时第一晶体管可以开启的阈值电压。
在本公开的示例性实施例中，第一晶体管TR_R作为读晶体管，在需要读取第二晶体管TR_W存储的电压时，可以对第一晶体管TR_R的第一栅极 G1输入一个电压使得第一晶体管TR_R的第一电极P1和第二电极P2关断，从而根据第一电极P1的电压大小(和/或电流大小)来判断第五电极P5存储的为高电压还是低电压，或者，存储的数据为“1”还是“0”。
在本公开的示例性实施例中，第一晶体管TR_R的第一栅极G1与读出字线R_WL相连，可以通过读出字线R_WL提供第一栅极G1的电压(第一电压)，通过前面的论述可知，第一晶体管TR_R的栅极存在背栅效应，因此，通过第五电极P5对第一晶体管TR_R的第二栅极G2(辅助栅极)提供存储的写入电压时，会使得第一晶体管TR_R的栅极的阈值电压发生偏移，而且根据第五电极P5所写入的数据的不同(如“1”或“0”)，偏移也不同，因此，对第一晶体管TR_R的第一栅极G1施加电压时可以根据第二栅极G2的电压大小来实施，以确保第一晶体管TR_R的第一电极P1和第二电极P2之间关断，从而使得第一电极P1读出所存储的数据。
在本公开的示例性实施例中，对第一晶体管TR_R的第一栅极G1施加的电压可以位于低电压到高电压(“0”-“1”)之间，以补充辅助栅极的电压，使得第一晶体管TR_R导通。
S402、当检测到所述第一晶体管连接的读出位线的电压变化且变化数值大于或等于预设的第一电压变化阈值时确定所述存储单元的读出的数据为“1”，当所述第一晶体管的连接的读出位线的电压无变化或者变化数值小于或等于预设的第二电压变化阈值时，则确定所述存储单元的读出数据为“0”。
在本公开的示例性实施例中，在数据读操作阶段之前还包括预充电阶段，所述方法还可以包括：
对所述读出位线或所述共用位线进行预充电，使得读出位线上的电压高于放大器差分输入信号输入端中的参考信号端提供的电压。在本公开的示例性实施例中，第一电极P1连接的读出位线R_BL在初始读取数据时可以预充一个电压(即该第二电压)，预充电压可以是一个小于存储器件电源电压VDD的电压，例如，可以包括但不限于VDD/4、VDD/3以及VDD/2等，详细数值可以根据不同的应用场景和需求自行定义。
在本公开的示例性实施例中，该参考电压可以包括但不限于0V。
在本公开的示例性实施例中，当检测到所述第一晶体管的第一电极P1的电压发生变化，且变化数值大于或等于预设的第一电压变化阈值时，确认所述存储阵列中需读取数据的存储单元的第二晶体管的第五电极端储存的电压为第一存储电压值，并读取所述第一存储电压值。
在本公开的示例性实施例中，该第一电压变化阈值可以根据不同的需求或精度要求自行定义，在此不做详细限制。
在本公开的示例性实施例中，如果之前将数据“1”写入第五电极P5，则可以在参考电压Vrefn(如0电位或接地端)和选定的读出位线R_BL之间测量显著的电导变化量(导通电流)，并且可以在选定的读出位线R_BL处感测到它。因此，当检测到所述第一晶体管TR_R的第一电极P1的电压发生变化，且变化数值大于或等于预设的第一电压变化阈值时，可以确定存储的写入电压为高电压，即写入数据为“1”。
在本公开的示例性实施例中，当检测到所述第一晶体管TR_R的第一电极的电压未发生变化，或者变化数值小于或等于预设的第二电压变化阈值时，确认所述第二晶体管TR_W的第五电极P5端储存的电压为第二存储电压值，并读取所述第二存储电压值；所述第二电压变化阈值小于所述第一电压变化阈值。
在本公开的示例性实施例中，该第二电压变化阈值可以根据不同的需求或精度要求自行定义，在此不做详细限制。
在本公开的示例性实施例中，如果之前将数据“0”写入第五电极P5，则不会在Vrefn和选定的读出位线R_BL之间感测到电导。因此，当检测到所述第一晶体管TR_R的第一电极P1的电压未发生变化，或者变化数值小于或等于预设的第二电压变化阈值时，可以确定存储的写入电压为低电压，即写入数据为“0”。
在本公开的示例性实施例中，所述方法还可以包括：
在对存储阵列2中任意的存储单元1中的第二晶体管TR_W存储的电压值进行读取过程中，在所述存储阵列2中无需读取数据的存储单元1的读出字线R_WL输入与需读取数据的存储单元1的第一晶体管TR_R的读出字线 R_WL输入电压不同的电压，以使得所述无需读取数据的存储单元1的第一晶体管TR_R关断；
其中，所述无需读取数据的存储单元的读出字线与需读取数据的存储单元的第一晶体管的读出字线为不同的字线。
已知传统的2T0C单元结构(如图2所示)的数据写入和数据读取也是分开的，分别用两个晶体管Tr_w(写晶体管)和Tr_r(读晶体管)来实现。它需要4个信号，分别为写操作需要的写-WL(写入字线)信号和写-BL(写入位线)信号，读操作需要读-WL(读取字线)信号和读-BL(读出位线)信号，与传统的1T1C结构的DRAM单元相比，本公开一些实施例方案中的2T0C结构由于非破坏性的读取特性，在Tr_w和Tr_r之间也不需要太大的电容。然而，在2T0C结构的存储阵列中，由于每个2T0C存储单元所连接的R-WLs(读取字线)和R-BLs(读出位线)上连接的全部2T0C存储单元之间存在串扰或均流问题，执行读操作时是一个挑战，DRAM界仍在努力解决这个问题。
在本公开的示例性实施例中，通过将存储阵列2中无需读取数据的存储单元1的第一晶体管TR_R的读出字线R_WL输入与需读取数据的存储单元1的第一晶体管TR_R的读出字线R_WL输入电压不同的电压，实现了使得无需读取数据的存储单元1的第一晶体管TR_R关断，从而解决了传统的2T0C结构在读取数据时存在的电流串扰和均流问题。例如，2T0C电池中的电流共享和串扰问题可以通过对未选择行的读出字线R_WL施加低电压来轻松解决。
在本公开的示例性实施例中，所述方法还可以包括：在刷新阶段进行数据刷新；
所述在刷新阶段进行数据刷新，可以包括：感应所述存储单元中的存储数据并通过所述放大器放大所述存储数据，将所述放大的存储数据回写入所述存储单元的存储节点。
在本公开的示例性实施例中，在所述第一晶体管TR_R读出所述第一存储电压值或所述第二存储电压值以后，在所述存储阵列中的写入字线W_WL输入所述存储单元的第三栅极G3的导通电压；
将读取的电压值输入需写入数据的存储单元1对应的写入位线W_BL，以对所述第二晶体管TR_W存储的电压值进行刷新。
在本公开的示例性实施例中，为了避免泄露使得写入的电压发生变化，可以在每次读取出写入电压之后及时将该写入电压重新写入写晶体管进行保存，以实现对存储电压的及时刷新。
在本公开的示例性实施例中，所述方法还可以包括：
在对所述第二晶体管TR_W的存储数据进行刷新过程中，在所述存储阵列2中无需刷新存储数据的存储单元1的写入字线W_WL输入电压使得所述无需写入数据的存储单元1的第二晶体管TR_W关断；
需要刷新的所述存储单元连接的写入字线与无需刷新存储数据的存储单元的写入字线为不同的字线。
在本公开的示例性实施例中，对于连接同一写入位线的多个存储单元1，当任意一个存储单元1需要通过该写入位线W_BL写入数据时，需要控制该写入位线W_BL上连接的其它存储单元1的栅极所连接的写入字线W_WL施加一个与需要写入数据的存储单元1的第三栅极G3输入电压不同的电压，从而使得需要写入数据的存储单元1的第二晶体管TR_W(写晶体管)导通，而其他的无需写入数据的存储单元的第二晶体管TR_W关断，确保了写入数据仅写入该需要写入数据的存储单元1。
本公开一些实施例提供了一种数据写入方法，基于所述的存储系统，如图13所示，所述方法可以包括步骤S501-S502：
S501、在所述存储系统3的存储阵列2中需写入数据的存储单元1的写入字线W_WL输入所述存储单元1的第三栅极G3的导通电压；
S502、在所述需写入数据的存储单元1的写入位线W_BL输入待写入电压。
在本公开的示例性实施例中，该需写入数据可以为“1”或“0”，写入字线W_WL被施加到高电压(即第三栅极G3的导通电压)，第二晶体管TR_W的第五电极P5和第六电极P6之间导通，则通过写入位线W_BL写入 电压后，第五电极P5端的电压与第六电极P6(与写入位线W_BL连接)端的电压相同，均为该写入电压。
在本公开的示例性实施例中，所述方法还可以包括：
在所述存储系统3的存储阵列2中无需写入数据的存储单元1的写入字线W_WL输入与所述第三栅极G3的导通电压不同的电压，以使得所述无需写入数据的存储单元1的第二晶体管TR_W关断。
在本公开的示例性实施例中，对于存储阵列2中连接同一写入位线W_BL的多个存储单元1，当任意一个存储单元1需要通过该写入位线W_BL写入数据时，需要控制该写入位线W_BL上连接的其它存储单元1的栅极所连接的写入字线W_WL施加一个与需要写入数据的存储单元1的第三栅极G3输入的导通电压不同的电压，从而使得需要写入数据的存储单元1的第二晶体管TR_W(写晶体管)导通，而其他的无需写入数据的存储单元的第二晶体管TR_W关断，确保了写入数据仅写入该需要写入数据的存储单元。
本公开一些实施例提供了一种数据读取方法，基于所述的存储系统，如图14所示，所述方法可以包括步骤S601-S605：
S601、在所述存储系统3的第一存储阵列21中需读取数据的存储单元1的第一晶体管TR_R对应的读出字线R_WL输入第三电压；所述第三电压位于第一阈值电压和第二阈值电压之间；所述第一阈值电压为存储节点存储数据为1时使得所述读晶体管开启得阈值电压；所述第二阈值电压为存储节点存储数据为0时使得所述读晶体管开启的阈值电压。
在本公开的示例性实施例中，第一晶体管TR_R作为读晶体管，在需要读取第二晶体管TR_W存储的电压时，可以对第一晶体管TR_R的第一栅极G1输入一个电压使得第一晶体管TR_R的第一电极P1和第二电极P2导通，从而根据第一电极P1的电压大小(和/或电流大小)来判断第五电极P5存储的为高电压还是低电压，或者，存储的数据为“1”还是“0”。
在本公开的示例性实施例中，第一晶体管TR_R的第一栅极G1与读出字线R_WL相连，可以通过读出字线R_WL提供第一栅极G1的电压(第三 电压)，通过前面的论述可知，第一晶体管TR_R的栅极存在背栅效应，因此，通过第五电极P5对第一晶体管TR_R的第二栅极G2(辅助栅极)提供存储的写入电压时，会使得第一晶体管TR_R的栅极的阈值电压发生偏移，而且根据第五电极P5所写入的数据的不同(如1或0)，偏移也不同，因此，对第一晶体管TR_R的第一栅极G1施加电压时可以根据第二栅极G2的电压大小来实施，以确保第一晶体管TR_R的第一电极P1和第二电极P2之间关断，从而使得第一电极P1读出所存储的电压。
在本公开的示例性实施例中，对第一晶体管TR_R的第一栅极G1施加的电压可以位于低电压到高电压(“0”-“1”)之间，以补充辅助栅极的电压，使得第一晶体管TR_R导通。
S602、为所述存储系统的第一存储阵列中需读取数据的存储单元的读出位线进行预充电，获取第四电压。
在本公开的示例性实施例中，在对第一存储阵列21的任意一条读出位线R_BL上连接的存储单元1进行信号放大之前，可以先对该读出位线R_BL进行预充电，获取第四电压，该第四电压的电压值可以为VDD。
S603、为所述存储系统3的第二存储阵列22中与所述需读取数据的存储单元相对应的存储单元的读出位线进行预充电，获取第五电压；所述第五电压小于所述第四电压。
在本公开的示例性实施例中，对与第一存储阵列21中的预充电的读出位线R_BL共用同一放大器4的第二存储阵列22中的相应读出位线R_BL进行预充电，获取第五电压；第二存储阵列22中的该相应读出位线R_BL的预充电电压作为第一存储阵列21中的读出位线R_BL的参考电压，该第五电压的电压值可以包括但不限于VDD/2。
S604、在所述第一存储阵列21中需读取数据的存储单元1的读出位线R_BL上的电压稳定后，控制所述放大器4的启动开关开启，对所述读出位线R_BL上的电压进行放大。
在本公开的示例性实施例中，当第二晶体管TR_W内存储数据为0时，则在读取数据以后，预充的第四电压不会发生变化，当第二晶体管TR_W内 存储数据为1时，则在读取数据以后，预充的第四电压会首先降低，等第四电压不再降低时则达到电压稳定状态，确定读取数据完成，此时可以将所述放大器4的启动开关开启，将当前两个读出位线上的电压输入放大器4，通过放大器4对降低并稳定后的第四电压(作为读取数据)进行放大。
在本公开的示例性实施例中，在读出位线R_BL对待读取数据的存储单元的存储数据进行读取之前，可以控制该待读取数据的存储单元的第一晶体管TR_R所连接的读出字线R_WL输入高电压，而不需要读取数据的存储单元的第一晶体管TR_R所连接的读出字线R_WL输入低电压，从而使得不需要读取数据的存储单元的第一晶体管TR_R关断，从而解决了传统的2T0C结构在读取数据时存在的电流串扰和均流问题。即，本公开一些实施例方案的2T0C电路中的电流共享和串扰问题可以通过对未选择行的读出字线R_WL施加低电压来轻松解决。
S605、通过所述放大器4的第一信号输出端读取放大后的电压，作为所述第一存储阵列21中需读取数据的存储单元的存储电压。
在本公开的示例性实施例中，在通过所述放大器4的第一信号输出端读取放大后的电压以后，所述方法还可以包括：
在所述第一存储阵列21中的与所述需读取数据的存储单元对应的写入字线输入所述第二晶体管TR_W的第三栅极G3的导通电压；
将读取的放大后的电压输入所述需读取数据的存储单元的第二晶体管TR_W对应的写入位线，以对所述需读取数据的存储单元的第二晶体管TR_W存储的电压值进行刷新。
在本公开的示例性实施例中，在对读出位线R_BL上的读取数据的信号进行放大以后，还可以将该放大后的信号通过放大器的信号输出端输入到待读取数据的存储单元1所连接的写入位线W_BL，以通过写入位线W_BL将放大后的读出数据重新写入该待读取数据的存储单元1的第二晶体管TR_W内，以实现对该待读取数据的存储单元1的第二晶体管TR_W内存储数据的刷新，避免由于泄露造成存储数据发生错误。
在本公开的示例性实施例中，所述方法还可以包括：
在对所述需读取数据的存储单元的第二晶体管TR_W存储的电压值进行刷新过程中，在所述第一存储阵列21中无需刷新数据的存储单元的写入字线W_WL输入与所述第二晶体管TR_W的第三栅极G3的导通电压不同的电压，以使得所述无需写入数据的存储单元1的第二晶体管TR_W关断。
在本公开的示例性实施例中，在对该待读取数据的存储单元1的第二晶体管TR_W内存储数据进行刷新之前，控制该待读取数据的存储单元1的第二晶体管TR_W的写入字线W_WL输入高电压，并控制不需要读取数据的存储单元1的第二晶体管TR_W的写入字线W_WL输入低电压，以使得不需要读取数据的存储单元1的第二晶体管TR_W关断，从而避免在进行数据刷新过程中对不需要读取数据的存储单元1的第二晶体管TR_W刷新入该待读取数据的存储单元1的第二晶体管TR_W的存储数据，提高了数据存储可靠性。
本公开一些实施例提供了一种存储阵列的控制芯片，所述控制芯片设置为执行基于所述存储阵列的数据写入方法，以及基于所述存储阵列的数据读取方法。
在本公开的示例性实施例中，前述的存储单元、存储阵列及其数据写入和数据读取方法实施例中的任何实施例均适用于该存储阵列的控制芯片实施例中，在此不再一一赘述。
本公开一些实施例提供了一种存储系统的控制芯片，所述控制芯片设置为执行基于所述存储阵列的数据写入方法。
本公开一些实施例提供了一种存储系统的控制芯片，所述控制芯片设置为执行基于所述存储阵列的数据读取方法。
在本公开的示例性实施例中，前述的存储单元、存储阵列及其数据写入和数据读取方法实施例中的任何实施例均适用于该存储系统的控制芯片实施例中，在此不再一一赘述。
本公开一些实施例提供了一种存储器，包括所述的存储阵列。
在本公开的示例性实施例中，前述的存储单元、存储阵列及其数据写入和数据读取方法实施例中的任何实施例均适用于该存储系统的控制芯片实施 例中，在此不再一一赘述。
本公开一些实施例提供了一种电子设备，包括所述的存储器。
在本公开的示例性实施例中，前述的存储单元、存储阵列及其数据写入和数据读取方法实施例中的任何实施例均适用于该存储系统的控制芯片实施例中，在此不再一一赘述。
领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。

Claims (20)

  1. 一种存储单元，包括：
    第一晶体管，设置为读晶体管；以及，
    第二晶体管，设置为写晶体管；
    其中，所述第一晶体管包括第一电极、第二电极、第三电极和第四电极；所述第三电极为第一栅极，所述第四电极为第二栅极；
    所述第二晶体管包括第五电极、第六电极和第七电极；所述第七电极为第三栅极；
    所述第一电极设置为与读出位线相连，所述第二电极设置为连接参考信号，所述第一栅极设置为与读出字线相连，所述第二栅极设置为与所述第五电极相连；
    所述第六电极设置为与写入位线相连，所述第三栅极设置为与写入字线相连。
  2. 根据权利要求1所述的存储单元，其中，所述第一电极和所述第六电极共用一个电极，配置为与不同的位线连接或与同一条位线连接。
  3. 根据权利要求2所述的存储单元，其中，所述不同的位线为所述读出位线和写入位线；所述同一条位线同时作为所述读出位线和写入位线。
  4. 根据权利要求1所述的存储单元，其中，所述第一栅极和第二栅极为相互独立的栅极，且所述第一栅极用于控制所述读晶体管的读操作；所述第二栅极配置为作为所述存储单元的存储节点，通过所述写晶体管在所述存储节点写入电信号。
  5. 一种存储阵列，包括：
    写入字线；
    读出字线；
    写入位线；
    读出位线；以及，
    多个如权利要求1-4任意一项所述的存储单元；
    其中，所述存储单元包括：第一晶体管和第二晶体管；所述第一晶体管包括第一电极、第二电极、第三电极和第四电极；所述第三电极为第一栅极，所述第四电极为第二栅极；
    所述第二晶体管包括第五电极、第六电极和第七电极；所述第七电极为第三栅极；
    所述第一电极与所述读出位线相连，所述第二电极设置为连接参考信号，所述第一栅极与所述读出字线相连，所述第二栅极与所述第五电极相连；
    所述第六电极与所述写入位线相连，所述第三栅极与所述写入字线相连。
  6. 根据权利要求5所述的存储阵列，其中，
    所述第一电极和所述第六电极共用一个电极，所述写入位线和所述读出位线共用一条位线，共用的所述电极与共用的所述位线相连。
  7. 一种存储阵列，包括：
    写入字线；
    读出字线；
    共用位线；以及，
    多个如权利要求1-4任意一项所述的存储单元；
    其中，所述存储单元包括：第一晶体管和第二晶体管；所述第一晶体管包括第一电极、第二电极、第三电极和第四电极；所述第三电极为第一栅极，所述第四电极为第二栅极；
    所述第二晶体管包括第五电极、第六电极和第七电极；所述第七电极为第三栅极；
    所述第一电极与所述第六电极共同与所述共用位线相连，所述第二电极设置为连接参考信号，所述第一栅极与所述读出字线相连，所述第二栅极与所述第五电极相连；
    所述第三栅极与所述写入字线相连。
  8. 一种存储系统，包括：
    多个如权利要求5或6或7所述的存储阵列；以及，
    多个放大器；
    其中，每个所述放大器为相邻两个所述存储阵列共用的放大器；所述放大器设置为对感应阶段感应的所述存储阵列中的存储单元中读取的存储数据进行放大，在刷新阶段，将放大后的存储数据回写到所述存储单元的存储节点。
  9. 根据权利要求8所述的存储系统，其中，所述放大器为电压放大器或电流放大器；
    所述放大器的两个差分输入信号的输入端分别连接两条不同的读出位线，所述两条不同的读出位线分别来自相邻的所述存储阵列；
    所述两个差分输入信号的输入端中，其中一个为读出位线读取的所述存储数据的输入端，另一个输入端为放大器差分输入信号的参考信号端。
  10. 一种数据写入方法，基于如权利要求7所述的存储阵列，所述方法包括：
    对于所述存储阵列中被选中的一行存储阵列中需写入数据的存储单元，通过所述存储单元的写入字线输入到所述存储单元的第二晶体管的栅极电压，以使得作为写晶体管的所述第二晶体管导通；
    通过所述存储单元的写入位线或共用位线向导通的第二晶体管输入写入数据，使得所述数据电压存储在与所述第二晶体管连接的第一晶体管的第二栅极中，其中，所述第二栅极配置为作为所述存储单元的存储节点，所述第一晶体管为读晶体管。
  11. 根据权利要求10所述的数据写入方法，还包括：
    在所述存储阵列中未被选中的每行存储单元的写入字线输入与被选中的一行存储单元的第三栅极的导通电压不同的电压，以使得无需写入数据的存储单元的第二晶体管关断。
  12. 一种数据读取方法，基于如权利要求7所述的存储阵列，所述方法包括：
    在数据读操作阶段，在所述存储阵列中被选中的一行存储单元中需读取 数据的存储单元的第一晶体管连接的读出字线输入第一电压；其中，所述第一电压位于第一阈值电压和第二阈值电压之间，所述第一阈值电压为所述存储单元存储数据“1”时对所述第一晶体管的开启阈值电压；所述第二阈值电压为所述存储单元存储数据“0”时对应的所述第一晶体管的开启阈值电压；
    当检测到所述第一晶体管连接的读出位线的电压变化且变化数值大于或等于预设的第一电压变化阈值时确定所述存储单元的读出的数据为“1”，当所述第一晶体管的连接的读出位线的电压无变化或者变化数值小于或等于预设的第二电压变化阈值时，则确定所述存储单元的读出数据为“0”。
  13. 根据权利要求12所述的数据读取方法，在数据读操作阶段之前还包括预充电阶段，所述方法还包括：
    对所述读出位线或所述共用位线进行预充电，使得读出位线上的电压高于放大器差分输入信号输入端中的参考信号端提供的电压。
  14. 根据权利要求12所述的数据读取方法，还包括：
    在对所述存储阵列中需读取数据的存储单元的第二晶体管存储的数据进行读取过程中，在所述存储阵列中无需读取数据的存储单元的读出字线输入与需读取数据的存储单元的第一晶体管的读出字线输入电压不同的电压，以使得所述无需读取数据的存储单元的第一晶体管关断；
    其中，所述无需读取数据的存储单元的读出字线与需读取数据的存储单元的第一晶体管的读出字线为不同的字线。
  15. 根据权利要求12所述的数据读取方法，还包括：在刷新阶段进行数据刷新；
    所述在刷新阶段进行数据刷新，包括：感应所述存储单元中存储数据并通过放大器放大所述存储数据，将放大的存储数据回写入所述存储单元的存储节点。
  16. 根据权利要求15所述的数据读取方法，还包括：
    在对所述第二晶体管的存储数据进行刷新过程中，在所述存储阵列中无需刷新存储数据的存储单元的写入字线输入电压使得所述无需写入数据的存储单元的第二晶体管关断；
    需要刷新的所述存储单元连接的写入字线与无需刷新存储数据的存储单元的写入字线为不同的字线。
  17. 一种存储阵列的控制芯片，所述控制芯片设置为执行如权利要求10-11任意一项所述的数据写入方法。
  18. 一种存储阵列的控制芯片，所述控制芯片设置为执行如权利要求12-16任一权利要求所述的数据读取方法。
  19. 一种存储器，包括如权利要求5-7任一权利要求所述的存储阵列。
  20. 一种电子设备，包括如权利要求19所述的存储器。
PCT/CN2022/140811 2022-07-07 2022-12-21 存储单元、阵列读写方法、控制芯片、存储器和电子设备 WO2024007544A1 (zh)

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