WO2021109075A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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WO2021109075A1
WO2021109075A1 PCT/CN2019/123310 CN2019123310W WO2021109075A1 WO 2021109075 A1 WO2021109075 A1 WO 2021109075A1 CN 2019123310 W CN2019123310 W CN 2019123310W WO 2021109075 A1 WO2021109075 A1 WO 2021109075A1
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semiconductor layer
type semiconductor
gan
based material
manufacturing
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PCT/CN2019/123310
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French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to US17/622,974 priority Critical patent/US20220262933A1/en
Priority to CN201980102498.3A priority patent/CN114730739B/zh
Priority to PCT/CN2019/123310 priority patent/WO2021109075A1/zh
Priority to TW109142503A priority patent/TWI797513B/zh
Publication of WO2021109075A1 publication Critical patent/WO2021109075A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof.
  • III-Nitride is the third-generation new semiconductor material after the first and second-generation semiconductor materials such as Si and GaAs.
  • GaN has many advantages as a wide-gap semiconductor material, such as high saturation drift speed, high breakdown voltage, It has excellent carrier transport performance and can form AlGaN, InGaN ternary alloys and AlInGaN quaternary alloys, and it is easy to fabricate GaN-based PN junctions.
  • GaN-based materials and semiconductor devices have received extensive and in-depth research in recent years, and the growth of GaN-based materials by MOCVD technology is becoming more and more mature.
  • optoelectronic devices such as GaN-based LEDs and LDs and microelectronics such as GaN-based HEMTs The research on the device has made remarkable achievements and considerable development.
  • One of the problems lies in the problem of over-etching when fabricating contact electrodes on the P-type GaN-based semiconductor layer and/or the N-type GaN-based semiconductor layer.
  • the purpose of the present invention is to provide a semiconductor structure and a manufacturing method thereof to improve the performance of a GaN-based semiconductor device.
  • a first aspect of the present invention provides a manufacturing method of a semiconductor structure, including:
  • the first P-type semiconductor layer includes a GaN-based material, and the upper surface is a Ga surface;
  • the N-type semiconductor layer includes a GaN-based material, and the upper surface is an N-face;
  • the second P-type semiconductor layer includes a GaN-based material, and the upper surface is an N-plane;
  • wet etching removes the second P-type semiconductor layer and N-type semiconductor layer in the collector region, exposing the first P-type semiconductor layer; dry etching removes the second P-type semiconductor layer in the base region, exposing the N-type semiconductor layer.
  • GaN crystal has a brazine structure, in which the Ga and N atomic layers are stacked in ABABAB hexagonal layers, and each Ga(N) atom forms a bond with the surrounding 4 N(Ga) atoms in a diamond-like tetrahedral structure. It should be noted that, taking Ga-N bonds parallel to the C axis ([0001] crystal orientation) as a reference, if the Ga atoms in each Ga-N bond are farther away from the substrate, the upper surface is the Ga plane; The N atoms in a Ga-N bond are farther away from the substrate, and the upper surface is the N surface.
  • P-type dopant ions in the first P-type semiconductor layer are activated.
  • a collector is formed on the first P-type semiconductor layer in the collector region, a base is formed on the N-type semiconductor layer in the base region, and an emitter is formed on the second P-type semiconductor layer in the emitter region .
  • an N-type semiconductor layer with an N-side upper surface is formed on the first P-type semiconductor layer by: connecting the Ga surface of the N-type semiconductor layer directly with the Ga surface of the first P-type semiconductor layer Bond.
  • an N-type semiconductor layer with an N-side upper surface on the first P-type semiconductor layer is passed: in the process of forming the N-type semiconductor layer, the N-type semiconductor layer is reversed by polarity. The N side is facing up.
  • forming a second P-type semiconductor layer with an N-side upper surface on the N-type semiconductor layer is achieved by connecting the Ga surface of the second P-type semiconductor layer directly with the N-side surface of the N-type semiconductor layer. Bond.
  • forming a second P-type semiconductor layer with an upper surface on the N-type semiconductor layer on the N-type semiconductor layer is passed: in the process of forming the second P-type semiconductor layer, the second P-type semiconductor layer is reversed by polarity.
  • the N side of the P-type semiconductor layer faces upward.
  • the GaN-based material is at least one of GaN, AlGaN, InGaN, and AlInGaN.
  • a second aspect of the present invention provides a method for manufacturing a semiconductor structure, including:
  • N-type semiconductor layer includes a GaN-based material, and the upper surface is a Ga surface;
  • the second P-type semiconductor layer includes a GaN-based material, and the upper surface is an N-plane;
  • a part of the second P-type semiconductor layer is removed by wet etching, exposing the N-type semiconductor layer.
  • forming a second P-type semiconductor layer with an N-side upper surface on the N-type semiconductor layer is achieved by directly connecting the Ga surface of the second P-type semiconductor layer with the Ga surface of the N-type semiconductor layer. Bond.
  • forming a second P-type semiconductor layer with an upper surface on the N-type semiconductor layer on the N-type semiconductor layer is passed: in the process of forming the second P-type semiconductor layer, the second P-type semiconductor layer is reversed by polarity.
  • the N side of the P-type semiconductor layer faces upward.
  • a third aspect of the present invention provides a semiconductor structure, including:
  • the first P-type semiconductor layer includes a GaN-based material, and the upper surface is a Ga plane; the N-type semiconductor layer includes a GaN-based material, and the upper surface is an N-plane; the second P-type semiconductor layer includes a GaN-based material , And the upper surface is an N surface; the Ga surface of the first P-type semiconductor layer and a part of the N surface of the N-type semiconductor layer are exposed.
  • the exposed first P-type semiconductor layer has a collector
  • the N-type semiconductor layer has a base electrode
  • the second P-type semiconductor layer has an emitter electrode
  • a fourth aspect of the present invention provides a semiconductor structure, including:
  • the N-type semiconductor layer and the second P-type semiconductor layer distributed from bottom to top; among them:
  • the N-type semiconductor layer includes a GaN-based material and the upper surface is a Ga plane; the second P-type semiconductor layer includes a GaN-based material and the upper surface is an N-plane; a partial region of the Ga plane of the N-type semiconductor layer exposed.
  • the present invention has the following beneficial effects:
  • a first P-type semiconductor layer is provided first, the first P-type semiconductor layer includes a GaN-based material; then an N-type semiconductor layer is formed on the first P-type semiconductor layer, and the N-type semiconductor layer Including a GaN-based material; then a second P-type semiconductor layer is formed on the N-type semiconductor layer, and the second P-type semiconductor layer includes a GaN-based material; wherein, when the first P-type semiconductor layer is provided, the control upper surface is Ga When forming an N-type semiconductor layer, control the upper surface to be an N surface; when forming a second P-type semiconductor layer, control the upper surface to be an N surface.
  • the etching starts from the N surface of the second P-type semiconductor layer and automatically stops at the Ga surface of the first P-type semiconductor layer, which can avoid over-etching.
  • dry etching when the dry etching stops, the first P-type semiconductor layer will be over-etched; during the dry etching process, nitrogen atoms in the GaN-based material preferentially escape, causing electron carriers
  • the number increases for the P-type semiconductor layer, some hole carriers will be neutralized, resulting in a decrease in hole carrier concentration, and even surface inversion; therefore, compared to dry etching, wet etching can avoid formation
  • wet etching can avoid formation The above-mentioned problems in the electrical connection structure of the P-type semiconductor layer.
  • the second P-type semiconductor layer is dry-etched and stopped on the upper surface of the N-type semiconductor layer.
  • the dry-etching stops the N-type semiconductor layer will be over-etched, and the nitrogen atoms in the GaN-based material will escape preferentially.
  • the increase in the number of electron carriers will reduce the surface resistivity of the N-type semiconductor layer, which is beneficial to reduce the contact resistance of the electrical connection structure of the N-type semiconductor layer.
  • the acceptor dopant Mg in GaN will be passivated by a large number of H atoms without generating holes; in addition, a large number of passivated and unbonded Mg ions It will enter the N-type GaN-based material layer grown on it, causing the PN junction junction to be blurred, and part of the N-type GaN-based material layer will be compensated, and the electron concentration will be reduced. In severe cases, the PN junction will fail.
  • an N-type semiconductor layer with an N-side upper surface is formed on the first P-type semiconductor layer through: a) The Ga surface of the N-type semiconductor layer is directly bonded to the Ga surface of the first P-type semiconductor layer ⁇ ; or b) In the process of forming the N-type semiconductor layer, the N-side of the N-type semiconductor layer faces upwards by means of polarity inversion.
  • forming a second P-type semiconductor layer with an N-side upper surface on the N-type semiconductor layer by: a) directly bonding the Ga surface of the second P-type semiconductor layer to the N surface of the N-type semiconductor layer; Or b) In the process of forming the second P-type semiconductor layer, the N side of the second P-type semiconductor layer is facing upwards by means of polarity inversion. Studies have shown that the above two methods are reliable.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to a first embodiment of the present invention
  • FIG. 2 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention.
  • FIG. 4 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 3;
  • FIG. 5 is a flowchart of a manufacturing method of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • FIG. 8 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 7.
  • the first P-type semiconductor layer 11 The upper surface 11a of the first P-type semiconductor layer
  • N-type semiconductor layer 12 The upper surface 12a of the N-type semiconductor layer
  • the second P-type semiconductor layer 13 The upper surface 12a of the second P-type semiconductor layer
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to a first embodiment of the present invention.
  • the semiconductor structure 1 of the first embodiment includes:
  • the first P-type semiconductor layer 11 includes a GaN-based material, and the upper surface 11a is a Ga surface; the N-type semiconductor layer 12 includes a GaN-based material, and the upper surface 12a is an N-surface; the second P-type semiconductor layer 13 includes a GaN-based material, In addition, the upper surface 13a is an N surface; the Ga surface of the first P-type semiconductor layer 11 and part of the N surface of the N-type semiconductor layer 12 are exposed.
  • the aforementioned semiconductor structure 1 may be a PNP bipolar transistor.
  • the semiconductor substrate 10 may be sapphire, silicon carbide, silicon, GaN, or diamond, etc., which is not limited in this embodiment.
  • the GaN-based material may be at least one of GaN, AlGaN, InGaN, and AlInGaN, which is not limited in this embodiment.
  • the upper surface 11a of the first P-type semiconductor layer 11 being a Ga plane means that the Ga-N bond parallel to the C axis ([0001] crystal orientation) is used as a reference, and the Ga atoms in each Ga-N bond are farther away from the semiconductor The substrate 10. It can be understood that, at this time, the lower surface of the first P-type semiconductor layer 11 is an N-plane.
  • the upper surface 12a of the N-type semiconductor layer 12 and the upper surface 13a of the second P-type semiconductor layer 13 being the N-plane means that the Ga-N bond parallel to the C axis ([0001] crystal orientation) is used as a reference, and each Ga The N atoms in the -N bond are farther away from the semiconductor substrate 10. It can be understood that, at this time, the lower surfaces of the N-type semiconductor layer 12 and the second P-type semiconductor layer 13 are Ga surfaces.
  • the exposed area of the upper surface 11a of the first P-type semiconductor layer 11, the exposed area of the upper surface 12a of the N-type semiconductor layer 12 and the upper surface 13a of the second P-type semiconductor layer 13 may form an electrical connection structure, such as a metal interconnection structure , To draw out the electrical signals of the first P-type semiconductor layer 11, the N-type semiconductor layer 12, and the second P-type semiconductor layer 13 respectively.
  • Figure 2 is a flow chart of the manufacturing method.
  • step S1 referring to FIG. 2 and FIG. 1, a first P-type semiconductor layer 11 is formed on the semiconductor substrate 10.
  • the first P-type semiconductor layer 11 includes a GaN-based material, and the upper surface 11a is a Ga surface.
  • the semiconductor substrate 10 may be sapphire, silicon carbide, silicon, GaN, or diamond, etc., which is not limited in this embodiment.
  • the GaN-based material of the first P-type semiconductor layer 11 may be at least one of GaN, AlGaN, InGaN, and AlInGaN, which is not limited in this embodiment.
  • the material of the first P-type semiconductor layer 11 is GaN as an example, which can be grown by MOCVD technology.
  • NH 3 and TMGa are N source and Ga source, respectively, and H 2 is a carrier gas.
  • P-type ion doping can be performed while growing GaN, the P-type ion can be Mg, and the Mg source can be CP2Mg.
  • the P-type doping ion may be at least one of calcium, carbon, beryllium, yttrium, and zinc.
  • a buffer layer may be grown on the semiconductor substrate 10 first, and then the first P-type semiconductor layer 11 may be grown on the buffer layer.
  • the arrangement of the buffer layer can reduce the screw dislocation (TD) density in the first P-type semiconductor layer 11 and the TD bending due to the lateral growth mechanism.
  • the upper surface 11a of the first P-type semiconductor layer 11 can be realized as a Ga surface by: In the process of forming the first P-type semiconductor layer 11, the Ga of the first P-type semiconductor layer 11 is grown by epitaxial growth. Face up.
  • step S2 still referring to FIG. 2 and FIG. 1, an N-type semiconductor layer 12 is formed on the first P-type semiconductor layer 11.
  • the N-type semiconductor layer 12 includes a GaN-based material, and the upper surface 12a is an N-face.
  • the GaN-based material of the N-type semiconductor layer 12 may also be at least one of GaN, AlGaN, InGaN, and AlInGaN.
  • the materials of the N-type semiconductor layer 12 and the first P-type semiconductor layer 11 are the same or different.
  • the material of the N-type semiconductor layer 12 is GaN as an example, and it can be grown by MOCVD technology.
  • NH 3 and TMGa are N source and Ga source, respectively, and H 2 is a carrier gas.
  • the N-type dopant ion may be at least one of silicon, germanium, and oxygen.
  • the upper surface 12a of the N-type semiconductor layer 12 can be realized by bonding the Ga surface of the N-type semiconductor layer 12 to the Ga surface of the first P-type semiconductor layer 11 directly.
  • the N-type semiconductor layer 12 epitaxial layer for bonding can be prepared by the following method: a sacrificial layer is provided during the process of preparing an epitaxial layer of GaN-based material with a Ga surface on the upper surface, and then a sacrificial layer is placed on the sacrificial layer Continue to prepare a predetermined thickness of a GaN-based material epitaxial layer whose upper surface is a Ga surface.
  • the sacrificial layer can be, for example, porous GaN, H-implanted GaN, or the like.
  • the GaN-based material epitaxial layer with the upper surface of the sacrificial layer can be peeled from the sacrificial layer, and the GaN-based material epitaxial layer with the upper surface of the Ga surface after the peeling is in contact with the sacrificial layer
  • the face is the N face.
  • the upper surface 12a of the N-type semiconductor layer 12 can be realized as the N-side by: in the process of forming the N-type semiconductor layer 12, the N-side of the N-type semiconductor layer 12 faces upward through a polarity reversal method.
  • the polarity reversal method refers to: first epitaxially grow an N-type semiconductor layer 12 whose upper surface 12a is a Ga surface; then add a polarity reversal element during the epitaxial growth, such as Mg, to achieve an N-surface Face up.
  • a polarity reversal layer on the first P-type semiconductor layer 11, and the material is, for example, Al 2 O 3 ; then continue to grow GaN-based material on the polarity reversal layer so that the N side faces upward.
  • step S3 still referring to FIG. 2 and FIG. 1, a second P-type semiconductor layer 13 is formed on the N-type semiconductor layer 12.
  • the second P-type semiconductor layer 13 includes a GaN-based material, and the upper surface 13a is N surface.
  • the GaN-based material of the second P-type semiconductor layer 13 refers to the GaN-based material of the first P-type semiconductor layer 11, and the two materials may be the same or different.
  • the upper surface 13a of the second P-type semiconductor layer 13 can be realized by bonding the Ga surface of the second P-type semiconductor layer 13 to the Ga surface of the N-type semiconductor layer 12 directly.
  • the second P-type semiconductor layer 13 epitaxial layer used for bonding can be prepared by the following method: a sacrificial layer is provided during the process of preparing an epitaxial layer of GaN-based material with a Ga surface on the upper surface, and then a sacrificial layer is placed on the sacrificial layer. Continue to prepare an epitaxial layer of GaN-based material with a predetermined thickness on the upper surface of the Ga surface.
  • the sacrificial layer can be, for example, porous GaN, H-implanted GaN, or the like.
  • the GaN-based material epitaxial layer with the upper surface of the sacrificial layer can be peeled from the sacrificial layer, and the GaN-based material epitaxial layer with the upper surface of the Ga surface after the peeling is in contact with the sacrificial layer
  • the face is the N face.
  • the upper surface 13a of the second P-type semiconductor layer 13 can be realized as the N-face: in the process of forming the second P-type semiconductor layer 13, the polarity of the second P-type semiconductor layer 13 is reversed. The N side is facing up.
  • the polarity reversal method refers to: first epitaxially grow the second P-type semiconductor layer 13 whose upper surface 13a is a Ga surface; then add a polarity reversal element during the epitaxial growth.
  • the polarity reversal element is, for example, Mg, etc., to achieve The N side is facing up.
  • the material is for example Al 2 O 3 ; then continue to grow a GaN-based material on the polarity reversal layer to achieve the N-side up.
  • step S4 still referring to FIG. 2 and FIG. 1, wet etching removes the second P-type semiconductor layer 13 and the N-type semiconductor layer 12 in the collector region 1 a, and exposes the first P-type semiconductor layer 11.
  • the wet etching solution is, for example, a KOH solution, which is corrosive on the N surface but non-corrosive on the Ga surface. Since the upper surfaces of the second P-type semiconductor layer 13 and the N-type semiconductor layer 12 are both N-planes, and the upper surface 11a of the first P-type semiconductor layer 11 is a Ga-plane, the etching process can automatically stop at the first P-type semiconductor layer. The upper surface 11a of the layer 11 will not over-etch the first P-type semiconductor layer 11.
  • dry etching is generally used to pattern the second P-type semiconductor layer 13 and the N-type semiconductor layer 12.
  • the first P-type semiconductor layer 13 will be over-etched.
  • nitrogen atoms in the GaN-based material preferentially escape, resulting in an increase in the number of electron carriers in the first P-type semiconductor layer 13 and neutralizing part of the hole carriers, resulting in holes
  • the carrier concentration drops, and even the surface inversion appears. Therefore, compared to dry etching, wet etching can avoid the above-mentioned problems in the patterning process.
  • step S5 still referring to FIG. 2 and FIG. 1, dry etching removes the second P-type semiconductor layer 13 in the base region 1 b, and exposes the N-type semiconductor layer 12.
  • the dry etching may be an ICP etching method, the reaction gas may be Cl2, and the auxiliary gas may be N2.
  • the N-type semiconductor layer 12 When the dry etching stops, the N-type semiconductor layer 12 will be over-etched. However, during the dry etching process, nitrogen atoms in the GaN-based material preferentially escape, resulting in an increase in the number of electron carriers.
  • the semiconductor layer 12 reduces the surface resistivity, which is beneficial to reduce the contact resistance of the electrical connection structure on the N-type semiconductor layer 12.
  • FIG. 3 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention.
  • the semiconductor structure 2 of the second embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, except that the semiconductor substrate 10 is omitted.
  • FIG. 4 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 3. 4, the manufacturing method of the second embodiment is substantially the same as the manufacturing method of the first embodiment. The only difference is: Step S1': a first P-type semiconductor layer 11 is provided, and the first P-type semiconductor layer 11 includes a GaN-based semiconductor layer. Material, and the upper surface 11a is a Ga surface. In other words, the first P-type semiconductor layer 11 of this embodiment may be a ready-made semiconductor intermediate structure.
  • FIG. 5 is a flowchart of a manufacturing method of a semiconductor structure according to a third embodiment of the present invention.
  • the manufacturing method of the third embodiment is roughly the same as the manufacturing methods of the first and second embodiments, except that step S11 is added to activate the P in the first P-type semiconductor layer 11. Type doping ions. Step S11 is performed between steps S1 and S2.
  • the P-type dopant ion can be magnesium, and the activation can be achieved by high-temperature annealing.
  • MOCVD technology grows P-type GaN-based materials, because there are a large number of H atoms in the MOCVD growth environment, if H atoms cannot be released, the acceptor dopant Mg in GaN easily forms covalent bonds with H atoms and cannot generate holes , Which is passivated by H atoms. In this step, the upper surface 11a of the first P-type semiconductor layer 11 is not blocked, so H atoms are easily released.
  • a large number of P-type doped ions Mg can form covalent bonds with atoms in the GaN-based material, that is, are activated to avoid passivation.
  • a large amount of Mg forms a covalent bond with atoms in the GaN-based material, which can also prevent free Mg ions from entering the N-type GaN-based material layer grown on it, and improve the quality of the PN junction.
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • the semiconductor structure 3 of the fourth embodiment is substantially the same as the semiconductor structures 1 and 2 of the first, second, and third embodiments. The only difference is: the exposed first P-type semiconductor layer 11 has a collector C, and the N-type semiconductor layer 12 is It has a base B, and the second P-type semiconductor layer 13 has an emitter E.
  • the materials of the collector C, the base B and the emitter E can all be metals or semiconductor materials with good conductivity after being doped.
  • FIG. 7 is a schematic structural diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • the semiconductor structure 4 of the fifth embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, except that the semiconductor structure 4 includes:
  • the semiconductor substrate 10, the N-type semiconductor layer 12 and the second P-type semiconductor layer 13 distributed from bottom to top; among them:
  • the N-type semiconductor layer 12 includes a GaN-based material, and the upper surface 12a is a Ga surface; the second P-type semiconductor layer 13 includes a GaN-based material, and the upper surface 13a is an N-surface; a part of the Ga surface of the N-type semiconductor layer 12 is exposed .
  • the N-type semiconductor layer 12 and the second P-type semiconductor layer 13 in this embodiment form a PN junction.
  • the exposed area of the upper surface 12a of the N-type semiconductor layer 12 and the upper surface 13a of the second P-type semiconductor layer 13 may form an electrical connection structure, such as a metal interconnection structure, to separate the N-type semiconductor layer 12 and the second P-type semiconductor layer 12 from each other.
  • the electrical signal of layer 13 is led out.
  • the semiconductor substrate 10 may also be omitted.
  • FIG. 8 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 7.
  • the manufacturing method includes:
  • Step S2' providing an N-type semiconductor layer 12, the N-type semiconductor layer 12 includes a GaN-based material, and the upper surface 12a is a Ga surface;
  • Step S3 forming a second P-type semiconductor layer 13 on the N-type semiconductor layer 12, the second P-type semiconductor layer 13 includes a GaN-based material, and the upper surface 13a is an N-face;
  • Step S4' the second P-type semiconductor layer 13 in a partial area is removed by wet etching, and the N-type semiconductor layer 12 is exposed.
  • the directionality of wet etching is used to make the etching start from the N surface of the second P-type semiconductor layer 13 and automatically stop at the Ga surface of the N-type semiconductor layer 12, which can avoid over-etching.

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Abstract

本申请提供了一种半导体结构及其制作方法，制作方法中，提供第一P型半导体层，在第一P型半导体层上依次形成N型半导体层与第二P型半导体层，第一P型半导体层、N型半导体层以及第二P型半导体层都包括GaN基材料；其中，所提供的第一P型半导体层中，控制上表面为Ga面；形成N型半导体层时，控制上表面为N面；形成第二P型半导体层时，控制上表面为N面。利用湿法刻蚀的方向性，使得从第二P型半导体层的N面开始刻蚀，自动停止于第一P型半导体层的Ga面，可以避免第一P型半导体层的过刻蚀以及空穴载流子浓度下降。之后干法刻蚀第二P型半导体层，停止于N型半导体层的上表面，有利于降低N型半导体层的电连接结构的接触电阻。

Description

半导体结构及其制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
III-氮化物是继Si、GaAs等第一、第二代半导体材料之后的第三代新型半导体材料，其中GaN作为宽禁带半导体材料有许多优点，诸如饱和漂移速度高、击穿电压大、载流子输运性能优异以及能够形成AlGaN、InGaN三元合金和AlInGaN四元合金等，容易制作GaN基的PN结。鉴于此，近几年来GaN基材料和半导体器件得到了广泛和深入的研究，MOCVD技术生长GaN基材料日趋成熟；在半导体器件研究方面，GaN基LED、LDs等光电子器件以及GaN基HEMT等微电子器件方面的研究都取得了显著的成绩和长足的发展。
目前GaN基半导体器件仍有改进空间。问题之一在于：在P型GaN基半导体层和/或N型GaN基半导体层上制作接触电极时存在过刻蚀问题。
有鉴于此，实有必要提供一种新的半导体结构及其制作方法，以解决上述技术问题。
发明内容
本发明的发明目的是提供一种半导体结构及其制作方法，提高GaN基半导体器件的性能。
为实现上述目的，本发明的第一方面提供一种半导体结构的制作方法，包括：
提供第一P型半导体层，所述第一P型半导体层包括GaN基材料，且上表面为Ga面；
在所述第一P型半导体层上形成N型半导体层，所述N型半导体层包括GaN基材料，且上表面为N面；
在所述N型半导体层上形成第二P型半导体层，所述第二P型半导体层包括GaN基材料，且上表面为N面；
湿法刻蚀去除集电极区域的第二P型半导体层与N型半导体层，暴露所述第一P型半导体层；干法刻蚀去除基极区域的第二P型半导体层，暴露所述N型半导体层。
GaN晶体为钎锌矿结构，其中Ga、N原子层呈ABABAB六方层堆垛，每个Ga(N)原子都与周围的4个N(Ga)原子呈类金刚石四面体结构成键。需要说明的是，以平行于C轴([0001]晶向)的Ga-N键作为参照，若每一个Ga-N键中的Ga原子更远离衬底，则上表面为Ga面；若每一个Ga-N键中的N原子更远离衬底，则上表面为N面。
可选地，在所述第一P型半导体层上形成N型半导体层前，激活所述第一P型半导体层中的P型掺杂离子。
可选地，在集电极区域的第一P型半导体层上形成集电极、在基极区域的N型半导体层上形成基极，以及在发射极区域的第二P型半导体层上形成发射极。
可选地，在所述第一P型半导体层上形成上表面为N面的N型半导体层通过：将所述N型半导体层的Ga面直接与所述第一P型半导体层的Ga面键合。
可选地，在所述第一P型半导体层上形成上表面为N面的N型半导体 层通过：形成N型半导体层的过程中，通过极性反转的方式使所述N型半导体层的N面朝上。
可选地，在所述N型半导体层上形成上表面为N面的第二P型半导体层通过：将所述第二P型半导体层的Ga面直接与所述N型半导体层的N面键合。
可选地，在所述N型半导体层上形成上表面为N面的第二P型半导体层通过：形成第二P型半导体层的过程中，通过极性反转的方式使所述第二P型半导体层的N面朝上。
可选地，所述GaN基材料为GaN、AlGaN、InGaN、AlInGaN中的至少一种。
本发明的第二方面提供一种半导体结构的制作方法，包括：
提供N型半导体层，所述N型半导体层包括GaN基材料，且上表面为Ga面；
在所述N型半导体层上形成第二P型半导体层，所述第二P型半导体层包括GaN基材料，且上表面为N面；
湿法刻蚀去除部分区域的第二P型半导体层，暴露所述N型半导体层。
可选地，在所述N型半导体层上形成上表面为N面的第二P型半导体层通过：将所述第二P型半导体层的Ga面直接与所述N型半导体层的Ga面键合。
可选地，在所述N型半导体层上形成上表面为N面的第二P型半导体层通过：形成第二P型半导体层的过程中，通过极性反转的方式使所述第二P型半导体层的N面朝上。
本发明的第三方面提供一种半导体结构，包括：
自下而上分布的第一P型半导体层、N型半导体层以及第二P型半导 体层；其中：
所述第一P型半导体层包括GaN基材料，且上表面为Ga面；所述N型半导体层包括GaN基材料，且上表面为N面；所述第二P型半导体层包括GaN基材料，且上表面为N面；所述第一P型半导体层的Ga面与所述N型半导体层的N面的部分区域裸露。
可选地，所述裸露的第一P型半导体层上具有集电极，N型半导体层上具有基极，第二P型半导体层上具有发射极。
本发明的第四方面提供一种半导体结构，包括：
自下而上分布的N型半导体层与第二P型半导体层；其中：
所述N型半导体层包括GaN基材料，且上表面为Ga面；所述第二P型半导体层包括GaN基材料，且上表面为N面；所述N型半导体层的Ga面的部分区域裸露。
与现有技术相比，本发明的有益效果在于：
1)本发明的半导体结构制作方法中，先提供第一P型半导体层，第一P型半导体层包括GaN基材料；再在第一P型半导体层上形成N型半导体层，N型半导体层包括GaN基材料；之后在N型半导体层上形成第二P型半导体层，第二P型半导体层包括GaN基材料；其中，所提供的第一P型半导体层中时，控制上表面为Ga面；形成N型半导体层时，控制上表面为N面；形成第二P型半导体层时，控制上表面为N面。利用湿法刻蚀的方向性，使得从第二P型半导体层的N面开始刻蚀，自动停止于第一P型半导体层的Ga面，可以避免过刻蚀。若采用干法刻蚀，干法刻蚀停止时，会对第一P型半导体层过刻蚀；由于干法刻蚀过程中，GaN基材料中的氮原子优先逸出，造成电子载流子数量变多，对于P型半导体层，会中和部分空穴载流子，造成空穴载流子浓度下降，甚至出现表面反型；因而相对于干法刻蚀，湿法刻蚀可以避免形成P型半导体层的电连接结构过程中的上述问题。之后干法刻蚀 第二P型半导体层，停止于N型半导体层的上表面，干法刻蚀停止时，会对N型半导体层过刻蚀，GaN基材料中的氮原子优先逸出造成电子载流子数量变多，对于N型半导体层，会降低表面的电阻率，有利于降低N型半导体层的电连接结构的接触电阻。
2)可选方案中，在第一P型半导体层上形成N型半导体层前，激活第一P型半导体层中的P型掺杂离子。本方案可以为释放的H原子提供逸出路径，提高PNP双极晶体管的质量，这是因为：MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉积)技术生长P型GaN基材料时，MOCVD生长环境中存在大量的H原子，若不移除，GaN中的受主掺杂剂Mg会被大量H原子钝化而不产生空穴；此外，大量的被钝化、未成键的Mg离子会进入其上面生长的N型GaN基材料层，造成PN结结面模糊并使得部分N型GaN基材料层被补偿、电子浓度降低，严重时会造成PN结失效。
3)可选方案中，在第一P型半导体层上形成上表面为N面的N型半导体层通过：a)将N型半导体层的Ga面直接与第一P型半导体层的Ga面键合；或b)形成N型半导体层的过程中，通过极性反转的方式使N型半导体层的N面朝上。可选方案中，在N型半导体层上形成上表面为N面的第二P型半导体层通过：a)将第二P型半导体层的Ga面直接与N型半导体层的N面键合；或b)形成第二P型半导体层的过程中，通过极性反转的方式使第二P型半导体层的N面朝上。研究表明，上述两种方法工艺可靠。
附图说明
图1是本发明第一实施例的半导体结构的结构示意图；
图2是图1中的半导体结构的制作方法的流程图；
图3是本发明第二实施例的半导体结构的结构示意图；
图4是图3中的半导体结构的制作方法的流程图；
图5是本发明第三实施例的半导体结构的制作方法的流程图；
图6是本发明第四实施例的半导体结构的结构示意图；
图7是本发明第五实施例的半导体结构的结构示意图；
图8是图7中的半导体结构的制作方法的流程图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
半导体结构1、2、3、4    半导体衬底10
第一P型半导体层11       第一P型半导体层的上表面11a
N型半导体层12           N型半导体层的上表面12a
第二P型半导体层13       第二P型半导体层的上表面12a
集电极区域1a            基极区域1b
发射极区域1c            集电极C
基极B                   发射极E
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的半导体结构的结构示意图。
参照图1所示，本实施例一的半导体结构1包括：
自下而上分布的半导体衬底10、第一P型半导体层11、N型半导体层12以及第二P型半导体层13；其中：
第一P型半导体层11包括GaN基材料，且上表面11a为Ga面；N型 半导体层12包括GaN基材料，且上表面12a为N面；第二P型半导体层13包括GaN基材料，且上表面13a为N面；第一P型半导体层11的Ga面与N型半导体层12的N面的部分区域裸露。
上述半导体结构1可以为PNP双极晶体管。
半导体衬底10可以为蓝宝石、碳化硅、硅、GaN或金刚石等，本实施例对此不加以限制。GaN基材料可以为GaN、AlGaN、InGaN、AlInGaN中的至少一种，本实施例对此也不加以限制。
第一P型半导体层11的上表面11a为Ga面是指：以平行于C轴([0001]晶向)的Ga-N键作为参照，每一个Ga-N键中的Ga原子更远离半导体衬底10。可以理解的是，此时，第一P型半导体层11的下表面为N面。
N型半导体层12的上表面12a、第二P型半导体层13的上表面13a为N面是指：以平行于C轴([0001]晶向)的Ga-N键作为参照，每一个Ga-N键中的N原子更远离半导体衬底10。可以理解的是，此时，N型半导体层12、第二P型半导体层13的下表面为Ga面。
第一P型半导体层11的上表面11a的裸露区域、N型半导体层12的上表面12a的裸露区域与第二P型半导体层13的上表面13a可以形成电连接结构，例如金属互连结构，以分别将第一P型半导体层11、N型半导体层12与第二P型半导体层13的电信号引出。
对于图1中的半导体结构1，本发明一实施例中提供了对应的制作方法。图2为制作方法的流程图。
首先，步骤S1：参照图2与图1所示，在半导体衬底10上形成第一P型半导体层11，第一P型半导体层11包括GaN基材料，且上表面11a为Ga面。
半导体衬底10可以为蓝宝石、碳化硅、硅、GaN或金刚石等，本实施例对此不加以限制。
第一P型半导体层11的GaN基材料可以为GaN、AlGaN、InGaN、AlInGaN中的至少一种，本实施例对此也不加以限制。
第一P型半导体层11的材料以GaN为例，可以通过MOCVD技术生长。示例性地，NH 3、TMGa分别为N源和Ga源，H 2为载气。具体地，可以边生长GaN，边进行P型离子掺杂，P型离子可以为Mg，Mg源可以为CP2Mg。其它可选方案中，P型掺杂离子可以为钙、碳、铍、钇和锌中的至少一种。
一个可选方案中，可以先在半导体衬底10上生长缓冲层，再在缓冲层上生长第一P型半导体层11。缓冲层的设置可以减小第一P型半导体层11中的螺位错(TD)密度以及由于横向生长机制导致的TD弯曲。
一个可选方案中，实现第一P型半导体层11的上表面11a为Ga面可以通过：形成第一P型半导体层11的过程中，通过外延生长方式使第一P型半导体层11的Ga面朝上。
接着，步骤S2：仍参照图2与图1所示，在第一P型半导体层11上形成N型半导体层12，N型半导体层12包括GaN基材料，且上表面12a为N面。
N型半导体层12的GaN基材料也可以为GaN、AlGaN、InGaN、AlInGaN中的至少一种。N型半导体层12与第一P型半导体层11的材料相同或不同。
N型半导体层12的材料以GaN为例，可以通过MOCVD技术生长。示例性地，NH 3、TMGa分别为N源和Ga源，H 2为载气。N型掺杂离子可以为硅、锗和氧中的至少一种。
一个可选方案中，实现N型半导体层12的上表面12a为N面可以通过：将N型半导体层12的Ga面直接与第一P型半导体层11的Ga面键合。
在一个可选方案中，用于键合的N型半导体层12外延层，可通过如下方法制备：制备上表面为Ga面的GaN基材料外延层过程中设置牺牲层，然后在该牺牲层上继续制备预定厚度的上表面为Ga面的GaN基材料外延层。 该牺牲层可例如多孔GaN、H注入后的GaN等。制备完成后，通过退火等工艺，该牺牲层上方的上表面为Ga面的GaN基材料外延层可从牺牲层处剥离，剥离后的上表面为Ga面的GaN基材料外延层与牺牲层接触的面即为N面。
一个可选方案中，实现N型半导体层12的上表面12a为N面可以通过：形成N型半导体层12的过程中，通过极性反转方式使N型半导体层12的N面朝上。
极性反转方式是指：首先外延生长上表面12a为Ga面的N型半导体层12；接着在外延生长的同时添加极性反转元素，极性反转元素例如为Mg等，实现N面朝上。
此外，还可以：首先在第一P型半导体层11上制作极性反转层，材料例如为Al 2O 3；接着在极性反转层上继续生长GaN基材料，实现N面朝上。
再接着，步骤S3：仍参照图2与图1所示，在N型半导体层12上形成第二P型半导体层13，第二P型半导体层13包括GaN基材料，且上表面13a为N面。
第二P型半导体层13的GaN基材料参照第一P型半导体层11的GaN基材料，两者材料可以相同，也可以不同。
一个可选方案中，实现第二P型半导体层13的上表面13a为N面可以通过：将第二P型半导体层13的Ga面直接与N型半导体层12的Ga面键合。
在一个可选方案中，用于键合的第二P型半导体层13外延层，可通过如下方法制备：制备上表面为Ga面的GaN基材料外延层过程中设置牺牲层，然后在该牺牲层上继续制备预定厚度的上表面为Ga面的GaN基材料外延层。该牺牲层可例如多孔GaN、H注入后的GaN等。制备完成后，通过退火等工艺，该牺牲层上方的上表面为Ga面的GaN基材料外延层可从牺牲层处剥离，剥离后的上表面为Ga面的GaN基材料外延层与牺牲层接触的面即为N面。
一个可选方案中，实现第二P型半导体层13的上表面13a为N面可以 通过：形成第二P型半导体层13的过程中，通过极性反转方式使第二P型半导体层13的N面朝上。
极性反转方式是指：首先外延生长上表面13a为Ga面的第二P型半导体层13；接着在外延生长的同时添加极性反转元素，极性反转元素例如为Mg等，实现N面朝上。
此外，还可以：首先在N型半导体层12上制作极性反转层，材料例如为Al 2O 3；接着在极性反转层上继续生长GaN基材料，实现N面朝上。
之后，步骤S4：仍参照图2与图1所示，湿法刻蚀去除集电极区域1a的第二P型半导体层13与N型半导体层12，暴露所述第一P型半导体层11。
湿法刻蚀溶液例如为KOH溶液，它在N表面上是腐蚀性的，但在Ga表面上是非腐蚀性的。由于第二P型半导体层13与N型半导体层12的上表面都为N面，第一P型半导体层11的上表面11a为Ga面，因而刻蚀工序可以自动停止在第一P型半导体层11的上表面11a，不会出现对第一P型半导体层11的过刻蚀。
现有技术中，一般采用干法刻蚀对第二P型半导体层13与N型半导体层12进行图形化。干法刻蚀停止时，会对第一P型半导体层13过刻蚀。由于干法刻蚀过程中，GaN基材料中的氮原子优先逸出，造成第一P型半导体层13中的电子载流子数量变多，会中和部分空穴载流子，造成空穴载流子浓度下降，甚至出现表面反型。因而相对于干法刻蚀，湿法刻蚀可以避免图形化过程中的上述问题。
接着，步骤S5：仍参照图2与图1所示，干法刻蚀去除基极区域1b的第二P型半导体层13，暴露N型半导体层12。
干法刻蚀可以为ICP刻蚀法，反应气体可以为Cl2，辅助气体可以为N2。
干法刻蚀停止时，会对N型半导体层12过刻蚀，但由于干法刻蚀过程 中，GaN基材料中的氮原子优先逸出，造成电子载流子数量变多，对于N型半导体层12，会降低表面的电阻率，有利于降低N型半导体层12上的电连接结构的接触电阻。
图3是本发明第二实施例的半导体结构的结构示意图。参照图3所示，本实施例二的半导体结构2与实施例一的半导体结构1大致相同，区别仅在于：省略了半导体衬底10。
需要说明的是，以平行于C轴([0001]晶向)的Ga-N键作为参照，若每一个Ga-N键中的Ga原子更远离下表面，则上表面为Ga面。
图4是图3中的半导体结构的制作方法的流程图。参照图4所示，本实施例二的制作方法与实施例一的制作方法大致相同，区别仅在于：步骤S1'：提供第一P型半导体层11，第一P型半导体层11包括GaN基材料，且上表面11a为Ga面。换言之，本实施例的第一P型半导体层11可以为现成的半导体中间结构。
图5是本发明第三实施例的半导体结构的制作方法流程图。参照图5、图2与图4所示，本实施例三的制作方法与实施例一、二的制作方法大致相同，区别仅在于：增加步骤S11，激活第一P型半导体层11中的P型掺杂离子。步骤S11在步骤S1与S2之间进行。
P型掺杂离子可以为镁，激活可以通过高温退火实现。MOCVD技术生长P型GaN基材料时，由于MOCVD生长环境中存在大量的H原子，若H原子无法释放，则GaN中的受主掺杂剂Mg容易与H原子形成共价键而无法产生空穴，即被H原子钝化。本步骤第一P型半导体层11上表面11a无遮挡，因而容易释放H原子，大量P型掺杂离子Mg可与GaN基材料中的原子形成共价键，即被激活而避免钝化。
此外，大量的Mg与GaN基材料中的原子形成共价键，也能避免游离态的Mg离子进入其上面生长的N型GaN基材料层，提高PN结质量。
图6是本发明第四实施例的半导体结构的结构示意图。本实施例四的半导体结构3与实施例一、二、三的半导体结构1、2大致相同，区别仅在于：裸露的第一P型半导体层11上具有集电极C，N型半导体层12上具有基极B，第二P型半导体层13上具有发射极E。
集电极C与第一P型半导体层11之间，基极B与N型半导体层12之间，发射极E与第二P型半导体层13之间都为欧姆接触。
集电极C、基极B与发射极E的材料都可以为金属或经掺杂后导电性能佳的半导体材料。
图7是本发明第五实施例的半导体结构的结构示意图。本实施例五的半导体结构4与实施例一的半导体结构1大致相同，区别仅在于：半导体结构4包括：
自下而上分布的半导体衬底10、N型半导体层12与第二P型半导体层13；其中：
N型半导体层12包括GaN基材料，且上表面12a为Ga面；第二P型半导体层13包括GaN基材料，且上表面13a为N面；N型半导体层12的Ga面的部分区域裸露。
可以看出，本实施例中的N型半导体层12与第二P型半导体层13形成PN结。
N型半导体层12的上表面12a的裸露区域与第二P型半导体层13的上表面13a可以形成电连接结构，例如金属互连结构，以分别将N型半导体层12与第二P型半导体层13的电信号引出。
一些实施例中，也可以省略半导体衬底10。
图8是图7中的半导体结构的制作方法的流程图。
参照图8所示，制作方法包括：
步骤S2'：提供N型半导体层12，N型半导体层12包括GaN基材料，且上表面12a为Ga面；
步骤S3：在N型半导体层12上形成第二P型半导体层13，第二P型半导体层13包括GaN基材料，且上表面13a为N面；
步骤S4'：湿法刻蚀去除部分区域的第二P型半导体层13，暴露N型半导体层12。
上述各步骤请参照前述实施例中的各步骤，本实施例在此不再赘述。
本实施例中，利用湿法刻蚀的方向性，使得从第二P型半导体层13的N面开始刻蚀，自动停止于N型半导体层12的Ga面，可以避免过刻蚀。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (14)

  1. 一种半导体结构的制作方法，其特征在于，包括：
    提供第一P型半导体层(11)，所述第一P型半导体层(11)包括GaN基材料，且上表面(11a)为Ga面；
    在所述第一P型半导体层(11)上形成N型半导体层(12)，所述N型半导体层(12)包括GaN基材料，且上表面(12a)为N面；
    在所述N型半导体层(12)上形成第二P型半导体层(13)，所述第二P型半导体层(13)包括GaN基材料，且上表面(13a)为N面；
    湿法刻蚀去除集电极区域(1a)的第二P型半导体层(13)与N型半导体层(12)，暴露所述第一P型半导体层(11)；
    干法刻蚀去除基极区域(1b)的第二P型半导体层(13)，暴露所述N型半导体层(12)。
  2. 根据权利要求1所述的半导体结构的制作方法，其特征在于，在所述第一P型半导体层(11)上形成N型半导体层(12)前，激活所述第一P型半导体层(11)中的P型掺杂离子。
  3. 根据权利要求1所述的半导体结构的制作方法，其特征在于，在集电极区域(1a)的第一P型半导体层(11)上形成集电极(C)、在基极区域(1b)的N型半导体层(12)上形成基极(B)，以及在发射极区域(1c)的第二P型半导体层(13)上形成发射极(E)。
  4. 根据权利要求1至3任一项所述的半导体结构的制作方法，其特征在于，在所述第一P型半导体层(11)上形成上表面(12a)为N面的N型半导体层(12)通过：将所述N型半导体层(12)的Ga面直接与所述第一P型半导体层(11)的Ga面键合。
  5. 根据权利要求1至3任一项所述的半导体结构的制作方法，其特征在于，在所述第一P型半导体层(11)上形成上表面(12a)为N面的N型半导体层(12)通过：形成N型半导体层(12)的过程中，通过极性反转的方 式使所述N型半导体层(12)的N面朝上。
  6. 根据权利要求1至3任一项所述的半导体结构的制作方法，其特征在于，在所述N型半导体层(12)上形成上表面(13a)为N面的第二P型半导体层(13)通过：将所述第二P型半导体层(13)的Ga面直接与所述N型半导体层(12)的N面键合。
  7. 根据权利要求1至3任一项所述的半导体结构的制作方法，其特征在于，在所述N型半导体层(12)上形成上表面(13a)为N面的第二P型半导体层(13)通过：形成第二P型半导体层(13)的过程中，通过极性反转的方式使所述第二P型半导体层(13)的N面朝上。
  8. 根据权利要求1所述的半导体结构的制作方法，其特征在于，所述GaN基材料为GaN、AlGaN、InGaN、AlInGaN中的至少一种。
  9. 一种半导体结构的制作方法，其特征在于，包括：
    提供N型半导体层(12)，所述N型半导体层(12)包括GaN基材料，且上表面(12a)为Ga面；
    在所述N型半导体层(12)上形成第二P型半导体层(13)，所述第二P型半导体层(13)包括GaN基材料，且上表面(13a)为N面；
    湿法刻蚀去除部分区域的第二P型半导体层(13)，暴露所述N型半导体层(12)。
  10. 根据权利要求9所述的半导体结构的制作方法，其特征在于，在所述N型半导体层(12)上形成上表面(13a)为N面的第二P型半导体层(13)通过：将所述第二P型半导体层(13)的Ga面直接与所述N型半导体层(12)的Ga面键合。
  11. 根据权利要求9所述的半导体结构的制作方法，其特征在于，在所述N型半导体层(12)上形成上表面(13a)为N面的第二P型半导体层(13)通过：形成第二P型半导体层(13)的过程中，通过极性反转的方式使所述第二P型半导体层(13)的N面朝上。
  12. 一种半导体结构，其特征在于，包括：
    自下而上分布的第一P型半导体层(11)、N型半导体层(12)以及第二P型半导体层(13)；其中：
    所述第一P型半导体层(11)包括GaN基材料，且上表面(11a)为Ga面；所述N型半导体层(12)包括GaN基材料，且上表面(12a)为N面；所述第二P型半导体层(13)包括GaN基材料，且上表面(13a)为N面；所述第一P型半导体层(11)的Ga面与所述N型半导体层(12)的N面的部分区域裸露。
  13. 根据权利要求12所述的半导体结构，其特征在于，所述裸露的第一P型半导体层(11)上具有集电极(C)，N型半导体层(12)上具有基极(B)，所述第二P型半导体层(13)上具有发射极(E)。
  14. 一种半导体结构，其特征在于，包括：
    自下而上分布的N型半导体层(12)与第二P型半导体层(13)；其中：
    所述N型半导体层(12)包括GaN基材料，且上表面(12a)为Ga面；所述第二P型半导体层(13)包括GaN基材料，且上表面(13a)为N面；所述N型半导体层(12)的Ga面的部分区域裸露。
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CN110504330A (zh) * 2019-07-29 2019-11-26 广微集成技术（深圳）有限公司 一种肖特基二极管及其制备方法

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