WO2022217539A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

Info

Publication number
WO2022217539A1
WO2022217539A1 PCT/CN2021/087487 CN2021087487W WO2022217539A1 WO 2022217539 A1 WO2022217539 A1 WO 2022217539A1 CN 2021087487 W CN2021087487 W CN 2021087487W WO 2022217539 A1 WO2022217539 A1 WO 2022217539A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor layer
semiconductor
silicon substrate
active layer
Prior art date
Application number
PCT/CN2021/087487
Other languages
English (en)
French (fr)
Inventor
程凯
张丽旸
Original Assignee
苏州晶湛半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州晶湛半导体有限公司 filed Critical 苏州晶湛半导体有限公司
Priority to CN202180096215.6A priority Critical patent/CN117063302A/zh
Priority to PCT/CN2021/087487 priority patent/WO2022217539A1/zh
Priority to US18/549,479 priority patent/US20240154063A1/en
Priority to TW111113418A priority patent/TWI833198B/zh
Publication of WO2022217539A1 publication Critical patent/WO2022217539A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004—Devices characterised by their operation
    • H01L33/002—Devices characterised by their operation having heterojunctions or graded gap
    • H01L33/0025—Devices characterised by their operation having heterojunctions or graded gap comprising only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • Group III nitrides are the third generation of new semiconductor materials after the first and second generation semiconductor materials such as Si and GaAs. They have many advantages such as high saturation drift speed, high breakdown voltage, and excellent carrier transport performance.
  • group III nitride materials and semiconductor devices have been extensively and deeply studied in recent years, and MOCVD (Metal-organic Chemical Vapor Deposition, metal organic chemical vapor deposition) technology to grow group III nitride materials is becoming more and more mature; in semiconductor devices
  • MOCVD Metal-organic Chemical Vapor Deposition, metal organic chemical vapor deposition
  • the purpose of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which can meet the demands of the industry for LED structures with good color rendering properties and freely adjustable emission wavelengths.
  • a first aspect of the present invention provides a semiconductor structure, comprising:
  • the silicon substrate has several through-silicon vias
  • first semiconductor layer located in each of the through silicon vias and on the silicon substrate, an active layer located on the first semiconductor layer, and a second semiconductor layer located on the active layer, so
  • the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer, and the materials of the first semiconductor layer, the active layer and the second semiconductor layer are group III nitrides.
  • the active layer is located only on the top surface of the first semiconductor layer.
  • the active layer contains In element; the smaller the size of the top surface of the first semiconductor layer, the larger the composition of In element of the active layer; the top surface of the first semiconductor layer is The larger the size of , the smaller the In element composition of the active layer.
  • dielectric layer between the first semiconductor layer and the upper surface of the silicon substrate.
  • the dielectric layer is also provided on the sidewall of the through silicon via.
  • the active layer is located on top and side surfaces of the first semiconductor layer.
  • the active layer contains In element; the included angle between the side surface and the top surface ranges from 40° to 70°; the In element of the active layer on the top surface
  • the composition of the element is larger than the composition of the In element of the active layer on the side surface.
  • a cross section of the first semiconductor layer along the thickness direction is triangular, and the active layer is located only on a side surface of the first semiconductor layer.
  • the material of the dielectric layer includes at least one of silicon dioxide, silicon nitride and aluminum oxide.
  • the aspect ratio of the through silicon via is greater than 1:1.
  • the distribution of the active layer on the first semiconductor layer at at least one of the through silicon vias is different from that at other through silicon vias. distribution of the active layer on the first semiconductor layer.
  • a common electrode is provided on a side of the silicon substrate away from the second semiconductor layer, and the common electrode is electrically connected to the through silicon vias in each through silicon via. the first semiconductor layer.
  • the semiconductor structure further includes: a group III nitride epitaxial layer on the first substrate, the group III nitride epitaxial layer and the silicon substrate are bonded together by a bonding layer, the There are several first through holes in the bonding layer, and each of the first through holes is communicated with the corresponding through silicon through holes; the first semiconductor layer is also located in the first through holes, so as to communicate with all the first through holes.
  • the group III nitride epitaxial layer is connected.
  • a common electrode is provided on the sidewall of the silicon substrate and/or the group III nitride epitaxial layer, and the common electrode is The first semiconductor layer in each of the through silicon vias is electrically connected.
  • the material of the first substrate includes: at least one of sapphire, silicon carbide and silicon.
  • the material of the bonding layer is silicon dioxide or silicon nitride.
  • a second aspect of the present invention provides a method for fabricating a semiconductor structure, comprising:
  • a silicon substrate and a group III nitride epitaxial layer on the first substrate are respectively provided, and a bonding layer is provided between the group III nitride epitaxial layer and the silicon substrate; the bonding layer is used to connect the The group III nitride epitaxial layer is bonded with the silicon substrate;
  • the silicon substrate and the bonding layer are patterned to form a plurality of through-silicon vias and a plurality of first through holes, each of which exposes the III-nitride epitaxial layer;
  • the through-silicon via is communicated with the corresponding first through-hole;
  • An active layer and a second semiconductor layer are epitaxially grown on the first semiconductor layer in sequence, the conductivity type of the second semiconductor layer is opposite to the conductivity type of the first semiconductor layer, the first semiconductor layer, the The materials of the active layer and the second semiconductor layer are group III nitrides.
  • the active layer is formed only on the top surface of the first semiconductor layer through a mask layer or an etching method.
  • the active layer contains In element; the smaller the size of the top surface of the first semiconductor layer, the larger the composition of In element of the active layer; the top surface of the first semiconductor layer is The larger the size of , the smaller the In element composition of the active layer.
  • a patterned dielectric layer is formed on the patterned silicon substrate.
  • a dielectric layer is formed on the side of the silicon substrate away from the group III nitride epitaxial layer; the dielectric layer and the silicon substrate Patterning is performed in the same process, or the dielectric layer is first patterned, and then the silicon substrate is etched using the patterned dielectric layer as a mask.
  • the dielectric layer is also formed on the sidewall of the through silicon via.
  • the active layer is formed on top and side surfaces of the first semiconductor layer.
  • the active layer contains In element; the included angle between the side surface and the top surface ranges from 40° to 70°; the In element of the active layer on the top surface
  • the composition of the element is larger than the composition of the In element of the active layer on the side surface.
  • a cross section of the first semiconductor layer along the thickness direction is triangular, and the active layer is formed only on a side surface of the first semiconductor layer.
  • the manufacturing method further includes: etching the bonding layer to lift the group III nitride epitaxial layer from the silicon substrate.
  • the aspect ratio of the through-silicon vias formed in it is generally large, which is not suitable for
  • the group III nitride epitaxial layer is epitaxially grown to form the first semiconductor layer, the extension of dislocations in the first semiconductor layer is limited, and the probability of annihilation in the interior and sidewalls of the through silicon via is increased, so that the dislocation density can be formed
  • the small first semiconductor layer, the active layer and the second semiconductor layer improve the color rendering of the LED structure.
  • the aspect ratio of the through silicon via is greater than 1:1.
  • the above aspect ratio can further limit the extension of dislocations in the first semiconductor layer and increase the probability of annihilation in the interior and sidewalls of the TSV.
  • the active layer is located only on the top surface of the first semiconductor layer.
  • the active layer may contain wavelength-sensitive elements such as In element.
  • the aspect ratio of the TSV By controlling the aspect ratio of the TSV to be different, the size of the top surface of the epitaxially grown first semiconductor layer corresponding to the TSV is different. Therefore, the composition size of the wavelength-sensitive elements such as In element in the active layer epitaxially grown on the corresponding first semiconductor layer is different, and the light emission wavelength of the LED structure is also different.
  • the smaller the size of the top surface of the first semiconductor layer the larger the composition of the In element in the active layer, and the longer the emission wavelength of the LED structure; the larger the size of the top surface of the first semiconductor layer, the larger the active layer.
  • the smaller the composition of the In element the shorter the emission wavelength of the LED structure.
  • the active layer is located on the top surface and the side surface of the first semiconductor layer.
  • the conditions of the epitaxial growth process can be controlled so that the angle between the side surface and the top surface of the first semiconductor layer ranges from 40° to 70°. Since the top surface is a (0001) crystal plane, the doping efficiency of In in the active layer is greater than that in the active layer on the semipolar surface of the side surface.
  • the composition of the In element is larger than that of the active layer located on the side surface. The larger the composition of the In element, the longer the corresponding emission wavelength.
  • the active layer is only located on the side surface of the first semiconductor layer.
  • the conditions of the epitaxial growth process can also be controlled so that the angle between the side surface of the first semiconductor layer and the upper surface of the silicon substrate ranges from 40° to 70°.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure according to a first embodiment of the present invention
  • FIG. 2 to 6 are schematic diagrams of intermediate structures corresponding to the process in FIG. 1;
  • FIG. 7 is a schematic cross-sectional structure diagram of the semiconductor structure according to the first embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional structure diagram of a semiconductor structure according to a second embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional structure diagram of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional structure diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • FIG. 11 is a schematic cross-sectional structural diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure according to a first embodiment of the present invention
  • FIGS. 2 to 6 are schematic diagrams of intermediate structures corresponding to the process in FIG. 1
  • FIG. 7 is a cross-section of the semiconductor structure according to the first embodiment of the present invention. Schematic.
  • a silicon substrate 20 and a group III nitride epitaxial layer 11 on the first substrate 10 , the group III nitride epitaxial layer 11 and the silicon substrate 20 are respectively provided.
  • the first substrate 10 may include: at least one of sapphire, silicon carbide, and silicon, or at least one of sapphire, silicon carbide, and silicon, and a group III nitride material thereon, which is not limited in this embodiment .
  • the material of the group III nitride epitaxial layer 11 may be at least one of GaN, AlGaN, InGaN, and AlInGaN.
  • a certain material is represented by a chemical element, but the molar ratio of each chemical element in the material is not limited.
  • GaN material contains Ga element and N element, but the molar ratio of Ga element and N element is not limited;
  • AlGaN material contains three elements, Al, Ga, and N, but the molar ratio of each is not limited.
  • the group III nitride epitaxial layer 11 has dislocations, and the dislocations are mainly linear dislocations in the [0001] orientation, that is, dislocations extending in the thickness direction of the group III nitride epitaxial layer 11 .
  • the silicon substrate 20 may be (100) type single crystal silicon, (110) type single crystal silicon, (111) type single crystal silicon, or the like.
  • the bonding layer 30 is formed on the group III nitride epitaxial layer 11 .
  • the material of the bonding layer 30 may be silicon nitride or silicon dioxide, and may be formed by physical vapor deposition or chemical vapor deposition, for example.
  • the bonding layer 30 is formed on the silicon substrate 20 , or the bonding layer 30 is formed on both the silicon substrate 20 and the III-nitride epitaxial layer 11 .
  • the bonding layer 30 may be provided separately, that is, not formed on the silicon substrate 20 nor formed on the group III nitride epitaxial layer 11 .
  • the material of the bonding layer 30 may be metal.
  • the thickness of the bonding layer 30 may range from 0.01 ⁇ m to 2 ⁇ m.
  • the group III nitride epitaxial layer 11 and the silicon substrate 20 can be bonded together by high temperature and high pressure; it is also possible to apply a positive voltage to one of the group III nitride epitaxial layer 11 and the silicon substrate 20, and apply a negative voltage to the other, and then apply a negative voltage to the other. bond together.
  • the first substrate 10 can support the group III nitride epitaxial layer 11 .
  • a plurality of through-silicon vias 20 a and a plurality of first vias 30 a are respectively formed on the patterned silicon substrate 20 and the bonding layer 30 .
  • the through holes 30a expose the group III nitride epitaxial layer 11, and each through silicon through hole 20a communicates with the corresponding first through hole 30a.
  • the silicon substrate 20 and the bonding layer 30 may be patterned in a one-step dry etching process; as shown in FIG. 4 , the silicon substrate 20 may also be patterned first to form through-silicon vias 20a, Then, using the patterned silicon substrate 20 as a mask, the bonding layer 30 is dry-etched to form a first through hole 30a.
  • the thickness of the silicon substrate 20 is relatively thick, and the aspect ratio of the through silicon vias 20a formed therein is generally relatively large, for example, greater than 1:1.
  • the aspect ratios of each TSV 20 a are the same. In other embodiments, the aspect ratios of the through silicon vias 20a may also be different.
  • step S3 in FIG. 1 and as shown in FIG. 6 epitaxial growth is performed on the group III nitride epitaxial layer 11 to form the patterned silicon substrate in each of the first through holes 30 a and the TSVs 20 a and the patterned silicon substrate.
  • a first semiconductor layer 41 is formed by growing on 20 .
  • a reusable block mask 50 may be disposed on the patterned silicon substrate 20 first.
  • the shadow reticle 50 has several openings 50a. Each opening 50a communicates with one of the first through holes 30a and the TSVs 20a. In other words, each opening 50a corresponds to one LED structure.
  • the shadow mask 50 may also be replaced by a patterned mask layer remaining in the semiconductor structure 1 .
  • the material of the patterned mask layer may include, for example, at least one of silicon dioxide and silicon nitride.
  • the mask layer can be formed by physical vapor deposition method or chemical vapor deposition method, and the patterning can be realized by dry etching or wet etching.
  • the epitaxial growth process of the first semiconductor layer 41 may include: atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxy (MBE, Molecular Beam Epitaxy) , or Plasma Enhanced Chemical Vapor Deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or Low Pressure Chemical Vapor Deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or Metal Organic Compound Chemical Vapor Deposition, or a combination thereof.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • Metal Organic Compound Chemical Vapor Deposition or a combination thereof.
  • the extension of dislocations in the first semiconductor layer 41 can be limited, so that more dislocations are annihilated in the interior or sidewalls of the TSV 20a, so that the dislocation density can be formed
  • the small first semiconductor layer 41 improves the quality of the first semiconductor layer 41 .
  • the first semiconductor layer 41 may be doped with P-type doping ions or N-type doping ions.
  • the P-type doping ions can be at least one of Mg ions, Zn ions, Ca ions, Sr ions or Ba ions
  • the N-type doping ions can be Si ions, Ge ions, Sn ions, Se ions or Te ions.
  • At least one, in-situ doping method can be used, that is, doping while growing.
  • the materials of the first semiconductor layer 41 and the group III nitride epitaxial layer 11 may be the same or different, including at least one of GaN, AlN, AlGaN, InGaN and AlInGaN.
  • the openings 50 a of the mask reticle 50 are of different sizes.
  • the size of the opening 50a refers to the area size of the opening 50a.
  • the size ratio of each opening 50a to the connected through silicon vias 20a may be fixed. Since the sizes of the openings 50a are different, the sizes of the top surfaces of the epitaxially grown first semiconductor layers 41 of the openings 50a are different. In this embodiment, the size of the top surface of the first semiconductor layer 41 is the area of the top surface of the first semiconductor layer 41 .
  • the sizes of the openings 50a are the same, the sizes of the top surfaces of the epitaxially grown first semiconductor layers 41 of the openings 50a are also the same.
  • the active layer 42 and the second semiconductor layer 43 are epitaxially grown on the first semiconductor layer 41 in sequence, and the conductivity type of the second semiconductor layer 43 is the same as that of the first semiconductor layer.
  • the conductivity types of 41 are opposite, and the materials of the first semiconductor layer 41 , the active layer 42 and the second semiconductor layer 43 are group III nitrides.
  • the first semiconductor layer 41 , the active layer 42 and the second semiconductor layer 43 form an LED structure.
  • the active layer 42 may include wavelength-sensitive elements such as In element or Al element.
  • the epitaxial growth process of the active layer 42 and the second semiconductor layer 43 may refer to the epitaxial growth process of the first semiconductor layer 41 .
  • the second semiconductor layer 43 is doped with N-type doping ions; when the first semiconductor layer 41 is doped with N-type doping ions, the second semiconductor layer 43 is doped with N-type doping ions P-type dopant ions.
  • the active layer 42 and the second semiconductor layer 43 of an LED structure are formed in one opening 50 a, and thus, the active layer 42 is only located on the top surface of the first semiconductor layer 41 .
  • the aperture ratios of the openings 50a of the shielding mask 50 are different, and the flow rates of the reactive gases in the openings 50a are different when the active layer 42 is grown, so that the doping rates of the In element and the Ga element are different, that is, the doping efficiency of the In element. Different, this makes the composition ratio of the In element in the grown active layer 42 different. Specifically, the smaller the hole ratio of the opening 50a, the faster the growth rate of GaN, the base material of the active layer 42 in the opening 50a, and the better selectivity for the doping of In element.
  • the doping rate of Ga element therefore, the smaller the proportion of holes in the opening 50a, the higher the composition content of In element in the active layer 42InGaN, in addition, the smaller the proportion of holes in the opening 50a, the thickness of the quantum well in the opening is also will increase, because of the quantum Stark effect, the wavelength of light will increase.
  • the composition ratio of the In element refers to the percentage of the amount of In in the sum of the amounts of all positively charged elements in the source layer 42 .
  • the material of the active layer 42 is InGaN
  • the composition of In refers to the percentage of the amount of In in the sum of the amount of In and the amount of Ga
  • the material of the active layer 42 is InAlGaN
  • In The composition refers to the percentage of the amount of In material to the sum of the amount of In material, the amount of Al material and the amount of Ga material.
  • the active layer 42 is only located on the top surface of the first semiconductor layer 41.
  • the active layer 42 and the second semiconductor layer 43 can be epitaxially grown on the entire surface, and then each layer is disconnected by etching to form each LED structure. , or epitaxially grow the first semiconductor layer 41 , the active layer 42 and the second semiconductor layer 43 on the entire surface, and then cut off each layer by etching to form each LED structure.
  • the shadow mask 50 is removed.
  • the semiconductor structure 1 of the first embodiment includes:
  • the silicon substrate 20 and the group III nitride epitaxial layer 11 on the first substrate 10 have a bonding layer 30 between the group III nitride epitaxial layer 11 and the silicon substrate 20; the group III nitride epitaxial layer 11 and the silicon
  • the substrates 20 are bonded together by a bonding layer 30; the silicon substrate 20 has several through-silicon vias 20a, the bonding layer 30 has several first through-holes 30a, and each through-silicon via 20a is associated with a corresponding first through-silicon via 20a.
  • a through hole 30a communicates;
  • the conductivity type of the second semiconductor layer 43 is opposite to that of the first semiconductor layer 41.
  • the materials of the first semiconductor layer 41, the active layer 42 and the second semiconductor layer 43 are group III nitrides.
  • the active layer 42 is only located on the top surface of the first semiconductor layer 41 .
  • the through-silicon vias 20a and the first vias 30a have a plurality of them respectively, and the sidewalls of the silicon substrate 20 and/or the III-nitride epitaxial layer 11 may be provided with a common electrode, and the common electrode is electrically connected to each of them.
  • the common electrode may be a ground electrode.
  • a respective driving electrode may be disposed on the second semiconductor layer 43 of each LED structure.
  • FIG. 8 is a schematic cross-sectional structure diagram of a semiconductor structure according to a second embodiment of the present invention.
  • the semiconductor structure 2 of the second embodiment and the fabrication method thereof are substantially the same as the semiconductor structure 1 of the first embodiment and the fabrication method thereof, except that the first substrate 10 and the group III nitride epitaxy are removed.
  • Layer 11 the semiconductor structure 2 of the second embodiment and the fabrication method thereof are substantially the same as the semiconductor structure 1 of the first embodiment and the fabrication method thereof, except that the first substrate 10 and the group III nitride epitaxy are removed.
  • the removal of the first substrate 10 and the group III nitride epitaxial layer 11 may be performed by etching the bonding layer 30 to lift the group III nitride epitaxial layer 11 from the silicon substrate 20 .
  • the first substrate 10 and the group III nitride epitaxial layer 11 peeled off from the silicon substrate 20 can be reused.
  • the common electrode may be disposed on the side of the silicon substrate 20 away from the second semiconductor layer 43 , and only needs to be connected to the first semiconductor layer 41 in each through-silicon via 20a.
  • FIG. 9 is a schematic cross-sectional structure diagram of a semiconductor structure according to a third embodiment of the present invention.
  • the semiconductor structure 3 of the third embodiment is substantially the same as the semiconductor structures 1 and 2 of the first and second embodiments, the only difference being that there is a dielectric between the first semiconductor layer 41 and the upper surface of the silicon substrate 20 Layer 12, the active layer 42 is located on the top surface and the side surface of the first semiconductor layer 41, and the top surface and the side surface are perpendicular to each other.
  • the material of the dielectric layer 12 may include at least one of silicon dioxide, silicon nitride and aluminum oxide.
  • the fabrication method of this embodiment is substantially the same as the fabrication method of the previous embodiment, and one of the differences is only that: between step S1 and step S2 , the silicon substrate 20 is performed on the side of the silicon substrate 20 away from the group III nitride epitaxial layer 11 .
  • the dielectric layer 12 is formed.
  • the dielectric layer 12 may be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition.
  • the dielectric layer 12 and the silicon substrate 20 may be patterned in the same process, for example, by one-step dry etching or wet etching.
  • the dielectric layer 12 is patterned first, and then the silicon substrate 20 is etched using the patterned dielectric layer 12 as a mask.
  • the patterned dielectric layer 12 is formed on the patterned silicon substrate 20 performed between step S2 and step S3 .
  • the dielectric layer 12 is formed, for example, by thermally oxidizing the silicon substrate 20 .
  • the dielectric layer 12 can improve the growth performance of the first semiconductor layer 41 on the silicon substrate 20 , especially on the (100) type single crystal silicon substrate 20 through material selection.
  • the dielectric layer 12 is also formed on the sidewalls of the TSVs 20a.
  • the dielectric layer 12 on the sidewall of the TSV 20a can prevent the GaN-based material of the first semiconductor layer 41 from reacting with the silicon substrate 20 when the first semiconductor layer 41 is epitaxially grown.
  • the second difference between the manufacturing method of the present embodiment and the manufacturing method of the preceding embodiment is only that: between step S3 and step S4 , the mask reticle 50 is removed.
  • the side surface of the first semiconductor layer 41 is exposed, so that the active layer 42 and the second semiconductor layer 43 can be epitaxially grown on the side surface of the first semiconductor layer 41 .
  • the active layer 42 and the second semiconductor layer 43 may be epitaxially grown on the entire surface, and then each layer may be disconnected by etching to form each LED structure.
  • FIG. 10 is a schematic cross-sectional structure diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • the semiconductor structure 4 of the fourth embodiment is substantially the same as the semiconductor structure 3 of the third embodiment, except that the active layer 42 is located on the top surface and the side surface of the first semiconductor layer 41 , the top surface and the side surface are There is an included angle ⁇ between the surfaces, 40° ⁇ 70°.
  • the specific size of the angle ⁇ between the side surface and the top surface of the first semiconductor layer 41 can be realized by the process conditions of epitaxial growth or the etching method.
  • the doping efficiency of the In element in the active layer 42 is greater than the doping efficiency of the In element in the active layer 42 on the semipolar surface of the side surface.
  • the composition of the In element of the layer 42 is larger than the composition of the In element of the active layer 42 located on the side surface. The larger the composition of the In element, the longer the corresponding emission wavelength.
  • FIG. 11 is a schematic cross-sectional structural diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • the semiconductor structure 5 of the fifth embodiment is substantially the same as the semiconductor structure 4 of the fourth embodiment, and the only difference is that a section of the first semiconductor layer 41 along the thickness direction is triangular, and the active layer 42 is only located in the first semiconductor layer 41 in the thickness direction.
  • a side surface of the semiconductor layer 41 has an included angle ⁇ between the side surface of the first semiconductor layer 41 and the upper surface of the silicon substrate 20, 40° ⁇ 70°.
  • the specific size of the angle ⁇ between the side surface of the first semiconductor layer 41 and the upper surface of the silicon substrate 20 can be achieved by the process conditions of epitaxial growth or the etching method.
  • the distribution of the active layer 42 at at least one TSV 20a on the first semiconductor layer 41 is different from that of the active layers 42 at other TSVs 20a distribution on the first semiconductor layer 41 .
  • the distribution of the active layer 42 on the first semiconductor layer 41 may be at least one of implementations one, three, four, and five.

Abstract

本申请提供了一种半导体结构及其制作方法，半导体结构包括：硅衬底，硅衬底内具有若干个穿硅通孔；以及位于每个穿硅通孔内以及硅衬底上的第一半导体层、位于第一半导体层上的有源层以及位于有源层上的第二半导体层，第二半导体层的导电类型与第一半导体层的导电类型相反，第一半导体层、有源层与第二半导体层的材料为Ⅲ族氮化物。利用穿硅通孔的深宽比较大，可使第一半导体层内的位错延伸受限，增加湮灭在穿硅通孔的侧壁的几率，从而可形成位错密度小的第一半导体层、有源层以及第二半导体层，提高LED的显色性且使发光波长可自由调整。

Description

半导体结构及其制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
III族氮化物是继Si、GaAs等第一、第二代半导体材料之后的第三代新型半导体材料，具有诸如饱和漂移速度高、击穿电压大、载流子输运性能优异等许多优点。鉴于此，近几年来III族氮化物材料和半导体器件得到了广泛和深入的研究，MOCVD(Metal-organic Chemical Vapor Deposition，金属有机物化学气相沉积)技术生长III族氮化物材料日趋成熟；在半导体器件研究方面，III族氮化物LED、LDS等光电子器件以及III族氮化物HEMT等微电子器件方面的研究都取得了显著的成绩和长足的发展。
随着III族氮化物材料在LED显示器件上的应用的逐步深入，终端产品迫切需要一种显色性好且发光波长可自由调整的LED结构。
发明内容
本发明的发明目的是提供一种半导体结构及其制作方法，满足行业内对LED结构的显色性好且发光波长可自由调整的需求。
为实现上述目的，本发明的第一方面提供一种半导体结构，包括：
硅衬底，所述硅衬底内具有若干个穿硅通孔；
位于每个所述穿硅通孔内以及所述硅衬底上的第一半导体层、位于所述第一半导体层上的有源层以及位于所述有源层上的第二半导体层，所述第 二半导体层的导电类型与所述第一半导体层的导电类型相反，所述第一半导体层、所述有源层与所述第二半导体层的材料为Ⅲ族氮化物。
可选地，所述有源层仅位于所述第一半导体层的顶表面。
可选地，所述有源层包含In元素；所述第一半导体层的顶表面的尺寸越小，所述有源层的In元素的组分越大；所述第一半导体层的顶表面的尺寸越大，所述有源层的In元素的组分越小。
可选地，所述第一半导体层与所述硅衬底的上表面之间具有介质层。
可选地，所述穿硅通孔的侧壁也设置有所述介质层。
可选地，所述有源层位于所述第一半导体层的顶表面与侧表面。
可选地，所述有源层包含In元素；所述侧表面与所述顶表面之间的夹角的范围为：40°～70°；位于所述顶表面的所述有源层的In元素的组分大于位于所述侧表面的所述有源层的In元素的组分。
可选地，所述第一半导体层沿厚度方向的一个剖面呈三角形，所述有源层仅位于所述第一半导体层的侧表面。
可选地，所述介质层的材料包括：二氧化硅、氮化硅与三氧化二铝中的至少一种。
可选地，所述穿硅通孔的深宽比大于1：1。
可选地，所述穿硅通孔具有多个，至少一个所述穿硅通孔处的所述有源层在所述第一半导体层上的分布不同于其它所述穿硅通孔处的所述有源层在所述第一半导体层上的分布。
可选地，所述穿硅通孔具有多个，所述硅衬底远离所述第二半导体层的一侧设置有共电极，所述共电极电连接每个所述穿硅通孔内的所述第一半导体层。
可选地，所述半导体结构还包括：位于第一衬底上的Ⅲ族氮化物外延 层，所述Ⅲ族氮化物外延层与所述硅衬底通过键合层键合在一起，所述键合层内具有若干个第一通孔，每个所述第一通孔与对应的所述穿硅通孔连通；所述第一半导体层还位于所述第一通孔内，以与所述Ⅲ族氮化物外延层连接。
可选地，所述穿硅通孔与所述第一通孔分别具有多个，所述硅衬底和/或所述Ⅲ族氮化物外延层的侧壁设置有共电极，所述共电极电连接每个所述穿硅通孔内的所述第一半导体层。
可选地，所述第一衬底的材料包括：蓝宝石、碳化硅和硅中的至少一种。
可选地，所述键合层的材料为二氧化硅或氮化硅。
本发明的第二方面提供一种半导体结构的制作方法，包括：
分别提供硅衬底与位于第一衬底上的Ⅲ族氮化物外延层，所述Ⅲ族氮化物外延层和所述硅衬底之间具有键合层；通过所述键合层将所述Ⅲ族氮化物外延层与所述硅衬底键合在一起；
图形化所述硅衬底与所述键合层分别对应形成若干个穿硅通孔若干个第一通孔，每个所述第一通孔暴露所述Ⅲ族氮化物外延层；每个所述穿硅通孔与对应的所述第一通孔连通；
对所述Ⅲ族氮化物外延层进行外延生长，以在每个所述第一通孔与所述穿硅通孔内以及所述图形化的硅衬底上生长形成第一半导体层；
依次在所述第一半导体层上外延生长有源层与第二半导体层，所述第二半导体层的导电类型与所述第一半导体层的导电类型相反，所述第一半导体层、所述有源层与所述第二半导体层的材料为Ⅲ族氮化物。
可选地，通过掩膜层或刻蚀法使所述有源层仅形成于所述第一半导体层的顶表面。
可选地，所述有源层包含In元素；所述第一半导体层的顶表面的尺寸 越小，所述有源层的In元素的组分越大；所述第一半导体层的顶表面的尺寸越大，所述有源层的In元素的组分越小。
可选地，所述第一半导体层进行外延生长前，在所述图形化的硅衬底上形成图形化的介质层。
可选地，图形化所述硅衬底形成穿硅通孔前，在所述硅衬底远离所述Ⅲ族氮化物外延层的一侧形成介质层；所述介质层与所述硅衬底在同一工序中进行图形化，或先图形化所述介质层，后以图形化的介质层为掩膜刻蚀所述硅衬底。
可选地，所述介质层还形成在所述穿硅通孔的侧壁。
可选地，所述有源层形成于所述第一半导体层的顶表面与侧表面。
可选地，所述有源层包含In元素；所述侧表面与所述顶表面之间的夹角的范围为：40°～70°；位于所述顶表面的所述有源层的In元素的组分大于位于所述侧表面的所述有源层的In元素的组分。
可选地，所述第一半导体层沿厚度方向的一个剖面呈三角形，所述有源层仅形成于所述第一半导体层的侧表面。
可选地，所述制作方法还包括：腐蚀所述键合层，以将所述Ⅲ族氮化物外延层从所述硅衬底上剥离。
与现有技术相比，本发明的有益效果在于：
1)将硅衬底键合在Ⅲ族氮化物外延层上，利用硅衬底成熟的工艺及其相对较厚的厚度，在其内形成的穿硅通孔的深宽比一般较大，对Ⅲ族氮化物外延层外延生长形成第一半导体层时，使第一半导体层内的位错延伸受限，增加了湮灭在穿硅通孔的内部及侧壁的几率，从而可形成位错密度小的第一半导体层、有源层以及第二半导体层，提高了LED结构的显色性。
2)可选方案中，穿硅通孔的深宽比大于1：1。上述深宽比能进一步限 制第一半导体层内的位错延伸，增加湮灭在穿硅通孔的内部及侧壁的几率。
3)可选方案中，有源层仅位于第一半导体层的顶表面。本方案中，有源层可以包含In元素等波长敏感元素，通过控制穿硅通孔的深宽比不同，使得对应穿硅通孔内外延生长的第一半导体层的顶表面的尺寸大小不同，从而对应的第一半导体层上外延生长的有源层的In元素等波长敏感元素的组分大小不同，进而LED结构的发光波长不同。具体地，第一半导体层的顶表面的尺寸越小，有源层的In元素的组分越大，LED结构的发光波长越长；第一半导体层的顶表面的尺寸越大，有源层的In元素的组分越小，LED结构的发光波长越短。
4)可选方案中，有源层位于第一半导体层的顶表面与侧表面。本方案中，可通过控制外延生长工艺的条件使得第一半导体层的侧表面与顶表面之间的夹角的范围为：40°～70°。由于顶表面为(0001)晶面，有源层中In元素的掺入效率大于侧表面的半极性面上有源层中In元素的掺入效率，因而，位于顶表面的有源层的In元素的组分大于位于侧表面的有源层的In元素的组分。In元素的组分越大，对应的发光波长越长。
5)可选方案中，有源层仅位于第一半导体层的侧表面。本方案中，也可通过控制外延生长工艺的条件使得第一半导体层的侧表面与硅衬底的上表面之间的夹角的范围为：40°～70°。
附图说明
图1是本发明第一实施例的半导体结构的制作方法的流程图；
图2至图6是图1中的流程对应的中间结构示意图；
图7是本发明第一实施例的半导体结构的截面结构示意图；
图8是本发明第二实施例的半导体结构的截面结构示意图；
图9是本发明第三实施例的半导体结构的截面结构示意图；
图10是本发明第四实施例的半导体结构的截面结构示意图；
图11是本发明第五实施例的半导体结构的截面结构示意图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
Figure PCTCN2021087487-appb-000001
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的半导体结构的制作方法的流程图；图2至图6是图1中的流程对应的中间结构示意图；图7是本发明第一实施例的半导体结构的截面结构示意图。
首先，参照图1中的步骤S1与图2所示，分别提供硅衬底20与位于第一衬底10上的Ⅲ族氮化物外延层11，Ⅲ族氮化物外延层11和硅衬底20之间具有键合层30；参照图3所示，通过键合层30将Ⅲ族氮化物外延层11与硅衬底20键合在一起。
第一衬底10可以包括：蓝宝石、碳化硅和硅中的至少一种，或蓝宝石、 碳化硅和硅中的至少一种及其上的Ⅲ族氮化物材料，本实施例对此不加以限制。
Ⅲ族氮化物外延层11的材料可以为GaN、AlGaN、InGaN、AlInGaN中的至少一种。
需要说明的是，本实施例中，以化学元素代表某种材料，但不限定该材料中各化学元素的摩尔占比。例如GaN材料中，包含Ga元素与N元素，但不限定Ga元素与N元素的摩尔占比；AlGaN材料中，包含Al、Ga、N三种元素，但不限定各自的摩尔占比大小。
Ⅲ族氮化物外延层11中具有位错，位错主要为[0001]晶向的线位错，即在Ⅲ族氮化物外延层11的厚度方向延伸的位错。
硅衬底20可以为(100)型单晶硅、(110)型单晶硅、(111)型单晶硅等。
本实施例中，参照图2所示，键合层30形成在Ⅲ族氮化物外延层11上。键合层30的材料可以为氮化硅或二氧化硅，例如可通过物理气相沉积法或化学气相沉积法形成。
另一实施例中，键合层30形成在硅衬底20上，或硅衬底20与Ⅲ族氮化物外延层11上都形成有键合层30。
再一实施例中，键合层30可单独提供，即不形成于硅衬底20上，也不形成于Ⅲ族氮化物外延层11上。键合层30的材料可以为金属。
键合层30的厚度范围可以为0.01μm～2μm。
Ⅲ族氮化物外延层11与硅衬底20可通过高温高压键合在一起；也可以在Ⅲ族氮化物外延层11与硅衬底20中的一个施加正电压，另一个施加负电压，之后键合在一起。
在键合工序中，第一衬底10可对Ⅲ族氮化物外延层11起支撑作用。
接着，参照图1中的步骤S2、图4与图5所示，图形化硅衬底20与键合层30分别对应形成若干穿硅通孔20a与若干第一通孔30a，每个第一通孔30a暴露Ⅲ族氮化物外延层11，每个穿硅通孔20a与对应的第一通孔30a连通。
本实施例中，若干是指一个、两个或两个以上的数目。
参照图5所示，硅衬底20与键合层30可在一步干法刻蚀工序中完成图形化；参照图4所示，也可以先图形化硅衬底20形成穿硅通孔20a，后以图形化的硅衬底20为掩膜，干法刻蚀键合层30形成第一通孔30a。
硅衬底20的厚度较厚，在其内形成的穿硅通孔20a的深宽比一般较大，例如大于1：1。
本实施例中，参照图4与图5所示，当穿硅通孔20a具有两个及其以上数目时，各个穿硅通孔20a的深宽比相同。其它实施例中，各个穿硅通孔20a的深宽比也可以不同。
之后，参照图1中的步骤S3与图6所示，对Ⅲ族氮化物外延层11进行外延生长，以在每个第一通孔30a与穿硅通孔20a内以及图形化的硅衬底20上生长形成第一半导体层41。
本实施例中，对Ⅲ族氮化物外延层11进行外延生长前，可以先在图形化的硅衬底20上设置可重复使用的遮挡掩模版50。
遮挡掩模版50具有若干开口50a。每一开口50a与一个第一通孔30a与穿硅通孔20a连通。换言之，每一开口50a对应一个LED结构。
其它实施例中，遮挡掩模版50也可以替换为保留在半导体结构1中的图形化的掩膜层。
图形化的掩膜层的材料例如可以包括：二氧化硅与氮化硅中的至少一种。掩膜层可以采用物理气相沉积法或化学气相沉积法形成，图形化可以采用干法刻蚀或湿法刻蚀实现。
第一半导体层41的外延生长工艺可以包括：原子层沉积法(ALD，Atomic layer deposition)、或化学气相沉积法(CVD，Chemical Vapor Deposition)、或分子束外延生长法(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积法、或其组合方式。
由于穿硅通孔20a的深宽比较大，因而能限制第一半导体层41内的位错延伸，使更多位错湮灭在穿硅通孔20a的内部或侧壁，从而可形成位错密度小的第一半导体层41，提高了第一半导体层41的质量。
第一半导体层41在外延生长时，可以掺入P型掺杂离子或N型掺杂离子。P型掺杂离子可以为Mg离子、Zn离子、Ca离子、Sr离子或Ba离子中的至少一种，N型掺杂离子可以为Si离子、Ge离子、Sn离子、Se离子或Te离子中的至少一种，都可以采用原位掺杂法，即边生长边掺杂。
第一半导体层41与Ⅲ族氮化物外延层11的材料可以相同或不同，包括：GaN、AlN、AlGaN、InGaN与AlInGaN中的至少一种。
本实施例中，参照图6所示，遮挡掩模版50的各个开口50a大小不一。本实施例中，开口50a的大小是指开口50a的面积大小。
当各个穿硅通孔20a的深宽比不同时，各个开口50a与所连通的穿硅通孔20a的大小之比可以固定。由于各个开口50a大小不一，因而，各个开口50a内外延生长的第一半导体层41的顶表面的尺寸大小不同。本实施例中，第一半导体层41的顶表面的尺寸是第一半导体层41的顶表面的面积。
其它实施例中，当各个开口50a的大小相同时，各个开口50a内外延生长的第一半导体层41的顶表面的尺寸大小也相同。
再接着，参照图1中的步骤S4与图6所示，依次在第一半导体层41上外延生长有源层42与第二半导体层43，第二半导体层43的导电类型与第 一半导体层41的导电类型相反，第一半导体层41、有源层42与第二半导体层43的材料为Ⅲ族氮化物。
第一半导体层41、有源层42与第二半导体层43形成了一LED结构。
有源层42可以包括In元素或Al元素等波长敏感元素。
有源层42与第二半导体层43的外延生长工艺可以参照第一半导体层41的外延生长工艺。当第一半导体层41掺入P型掺杂离子时，第二半导体层43掺入N型掺杂离子；当第一半导体层41掺入N型掺杂离子时，第二半导体层43掺入P型掺杂离子。
本实施例中，一个LED结构的有源层42与第二半导体层43形成在一个开口50a内，因而，有源层42仅位于第一半导体层41的顶表面。
遮挡掩模版50的开口50a的孔占比大小不同，生长有源层42时各开口50a内的反应气体的流速不同，从而In元素与Ga元素的掺入速率不同，即In元素的掺入效率不同，这使得生长的有源层42中In元素的组分占比不同。具体地，开口50a的孔占比越小，开口50a内有源层42的基础材料GaN的生长速度会变快，In元素的掺杂具有更好的选择性，In元素的掺入速率越大于Ga元素的掺入速率，因此，开口50a的孔占比越小，有源层42InGaN中In元素的组分含量越高，另外，开口50a的孔占比越小，开口内量子阱的厚度也会随之增加，因为量子斯塔克效应，发光的波长会随之增加。反之，开口50a的孔占比越大，In元素的掺入速率与Ga元素的掺入速率差异越不明显，即In元素的掺入效率越低，生长的有源层42中In元素的组分占比越低。
In元素的组分占比是指：In的物质的量占有源层42中所有带正电荷的元素的物质的量之和的百分比。例如：有源层42的材料为InGaN，In的组分是指：In的物质的量占In的物质的量与Ga的物质的量之和的百分比；有源层42的材料为InAlGaN，In的组分是指：In的物质的量占In的物质的量、Al的物质的量与Ga的物质的量之和的百分比。
其它实施例中，有源层42仅位于第一半导体层41的顶表面也可以通过整面外延生长有源层42与第二半导体层43，后通过刻蚀法断开各层形成各个LED结构，或整面外延生长第一半导体层41、有源层42与第二半导体层43，后通过刻蚀法断开各层形成各个LED结构。
之后，参照图7所示，去除遮挡掩模版50。
参照图7所示，本实施例一的半导体结构1包括：
硅衬底20与位于第一衬底10上的Ⅲ族氮化物外延层11，Ⅲ族氮化物外延层11与硅衬底20之间具有键合层30；Ⅲ族氮化物外延层11与硅衬底20通过键合层30键合在一起；硅衬底20内具有若干穿硅通孔20a，键合层30内具有若干第一通孔30a，每个穿硅通孔20a与对应的第一通孔30a连通；
位于穿硅通孔20a与第一通孔30a内以及硅衬底20上的第一半导体层41、位于第一半导体层41上的有源层42以及位于有源层42上的第二半导体层43，第二半导体层43的导电类型与第一半导体层41的导电类型相反，第一半导体层41、有源层42与第二半导体层43的材料为Ⅲ族氮化物。
本实施例中，有源层42仅位于第一半导体层41的顶表面。第一半导体层41的顶表面的尺寸越小，有源层42的In元素的组分越大，LED结构的发光波长越长；第一半导体层41的顶表面的尺寸越大，有源层42的In元素的组分越小，LED结构的发光波长越短。
一些实施例中，穿硅通孔20a与第一通孔30a分别具有多个，硅衬底20和/或Ⅲ族氮化物外延层11的侧壁可以设置有共电极，共电极电连接每个穿硅通孔20a内的第一半导体层41。共电极可以为接地电极。每个LED结构的第二半导体层43上可以设置有各自的驱动电极。
图8是本发明第二实施例的半导体结构的截面结构示意图。
参照图8所示，本实施例二的半导体结构2及其制作方法与实施例一的半导体结构1及其制作方法大致相同，区别仅在于：去除了第一衬底10与 Ⅲ族氮化物外延层11。
去除第一衬底10与Ⅲ族氮化物外延层11可以通过腐蚀键合层30，以将Ⅲ族氮化物外延层11从硅衬底20上剥离。
从硅衬底20上剥离的第一衬底10与Ⅲ族氮化物外延层11可重复使用。
本实施例中，共电极可以设置在硅衬底20远离第二半导体层43的一侧，连接每个穿硅通孔20a内的第一半导体层41即可。
图9是本发明第三实施例的半导体结构的截面结构示意图。
参照图9所示，本实施例三的半导体结构3与实施例一、二的半导体结构1、2大致相同，区别仅在于：第一半导体层41与硅衬底20的上表面之间具有介质层12，有源层42位于第一半导体层41的顶表面与侧表面，顶表面与侧表面相互垂直。
介质层12的材料可以包括：二氧化硅、氮化硅与三氧化二铝中的至少一种。
对应地，本实施例的制作方法与前述实施例的制作方法大致相同，区别之一仅在于：步骤S1与步骤S2之间执行：在硅衬底20远离Ⅲ族氮化物外延层11的一侧形成介质层12。介质层12可以采用物理气相沉积法、化学气相沉积法或原子层沉积法形成。一个可选方案中，步骤S2中，介质层12可以与硅衬底20在同一工序中进行图形化，例如采用一步干法刻蚀或湿法刻蚀实现。另一个可选方案中，步骤S2中，先图形化介质层12，后以图形化的介质层12为掩膜刻蚀硅衬底20。
或本实施例的制作方法与前述实施例的制作方法的区别之一仅在于：步骤S2与步骤S3之间执行：在图形化的硅衬底20上形成图形化的介质层12。例如通过热氧化硅衬底20形成介质层12。
介质层12可通过材料选择，提高第一半导体层41在硅衬底20，尤其在(100)型单晶硅衬底20上的生长性能。
一些实施例中，介质层12还形成在穿硅通孔20a的侧壁。穿硅通孔20a侧壁的介质层12可防止外延生长第一半导体层41时，第一半导体层41的GaN基材料与硅衬底20发生反应。
本实施例的制作方法与前述实施例的制作方法的区别之二仅在于：步骤S3与步骤S4之间执行：去除遮挡掩模版50。
去除遮挡掩模版50后，暴露第一半导体层41的侧表面，因而，有源层42与第二半导体层43可外延生长于第一半导体层41的侧表面。可以通过整面外延生长有源层42与第二半导体层43，后通过刻蚀法断开各层形成各个LED结构。
图10是本发明第四实施例的半导体结构的截面结构示意图。
参照图10所示，本实施例四的半导体结构4与实施例三的半导体结构3大致相同，区别仅在于：有源层42位于第一半导体层41的顶表面与侧表面，顶表面与侧表面之间具有夹角α，40°≤α≤70°。
第一半导体层41的侧表面与顶表面之间的夹角α的具体大小，可通过外延生长的工艺条件或刻蚀法实现。
侧表面与顶表面之间的夹角α越大，即侧表面越陡峭。
由于顶表面为(0001)晶面，有源层42中In元素的掺入效率大于侧表面的半极性面上有源层42中In元素的掺入效率，因而，位于顶表面的有源层42的In元素的组分大于位于侧表面的有源层42的In元素的组分。In元素的组分越大，对应的发光波长越长。
图11是本发明第五实施例的半导体结构的截面结构示意图。
参照图11所示，本实施例五的半导体结构5与实施例四的半导体结构4大致相同，区别仅在于：第一半导体层41沿厚度方向的一个剖面呈三角形，有源层42仅位于第一半导体层41的侧表面，第一半导体层41的侧表面与硅衬底20的上表面之间具有夹角β，40°≤β≤70°。
第一半导体层41的侧表面与硅衬底20的上表面之间的夹角β的具体大小，可通过外延生长的工艺条件或或刻蚀法实现。
第一半导体层41的侧表面与硅衬底20的上表面之间的夹角β越大，即侧表面越陡峭。
一些实施例中，穿硅通孔20a具有多个，至少一个穿硅通孔20a处的有源层42在第一半导体层41上的分布不同于其它穿硅通孔20a处的有源层42在第一半导体层41上的分布。有源层42在第一半导体层41上的分布可以为实施一、三、四、五中的至少一种。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

  1. 一种半导体结构，其特征在于，包括：
    硅衬底(20)，所述硅衬底(20)内具有若干个穿硅通孔(20a)；
    位于每个所述穿硅通孔(20a)内以及所述硅衬底(20)上的第一半导体层(41)、位于所述第一半导体层(41)上的有源层(42)以及位于所述有源层(42)上的第二半导体层(43)，所述第二半导体层(43)的导电类型与所述第一半导体层(41)的导电类型相反，所述第一半导体层(41)、所述有源层(42)与所述第二半导体层(43)的材料为Ⅲ族氮化物。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述有源层(42)仅位于所述第一半导体层(41)的顶表面。
  3. 根据权利要求2所述的半导体结构，其特征在于，所述有源层(42)包含In元素；所述第一半导体层(41)的顶表面的尺寸越小，所述有源层(42)的In元素的组分越大；所述第一半导体层(41)的顶表面的尺寸越大，所述有源层(42)的In元素的组分越小。
  4. 根据权利要求1所述的半导体结构，其特征在于，所述第一半导体层(41)与所述硅衬底(20)的上表面之间具有介质层(12)。
  5. 根据权利要求4所述的半导体结构，其特征在于，所述有源层(42)位于所述第一半导体层(41)的顶表面与侧表面。
  6. 根据权利要求5所述的半导体结构，其特征在于，所述有源层(42)包含In元素；所述侧表面与所述顶表面之间的夹角的范围为：40°～70°；位于所述顶表面的所述有源层(42)的In元素的组分大于位于所述侧表面的所述有源层(42)的In元素的组分。
  7. 根据权利要求4所述的半导体结构，其特征在于，所述第一半导体层(41)沿厚度方向的一个剖面呈三角形，所述有源层(42)仅位于所述第一半导体层(41)的侧表面。
  8. 根据权利要求1所述的半导体结构，其特征在于，所述穿硅通孔(20a) 的深宽比大于1：1。
  9. 根据权利要求1所述的半导体结构，其特征在于，所述穿硅通孔(20a)具有多个，所述硅衬底(20)远离所述第二半导体层(43)的一侧设置有共电极，所述共电极电连接每个所述穿硅通孔(20a)内的所述第一半导体层(41)。
  10. 根据权利要求1所述的半导体结构，其特征在于，还包括：位于第一衬底(10)上的Ⅲ族氮化物外延层(11)，所述Ⅲ族氮化物外延层(11)与所述硅衬底(20)通过键合层(30)键合在一起，所述键合层(30)内具有若干个第一通孔(30a)，每个所述第一通孔(30a)与对应的所述穿硅通孔(20a)连通；所述第一半导体层(41)还位于所述第一通孔(30a)内，以与所述Ⅲ族氮化物外延层(11)连接。
  11. 根据权利要求10所述的半导体结构，其特征在于，所述穿硅通孔(20a)与所述第一通孔(30a)分别具有多个，所述硅衬底(20)和/或所述Ⅲ族氮化物外延层(11)的侧壁设置有共电极，所述共电极电连接每个所述穿硅通孔(20a)内的所述第一半导体层(41)。
  12. 一种半导体结构的制作方法，其特征在于，包括：
    分别提供硅衬底(20)与位于第一衬底(10)上的Ⅲ族氮化物外延层(11)，所述Ⅲ族氮化物外延层(11)和所述硅衬底(20)之间具有键合层(30)；通过所述键合层(30)将所述Ⅲ族氮化物外延层(11)与所述硅衬底(20)键合在一起；
    图形化所述硅衬底(20)与所述键合层(30)分别对应形成若干个穿硅通孔(20a)若干个第一通孔(30a)，每个所述第一通孔(30a)暴露所述Ⅲ族氮化物外延层(11)；每个所述穿硅通孔(20a)与对应的所述第一通孔(30a)连通；
    对所述Ⅲ族氮化物外延层(11)进行外延生长，以在每个所述第一通孔(30a)与所述穿硅通孔(20a)内以及所述图形化的硅衬底(20)上生长形成第一半导体层(41)；
    依次在所述第一半导体层(41)上外延生长有源层(42)与第二半导体层(43)，所述第二半导体层(43)的导电类型与所述第一半导体层(41)的导电类型相反，所述第一半导体层(41)、所述有源层(42)与所述第二半导体层(43)的材料为Ⅲ族氮化物。
  13. 根据权利要求12所述的半导体结构的制作方法，其特征在于，通过掩膜层或刻蚀法使所述有源层(42)仅形成于所述第一半导体层(41)的顶表面。
  14. 根据权利要求13所述的半导体结构的制作方法，其特征在于，所述有源层(42)包含In元素；所述第一半导体层(41)的顶表面的尺寸越小，所述有源层(42)的In元素的组分越大；所述第一半导体层(41)的顶表面的尺寸越大，所述有源层(42)的In元素的组分越小。
  15. 根据权利要求12所述的半导体结构的制作方法，其特征在于，所述第一半导体层(41)进行外延生长前，在所述图形化的硅衬底(20)上形成图形化的介质层(12)。
  16. 根据权利要求12所述的半导体结构的制作方法，其特征在于，图形化所述硅衬底(20)形成穿硅通孔(20a)前，在所述硅衬底(20)远离所述Ⅲ族氮化物外延层(11)的一侧形成介质层(12)；所述介质层(12)与所述硅衬底(20)在同一工序中进行图形化，或先图形化所述介质层(12)，后以图形化的介质层(12)为掩膜刻蚀所述硅衬底(20)。
  17. 根据权利要求15所述的半导体结构的制作方法，其特征在于，所述有源层(42)形成于所述第一半导体层(41)的顶表面与侧表面。
  18. 根据权利要求17所述的半导体结构的制作方法，其特征在于，所述有源层(42)包含In元素；所述侧表面与所述顶表面之间的夹角越大，位于所述侧表面的所述有源层(42)的In元素的组分越小；所述侧表面与所述顶表面之间的夹角越小，位于所述侧表面的所述有源层(42)的In元素的组分越大。
  19. 根据权利要求17所述的半导体结构的制作方法，其特征在于，所述 第一半导体层(41)沿厚度方向的一个剖面呈三角形，所述有源层(42)仅形成于所述第一半导体层(41)的侧表面。
  20. 根据权利要求12所述的半导体结构的制作方法，其特征在于，还包括：腐蚀所述键合层(30)，以将所述Ⅲ族氮化物外延层(11)从所述硅衬底(20)上剥离。
PCT/CN2021/087487 2021-04-15 2021-04-15 半导体结构及其制作方法 WO2022217539A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202180096215.6A CN117063302A (zh) 2021-04-15 2021-04-15 半导体结构及其制作方法
PCT/CN2021/087487 WO2022217539A1 (zh) 2021-04-15 2021-04-15 半导体结构及其制作方法
US18/549,479 US20240154063A1 (en) 2021-04-15 2021-04-15 Semiconductor structures and manufacturing methods thereof
TW111113418A TWI833198B (zh) 2021-04-15 2022-04-08 半導體結構及其製作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/087487 WO2022217539A1 (zh) 2021-04-15 2021-04-15 半导体结构及其制作方法

Publications (1)

Publication Number Publication Date
WO2022217539A1 true WO2022217539A1 (zh) 2022-10-20

Family

ID=83639991

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/087487 WO2022217539A1 (zh) 2021-04-15 2021-04-15 半导体结构及其制作方法

Country Status (4)

Country Link
US (1) US20240154063A1 (zh)
CN (1) CN117063302A (zh)
TW (1) TWI833198B (zh)
WO (1) WO2022217539A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012115541A2 (en) * 2011-02-24 2012-08-30 Yury Georgievich Shreter Light-emitting semiconductor device
CN103000776A (zh) * 2012-11-14 2013-03-27 深圳大学 Led芯片及led芯片的制造方法
CN104170100A (zh) * 2012-03-14 2014-11-26 首尔伟傲世有限公司 发光二极管及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB201112327D0 (en) * 2011-07-18 2011-08-31 Epigan Nv Method for growing III-V epitaxial layers
US9397168B2 (en) * 2014-10-17 2016-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method to define the active region of a transistor employing a group III-V semiconductor material
US9627473B2 (en) * 2015-09-08 2017-04-18 Macom Technology Solutions Holdings, Inc. Parasitic channel mitigation in III-nitride material semiconductor structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012115541A2 (en) * 2011-02-24 2012-08-30 Yury Georgievich Shreter Light-emitting semiconductor device
CN104170100A (zh) * 2012-03-14 2014-11-26 首尔伟傲世有限公司 发光二极管及其制造方法
CN103000776A (zh) * 2012-11-14 2013-03-27 深圳大学 Led芯片及led芯片的制造方法

Also Published As

Publication number Publication date
US20240154063A1 (en) 2024-05-09
CN117063302A (zh) 2023-11-14
TW202243284A (zh) 2022-11-01
TWI833198B (zh) 2024-02-21

Similar Documents

Publication Publication Date Title
US8686474B2 (en) III-V compound semiconductor epitaxy from a non-III-V substrate
US8580590B2 (en) Method for manufacturing polychromatic light emitting diode device having wavelength conversion layer made of semiconductor
TWI416615B (zh) 分離二種材料系統之方法
US8435820B2 (en) Patterned substrate for hetero-epitaxial growth of group-III nitride film
US9356191B2 (en) Epitaxial layer wafer having void for separating growth substrate therefrom and semiconductor device fabricated using the same
US8486730B2 (en) Method of separating light-emitting diode from a growth substrate
TW200306019A (en) Process for producing group III nitride compound semiconductor, group III nitride compound semiconductor component, and method for producing group III nitride compound semiconductor substrate
US8133803B2 (en) Method for fabricating semiconductor substrates and semiconductor devices
US20140151714A1 (en) Gallium nitride substrate and method for fabricating the same
JP2022533787A (ja) パッシベーション層を含む発光ダイオード前駆体
US20230053953A1 (en) Group iii nitride structures and manufacturing methods thereof
WO2022217539A1 (zh) 半导体结构及其制作方法
WO2022077254A1 (zh) 微型led结构的制作方法
US8048786B2 (en) Method for fabricating single-crystalline substrate containing gallium nitride
WO2022217542A1 (zh) 半导体结构及其制作方法
US20230073455A1 (en) Group-iii-nitride structures and manufacturing methods thereof
JP7338045B2 (ja) 発光ダイオードおよび発光ダイオードの形成方法
US20210210656A1 (en) Method for micro-led epitaxial wafer manufacturing and micro-led epitaxial wafer
TWI792110B (zh) 半導體結構及其製作方法
TWI797513B (zh) 半導體結構及其製作方法
US20210043460A1 (en) Manufacturing method of a semiconductor substrate
KR20100020936A (ko) 파티션화된 기판 상에 제작되는 반도체 소자용 고품질 경계부 형성 방법
CN116210071A (zh) 一种半导体结构及其制备方法
WO2022052097A1 (zh) 发光二极管及其制备方法
CN117672821A (zh) 一种半导体结构及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21936421

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 18549479

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 202180096215.6

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21936421

Country of ref document: EP

Kind code of ref document: A1