WO2017088546A1 - 发光二极管及其制作方法 - Google Patents

发光二极管及其制作方法 Download PDF

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Publication number
WO2017088546A1
WO2017088546A1 PCT/CN2016/097806 CN2016097806W WO2017088546A1 WO 2017088546 A1 WO2017088546 A1 WO 2017088546A1 CN 2016097806 W CN2016097806 W CN 2016097806W WO 2017088546 A1 WO2017088546 A1 WO 2017088546A1
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Prior art keywords
nitride layer
layer
type nitride
gallium
type
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PCT/CN2016/097806
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English (en)
French (fr)
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张洁
朱学亮
杜成孝
刘建明
徐宸科
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厦门市三安光电科技有限公司
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Publication of WO2017088546A1 publication Critical patent/WO2017088546A1/zh
Priority to US15/723,720 priority Critical patent/US10263147B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to the field of semiconductors, and more particularly to a vertical light emitting diode having a good n-type ohmic contact and a method of fabricating the same.
  • the surface of the GaN thin film exposed after the substrate is peeled off is generally a nitrogen polar surface, and the metal ohmic contact characteristics of the nitrogen polarity and the gallium polar surface are greatly different, and the conventional Ti/ The Al metal electrode can form a very stable ohmic contact with the gallium polar GaN, but it is difficult to obtain a stable ohmic contact with the nitrogen polar GaN, and the forward working voltage rises after the failure, which seriously deteriorates the performance stability of the vertical GaN chip.
  • the present invention provides a vertical light emitting diode having a good n-type ohmic contact and a manufacturing method thereof, which overcomes the poor stability of the n-plane GaN ohmic contact electrode existing in the existing vertical chip, resulting in chip voltage reliability. problem.
  • the present invention first provides an LED epitaxial structure for a vertical chip, comprising: a substrate having opposite upper and lower surfaces, a portion of the upper surface being nitrided; an n-type nitride layer, forming a crystal having a nitrogen polarity and a gallium polarity crystal on the upper surface of the substrate, wherein the nitrogen polarity crystal is grown over a region where the substrate is nitrided, and the nitrogen polarity is The surface of the gallium polar region exhibits a height difference; n a recovery layer formed on the n-type nitride layer, the upper surface of which is a connected gallium polar surface; an active layer formed on the n-type recovery layer; and a p-type layer formed on the active layer .
  • the present invention also provides a vertical LED chip comprising, in order from bottom to top, a conductive substrate, a p-type nitride layer, an active layer, an n-type recovery layer, an n-type nitride layer, and an n-electrode.
  • the n-type nitride layer has a nitrogen-polar crystal and a gallium-polar crystal, and the surface of the nitrogen polarity and the gallium polarity region exhibits a height difference, and the n-type recovery layer is adjacent to the n-type
  • One side surface of the nitride layer has a mixing polarity consistent with the n-type nitride layer, and a side surface contacting the n-type nitride layer is a connected gallium polar surface.
  • a region where the upper surface of the substrate is nitrided is a strip or block pattern periodically arranged, and the size of the pattern is 10 to 200 nm.
  • the crystal of the nitrogen polarity of the n-type nitride layer and the crystal of the gallium polarity are alternately arranged; the thickness of the n-type recovery layer is 0.3 ⁇ 1 ⁇ , The impurity concentration is 2el7cm ⁇ ⁇ 5el8cm 3 ; at least half of the upper surface of the n-type nitride layer is a gallium polar surface.
  • the present invention also provides a method for fabricating a vertical LED chip, comprising the steps of: 1) providing a substrate having opposing upper and lower surfaces, nitriding a partial region of the upper surface; 2) An n-type nitride layer having a nitrogen-polar crystal and a gallium-polar crystal grown on the upper surface of the substrate, wherein the nitrogen-polar crystal is grown over the nitrided region of the substrate, and The surface of the nitrogen polarity and the gallium polarity region exhibits a height difference; 3) growing an n-type recovery layer on the n-type nitride layer, the upper surface of which is a connected gallium polar surface; 4) in the n-type The recovery layer sequentially grows the active layer and the p-type nitride layer to form an LED epitaxial structure; 5) providing a conductive substrate to be bonded to a surface of the p-type nitride layer of the LED epitaxial structure; 6) removing the a substrate of an
  • the region where the upper surface of the substrate is nitrided is a strip or block pattern periodically arranged, and the size of the pattern is 10 to 200 nm.
  • the step 3 by controlling the temperature, pressure and growth rate of growth, the lateral epitaxial ability of the gallium polar region is improved, and the gallium polar surface is connected after completion of the germanium.
  • the growth temperature is 1100 ⁇ 1150 ° C
  • the pressure is 100 ⁇ 150 torr
  • the growth rate is ⁇ /h or less.
  • step 6 removing the substrate to expose the surface of the epitaxial structure, using a wet method
  • the exposed surface is etched to form a surface having a height difference on the surface of the n-type nitride layer.
  • the subsequently grown n-type nitride layer has the same regular mixed polarity as the substrate nitridation process, ⁇ Because the nitrogen polarity growth rate is slightly slower than the gallium polarity, the surface nitrogen polarity and the gallium polarity region exhibit a regular height difference, and the exposed n-type nitride layer is removed after subsequent stripping of the substrate in the vertical chip process.
  • Surface nitrogen polarity is mixed with gallium polarity, and n is formed on the n-type nitride layer
  • the ohmic contact electrode can directly use the mature Ti/Al metal electrode to solve the problem of stability of the ohmic contact of the nitrogen polar surface, and to ensure the voltage reliability of the thin film GaN-based light-emitting device.
  • FIG. 1 is a cross-sectional view of an epitaxial structure of an LED for a vertical structure in accordance with an embodiment of the present invention.
  • FIG. 2 is a cross-sectional schematic view of a vertical LED chip having a good n-type ohmic contact in accordance with an embodiment of the present invention.
  • FIG. 3 is a flow chart of fabricating a vertical LED chip in accordance with an embodiment of the present invention.
  • FIG. 4 to FIG. 12 are schematic diagrams showing a process of fabricating a vertical LED chip according to an embodiment of the present invention.
  • FIG. 13 to FIG. 14 are schematic diagrams showing another part of a process for fabricating a vertical LED chip according to an embodiment of the present invention.
  • the present invention will be further described with reference to the accompanying drawings and preferred embodiments.
  • the LED structure proposed by the present invention may be modified within a certain range according to the application field and the process process implementation, and the material selection may be modified.
  • an LED epitaxial structure includes, in order from bottom to top, a substrate 1, a u-type nitride layer 2, an n-type nitride layer 3, an n-type recovery layer 4, and an n-type superlattice structure.
  • the preferred sapphire of the substrate 1 has a surface structure of a planar structure.
  • the upper surface of the substrate 1 is subjected to a local nitridation treatment in which the nitrided regions are strip-shaped or block-shaped.
  • black represents that the surface of the substrate has been nitrided, black and white stripes or
  • the block alternately represents the presence or absence of a region of the substrate surface where nitriding is performed.
  • the nitrided area should not be too small, so that the n-type nitride layer has a sufficiently large gallium polar surface area for making n-type ohmic contact.
  • the nitriding area should not be too large, otherwise it is difficult to grow the nitride layer. Considering the above two factors, the preferred values are 3: 7-7: 3, and the best value is 1:1.
  • the unintentionally dilute nitride layer (abbreviated as u-type nitride layer) 2 is formed on the surface of the substrate 1, which generally includes a low temperature buffer layer of 20 to 50 nm, a 3D nitride layer of 1 to 2 ⁇ m, and 1 ⁇ 2 ⁇ 2D nitride layer.
  • the u-type nitride layer 2 is composed of a nitride layer in which gallium polarity and nitrogen polarity are alternately arranged.
  • the surface of the nitrogen polarity and the gallium polarity region exhibits a height difference, wherein the nitride layer of nitrogen polarity is located above the region where the substrate is nitrided.
  • the n-type nitride layer 3 is formed on the surface of the u-type nitride layer 2, and is also composed of a nitride layer in which the gallium polarity and the nitrogen polarity are alternately arranged, and may be miscellaneous with Si, Ge, Se, or
  • the GaN layer or the AlGaN layer of Te has a thickness of 1.5 to 4 ⁇ m. Since the nitrogen polar nitride growth rate is slightly slower than the gallium polar nitride, the surface height difference between the nitrogen polarity and the gallium polarity region is increased.
  • the n-type recovery layer 4 is formed on the surface of the n-type nitride layer 3, and the Z-type gallium nitride material can be selected to increase the gallium polarity region side by controlling the temperature, pressure and growth rate during growth.
  • the epitaxial ability is such that the upper surface of the Ga polar surface is connected.
  • the n-type recovery layer 4 has a thickness of 0.3 to 1 ⁇ m and a miscellaneous concentration of 2E17 cm 3 to 5 E18 cm -3 .
  • the n-type superlattice structure layer 5 is formed on the surface of the n-type recovery layer, and may be a multilayer structure of a carbon nitride or nitride containing a group II, III, or IV element, such as InGaN/GaN, AlGaN. /GaN, InGaN/GaN/AlGaN, or AlGaN/GaN/InGaN.
  • a group II, III, or IV element such as InGaN/GaN, AlGaN. /GaN, InGaN/GaN/AlGaN, or AlGaN/GaN/InGaN.
  • the active layer 6 is formed on the surface of the n-type superlattice layer 5, and may be a multi-quantum well structure, with an InGaN layer as a well layer and a GaN layer as a barrier layer, wherein the well layer has a film thickness of 18 ⁇ 30 people, the film thickness of the barrier layer is 80 to 200 people.
  • the p-type nitride layer 7 is formed on the surface of the active layer 6 to have a thickness of 50 to 150 nm.
  • a Mg-indium aluminum nitride indium gallium layer may be interposed between the p-type nitride layer 7 and the active layer 6 as an electron blocking layer having a thickness of 10 to 30 nm.
  • the p-type contact layer 8 is formed on the surface of the p-type nitride layer 7, and is made of p-type gallium nitride having a thickness of 5 to 10 nm.
  • FIG. 2 is a cross-sectional schematic view of a vertical LED chip having a good n-type ohmic contact in accordance with an embodiment of the present invention.
  • the LED epitaxial structure shown in FIG. 1 is flip-chip bonded to the surface of the conductive substrate 9, and the substrate 1 and the u-type nitride layer 2 are removed, and the surface of the exposed n-type nitride layer 3 is nitrogen.
  • the polarity is mixed with the gallium polarity, and the n-type ohmic contact electrode 10 is formed on the surface of the n-type nitride layer 3, which is a direct Ti/Al metal electrode.
  • FIG. 3 is a flow chart of manufacturing a vertical LED chip according to an embodiment of the present invention, which includes steps S100 to S6 00, wherein steps S100 to S400 are epitaxial processes, and S500 to S600 are chip processes, and FIG. 4 is combined below. 12 Detailed instructions.
  • Step S100 providing a flat substrate 1, a partial region of the upper surface of the nitride substrate.
  • black indicates that the surface of the substrate has been nitrided, and black-and-white strips or blocks alternately represent the presence or absence of nitridation on the surface of the substrate.
  • a strip or block region mask is formed on the surface of the substrate, and the mask pattern has a period size of 10 to 200 nm, and the surface unmasked region is nitrided by NH3 or other N source under high temperature conditions by MOCVD or other equipment. , remove the mask.
  • Step S200 growing a u-type nitride layer and an n-type nitride layer on the upper surface of the substrate, which are a mixture of nitrogen polarity and gallium polarity, and a surface of a nitrogen polarity and a gallium polarity region.
  • a height difference is exhibited in which a crystal of nitrogen polarity is grown over the nitrided region of the substrate as shown in FIG. Specifically: put the substrate into the MOCV D cavity, heat up to 1100 ⁇ 1150 °C, reduce the pressure to 100 ⁇ 300torr, and pass H 2
  • the pressure is maintained at 300-500 torr, annealing at this temperature for 1 to 5 minutes, then introducing trimethylgallium, growing 1 ⁇ 2 ⁇ of non-tideous gallium nitride; continuing to heat up to 1050-1150 ° C, pressure Reduce to 200 ⁇ 300t orr, grow 1 ⁇ 2 ⁇ thick non-tideous GaN; cool down to 1030 ⁇ 1120°C, maintain pressure at 200-300tor r, grow 1.5 ⁇ 4 ⁇ n-type GaN, pass into A Silanes are cumbersome.
  • the epitaxial layer will have the same polarity as the substrate nitride, but because the nitrogen polarity growth rate is slightly slower than the gallium polarity, the surface nitrogen polarity and gallium polarity The area presents the height difference of the rules.
  • Step S300 forming an n-type recovery layer 4 on the n-type nitride layer 3, and improving the lateral epitaxial ability of the Ga polar region by controlling the temperature, pressure, and growth rate of growth, and connecting the surface of the germanium gallium polar surface , as shown in Figure 7. Specifically, the temperature is raised to 1100-1150 ° C, the pressure is reduced to below 100-150 torr, and the growth rate is reduced to ⁇ /h.
  • the growth layer of ⁇ -type GaN is 0.3 ⁇ 1 ⁇ , and the Si impurity concentration is 2el7cm 3 ⁇ 5el8cm 3 .
  • Step S400 sequentially growing an n-type superlattice structure layer 5, an active layer 6, a p-type nitride layer 7, and a p-type contact layer 8 in the n-type recovery layer 4 to form an LED epitaxial structure, as shown in FIG. Show. Specifically: First, the temperature is lowered to 750 ⁇ 900 °C, the pressure is increased to 200 ⁇ 300torr, and the InGaN/GsN superlattice layer is grown for 10 ⁇ 30 cycles.
  • the thickness of InGaN in each period is 1-3 nm, GaN Thickness range 2 ⁇ -10nm; Next, the temperature is maintained at 750 ⁇ 900 °C, the pressure is maintained at 200 ⁇ 300torr, and the InGaN/GaN multiple quantum well layer is grown for 4 ⁇ 15 cycles.
  • the thickness of InGaN is 2 ⁇ 4nm in each period.
  • the thickness of GaN is 5 ⁇ 15nm; then, the temperature is raised to 800 ⁇ 950°C, the pressure is reduced to 100 ⁇ 150torr, and the p-type AlGaN electron blocking layer is grown; then, the temperature is raised to 900 ⁇ 1050°C, and the pressure is raised to 200 ⁇ 300torr grows p-type GaN with a thickness of 50 ⁇ 150nm. Finally, a heavily p-type GaN contact layer is grown at 900 ⁇ 1050°C with a thickness of 5 ⁇ 10nm.
  • Step S500 providing a conductive substrate 9, bonding the LED epitaxial structure to the conductive substrate 9 by a wafer bonding technique or an electroplating technique, as shown in FIG.
  • the conductive substrate 9 may be a Si substrate or other metal substrate having good thermal conductivity, and bonded by a bonding layer having good thermal conductivity and strong mechanical bonding force, such as Au, Ag, Cu, Pt, Pd, Al, and the like.
  • a mirror system can also be provided between the conductive substrate 9 and the p-type contact layer 8.
  • Step S600 removing the substrate 1 of the LED epitaxial structure, exposing the surface of the n-type nitride layer 3, forming the n-electrode 10 thereon, and forming the p-electrode 11 on the back surface of the conductive substrate 9, as shown in FIG. Shown.
  • the substrate 1 is first removed by a laser lift-off technique, as shown in FIG. 10; then, the u-type nitride layer 2 is removed by dry etching, and the n-type nitride layer is exposed, as shown in FIG.
  • the n-type nitride layer 3 has a surface nitrogen polarity and a gallium polarity mixed, and the n-electrode 10 is formed on the n-type nitride layer 3, and 50% of the area is in contact with the gallium polar nitride layer, and can be directly used for maturity.
  • Ti/Al metal electrode to solve the ohmic contact of the nitrogen polar surface The stability problem ensures the voltage reliability of the thin film GaN-based light-emitting device.
  • FIG. 13 to FIG. 14 are schematic diagrams showing another part of a process for fabricating a vertical LED chip according to an embodiment of the present invention.
  • step S600 after the substrate 1 is removed, the u-type nitride layer 2 is removed by wet etching, because the nitrogen polar region is etched faster, thereby increasing the surface roughness.
  • the height difference as shown in FIG. 13, can be used as a light-taking structure on the one hand, and increase the contact area between the sidewall of the gallium polarity region and the n-electrode on the other hand, further reducing the voltage of the chip, and improving the n-electrode and Adhesion of the epitaxial layer.

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Abstract

一种LED外延、芯片结构及其制作方法，其中芯片自下而上依次包括：导电基板（9）、p型氮化物层（7）、有源层（6）、n型恢复层（4）、n型氮化物层（3）和n电极（10），其特征在于：所述n型氮化物层（3）具有氮极性的晶体和镓极性的晶体，且所述氮极性和镓极性区域的表面呈现高度差，所述n型恢复层（4）邻近所述n型氮化物层（3）的一侧表面具有与所述n型氮化物层（3）一致的混合极性，远离所述n型氮化物层（3）接触的一侧表面为相连的镓极性表面。

Description

发光二极管及其制作方法
技术领域
[0001] 本发明涉及半导体领域， 具体为一种具有良好 n型欧姆接触的垂直发光二极管 其及制作方法。
背景技术
[0002] 近年来， 随着衬底转移技术的成熟， 垂直结构芯片技术越来越多地被业界应用 ， 其一般在蓝宝石衬底上通过 MOCVD沉积 GaN基薄膜， 然后把 GaN基薄膜通过 晶圆键合技术或电镀技术黏结到半导体或金属基板上， 再把蓝宝石衬底剥离去 除。 此种技术因为较高的光萃取效率、 电流扩展能力及导热能力， 有效的提高 了 GaN基 LED芯片的发光效率， 特别是在高电流密度大功率应用领域体现出越来 越明显的优势。
[0003] 然而， 在前述垂直结构芯片技术中， 衬底剥离后暴露的 GaN薄膜表面一般为氮 极性面， 而氮极性和镓极性面的金属欧姆接触特性相差极大， 常规 Ti/Al金属电 极可以与镓极性 GaN形成非常稳定的欧姆接触， 但是与氮极性 GaN很难获得稳定 的欧姆接触， 失效后正向工作电压升高， 严重恶化了垂直 GaN芯片的性能稳定 性。
技术问题
问题的解决方案
技术解决方案
[0004] 针对上述问题， 本发明提供了一种具有良好 n型欧姆接触的垂直发光二极管及 其制作方法， 以克服现有垂直芯片存在的 n面 GaN欧姆接触电极稳定性差而导致 芯片电压可靠性问题。
[0005] 本发明首先提供了一种用于垂直芯片的 LED外延结构， 包括： 衬底， 具有相对 的上、 下表面， 所述上表面的部分区域被氮化； n型氮化物层， 形成于所述衬底 的上表面， 具有氮极性的晶体和镓极性的晶体， 其中所述氮极性的晶体生长于 所述衬底被氮化的区域上方， 且所述氮极性和镓极性区域的表面呈现高度差； n 型恢复层， 形成于 n型氮化物层上， 其上表面为相连的镓极性表面； 有源层， 形 成于所述 n型恢复层上； p型层， 形成于所述有源层上。
[0006] 本发明同吋提供了一种垂直 LED芯片， 自下而上依次包括： 导电基板、 p型氮 化物层、 有源层、 n型恢复层、 n型氮化物层和 n电极。 其中， 所述 n型氮化物层 具有氮极性的晶体和镓极性的晶体， 且所述氮极性和镓极性区域的表面呈现高 度差， 所述 n型恢复层邻近所述 n型氮化物层的一侧表面具有与所述 n型氮化物层 一致的混合极性， 远离所述 n型氮化物层接触的一侧表面为相连的镓极性表面。
[0007] 优选地， 在前述 LED外延结构中， 所述衬底上表面被氮化的区域为周期性排列 的条状或者块状图案， 图案的尺寸为 10~200nm。
[0008] 优选地， 在前 LED外延结构及芯片中， 所述 n型氮化物层的氮极性的晶体和镓 极性的晶体交替排列； 所述 n型恢复层的厚度为 0.3~1μηι， 惨杂浓度为 2el7cm ^ ~5el8cm 3； 所述 n型氮化物层的上表面至少有一半为镓极性表面。
[0009] 本发明还提供了一种垂直 LED芯片的制作方法， 包括步骤： 1) 提供一具有相 对的上、 下表面的衬底， 氮化所述上表面的部分区域； 2) 在所述衬底的上表面 上生长 n型氮化物层， 其具有氮极性的晶体和镓极性的晶体， 其中所述氮极性的 晶体生长于所述衬底的被氮化区域上方， 且所述氮极性和镓极性区域的表面呈 现高度差； 3) 在所述 n型氮化物层上生长 n型恢复层， 其上表面为相连的镓极性 表面； 4) 在所述 n型恢复层依次生长有源层和 p型氮化物层， 构成 LED外延结构 ； 5) 提供一导电基板， 将其与前述 LED外延结构之 p型氮化物层一侧表面连结； 6) 移除所述 LED外延结构的衬底， 露出 n型氮化物层的表面， 在其上制作 n电极
[0010] 优选地， 所述步骤 1) 中， 衬底上表面被氮化的区域为周期性排列的条状或者 块状图案， 图案的尺寸为 10~200nm。
[0011] 优选地， 所述步骤 3) 中， 通过控制生长的温度、 压力和生长速率， 提高镓极 性区域侧向外延能力， 在完成吋形成镓极性表面相连。
[0012] 优选地， 所述步骤 3) 中， 生长温度为 1100~1150°C、 压力为 100~150torr， 生长 速率为 Ιμηι /h以下。
[0013] 在一些实施例中， 所述步骤 6) 中， 移除衬底露出外延结构的表面， 采用湿法 蚀刻该露出的表面， 在 n型氮化物层的表面形成具有高度差的表面。 发明的有益效果
有益效果
[0014] 在本发明中的 LED外延结构中， 由于事先对衬底进行部分区域的氮化处理， 其 后续生长的 n型氮化物层具有与衬底氮化工艺同规则的混合极性， 同吋由于氮极 性生长速率稍慢于镓极性， 所以表面的氮极性和镓极性区域呈现规则的高度差 ， 在后续进行垂直芯片工艺中剥离衬底后， 裸露的 n型氮化物层表面氮极性与镓 极性混合排列， 在该 n型氮化物层上制作 n
型欧姆接触电极吋可直接使用成熟的 Ti/Al金属电极， 解决氮极性面欧姆接触稳 定性的问题， 保证薄膜 GaN基发光器件的电压可靠性。
对附图的简要说明
附图说明
[0015] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明的 实施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描 述概要， 不是按比例绘制。
[0016] 图 1是根据本发明实施的一种用于垂直结构的 LED外延结构剖视图示意图。
[0017] 图 2是根据本发明实施的一种具有良好 n型欧姆接触的垂直 LED芯片的剖面示意 图。
[0018] 图 3是根据本发明实施的一种制作垂直 LED芯片的流程图。
[0019] 图 4~图12为根据本发明实施的一种制作垂直 LED芯片的过程示意图。
[0020] 图 13~图14为根据本发明实施的另一种制作垂直 LED芯片的部分过程示意图。
本发明的实施方式
[0021] 下面结合附图和优选的具体实施例对本发明做进一步说明。 在具体的器件设计 和制造中， 本发明提出的 LED结构将根据应用领域和工艺制程实施的需要， 可对 其部分结构和尺寸在一定范围内作出修改， 对材料的选取进行变通。
[0022] 图 1是根据本发明实施的一种用于垂直结构的 LED外延结构剖视图示意图。 [0023] 参看图 1， 一种 LED外延结构， 从下到上依次包括： 衬底 1、 u型氮化物层 2、 n 型氮化物层 3、 n型恢复层 4、 n型超晶格结构层 5、 有源层 6、 p型氮化物层 7和 p型 接触层 8。
[0024] 其中， 衬底 1的优选蓝宝石， 其表面结构为平面结构。 衬底 1的上表面作局部氮 化处理， 其中被氮化区域为条状或者块状， 请参考图 4和 5所示图案， 其中黑色 代表衬底表面已被氮化， 黑白色条状或块状交替代表衬底表面有无实施氮化的 区域交替。 关于氮化区域和无氮化区域的面积比例， 主要考虑两大因素： 第一 ， 氮化面积不宜过小， 使得 n型氮化物层具有足够大的镓极性表面积用于制作 n 型欧姆接触电极； 第二， 氮化面积不宜过大， 否则难以生长氮化物层。 综合考 虑前面两大因素， 其较佳的取值为 3: 7-7： 3， 最佳值为 1:1。
[0025] 非故意惨杂氮化物层 （简称 u型氮化物层） 2形成衬底 1的表面上， 其一般包括 2 0~50nm的低温缓冲层、 1~2μηι的 3D氮化物层和 1~2μηι的 2D氮化物层。 u型氮化物 层 2由镓极性和氮极性交替排列的氮化物层构成。 氮极性和镓极性区域的表面呈 现高度差， 其中氮极性的氮化物层位于衬底被氮化的区域上方。
[0026] n型氮化物层 3形成于 u型氮化物层 2的表面上， 同样由镓极性和氮极性交替排列 的氮化物层构成， 可以为惨杂有 Si、 Ge、 Se、 或者 Te的 GaN层或者 AlGaN层， 厚 度 1.5~4μηι。 由于氮极性氮化物生长速率稍慢于镓极性氮化物， 因此氮极性和镓 极性区域的表面高度差加大。
[0027] η型恢复层 4形成于 η型氮化物层 3的表面上， 可选用惨 Si氮化镓材料， 在生长过 程中通过控制生长的温度、 压力和生长速率， 提高镓极性区域侧向外延能力， 从而吋形成 Ga极性表面相连的上表面。 较佳的， n型恢复层 4的厚度为 0.3~1μηι， 惨杂浓度为 2E17cm 3~5E18cm - 3。
[0028] n型超晶格结构层 5形成于 n型恢复层的表面上， 可以为包含 II、 III、 或者 IV族元 素的氮化碳或者氮化物的多层结构， 诸如 InGaN/GaN、 AlGaN/GaN、 InGaN/GaN /AlGaN、 或者 AlGaN/GaN/InGaN等。
[0029] 有源层 6形成于 n型超晶格层 5的表面上， 可以为多量子阱结构， 以 InGaN层作为 阱层、 GaN层作为势垒层， 其中阱层的膜厚为 18人〜 30人， 势垒层的膜厚为 80人 〜200人。 [0030] p型氮化物层 7形成于有源层 6的表面之上， 厚度为 50~150nm。 可在 p型氮化物 层 7与有源层 6间插入一由惨杂了 Mg的氮化铝铟镓层作为电子阻挡层， 厚度为 10~ 30nm。
[0031] p型接触层 8形成于 p型氮化层 7的表面上， 采用重惨杂 p型氮化镓， 厚度为 5~10n m。
[0032] 图 2是根据本发明实施的一种具有良好 n型欧姆接触的垂直 LED芯片的剖面示意 图。
[0033] 参看图 2， 前述图 1所示的 LED外延结构倒装黏合至导电基板 9的表面上， 并去 除衬底 1和 u型氮化物层 2， 裸露的 n型氮化物层 3表面氮极性与镓极性混合排列， n型欧姆接触电极 10制作在 n型氮化物层 3的表面上， 其直接 Ti/Al金属电极。
[0034] 图 3是根据本发明实施的一种制作垂直 LED芯片的流程图， 其包括步骤 S100~S6 00， 其中步骤 S100~S400为外延工艺， S500~S600为芯片工艺， 下面结合图 4~12 进行详细说明。
[0035] 步骤 S100: 提供一平片衬底 1， 氮化衬底上表面的部分区域。 如图 4~5所示， 其 中黑色代表衬底表面已被氮化， 黑白色条状或块状交替代表衬底表面有无实施 氮化的区域交替。 具体为： 在衬底表面制作条状或者块状区域掩膜， 掩膜图案 周期尺寸在 10-200nm， 通过 MOCVD或者其他设备高温条件下通过 NH3或其他 N 源使表面未掩膜区域发生氮化， 去除掩膜。
[0036] 步骤 S200: 在前述衬底的上表面上生长 u型氮化物层、 n型氮化物层， 其为氮极 性与镓极性混合排列， 且氮极性和镓极性区域的表面呈现高度差， 其中氮极性 的晶体生长于衬底的被氮化区域上方， 如图 6所示。 具体为： 将衬底放入 MOCV D腔内， 升温至 1100~1150°C， 压力降低至 100~300torr， 通入 H 2
高温处理表面 5~10分钟； 降温至 500~600°C， 压力升高至 300~500torr， 通入氨气 和三甲基镓， 生长 20-50nm的低温缓冲层， 然后关闭三甲基镓； 升温至 1000~110 0。C， 压力保持 300-500torr， 在此温度下进行退火处理 1~5分钟， 然后通入三甲基 镓， 生长 1~2μηι的非惨杂氮化镓； 继续升温至 1050-1150°C， 压力降低至 200~300t orr, 生长 1~2μηι厚的非惨杂氮化镓； 降温至 1030~1120°C， 压力保持在 200-300tor r, 生长 1.5~4μηι的 n型氮化镓， 通入甲硅烷进行惨杂。 因为对衬底作区域性氮化 处理， 所以 n型 GaN层生长完吋外延层会出现与衬底氮化同图案的混合极性， 但 是因为氮极性生长速率稍慢于镓极性， 所以表面的氮极性和镓极性区域呈现规 则的高度差。
[0037] 步骤 S300: 在 n型氮化物层 3上形成 n型恢复层 4， 通过控制生长的温度、 压力和 生长速率， 提高 Ga极性区域侧向外延能力， 在完成吋镓极性表面相连， 如图 7所 示。 具体为： 升温至 1100-1150°C， 压力降低至 100-150torr以下， 生长速率降低 至 Ιμηι/h以下生长厚度为 0.3~1μηι的 η型 GaN恢复层， Si惨杂浓度为 2el7cm 3 ~5el8cm 3。
[0038] 步骤 S400: 在 n型恢复层 4依次生长 n型超晶格结构层 5、 有源层 6、 p型氮化物层 7和 p型接触层 8， 构成 LED外延结构， 如图 8所示。 具体为： 首先， 降温至 750~9 00°C， 压力升高至 200~300torr， 生长 10~30个周期的 InGaN/GsN超晶格层， 每个 周期内 InGaN的厚度范围 l~3nm， GaN厚度范围 2~-10nm; 接着， 升温至 750~900 °C， 压力保持在 200~300torr， 生长 4~15个周期的 InGaN/GaN多量子阱层， 每个周 期内 InGaN的厚度为 2~4nm， GaN厚度为 5~15nm; 接着， 升温至 800~950°C， 压 力降低至 100~150torr， 生长 p型 AlGaN电子阻挡层； 接着， 升温至在 900~1050°C ， 压力升高至 200~300torr生长 p型 GaN， 厚度为 50~150nm; 最后， 在 900~1050°C 环境下生长重惨杂 p型 GaN接触层， 厚度为 5~10nm。
[0039] 步骤 S500: 提供导电基板 9， 通过晶圆键合技术或电镀技术将前述 LED外延结 构连结黏结到该导电基板 9， 如图 9所示。 具体地， 导电基板 9可采用 Si基板或其 他导热性良好的金属基板， 采用具有良好的导热性和强的机械结合力结合层进 行黏结， 诸如 Au、 Ag、 Cu、 Pt、 Pd、 Al等材料。 在一些较佳实施例中， 还可在 导电基板 9与 p型接触层 8之间设置反射镜系统。
[0040] 步骤 S600: 移除前述 LED外延结构的衬底 1， 露出 n型氮化物层 3的表面， 在其 上制作 n电极 10， 并在导电基板 9的背面制作 p电极 11， 如图 12所示。 具体的， 首 先采用激光剥离的技术去除衬底 1， 如图 10所示； 接着， 采用干蚀刻的方式去除 u型氮化物层 2， 裸露出 n型氮化物层， 如图 11所示， 裸露的 n型氮化物层 3表面氮 极性与镓极性混合排列， n电极 10制作在该 n型氮化物层 3上， 有 50%面积接触到 镓极性氮化物层上， 可直接使用成熟的 Ti/Al金属电极， 解决氮极性面欧姆接触 稳定性的问题， 保证薄膜 GaN基发光器件的电压可靠性。
[0041] 图 13~图14为根据本发明实施的另一种制作垂直 LED芯片的部分过程示意图。
[0042] 在本实施方式中， 在步骤 S600中， 移除衬底 1后， 采用湿法蚀刻的方式去除 u型 氮化物层 2， 由于氮极性区域蚀刻较快， 从而加大表面的凸凹高度差， 如图 13所 示， 如此一方面可作为取光结构， 另一方面增大镓极性区域的侧壁与 n电极的接 触面积， 进一步降低芯片的电压的同吋， 提升 n电极与外延层的粘附力。
[0043] 尽管已经描述本发明的示例性实施例， 但是理解的是， 本发明不应限于这些示 例性实施例而是本领域的技术人员能够在如下文的权利要求所要求的本发明的 精神和范围内进行各种变化和修改。

Claims

权利要求书
[权利要求 1] 一种用于垂直芯片的 LED外延结构， 包括：
衬底， 具有相对的上、 下表面， 所述上表面的部分区域被氮化； n型氮化物层， 形成于所述衬底的上表面， 具有氮极性的晶体和镓极 性的晶体， 其中所述氮极性的晶体生长于所述衬底被氮化的区域上方
， 且所述氮极性和镓极性区域的表面呈现高度差； n型恢复层， 形成于 n型氮化物层上， 其上表面为相连的镓极性表面； 有源层， 形成于所述 n型恢复层上；
p型层， 形成于所述有源层上。
[权利要求 2] 根据权利要求 1所述的 LED外延结构， 其特征在于： 所述衬底上表面 被氮化的区域为周期性排列的条状或者块状图案， 图案的尺寸为 10~2 00nm。
[权利要求 3] 根据权利要求 1所述的 LED外延结构， 其特征在于： 所述 n型氮化物层 的氮极性的晶体和镓极性的晶体交替排列。
[权利要求 4] 根据权利要求 1所述的 LED外延结构， 其特征在于： 所述 n型恢复层的 厚度为 0.3~1μηι， 惨杂浓度为 2el7cm 3~5el8cm - 3。
[权利要求 5] —种垂直 LED芯片， 自下而上依次包括： 导电基板、 p型氮化物层、 有源层、 n型恢复层、 n型氮化物层和 n电极， 其特征在于： 所述 n型氮 化物层具有氮极性的晶体和镓极性的晶体， 且所述氮极性和镓极性区 域的表面呈现高度差， 所述 n型恢复层邻近所述 n型氮化物层的一侧表 面具有与所述 n型氮化物层一致的混合极性， 远离所述 n型氮化物层接 触的一侧表面为相连的镓极性表面。
[权利要求 6] 根据权利要求 5所述的一种垂直 LED芯片， 其特征在于： 所述 n型氮化 物层中， 氮极性的晶体和镓极性的晶体交替排列。
[权利要求 7] 根据权利要求 5所述的一种垂直 LED芯片， 其特征在于： 所述 n型氮化 物层的上表面至少有一半为镓极性表面。
[权利要求 8] 根据权利要求 5所述的一种垂直 LED芯片， 其特征在于： 所述 n型恢复 层的厚度为 0.3~1μηι， 惨杂浓度为 2el7cm 3~5el8cm - 3。 一种垂直 LED芯片的制作方法， 包括步骤：
1) 提供一具有相对的上、 下表面的衬底， 氮化所述上表面的部分区 域；
2) 在所述衬底的上表面上生长 n型氮化物层， 其具有氮极性的晶体和 镓极性的晶体， 其中所述氮极性的晶体生长于所述衬底的被氮化区域 上方， 且所述氮极性和镓极性区域的表面呈现高度差；
3) 在所述 n型氮化物层上生长 n型恢复层， 其上表面为相连的镓极性 表面；
4) 在所述 n型恢复层依次生长有源层和 p型氮化物层， 构成 LED外延 结构；
5) 提供一导电基板， 将其与前述 LED外延结构之 p型氮化物层一侧表 面连结；
6) 移除所述 LED外延结构的衬底， 露出 n型氮化物层的表面， 在其上 制作 n电极。
根据权利要求 9所述的垂直 LED芯片的制作方法， 其特征在于： 所述 步骤 1) 中， 衬底上表面被氮化的区域为周期性排列的条状或者块状 图案， 图案的尺寸为 10~200nm。
根据权利要求 9所述的垂直 LED芯片的制作方法， 其特征在于： 所述 步骤 3) 中， 通过控制生长的温度、 压力和生长速率， 提高镓极性区 域侧向外延能力， 在完成吋形成镓极性表面相连。
根据权利要求 11所述的垂直 LED芯片的制作方法， 其特征在于： 所述 步骤 3) 中， 生长温度为 1100~1150°C、 压力为 100~150torr， 生长速率 为 1μηι/1ι以下。
根据权利要求 9所述的垂直 LED芯片的制作方法， 其特征在于： 所述 步骤 6) 中， 移除衬底露出外延结构的表面， 采用湿法蚀刻该露出的 表面， 在 n型氮化物层的表面形成具有高度差的表面。
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