WO2020206926A1 - 驱动芯片及显示面板 - Google Patents

驱动芯片及显示面板 Download PDF

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Publication number
WO2020206926A1
WO2020206926A1 PCT/CN2019/105014 CN2019105014W WO2020206926A1 WO 2020206926 A1 WO2020206926 A1 WO 2020206926A1 CN 2019105014 W CN2019105014 W CN 2019105014W WO 2020206926 A1 WO2020206926 A1 WO 2020206926A1
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WO
WIPO (PCT)
Prior art keywords
input pin
pin group
bonding pad
group
pins
Prior art date
Application number
PCT/CN2019/105014
Other languages
English (en)
French (fr)
Inventor
卢延涛
刘广辉
王超
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/612,785 priority Critical patent/US11189584B2/en
Publication of WO2020206926A1 publication Critical patent/WO2020206926A1/zh
Priority to US17/509,000 priority patent/US11676921B2/en

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present application relates to the field of display technology, and in particular to a driving chip and a display panel.
  • the driving chip 10 is bound to the glass substrate of the display panel 100, and the flexible printed circuit board 20 is arranged on both sides of the driving chip 10 so that the display panel 100 realizes a narrow frame.
  • the flexible printed circuit board 20 is bound to both sides of the driving chip 10
  • the wire electrically connecting the flexible printed circuit board 20 and the driving chip 10 will be too long, and the long wire will cause too much impedance, which may cause the display panel to malfunction. display.
  • the purpose of this application is to provide a driver chip and a display panel.
  • the bonding pads of the display panel and the input pins on the driver chip have a small distance, so that the impedance of the connecting wires between the two is reduced, so that the display The panel displays normally.
  • a display panel comprising a display area and a non-display area located outside the display area, the non-display area is provided with a driving chip and a plurality of first bindings arranged on opposite sides of the driving chip Pads and a plurality of second bonding pads, the driver chip includes a plurality of input pins, the plurality of input pins include a first input pin group and a second input pin group, the first input The pin group is disposed close to the first bonding pad, the second input pin group is disposed close to the second bonding pad, and the first input pin group and the second input pin group are Have spacing between.
  • the first input pin group and the second input pin group are arranged side by side on the same side of the driving chip.
  • the driving chip further includes a plurality of output pins.
  • a plurality of the output pins are arranged side by side with the first input pin group and the second input pin group and are located in the first input pin group and the second input pin group. Between the foot groups.
  • a plurality of the output pins are arranged on opposite sides of the first input pin group and the second input pin group.
  • the driving chip further includes a plurality of dummy pins.
  • a plurality of the output pins, the first input pin group and the second input pin group are arranged side by side on a side of the driving chip away from the display area, and a plurality of The output pin is located between the first input pin group and the second input pin group, and a plurality of the virtual pins are located on a side of the driving chip close to the display area.
  • the first bonding pad close to the first input pin and the first input pin close to the first bonding pad are electrically connected by a first wire, which is far away
  • the first bonding pad of the first input pin is electrically connected to the first input pin far away from the first bonding pad through a second wire.
  • a plurality of the output pins, the first input pin group and the second input pin group are arranged side by side on the side of the driving chip close to the display area, and a plurality of The output pin is located between the first input pin group and the second input pin group, and the plurality of dummy pins are located on a side of the driving chip away from the display area.
  • the first bonding pad close to the first input pin and the first input pin far from the first bonding pad are electrically connected by a first wire, which is far away
  • the first bonding pad of the first input pin and the first input pin close to the first bonding pad are electrically connected by a second wire.
  • a plurality of the output pins are located on a side of the driving chip close to the display area, and a plurality of the dummy pins are related to the first input pin group and the second input lead.
  • the pin groups are arranged side by side on a side of the driving chip away from the display area, and a plurality of the dummy pins are located between the first input pin group and the second input pin group.
  • the height of at least part of the first bonding pads of the plurality of first bonding pads and at least part of the second bonding pads of the plurality of second bonding pads increases from a direction close to the drive chip to a direction away from the drive chip.
  • the at least part of the first bonding pad is a first bonding pad group
  • the at least part of the second bonding pad is a third bonding pad group
  • the The first bonding pads of the first bonding pad group are arranged continuously or discontinuously
  • the second bonding pads of the third bonding pad group are arranged continuously or discontinuously.
  • a driver chip the driver chip includes a plurality of input pins, the plurality of input pins include a first input pin group and a second input pin group, the first input pin group and the first input pin group Two input pin group interval setting.
  • the first input pin group and the second input pin group are located on the same side of the driver chip and arranged side by side.
  • the driving chip further includes a plurality of output pins, and the plurality of output pins are arranged side by side with the first input pin group and the second input pin group and a plurality of the The output pin is located between the first input pin group and the second input pin group.
  • the driver chip further includes a plurality of output pins, and the plurality of output pins are arranged on opposite sides of the first input pin and the second input pin.
  • the driver chip further includes a plurality of virtual pins, and the plurality of virtual pins are arranged side by side with the first input pin group and the second input pin group, and a plurality of the The dummy pin is located between the first input pin group and the second input pin group.
  • the driver chip further includes a plurality of dummy pins, and the plurality of dummy pins are arranged on opposite sides of the first input pin and the second input pin.
  • the present application provides a driving chip and a display panel.
  • the display panel includes a driving chip and a plurality of first bonding pads and a plurality of second bonding pads arranged on opposite sides of the driving chip.
  • the driving chip includes a plurality of input leads.
  • the multiple input pins include a first input pin group and a second input pin group.
  • the first input pin group and the second input pin group are spaced apart, and the first input pin group is close to the multiple A bonding pad, and the second input pin group is close to a plurality of second bonding pads, so that the first input pin and the first bonding pad, and the second input pin and the second bonding pad are welded
  • the distance between the disks is reduced, so that the wires that electrically connect the first input pin and the first bonding pad and that electrically connect the second input pin and the second bonding pad become shorter, and the impedance of the wire becomes shorter. Small, so that the drive chip normally inputs electrical signals, so that the display panel can display normally.
  • FIG. 1 is a schematic diagram of a driving chip and a flexible printed circuit board bound to a display panel in a conventional technology
  • FIG. 2 is a schematic diagram of the structure of the display panel according to the first embodiment of the application.
  • 3A is a first schematic diagram of a plurality of first bonding pads in the display panel shown in FIG. 2;
  • 3B is a second schematic diagram of a plurality of first bonding pads in the display panel shown in FIG. 2;
  • 3C is a third schematic diagram of a plurality of first bonding pads in the display panel shown in FIG. 2;
  • 3D is a fourth schematic diagram of a plurality of first bonding pads in the display panel shown in FIG. 2;
  • FIG. 3E is a fifth schematic diagram of a plurality of first bonding pads in the display panel shown in FIG. 2;
  • FIG. 4 is a schematic structural diagram of a display panel according to a second embodiment of the application.
  • FIG. 5 is a schematic structural diagram of a display panel according to a third embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a display panel according to a fourth embodiment of the application.
  • FIG. 7 is a schematic structural diagram of a display panel according to a fifth embodiment of the application.
  • FIG. 8 is a schematic structural diagram of a display panel according to a sixth embodiment of the application.
  • FIG. 2 is a schematic structural diagram of a display panel according to the first embodiment of the application.
  • the display panel 100 is a liquid crystal display panel or an organic light emitting diode display panel.
  • the display panel 100 has a display area 100a and a non-display area 100b, and the non-display area 100b is located outside the display area 100a.
  • the display area 100a is used to display images.
  • the non-display area 100b is provided with a driving chip 11, a plurality of first bonding pads 141, and a plurality of second bonding pads 142.
  • the driving chip 11 is located in the middle of one end of the non-display area 100 b of the display panel 100.
  • the driving chip 11 includes a plurality of input pins, a plurality of output pins 113 and a plurality of dummy pins 114, and the plurality of input pins includes a first input pin group 111 and a second input pin group 112.
  • Both the first input pin group 111 and the second input pin group 112 are used to input electrical signals to the driving chip 11.
  • the first input pin group 111 includes a plurality of first input pins 1111
  • the second input pin group 112 includes a plurality of second input pins 1121.
  • the bonding pad 142 that is, the first input pin 1111 is centrally arranged on the side of the driving chip 11 close to the first bonding pad 141, and the second input pin 1121 is centrally arranged on the driving chip 11 close to the second bonding pad. 142 side.
  • the first input pin group 111 and the second input pin group 112 are arranged at both ends of the driving chip 11 at intervals, so that the plurality of first input pins 1111 in the first input pin group 111 to the first The distance between the bonding pads 141 becomes shorter, and the distance between the plurality of second input pins 1121 to the plurality of second bonding pads 142 in the second input pin group 112 becomes shorter.
  • the distances between the first input pin group 111 and the second input pin group 112 of the present application to the first bonding pad 141 and the second bonding pad 142 are closer, so that the first input pin is connected
  • the length of the wire connecting the pin 1111 and the first bonding pad 141 and the wire connecting the second input pin 1121 and the second bonding pad 142 is shorter, so that the impedance of the wire is smaller and the drive chip 11 can be input normally Electrical signals, so that the display panel displays normally.
  • the first input pin group 111 and the second input pin group 112 are respectively arranged on the side close to the first bonding pad 141 and the second bonding pad 142, thereby reducing the number of The length of the connecting wire between the bonding pad on the side far away from the driving chip 11 and the driving chip 11, thereby reducing the impedance of the wire, and enabling the display panel to display images normally.
  • the first input pin group 111 and the second input pin group 112 are arranged side by side on the same side of the driving chip 11.
  • the multiple output pins 113 are arranged side by side with the first input pin group 111 and the second input pin group 112 and are located between the first input pin group 111 and the second input pin group 112.
  • the plurality of output pins 113, the first input pin group 111 and the second input pin group 112 are arranged side by side on the side of the driving chip 11 away from the display area 100a, and the plurality of output pins 113 are located in the first input pin group.
  • a plurality of output pins 113 are also located in the middle of the driving chip 11 away from the display area 100a.
  • the plurality of first input pins 1111 are arranged side by side and at equal intervals, and the plurality of second input pins 1121 are arranged side by side and at equal intervals.
  • a plurality of output pins 113 are arranged side by side and at equal intervals. It can be understood that the first input pin group 111 and the second input pin group 112 can also be arranged alternately, as long as the distance from the plurality of first input pins 1111 to the plurality of first bonding pads 141 and the plurality of The distance between the second input pin 1121 and the plurality of second bonding pads 142 only needs to be shorter.
  • the size of the driver chip of the present application is basically unchanged from the traditional driver chip.
  • the first input pin group 111 and the second input pin group 112 arranged side by side, and the multiple The output pin 113 is arranged between the first input pin group 111 and the second input pin group 112.
  • this application screens the existing input pins, and discards the input pins that will not affect the electrical signal input of the driving chip after being discarded.
  • the input pins with the same function are partially discarded to make The number of input pins is reduced, and the remaining input pins are divided into the first input pin group 111 and the second input pin group 112, and the output pins 113 are set in the first input pin group 111 and the second input pin group 111. Between two input pin groups 112.
  • the spacing between the two can be set with multiple pins, including all output pins or multiple dummy pins in the traditional technology. Pin.
  • the plurality of dummy pins 114 are used to bind the driving chip 11 to the display panel 100 evenly.
  • a plurality of dummy pins 114 are located on the side of the driving chip 11 close to the display area 100a. Specifically, as shown in FIG. 2, a plurality of dummy pins 114 are arranged side by side in a straight line on the side of the driving chip 11 close to the display area 100 a.
  • the multiple dummy pins 114 are not connected to electrical signals.
  • the thickness of the plurality of dummy pins 114 perpendicular to the thickness direction of the driving chip 11 is equal to the thickness of the first input pin 1111, the second input pin 1121, and the output pin 113 perpendicular to the thickness direction of the driving chip 11.
  • the first input pin 1111 The thicknesses of the second input pin 1121 and the output pin 113 perpendicular to the thickness direction of the driving chip 11 are equal so that the driving chip 11 can be flatly bound on the glass substrate of the display panel 100.
  • the plurality of first bonding pads 141 and the plurality of second bonding pads 142 are respectively disposed on two opposite sides of the driving chip 11.
  • a plurality of first bonding pads 141 are located on the side of the driver chip 11 and adjacent to the display area 100a on the side of the driver chip 11, and a plurality of second bonding pads 142 are located on the side of the driver chip 11 and the display area 100a is located on the driver chip. 11 is adjacent to the side.
  • Each first input pin 1111 and each first bonding pad 141, and each second input pin 1121 and each second bonding pad 142 are connected by wires.
  • the height of at least part of the first bonding pad 141 of the plurality of first bonding pads 141 and the height of at least part of the second bonding pad 142 of the plurality of second bonding pads 142 range from being close to the driving chip 11 to far away
  • the direction of the driver chip 11 is increased to solve the problem that when the bonding pad height in the traditional technology is the same, the space close to the driver chip is small, and the space close to the driver chip is small, which makes the wires near the driver chip too crowded and may cause short circuits , Causing display abnormalities.
  • the first bonding pads 141 of the plurality of first bonding pads 141 are the first bonding pad group 141a, and the plurality of first bonding pads 141 also include other than the first bonding pads.
  • the second bonding pad group 141b other than the pad group 141a is fixed.
  • At least a part of the second bonding pads 142 of the plurality of second bonding pads 142 are the third bonding pad group 142a, and the plurality of second bonding pads 142 also include other than the third bonding pad group 142a. Outside the fourth bonding pad group 142b.
  • the first bonding pads 141 in the first bonding pad group 141a are arranged continuously or discontinuously, and the second bonding pads 142 in the third bonding pad group 142a are arranged continuously or discontinuously.
  • the height of the first bonding pads 141 in the first bonding pad group 141a increases in order from the direction close to the driving chip 11 to the direction away from the driving chip 11 and is arranged in series.
  • the first bonding pad group 141a is arranged close to the driving chip 11. On one side of the chip 11, the second bonding pad group 141 b is arranged on the side away from the driving chip 11.
  • the height of the second bonding pads 142 in the third bonding pad group 142a increases in order from the direction close to the driving chip 11 to the direction away from the driving chip 11 and is arranged in series.
  • the third bonding pad group 142a is arranged close to On one side of the driving chip 11, the fourth bonding pad group 142 b is arranged on the side away from the driving chip 11.
  • the height of at least part of the first bonding pads 141 of the plurality of first bonding pads 141 increases from a direction closer to the driving chip 11 to a direction away from the driving chip 11
  • the following uses a plurality of first bonding pads
  • the number of the fixed pads 141 is 6 for description, but the number of the plurality of first bonding pads 141 is not limited to 6.
  • the plurality of first bonding pads 141 sequentially includes a first sub-binding pad 1411, a second sub-binding pad 1412, a third sub-binding pad 1413, a fourth sub-binding pad 1414, a fifth sub-binding pad 1415, and a sixth Sub-bonding pad 1416.
  • FIG. 3A it is a first schematic diagram of a plurality of first bonding pads in the display panel shown in FIG. 2.
  • the plurality of first bonding pads 141 are all the first bonding pad group 141a, and the height of the first bonding pads 141 increases in order from being close to the driving chip 11 to far away from the driving chip 11, so that the first bonding pad 141 is close to the driving chip 11
  • the space above a bonding pad 141 for wiring wires is larger, so as to prevent the multiple wires connecting the first input pin 1111 and the first bonding pad 141 from being short-circuited, causing display abnormalities.
  • FIG. 3B it is a second schematic diagram of a plurality of first bonding pads in the display panel shown in FIG. 2.
  • the plurality of first bonding pads 141 includes a first bonding pad group 141a and a second bonding pad group 141b.
  • the second bonding pad group 141b is located between the first bonding pad group 141a and the driving chip 11.
  • the first bonding pad group 141a includes a fourth sub bonding pad 1414, a fifth sub bonding pad 1415, and a sixth sub bonding pad 1416
  • the second bonding pad group 141b includes a first sub bonding pad.
  • the pad 1411, the second sub-bonding pad 1412, and the third sub-bonding pad 1413 are examples of the pad 1413.
  • the height of the fourth sub bonding pad 1414 is smaller than the height of the fifth sub bonding pad 1415, and the height of the fifth sub bonding pad 1415 is smaller than the sixth sub bonding pad.
  • the height of the pad 1416 In order to increase the wiring space of the wires, the height of the first sub-binding pad 1411, the height of the second sub-binding pad 1412, and the height of the third sub-binding pad 1413 are less than or equal to the fourth sub-binding pad 1414 the height of.
  • the height of the first sub-binding pad 1411, the height of the second sub-binding pad 1412, and the height of the third sub-binding pad 1413 may also be greater than The height of the fourth sub-bonding pad 1414.
  • the plurality of first bonding pads 141 includes a first bonding pad group 141a and a second bonding pad group 141b.
  • the second bonding pad group 141b is located on both sides of the first bonding pad group 141a.
  • the first bonding pad group 141a includes a second sub bonding pad 1412, a third sub bonding pad 1413, and a fourth sub bonding pad 1414, and the second bonding pad group 141b includes a first sub bonding pad.
  • the pad 1411, the fifth sub bonding pad 1415, and the sixth sub bonding pad 1416 are examples of the first bonding pad 1416.
  • the height of the second sub bonding pad 1412 is smaller than the height of the third sub bonding pad 1413, and the height of the third sub bonding pad 1413 is smaller than the fourth sub bonding pad.
  • the height of 1414 In order to increase the wiring space of the wires, the height of the first sub-binding pad 1411 may be less than or equal to the height of the second sub-binding pad 1412, the height of the fifth sub-binding pad 1415, and the sixth sub-binding pad.
  • the height of 1416 may be greater than or equal to the height of the fourth sub-binding pad 1414. It can be understood that the height of the fifth sub-binding pad 1415 and the sixth sub-binding pad 1416 may also be smaller than the height of the fourth sub-binding pad 1414.
  • the plurality of first bonding pads 141 includes a first bonding pad group 141a and a second bonding pad group 141b.
  • the first bonding pad group 141a is located between the second bonding pad group 141b and the driving chip 11.
  • the first bonding pad group 141a includes a first sub bonding pad 1411, a second sub bonding pad 1412, and a third sub bonding pad 1413, and the second bonding pad group 141b includes a fourth sub bonding pad.
  • the pad 1414, the fifth sub bonding pad 1415, and the sixth sub bonding pad 1416 includes a fourth sub bonding pad.
  • the height of the first sub-binding pad 1411 is smaller than the height of the second sub-binding pad 1412, and the height of the second sub-binding pad 1412 is smaller than the height of the third sub-binding pad 1413.
  • the height of the fourth sub-binding pad 1414, the height of the fifth sub-binding pad 1415, and the height of the sixth sub-binding pad 1416 may be greater than or equal to the height of the third sub-binding pad 1413, or may be smaller than the height of the third sub-binding pad 1413.
  • the height of the three bonding pads 1413 is smaller than the height of the second sub-binding pad 1412, and the height of the second sub-binding pad 1412 is smaller than the height of the third sub-binding pad 1413.
  • the plurality of first bonding pads 141 includes a first bonding pad group 141a and a second bonding pad group 141b.
  • the first bonding pad group 141a may include any two first bonding pads 141 arranged at intervals.
  • the first bonding pad group 141a includes a first sub bonding pad 1411, a third sub bonding pad 1413, and a fifth sub bonding pad 1415
  • the second bonding pad group 141b includes a second bonding pad 1411.
  • the sub-binding pad 1412, the fourth sub-binding pad 1414, and the sixth sub-binding pad 1416 are examples of the sub-binding pad 1416.
  • the height of the first sub-binding pad 1411 is smaller than the height of the third sub-binding pad 1413, and the height of the third sub-binding pad 1413 is smaller than the height of the fifth sub-binding pad 1415.
  • the height of the second sub-binding pad 1412 may be between the height of the first sub-binding pad 1411 and the height of the third sub-binding pad 1413, or may be equal to the first sub-binding pad 1411 and the third sub-binding pad 1411. The height of any one of the sub-bonding pads 1413.
  • the height of the fourth sub-binding pad 1414 may be between the height of the third sub-binding pad 1413 and the height of the fifth sub-binding pad 1415, or may be equal to the height of the third sub-binding pad 1413 and Any one of the heights of the fifth sub-binding pad 1415.
  • the height of the sixth sub-binding pad 1416 may be greater than or equal to the height of the fifth sub-binding pad 1415, or may be less than the height of the fifth sub-binding pad 1415.
  • the first bonding pad 141 belonging to the second bonding pad group 141b between the first sub bonding pad 1411 and the third sub bonding pad 1413 The number of is not limited to one, but can also be multiple.
  • the number of the first bonding pads 141 belonging to the second bonding pad group 141b between the third sub bonding pad 1413 and the fifth sub bonding pad 1415 It is not limited to one, but may be multiple.
  • the arrangement of the plurality of second bonding pads 142 is the same as the arrangement of the plurality of first bonding pads 141, and will not be described in detail here.
  • the heights of at least part of the plurality of first bonding pads 141 gradually increase from being close to the driving chip 11 to being far away from the driving chip 11, and the heights of at least part of the second bonding pads 142 are increasing from being close to the driving chip 11 to far away from the driving chip 11.
  • the chip 11 is incremented one by one, thereby further avoiding the multiple wires connecting the first input pin 1111 and the first bonding pad 141 and the multiple wires connecting the second input pin 1121 and the second bonding pad 142 from each other. A short-circuit occurs between them, causing display abnormalities.
  • the plurality of first bonding pads 141 are arranged side by side at equal intervals and the areas of any two first bonding pads 141 are equal.
  • the plurality of second bonding pads 142 are arranged side by side at equal intervals and any two second bonding pads 142 are arranged side by side.
  • the fixed pads 142 have the same area.
  • the shapes of the plurality of first bonding pads 141 and the plurality of second bonding pads 142 are regular patterns or irregular patterns, and the regular patterns include rectangles and trapezoids.
  • the height difference between any two adjacent first bonding pads 141 is the same, and the height difference between any two adjacent second bonding pads 142 is the same.
  • the first bonding pad 141 (for example, the first sub-bonding pad 1411) near the first input pin 1111 and the first input pin 1111 near the first bonding pad 141 are electrically connected by a first wire 161
  • the first bonding pad 141 far away from the first input pin 1111 (for example, the sixth sub bonding pad 1416) and the first input pin 1111 far away from the first bonding pad 141 are electrically connected through the second wire 162
  • the length of the first wire 161 is less than the length of the second wire 162.
  • the first bonding pad 141 close to the first input pin 1111 is used to input the required wire resistance to the first input pin 1111 close to the first bonding pad 141
  • the first bonding pad 141 far from the first input pin 1111 is used to input an electrical signal with low wire resistance to the first input pin 1111 far from the first bonding pad 141.
  • the sector-shaped wiring 18 extending from the display area 100a to the driver chip 11 can use the upper space of the driver chip 11 (the virtual pin 114 in FIG. 2 is located in the space on the side of the driver chip 11), that is, the sector-shaped wiring Part of the space occupied by 18 overlaps with the space occupied by the driving chip 11, thereby shortening the distance between the display area 100a and the driving chip 11, thereby narrowing the lower frame of the display panel 100 in the embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a display panel according to a second embodiment of the application.
  • the display panel 100 shown in FIG. 4 is similar to the display panel substrate shown in FIG. 2 except that a plurality of dummy pins 114 are distributed in an arc. It can be understood that the multiple virtual pins 114 can also be distributed in other shapes, and it is only necessary to ensure that the driving chip 11 can be flatly bound to the display panel 100.
  • FIG. 5 is a schematic structural diagram of a display panel according to a third embodiment of the application.
  • the display panel 100 shown in FIG. 5 is basically similar to the display panel 100 shown in FIG. 2, except that a plurality of output pins 113, the first input pin group 111 and the second input pin group 112 are arranged side by side on the driving chip. 11 is close to one side of the display area 100a, and a plurality of output pins 113 are located between the first input pin group 111 and the second input pin group 112, and a plurality of dummy pins 114 are located on the driving chip 11 away from the display area 100a One side.
  • the first bonding pad 141 (for example, the first sub-bonding pad 1411) near the first input pin 1111 and the first input pin 1111 near the first bonding pad 141 are electrically connected by a first wire 161 , Wherein one end of the first wire 161 is connected to the end of the first input pin 1111 close to the first bonding pad 141 and far away from the display area 100a; and the first bonding pad 141 (for example, The sixth sub-bonding pad 1416) is electrically connected to the first input pin 1111 far away from the first bonding pad 141 through a second wire 162, wherein one end of the second wire 162 is connected to the first input pin 1111 far away from the first bonding pad.
  • the first input pin 1111 of 141 is connected to one end close to the display area 100a.
  • the length of the first wire 161 is less than the length of the second wire 162.
  • FIG. 6 it is a schematic diagram of the structure of the display panel according to the fourth embodiment of the application.
  • the display panel shown in FIG. 6 is basically similar to the display panel shown in FIG. 5, except that the first bonding pad 141 (for example, the first sub bonding pad 1411) close to the first input pin 1111 is different from the The first input pin 1111 of a bonding pad 141 is electrically connected through a first wire 161, and is far away from the first bonding pad 141 (for example, the sixth sub bonding pad 1416) of the first input pin 1111 and close to The first input pin 1111 of the first bonding pad 141 is electrically connected through the second wire 162, so that the lengths of the first wire 161 and the second wire 162 are approximately the same, so that the first wire 161 and the second wire The impedance of the wire 162 is more uniform.
  • part of the wire (for example, the first wire 161) connecting the first input pin 1111 and the first bonding pad 141 and the first input pin 1111 are far away from the display
  • One end of the area 100a is connected
  • part of the wire (for example, the second wire 162) connecting the first input pin 1111 and the first bonding pad 141 is connected to the end of the first input pin 1111 close to the display area 100a, and the driver chip 11
  • the side far away from the display area 100a (the side of the driving chip 11 provided with the dummy pins 114) has sufficient wiring space, which is matched with "at least part of the first bonding pads 141 of the plurality of first bonding pads 141
  • the height increases from the direction close to the driver chip 11 to the direction away from the driver chip 11", so that the wire (for example, the first wire 161) connecting the first bonding pad 141 close to the driver chip 11 and the first input pin 1111 is in the driver chip 11
  • the wires connecting the second input pin 1121 and the second bonding pad 142 can be further prevented from being short-circuited with each other.
  • part of the space occupied by the wires connecting the second input pin 1121 and the second bonding pad 142 and the space occupied by the wires connecting the first input pin 1111 and the first bonding pad 141 are bound to the driving chip 11
  • the space occupied by the predetermined use overlaps, so that the overall space occupied by the wires outside the space occupied by the driving chip 11 is reduced.
  • FIG. 7 is a schematic structural diagram of a display panel according to a fifth embodiment of the application.
  • the display panel 100 shown in FIG. 7 is basically similar to the display panel 100 shown in FIG. 2, except that the multiple output pins 113 are located in the middle of the side of the driving chip 11 close to the display area 100a, and the multiple output pins 113 is arranged on the opposite side of the first input pin group 111 and the second input pin group 112, and a plurality of dummy pins 114 are arranged side by side with the first input pin group 111 and the second input pin group 112 on the driving chip 11 A side far from the display area 100a, and a plurality of dummy pins 114 are located between the first input pin group 111 and the second input pin group 112.
  • FIG. 8 is a schematic structural diagram of a display panel according to a sixth embodiment of the application.
  • the display panel 100 shown in FIG. 8 is basically similar to the display panel 100 shown in FIG. 7, except that some dummy pins 114 are arranged side by side with the first input pin group 111 and the second input pin group 112 in the driving chip 11.
  • the chip 11 is close to one side of the display area 100a, and the virtual pins 114 are located on both sides of the multiple output pins 113.
  • the driving chip shown in FIG. 8 can be more evenly bound to On the display panel.
  • the application also provides a driving chip.
  • the driving chip includes a plurality of input pins, the plurality of input pins include a first input pin group and a second input pin group, and the first input pin group and the second input pin group are arranged at intervals. So that when the driver chip is bound to the display panel, the first input pin group and the second input pin group are respectively close to the corresponding bonding pad, so that the distance from the first input pin to the corresponding bonding pad is changed.
  • the distance between the second input pin and the corresponding bonding pad becomes closer, so that the length of the wire connecting the first input pin and the corresponding bonding pad and the wire connecting the second input pin and the corresponding bonding pad If it becomes shorter, the impedance of the wire becomes smaller, and the electrical signal input to the drive chip through the wire is normal, so that the display panel can display normally.
  • the first input pin group 111 and the second input pin group 112 are located on the same side of the driving chip 11 and arranged side by side.
  • the driver chip 11 also includes a plurality of output pins 113, the plurality of output pins 113 are arranged side by side with the first input pin group 111 and the second input pin group 112, and the plurality of output pins 113 are located in the first input pin group. 111 and the second input pin group 112.
  • the driver chip 11 also includes a plurality of output pins 113, and the plurality of output pins 113 are arranged on opposite sides of the first input pin 1111 and the second input pin 1121, and the plurality of output pins 113 is located in the middle position on the side of the driving chip 11.
  • the driver chip 11 further includes a plurality of dummy pins 114, the plurality of dummy pins 114 are arranged side by side with the first input pin group 111 and the second input pin group 112, and the plurality of dummy pins 114 are located at the first input pin group 111 and the second input pin group 112. Between an input pin group 111 and the second input pin group 112.
  • the driver chip 11 also includes a plurality of dummy pins 114, and the plurality of dummy pins 114 are arranged on the opposite side of the first input pin 1111 and the second input pin 1121 .

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Abstract

一种驱动芯片（11）及显示面板（100），显示面板（100）包括驱动芯片（11）以及设置于驱动芯片（11）相对两侧的多个第一绑定焊盘（141）以及多个第二绑定焊盘（142），驱动芯片（11）包括第一输入引脚组（111）和第二输入引脚组（112），第一输入引脚组（111）和第二输入引脚组（112）之间具有间距，第一输入引脚组（111）靠近多个第一绑定焊盘（141），第二输入引脚组（112）靠近多个第二绑定焊盘（142）。

Description

驱动芯片及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种驱动芯片以及显示面板。
 背景技术
如图1所示，传统技术中通过将驱动芯片10绑定于显示面板100的玻璃基板上，柔性印刷电路板20设置于驱动芯片10的两侧以使显示面板100实现窄边框。然而，由于柔性印刷电路板20绑定于驱动芯片10的两侧会导致电性连接柔性印刷电路板20和驱动芯片10的导线太长，导线太长导致阻抗太大而可能造成显示面板不能正常显示。
因此，有必要提出一种技术方案以解决导线太长使得阻抗太大而造成显示面板不能正常显示的问题。
 技术问题
本申请的目的在于提供一种驱动芯片及显示面板，该显示面板的绑定焊盘与驱动芯片上的输入引脚的距离小，使得两者之间的连接导线的阻抗减小，以使显示面板正常显示。
 技术解决方案
一种显示面板，所述显示面板包括显示区以及位于所述显示区外的非显示区，所述非显示区设置有驱动芯片以及设置于所述驱动芯片相对两侧的多个第一绑定焊盘以及多个第二绑定焊盘，所述驱动芯片包括多个输入引脚，多个所述输入引脚包括第一输入引脚组以及第二输入引脚组，所述第一输入引脚组靠近所述第一绑定焊盘设置，所述第二输入引脚组靠近所述第二绑定焊盘设置，且所述第一输入引脚组以及第二输入引脚组之间具有间距。
在上述显示面板中，每个所述第一输入引脚与每个所述第一绑定焊盘之间、每个所述第二输入引脚与每个所述第二绑定焊盘之间通过导线电性连接。
在上述显示面板中，所述第一输入引脚组和所述第二输入引脚组并排地设置于所述驱动芯片的同一侧。
在上述显示面板中，所述驱动芯片还包括多个输出引脚。
在上述显示面板中，多个所述输出引脚与所述第一输入引脚组和所述第二输入引脚组并排设置且位于所述第一输入引脚组和所述第二输入引脚组的之间。
在上述显示面板中，多个所述输出引脚设置于所述第一输入引脚组和所述第二输入引脚组的对侧。
在上述显示面板中，所述驱动芯片还包括多个虚拟引脚。
在上述显示面板中，多个所述输出引脚与所述第一输入引脚组以及所述第二输入引脚组并排设置于所述驱动芯片远离所述显示区的一侧，且多个所述输出引脚位于所述第一输入引脚组和所述第二输入引脚组之间，多个所述虚拟引脚位于驱动芯片靠近所述显示区的一侧。
在上述显示面板中，靠近所述第一输入引脚的所述第一绑定焊盘与靠近所述第一绑定焊盘的所述第一输入引脚通过第一导线电性连接，远离所述第一输入引脚的所述第一绑定焊盘与远离所述第一绑定焊盘的所述第一输入引脚通过第二导线电性连接。
在上述显示面板中，多个所述输出引脚与所述第一输入引脚组以及所述第二输入引脚组并排设置于所述驱动芯片靠近所述显示区的一侧，且多个所述输出引脚位于所述第一输入引脚组和所述第二输入引脚组之间，多个所述虚拟引脚位于所述驱动芯片远离所述显示区的一侧。
在上述显示面板中，靠近所述第一输入引脚的所述第一绑定焊盘与远离所述第一绑定焊盘的所述第一输入引脚通过第一导线电性连接，远离所述第一输入引脚的所述第一绑定焊盘与靠近所述第一绑定焊盘的所述第一输入引脚通过第二导线电性连接。
在上述显示面板中，多个所述输出引脚位于所述驱动芯片靠近所述显示区的一侧，多个所述虚拟引脚与所述第一输入引脚组以及所述第二输入引脚组并排设置于所述驱动芯片远离所述显示区的一侧，且多个所述虚拟引脚位于所述第一输入引脚组和所述第二输入引脚组之间。
在上述显示面板中，多个所述第一绑定焊盘的至少部分所述第一绑定焊盘的高度以及多个所述第二绑定焊盘的至少部分所述第二绑定焊盘的高度从靠近所述驱动芯片至远离所述驱动芯片的方向递增。
在上述显示面板中，所述至少部分所述第一绑定焊盘为第一绑定焊盘组，所述至少部分所述第二绑定焊盘为第三绑定焊盘组，所述第一绑定焊盘组的第一绑定焊盘连续或不连续排列地设置，所述第三绑定焊盘组的第二绑定焊盘连续或不连续排列地设置。
一种驱动芯片，所述驱动芯片包括多个输入引脚，多个所述输入引脚包括第一输入引脚组和第二输入引脚组，所述第一输入引脚组与所述第二输入引脚组间隔设置。
在上述驱动芯片中，所述第一输入引脚组和所述第二输入引脚组位于所述驱动芯片的同一侧且并排设置。
在上述驱动芯片中，所述驱动芯片还包括多个输出引脚，多个所述输出引脚与所述第一输入引脚组以及所述第二输入引脚组并排设置且多个所述输出引脚位于所述第一输入引脚组和所述第二输入引脚组之间。
在上述驱动芯片中，所述驱动芯片还包括多个输出引脚，多个所述输出引脚设置于所述第一输入引脚和所述第二输入引脚的对侧。
在上述驱动芯片中，所述驱动芯片还包括多个虚拟引脚，多个所述虚拟引脚与所述第一输入引脚组以及所述第二输入引脚组并排设置且多个所述虚拟引脚位于所述第一输入引脚组以及所述第二输入引脚组之间。
在上述驱动芯片中，所述驱动芯片还包括多个虚拟引脚，多个所述虚拟引脚设置于所述第一输入引脚和所述第二输入引脚的对侧。
 有益效果
本申请提供一种驱动芯片及显示面板，显示面板包括驱动芯片以及设置于驱动芯片相对两侧的多个第一绑定焊盘以及多个第二绑定焊盘，驱动芯片包括多个输入引脚，多个输入引脚包括第一输入引脚组和第二输入引脚组，第一输入引脚组和第二输入引脚组之间具有间距，第一输入引脚组靠近多个第一绑定焊盘，第二输入引脚组靠近多个第二绑定焊盘，以使得第一输入引脚与第一绑定焊盘之间、第二输入引脚与第二绑定焊盘之间的距离减小，从而使得电性连接第一输入引脚与第一绑定焊盘以及电性连接第二输入引脚与第二绑定焊盘的导线变短，导线的阻抗变小，使得驱动芯片正常输入电信号，从而使得显示面板正常显示。
 附图说明
图1为传统技术中驱动芯片以及柔性印刷电路板绑定于显示面板的示意图；
图2为本申请第一实施例显示面板的结构示意图；
图3A为图2所示显示面板中多个第一绑定焊盘的第一种示意图；
图3B为图2所示显示面板中多个第一绑定焊盘的第二种示意图；
图3C为图2所示显示面板中多个第一绑定焊盘的第三种示意图；
图 3D为图2所示显示面板中多个第一绑定焊盘的第四种示意图；
图 3E为图2所示显示面板中多个第一绑定焊盘的第五种示意图；
图4为本申请第二实施例显示面板的结构示意图；
图5为本申请第三实施例显示面板的结构示意图；
图6为本申请第四实施例显示面板的结构示意图；
图7为本申请第五实施例显示面板的结构示意图；
图8为本申请第六实施例显示面板的结构示意图。
附图标注如下：
100显示面板；100a 显示区； 100b非显示区；10，11驱动芯片；111第一输入引脚组；112第二输入引脚组；1111第一输入引脚； 1121第二输入引脚；113输出引脚；114虚拟引脚；141第一绑定焊盘；142第二绑定焊盘；141a第一绑定焊盘组；141b第二绑定焊盘组；142a第三绑定焊盘组；142b第四绑定焊盘组；1411第一子绑定焊盘；1412第二子绑定焊盘；1413第三子绑定焊盘；1414第四子绑定焊盘；1415第五子绑定焊盘；1416第六子绑定焊盘；161第一导线；162第二导线；18扇形走线； 20柔性印刷电路板。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图2，其为本申请第一实施例显示面板的结构示意图。显示面板100为液晶显示面板或有机发光二极管显示面板。显示面板100具有显示区100a以及非显示区100b，非显示区100b位于显示区100a外。显示区100a用于显示图像。非显示区100b设置有驱动芯片11、多个第一绑定焊盘141以及多个第二绑定焊盘142。
驱动芯片11位于显示面板100的非显示区100b一端的中间位置。驱动芯片11包括多个输入引脚、多个输出引脚113以及多个虚拟引脚114，多个输入引脚包括第一输入引脚组111以及第二输入引脚组112。
第一输入引脚组111和第二输入引脚组112均用于向驱动芯片11输入电信号。第一输入引脚组111包括多个第一输入引脚1111，第二输入引脚组112包括多个第二输入引脚1121。第一输入引脚组111和第二输入引脚组112之间具有间距，第一输入引脚组111靠近多个第一绑定焊盘141，第二输入引脚组112靠近多个第二绑定焊盘142，即第一输入引脚1111集中设置于驱动芯片11靠近第一绑定焊盘141的一侧，第二输入引脚1121集中设置于驱动芯片11靠近第二绑定焊盘142的一侧。第一输入引脚组111和第二输入引脚组112间隔地设置在驱动芯片11的两端部，以使得第一输入引脚组111中的多个第一输入引脚1111至多个第一绑定焊盘141之间的距离变近，第二输入引脚组112中的多个第二输入引脚1121至多个第二绑定焊盘142之间的距离变近。相对于传统技术，本申请第一输入引脚组111和第二输入引脚组112分别至第一绑定焊盘141和第二绑定焊盘142的距离更近，使得连接第一输入引脚1111和第一绑定焊盘141的导线以及连接第二输入引脚1121和第二绑定焊盘142的导线的长度更短，从而使导线的阻抗更小，保证驱动芯片11能正常输入电信号，从而使得显示面板正常显示。具体地，本申请通过将第一输入引脚组111和第二输入引脚组112分别设置在靠近第一绑定焊盘141和第二绑定焊盘142的一侧，从而减小设置在远离驱动芯片11一侧的绑定焊盘与驱动芯片11之间连接导线的长度，从而减小导线阻抗，使显示面板正常显示画面。
第一输入引脚组111和第二输入引脚组112并排地设置于驱动芯片11的同一侧。多个输出引脚113与第一输入引脚组111和第二输入引脚组112并排设置且位于第一输入引脚组111和第二输入引脚组112的之间。具体地，多个输出引脚113与第一输入引脚组111以及第二输入引脚组112并排设置于驱动芯片11远离显示区100a的一侧，且多个输出引脚113位于第一输入引脚组111和第二输入引脚组112之间，多个输出引脚113也位于驱动芯片11远离显示区100a的中间位置。多个第一输入引脚1111并排且等间隔地设置，多个第二输入引脚1121并排且等间隔地设置。多个输出引脚113并排且等间隔地设置。可以理解的是，第一输入引脚组111和第二输入引脚组112也可以交错地设置，只要多个第一输入引脚1111至多个第一绑定焊盘141的距离和多个第二输入引脚1121至多个第二绑定焊盘142的距离变近即可。
需要说明的是，本申请驱动芯片的尺寸相对于传统驱动芯片基本无变化，为了使多个输出引脚113、第一输入引脚组111以及第二输入引脚组112并排设置，且多个输出引脚113设置于第一输入引脚组111和第二输入引脚组112之间。相对于现有技术，本申请对现有的输入引脚进行筛选，对于舍弃后不会影响驱动芯片电信号输入的输入引脚舍弃，例如，具有相同功能的输入引脚进行部分舍弃，以使得输入引脚的数目变少，再将剩余的输入引脚分为第一输入引脚组111和第二输入引脚组112，再使得输出引脚113设置于第一输入引脚组111和第二输入引脚组112之间。本申请中第一输入引脚组111和第二输入引脚组112之间并排设置时两者之间的的间距可以设置多个引脚，包括传统技术中的全部输出引脚或多个虚拟引脚。
多个虚拟引脚114用于使驱动芯片11平整地绑定于显示面板100上。多个虚拟引脚114位于驱动芯片11靠近显示区100a的一侧。具体地，多个虚拟引脚114如图2所示呈直线并排设置于驱动芯片11靠近显示区100a的一侧。多个虚拟引脚114未接入电信号。多个虚拟引脚114垂直于驱动芯片11厚度方向的厚度等于第一输入引脚1111、第二输入引脚1121以及输出引脚113垂直于驱动芯片11厚度方向的厚度，第一输入引脚1111、第二输入引脚1121以及输出引脚113垂直于驱动芯片11厚度方向的厚度均相等以使得驱动芯片11能平整地绑定在显示面板100的玻璃基板上。
多个第一绑定焊盘141和多个第二绑定焊盘142分别设置于驱动芯片11相对的两侧。多个第一绑定焊盘141位于驱动芯片11所在侧与显示区100a位于驱动芯片11所在侧相邻，多个第二绑定焊盘142位于驱动芯片11所在侧与显示区100a位于驱动芯片11所在侧相邻。每个第一输入引脚1111与每个第一绑定焊盘141之间、每个第二输入引脚1121与每个第二绑定焊盘142之间通过导线连接。多个第一绑定焊盘141的至少部分第一绑定焊盘141的高度以及多个第二绑定焊盘142的至少部分第二绑定焊盘142的高度从靠近驱动芯片11至远离驱动芯片11的方向递增，以解决传统技术中绑定焊盘高度一致时容易导致靠近驱动芯片的空间较小，靠近驱动芯片的空间较小使得靠近驱动芯片一侧的导线过于拥挤而可能导致短路，引起显示异常的问题。
如图2所示，多个第一绑定焊盘141的至少部分第一绑定焊盘141为第一绑定焊盘组141a，多个第一绑定焊盘141还包括除第一绑定焊盘组141a之外的第二绑定焊盘组141b。多个第二绑定焊盘142的至少部分第二绑定焊盘142为第三绑定焊盘组142a，多个第二绑定焊盘142还包括除第三绑定焊盘组142a之外的第四绑定焊盘组142b。第一绑定焊盘组141a中的第一绑定焊盘141连续或者不连续地排列设置，第三绑定焊盘组142a中的第二绑定焊盘142连续或者不连续地排列设置。第一绑定焊盘组141a中第一绑定焊盘141的高度从靠近驱动芯片11至远离驱动芯片11的方向依序增加且连续排列设置，第一绑定焊盘组141a设置在靠近驱动芯片11的一侧，第二绑定焊盘组141b设置在远离驱动芯片11的一侧。第三绑定焊盘组142a中的第二绑定焊盘142的高度从靠近驱动芯片11至远离驱动芯片11的方向依序增加且连续排列设置，第三绑定焊盘组142a设置在靠近驱动芯片11的一侧，第四绑定焊盘组142b设置在远离驱动芯片11的一侧。
为了详细说明“多个第一绑定焊盘141的至少部分第一绑定焊盘141的高度从靠近驱动芯片11至远离驱动芯片11的方向递增”的技术方案，以下以多个第一绑定焊盘141的数目为6个进行说明，然而多个第一绑定焊盘141的数目不限于6个，从靠近驱动芯片11至远离驱动芯片11的方向，多个第一绑定焊盘141依次包括第一子绑定焊盘1411、第二子绑定焊盘1412、第三子绑定焊盘1413、第四子绑定焊盘1414、第五子绑定焊盘1415以及第六子绑定焊盘1416。
如图3A所示，其为图2所示显示面板中多个第一绑定焊盘的第一种示意图。多个第一绑定焊盘141全部为第一绑定焊盘组141a，第一绑定焊盘141的高度从靠近驱动芯片11至远离驱动芯片11依次递增，以使得靠近驱动芯片11的第一绑定焊盘141的上方用于布设导线的空间更大，避免连接第一输入引脚1111以及第一绑定焊盘141的多条导线发生短路，引起显示异常。
如图3B所示，其为图2所示显示面板中多个第一绑定焊盘的第二种示意图。多个第一绑定焊盘141包括第一绑定焊盘组141a和第二绑定焊盘组141b。第二绑定焊盘组141b位于第一绑定焊盘组141a和驱动芯片11之间。第一绑定焊盘组141a包括第四子绑定焊盘1414、第五子绑定焊盘1415以及第六子绑定焊盘1416，第二绑定焊盘组141b包括第一子绑定焊盘1411、第二子绑定焊盘1412以及第三子绑定焊盘1413。其中，第一绑定焊盘组141a中，第四子绑定焊盘1414的高度小于第五子绑定焊盘1415的高度，第五子绑定焊盘1415的高度小于第六子绑定焊盘1416的高度。为了增加导线的布线空间，第一子绑定焊盘1411的高度、第二子绑定焊盘1412的高度以及第三子绑定焊盘1413的高度小于或等于第四子绑定焊盘1414的高度。在其他多个第一绑定焊盘的实施例中，第一子绑定焊盘1411的高度、第二子绑定焊盘1412的高度以及第三子绑定焊盘1413的高度也可以大于第四子绑定焊盘1414的高度。
如图3C所示，其为图2所示显示面板中多个第一绑定焊盘的第三种示意图。多个第一绑定焊盘141包括第一绑定焊盘组141a和第二绑定焊盘组141b。第二绑定焊盘组141b位于第一绑定焊盘组141a的两侧。第一绑定焊盘组141a包括第二子绑定焊盘1412、第三子绑定焊盘1413以及第四子绑定焊盘1414，第二绑定焊盘组141b包括第一子绑定焊盘1411、第五子绑定焊盘1415以及第六子绑定焊盘1416。第一绑定焊盘组141a中，第二子绑定焊盘1412的高度小于第三子绑定焊盘1413的高度，第三子绑定焊盘1413的高度小于第四子绑定焊盘1414的高度。为了增大导线的布线空间，第一子绑定焊盘1411的高度可以小于等于第二子绑定焊盘1412的高度，第五子绑定焊盘1415的高度以及第六子绑定焊盘1416的高度可以大于等于第四子绑定焊盘1414的高度。可以理解的是，第五子绑定焊盘1415和第六子绑定焊盘1416的高度也可以小于第四子绑定焊盘1414的高度。
如图3D所示，其为图2所示显示面板中多个第一绑定焊盘的第四种示意图。多个第一绑定焊盘141包括第一绑定焊盘组141a和第二绑定焊盘组141b。第一绑定焊盘组141a位于第二绑定焊盘组141b和驱动芯片11之间。第一绑定焊盘组141a包括第一子绑定焊盘1411、第二子绑定焊盘1412以及第三子绑定焊盘1413，第二绑定焊盘组141b包括第四子绑定焊盘1414、第五子绑定焊盘1415以及第六子绑定焊盘1416。第一子绑定焊盘1411的高度小于第二子绑定焊盘1412的高度，第二子绑定焊盘1412的高度小于第三子绑定焊盘1413的高度。第四子绑定焊盘1414的高度、第五子绑定焊盘1415的高度以及第六子绑定焊盘1416的高度可以大于等于第三子绑定焊盘1413的高度，也可以小于第三子绑定焊盘1413的高度。
如图3E所示，其为图2所示显示面板中多个第一绑定焊盘的第五种示意图。多个第一绑定焊盘141包括第一绑定焊盘组141a和第二绑定焊盘组141b。第一绑定焊盘组141a可包括任意两个间隔排布的第一绑定焊盘141。具体地，第一绑定焊盘组141a包括第一子绑定焊盘1411、第三子绑定焊盘1413以及第五子绑定焊盘1415，第二绑定焊盘组141b包括第二子绑定焊盘1412、第四子绑定焊盘1414以及第六子绑定焊盘1416。第一子绑定焊盘1411的高度小于第三子绑定焊盘1413的高度，第三子绑定焊盘1413的高度小于第五子绑定焊盘1415的高度。第二子绑定焊盘1412的高度可以在第一子绑定焊盘1411的高度和第三子绑定焊盘1413的高度之间，也可以等于第一子绑定焊盘1411和第三子绑定焊盘1413中任意一者的高度。第四子绑定焊盘1414的高度可以在第三子绑定焊盘1413的高度和第五子绑定焊盘1415的高度之间，也可以等于第三子绑定焊盘1413的高度和第五子绑定焊盘1415的高度中的任意一者。第六子绑定焊盘1416的高度可以大于等于第五子绑定焊盘1415的高度，也可以小于第五子绑定焊盘1415的高度。在多个第一绑定焊盘的其他示意图中，第一子绑定焊1411和第三子绑定焊盘1413之间的属于第二绑定焊盘组141b的第一绑定焊盘141的数目不限于一个，也可以为多个，第三子绑定焊盘1413和第五子绑定焊盘1415之间属于第二绑定焊盘组141b的第一绑定焊盘141的数目不限于一个，也可以为多个。
多个第二绑定焊盘142的布设方式与多个第一绑定焊盘141的布设方式相同，此处不作详述。
具体地，至少部分多个第一绑定焊盘141的高度从靠近驱动芯片11至远离驱动芯片11依次递增，至少部分多个第二绑定焊盘142的高度从靠近驱动芯片11至远离驱动芯片11依次递增，从而进一步地避免连接第一输入引脚1111以及第一绑定焊盘141的多条导线以及连接第二输入引脚1121以及第二绑定焊盘142的多条导线相互之间发生短路，引起显示异常。
多个第一绑定焊盘141等间隔地并排设置且任意两个第一绑定焊盘141的面积相等，多个第二绑定焊盘142等间隔地并排设置且任意两个第二绑定焊盘142的面积相等。多个第一绑定焊盘141和多个第二绑定焊盘142的形状为规则图形或不规则图形，规则图形包括矩形以及梯形等。
进一步地，任意两个相邻的第一绑定焊盘141的高度差相等，任意两个相邻的第二绑定焊盘142的高度差相等。
靠近第一输入引脚1111的第一绑定焊盘141（例如第一子绑定焊盘1411）与靠近第一绑定焊盘141的第一输入引脚1111通过第一导线161电性连接，远离第一输入引脚1111的第一绑定焊盘141（例如第六子绑定焊盘1416）与远离第一绑定焊盘141的第一输入引脚1111通过第二导线162电性连接，第一导线161的长度小于第二导线162的长度。由于第一导线161的长度短而阻抗小，靠近第一输入引脚1111的第一绑定焊盘141用于向靠近第一绑定焊盘141的第一输入引脚1111输入要求导线阻值小的电信号，远离第一输入引脚1111的第一绑定焊盘141用于向远离第一绑定焊盘141的第一输入引脚1111输入导线阻值要求不高的电信号。
需要说明的是，从显示区100a延伸至驱动芯片11的扇形走线18可利用驱动芯片11的上侧空间（图2中虚拟引脚114位于驱动芯片11所在侧的空间），即扇形走线18占用的部分空间与驱动芯片11占用的空间重合，从而缩短了显示区100a与驱动芯片11之间的间距，从而使得本申请实施例显示面板100的下边框变窄。
请参阅图4，其为本申请第二实施例显示面板的结构示意图。图4所示显示面板100与图2所示显示面板基板相似，不同之处在于，多个虚拟引脚114呈弧线分布。可以理解的是，多个虚拟引脚114也可以成其他形状分布，只需要保证驱动芯片11能平整地绑定于显示面板100上即可。
请参阅图5，其为本申请第三实施例显示面板的结构示意图。图5所示显示面板100与图2所示显示面板100基本相似，不同之处在于，多个输出引脚113与第一输入引脚组111以及第二输入引脚组112并排设置于驱动芯片11靠近显示区100a的一侧，且多个输出引脚113位于第一输入引脚组111和第二输入引脚组112之间，多个虚拟引脚114位于驱动芯片11远离显示区100a的一侧。
靠近第一输入引脚1111的第一绑定焊盘141（例如第一子绑定焊盘1411）与靠近第一绑定焊盘141的第一输入引脚1111通过第一导线161电性连接，其中，第一导线161的一端与靠近第一绑定焊盘141的第一输入引脚1111远离显示区100a的一端连接；远离第一输入引脚1111的第一绑定焊盘141（例如第六子绑定焊盘1416）与远离第一绑定焊盘141的第一输入引脚1111通过第二导线162电性连接，其中，第二导线162的一端与远离第一绑定焊盘141的第一输入引脚1111靠近显示区100a的一端连接。第一导线161的长度小于第二导线162的长度。
如图6所示，其为本申请第四实施例显示面板的结构示意图。图6所示显示面板与图5所示显示面板基本相似，不同之处在于，靠近第一输入引脚1111的第一绑定焊盘141（例如第一子绑定焊盘1411）与远离第一绑定焊盘141的第一输入引脚1111通过第一导线161电性连接，远离第一输入引脚1111的第一绑定焊盘141（例如第六子绑定焊盘1416）与靠近第一绑定焊盘141的第一输入引脚1111通过第二导线162电性连接，从而使得第一导线161和第二导线162的长度趋近于相同，从而使得第一导线161和第二导线162的阻抗更加均一化。
需要说明的是，图5和图6所示显示面板中，部分连接第一输入引脚1111和第一绑定焊盘141的导线（例如第一导线161）与第一输入引脚1111远离显示区100a的一端连接，部分连接第一输入引脚1111和第一绑定焊盘141的导线（例如第二导线162）与第一输入引脚1111靠近显示区100a的一端连接，而在驱动芯片11远离显示区100a的一侧（驱动芯片11设置有虚拟引脚114的一侧）具有充足的布线空间，配合“多个第一绑定焊盘141的至少部分第一绑定焊盘141的高度从靠近驱动芯片11至远离驱动芯片11的方向递增”，使得连接靠近驱动芯片11的第一绑定焊盘141和第一输入引脚1111的导线（例如第一导线161）在驱动芯片11远离显示区100a一侧（驱动芯片11设置有虚拟引脚114的一侧）具有更充足的布线空间而不会相互之间发生短路，且部分连接第一输入引脚1111和第一绑定焊盘141的导线（例如第二导线162）与第一输入引脚1111靠近显示区100a的一端连接使得导线不会集中于一个区域，更进一步地避免导线之间发生短路。同理，也能进一步地避免连接第二输入引脚1121以及第二绑定焊盘142的导线相互之间发生短路。此外，部分连接第二输入引脚1121以及第二绑定焊盘142的导线占用的空间以及部分连接第一输入引脚1111以及第一绑定焊盘141的导线占用的空间与驱动芯片11绑定用占用的空间重合，使得导线在驱动芯片11占用空间之外所占用的整体空间减小。
请参阅图7，其为本申请第五实施例显示面板的结构示意图。图7所示显示面板100与图2所示显示面板100基本相似，不同之处在于，多个输出引脚113位于驱动芯片11靠近显示区100a的一侧的中间位置，且多个输出引脚113设置于第一输入引脚组111和第二输入引脚组112的对侧，多个虚拟引脚114与第一输入引脚组111以及第二输入引脚组112并排设置于驱动芯片11远离显示区100a的一侧，且多个虚拟引脚114位于第一输入引脚组111和第二输入引脚组112之间。
请参阅图8，其为本申请第六实施例显示面板的结构示意图。图8所示显示面板100与图7所示显示面板100基本相似，不同之处在于，部分虚拟引脚114与第一输入引脚组111以及第二输入引脚组112并排设置于驱动芯片11远离显示区100a的一侧，且该部分虚拟引脚114位于第一输入引脚组111和第二输入引脚组112之间；部分虚拟引脚114与多个输出引脚113并排设置于驱动芯片11靠近显示区100a的一侧，且该部分虚拟引脚114位于多个输出引脚113的两侧，相对于图7所示驱动芯片，图8所示驱动芯片能更平整地绑定于显示面板上。
本申请还提供一种驱动芯片。该驱动芯片包括多个输入引脚，多个输入引脚包括第一输入引脚组和第二输入引脚组，第一输入引脚组与第二输入引脚组间隔设置。以使驱动芯片绑定于显示面板上时，第一输入引脚组和第二输入引脚组分别靠近对应的绑定焊盘，从而使得第一输入引脚至对应绑定焊盘的距离变近，第二输入引脚至对应绑定焊盘的距离变近，使得连接第一输入引脚和对应绑定焊盘的导线以及连接第二输入引脚和对应绑定焊盘的导线的长度变短，导线阻抗变小，通过导线输入至驱动芯片的电信号正常，从而使显示面板正常显示。
请参阅图2、图4、图5以及图6，第一输入引脚组111和第二输入引脚组112位于驱动芯片11的同一侧且并排设置。驱动芯片11还包括多个输出引脚113，多个输出引脚113与第一输入引脚组111以及第二输入引脚组112并排设置且多个输出引脚113位于第一输入引脚组111和第二输入引脚组112之间。
请参阅图7和图8，驱动芯片11还包括多个输出引脚113，多个输出引脚113设置于第一输入引脚1111和第二输入引脚1121的对侧，多个输出引脚113位于驱动芯片11一侧的中间位置。
请参阅图7，驱动芯片11还包括多个虚拟引脚114，多个虚拟引脚114与第一输入引脚组111以及第二输入引脚组112并排设置且多个虚拟引脚114位于第一输入引脚组111以及所述第二输入引脚组112之间。
请参阅图2、图4、图5以及图6，驱动芯片11还包括多个虚拟引脚114，多个虚拟引脚114设置于第一输入引脚1111和第二输入引脚1121的对侧。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括显示区以及位于所述显示区外的非显示区，所述非显示区设置有驱动芯片以及设置于所述驱动芯片相对两侧的多个第一绑定焊盘以及多个第二绑定焊盘，所述驱动芯片包括多个输入引脚，多个所述输入引脚包括第一输入引脚组以及第二输入引脚组，所述第一输入引脚组靠近所述第一绑定焊盘设置，所述第二输入引脚组靠近所述第二绑定焊盘设置，且所述第一输入引脚组以及第二输入引脚组之间具有间距。
  2. 根据权利要求1所述的显示面板，其中，每个所述第一输入引脚与每个所述第一绑定焊盘之间、每个所述第二输入引脚与每个所述第二绑定焊盘之间通过导线电性连接。
  3. 根据权利要求1所述的显示面板，其中，所述第一输入引脚组和所述第二输入引脚组并排地设置于所述驱动芯片的同一侧。
  4. 根据权利要求3所述的显示面板，其中，所述驱动芯片还包括多个输出引脚。
  5. 根据权利要求4所述的显示面板，其中，多个所述输出引脚与所述第一输入引脚组和所述第二输入引脚组并排设置且位于所述第一输入引脚组和所述第二输入引脚组的之间。
  6. 根据权利要求4所述的显示面板，其中，多个所述输出引脚设置于所述第一输入引脚组和所述第二输入引脚组的对侧。
  7. 根据权利要求4所述的显示面板，其中，所述驱动芯片还包括多个虚拟引脚。
  8. 根据权利要求7所述的显示面板，其中，多个所述输出引脚与所述第一输入引脚组以及所述第二输入引脚组并排设置于所述驱动芯片远离所述显示区的一侧，且多个所述输出引脚位于所述第一输入引脚组和所述第二输入引脚组之间，多个所述虚拟引脚位于驱动芯片靠近所述显示区的一侧。
  9. 根据权利要求8所述的显示面板，其中，靠近所述第一输入引脚的所述第一绑定焊盘与靠近所述第一绑定焊盘的所述第一输入引脚通过第一导线电性连接，远离所述第一输入引脚的所述第一绑定焊盘与远离所述第一绑定焊盘的所述第一输入引脚通过第二导线电性连接。
  10. 根据权利要求7所述的显示面板，其中，多个所述输出引脚与所述第一输入引脚组以及所述第二输入引脚组并排设置于所述驱动芯片靠近所述显示区的一侧，且多个所述输出引脚位于所述第一输入引脚组和所述第二输入引脚组之间，多个所述虚拟引脚位于所述驱动芯片远离所述显示区的一侧。
  11. 根据权利要求10所述的显示面板，其中，靠近所述第一输入引脚的所述第一绑定焊盘与远离所述第一绑定焊盘的所述第一输入引脚通过第一导线电性连接，远离所述第一输入引脚的所述第一绑定焊盘与靠近所述第一绑定焊盘的所述第一输入引脚通过第二导线电性连接。
  12. 根据权利要求7所述的显示面板，其中，多个所述输出引脚位于所述驱动芯片靠近所述显示区的一侧，多个所述虚拟引脚与所述第一输入引脚组以及所述第二输入引脚组并排设置于所述驱动芯片远离所述显示区的一侧，且多个所述虚拟引脚位于所述第一输入引脚组和所述第二输入引脚组之间。
  13. 根据权利要求2所述的显示面板，其中，多个所述第一绑定焊盘的至少部分所述第一绑定焊盘的高度以及多个所述第二绑定焊盘的至少部分所述第二绑定焊盘的高度从靠近所述驱动芯片至远离所述驱动芯片的方向递增。
  14. 根据权利要求13所述的显示面板，其中，所述至少部分所述第一绑定焊盘为第一绑定焊盘组，所述至少部分所述第二绑定焊盘为第三绑定焊盘组，所述第一绑定焊盘组的第一绑定焊盘连续或不连续排列地设置，所述第三绑定焊盘组的第二绑定焊盘连续或不连续排列地设置。
  15. 一种驱动芯片，其中，所述驱动芯片包括多个输入引脚，多个所述输入引脚包括第一输入引脚组和第二输入引脚组，所述第一输入引脚组与所述第二输入引脚组间隔设置。
  16. 根据权利要求15所述的驱动芯片，其中，所述第一输入引脚组和所述第二输入引脚组位于所述驱动芯片的同一侧且并排设置。
  17. 根据权利要求16所述的驱动芯片，其中，所述驱动芯片还包括多个输出引脚，多个所述输出引脚与所述第一输入引脚组以及所述第二输入引脚组并排设置且多个所述输出引脚位于所述第一输入引脚组和所述第二输入引脚组之间。
  18. 根据权利要求16所述的驱动芯片，其中，所述驱动芯片还包括多个输出引脚，多个所述输出引脚设置于所述第一输入引脚和所述第二输入引脚的对侧。
  19. 根据权利要求16所述的驱动芯片，其中，所述驱动芯片还包括多个虚拟引脚，多个所述虚拟引脚与所述第一输入引脚组以及所述第二输入引脚组并排设置且多个所述虚拟引脚位于所述第一输入引脚组以及所述第二输入引脚组之间。
  20. 根据权利要求16所述的驱动芯片，其中，所述驱动芯片还包括多个虚拟引脚，多个所述虚拟引脚设置于所述第一输入引脚和所述第二输入引脚的对侧。
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