WO2021093053A1 - 覆晶薄膜及显示装置 - Google Patents

覆晶薄膜及显示装置 Download PDF

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Publication number
WO2021093053A1
WO2021093053A1 PCT/CN2019/123145 CN2019123145W WO2021093053A1 WO 2021093053 A1 WO2021093053 A1 WO 2021093053A1 CN 2019123145 W CN2019123145 W CN 2019123145W WO 2021093053 A1 WO2021093053 A1 WO 2021093053A1
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WO
WIPO (PCT)
Prior art keywords
source signal
source
signal line
cross
area
Prior art date
Application number
PCT/CN2019/123145
Other languages
English (en)
French (fr)
Inventor
傅晓立
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US16/623,800 priority Critical patent/US11081441B1/en
Publication of WO2021093053A1 publication Critical patent/WO2021093053A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/1613—Constructional details or arrangements for portable computers
    • G06F1/1633—Constructional details or arrangements of portable computers not specific to the type of enclosures covered by groups G06F1/1615 - G06F1/1626
    • G06F1/1637—Details related to the display arrangement, including those related to the mounting of the display in the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

Definitions

  • This application relates to the field of display, and in particular to a flip chip film and a display device.
  • the display panel has a display area and a non-display area.
  • the non-display area is provided with a fan-out area and a binding area.
  • the fan-out wiring in the fan-out area connects the data lines of the pixels in the display area and the source conversion terminal in the binding area;
  • the specific performance is that the fan-out traces in the middle area of the fan-out area are relatively short, the fan-out traces in the areas on both sides of the fan-out area are relatively long, and the fan-out traces in the fan-out area are relatively long.
  • the cross-sectional area is the same, so the impedance of the fan-out traces on both sides is larger than that of the fan-out traces in the middle area, which makes the fan-out traces on both sides of the signal attenuate severely.
  • the visual effect is shown as a color shift.
  • the present application provides a flip-chip film and a display device to alleviate the technical problem that the different lengths of fan-out traces in the fan-out area cause different charging of pixels in different positions in the display area in the prior art.
  • the embodiment of the present application provides a flip chip film, which includes:
  • the source driving chip is arranged on the substrate and includes a source driving terminal
  • the source connecting terminals are arranged in a one-to-one correspondence with the source driving terminals;
  • the source signal line is connected to the source connection terminal and the source drive terminal;
  • the source signal line includes a plurality of first source signal lines located in the middle area and a plurality of second source signal lines located in the two side areas.
  • the first source signal lines The cross-sectional area of is smaller than the cross-sectional area of the second source signal line, and the reference plane is perpendicular to the substrate and parallel to the arrangement direction of the source connection terminals.
  • the cross-sectional areas of the multiple first source signal lines are different, and gradually increase from the middle region to the two side regions.
  • the cross-sectional areas of the plurality of first source signal lines are the same.
  • the cross-sectional areas of the multiple second source signal lines are different, and gradually increase from the middle region to the two side regions.
  • the cross-sectional areas of the plurality of second source signal lines are the same.
  • the cross-sectional area of the first source signal line remains unchanged from one end to the other end.
  • the cross-sectional area of the second source signal line gradually decreases from one end to the other end.
  • the cross section of the first source signal line is a first rectangle
  • the cross section of the second source signal line is a second rectangle
  • the area of the first rectangle is smaller than the area of the second rectangle.
  • the length of the bottom side of the first rectangle is less than the length of the bottom side of the second rectangle, and/or the width of the first rectangle is less than the width of the second rectangle .
  • the cross section of the first source signal line is a first trapezoid
  • the cross section of the second source signal line is a second trapezoid.
  • the area of the first trapezoid is smaller than the area of the second trapezoid.
  • the length of the bottom side of the first trapezoid is less than the length of the bottom side of the second trapezoid, and/or the length of the top side of the first trapezoid is less than the length of the second trapezoid
  • the length of the top side, and/or the height of the first trapezoid is smaller than the height of the second trapezoid.
  • the cross section of the first source signal line is a third trapezoid
  • the cross section of the second source signal line is a third rectangular cross section.
  • the area of the third trapezoid is smaller than the area of the third rectangle.
  • half of the sum of the length of the bottom side and the top side of the third trapezoid is less than the length of the bottom side of the third rectangle, and/or the height of the third trapezoid is less than The height of the third rectangle.
  • an embodiment of the present application also provides a display device, which includes:
  • the display panel includes a fan-out wiring and a source switching terminal.
  • the fan-out wiring includes a plurality of first fan-out wirings located in a middle area and a plurality of second fan-out wirings located in two side areas.
  • the source conversion The terminals include a first source switching terminal connected to the first fan-out wiring and a second source switching terminal connected to the second fan-out wiring, the length of the first fan-out wiring is smaller than the length of the second fan-out wiring;
  • the flip chip film includes a source signal line and a source connection terminal.
  • the source signal line includes a plurality of first source signal lines located in the middle area and a plurality of second source signal lines located in the two side areas,
  • the source connection terminal includes a first source connection terminal connected to a first source signal line and a second source connection terminal connected to a second source signal line; the first source signal line passes through the first source connection terminal.
  • the source connection terminal and the first source conversion terminal are electrically connected to the first fan-out wiring, and the second source signal line is electrically connected to the second fan through the second source connection terminal and the second source conversion terminal Run out
  • the cross-sectional area of the first source signal line is smaller than the cross-sectional area of the second source signal line, and the reference plane is perpendicular to the substrate of the chip on film and parallel to the The arrangement direction of the source connection terminals.
  • the cross-sectional areas of the multiple first source signal lines are different and gradually increase from the middle area to the two side areas.
  • the cross-sectional areas of the plurality of first source signal lines are the same.
  • the cross-sectional areas of the plurality of second source signal lines are different, and gradually increase from the middle area to the two side areas.
  • the cross-sectional areas of the plurality of second source signal lines are the same.
  • the sum of the resistance of the first source signal line and the first fan-out wiring is the same as the resistance of the second source signal line and the second fan-out wiring.
  • the sum of resistance is equal.
  • the cross-sectional area of the second source signal line gradually decreases from one end to the other end.
  • the present application provides a new flip chip film and a display device.
  • the flip chip film includes a substrate; a source drive chip arranged on the substrate and includes a source drive terminal; a source connection terminal connected to the source drive The terminals are arranged in one-to-one correspondence; a source signal line is connected to the source connection terminal and the source drive terminal; wherein, the source signal line includes a first source signal line located in the middle area and a first source signal line located in both sides of the area On the reference plane, the cross-sectional area of the first source signal line is smaller than the cross-sectional area of the second source signal line; based on this structure, the impedance of the first source signal line can be greater than The impedance of the second source signal line.
  • the first source signal line is connected to the first fan-out wiring in the middle area
  • the second source The signal line is connected to the second fan-out traces located on both sides of the area, so that the attenuation from the source driver chip to the data lines is approximately the same or even the same, so that the charging of the pixels in different positions in the display area is approximately the same or even the same, alleviating the existing
  • the technology has a technical problem that the different lengths of fan-out traces in the fan-out area lead to different charging of pixels in different positions in the display area.
  • FIG. 1 is a schematic diagram of the structure of a flip chip film provided by this application.
  • FIG. 2 is a schematic cross-sectional view of the flip chip film provided by this application.
  • FIG. 3 is a schematic diagram of the structure of the display device provided by this application.
  • the present application can alleviate this defect.
  • the flip chip film 10 provided by the embodiment of the present application includes:
  • the source driving chip 12 is arranged on the substrate 11 and includes a source driving terminal 121;
  • the source connecting terminals 13 are arranged in a one-to-one correspondence with the source driving terminals 121;
  • the source signal line 14 is connected to the source connecting terminal 13 and the source driving terminal 121;
  • the source signal line 14 includes a plurality of first source signal lines 141 located in the middle area A1 and a plurality of second source signal lines 142 located in the two side areas A2.
  • the first source signal lines 141 The cross-sectional area of a source signal line 141 is smaller than the cross-sectional area of the second source signal line 142, and the reference plane m is perpendicular to the substrate 11 and parallel to the arrangement direction 1 of the source connection terminals 13.
  • the sizes of the middle area A1 and the two side areas A2 can be set as required.
  • the middle area A1 includes three source connection terminals 13, and the two side areas A2 respectively include half of the remaining source connection terminals 13, that is, the two side areas A2 respectively include Two source connection terminals 13; in another embodiment, the middle area A1 includes one source connection terminal 13, and the two side areas A2 respectively include half of the remaining source connection terminals 13, that is, two side areas A2 includes three source connection terminals 13 respectively.
  • the number of the two-side areas A2 may be greater than two, that is, at least two two-side areas A2 are included on the same side of the middle area A1.
  • one area includes only one source connection terminal.
  • the first source signal line 141 located in the middle area A1 refers to the source signal line 14 connected to the source connection terminal 13 located in the middle area A1, and the second source signal line 14 located in the two side areas A2
  • the line 142 refers to the source signal line 14 connected to the source connection terminal 13 located in the area A2 on both sides.
  • the present embodiment provides a flip chip film, the flip chip film includes a substrate; a source driving chip is arranged on the substrate and includes a source driving terminal; a source connection terminal corresponds to the source driving terminal one-to-one Provided; a source signal line, connected to the source connection terminal and the source drive terminal; wherein the source signal line includes a first source signal line located in the middle area and a second source located in both sides of the area Signal line, on the reference plane, the cross-sectional area of the first source signal line is smaller than the cross-sectional area of the second source signal line; based on this structure, the impedance of the first source signal line can be greater than that of the second source signal line The impedance of the signal line.
  • the first source signal line is connected to the first fan-out line in the middle area
  • the second source signal line is connected to In the second fan-out traces on both sides of the area
  • the attenuation from the source driver chip to each data line is approximately the same or even the same, so that the charging of pixels in different positions in the display area is approximately the same or even the same, which alleviates the fan-out area in the prior art.
  • the different lengths of fan-out traces lead to technical problems of different pixel charging in different positions in the display area.
  • the cross-sectional area of the first source signal line 141 remains unchanged from one end to the other end.
  • the cross-sectional area of the second source signal line is gradually reduced from one end to the other end, for example, the cross-sectional area of the second source signal line is set in a manner such as a proportional reduction.
  • the cross-sectional areas of the plurality of first source signal lines are different, and gradually increase from the middle area to the two side areas.
  • the cross-sectional areas of the plurality of first source signal lines are the same.
  • the cross-sectional areas of the plurality of second source signal lines are different, and gradually increase from the middle area to the two side areas.
  • the cross-sectional areas of the plurality of second source signal lines are the same.
  • the cross section of the first source signal line 141 is a first rectangle
  • the second source signal line 142 The cross section of is a second rectangle, and the area of the first rectangle is smaller than the area of the second rectangle.
  • a source signal line with a rectangular cross section is used to reduce the design difficulty of the source signal line.
  • the length of the base of the first rectangle is less than the length of the base of the second rectangle, and/or the width of the first rectangle is less than that of the The width of the second rectangle.
  • the cross section of the first source signal line 141 is a first trapezoid
  • the second source signal line 142 The cross section of is a second trapezoid, and the area of the first trapezoid is smaller than the area of the second trapezoid.
  • the length of the bottom side of the first trapezoid is less than the length of the bottom side of the second trapezoid, and/or the length of the top side of the first trapezoid is less than The length of the top side of the second trapezoid, and/or the height of the first trapezoid is smaller than the height of the second trapezoid.
  • the cross section of the first source signal line 141 is a third trapezoid, and the second source signal line 142
  • the cross section of is a third rectangle, and the area of the third trapezoid is smaller than the area of the third rectangle.
  • the sum of half the length of the bottom side and the top side of the third trapezoid is less than the length of the bottom side of the third rectangle, and/or the third The height of the trapezoid is smaller than the height of the third rectangle.
  • the cross section of the first source signal line 141 is a first circle
  • the second source signal line is a horizontal second circle
  • the area of the first circle is smaller than the area of the second circle.
  • the display device 30 provided by the present application includes a display panel 20 and a chip on film 10 (the state shown in FIG. 3 is that the display panel 20 and the chip on film 10 are not bound Set together); where:
  • the display panel 20 includes a display area AA, a fan-out area FA, and a binding area BA, a data line 23 located in the display area AA, a fan-out wiring 21 located in the fan-out area FA, and a source switch located in the binding area BA Terminal 22.
  • the fan-out wiring 21 includes a plurality of first fan-out wirings 211 located in the middle area AA1 and at least one first side area AA2 and at least one second side located on both sides of the central area AA1.
  • the source switching terminal 22 includes a first source switching terminal connected to the first fan-out trace 211 and a second source connected to the second fan-out trace 212 Pole switching terminal, the length of the first fan-out wire 211 is less than the length of the second fan-out wire 212;
  • the flip-chip film 10 includes a source signal line 14 and a source connection terminal 13.
  • the source signal line 14 includes a plurality of first source signal lines 141 located in the middle area A1 and a plurality of first source signal lines 141 located in the two side areas A2.
  • a second source signal line 142, the source connection terminal 13 includes a first source connection terminal connected to the first source signal line 141 and a second source connection terminal connected to the second source signal line 142;
  • the first source signal line 141 is electrically connected to the first fan-out wiring 211 through a first source connection terminal 131 and a first source switching terminal 221
  • the second source signal line 142 is electrically connected to the first fan-out wiring 211 through a second source
  • the connecting terminal 132 and the second source switching terminal 222 are electrically connected to the second fan-out wiring 212;
  • the cross-sectional area of the first source signal line 141 is smaller than the cross-sectional area of the second source signal line 142, and the reference plane is perpendicular to the substrate of the chip on film and parallel to In the arrangement direction l of the source connection terminals;
  • the display panel 20 and the chip-on-chip film 10 are bonded and connected by anisotropic conductive adhesives (ACA, Anisotropic Conductive Adhesives).
  • ACA Anisotropic Conductive Adhesives
  • This embodiment provides a display device, which includes a chip-on-chip film and a display panel.
  • the first source signal line is connected to the first fan-out line
  • the second source signal line is connected to the second fan-out line
  • the source driver chip is connected to each
  • the attenuation of the data lines is approximately the same or even the same, so that the charging of the pixels in different positions in the display area is approximately the same or the same, which alleviates the prior art technology that the different lengths of fan-out traces in the fan-out area lead to different charging of the pixels in different positions in the display area. problem.
  • the data lines, the fan-out wiring, the source switching terminal, the source signal line, and the source connection terminal are all symmetrical about the center line n of the display area.
  • the display area AA is divided into a central area AA1, and at least one first side area AA2 and at least one second side area AA3 located on both sides of the central area AA1.
  • the central area The size and number of AA1, the first side area AA2 and the second side area AA3 can be set as needed. For example, each area contains only one column of pixels, or each area contains one third of the total number of pixels of the display panel, etc. .
  • this application assigns the fan-out wiring connected to the data line in the same area to the corresponding area, and the source signal line connected to the fan-out wiring in the same area also belongs to the corresponding area; for example, The fan-out wiring connected to the data line in the central area AA1 is recorded as the central area fan-out wiring, and the source signal line connected to the central area fan-out wiring is recorded as the central area source signal line.
  • the fan-out traces connected by the data lines are recorded as the fan-out traces in the first side area
  • the source signal lines connected to the fan-out traces in the first side area are recorded as the source signal lines in the first side area
  • the second side area Fan-out traces connected to data lines in area AA3 are recorded as second-side area fan-out traces, etc.
  • source signal lines connected to second-side-area fan-out traces are recorded as second-side area source signal lines.
  • the fan-out wiring arrangements belonging to the same area are roughly the same, so their lengths are not too different, and the fan-out wiring arrangements in different areas are quite different, then The length difference is too large. Therefore, the cross-sectional shape of the source signal line belonging to the same area is the same, and the area decreases from the side to the center line. The cross-sectional shape of the source signal line belonging to different areas is different; this is convenient Adjust the area of each source signal line and then adjust its resistance.
  • the sum of the resistances of the first source signal line 141 and the first fan-out wiring 211 is equal to the sum of the resistances of the second source signal line 142 and the second fan-out wiring 212.
  • the cross-sectional area of the first source signal line 141 remains unchanged from one end to the other end.
  • the cross-sectional area of the second source signal line is gradually reduced from one end to the other end, for example, the cross-sectional area of the second source signal line is set in a manner such as a proportional reduction.
  • the cross-sectional areas of the plurality of first source signal lines are different, and gradually increase from the middle area to the two side areas.
  • the cross-sectional areas of the plurality of first source signal lines are the same.
  • the cross-sectional areas of the plurality of second source signal lines are different, and gradually increase from the middle area to the two side areas.
  • the cross-sectional areas of the plurality of second source signal lines are the same.
  • the cross section of the first source signal line 141 is a first rectangle
  • the cross section of the second source signal line 142 is a second rectangle.
  • the area of the first rectangle is smaller than the area of the second rectangle.
  • a source signal line with a rectangular cross section is used to reduce the design difficulty of the source signal line.
  • the length of the base of the first rectangle is less than the length of the base of the second rectangle, and/or the width of the first rectangle is less than the width of the second rectangle.
  • the cross section of the first source signal line 141 is a first trapezoid
  • the cross section of the second source signal line 142 is a second trapezoid
  • the The area of the first trapezoid is smaller than the area of the second trapezoid.
  • the length of the bottom side of the first trapezoid is less than the length of the bottom side of the second trapezoid, and/or the length of the top side of the first trapezoid is less than the length of the top side of the second trapezoid, And/or the height of the first trapezoid is smaller than the height of the second trapezoid.
  • the cross section of the first source signal line 141 is a third trapezoid
  • the cross section of the second source signal line 142 is a third rectangle
  • the The area of the third trapezoid is smaller than the area of the third rectangle.
  • half of the sum of the length of the bottom side and the top side of the third trapezoid is less than the length of the bottom side of the third rectangle, and/or the height of the third trapezoid is less than that of the third rectangle. height.
  • the cross section of the first source signal line 141 is a first circular shape
  • the cross section of the second source signal line 142 is a horizontal second circular shape
  • the area of the first circle is smaller than the area of the second circle.
  • the present application provides a new flip chip film and a display device.
  • the flip chip film includes a substrate; a source drive chip arranged on the substrate and includes a source drive terminal; a source connection terminal connected to the source drive The terminals are arranged in one-to-one correspondence; a source signal line is connected to the source connection terminal and the source drive terminal; wherein, the source signal line includes a first source signal line located in the middle area and a first source signal line located in both sides of the area On the reference plane, the cross-sectional area of the first source signal line is smaller than the cross-sectional area of the second source signal line; based on this structure, the impedance of the first source signal line can be greater than The impedance of the second source signal line.
  • the first source signal line is connected to the first fan-out wiring in the middle area
  • the second source The signal line is connected to the second fan-out wiring located on both sides of the area, and the attenuation from the source driver chip to each data line is approximately the same or even the same, so that the charging of the pixels in different positions in the display area is approximately the same or even the same, alleviating the existing technology.
  • the different lengths of the fan-out traces in the fan-out area lead to the technical problem of different charging of pixels in different positions in the display area.

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Abstract

一种覆晶薄膜（10）及显示装置（30），该覆晶薄膜（10）的源极信号线（14）包括位于中间区域（A1）的第一源极信号线（141）和位于两侧区域（A2）的第二源极信号线（142），在参考面（m）上，第一源极信号线（141）的横截面面积小于第二源极信号线（142）的横截面面积；基于此结构，可以使得源极驱动芯片（12）到各数据线的衰减大致相同甚至完全相同。

Description

覆晶薄膜及显示装置 技术领域
本申请涉及显示领域，尤其涉及一种覆晶薄膜及显示装置。
 背景技术
显示面板具有显示区和非显示区，非显示区设置有扇出区和绑定区，扇出区内的扇出走线连接显示区内像素的数据线以及绑定区内的源极转换端子；但是由于扇出区内部分扇出走线的长度不同，具体表现为位于扇出区中间区域的扇出走线比较短，位于扇出区两侧区域的扇出走线比较长，而条扇出走线的截面积相同，所以两侧区域的扇出走线阻抗比中间区域的扇出走线阻抗大，使得信号在两侧的扇出走线衰减严重，最终导致与两侧区域扇出走线连接的像素，与中间区域扇出走线连接的像素相比，存在严重的充电不足，视效上表现为色偏。
即，现有技术存在扇出区内扇出走线长度不同导致显示区内不同位置像素充电不同的技术问题。
 技术问题
本申请提供一种覆晶薄膜及显示装置，以缓解现有技术存在扇出区内扇出走线长度不同导致显示区内不同位置像素充电不同的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供了一种覆晶薄膜，其包括：
基板；
源极驱动芯片，设置在所述基板上，包括源极驱动端子；
源极连接端子，与所述源极驱动端子一一对应设置；
源极信号线，连接所述源极连接端子以及所述源极驱动端子；
其中，所述源极信号线包括位于中间区域的多个第一源极信号线、和位于两侧区域的多个第二源极信号线，在参考面上，所述第一源极信号线的横截面面积小于第二源极信号线的横截面面积，所述参考面垂直于所述基板、且并行于所述源极连接端子的排列方向。
在本申请实施例提供的覆晶薄膜中，在所述参考面内，多个第一源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
在本申请实施例提供的覆晶薄膜中，在所述参考面内，多个第一源极信号线的横截面的面积相同。
在本申请实施例提供的覆晶薄膜中，在所述参考面内，多个第二源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
在本申请实施例提供的覆晶薄膜中，在所述参考面内，多个第二源极信号线的横截面的面积相同。
在本申请实施例提供的覆晶薄膜中，所述第一源极信号线的横截面积，从一端到另一端保持不变。
在本申请实施例提供的覆晶薄膜中，所述第二源极信号线的横截面积，从一端到另一端逐渐减小。
在本申请实施例提供的覆晶薄膜中，在所述参考面内，所述第一源极信号线的横截面为第一矩形，所述第二源极信号线的横截面为第二矩形，所述第一矩形的面积小于所述第二矩形的面积。
在本申请实施例提供的覆晶薄膜中，所述第一矩形的底边长度小于所述第二矩形的底边长度，和/或所述第一矩形的宽度小于所述第二矩形的宽度。
在本申请实施例提供的覆晶薄膜中，在所述参考面内，所述第一源极信号线的横截面为第一梯形，所述第二源极信号线的横截面为第二梯形，所述第一梯形的面积小于所述第二梯形的面积。
在本申请实施例提供的覆晶薄膜中，所述第一梯形的底边长度小于所述第二梯形的底边长度，和/或所述第一梯形的顶边长度小于所述第二梯形的顶边长度，和/或所述第一梯形的高度小于所述第二梯形的高度。
在本申请实施例提供的覆晶薄膜中，在所述参考面内，所述第一源极信号线的横截面为第三梯形，所述第二源极信号线的截面为横第三矩形，所述第三梯形的面积小于与所述第三矩形的面积。
在本申请实施例提供的覆晶薄膜中，所述第三梯形的底边与顶边长度之和的一半小于所述第三矩形的底边长度，和/或所述第三梯形的高度小于所述第三矩形的高度。
同时，本申请实施例还提供了一种显示装置，其包括：
显示面板，包括扇出走线以及源极转换端子，所述扇出走线包括位于中间区域的多个第一扇出走线、和位于两侧区域的多个第二扇出走线，所述源极转换端子包括与第一扇出走线连接的第一源极转换端子以及与第二扇出走线连接的第二源极转换端子，第一扇出走线的长度小于和第二扇出走线的长度；
覆晶薄膜，包括源极信号线以及源极连接端子，所述源极信号线包括位于中间区域的多个第一源极信号线、和位于两侧区域的多个第二源极信号线，所述源极连接端子包括与第一源极信号线连接的第一源极连接端子以及与第二源极信号线连接的第二源极连接端子；所述第一源极信号线通过第一源极连接端子以及第一源极转换端子电连接所述第一扇出走线，所述第二源极信号线通过第二源极连接端子以及第二源极转换端子电连接所述第二扇出走线；
其中，在参考面上，所述第一源极信号线的横截面面积小于第二源极信号线的横截面面积，所述参考面垂直于所述覆晶薄膜的基板、且并行于所述源极连接端子的排列方向。
在本申请实施例提供的显示装置中，在所述参考面内，多个第一源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
在本申请实施例提供的显示装置中，在所述参考面内，多个第一源极信号线的横截面的面积相同。
在本申请实施例提供的显示装置中，在所述参考面内，多个第二源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
在本申请实施例提供的显示装置中，在所述参考面内，多个第二源极信号线的横截面的面积相同。
在本申请实施例提供的显示装置中，所述第一源极信号线与所述第一扇出走线的电阻之和，与所述第二源极信号线与所述第二扇出走线的电阻之和相等。
在本申请实施例提供的显示装置中，所述第二源极信号线的横截面积，从一端到另一端逐渐减小。
 有益效果
本申请提供一种新的覆晶薄膜及显示装置，该覆晶薄膜包括基板；源极驱动芯片，设置在所述基板上，包括源极驱动端子；源极连接端子，与所述源极驱动端子一一对应设置；源极信号线，连接所述源极连接端子以及所述源极驱动端子；其中，所述源极信号线包括位于中间区域的第一源极信号线和位于两侧区域的第二源极信号线，在参考面上，第一源极信号线的横截面面积小于第二源极信号线的横截面面积；基于此结构，可以使得第一源极信号线的阻抗大于第二源极信号线的阻抗，在此基础上，将覆晶薄膜与显示面板绑定形成显示模组之后，第一源极信号线连接位于中间区域的第一扇出走线，第二源极信号线连接位于两侧区域的第二扇出走线，进而使得源极驱动芯片到各数据线的衰减大致相同甚至完全相同，使得显示区内不同位置像素充电大致相同甚至完全相同，缓解了现有技术存在扇出区内扇出走线长度不同导致显示区内不同位置像素充电不同的技术问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请提供的覆晶薄膜的结构示意图。
图2为本申请提供的覆晶薄膜的截面示意图。
图3为本申请提供的显示装置的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
针对现有技术存在的扇出区内扇出走线长度不同导致显示区内不同位置像素充电不同的技术问题，本申请能够缓解该缺陷。
在一种实施例中，如图1及图2所示，本申请实施例提供的覆晶薄膜10包括：
基板11；
源极驱动芯片12，设置在所述基板上11，包括源极驱动端子121；
源极连接端子13，与所述源极驱动端子121一一对应设置；
源极信号线14，连接所述源极连接端子13以及所述源极驱动端子121；
其中，所述源极信号线14包括位于中间区域A1的多个第一源极信号线141和位于两侧区域A2的多个第二源极信号线142，在参考面m上，所述第一源极信号线141的横截面面积小于第二源极信号线142的横截面面积，所述参考面m垂直于所述基板11、且并行于所述源极连接端子13的排列方向l。
在本申请实施例中，中间区域A1和两侧区域A2的大小可以根据需要设置。例如在一种实施例中，如图1所示，中间区域A1包括3个源极连接端子13，两侧区域A2分别包括剩余源极连接端子13的一半，即两个两侧区域A2分别包括2个源极连接端子13；而在另外一种实施例中，中间区域A1包括1个源极连接端子13，两侧区域A2分别包括剩余源极连接端子13的一半，即两个两侧区域A2分别包括3个源极连接端子13。
在本申请实施例中，两侧区域A2的数量可以大于两个，也即在中间区域A1的同一侧包括至少两个两侧区域A2。在一种实施例中，一个区域（包括中间区域或者两侧区域）仅包括一个源极连接端子。
在本申请实施例中，位于中间区域A1的第一源极信号线141是指连接位于中间区域A1的源极连接端子13的源极信号线14，位于两侧区域A2的第二源极信号线142是指连接位于两侧区域A2的源极连接端子13的源极信号线14。
本实施例提供一种覆晶薄膜，该覆晶薄膜包括基板；源极驱动芯片，设置在所述基板上，包括源极驱动端子；源极连接端子，与所述源极驱动端子一一对应设置；源极信号线，连接所述源极连接端子以及所述源极驱动端子；其中，所述源极信号线包括位于中间区域的第一源极信号线和位于两侧区域的第二源极信号线，在参考面上，第一源极信号线的横截面面积小于第二源极信号线的横截面面积；基于此结构，可以使得第一源极信号线的阻抗大于第二源极信号线的阻抗，在此基础上，将覆晶薄膜与显示面板绑定形成显示模组之后，第一源极信号线连接位于中间区域的第一扇出走线，第二源极信号线连接位于两侧区域的第二扇出走线，源极驱动芯片到各数据线的衰减大致相同甚至完全相同，使得显示区内不同位置像素充电大致相同甚至完全相同，缓解了现有技术存在扇出区内扇出走线长度不同导致显示区内不同位置像素充电不同的技术问题。
在一种实施例中，如图1所示，所述第一源极信号线141的横截面积，从一端到另一端保持不变。
在一种实施例中，所述第二源极信号线的横截面积，从一端到另一端逐渐减小，例如等比例减小等方式来设置。
在一种实施例中，如图1所示，在所述参考面内，多个第一源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
在一种实施例中，在所述参考面内，多个第一源极信号线的横截面的面积相同。
在一种实施例中，如图1所示，在所述参考面内，多个第二源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
在一种实施例中，在所述参考面内，多个第二源极信号线的横截面的面积相同。
在一种实施例中，如图2中（a）所示，在所述参考面内，所述第一源极信号线141的横截面为第一矩形，所述第二源极信号线142的横截面为第二矩形，所述第一矩形的面积小于所述第二矩形的面积。本实施例采用截面为矩形的源极信号线，降低源极信号线的设计难度。
在一种实施例中，如图2中（a）所示，所述第一矩形的底边长度小于所述第二矩形的底边长度，和/或所述第一矩形的宽度小于所述第二矩形的宽度。
在一种实施例中，如图2中（b）所示，在所述参考面内，所述第一源极信号线141的横截面为第一梯形，所述第二源极信号线142的横截面为第二梯形，所述第一梯形的面积小于所述第二梯形的面积。
在一种实施例中，如图2中（b）所示，所述第一梯形的底边长度小于所述第二梯形的底边长度，和/或所述第一梯形的顶边长度小于所述第二梯形的顶边长度，和/或所述第一梯形的高度小于所述第二梯形的高度。
在一种实施例中，如图2中（c）所示，在所述参考面内，所述第一源极信号线141的横截面为第三梯形，所述第二源极信号线142的横截面为第三矩形，所述第三梯形的面积小于与所述第三矩形的面积。
在一种实施例中，如图2中（c）所示，所述第三梯形的底边与顶边长度之和一半小于所述第三矩形的底边长度，和/或所述第三梯形的高度小于所述第三矩形的高度。
在一种实施例中，如图2中（d）所示，在所述参考面内，所述第一源极信号线141的横截面为第一圆形，所述第二源极信号线142的截面为横第二圆形，所述第一圆形的面积小于所述第二圆形的面积。
在一种实施例中，如图3以及图1所示，本申请提供的显示装置30包括显示面板20以及覆晶薄膜10（图3所示的状态是显示面板20与覆晶薄膜10没有绑定到一起的状态）；其中：
所述显示面板20包括显示区AA、扇出区FA以及绑定区BA，位于显示区AA的数据线23、位于扇出区FA的扇出走线21、以及位于绑定区BA的源极转换端子22，所述扇出走线21包括位于中间区域AA1的多个第一扇出走线211和位于两侧区域（包括中心区域AA1两侧的至少一个第一侧边区域AA2和至少一个第二侧边区域AA3）的多个第二扇出走线212，所述源极转换端子22包括与第一扇出走线211连接的第一源极转换端子以及与第二扇出走线212连接的第二源极转换端子，所述第一扇出走线211的长度小于第二扇出走线212的长度；
所述覆晶薄膜10包括源极信号线14以及源极连接端子13，所述源极信号线14包括位于中间区域A1的多个第一源极信号线141和位于两侧区域A2的多个第二源极信号线142，所述源极连接端子13包括与第一源极信号线141连接的第一源极连接端子以及与第二源极信号线142连接的第二源极连接端子；所述第一源极信号线141通过第一源极连接端子131以及第一源极转换端子221电连接所述第一扇出走线211，所述第二源极信号线142通过第二源极连接端子132以及第二源极转换端子222电连接所述第二扇出走线212；
其中，在参考面m上，所述第一源极信号线141的横截面面积小于第二源极信号线142的横截面面积，所述参考面垂直于所述覆晶薄膜的基板、且并行于所述源极连接端子的排列方向l；
显示面板20与覆晶薄膜10通过各向异性导电胶（ACA,Anisotropic Conductive Adhesives）绑定连接。
本实施例提供一种显示装置，该包括覆晶薄膜以及显示面板，第一源极信号线连接第一扇出走线，第二源极信号线连接第二扇出走线，源极驱动芯片到各数据线的衰减大致相同甚至完全相同，使得显示区内不同位置像素充电大致相同甚至完全相同，缓解了现有技术存在扇出区内扇出走线长度不同导致显示区内不同位置像素充电不同的技术问题。
在一种实施例中，如图3所示，数据线、扇出走线、源极转换端子、源极信号线以及源极连接端子均关于显示区的中心线n对称。
在一种实施例中，如图3所示，将显示区AA分为中心区域AA1以及位于中心区域AA1两侧的至少一个第一侧边区域AA2和至少一个第二侧边区域AA3，中心区域AA1、第一侧边区域AA2和第二侧边区域AA3可以根据需要设置其大小以及数量，例如每个区域仅包含一列像素，又如每个区域包含显示面板总像素数量的三分之一等。
为了便于下文说明，本申请将与同一个区域内的数据线连接的扇出走线归属于对应的区域，与同一个区域的扇出走线连接的源极信号线也归属于对应的区域；例如与中心区域AA1内的数据线连接的扇出走线记为中心区域扇出走线，与中心区域扇出走线连接的源极信号线记为中心区域源极信号线，与第一侧边区域AA2内的数据线连接的扇出走线记为第一侧边区域扇出走线，与第一侧边区域扇出走线连接的源极信号线记为第一侧边区域源极信号线，与第二侧边区域AA3内的数据线连接的扇出走线记为第二侧边区域扇出走线等，与第二侧边区域扇出走线连接的源极信号线记为第二侧边区域源极信号线。
在一种实施例中，如图3所示，归属于同一个区域的扇出走线排布方式大体相同，那么其长度相差不太大，不同区域的扇出走线排布方式差异较大，那么其长度相差太大，因此，归属于同一个区域的源极信号线的截面形状相同、且面积从侧边向中心线方向递减，归属于不同区域的源极信号线的截面形状不同；这样便于调整各源极信号线的面积进而调整其电阻。
在一种实施例中，第一源极信号线141与第一扇出走线211的电阻之和，与第二源极信号线142与第二扇出走线212的电阻之和相等。
在一种实施例中，如图3所示，所述第一源极信号线141的横截面积，从一端到另一端保持不变。
在一种实施例中，所述第二源极信号线的横截面积，从一端到另一端逐渐减小，例如等比例减小等方式来设置。
在一种实施例中，如图1所示，在所述参考面内，多个第一源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
在一种实施例中，在所述参考面内，多个第一源极信号线的横截面的面积相同。
在一种实施例中，如图1所示，在所述参考面内，多个第二源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
在一种实施例中，在所述参考面内，多个第二源极信号线的横截面的面积相同。
在一种实施例中，在所述参考面内，所述第一源极信号线141的横截面为第一矩形，所述第二源极信号线142的横截面为第二矩形，所述第一矩形的面积小于所述第二矩形的面积。本实施例采用截面为矩形的源极信号线，降低源极信号线的设计难度。
在一种实施例中，所述第一矩形的底边长度小于所述第二矩形的底边长度，和/或所述第一矩形的宽度小于所述第二矩形的宽度。
在一种实施例中，在所述参考面内，所述第一源极信号线141的横截面为第一梯形，所述第二源极信号线142的横截面为第二梯形，所述第一梯形的面积小于所述第二梯形的面积。
在一种实施例中，所述第一梯形的底边长度小于所述第二梯形的底边长度，和/或所述第一梯形的顶边长度小于所述第二梯形的顶边长度，和/或所述第一梯形的高度小于所述第二梯形的高度。
在一种实施例中，在所述参考面内，所述第一源极信号线141的横截面为第三梯形，所述第二源极信号线142的横截面为第三矩形，所述第三梯形的面积小于与所述第三矩形的面积。
在一种实施例中，所述第三梯形的底边与顶边长度之和一半小于所述第三矩形的底边长度，和/或所述第三梯形的高度小于所述第三矩形的高度。
在一种实施例中，在所述参考面内，所述第一源极信号线141的横截面为第一圆形，所述第二源极信号线142的截面为横第二圆形，所述第一圆形的面积小于所述第二圆形的面积。
根据上述实施例可知：
本申请提供一种新的覆晶薄膜及显示装置，该覆晶薄膜包括基板；源极驱动芯片，设置在所述基板上，包括源极驱动端子；源极连接端子，与所述源极驱动端子一一对应设置；源极信号线，连接所述源极连接端子以及所述源极驱动端子；其中，所述源极信号线包括位于中间区域的第一源极信号线和位于两侧区域的第二源极信号线，在参考面上，第一源极信号线的横截面面积小于第二源极信号线的横截面面积；基于此结构，可以使得第一源极信号线的阻抗大于第二源极信号线的阻抗，在此基础上，将覆晶薄膜与显示面板绑定形成显示模组之后，第一源极信号线连接位于中间区域的第一扇出走线，第二源极信号线连接位于两侧区域的第二扇出走线，源极驱动芯片到各数据线的衰减大致相同甚至完全相同，使得显示区内不同位置像素充电大致相同甚至完全相同，缓解了现有技术存在扇出区内扇出走线长度不同导致显示区内不同位置像素充电不同的技术问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种覆晶薄膜，其包括：
    基板；
    源极驱动芯片，设置在所述基板上，包括源极驱动端子；
    源极连接端子，与所述源极驱动端子一一对应设置；
    源极信号线，连接所述源极连接端子以及所述源极驱动端子；
    其中，所述源极信号线包括位于中间区域的多个第一源极信号线、和位于两侧区域的多个第二源极信号线，在参考面上，所述第一源极信号线的横截面面积小于第二源极信号线的横截面面积，所述参考面垂直于所述基板、且并行于所述源极连接端子的排列方向。
  2. 根据权利要求1所述的覆晶薄膜，其中，在所述参考面内，多个第一源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
  3. 根据权利要求1所述的覆晶薄膜，其中，在所述参考面内，多个第一源极信号线的横截面的面积相同。
  4. 根据权利要求1所述的覆晶薄膜，其中，在所述参考面内，多个第二源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
  5. 根据权利要求1所述的覆晶薄膜，其中，在所述参考面内，多个第二源极信号线的横截面的面积相同。
  6. 根据权利要求1所述的覆晶薄膜，其中，所述第一源极信号线的横截面积，从一端到另一端保持不变。
  7. 根据权利要求1所述的覆晶薄膜，其中，所述第二源极信号线的横截面积，从一端到另一端逐渐减小。
  8. 根据权利要求1所述的覆晶薄膜，其中，在所述参考面内，所述第一源极信号线的横截面为第一矩形，所述第二源极信号线的横截面为第二矩形，所述第一矩形的面积小于所述第二矩形的面积。
  9. 根据权利要求8所述的覆晶薄膜，其中，所述第一矩形的底边长度小于所述第二矩形的底边长度，和/或所述第一矩形的宽度小于所述第二矩形的宽度。
  10. 根据权利要求1所述的覆晶薄膜，其中，在所述参考面内，所述第一源极信号线的横截面为第一梯形，所述第二源极信号线的横截面为第二梯形，所述第一梯形的面积小于所述第二梯形的面积。
  11. 根据权利要求10所述的覆晶薄膜，其中，所述第一梯形的底边长度小于所述第二梯形的底边长度，和/或所述第一梯形的顶边长度小于所述第二梯形的顶边长度，和/或所述第一梯形的高度小于所述第二梯形的高度。
  12. 根据权利要求1所述的覆晶薄膜，其中，在所述参考面内，所述第一源极信号线的横截面为第三梯形，所述第二源极信号线的截面为横第三矩形，所述第三梯形的面积小于与所述第三矩形的面积。
  13. 根据权利要求12所述的覆晶薄膜，其中，所述第三梯形的底边与顶边长度之和的一半小于所述第三矩形的底边长度，和/或所述第三梯形的高度小于所述第三矩形的高度。
  14. 一种显示装置，其包括：
    显示面板，包括扇出走线以及源极转换端子，所述扇出走线包括位于中间区域的多个第一扇出走线、和位于两侧区域的多个第二扇出走线，所述源极转换端子包括与第一扇出走线连接的第一源极转换端子以及与第二扇出走线连接的第二源极转换端子，第一扇出走线的长度小于第二扇出走线的长度；
    覆晶薄膜，包括源极信号线以及源极连接端子，所述源极信号线包括位于中间区域的多个第一源极信号线、和位于两侧区域的多个第二源极信号线，所述源极连接端子包括与第一源极信号线连接的第一源极连接端子以及与第二源极信号线连接的第二源极连接端子；所述第一源极信号线通过第一源极连接端子以及第一源极转换端子电连接所述第一扇出走线，所述第二源极信号线通过第二源极连接端子以及第二源极转换端子电连接所述第二扇出走线；
    其中，在参考面上，所述第一源极信号线的横截面面积小于第二源极信号线的横截面面积，所述参考面垂直于所述覆晶薄膜的基板、且并行于所述源极连接端子的排列方向。
  15. 根据权利要求14所述的显示装置，其中，在所述参考面内，多个第一源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
  16. 根据权利要求14所述的显示装置，其中，在所述参考面内，多个第一源极信号线的横截面的面积相同。
  17. 根据权利要求14所述的显示装置，其中，在所述参考面内，多个第二源极信号线的横截面的面积不同，且沿中间区域到两侧区域的方向上逐渐增大。
  18. 根据权利要求14所述的显示装置，其中，在所述参考面内，多个第二源极信号线的横截面的面积相同。
  19. 根据权利要求14所述的显示装置，其中，所述第一源极信号线与所述第一扇出走线的电阻之和，与所述第二源极信号线与所述第二扇出走线的电阻之和相等。
  20. 根据权利要求14所述的显示装置，其中，所述第二源极信号线的横截面积，从一端到另一端逐渐减小。
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CN113539114B (zh) * 2021-07-30 2023-04-21 惠科股份有限公司 覆晶薄膜和显示装置
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102246218A (zh) * 2009-12-10 2011-11-16 松下电器产业株式会社 显示屏模块以及显示装置
CN103839488A (zh) * 2012-11-23 2014-06-04 乐金显示有限公司 显示装置
US20170184903A1 (en) * 2015-12-28 2017-06-29 Seiko Epson Corporation Electrooptic device and electronic device
CN109976052A (zh) * 2019-04-29 2019-07-05 深圳市华星光电技术有限公司 显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100237679B1 (ko) * 1995-12-30 2000-01-15 윤종용 저항 차를 줄이는 팬 아웃부를 가지는 액정 표시 패널
JP2003140181A (ja) * 2001-11-02 2003-05-14 Nec Corp 液晶表示装置
US20070216845A1 (en) * 2006-03-16 2007-09-20 Chia-Te Liao Uniform impedance conducting lines for a liquid crystal display
KR101281867B1 (ko) * 2006-06-29 2013-07-03 엘지디스플레이 주식회사 액정표시장치
JP5260912B2 (ja) * 2007-07-31 2013-08-14 パナソニック液晶ディスプレイ株式会社 表示装置
TWI395007B (zh) * 2009-09-30 2013-05-01 Au Optronics Corp 扇出線路以及顯示面板
KR20180061856A (ko) * 2016-11-30 2018-06-08 엘지디스플레이 주식회사 플렉서블 표시장치
CN109461765B (zh) 2018-11-08 2020-12-15 上海天马有机发光显示技术有限公司 显示面板及显示装置
CN110139470A (zh) * 2019-05-13 2019-08-16 深圳市华星光电技术有限公司 柔性电路板及显示装置
CN110134278A (zh) * 2019-05-13 2019-08-16 京东方科技集团股份有限公司 触控显示面板及其制造方法、触控显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102246218A (zh) * 2009-12-10 2011-11-16 松下电器产业株式会社 显示屏模块以及显示装置
CN103839488A (zh) * 2012-11-23 2014-06-04 乐金显示有限公司 显示装置
US20170184903A1 (en) * 2015-12-28 2017-06-29 Seiko Epson Corporation Electrooptic device and electronic device
CN109976052A (zh) * 2019-04-29 2019-07-05 深圳市华星光电技术有限公司 显示装置

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