WO2021208120A1 - 一种显示面板 - Google Patents

一种显示面板 Download PDF

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Publication number
WO2021208120A1
WO2021208120A1 PCT/CN2020/086035 CN2020086035W WO2021208120A1 WO 2021208120 A1 WO2021208120 A1 WO 2021208120A1 CN 2020086035 W CN2020086035 W CN 2020086035W WO 2021208120 A1 WO2021208120 A1 WO 2021208120A1
Authority
WO
WIPO (PCT)
Prior art keywords
goa
bus
unit
goa circuit
display panel
Prior art date
Application number
PCT/CN2020/086035
Other languages
English (en)
French (fr)
Inventor
朱静
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/763,535 priority Critical patent/US11468811B2/en
Publication of WO2021208120A1 publication Critical patent/WO2021208120A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • This application relates to the field of display technology, and in particular to a display panel.
  • the gate driver array (Gate Driver On Array, GOA) technology is a technology in which gate driver ICs (Gate Driver ICs) are directly fabricated on an array substrate to replace driver chips made by external silicon chips.
  • GOA Gate Driver On Array
  • GOA In AA GOA circuit is located in the display area
  • the present application provides a display panel, which can solve the problems of low aperture ratio and insufficient transmittance of existing narrow-frame display panels.
  • the present application provides a display panel, which includes a display area and a non-display area located at the periphery of the display area, the display area includes pixel units distributed in an array, and the non-display area on opposite sides of the display area is provided with GOA bus unit;
  • Two GOA circuit units are arranged side by side between the pixel units in two adjacent rows, and the two GOA circuit units arranged side by side are electrically connected to the pixel units;
  • the GOA circuit unit is electrically connected to the GOA bus unit through a signal connection line arranged in the display area;
  • two GOA circuit units arranged side by side share at least one signal connection line.
  • the GOA bus unit includes at least one signal bus extending in a column direction, and one signal connection line is correspondingly connected to one signal bus.
  • the signal bus includes a first low-frequency clock signal bus and a second low-frequency clock signal bus
  • the GOA circuit unit is connected to the first low-frequency clock signal connection line and the second low-frequency clock signal connection line respectively.
  • the first low-frequency clock signal bus and the second low-frequency clock signal bus are electrically connected; wherein two GOA circuit units arranged side by side share the first low-frequency clock signal connection line and the second low-frequency clock signal connection line At least one of them.
  • the signal bus includes a reset signal bus
  • the GOA circuit unit is electrically connected to the reset signal bus through a reset signal connection line; wherein, two GOA circuit units arranged side by side share one Reset signal connection line.
  • the signal bus includes a power signal bus
  • the GOA circuit unit is electrically connected to the power signal bus through a power signal connection line; wherein, two GOA circuit units arranged side by side share one Power signal connection line.
  • two GOA circuit units arranged side by side are electrically connected to the pixel units in the same row, or two GOA circuit units arranged side by side are electrically connected to the pixel units in two adjacent rows.
  • the two GOA circuit units arranged side by side are a first GOA circuit unit and a second GOA circuit unit.
  • the GOA bus unit includes a first GOA bus unit and a second GOA bus unit.
  • a GOA circuit unit is electrically connected to the first GOA bus unit, and the second GOA circuit unit is electrically connected to the second GOA bus unit.
  • one of the first GOA bus unit and the second GOA bus unit includes the first low-frequency clock signal bus, and the other includes the second low-frequency clock signal bus;
  • One of the first GOA bus unit and the second GOA bus unit includes the reset signal bus, and the other includes the power signal bus.
  • the number of the signal buses in the first GOA bus unit and the second GOA bus unit are equal.
  • the GOA circuit unit and the signal connection line are both located between the pixel units in two adjacent rows, and the GOA circuit unit is electrically connected to the pixel unit through a scan line.
  • the present application also provides a display panel, which includes a display area and a non-display area located at the periphery of the display area, the display area includes pixel units arranged in an array, and the non-display area on opposite sides of the display area Equipped with GOA bus unit;
  • the display panel is of a bidirectional drive type, two GOA circuit units are arranged side by side between the pixel units in two adjacent rows, and the two GOA circuit units arranged side by side are electrically connected to the pixel units;
  • the GOA circuit unit is electrically connected to the GOA bus unit through a signal connection line arranged in the display area;
  • two GOA circuit units arranged side by side share at least one signal connection line.
  • the GOA bus unit includes at least one signal bus extending in a column direction, and one signal connection line is correspondingly connected to one signal bus.
  • the signal bus includes a first low-frequency clock signal bus and a second low-frequency clock signal bus
  • the GOA circuit unit is connected to the first low-frequency clock signal connection line and the second low-frequency clock signal connection line respectively.
  • the first low-frequency clock signal bus and the second low-frequency clock signal bus are electrically connected; wherein two GOA circuit units arranged side by side share the first low-frequency clock signal connection line and the second low-frequency clock signal connection line At least one of them.
  • the signal bus includes a reset signal bus
  • the GOA circuit unit is electrically connected to the reset signal bus through a reset signal connection line; wherein, two GOA circuit units arranged side by side share one Reset signal connection line.
  • the signal bus includes a power signal bus
  • the GOA circuit unit is electrically connected to the power signal bus through a power signal connection line; wherein, two GOA circuit units arranged side by side share one Power signal connection line.
  • two GOA circuit units arranged side by side are electrically connected to the pixel units in the same row, or two GOA circuit units arranged side by side are electrically connected to the pixel units in two adjacent rows.
  • the two GOA circuit units arranged side by side are a first GOA circuit unit and a second GOA circuit unit.
  • the GOA bus unit includes a first GOA bus unit and a second GOA bus unit.
  • a GOA circuit unit is electrically connected to the first GOA bus unit, and the second GOA circuit unit is electrically connected to the second GOA bus unit.
  • one of the first GOA bus unit and the second GOA bus unit includes the first low-frequency clock signal bus, and the other includes the second low-frequency clock signal bus;
  • One of the first GOA bus unit and the second GOA bus unit includes the reset signal bus, and the other includes the power signal bus.
  • the number of the signal buses in the first GOA bus unit and the second GOA bus unit are equal.
  • the GOA circuit unit and the signal connection line are both located between the pixel units in two adjacent rows, and the GOA circuit unit is electrically connected to the pixel unit through a scan line.
  • the display panel provided by the present application has two GOA circuit units arranged side by side between two adjacent rows of pixel units, and the two GOA circuit units arranged side by side are electrically connected to the same row of pixel units.
  • Bidirectional driving to improve the driving capability of the display panel; in addition, the two GOA circuit units arranged side by side in the present application share at least one signal connection line to connect to the GOA bus unit, thereby reducing the total number of signal connection lines in the display area and saving space It can be used to increase the aperture ratio of the pixel unit, thereby increasing the transmittance of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided in Embodiment 1 of the application;
  • FIG. 2 is a schematic diagram of the structure of a display panel provided in the second embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a display panel provided in Embodiment 3 of the application.
  • FIG. 4 is a schematic structural diagram of a display panel provided in the fourth embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features.
  • “multiple” means two or more than two, unless otherwise specifically defined. In this application, “/” means “or”.
  • the GOA display panel uses the GOA circuit to drive the display panel for display.
  • the GOA circuit includes GOA Busline and GOA Circuit.
  • the RC (Resistance-Capacitance) load of the GOA bus unit is heavier. It is not suitable to be placed in the display area.
  • the GOA bus unit is set in the frame area of the display panel, and the GOA circuit unit is set in the display area to achieve a narrow side width.
  • the multi-level GOA circuit units are arranged between the pixels in the display area, and each level of the GOA circuit unit drives a row of pixel units correspondingly, it is necessary to lay multiple signal connection lines between the pixels to transmit signals.
  • the number of GOA circuit units and signal connection lines will also increase, and GOA circuit units and signal connection lines also require a certain amount of space, so that the aperture ratio of the pixel unit is compressed, and thus Affect the penetration rate of the display panel.
  • the present application provides a display panel to solve the above-mentioned defects.
  • the display panel of the present application includes a display area and a non-display area located at the periphery of the display area.
  • the display area includes pixel units distributed in an array.
  • a GOA bus unit is arranged in the non-display area.
  • Two GOA circuit units and a plurality of signal connection lines are arranged side by side between the pixel units in two adjacent rows in the display area, and the two GOA circuit units arranged side by side are electrically connected to the pixel units.
  • the display panel of the present application is a bidirectional drive type, that is, includes two sets of GOA circuits, each set of GOA circuits includes N-level GOA circuit units, where N is a positive integer greater than zero. Each GOA circuit unit is connected to a scan line.
  • the GOA bus unit includes multiple signal buses, which are respectively used to transmit different driving signals, each level of GOA circuit unit needs to be electrically connected to multiple signal buses in a one-to-one correspondence through multiple signal connection lines.
  • the GOA bus unit includes a first low-frequency clock signal bus, a second low-frequency clock signal bus, a reset signal bus, a power signal bus, and a multi-level high-frequency clock signal bus.
  • the GOA circuit unit is electrically connected to the GOA bus unit through a signal connection line.
  • each GOA circuit unit and the GOA bus unit are connected through a first low-frequency clock signal connection line, a second low-frequency clock signal connection line, and reset
  • the signal connection line is connected with the power supply signal and the high-frequency clock signal connection line realizes signal transmission.
  • two GOA circuit units arranged side by side in the display area of the display panel share at least one signal connection line. Therefore, the total number of signal connection lines in the display area is reduced, and the saved space can be used to increase the aperture ratio of the pixel unit, thereby improving the transmittance of the display panel.
  • FIG. 1 is a schematic diagram of the structure of the display panel provided in the first embodiment of this application.
  • the display panel 1 includes pixel units 2 arranged in an array in the display area 10, and GOA circuit units 3 and signal connection lines 4 located between two adjacent rows of pixel units 2.
  • Each level of GOA circuit unit 3 is connected to each other through scan lines 6
  • a row of pixel units 2 are electrically connected, and the GOA circuit unit 3 is used to provide gate signals for the pixel units 2 connected to it.
  • two GOA circuit units are arranged side by side along the row direction between the pixel units 2 in two adjacent rows, and the two GOA circuit units arranged side by side are electrically connected to the pixel units 2 in the same row.
  • the two GOA circuit units arranged side by side are GOA circuit units of the same level in the two sets of GOA circuits, so the pixel units 2 in the same row can be driven at the same time.
  • the two GOA circuit units arranged side by side are a first GOA circuit unit 31 and a second GOA circuit unit 32.
  • the first GOA circuit unit 31 is connected to a part of the pixel units 2 in a row of pixel units 2 (for example, the same as the left half of the pixel unit).
  • the second GOA circuit unit 32 is electrically connected to the remaining pixel units 2 in the row of pixel units 2 (for example, to the right half of the pixel units).
  • the first GOA circuit units 31 in different rows are located in the same column, and the second GOA circuit units 32 in different rows are located in the same column, which is of course not limited thereto.
  • the non-display area 11 on opposite sides of the display area 10 is provided with a GOA bus unit 5, and the GOA circuit unit 3 is electrically connected to the GOA bus unit 5 through the signal connection line 4.
  • the GOA bus unit 5 includes at least one signal bus extending in a column direction, and one signal connection line 4 is correspondingly connected to one signal bus. Wherein, two GOA circuit units arranged side by side in the same row share at least one signal connection line.
  • the GOA bus unit 5 includes a first GOA bus unit 51 and a second GOA bus unit 52, and the first GOA bus unit 51 and the second GOA bus unit 52 are respectively located opposite to the display area 10. On both sides.
  • the first GOA circuit unit 31 is electrically connected to the first GOA bus unit 51
  • the second GOA circuit unit 32 is electrically connected to the second GOA bus unit 52.
  • the signal bus includes a first low-frequency clock signal bus 501, a second low-frequency clock signal bus 502, a reset signal bus 503, a power signal bus 504, and multiple high-frequency clock signal buses (CK) extending along the column direction, such as CK1 ⁇ CKn, n is a positive integer greater than or equal to 2. In this embodiment, n is equal to 8 as an example.
  • the signal connection line 4 includes a first low-frequency clock signal connection line 41, a second low-frequency clock signal connection line 42, a reset signal connection line 43, a power signal connection line 44, and a high-frequency clock signal connection line 45.
  • the first low-frequency clock signal bus 501 is used to transmit a first low-frequency clock signal (LC1)
  • the second low-frequency clock signal bus 502 is used to transmit a second low-frequency clock signal (LC2)
  • the reset signal bus 503 The power signal bus 504 is used to transmit a reset signal (RST)
  • the power signal bus 504 is used to transmit a power signal (VSS)
  • the plurality of high-frequency clock signal buses (CK) are used to transmit a high-frequency clock signal.
  • the first GOA bus unit 51 and the second GOA bus unit 52 both include the high-frequency clock signal bus (CK1...CK8) and the reset signal bus 503 And the power signal bus 504.
  • one of the first GOA bus unit 51 and the second GOA bus unit 52 includes the first low-frequency clock signal bus 501, and the other includes the second low-frequency clock signal bus 502.
  • the number of the signal buses in the first GOA bus unit 51 and the second GOA bus unit 52 is equal.
  • the first GOA circuit unit 31 is connected to the first GOA bus unit 51 through a first set of the reset signal connection line 43, the power signal connection line 44, and the high-frequency clock signal connection line 45, respectively.
  • the reset signal bus 503, the power signal bus 504, and the high-frequency clock signal bus (one of CK1...CK8, such as CK1) are electrically connected in a one-to-one correspondence.
  • the second GOA circuit unit 32 is connected to all of the second GOA bus unit 52 through a second set of the reset signal connection line 43, the power signal connection line 44, and the high-frequency clock signal connection line 45.
  • the reset signal bus 503, the power signal bus 504, and the high-frequency clock signal bus (one of CK1...CK8, such as CK1) are electrically connected in a one-to-one correspondence.
  • the first GOA circuit unit 31 and the second GOA circuit unit 32 share at least one of the first low-frequency clock signal connection line 41 and the second low-frequency clock signal connection line 42.
  • the first GOA circuit unit 31 and the second GOA circuit unit 32 share the first low-frequency clock signal connection line 41 and communicate with the first low-frequency clock signal connection line 41 through the first GOA circuit unit 31 and the second GOA circuit unit 32.
  • a low-frequency clock signal bus 501 is electrically connected; and the first GOA circuit unit 31 and the second GOA circuit unit 32 share the second low-frequency clock signal connection line 42 and pass through the second low-frequency clock signal connection line 42 is electrically connected to the second low-frequency clock signal bus 502.
  • the first low-frequency clock signal bus 501 transmits the first low-frequency clock signal to the first GOA circuit unit 31 and the second GOA circuit unit 32 through the first low-frequency clock signal connection line 41 ( LC1), the second low-frequency clock signal bus 502 transmits a second low-frequency clock signal (LC2 ).
  • the first GOA circuit unit 31 and the second GOA circuit unit 32 may share one of the first low-frequency clock signal connection line 41 and the second low-frequency clock signal connection line 42 A sort of.
  • the frame of the display panel is wider and The aperture ratio and transmittance of the pixel are reduced.
  • this application reduces one signal bus in the first GOA bus unit and the second GOA bus unit on both sides of the display area, thereby reducing the frame of the display panel and reducing the signal connections in the display area.
  • the number of lines increases the aperture ratio and transmittance of the pixel.
  • the GOA circuit units of the same level in the two sets of GOA circuits are correspondingly connected to the same scan line, so that the two sets of GOA circuits can drive the same row of pixel units together. Due to the increase in the resolution and size of the display panel, the signal attenuation is more serious, and the use of bidirectional driving can solve this problem and improve the driving force of the display panel.
  • FIG. 2 is a schematic structural diagram of the display panel provided in the second embodiment of this application.
  • the structure of the display panel in this embodiment is the same as/similar to the display panel in the first embodiment, except that the two GOA circuit units 3 arranged side by side in the display panel in this embodiment and the pixels in two adjacent rows Unit 2 is electrically connected.
  • the first GOA circuit unit 31 and the second GOA circuit unit 32 arranged side by side in the row direction differ by one level in the number of stages.
  • the first GOA circuit unit 31 is the first GOA circuit in the first set of GOA circuits.
  • N-level GOA circuit unit is the N+1th level GOA circuit unit in the second set of GOA circuits, and N is a positive integer greater than zero. Therefore, the first GOA circuit unit 31 and the second GOA circuit unit 32 arranged side by side in the same row are used to drive the pixel units 2 in adjacent rows, respectively.
  • the first GOA circuit unit 31 is connected to a part of the pixel units 2 in a row of pixel units 2 (for example, with the left half of the pixel unit ) Electrically connected, the second GOA circuit unit 32 is electrically connected to a part of the pixel units 2 in the upper/lower row of pixel units 2 (for example, to the right half of the pixel units).
  • two GOA circuit units 3 arranged side by side are electrically connected to two adjacent scan lines, so that two sets of GOA circuits can drive the same row of pixel units together. Due to the increase in the resolution and size of the display panel, the signal attenuation is more serious, and the use of bidirectional driving can solve this problem and improve the driving force of the display panel.
  • one signal bus is reduced in the first GOA bus unit and the second GOA bus unit on both sides of the display area, thereby reducing the frame of the display panel and also reducing the display area.
  • the number of internal signal connection lines increases the aperture ratio and transmittance of the pixel.
  • FIG. 3 is a schematic diagram of the structure of the display panel provided in the third embodiment of this application.
  • the structure of the display panel of this embodiment is the same as/similar to the display panel of the first embodiment, except that the two GOA circuit units 3 arranged side by side in the display panel of this embodiment share one reset signal connection line 43 And, one of the first GOA bus unit 51 and the second GOA bus unit 52 includes a reset signal bus 503, and the other does not include a reset signal bus 503.
  • the reset signal bus 503 transmits a reset signal (RST );
  • the first low-frequency clock signal bus 501 transmits a first low-frequency clock signal to the first GOA circuit unit 31 and the second GOA circuit unit 32 through a shared first low-frequency clock signal connection line 41, respectively (LC1);
  • the second low-frequency clock signal bus 502 transmits a second low-frequency signal to the first GOA circuit unit 31 and the second GOA circuit unit 32 through a shared second low-frequency clock signal connection line 42 respectively Clock signal (LC2).
  • one signal bus is reduced in the first GOA bus unit and the second GOA bus unit, and a reset signal bus is reduced in the first GOA bus unit or the second GOA bus unit. Therefore, the frame of the display panel is further reduced, and the number of signal connection lines in the display area is also reduced, thereby further increasing the aperture ratio and transmittance of the pixel.
  • FIG. 4 is a schematic structural diagram of the display panel provided in the fourth embodiment of this application.
  • the structure of the display panel in this embodiment is the same as/similar to the display panel in the third embodiment above, except that the two GOA circuit units 3 arranged side by side in the display panel in this embodiment share a power signal connection line 44, and One of the first GOA bus unit 51 and the second GOA bus unit 52 includes a power signal bus 504, and the other does not include a power signal bus 504.
  • the power signal bus 504 transmits a power signal (VSS) to the first GOA circuit unit 31 and the second GOA circuit unit 32 through a common power signal connection line 44, respectively );
  • the reset signal bus 503 transmits a reset signal (RST) to the first GOA circuit unit 31 and the second GOA circuit unit 32 through a common reset signal connection line 43;
  • the clock signal bus 501 transmits a first low-frequency clock signal (LC1) to the first GOA circuit unit 31 and the second GOA circuit unit 32 through a common first low-frequency clock signal connection line 41;
  • the two low-frequency clock signal buses 502 respectively transmit a second low-frequency clock signal (LC2) to the first GOA circuit unit 31 and the second GOA circuit unit 32 through a common second low-frequency clock signal connection line 42.
  • one of the first GOA bus unit 51 and the second GOA bus unit 52 includes the reset signal bus 503, and the other includes the power signal bus 504.
  • one power signal bus is reduced in the first GOA bus unit or the second GOA bus unit. Therefore, compared with the third embodiment, the display panel can be further reduced. It also reduces the number of signal connection lines in the display area, thereby further increasing the aperture ratio and transmittance of the pixel.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示面板（1），显示面板（1）的显示区（10）包括像素单元（2），显示区（10）两侧的非显示区（11）设有GOA总线单元（5）；相邻两行像素单元（2）之间并排设有两个GOA电路单元（3），且并排设置的两个GOA电路单元（3）与像素单元（2）电连接；GOA电路单元（3）通过信号连接线（4）与GOA总线单元（5）电连接；其中，并排设置的两个GOA电路单元（3）共用至少一条信号连接线（4），从而有利于增大像素单元的开口率和穿透率。

Description

一种显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
栅极驱动阵列(Gate Driver On Array，GOA)技术是直接将栅极驱动电路(Gate Driver ICs)制作在阵列(Array)基板上，来代替由外接硅芯片制作的驱动芯片的一种技术。目前，大尺寸、高解析度的显示产品及极致窄边框的显示产品成为市场的趋势，拼接屏的需求对四边窄边宽的要求更是最求极致。并且，为了最求低成本和外观的极致，GOA In AA （GOA电路位于显示区）的技术越来越多的得到青睐。
然而，随着解析度变高和像素尺寸缩小，GOA布局空间随之变大，将GOA设计在AA区，导致开口率降低，穿透率严重不足。
因此，现有技术存在缺陷，急需解决。
 技术问题
本申请提供一种显示面板，能够解决现有窄边框显示面板开口率较低，穿透率不足的问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种显示面板，包括显示区以及位于所述显示区外围的非显示区，所述显示区包括阵列分布的像素单元，所述显示区相对两侧的所述非显示区内设置有GOA总线单元；
相邻两行所述像素单元之间并排的设置有两个GOA电路单元，且并排设置的两个GOA电路单元与所述像素单元电连接；
所述GOA电路单元通过设置于所述显示区内的信号连接线与所述GOA总线单元电连接；
其中，并排设置的两个GOA电路单元共用至少一条信号连接线。
在本申请的显示面板中，所述GOA总线单元包括沿列方向延伸的至少一条信号总线，一所述信号连接线对应连接一所述信号总线。
在本申请的显示面板中，所述信号总线包括第一低频时钟信号总线、第二低频时钟信号总线，所述GOA电路单元通过第一低频时钟信号连接线和第二低频时钟信号连接线分别与所述第一低频时钟信号总线和所述第二低频时钟信号总线电连接；其中，并排设置的两个GOA电路单元共用所述第一低频时钟信号连接线和所述第二低频时钟信号连接线中的至少一种。
在本申请的显示面板中，所述信号总线包括复位信号总线，所述GOA电路单元通过复位信号连接线与所述复位信号总线电连接；其中，并排设置的两个GOA电路单元共用一条所述复位信号连接线。
在本申请的显示面板中，所述信号总线包括电源信号总线，所述GOA电路单元通过电源信号连接线与所述电源信号总线电连接；其中，并排设置的两个GOA电路单元共用一条所述电源信号连接线。
在本申请的显示面板中，并排设置的两个GOA电路单元与同一行所述像素单元电连接，或者并排设置的两个GOA电路单元与相邻两行的所述像素单元电连接。
在本申请的显示面板中，并排设置的两个GOA电路单元为第一GOA电路单元和第二GOA电路单元，所述GOA总线单元包括第一GOA总线单元和第二GOA总线单元，所述第一GOA电路单元与所述第一GOA总线单元电连接，所述第二GOA电路单元与所述第二GOA总线单元电连接。
在本申请的显示面板中，所述第一GOA总线单元和所述第二GOA总线单元中的一者包括所述第一低频时钟信号总线，另一者包括所述第二低频时钟信号总线；所述第一GOA总线单元和所述第二GOA总线单元中的一者包括所述复位信号总线，另一者包括所述电源信号总线。
在本申请的显示面板中，所述第一GOA总线单元和所述第二GOA总线单元中的所述信号总线的数量相等。
在本申请的显示面板中，所述GOA电路单元与所述信号连接线均位于相邻两行所述像素单元之间，所述GOA电路单元通过扫描线与所述像素单元电连接。
本申请还提供一种显示面板，其包括显示区以及位于所述显示区外围的非显示区，所述显示区包括阵列分布的像素单元，所述显示区相对两侧的所述非显示区内设置有GOA总线单元；
所述显示面板为双向驱动型，相邻两行所述像素单元之间并排的设置有两个GOA电路单元，且并排设置的两个GOA电路单元与所述像素单元电连接；
所述GOA电路单元通过设置于所述显示区内的信号连接线与所述GOA总线单元电连接；
其中，并排设置的两个GOA电路单元共用至少一条信号连接线。
在本申请的显示面板中，所述GOA总线单元包括沿列方向延伸的至少一条信号总线，一所述信号连接线对应连接一所述信号总线。
在本申请的显示面板中，所述信号总线包括第一低频时钟信号总线、第二低频时钟信号总线，所述GOA电路单元通过第一低频时钟信号连接线和第二低频时钟信号连接线分别与所述第一低频时钟信号总线和所述第二低频时钟信号总线电连接；其中，并排设置的两个GOA电路单元共用所述第一低频时钟信号连接线和所述第二低频时钟信号连接线中的至少一种。
在本申请的显示面板中，所述信号总线包括复位信号总线，所述GOA电路单元通过复位信号连接线与所述复位信号总线电连接；其中，并排设置的两个GOA电路单元共用一条所述复位信号连接线。
在本申请的显示面板中，所述信号总线包括电源信号总线，所述GOA电路单元通过电源信号连接线与所述电源信号总线电连接；其中，并排设置的两个GOA电路单元共用一条所述电源信号连接线。
在本申请的显示面板中，并排设置的两个GOA电路单元与同一行所述像素单元电连接，或者并排设置的两个GOA电路单元与相邻两行的所述像素单元电连接。
在本申请的显示面板中，并排设置的两个GOA电路单元为第一GOA电路单元和第二GOA电路单元，所述GOA总线单元包括第一GOA总线单元和第二GOA总线单元，所述第一GOA电路单元与所述第一GOA总线单元电连接，所述第二GOA电路单元与所述第二GOA总线单元电连接。
在本申请的显示面板中，所述第一GOA总线单元和所述第二GOA总线单元中的一者包括所述第一低频时钟信号总线，另一者包括所述第二低频时钟信号总线；所述第一GOA总线单元和所述第二GOA总线单元中的一者包括所述复位信号总线，另一者包括所述电源信号总线。
在本申请的显示面板中，所述第一GOA总线单元和所述第二GOA总线单元中的所述信号总线的数量相等。
在本申请的显示面板中，所述GOA电路单元与所述信号连接线均位于相邻两行所述像素单元之间，所述GOA电路单元通过扫描线与所述像素单元电连接。
 有益效果
本申请的有益效果为：本申请提供的显示面板，通过在相邻两行像素单元之间并排设置两个GOA电路单元，将并排设置的两个GOA电路单元与同一行像素单元电连接，采用双向驱动以提高显示面板的驱动能力；另外，本申请并排设置的两个GOA电路单元共用至少一条信号连接线与GOA总线单元连接，从而减少了显示区内信号连接线的总数量，节省的空间可以用来增大像素单元的开口率，从而可以提高显示面板的穿透率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例一提供的显示面板的结构示意图；
图2为本申请实施例二提供的显示面板的结构示意图；
图3为本申请实施例三提供的显示面板的结构示意图；
图4为本申请实施例四提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“纵向”、“横向”、“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。在本申请中，“/”表示“或者”的意思。
本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
GOA型显示面板是采用GOA电路驱动显示面板进行显示，随着高解析度的显示产品及极致窄边框的显示产品成为市场的趋势，GOA In AA型显示面板应运而生。GOA电路包括GOA总线单元(GOA Busline)和GOA电路单元（GOA Circuit），但是随着显示面板的尺寸和解析度的逐渐增大，GOA总线单元的RC（Resistance-Capacitance，阻抗）负载较重，不适合放到显示区，一般将GOA总线单元设置在显示面板的边框区，将GOA电路单元设置在显示区，以实现窄边宽。
但是，由于多级GOA电路单元设置在显示区的像素之间，且每一级GOA电路单元都对应驱动一行像素单元，因此需要在像素之间布设多条信号连接线以传递信号。由于显示面板的解析度的增大，导致GOA电路单元和信号连接线的数量也会增大，并且GOA电路单元和信号连接线也需要一定的空间，从而使像素单元的开口率被压缩，进而影响显示面板的穿透率。
基于此，本申请提供一种显示面板以解决上述缺陷。
请参照图1~图4所示，本申请的显示面板包括显示区以及位于所述显示区外围的非显示区，所述显示区包括阵列分布的像素单元，所述显示区相对两侧的所述非显示区内设置有GOA总线单元。所述显示区内相邻两行所述像素单元之间并排的设置有两个GOA电路单元以及多条信号连接线，且并排设置的两个GOA电路单元与所述像素单元电连接。
本申请的显示面板为双向驱动型，即包括两套GOA电路，每套GOA电路均包括N级GOA电路单元，其中，N为大于零的正整数。每一级GOA电路单元对应连接一条扫描线。
由于所述GOA总线单元包括多条信号总线，分别用于传输不同的驱动信号，每一级GOA电路单元都需要通过多条信号连接线分别与多条信号总线一一对应电连接。例如，GOA总线单元包括第一低频时钟信号总线、第二低频时钟信号总线、复位信号总线和电源信号总线以及多级高频时钟信号总线。所述GOA电路单元通过信号连接线与所述GOA总线单元电连接，例如，每一个GOA电路单元与GOA总线单元之间均通过第一低频时钟信号连接线、第二低频时钟信号连接线、复位信号连接线和电源信号连接以及高频时钟信号连接线实现信号的传输。
在本申请中，所述显示面板的显示区内并排设置的两个GOA电路单元共用至少一条信号连接线。从而减少了显示区内信号连接线的总数量，节省的空间可以用来增大像素单元的开口率，从而可以提高显示面板的穿透率。
以下请结合具体实施例对本申请的显示面板进行详细描述。
实施例一
请参照图1所示，为本申请实施例一提供的显示面板的结构示意图。显示面板1包括位于显示区10内阵列分布的像素单元2，以及位于相邻两行像素单元2之间的GOA电路单元3以及信号连接线4，每一级GOA电路单元3通过扫描线6与一行像素单元2电连接，GOA电路单元3用于为与之相连的像素单元2提供栅极信号。
具体地，相邻两行所述像素单元2之间沿行方向并排的设置有两个GOA电路单元，且并排设置的两个GOA电路单元与同一行所述像素单元2电连接。其中，并排设置的两个GOA电路单元分别为两套GOA电路中的同一级GOA电路单元，因此可以同时驱动同一行所述像素单元2。
进一步，并排设置的两个GOA电路单元为第一GOA电路单元31和第二GOA电路单元32，所述第一GOA电路单元31与一行像素单元2中的部分像素单元2（例如与左半边像素单元）电连接，所述第二GOA电路单元32与该行像素单元2中的剩余的像素单元2（例如与右半边像素单元）电连接。
在本实施例中，不同行的所述第一GOA电路单元31位于同一列，不同行的所述第二GOA电路单元32位于同一列，当然并不以此为限。
所述显示区10相对两侧的非显示区11内设置有GOA总线单元5，所述GOA电路单元3通过所述信号连接线4与所述GOA总线单元5电连接。所述GOA总线单元5包括沿列方向延伸的至少一条信号总线，一所述信号连接线4对应连接一所述信号总线。其中，同一行并排设置的两个GOA电路单元共用至少一条信号连接线。
具体地，所述GOA总线单元5包括第一GOA总线单元51和第二GOA总线单元52，所述第一GOA总线单元51和所述第二GOA总线单元52分别位于所述显示区10的相对两侧。且所述第一GOA电路单元31与所述第一GOA总线单元51电连接，所述第二GOA电路单元32与所述第二GOA总线单元52电连接。
其中，所述信号总线包括沿列方向延伸的第一低频时钟信号总线501、第二低频时钟信号总线502、复位信号总线503、电源信号总线504以及多条高频时钟信号总线（CK），例如CK1~CKn，n为大于或等于2的正整数，本实施例中以n等于8为例说明。对应的，所述信号连接线4包括第一低频时钟信号连接线41、第二低频时钟信号连接线42、复位信号连接线43、电源信号连接线44以及高频时钟信号连接线45。
其中，所述第一低频时钟信号总线501用于传输第一低频时钟信号（LC1），所述第二低频时钟信号总线502用于传输第二低频时钟信号（LC2），所述复位信号总线503用于传输复位信号（RST），电源信号总线504用于传输电源信号（VSS），多条所述高频时钟信号总线（CK）用于传输高频时钟信号。
在本实施例中，所述第一GOA总线单元51和所述第二GOA总线单元52中均包括所述高频时钟信号总线（CK1......CK8）、所述复位信号总线503以及所述电源信号总线504。其中，所述第一GOA总线单元51和所述第二GOA总线单元52中的一者包括所述第一低频时钟信号总线501，另一者包括所述第二低频时钟信号总线502。所述第一GOA总线单元51和所述第二GOA总线单元52中的所述信号总线的数量相等。
具体地，所述第一GOA电路单元31通过第一组所述复位信号连接线43、所述电源信号连接线44以及所述高频时钟信号连接线45分别与所述第一GOA总线单元51中的所述复位信号总线503、所述电源信号总线504以及所述高频时钟信号总线（CK1......CK8中的一条，例如CK1）一一对应的电连接。所述第二GOA电路单元32通过第二组所述复位信号连接线43、所述电源信号连接线44以及所述高频时钟信号连接线45分别与所述第二GOA总线单元52中的所述复位信号总线503、所述电源信号总线504以及所述高频时钟信号总线（CK1......CK8中的一条，例如CK1）一一对应的电连接。
其中，所述第一GOA电路单元31与所述第二GOA电路单元32共用所述第一低频时钟信号连接线41和所述第二低频时钟信号连接线42中的至少一种。
在本实施例中，所述第一GOA电路单元31与所述第二GOA电路单元32共用所述第一低频时钟信号连接线41并通过所述第一低频时钟信号连接线41与所述第一低频时钟信号总线501电连接；并且，所述第一GOA电路单元31与所述第二GOA电路单元32共用所述第二低频时钟信号连接线42并通过所述第二低频时钟信号连接线42与所述第二低频时钟信号总线502电连接。也就是说，所述第一低频时钟信号总线501通过所述第一低频时钟信号连接线41分别向所述第一GOA电路单元31和所述第二GOA电路单元32传输第一低频时钟信号（LC1），所述第二低频时钟信号总线502通过所述第二低频时钟信号连接线42分别向所述第一GOA电路单元31和所述第二GOA电路单元32传输第二低频时钟信号（LC2）。
当然，在其他实施例中，所述第一GOA电路单元31与所述第二GOA电路单元32可以共用所述第一低频时钟信号连接线41和所述第二低频时钟信号连接线42中的一种。
传统显示面板中由于第一GOA总线单元和第二GOA总线单元中均包括第一低频时钟信号总线和第二低频时钟信号总线以及与之对应的信号连接线，因此使得显示面板的边框较宽以及像素的开口率和穿透率降低。而本申请通过上述设计，在显示区两侧的第一GOA总线单元和第二GOA总线单元中分别减少了一条信号总线，从而减小显示面板的边框，并且还减小了显示区内信号连接线的数量，进而增大了像素的开口率和穿透率。
在本实施例中，两套GOA电路中的同一级GOA电路单元对应连接同一条扫描线，从而实现两套GOA电路共同驱动同一行像素单元。由于显示面板的解析度及尺寸的增大，信号的衰减较为严重，而采用双向驱动可以很好的解决此问题，提升显示面板的驱动力。
实施例二
请参照图2所示，为本申请实施例二提供的显示面板的结构示意图。本实施例的显示面板与上述实施例一中的显示面板的结构相同/相似，区别仅在于：本实施例的显示面板中并排设置的两个GOA电路单元3与相邻两行的所述像素单元2电连接。
具体地，沿行的方向并排设置的第一GOA电路单元31和第二GOA电路单元32在级数上相差一级，例如，所述第一GOA电路单元31为第一套GOA电路中的第N级GOA电路单元，则第二GOA电路单元32为第二套GOA电路中的第N+1级GOA电路单元，N为大于0的正整数。因此位于同一行并排设置的所述第一GOA电路单元31和所述第二GOA电路单元32用于分别驱动相邻行的所述像素单元2。
进一步，并排设置的所述第一GOA电路单元31与所述第二GOA电路单元32中，所述第一GOA电路单元31与一行像素单元2中的部分像素单元2（例如与左半边像素单元）电连接，所述第二GOA电路单元32与上/下一行像素单元2中的部分像素单元2（例如与右半边像素单元）电连接。
在本实施例中，并排设置的两个GOA电路单元3电连接至相邻两条扫描线上，从而实现两套GOA电路共同驱动同一行像素单元。由于显示面板的解析度及尺寸的增大，信号的衰减较为严重，而采用双向驱动可以很好的解决此问题，提升显示面板的驱动力。
本实施例的显示面板通过上述设计，在显示区两侧的第一GOA总线单元和第二GOA总线单元中分别减少了一条信号总线，从而减小显示面板的边框，并且还减小了显示区内信号连接线的数量，进而增大了像素的开口率和穿透率。
实施例三
请参照图3所示，为本申请实施例三提供的显示面板的结构示意图。本实施例的显示面板与上述实施例一中的显示面板的结构相同/相似，区别仅在于：本实施例的显示面板中并排设置的两个GOA电路单元3共用一条所述复位信号连接线43，并且，所述第一GOA总线单元51和所述第二GOA总线单元52中的一者包括复位信号总线503，另一者不包括复位信号总线503。
也就是说，本实施例中，所述复位信号总线503通过共用的一条所述复位信号连接线43分别向所述第一GOA电路单元31和所述第二GOA电路单元32传输复位信号（RST）；所述第一低频时钟信号总线501通过共用的一条所述第一低频时钟信号连接线41分别向所述第一GOA电路单元31和所述第二GOA电路单元32传输第一低频时钟信号（LC1）；所述第二低频时钟信号总线502通过共用的一条所述第二低频时钟信号连接线42分别向所述第一GOA电路单元31和所述第二GOA电路单元32传输第二低频时钟信号（LC2）。
本实施例的显示面板在第一GOA总线单元和第二GOA总线单元中分别减少了一条信号总线的基础上，又在第一GOA总线单元或第二GOA总线单元中减少了一条复位信号总线，因此进一步减小显示面板的边框，并且还减小了显示区内信号连接线的数量，从而进一步增大了像素的开口率和穿透率。
实施例四
请参照图4所示，为本申请实施例四提供的显示面板的结构示意图。本实施例的显示面板与上述实施例三中的显示面板的结构相同/相似，区别仅在于：本实施例的显示面板中并排设置的两个GOA电路单元3共用一条电源信号连接线44，并且，所述第一GOA总线单元51和所述第二GOA总线单元52中的一者包括电源信号总线504，另一者不包括电源信号总线504。
也就是说，本实施例中，所述电源信号总线504通过共用的一条所述电源信号连接线44分别向所述第一GOA电路单元31和所述第二GOA电路单元32传输电源信号（VSS）；所述复位信号总线503通过共用的一条所述复位信号连接线43分别向所述第一GOA电路单元31和所述第二GOA电路单元32传输复位信号（RST）；所述第一低频时钟信号总线501通过共用的一条所述第一低频时钟信号连接线41分别向所述第一GOA电路单元31和所述第二GOA电路单元32传输第一低频时钟信号（LC1）；所述第二低频时钟信号总线502通过共用的一条所述第二低频时钟信号连接线42分别向所述第一GOA电路单元31和所述第二GOA电路单元32传输第二低频时钟信号（LC2）。
进一步，所述第一GOA总线单元51和所述第二GOA总线单元52中的一者包括所述复位信号总线503，另一者包括所述电源信号总线504。
本实施例的显示面板在上述实施例三的基础上，又在第一GOA总线单元或第二GOA总线单元中减少了一条电源信号总线，因此相较于上述实施例三可以进一步减小显示面板的边框，并且还减小了显示区内信号连接线的数量，从而更进一步增大了像素的开口率和穿透率。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括显示区以及位于所述显示区外围的非显示区，所述显示区包括阵列分布的像素单元，所述显示区相对两侧的所述非显示区内设置有GOA总线单元；
    相邻两行所述像素单元之间并排的设置有两个GOA电路单元，且并排设置的两个GOA电路单元与所述像素单元电连接；
    所述GOA电路单元通过设置于所述显示区内的信号连接线与所述GOA总线单元电连接；
    其中，并排设置的两个GOA电路单元共用至少一条信号连接线。
  2. 根据权利要求1所述的显示面板，其中，所述GOA总线单元包括沿列方向延伸的至少一条信号总线，一所述信号连接线对应连接一所述信号总线。
  3. 根据权利要求2所述的显示面板，其中，所述信号总线包括第一低频时钟信号总线、第二低频时钟信号总线，所述GOA电路单元通过第一低频时钟信号连接线和第二低频时钟信号连接线分别与所述第一低频时钟信号总线和所述第二低频时钟信号总线电连接；其中，并排设置的两个GOA电路单元共用所述第一低频时钟信号连接线和所述第二低频时钟信号连接线中的至少一种。
  4. 根据权利要求2所述的显示面板，其中，所述信号总线包括复位信号总线，所述GOA电路单元通过复位信号连接线与所述复位信号总线电连接；其中，并排设置的两个GOA电路单元共用一条所述复位信号连接线。
  5. 根据权利要求2所述的显示面板，其中，所述信号总线包括电源信号总线，所述GOA电路单元通过电源信号连接线与所述电源信号总线电连接；其中，并排设置的两个GOA电路单元共用一条所述电源信号连接线。
  6. 根据权利要求1所述的显示面板，其中，并排设置的两个GOA电路单元与同一行所述像素单元电连接，或者并排设置的两个GOA电路单元与相邻两行的所述像素单元电连接。
  7. 根据权利要求1所述的显示面板，其中，并排设置的两个GOA电路单元为第一GOA电路单元和第二GOA电路单元，所述GOA总线单元包括第一GOA总线单元和第二GOA总线单元，所述第一GOA电路单元与所述第一GOA总线单元电连接，所述第二GOA电路单元与所述第二GOA总线单元电连接。
  8. 根据权利要求7所述的显示面板，其中，所述第一GOA总线单元和所述第二GOA总线单元中的一者包括所述第一低频时钟信号总线，另一者包括所述第二低频时钟信号总线；所述第一GOA总线单元和所述第二GOA总线单元中的一者包括所述复位信号总线，另一者包括所述电源信号总线。
  9. 根据权利要求8所述的显示面板，其中，所述第一GOA总线单元和所述第二GOA总线单元中的所述信号总线的数量相等。
  10. 根据权利要求1所述的显示面板，其中，所述GOA电路单元与所述信号连接线均位于相邻两行所述像素单元之间，所述GOA电路单元通过扫描线与所述像素单元电连接。
  11. 一种显示面板，其包括显示区以及位于所述显示区外围的非显示区，所述显示区包括阵列分布的像素单元，所述显示区相对两侧的所述非显示区内设置有GOA总线单元；
    所述显示面板为双向驱动型，相邻两行所述像素单元之间并排的设置有两个GOA电路单元，且并排设置的两个GOA电路单元与所述像素单元电连接；
    所述GOA电路单元通过设置于所述显示区内的信号连接线与所述GOA总线单元电连接；
    其中，并排设置的两个GOA电路单元共用至少一条信号连接线。
  12. 根据权利要求11所述的显示面板，其中，所述GOA总线单元包括沿列方向延伸的至少一条信号总线，一所述信号连接线对应连接一所述信号总线。
  13. 根据权利要求12所述的显示面板，其中，所述信号总线包括第一低频时钟信号总线、第二低频时钟信号总线，所述GOA电路单元通过第一低频时钟信号连接线和第二低频时钟信号连接线分别与所述第一低频时钟信号总线和所述第二低频时钟信号总线电连接；其中，并排设置的两个GOA电路单元共用所述第一低频时钟信号连接线和所述第二低频时钟信号连接线中的至少一种。
  14. 根据权利要求12所述的显示面板，其中，所述信号总线包括复位信号总线，所述GOA电路单元通过复位信号连接线与所述复位信号总线电连接；其中，并排设置的两个GOA电路单元共用一条所述复位信号连接线。
  15. 根据权利要求12所述的显示面板，其中，所述信号总线包括电源信号总线，所述GOA电路单元通过电源信号连接线与所述电源信号总线电连接；其中，并排设置的两个GOA电路单元共用一条所述电源信号连接线。
  16. 根据权利要求11所述的显示面板，其中，并排设置的两个GOA电路单元与同一行所述像素单元电连接，或者并排设置的两个GOA电路单元与相邻两行的所述像素单元电连接。
  17. 根据权利要求11所述的显示面板，其中，并排设置的两个GOA电路单元为第一GOA电路单元和第二GOA电路单元，所述GOA总线单元包括第一GOA总线单元和第二GOA总线单元，所述第一GOA电路单元与所述第一GOA总线单元电连接，所述第二GOA电路单元与所述第二GOA总线单元电连接。
  18. 根据权利要求17所述的显示面板，其中，所述第一GOA总线单元和所述第二GOA总线单元中的一者包括所述第一低频时钟信号总线，另一者包括所述第二低频时钟信号总线；所述第一GOA总线单元和所述第二GOA总线单元中的一者包括所述复位信号总线，另一者包括所述电源信号总线。
  19. 根据权利要求18所述的显示面板，其中，所述第一GOA总线单元和所述第二GOA总线单元中的所述信号总线的数量相等。
  20. 根据权利要求11所述的显示面板，其中，所述GOA电路单元与所述信号连接线均位于相邻两行所述像素单元之间，所述GOA电路单元通过扫描线与所述像素单元电连接。
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