WO2024031760A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024031760A1
WO2024031760A1 PCT/CN2022/116439 CN2022116439W WO2024031760A1 WO 2024031760 A1 WO2024031760 A1 WO 2024031760A1 CN 2022116439 W CN2022116439 W CN 2022116439W WO 2024031760 A1 WO2024031760 A1 WO 2024031760A1
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WO
WIPO (PCT)
Prior art keywords
pull
transistor
control signal
scan
display panel
Prior art date
Application number
PCT/CN2022/116439
Other languages
English (en)
French (fr)
Inventor
曹海明
田超
艾飞
刘广辉
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US17/915,517 priority Critical patent/US20240296767A1/en
Publication of WO2024031760A1 publication Critical patent/WO2024031760A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel and a display device.
  • Array substrate gate drive technology (Gate Driver On Array, GOA) is a driving method that integrates the gate drive circuit on the array substrate of the display panel to achieve progressive scanning.
  • This driving technology can eliminate the need for gate drivers, has the advantages of reducing production costs and achieving narrow bezel designs for panels, and is used by a variety of displays.
  • the RC of the scan line Loading (resistance-capacitance load) continues to increase, and the transmission loss of the scanning signal output by the GOA increases, causing the falling edge of the scanning signal to seriously deteriorate, reducing the pixel charging time and increasing the risk of pixel mischarging.
  • This application provides a display panel and a display device to solve the technical problems of serious deterioration of the falling edge of the scanning signal due to RC Loading, reduction of pixel charging time, and increased risk of pixel mischarging.
  • This application provides a display panel, which includes:
  • a plurality of scan lines, the plurality of scan lines are arranged at intervals along the first direction;
  • At least one pull-down circuit is connected to the n-th scan line, and the pull-down circuit is used to pull down the potential of the n-th scan line;
  • the pull-down circuit includes a forward-scan pull-down unit and/or a reverse-scan pull-down unit;
  • the forward-scan pull-down unit is connected to the n+mth level scanning signal, the first control signal and the reference low-level signal, and is connected with the The nth scan line is connected;
  • the reverse sweep pull-down unit is connected to the n-mth level scan signal, the second control signal and the reference low level signal, and is connected to the nth scan line;
  • n and m are both An integer greater than zero, and n ⁇ 2, n>m.
  • the positive scan pull-down unit includes a first transistor and a second transistor
  • the gate of the first transistor is connected to one of the n+mth level scanning signal and the first control signal, and the source of the first transistor and the drain of the second transistor are connected together, the drain of the first transistor is connected to the nth scan line; the gate of the second transistor is connected to the n+mth level scan signal and the first control signal.
  • the source of the second transistor is connected to the reference low level signal.
  • the reverse sweep pull-down unit includes a third transistor and a fourth transistor
  • the gate of the third transistor is connected to one of the n-mth level scanning signal and the second control signal, and the source of the third transistor and the drain of the fourth transistor are connected at Together, the drain of the third transistor is connected to the nth scan line; the gate of the fourth transistor is connected to the other one of the n-mth level scan signal and the second control signal, The source of the fourth transistor is connected to the reference low level signal.
  • the display panel has a display area, and the pull-down circuit is provided in the display area.
  • the display panel includes a plurality of pull-down circuits, each pull-down circuit is connected to one of the scan lines, and each of the scan lines is connected to at least one of the pull-down circuits. Circuit connection.
  • the pull-down circuits corresponding to two adjacent scan lines are arranged in a staggered manner along the first direction.
  • each scan line is connected to two pull-down circuits, and along the extension direction of the scan line, the pull-down circuit connected to the odd-numbered row of scan lines Located between the pull-down circuits connected to the scan lines of the even-numbered rows.
  • the display panel along the direction in which the scan line extends, also has a first non-display area and a second non-display area located on both sides of the display area; the display The panel further includes a first GOA circuit and a second GOA circuit, the first GOA circuit is disposed in the first non-display area, and the second GOA circuit is disposed in the second non-display area;
  • each of the scan lines is connected to two pull-down circuits, and along the extension direction of the scan lines, the pull-down circuits connected to the scan lines in odd-numbered rows are located in all the pull-down circuits connected to the scan lines in even-numbered rows. between the pull-down circuits described above.
  • the display panel further includes at least one first control signal line and at least one second control signal line, and the first control signal line is used to transmit the first control signal.
  • the second control signal line is used to transmit the second control signal; both the first control signal line and the second control signal line extend along the first direction, and each pull-down circuit is connected to The first control signal line and the second control signal line are connected.
  • the display panel along the direction in which the scan line extends, has a display area and a first non-display area and a second non-display area located on both sides of the display area;
  • the display panel further includes a first GOA circuit located in the first non-display area, and the pull-down circuit is located in the second non-display area.
  • this application also provides a display device.
  • the display device includes a display panel and a driving device.
  • the display panel is the display panel described in any one of the above.
  • the driving device outputs the first control signal and a driving device.
  • the second control signal is sent to the display panel.
  • the display panel includes a plurality of scan lines and at least one pull-down unit.
  • a plurality of the scan lines are arranged at intervals along the first direction;
  • the pull-down circuit is connected to the n-th scan line, and the pull-down circuit is used to pull down the potential of the n-th scan line;
  • the pull-down circuit includes A forward scan pull-down unit and/or a reverse scan pull-down unit;
  • the forward scan pull-down unit is connected to the n+mth level scan signal, the first control signal and the reference low level signal, and is connected to the nth scan line;
  • the reverse sweep pull-down unit is connected to the n-mth level scanning signal, the second control signal and the reference low level signal, and is connected to the nth scanning line;
  • n and m are both integers greater than zero, and n ⁇ 2, n>m.
  • this application can further pull down the potential of the n-th scan line, improve the uniformity of the falling edges of the scan signals in the display panel, increase the charging time of the pixels, and avoid errors. Charge.
  • the pull-down circuit can include both a forward-scan pull-down unit and a reverse-scan pull-down unit, the display panel can realize forward scanning and reverse scanning, meeting the application scenario where the same screen is compatible with both forward and reverse scanning.
  • Figure 1 is a first structural schematic diagram of a display panel provided by this application.
  • Figure 2 is a schematic structural diagram of the pull-down circuit provided by this application.
  • Figure 3 is a signal timing diagram when the existing display panel provided by this application is working
  • Figure 4 is a signal timing diagram when the display panel provided by this application is working
  • Figure 5 is a first circuit schematic diagram of the pull-down circuit provided by this application.
  • Figure 6 is a signal timing diagram of the pull-down circuit shown in Figure 5 when the display panel is scanning in the forward direction;
  • Figure 7 is a signal timing diagram of the pull-down circuit shown in Figure 5 when the display panel is scanned in reverse;
  • Figure 8 is a second circuit schematic diagram of the pull-down circuit provided by this application.
  • FIG. 9 is a second structural schematic diagram of the display panel provided by this application.
  • Figure 10 is a third circuit schematic diagram of the pull-down circuit provided by this application.
  • Figure 11 is a signal timing diagram of the pull-down circuit shown in Figure 10 when the display panel is scanning in the forward direction;
  • Figure 12 is a signal timing diagram of the pull-down circuit shown in Figure 10 when the display panel is scanned in reverse;
  • Figure 13 is a fourth circuit schematic diagram of the pull-down circuit provided by this application.
  • Figure 14 is a third structural schematic diagram of the display panel provided by this application.
  • Figure 15 is a schematic structural diagram of a display device provided by this application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first”, “second”, etc. may explicitly or implicitly include one or more of the described features, and therefore cannot be construed as a limitation of the present application.
  • the terms “connected” and “connected” should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection; it can be a direct connection or a connection through The intermediate medium is indirectly connected, which can be the internal connection between two components.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • This application provides a display panel and a display device, which are described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.
  • Figure 1 is a first structural schematic diagram of a display panel provided by this application
  • Figure 2 is a schematic structural diagram of a pull-down circuit provided by this application.
  • the display panel 100 includes a plurality of scan lines 20 and at least one pull-down circuit 10 .
  • the plurality of scan lines 20 are arranged at intervals along the first direction Y.
  • the plurality of scan lines 20 are respectively the first scan line G1, the second scan line G2, the third scan line G3, the fourth scan line G4, and the n-1th scan line.
  • Gn-1, the n-th scan line Gn, the n+1-th scan line Gn+1, the n+2-th scan line Gn+2, etc. will not be described one by one here.
  • the pull-down circuit 10 is connected to the n-th scanning line Gn.
  • the pull-down circuit 10 is used to pull down the potential of the n-th scanning line Gn.
  • the pull-down circuit 10 includes a forward-scan pull-down unit 11 and/or a reverse-scan pull-down unit 12 .
  • the positive scan pull-down unit 11 receives the n+m-th level scan signal G(n+m), the first control signal U2D and the reference low-level signal VGL, and is connected to the n-th scan line Gn.
  • the antiscan pull-down unit 12 receives the n-mth level scanning signal G(n-m), the second control signal D2U and the reference low-level signal VGL, and is connected to the nth scanning line Gn.
  • n and m are both integers greater than zero, and n ⁇ 2, n>m.
  • the embodiment of the present application can further pull down the potential of the n-th scan line Gn, improve the uniformity of the falling edges of the scan signals in the display panel 100, and increase the pixel charging time and avoid incorrect charging.
  • the pull-down circuit 10 can include both a forward-scan pull-down unit 11 and a reverse-scan pull-down unit 12, the display panel 100 can implement forward scanning and reverse scanning, satisfying application scenarios where the same screen is compatible with both forward and reverse scanning.
  • the pull-down circuit 10 may include only the forward-scan pull-down unit 11 or only the reverse-scan pull-down unit 12 to meet the requirements of the screen. Formal or reverse installation is required.
  • Figure 3 is a signal timing diagram when the existing display panel provided by this application is working
  • Figure 4 is a signal timing diagram when the display panel provided by this application is working.
  • the scanning signals at all levels are turned on line by line.
  • the n-1th level scanning signal G(n-1) changes from high potential VGH to low potential VGL
  • the nth level scanning signal G(n) changes from low potential VGL to high potential VGH
  • the nth level scanning signal G(n) changes from low potential VGL to high potential VGH
  • the scanning signal G(n) changes from the high potential VGH to the low potential VGL
  • the n+1th level scanning signal G(n+1) changes from the low potential VGL to the high potential VGH.
  • the RC Loading of the scan line 20 continues to increase, and the transmission loss of the scan signal increases, resulting in serious deterioration of the falling edges of the scan signals at all levels.
  • the n-1th level scanning signal G(n-1) changes from high potential VGH to low potential VGL
  • the n-1th level scanning signal G(n-1) has a first falling edge t1
  • the nth level scanning signal G(n-1) changes from high potential VGH to low potential VGL
  • the level scanning signal G(n) changes from the high potential VGH to the low potential VGL
  • the nth level scanning signal G(n) has a second falling edge t2.
  • the slopes of the falling edge t1 and the falling edge t2 are gentle, indicating that the n-1th level scanning signal G(n-1) and the nth level scanning signal G(n) are pulled down slowly from the high potential VGH to the low potential VGL.
  • the pull-down circuit 10 switches on the n+1-th level scanning signal G(n+1 ), the first control signal U2D, the n-1th level scanning signal G(n-1) and the second control signal D2U, further pull down the nth level scanning signal G(n); at this time, the n+1th level scanning signal G(n-1) is further pulled down.
  • the level scanning signal G(n+1) has a third falling edge t4.
  • the pull-down circuit 10 further pulls down the potential of the n-1th level scanning signal G(n-1); thus When , the n-th level scanning signal G(n) has the fourth falling edge t3.
  • the duration of the third falling edge t4 and the fourth falling edge t3 is short, and the pull-down is relatively rapid.
  • the pull-down circuit 10 can be disposed in the display area of the display panel 100 or in the non-display area of the display panel 100 . Specifically, the pull-down circuit 10 can be set according to the specifications of the display panel 100 .
  • the display panel 100 has a display area AA.
  • a plurality of scan lines 20 are provided in the display area AA.
  • the pull-down circuit 10 is also provided in the display area AA.
  • the pull-down circuit 10 is integrated and arranged in the display area AA, which can effectively reduce the frame of the display panel 100 and facilitate the narrowing of the frame.
  • the display panel 100 may include multiple pull-down circuits 10 .
  • Each pull-down circuit 10 is connected to a scan line 20 .
  • Each scan line 20 is connected to at least one pull-down circuit 10 to achieve uniformity of the falling edges of the scan signals on each scan line 20 .
  • the number and position of the pull-down circuits 10 shown in FIG. 1 are only examples and cannot be understood as limitations of the present application.
  • the pull-down circuits 10 correspondingly connected to two adjacent scan lines 20 are staggered along the first direction Y.
  • first direction Y For example, when each scan line 20 is connected to a pull-down circuit 10, multiple pull-down circuits 10 connected to the odd-numbered row scan lines 20 are arranged in a column along the first direction Y, and multiple pull-down circuits 10 connected to the even-numbered row scan lines 20 are arranged in a row.
  • the circuits 10 are arranged in another column along the first direction Y.
  • the display area AA of the display panel 100 is also provided with a pixel circuit (not shown in the figure), the wiring space in the display area AA is limited.
  • the pull-down circuits 10 connected to two adjacent scan lines 20 are staggered, which can effectively utilize the wiring space in the display area AA, while improving the uniformity of the distribution of multiple pull-down circuits 10 in the plane and avoiding the impact
  • the display screen of the display panel 100 is displayed.
  • the display panel 100 may further include a GOA circuit. Specifically, when the display panel 100 adopts single-sided driving, the display panel 100 may only include the first GOA circuit 31 or the second GOA circuit 32; when the display panel 100 adopts double-sided driving, the display panel 100 may include the first GOA at the same time. circuit 31 and the second GOA circuit 32; this application does not specifically limit this.
  • the GOA circuit is used to generate scanning signals at various levels and output the scanning signals to corresponding scanning lines 20 .
  • the GOA circuit is used to output the n-1th level scanning signal G(n-1) to the n-1th scanning line Gn-1, and output the nth level scanning signal G(n) to the nth scanning line Gn.
  • the n+1th level scanning signal G(n+1) is output to the n+1th scanning line Gn+1.
  • the display panel 100 when the display panel 100 adopts double-sided driving, along the direction in which the scan line 20 extends, the display panel 100 also has a first non-display area NA1 and a second non-display area NA1 located on both sides of the display area AA. Display area NA2.
  • the first GOA circuit 31 is provided in the first non-display area NA1.
  • the second GOA circuit 32 is provided in the second non-display area NA2.
  • the pull-down circuit 10 can be connected to the scanning signal output end of the GOA circuit (not shown in the figure) to access the n+mth level scanning signal G(n+m) and the n-mth level scanning signal.
  • Signal G(n-m) the n+mth level scanning signal.
  • the pull-down circuit 10 can also access the n+mth level scanning signal G(n+m) and the n-mth level scanning signal G(n-m) by being connected to the corresponding scanning line 20 .
  • the pull-down circuit 10 is connected to the n-th scanning line Gn, and can access the n-th level scanning signal G(n), which will not be described again here.
  • the display panel 100 generally uses a progressive scanning method to charge pixels. Therefore, when the n-th level scanning signal G(n) is a high-level signal, the n-1-th level scanning signal G(n-1) needs to be pulled down; when the n+1-th level scanning signal G(n+1) When it is a high-level signal, it is necessary to pull down the n-th level scanning signal G(n). Therefore, pull-down modules are provided in both the first GOA circuit 31 and the second GOA circuit 32 .
  • the pull-down modules in the first GOA circuit 31 and the second GOA circuit 32 are independent of each other from the pull-down circuit 10 in the solution of this application, but both are used to pull down the corresponding scanning signals.
  • n and m are both integers greater than zero.
  • the value of n can be determined according to the driving architecture of the display panel 100 and the number of scan lines.
  • the value of m can be determined based on the cascade relationship between the GOA units in the GOA circuit (first GOA circuit 31/second GOA circuit 32). For example, m can be 1, 2, 3, 4, etc., which will not be described again here.
  • the display panel 100 further includes at least one first control signal line 41 and at least one second control signal line 42 .
  • the first control signal line 41 is used to transmit the first control signal U2D.
  • the second control signal line 42 is used to transmit the second control signal D2U.
  • the first control signal line 41 and the second control signal line 42 both extend along the first direction Y, and each pull-down circuit 10 is connected to the first control signal line 41 and the second control signal line 42 respectively.
  • a first control signal line 41 and a second control signal line 42 can be provided corresponding to each column of pull-down circuits 10;
  • a first control signal line 41 and a second control signal line 42 are provided between the column pull-down circuits 10.
  • the pull-down circuits 10 of two adjacent columns are connected to the same first control signal line 41 and the same second control signal line 42. connect.
  • the wiring in the display panel 100 can be regularized to avoid signal crosstalk.
  • the reference low-level signal VGL is also a required signal in the display panel 100 , and the pull-down circuit 10 can be connected to the original transmission line of the reference low-level signal VGL in the display panel 100 .
  • the reference low level signal VGL required by the signal line transmission pull-down circuit 10 can also be additionally set.
  • each scan line 20 may be connected to two pull-down circuits 10 .
  • the pull-down circuits 10 connected to the odd-numbered row scan lines 20 are located between the pull-down circuits 10 connected to the even-numbered row scan lines 20 .
  • each scan line 20 is connected to two pull-down circuits 10, so that the potential of the scan line 20 can be pulled down at different positions of the scan line 20, while combining the first GOA circuit 31 and the second GOA circuit 32.
  • the pull-down effect can further improve the uniformity of the falling edges of the scanning signals in the display panel 100 .
  • arranging the pull-down circuits 10 connected to the odd-numbered row scan lines 20 between the pull-down circuits 10 connected to the even-numbered row scan lines 20 can regularize the in-plane wiring and improve the wiring space utilization.
  • the display panel 100 further includes a first connection line 43 and a second connection line 44 .
  • the extension direction of the first connection line 43 and the second connection line 44 is the same as the extension direction of the scan line 20 .
  • the first connection line 43 and the second connection line 44 may be provided in the display area AA or in the lower frame non-display area of the display panel 100 .
  • the first connection line 43 is connected to the plurality of first control signal lines 41, and the second connection line 44 Connected to a plurality of second control signal lines 42 . Therefore, the first control signal U2D can be transmitted to the plurality of first control signal lines 41 through the first connection line 43 , and the second control signal D2U can be transmitted to the plurality of second control signal lines 42 through the second connection line 44 .
  • Figure 5 is a first circuit schematic diagram of the pull-down circuit provided by this application.
  • the forward scan pull-down unit 11 includes a first transistor T1 and a second transistor T2.
  • the gate of the first transistor T1 is connected to the n+mth level scanning signal G(n+m).
  • the source of the first transistor T1 and the drain of the second transistor T2 are connected together.
  • the drain of the first transistor T1 is connected to the n-th scanning line Gn.
  • the gate of the second transistor T2 is connected to the first control signal U2D.
  • the source of the second transistor T2 is connected to the reference low level signal VGL.
  • the gate of the first transistor T1 is connected to the n+1th level scanning signal G(n+1).
  • the forward scan pull-down unit 11 is used to pull down the potential of the nth scan line Gn when the display panel 100 performs forward scan.
  • the reverse sweep pull-down unit 12 includes a third transistor T3 and a fourth transistor T4.
  • the gate of the third transistor T3 is connected to the n-mth level scanning signal G(n-m).
  • the source of the third transistor T3 and the drain of the fourth transistor T4 are connected together.
  • the drain of the third transistor T3 is connected to the n-th scanning line Gn.
  • the gate of the fourth transistor T4 is connected to the second control signal D2U.
  • the source of the fourth transistor T4 is connected to the reference low level signal VGL.
  • the reverse scan pull-down unit 12 is used to pull down the potential of the nth scan line Gn when the display panel 100 performs reverse scan.
  • the transistors used in all embodiments of the present application can be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, their source and drain The poles are interchangeable. In the embodiment of the present application, in order to distinguish the two electrodes of the transistor except the gate electrode, one electrode is called the source electrode and the other electrode is called the drain electrode. According to the shape in the attached figure, the middle terminal of the switching transistor is the gate, the signal input terminal is the source, and the output terminal is the drain. In addition, the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors.
  • the P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level.
  • the N-type transistor is when the gate is at a high level. It is turned on when the gate is high and turned off when the gate is low.
  • transistors in the following embodiments of the present application are all described using N-type transistors as examples, but this should not be understood as limiting the present application.
  • FIG. 6 is a signal timing diagram of the pull-down circuit shown in FIG. 5 when the display panel is scanning in the forward direction.
  • the first control signal U2D remains a high-level signal, and the second transistor T2 is turned on; the second control signal D2U remains a low-level signal, and the fourth transistor T4 is turned off. That is, during forward scanning, the forward scanning pull-down unit 11 is in the working state, and the reverse scanning pull-down unit 12 is in the non-working state.
  • the GOA circuit When the GOA circuit outputs a high-level n-th level scanning signal G(n) to the n-th scanning line Gn, the pixels connected to the n-th scanning line Gn begin to charge. Next, when the GOA circuit outputs the high-level n+1th level scanning signal G(n+1) to the n+1th scanning line Gn+1, the pixel connected to the n+1th scanning line Gn+1 Charging begins.
  • the n+1th level scan signal G(n+1) is high level
  • the first transistor T1 is turned on, and the reference low level signal VGL is transmitted to the nth scan line Gn via the second transistor T2 and the first transistor T1. This further pulls down the potential of the nth scan line Gn, improves the uniformity of the falling edge of the scan signal on the nth scan line Gn, increases the charging time of the pixel, and avoids mischarging.
  • Figure 7 is a signal timing diagram of the pull-down circuit shown in Figure 5 when the display panel is scanned in reverse direction.
  • the first control signal U2D remains a low-level signal, and the second transistor T2 is turned off; the second control signal D2U remains a high-level signal, and the fourth transistor T4 is turned on. That is, during reverse scanning, the forward scanning pull-down unit 11 is in the non-working state, and the reverse scanning pull-down unit 12 is in the working state.
  • the GOA circuit When the GOA circuit outputs a high-level n-th level scanning signal G(n) to the n-th scanning line Gn, the pixels connected to the n-th scanning line Gn begin to charge. Next, when the GOA circuit outputs the high-level n-1th level scanning signal G(n-1) to the n-1th scanning line Gn-1, the pixel connected to the n-1th scanning line Gn-1 Charging begins.
  • the n-1th level scan signal G(n-1) is high level
  • the third transistor T3 is turned on, and the reference low-level signal VGL is transmitted to the nth scan line Gn via the fourth transistor T4 and the third transistor T3. This further pulls down the potential of the nth scan line Gn, improves the uniformity of the falling edge of the scan signal on the nth scan line Gn, increases the charging time of the pixel, and avoids mischarging.
  • Figure 8 is a second circuit schematic diagram of the pull-down circuit provided by this application.
  • the difference from the pull-down circuit 10 shown in FIG. 5 is at least that in the embodiment of the present application, the gate of the first transistor T1 is connected to the first control signal U2D.
  • the source of the first transistor T1 and the drain of the second transistor T2 are connected together.
  • the drain of the first transistor T1 is connected to the n-th scanning line Gn.
  • the gate of the second transistor T2 is connected to the n+mth level scanning signal G(n+m).
  • the source of the second transistor T2 is connected to the reference low level signal VGL.
  • the gate of the second transistor T2 is connected to the n+1th level scanning signal G(n+1).
  • the forward scan pull-down unit 11 is used to pull down the potential of the nth scan line Gn when the display panel 100 performs forward scan.
  • the gate of the third transistor T3 is connected to the second control signal D2U.
  • the source of the third transistor T3 and the drain of the fourth transistor T4 are connected together.
  • the drain of the third transistor T3 is connected to the n-th scanning line Gn.
  • the gate of the fourth transistor T4 is connected to the n-mth level scanning signal G(n-m).
  • the source of the fourth transistor T4 is connected to the reference low level signal VGL.
  • the reverse scan pull-down unit 12 is used to pull down the potential of the nth scan line Gn when the display panel 100 performs reverse scan.
  • FIG. 9 is a second structural schematic diagram of the display panel provided by the present application.
  • the pull-down circuit 10 is connected to the n+1th scan line Gn+1 to pull down the potential of the n+1th scan line Gn+1, the pull-down circuit 10 is connected to the n-1th scan line Gn-1. , to access the n-1th level scanning signal G(n-1); at the same time, the pull-down circuit 10 is connected to the n+3rd scanning line Gn+3 to access the n+3rd level scanning signal G(n+ 3).
  • Figure 10 is a third circuit schematic diagram of the pull-down circuit provided by this application.
  • the gate of the first transistor T1 is connected to the n+2th level scanning signal G(n+2).
  • the source of the first transistor T1 and the drain of the second transistor T2 are connected together.
  • the drain of the first transistor T1 is connected to the n-th scanning line Gn.
  • the gate of the second transistor T2 is connected to the first control signal U2D.
  • the source of the second transistor T2 is connected to the reference low level signal VGL.
  • the gate of the third transistor T3 is connected to the n-2th level scanning signal G(n-2).
  • the source of the third transistor T3 and the drain of the fourth transistor T4 are connected together.
  • the drain of the third transistor T3 is connected to the n-th scanning line Gn.
  • the gate of the fourth transistor T4 is connected to the second control signal D2U.
  • the source of the fourth transistor T4 is connected to the reference low level signal VGL.
  • FIG. 11 is a signal timing diagram of the pull-down circuit shown in FIG. 10 when the display panel is scanning in the forward direction.
  • the first control signal U2D remains a high-level signal, and the second transistor T2 is turned on; the second control signal D2U remains a low-level signal, and the fourth transistor T4 is turned off. That is, during forward scanning, the forward scanning pull-down unit 11 is in the working state, and the reverse scanning pull-down unit 12 is in the non-working state.
  • the GOA circuit When the GOA circuit outputs a high-level n-th level scanning signal G(n) to the n-th scanning line Gn, the pixels connected to the n-th scanning line Gn begin to charge. Next, when the GOA circuit outputs the high-level n+2-th level scanning signal G(n+2) to the n+2-th scanning line Gn+2, the pixel connected to the n+2-th scanning line Gn+2 Charging begins.
  • the n+2th level scan signal G(n+2) is high level
  • the first transistor T1 is turned on, and the reference low level signal VGL is transmitted to the nth scan line Gn via the second transistor T2 and the first transistor T1. This further pulls down the potential of the nth scan line Gn, improves the uniformity of the falling edge of the scan signal on the nth scan line Gn, increases the charging time of the pixel, and avoids mischarging.
  • FIG. 12 is a signal timing diagram of the pull-down circuit shown in FIG. 10 when the display panel is scanned in reverse direction.
  • the first control signal U2D remains a low-level signal, and the second transistor T2 is turned off; the second control signal D2U remains a high-level signal, and the fourth transistor T4 is turned on. That is, during reverse scanning, the forward scanning pull-down unit 11 is in the non-working state, and the reverse scanning pull-down unit 12 is in the working state.
  • the GOA circuit When the GOA circuit outputs a high-level n-th level scanning signal G(n) to the n-th scanning line Gn, the pixels connected to the n-th scanning line Gn begin to charge. Next, when the GOA circuit outputs the high-level n-2th level scanning signal G(n-2) to the n-2nd scanning line Gn-2, the pixel connected to the n-2nd scanning line Gn-2 Charging begins.
  • the n-2th level scan signal G(n-2) is high level
  • the third transistor T3 is turned on, and the reference low-level signal VGL is transmitted to the nth scan line Gn via the fourth transistor T4 and the third transistor T3. This further pulls down the potential of the nth scan line Gn, improves the uniformity of the falling edge of the scan signal on the nth scan line Gn, increases the charging time of the pixel, and avoids mischarging.
  • Figure 13 is a fourth circuit schematic diagram of the pull-down circuit provided by this application.
  • the difference from the pull-down circuit 10 shown in FIG. 10 is at least that in the embodiment of the present application, the gate of the first transistor T1 is connected to the first control signal U2D.
  • the source of the first transistor T1 and the drain of the second transistor T2 are connected together.
  • the drain of the first transistor T1 is connected to the n-th scanning line Gn.
  • the gate of the second transistor T2 is connected to the n+2th level scanning signal G(n+2).
  • the source of the second transistor T2 is connected to the reference low level signal VGL.
  • the gate of the third transistor T3 is connected to the second control signal D2U.
  • the source of the third transistor T3 and the drain of the fourth transistor T4 are connected together.
  • the drain of the third transistor T3 is connected to the n-th scanning line Gn.
  • the gate of the fourth transistor T4 is connected to the n-mth level scanning signal G(n-2).
  • the source of the fourth transistor T4 is connected to the reference low level signal VGL.
  • FIG. 14 is a third structural schematic diagram of a display panel provided by this application.
  • the difference from the display panel 100 shown in FIG. 1 is that in the embodiment of the present application, the display panel 100 only includes the first GOA circuit 31 .
  • the first GOA circuit 31 is located in the first non-display area NA1.
  • the pull-down circuit 10 is located in the second non-display area NA2.
  • the display panel 100 in the embodiment of the present application adopts single-side driving.
  • the scan signal is transmitted from the first GOA circuit 31 in a direction away from the first GOA circuit 31 .
  • the extension length of the scan line 20 is longer and the RC loading is larger.
  • the transmission loss of the scan signal gradually increases.
  • the first GOA circuit 31 pulls down the potential of the scanning signal, the falling edges of the scanning signals on the corresponding scanning line 20 are not uniform.
  • the pull-down circuit 10 is provided in the second non-display area NA2.
  • the pull-down circuit 10 and the first GOA circuit 31 can respectively pull down the potential of the scan line 20 at both ends of the scan line 20, thereby further improving the display panel 100.
  • the falling edge uniformity of the internal scanning signal is ensured to avoid pixel mischarge.
  • this application also provides a display device.
  • the display device includes a display panel.
  • the display panel is the display panel 100 described in any of the above embodiments, which will not be described again here.
  • the display device may be a smartphone, a tablet computer, an e-book reader, a smart watch, a video camera, a game console, etc., which is not limited in this application.
  • FIG. 15 is a schematic structural diagram of a display device provided by the present application.
  • the display device 1000 includes a display panel 100 and a driving device 200 .
  • the driving device 200 outputs the first control signal U2D and the second control signal D2U to the display panel 100 .
  • the driving device 200 may include a source driver chip, a circuit board, etc.
  • the first control signal U2D and the second control signal D2U may be output by the source driver chip.
  • the first control signal U2D and the second control signal D2U may also be output by the power management integrated chip on the circuit board. This application does not specifically limit this.
  • the display device 1000 in the embodiment of the present application includes a display panel 100.
  • the display panel 100 is provided with a pull-down circuit, which can further pull down the potential of the scan line 20, improve the uniformity of the falling edges of the scan signals in the display panel 100, and increase the charging time of the pixels. and avoid mischarges.
  • the pull-down circuit can include both a forward-scan pull-down unit and a reverse-scan pull-down unit, the display panel can realize forward scanning and reverse scanning, meeting the application scenario where the same screen is compatible with both forward and reverse scanning.

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Abstract

一种显示面板((100)及显示装置(1000)。显示面板(100)包括多条扫描线(20)和至少一下拉电路(10)。下拉电路(10)包括正扫下拉单元(11)和/或反扫下拉单元(12)；正扫下拉单元(11)接入第n+m级扫描信号(G(n+m))、第一控制信号(U2D)以及参考低电平信号(VGL)，并与第n条扫描线(Gn)连接；反扫下拉单元(12)接入第n-m级扫描信号(G(n-m))、第二控制信号(D2U)以及参考低电平信号(VGL)，并与第n条扫描线(Gn)连接。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及显示装置。
 背景技术
阵列基板栅极驱动技术(Gate Driver On Array, GOA)，是将栅极驱动电路集成在显示面板的阵列基板上，以实现逐行扫描的驱动方式。该驱动技术可以省掉栅极驱动器，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。
 技术问题
随着显示面板的尺寸增大以及分辨率提升，扫描线的RC Loading（阻容负载）不断增加，GOA输出的扫描信号的传输损耗增大，导致扫描信号的下降沿恶化严重，减少了像素充电时间、增加了像素错充的风险。
 技术解决方案
本申请提供一种显示面板及显示装置，以解决由于RC Loading导致扫描信号的下降沿恶化严重，像素充电时间减少以及像素错充风险增加的技术问题。
本申请提供了一种显示面板，其包括：
多条扫描线，多条所述扫描线沿第一方向间隔排布；
至少一下拉电路，与第n条扫描线连接，所述下拉电路用于下拉所述第n条扫描线的电位；
其中，所述下拉电路包括正扫下拉单元和/或反扫下拉单元；所述正扫下拉单元接入第n+m级扫描信号、第一控制信号以及参考低电平信号，并与所述第n条扫描线连接；所述反扫下拉单元接入第n-m级扫描信号、第二控制信号以及所述参考低电平信号，并与所述第n条扫描线连接；n和m均为大于零的整数，且n≥2，n＞m。
可选的，在本申请一些实施例中，所述正扫下拉单元包括第一晶体管和第二晶体管；
其中，所述第一晶体管的栅极接入所述第n+m级扫描信号和所述第一控制信号中的一者，所述第一晶体管的源极与所述第二晶体管的漏极连接在一起，所述第一晶体管的漏极与所述第n条扫描线连接；所述第二晶体管的栅极接入所述第n+m级扫描信号和所述第一控制信号中的另一者，所述第二晶体管的源极接入所述参考低电平信号。
可选的，在本申请一些实施例中，所述反扫下拉单元包括第三晶体管和第四晶体管；
其中，所述第三晶体管的栅极接入所述第n-m级扫描信号和所述第二控制信号中的一者，所述第三晶体管的源极与所述第四晶体管的漏极连接在一起，所述第三晶体管的漏极与所述第n条扫描线连接；所述第四晶体管的栅极接入所述第n-m级扫描信号和所述第二控制信号中的另一者，所述第四晶体管的源极接入所述参考低电平信号。
可选的，在本申请一些实施例中，所述显示面板具有显示区，所述下拉电路设置在所述显示区内。
可选的，在本申请一些实施例中，所述显示面板包括多个所述下拉电路，每一所述下拉电路与一条所述扫描线连接，每条所述扫描线与至少一个所述下拉电路连接。
可选的，在本申请一些实施例中，沿所述第一方向，与相邻两条所述扫描线对应连接的所述下拉电路交错设置。
可选的，在本申请一些实施例中，每条所述扫描线与两个所述下拉电路连接，沿所述扫描线的延伸方向，与第奇数行所述扫描线连接的所述下拉电路位于与第偶数行所述扫描线连接的所述下拉电路之间。
可选的，在本申请一些实施例中，沿所述扫描线延伸的方向，所述显示面板还具有位于所述显示区两侧的第一非显示区和第二非显示区；所述显示面板还包括第一GOA电路和第二GOA电路，所述第一GOA电路设置在所述第一非显示区，所述第二GOA电路设置在所述第二非显示区；
其中，每条所述扫描线与两个所述下拉电路连接，沿所述扫描线的延伸方向，与奇数行所述扫描线连接的所述下拉电路位于与偶数行所述扫描线连接的所述下拉电路之间。
可选的，在本申请一些实施例中，所述显示面板还包括至少一第一控制信号线和至少一第二控制信号线，所述第一控制信号线用于传输所述第一控制信号，所述第二控制信号线用于传输所述第二控制信号；所述第一控制信号线和所述第二控制信号线均沿所述第一方向延伸，每一所述下拉电路分别与所述第一控制信号线以及所述第二控制信号线连接。
可选的，在本申请一些实施例中，沿所述扫描线延伸的方向，所述显示面板具有显示区以及位于所述显示区两侧的第一非显示区和第二非显示区；所述显示面板还包括第一GOA电路，所述第一GOA电路位于所述第一非显示区，所述下拉电路位于所述第二非显示区。
相应的，本申请还提供一种显示装置，所述显示装置包括显示面板和驱动装置，所述显示面板为上述任一项所述的显示面板，所述驱动装置输出所述第一控制信号和所述第二控制信号至所述显示面板。
 有益效果
本申请提供一种显示面板及显示装置。所述显示面板包括多条扫描线和至少一下拉单元。多条所述扫描线沿第一方向间隔排布；所述下拉电路与第n条扫描线连接，所述下拉电路用于下拉所述第n条扫描线的电位；其中，所述下拉电路包括正扫下拉单元和/或反扫下拉单元；所述正扫下拉单元接入第n+m级扫描信号、第一控制信号以及参考低电平信号，并与所述第n条扫描线连接；所述反扫下拉单元接入第n-m级扫描信号、第二控制信号以及所述参考低电平信号，并与所述第n条扫描线连接；n和m均为大于零的整数，且n≥2，n＞m。本申请通过在显示面板中设置与第n条扫描线连接的下拉电路，可以进一步下拉第n条扫描线的电位，提升显示面板内扫描信号的下降沿均一性，增加像素的充电时间并避免错充。此外，由于下拉电路可以同时包括正扫下拉单元和反扫下拉单元，显示面板可以实现正向扫描和反向扫描，满足同一屏幕兼容正装倒装的应用场景。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1是本申请提供的显示面板的第一结构示意图；
图2是本申请提供的下拉电路的结构示意图；
图3是本申请提供的现有显示面板工作时的信号时序图；
图4是本申请提供的显示面板工作时的信号时序图；
图5是本申请提供的下拉电路的第一电路示意图；
图6是图5所示的下拉电路在显示面板正向扫描时的信号时序图；
图7是图5所示的下拉电路在显示面板反向扫描时的信号时序图；
图8是本申请提供的下拉电路的第二电路示意图；
图9是本申请提供的显示面板的第二结构示意图；
图10是本申请提供的下拉电路的第三电路示意图；
图11是图10所示的下拉电路在显示面板正向扫描时的信号时序图；
图12是图10所示的下拉电路在显示面板反向扫描时的信号时序图；
图13是本申请提供的下拉电路的第四电路示意图；
图14是本申请提供的显示面板的第三结构示意图；
图15是本申请提供的显示装置的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获取的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”和“第二”等的特征可以明示或者隐含地包括一个或者更多个所述特征，因此不能理解为对本申请的限制。此外，需要说明的是，除非另有明确的规定和限定，术语“相连”、“连接”应做广义理解，例如，可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
本申请提供一种显示面板及显示装置，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1和图2，图1是本申请提供的显示面板的第一结构示意图；图2是本申请提供的下拉电路的结构示意图。在本申请实施例中，显示面板100包括多条扫描线20和至少一下拉电路10。
其中，多条扫描线20沿第一方向Y间隔排布。比如，沿第一方向Y，多条扫描线20分别为第一条扫描线G1、第二条扫描线G2、第三条扫描线G3、第四条扫描线G4、第n-1条扫描线Gn-1、第n条扫描线Gn、第n+1条扫描线Gn+1、第n+2条扫描线Gn+2等，在此不一一赘述。
其中，下拉电路10与第n条扫描线Gn连接。下拉电路10用于下拉第n条扫描线Gn的电位。
具体的，下拉电路10包括正扫下拉单元11和/或反扫下拉单元12。正扫下拉单元11接入第n+m级扫描信号G(n+m)、第一控制信号U2D以及参考低电平信号VGL，并与第n条扫描线Gn连接。反扫下拉单元12接入第n-m级扫描信号G(n-m)、第二控制信号D2U以及参考低电平信号VGL，并与第n条扫描线Gn连接。其中，n和m均为大于零的整数，且n≥2，n＞m。
本申请实施例通过在显示面板100中设置与第n条扫描线Gn连接的下拉电路10，可以进一步下拉第n条扫描线Gn的电位，提升显示面板100内扫描信号的下降沿均一性，增加像素的充电时间并避免错充。此外，由于下拉电路10可以同时包括正扫下拉单元11和反扫下拉单元12，显示面板100可以实现正向扫描和反向扫描，满足同一屏幕兼容正装倒装的应用场景。
当然，在本申请一些实施例中，当显示面板100只进行正向扫描或只进行反向扫描时，下拉电路10可以仅包括正扫下拉单元11或仅包括反扫下拉单元12，满足屏幕的正装或倒装需求即可。
具体的，请参阅图3和图4，图3是本申请提供的现有显示面板工作时的信号时序图；图4是本申请提供的显示面板工作时的信号时序图。本申请实施例以m=1为例进行说明，但不能理解为对本申请的限定。
如图3所示，各级扫描信号逐行打开。比如，当第n-1级扫描信号G(n-1)由高电位VGH转变为低电位VGL时，第n级扫描信号G(n)由低电位VGL转变为高电位VGH；当第n级扫描信号G(n)由高电位VGH转变为低电位VGL时，第n+1级扫描信号G(n+1)由低电位VGL转变为高电位VGH。但随着显示面板的尺寸增大以及分辨率提升，扫描线20的RC Loading不断增加，扫描信号的传输损耗增大，导致各级扫描信号的下降沿恶化严重。比如，当第n-1级扫描信号G(n-1)由高电位VGH转变为低电位VGL时，第n-1级扫描信号G(n-1)具有第一下降沿t1；当第n级扫描信号G(n)由高电位VGH转变为低电位VGL时，第n级扫描信号G(n)具有第二下降沿t2。下降沿t1和下降沿t2的坡度较缓，说明第n-1级扫描信号G(n-1)和第n级扫描信号G(n)由高电位VGH到低电位VGL的下拉较为缓慢。
如图4所示，在本申请实施例中，当第n级扫描信号G(n)由高电位VGH转变为低电位VGL时，下拉电路10在第n+1级扫描信号G(n+1)、第一控制信号U2D、第n-1级扫描信号G(n-1)以及第二控制信号D2U的作用下，进一步下拉第n级扫描信号G(n)；此时，第n+1级扫描信号G(n+1)具有第三下降沿t4。同理，当第n-1级扫描信号G(n-1)由高电位VGH转变为低电位VGL时，下拉电路10进一步下拉第n-1级扫描信号G(n-1)的电位；此时，第n级扫描信号G(n)具有第四下降沿t3。第三下降沿t4和第四下降沿t3的持续时间较短，下拉较为迅速。
可知，t3=t4<t1=t2。也即，本申请实施例在下拉电路10的作用下，可以进一步下拉第n条扫描线Gn的电位，有效减小了各级扫描信号的下降沿。
在本申请实施例中，下拉电路10可以设置在显示面板100的显示区也可以设置在显示面板100的非显示区，具体可根据显示面板100的规格要求进行设置。
比如，在本申请一些实施例中，显示面板100具有显示区AA。多条扫描线20设置在显示区AA内。下拉电路10也设置在显示区AA内。
本申请实施例通过将下拉电路10集成设置在显示区AA内，可以有效减小显示面板100的边框，利于实现窄边框化。
在本申请实施例中，显示面板100可以包括多个下拉电路10。每一下拉电路10与一条扫描线20连接。每条扫描线20与至少一个下拉电路10连接，以实现每一条扫描线20上的扫描信号的下降沿均一性。图1中示出的下拉电路10的数量以及位置仅作为示例，不能理解为对本申请的限定。
具体的，在本申请实施例中，沿第一方向Y，与相邻两条扫描线20对应连接的下拉电路10交错设置。比如，当每条扫描线20均与一个下拉电路10连接时，与奇数行扫描线20连接的多个下拉电路10沿第一方向Y排列成一列，与偶数行扫描线20连接的多个下拉电路10沿第一方向Y排列成另一列。
可以理解的是，由于显示面板100的显示区AA内还设有像素电路（图中未示出），显示区AA内的布线空间有限。本申请实施例将与相邻两条扫描线20对应连接的下拉电路10交错设置，可以有效利用显示区AA内的布线空间，同时提高多个下拉电路10在面内的分布均匀性，避免影响显示面板100的显示画面。
在本申请实施例中，显示面板100还可以包括GOA电路。具体的，当显示面板100采用单侧驱动时，显示面板100可以仅包括第一GOA电路31或第二GOA电路32；当显示面板100采用双侧驱动时，显示面板100可以同时包括第一GOA电路31和第二GOA电路32；本申请对此不作具体限定。
其中，GOA电路用于产生各级扫描信号，并将扫描信号输出至相应的扫描线20。比如，GOA电路用于输出第n-1级扫描信号G(n-1)至第n-1条扫描线Gn-1、输出第n级扫描信号G(n)至第n条扫描线Gn、输出第n+1级扫描信号G(n+1)至第n+1条扫描线Gn+1。
具体的，在本申请实施例中，当显示面板100采用双侧驱动时，沿扫描线20延伸的方向，显示面板100还具有位于显示区AA两侧的第一非显示区NA1和第二非显示区NA2。第一GOA电路31设置在第一非显示区NA1。第二GOA电路32设置在第二非显示区NA2。
在本申请实施例中，下拉电路10可以通过与GOA电路的扫描信号输出端（图中未示出）连接，以接入第n+m级扫描信号G(n+m)和第n-m级扫描信号G(n-m)。
当然，下拉电路10也可以通过与相应的扫描线20连接，接入第n+m级扫描信号G(n+m)和第n-m级扫描信号G(n-m)。比如，如图1所示，下拉电路10与第n条扫描线Gn连接，即可接入第n级扫描信号G(n)，在此不一一赘述。
需要说明的是，通常显示面板100采用逐行扫描的方式对像素进行充电。因此，当第n级扫描信号G(n)为高电平信号时，需要拉低第n-1级扫描信号G(n-1)；当第n+1级扫描信号G(n+1)为高电平信号时，需要拉低第n级扫描信号G(n)。因此，第一GOA电路31和第二GOA电路32中均设置有下拉模块。第一GOA电路31和第二GOA电路32中的下拉模块与本申请方案中的下拉电路10相互独立，但均用于下拉相应的扫描信号。
在本申请实施例中，n和m均为大于零的整数。其中，n的数值可以根据显示面板100的驱动架构以及扫描线的数量确定。m的数值可以根据GOA电路（第一GOA电路31/第二GOA电路32）中各GOA单元之间的级联关系确定。比如，m可以是1、2、3、4等，在此不再赘述。
需要说明的是，图1中以m=1为例对本申请实施例进行说明，但不能理解为对本申请的限定。
在本申请实施例中，显示面板100还包括至少一第一控制信号线41和至少一第二控制信号线42。第一控制信号线41用于传输第一控制信号U2D。第二控制信号线42用于传输第二控制信号D2U。第一控制信号线41和第二控制信号线42均沿第一方向Y延伸，每一下拉电路10分别与第一控制信号线41以及第二控制信号线42连接。
当多个下拉电路10沿扫描线20的延伸方向排布成多列时，可对应每一列下拉电路10设置一条第一控制信号线41和一条第二控制信号线42；也可在相邻两列下拉电路10之间设置一条第一控制信号线41和一条第二控制信号线42，相邻两列的下拉电路10均与同一条第一控制信号线41以及同一条第二控制信号线42连接。由此，可以规整显示面板100中的布线，避免产生信号串扰。
需要说明的是，参考低电平信号VGL也是显示面板100面内所需的信号，下拉电路10可与显示面板100内原有的参考低电平信号VGL的传输线连接。当然，也可以额外设置信号线传输下拉电路10所需的参考低电平信号VGL。
在本申请一些实施例中，每条扫描线20可以与两个下拉电路10连接。沿扫描线20的延伸方向，与第奇数行扫描线20连接的下拉电路10位于与第偶数行扫描线20连接的下拉电路10之间。
一方面，当显示面板100的尺寸较大时，扫描线20的延伸长度较长，RC loading较大，同一条扫描线20上的扫描信号的传输波形不相同，导致扫描信号的下降沿不均一。本申请实施例通过设置每条扫描线20与两个下拉电路10连接，可以在扫描线20的不同位置处对扫描线20的电位进行下拉，同时结合第一GOA电路31以及第二GOA电路32的下拉作用，可以进一步提升显示面板100内扫描信号的下降沿均一性。
另一方面，将与奇数行扫描线20连接的下拉电路10设置在与偶数行扫描线20连接的下拉电路10之间，可以规整面内的布线，提高布线空间利用率。
进一步的，显示面板100还包括第一连接线43和第二连接线44。第一连接线43和第二连接线44的延伸方向与扫描线20的延伸方向相同。第一连接线43和第二连接线44可以设置在显示区AA内，也可以设置在显示面板100的下边框非显示区内。
可以理解的是，当显示面板100包括多条第一控制信号线41和多条第二控制信号线42时，第一连接线43与多条第一控制信号线41连接，第二连接线44与多条第二控制信号线42连接。由此，可以通过第一连接线43将第一控制信号U2D传输至多条第一控制信号线41，以及通过第二连接线44将第二控制信号D2U传输至多条第二控制信号线42。
请参阅图2和图5，图5是本申请提供的下拉电路的第一电路示意图。在本申请一些实施例中，正扫下拉单元11包括第一晶体管T1和第二晶体管T2。
其中，第一晶体管T1的栅极接入第n+m级扫描信号G(n+m)。第一晶体管T1的源极与第二晶体管T2的漏极连接在一起。第一晶体管T1的漏极与第n条扫描线Gn连接。第二晶体管T2的栅极接入第一控制信号U2D。第二晶体管T2的源极接入参考低电平信号VGL。
当m=1时，第一晶体管T1的栅极接入第n+1级扫描信号G(n+1)。正扫下拉单元11用于在显示面板100进行正向扫描时，下拉第n条扫描线Gn的电位。
进一步的，在本申请实施例中，反扫下拉单元12包括第三晶体管T3和第四晶体管T4。
其中，第三晶体管T3的栅极接入第n-m级扫描信号G(n-m)。第三晶体管T3的源极与第四晶体管T4的漏极连接在一起。第三晶体管T3的漏极与第n条扫描线Gn连接。第四晶体管T4的栅极接入第二控制信号D2U。第四晶体管T4的源极接入参考低电平信号VGL。
当m=1时，第三晶体管T3的栅极接入第n-1级扫描信号G(n-1)。反扫下拉单元12用于在显示面板100进行反向扫描时，下拉第n条扫描线Gn的电位。
需要说明的是，本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P型晶体管和/或N型晶体管两种，其中，P型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
此外，本申请以下实施例中的晶体管均以N型晶体管为例进行说明，但不能理解为对本申请的限制。
请参阅图5和图6。图6是图5所示的下拉电路在显示面板正向扫描时的信号时序图。在正向扫描时，第一控制信号U2D保持为高电平信号，第二晶体管T2打开；第二控制信号D2U保持为低电平信号，第四晶体管T4关闭。也即，在正向扫描时，正扫下拉单元11处于工作状态，反扫下拉单元12处于非工作状态。
当GOA电路输出高电平的第n级扫描信号G(n)至第n条扫描线Gn时，与第n条扫描线Gn连接的像素开始进行充电。接着，当GOA电路输出高电平的第n+1级扫描信号G(n+1)至第n+1条扫描线Gn+1时，与第n+1条扫描线Gn+1连接的像素开始进行充电。当第n+1级扫描信号G(n+1)为高电平时，第一晶体管T1打开，参考低电平信号VGL经由第二晶体管T2和第一晶体管T1传输至第n条扫描线Gn，从而进一步下拉第n条扫描线Gn的电位，改善第n条扫描线Gn上的扫描信号的下降沿均一性，增加像素的充电时间并避免错充。
请参阅图5和图7，图7是图5所示的下拉电路在显示面板反向扫描时的信号时序图。在反向扫描时，第一控制信号U2D保持为低电平信号，第二晶体管T2关闭；第二控制信号D2U保持为高电平信号，第四晶体管T4打开。也即，在反向扫描时，正扫下拉单元11处非于工作状态，反扫下拉单元12处于工作状态。
当GOA电路输出高电平的第n级扫描信号G(n)至第n条扫描线Gn时，与第n条扫描线Gn连接的像素开始进行充电。接着，当GOA电路输出高电平的第n-1级扫描信号G(n-1)至第n-1条扫描线Gn-1时，与第n-1条扫描线Gn-1连接的像素开始进行充电。当第n-1级扫描信号G(n-1)为高电平时，第三晶体管T3打开，参考低电平信号VGL经由第四晶体管T4和第三晶体管T3传输至第n条扫描线Gn，从而进一步下拉第n条扫描线Gn的电位，改善第n条扫描线Gn上的扫描信号的下降沿均一性，增加像素的充电时间并避免错充。
请参阅图8，图8是本申请提供的下拉电路的第二电路示意图。与图5所示的下拉电路10的不同之处至少在于，在本申请实施例中，第一晶体管T1的栅极接入第一控制信号U2D。第一晶体管T1的源极与第二晶体管T2的漏极连接在一起。第一晶体管T1的漏极与第n条扫描线Gn连接。第二晶体管T2的栅极接入第n+m级扫描信号G(n+m)。第二晶体管T2的源极接入参考低电平信号VGL。
当m=1时，第二晶体管T2的栅极接入第n+1级扫描信号G(n+1)。正扫下拉单元11用于在显示面板100进行正向扫描时，下拉第n条扫描线Gn的电位。
此外，第三晶体管T3的栅极接入第二控制信号D2U。第三晶体管T3的源极与第四晶体管T4的漏极连接在一起。第三晶体管T3的漏极与第n条扫描线Gn连接。第四晶体管T4的栅极接入第n-m级扫描信号G(n-m)。第四晶体管T4的源极接入参考低电平信号VGL。
当m=1时，第三晶体管T3的栅极接入第n-1级扫描信号G(n-1)。反扫下拉单元12用于在显示面板100进行反向扫描时，下拉第n条扫描线Gn的电位。
需要说明的是，图8所示的下拉电路10的信号时序图与图5所示的下拉电路10的信号时序图相同，在此不再赘述。
请参阅图9，图9是本申请提供的显示面板的第二结构示意图。与图1所示的显示面板100的不同之处在于，在本申请实施例中，m=2。比如，当下拉电路10与第n+1条扫描线Gn+1连接，以下拉第n+1条扫描线Gn+1的电位时，下拉电路10与第n-1条扫描线Gn-1连接，以接入第n-1级扫描信号G(n-1)；同时，下拉电路10与第n+3条扫描线Gn+3连接，以接入第n+3级扫描信号G(n+3)。
请参阅图10，图10是本申请提供的下拉电路的第三电路示意图。在本申请实施例中，第一晶体管T1的栅极接入第n+2级扫描信号G(n+2)。第一晶体管T1的源极与第二晶体管T2的漏极连接在一起。第一晶体管T1的漏极与第n条扫描线Gn连接。第二晶体管T2的栅极接入第一控制信号U2D。第二晶体管T2的源极接入参考低电平信号VGL。
第三晶体管T3的栅极接入第n-2级扫描信号G(n-2)。第三晶体管T3的源极与第四晶体管T4的漏极连接在一起。第三晶体管T3的漏极与第n条扫描线Gn连接。第四晶体管T4的栅极接入第二控制信号D2U。第四晶体管T4的源极接入参考低电平信号VGL。
请参阅图10和图11。图11是图10所示的下拉电路在显示面板正向扫描时的信号时序图。在正向扫描时，第一控制信号U2D保持为高电平信号，第二晶体管T2打开；第二控制信号D2U保持为低电平信号，第四晶体管T4关闭。也即，在正向扫描时，正扫下拉单元11处于工作状态，反扫下拉单元12处于非工作状态。
当GOA电路输出高电平的第n级扫描信号G(n)至第n条扫描线Gn时，与第n条扫描线Gn连接的像素开始进行充电。接着，当GOA电路输出高电平的第n+2级扫描信号G(n+2)至第n+2条扫描线Gn+2时，与第n+2条扫描线Gn+2连接的像素开始进行充电。当第n+2级扫描信号G(n+2)为高电平时，第一晶体管T1打开，参考低电平信号VGL经由第二晶体管T2和第一晶体管T1传输至第n条扫描线Gn，从而进一步下拉第n条扫描线Gn的电位，改善第n条扫描线Gn上的扫描信号的下降沿均一性，增加像素的充电时间并避免错充。
请参阅图10和图12。图12是图10所示的下拉电路在显示面板反向扫描时的信号时序图。在反向扫描时，第一控制信号U2D保持为低电平信号，第二晶体管T2关闭；第二控制信号D2U保持为高电平信号，第四晶体管T4打开。也即，在反向扫描时，正扫下拉单元11处非于工作状态，反扫下拉单元12处于工作状态。
当GOA电路输出高电平的第n级扫描信号G(n)至第n条扫描线Gn时，与第n条扫描线Gn连接的像素开始进行充电。接着，当GOA电路输出高电平的第n-2级扫描信号G(n-2)至第n-2条扫描线Gn-2时，与第n-2条扫描线Gn-2连接的像素开始进行充电。当第n-2级扫描信号G(n-2)为高电平时，第三晶体管T3打开，参考低电平信号VGL经由第四晶体管T4和第三晶体管T3传输至第n条扫描线Gn，从而进一步下拉第n条扫描线Gn的电位，改善第n条扫描线Gn上的扫描信号的下降沿均一性，增加像素的充电时间并避免错充。
请参阅图13，图13是本申请提供的下拉电路的第四电路示意图。与图10所示的下拉电路10的不同之处至少在于，在本申请实施例中，第一晶体管T1的栅极接入第一控制信号U2D。第一晶体管T1的源极与第二晶体管T2的漏极连接在一起。第一晶体管T1的漏极与第n条扫描线Gn连接。第二晶体管T2的栅极接入第n+2级扫描信号G(n+2)。第二晶体管T2的源极接入参考低电平信号VGL。
此外，第三晶体管T3的栅极接入第二控制信号D2U。第三晶体管T3的源极与第四晶体管T4的漏极连接在一起。第三晶体管T3的漏极与第n条扫描线Gn连接。第四晶体管T4的栅极接入第n-m级扫描信号G(n-2)。第四晶体管T4的源极接入参考低电平信号VGL。
需要说明的是，图13所示的下拉电路10的信号时序图与图10所示的下拉电路10的信号时序图相同，在此不再赘述。
请参阅图14，图14是本申请提供的显示面板的第三结构示意图。与图1所示的显示面板100的不同之处在于，在本申请实施例中，显示面板100仅包括第一GOA电路31。第一GOA电路31位于第一非显示区NA1。下拉电路10位于第二非显示区NA2。
本申请实施例中的显示面板100采用单侧驱动，在同一条扫描线20中，扫描信号自第一GOA电路31向远离第一GOA电路31的方向传输。当显示面板100的尺寸较大时，扫描线20的延伸长度较长，RC loading较大。沿扫描线20延伸的方向，扫描信号的传输损耗逐渐增。当第一GOA电路31下拉扫描信号的电位后，相应的扫描线20上各处的扫描信号的下降沿不均一。
本申请实施例通过在第二非显示区NA2设置下拉电路10，下拉电路10和第一GOA电路31可以在扫描线20的两端分别对扫描线20的电位进行下拉，从而进一步提升显示面板100内扫描信号的下降沿均一性，避免出现像素错充。
相应的，本申请还提供一种显示装置。显示装置包括显示面板。显示面板为上述任一实施例所述的显示面板100，在此不再赘述。
此外，显示装置可以是智能手机、平板电脑、电子书阅读器、智能手表、摄像机、游戏机等，本申请对此不作限定。
具体的，请参阅图15，图15是本申请提供的显示装置的一种结构示意图。其中，显示装置1000包括显示面板100和驱动装置200。驱动装置200输出第一控制信号U2D和第二控制信号D2U至显示面板100。
其中，驱动装置200可以包括源极驱动芯片、电路板等。第一控制信号U2D和第二控制信号D2U可以由源极驱动芯片输出。第一控制信号U2D和第二控制信号D2U也可以由电路板上的电源管理集成芯片输出。本申请对此不作具体限定。
本申请实施例中的显示装置1000包括显示面板100，显示面板100中设有下拉电路，可以进一步下拉扫描线20的电位，提升显示面板100内扫描信号的下降沿均一性，增加像素的充电时间并避免错充。此外，由于下拉电路可以同时包括正扫下拉单元和反扫下拉单元，显示面板可以实现正向扫描和反向扫描，满足同一屏幕兼容正装倒装的应用场景。
以上对本申请实施例提供的显示面板及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其包括：
    多条扫描线，多条所述扫描线沿第一方向间隔排布；
    至少一下拉电路，与第n条扫描线连接，所述下拉电路用于下拉所述第n条扫描线的电位；
    其中，所述下拉电路包括正扫下拉单元和/或反扫下拉单元；所述正扫下拉单元接入第n+m级扫描信号、第一控制信号以及参考低电平信号，并与所述第n条扫描线连接；所述反扫下拉单元接入第n-m级扫描信号、第二控制信号以及所述参考低电平信号，并与所述第n条扫描线连接；n和m均为大于零的整数，且n≥2，n＞m。
  2. 根据权利要求1所述的显示面板，其中，所述正扫下拉单元包括第一晶体管和第二晶体管；
    其中，所述第一晶体管的栅极接入所述第n+m级扫描信号和所述第一控制信号中的一者，所述第一晶体管的源极与所述第二晶体管的漏极连接在一起，所述第一晶体管的漏极与所述第n条扫描线连接；所述第二晶体管的栅极接入所述第n+m级扫描信号和所述第一控制信号中的另一者，所述第二晶体管的源极接入所述参考低电平信号。
  3. 根据权利要求2所述的显示面板，其中，所述反扫下拉单元包括第三晶体管和第四晶体管；
    其中，所述第三晶体管的栅极接入所述第n-m级扫描信号和所述第二控制信号中的一者，所述第三晶体管的源极与所述第四晶体管的漏极连接在一起，所述第三晶体管的漏极与所述第n条扫描线连接；所述第四晶体管的栅极接入所述第n-m级扫描信号和所述第二控制信号中的另一者，所述第四晶体管的源极接入所述参考低电平信号。
  4. 根据权利要求1所述的显示面板，其中，所述显示面板具有显示区，所述下拉电路设置在所述显示区内。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板包括多个所述下拉电路，每一所述下拉电路与一条所述扫描线连接，每条所述扫描线与至少一个所述下拉电路连接。
  6. 根据权利要求5所述的显示面板，其中，沿所述第一方向，与相邻两条所述扫描线对应连接的所述下拉电路交错设置。
  7. 根据权利要求5所述的显示面板，其中，每条所述扫描线与两个所述下拉电路连接，沿所述扫描线的延伸方向，与第奇数行所述扫描线连接的所述下拉电路位于与第偶数行所述扫描线连接的所述下拉电路之间。
  8. 根据权利要求5所述的显示面板，其中，沿所述扫描线延伸的方向，所述显示面板还具有位于所述显示区两侧的第一非显示区和第二非显示区；所述显示面板还包括第一GOA电路和第二GOA电路，所述第一GOA电路设置在所述第一非显示区，所述第二GOA电路设置在所述第二非显示区；
    其中，每条所述扫描线与两个所述下拉电路连接，沿所述扫描线的延伸方向，与奇数行所述扫描线连接的所述下拉电路位于与偶数行所述扫描线连接的所述下拉电路之间。
  9. 根据权利要求5所述的显示面板，其中，所述显示面板还包括至少一第一控制信号线和至少一第二控制信号线，所述第一控制信号线用于传输所述第一控制信号，所述第二控制信号线用于传输所述第二控制信号；所述第一控制信号线和所述第二控制信号线均沿所述第一方向延伸，每一所述下拉电路分别与所述第一控制信号线以及所述第二控制信号线连接。
  10. 根据权利要求1所述的显示面板，其中，沿所述扫描线延伸的方向，所述显示面板具有显示区以及位于所述显示区两侧的第一非显示区和第二非显示区；所述显示面板还包括第一GOA电路，所述第一GOA电路位于所述第一非显示区，所述下拉电路位于所述第二非显示区。
  11. 一种显示装置，所述显示装置包括显示面板和驱动装置，所述显示面板为如权利要求1所述的显示面板，所述驱动装置输出所述第一控制信号和所述第二控制信号至所述显示面板。
  12. 根据权利要求11所述的显示装置，其中，所述正扫下拉单元包括第一晶体管和第二晶体管；
    其中，所述第一晶体管的栅极接入所述第n+m级扫描信号和所述第一控制信号中的一者，所述第一晶体管的源极与所述第二晶体管的漏极连接在一起，所述第一晶体管的漏极与所述第n条扫描线连接；所述第二晶体管的栅极接入所述第n+m级扫描信号和所述第一控制信号中的另一者，所述第二晶体管的源极接入所述参考低电平信号。
  13. 根据权利要求12所述的显示装置，其中，所述反扫下拉单元包括第三晶体管和第四晶体管；
    其中，所述第三晶体管的栅极接入所述第n-m级扫描信号和所述第二控制信号中的一者，所述第三晶体管的源极与所述第四晶体管的漏极连接在一起，所述第三晶体管的漏极与所述第n条扫描线连接；所述第四晶体管的栅极接入所述第n-m级扫描信号和所述第二控制信号中的另一者，所述第四晶体管的源极接入所述参考低电平信号。
  14. 根据权利要求11所述的显示装置，其中，所述显示面板具有显示区，所述下拉电路设置在所述显示区内。
  15. 根据权利要求14所述的显示装置，其中，所述显示面板包括多个所述下拉电路，每一所述下拉电路与一条所述扫描线连接，每条所述扫描线与至少一个所述下拉电路连接。
  16. 根据权利要求15所述的显示装置，其中，沿所述第一方向，与相邻两条所述扫描线对应连接的所述下拉电路交错设置。
  17. 根据权利要求15所述的显示装置，其中，每条所述扫描线与两个所述下拉电路连接，沿所述扫描线的延伸方向，与第奇数行所述扫描线连接的所述下拉电路位于与第偶数行所述扫描线连接的所述下拉电路之间。
  18. 根据权利要求15所述的显示装置，其中，沿所述扫描线延伸的方向，所述显示面板还具有位于所述显示区两侧的第一非显示区和第二非显示区；所述显示面板还包括第一GOA电路和第二GOA电路，所述第一GOA电路设置在所述第一非显示区，所述第二GOA电路设置在所述第二非显示区；
    其中，每条所述扫描线与两个所述下拉电路连接，沿所述扫描线的延伸方向，与奇数行所述扫描线连接的所述下拉电路位于与偶数行所述扫描线连接的所述下拉电路之间。
  19. 根据权利要求15所述的显示装置，其中，所述显示面板还包括至少一第一控制信号线和至少一第二控制信号线，所述第一控制信号线用于传输所述第一控制信号，所述第二控制信号线用于传输所述第二控制信号；所述第一控制信号线和所述第二控制信号线均沿所述第一方向延伸，每一所述下拉电路分别与所述第一控制信号线以及所述第二控制信号线连接。
  20. 根据权利要求15所述的显示装置，其中，每条所述扫描线与两个所述下拉电路连接，沿所述扫描线的延伸方向，与第奇数行所述扫描线连接的所述下拉电路位于与第偶数行所述扫描线连接的所述下拉电路之间。
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Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10253940A (ja) * 1997-03-11 1998-09-25 Nec Corp 液晶表示装置
CN102789757A (zh) * 2011-05-18 2012-11-21 三星电子株式会社 栅极驱动电路及具有该栅极驱动电路的显示设备
US20130278572A1 (en) * 2012-04-20 2013-10-24 Samsung Display Co., Ltd. Display Panel and Display Device Having the Same
CN104537992A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路
CN105529006A (zh) * 2016-01-25 2016-04-27 武汉华星光电技术有限公司 一种栅极驱动电路以及液晶显示器
CN106486048A (zh) * 2017-01-03 2017-03-08 京东方科技集团股份有限公司 控制电路及显示装置
CN106647084A (zh) * 2017-02-27 2017-05-10 深圳市华星光电技术有限公司 一种阵列基板及显示面板
CN114141794A (zh) * 2021-12-08 2022-03-04 武汉华星光电技术有限公司 显示面板及显示装置
CN114170985A (zh) * 2021-12-02 2022-03-11 武汉华星光电技术有限公司 显示面板及电子装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10253940A (ja) * 1997-03-11 1998-09-25 Nec Corp 液晶表示装置
CN102789757A (zh) * 2011-05-18 2012-11-21 三星电子株式会社 栅极驱动电路及具有该栅极驱动电路的显示设备
US20130278572A1 (en) * 2012-04-20 2013-10-24 Samsung Display Co., Ltd. Display Panel and Display Device Having the Same
CN104537992A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路
CN105529006A (zh) * 2016-01-25 2016-04-27 武汉华星光电技术有限公司 一种栅极驱动电路以及液晶显示器
CN106486048A (zh) * 2017-01-03 2017-03-08 京东方科技集团股份有限公司 控制电路及显示装置
CN106647084A (zh) * 2017-02-27 2017-05-10 深圳市华星光电技术有限公司 一种阵列基板及显示面板
CN114170985A (zh) * 2021-12-02 2022-03-11 武汉华星光电技术有限公司 显示面板及电子装置
CN114141794A (zh) * 2021-12-08 2022-03-04 武汉华星光电技术有限公司 显示面板及显示装置

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