WO2018129786A1 - Cmos goa电路 - Google Patents

Cmos goa电路 Download PDF

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Publication number
WO2018129786A1
WO2018129786A1 PCT/CN2017/073878 CN2017073878W WO2018129786A1 WO 2018129786 A1 WO2018129786 A1 WO 2018129786A1 CN 2017073878 W CN2017073878 W CN 2017073878W WO 2018129786 A1 WO2018129786 A1 WO 2018129786A1
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Prior art keywords
signal
node
clock signal
control
electrically connected
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PCT/CN2017/073878
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English (en)
French (fr)
Inventor
易士娟
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武汉华星光电技术有限公司
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Priority to US15/511,016 priority Critical patent/US10311819B2/en
Publication of WO2018129786A1 publication Critical patent/WO2018129786A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a CMOS GOA circuit.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF), and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • each pixel is electrically connected to a thin film transistor (TFT), a gate of a thin film transistor is connected to a horizontal scanning line, and a drain is connected to a vertical data line, and a source (Source) ) is connected to the pixel electrode.
  • TFT thin film transistor
  • Source Source
  • the driving of the horizontal scanning line of the active liquid crystal display panel is mainly completed by an external integrated circuit (IC), and the external IC can control the stepwise charging and discharging of the horizontal scanning lines of each level.
  • the GOA technology (Gate Driver on Array) is an array substrate row driving technology, which is a driving method in which a gate driving circuit can be fabricated on a TFT array substrate by using an array process of a liquid crystal display panel to realize a gate-by-row scanning.
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product cost, and can make LCD panels more suitable for making narrow-frame or borderless display products.
  • the NAND gate circuit is used for signal processing, and the number of thin film transistors required (usually four) is more, which is not conducive to the design of the narrow bezel panel. Therefore, a new CMOS GOA circuit design is needed. Reduce the number of transistors in the CMOS GOA circuit and reduce the frame size of the display product.
  • the present invention provides a CMOS GOA circuit comprising: a multi-level GOA unit in which odd-numbered GOA units are cascaded, and even-level GOA units are cascaded;
  • Each level of the GOA unit includes: a forward and reverse scan control module, a control input module, a reset module, a latch module, a signal processing module, and an output buffer module;
  • N be positive integers, except for the first level, the second level, the second last level, and the last level GOA unit, in the Nth level GOA unit:
  • the forward/reverse scan control module accesses the potential signal of the first node of the upper two-stage N-2th GOA unit, the potential signal of the first node of the lower two-stage N+2th GOA unit, and the forward scan signal And a reverse scan signal for controlling the GOA circuit to perform a forward scan or a reverse scan by a potential change of the forward scan signal and the reverse scan signal;
  • the control input module is electrically connected to the forward/reverse scan control module and is connected to the Mth clock signal and the Mth inverted clock signal for the Mth clock signal and the Mth inverted clock signal. Controlling, under the control, the potential signal of the first node of the upper two-stage N-2th GOA unit transmitted by the forward/reverse scan control module or the first node of the lower two-stage N+2th GOA unit is inverted and output To the second node;
  • the reset module is connected to the reset signal and the constant voltage high potential signal, and is electrically connected to the second node, and is configured to perform a zeroing process on the potential signal of the first node under the control of the reset signal;
  • the latch module is connected to the Mth clock signal and the Mth inverted clock signal, and is electrically connected to the first node and the second node, and is configured to invert the potential signal of the second node and output the signal to the first node. And latching the potential signal of the first node under the control of the Mth clock signal and the Mth inverted clock signal, keeping the phase signals of the first node and the second node opposite in phase;
  • the signal processing module includes: a first thin film transistor and a second thin film transistor; a gate of the first thin film transistor is connected to a first control signal, a source is connected to an output node, and a drain is electrically connected to the third node; The gate and the source of the second thin film transistor are both connected to the second control signal, and the drain is electrically connected to the third node, and the first control signal is opposite to the phase of the second control signal, and the first The control signal and the second control signal control the first thin film transistor and the second thin film transistor to be alternately turned on, and input the potential signal or the second control signal of the output node to the third node;
  • the output buffer module is electrically connected to the third node, and is configured to invert the potential signal of the third node and output the signal as a gate scan driving signal.
  • the first thin film transistor and the second thin film transistor are both N-type thin film transistors, the output node is a second node, the first control signal is the M+2 clock signal, and the second control signal is The M+2 is an inverted clock signal, and the output buffer module performs an odd number of inversions on the potential signal of the third node and outputs the signal as a gate scan driving signal.
  • the first thin film transistor and the second thin film transistor are both P-type thin film transistors, the output node is a first node, the first control signal is the M+2 inverted clock signal, and the second control signal is the M+
  • the two clock signals are outputted by the output buffer module to the potential signal of the third node after an even number of times as a gate scan driving signal.
  • the forward/reverse scan control module includes: a first transfer gate and a second transfer gate, the control input module includes: a first clock control inverter, the reset module includes: a third thin film transistor, the latch The module includes: a second clocked inverter, and a first inverter;
  • the low potential control end of the first transmission gate is connected to the forward scan signal, the high potential control end is connected to the reverse scan signal, and the input end is electrically connected to the first node of the upper two-stage N-2th GOA unit.
  • the output end is electrically connected to the input end of the first clocked inverter;
  • the high potential control end of the second transmission gate is connected to the forward scan signal, the low potential control end is connected to the reverse scan signal, and the input end is electrically connected to the first node of the next two levels of the N+2th GOA unit.
  • the output end is electrically connected to the input end of the first clocked inverter;
  • the high potential control end of the first clocked inverter is connected to the Mth clock signal, the low potential control end is connected to the Mth inverted clock signal, and the output end is electrically connected to the second node;
  • the third thin film transistor is a P-type thin film transistor, the gate thereof is connected to the reset signal, the source is connected to the constant voltage high potential signal, and the drain is electrically connected to the second node;
  • the low potential control end of the second clocked inverter is connected to the Mth clock signal, the high potential control end is connected to the Mth inverted clock signal, the input end is electrically connected to the first node, and the output end is electrically Connected to the second node;
  • the input end of the first inverter is electrically connected to the second node, and the output end is electrically connected to the first node.
  • the output buffer module includes: a second inverter, a third inverter, and a fourth inverter; an input end of the second inverter is electrically connected to the third node, and the output end is electrically connected to the An input end of the third inverter, an output end of the third inverter is electrically connected to an input end of the fourth inverter, and an output end of the fourth inverter outputs a gate scan driving signal.
  • the output buffer module includes: a second inverter, a third inverter, an input end of the second inverter IN2 is electrically connected to the third node, and an output end is electrically connected to the third inverter IN3 At the input end, the output of the third inverter IN3 outputs a gate scan driving signal.
  • the clock signal includes four clock signals: a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; when the Mth clock signal is the third clock signal, the Mth +2 clock signals are the first clock signal, when the Mth clock signal is the fourth When the clock signal is used, the M+2 clock signal is the second clock signal;
  • the cascaded odd-numbered GOA units access the first clock signal and the third clock signal
  • the cascaded even-numbered GOA units access the second clock signal and the fourth clock signal.
  • the input end of the first transmission gate is connected to the start signal of the circuit
  • the input of the second transmission gate is connected to the start signal of the circuit.
  • the display panel applied to the bilaterally driven interlaced scanning architecture, the cascaded odd-level GOA unit and the cascaded even-numbered GOA unit are respectively disposed on the left and right sides of the display panel.
  • the present invention also provides a CMOS GOA circuit comprising: a multi-level GOA unit, wherein odd-numbered GOA units are cascaded, and even-level GOA units are cascaded;
  • Each level of the GOA unit includes: a forward and reverse scan control module, a control input module, a reset module, a latch module, a signal processing module, and an output buffer module;
  • N be positive integers, except for the first level, the second level, the second last level, and the last level GOA unit, in the Nth level GOA unit:
  • the forward/reverse scan control module accesses the potential signal of the first node of the upper two-stage N-2th GOA unit, the potential signal of the first node of the lower two-stage N+2th GOA unit, and the forward scan signal And a reverse scan signal for controlling the GOA circuit to perform a forward scan or a reverse scan by a potential change of the forward scan signal and the reverse scan signal;
  • the control input module is electrically connected to the forward/reverse scan control module and is connected to the Mth clock signal and the Mth inverted clock signal for the Mth clock signal and the Mth inverted clock signal. Controlling, under the control, the potential signal of the first node of the upper two-stage N-2th GOA unit transmitted by the forward/reverse scan control module or the first node of the lower two-stage N+2th GOA unit is inverted and output To the second node;
  • the reset module is connected to the reset signal and the constant voltage high potential signal, and is electrically connected to the second node, and is configured to perform a zeroing process on the potential signal of the first node under the control of the reset signal;
  • the latch module is connected to the Mth clock signal and the Mth inverted clock signal, and is electrically connected to the first node and the second node, and is configured to invert the potential signal of the second node and output the signal to the first node. And latching the potential signal of the first node under the control of the Mth clock signal and the Mth inverted clock signal, keeping the phase signals of the first node and the second node opposite in phase;
  • the signal processing module includes: a first thin film transistor and a second thin film transistor; a gate of the thin film transistor is connected to the first control signal, the source is connected to the output node, and the drain is electrically connected to the third node; the gate and the source of the second thin film transistor are both connected to the second control signal, and the drain
  • the third thin node is electrically connected to the third node, and the first control signal is opposite to the phase of the second control signal, and the first thin film transistor and the second thin film transistor are alternately turned on by the first control signal and the second control signal, Inputting the potential signal of the output node or the second control signal to the third node;
  • the output buffer module is electrically connected to the third node, and is used for inverting the potential signal of the third node and outputting it as a gate scan driving signal;
  • the first thin film transistor and the second thin film transistor are both N-type thin film transistors, the output node is a second node, the first control signal is the M+2 clock signal, and the second control signal is the M+ Two inverted clock signals, the output buffer module performs an odd number of inversions on the potential signal of the third node and outputs the same as a gate scan driving signal;
  • the display panel applied to the bilaterally driven interlaced scanning architecture, the cascaded odd-level GOA unit and the cascaded even-numbered GOA unit are respectively disposed on the left and right sides of the display panel.
  • the present invention provides a CMOS GOA circuit
  • the signal processing module of the CMOS GOA circuit includes first and second thin film transistors, wherein a gate of the first thin film transistor is connected to a first control signal
  • the source is connected to the output node, and the drain is electrically connected to the third node; the gate and the source of the second thin film transistor are both connected to the second control signal, and the drain is electrically connected to the third node, the first
  • the control signal is opposite to the phase of the second control signal, and the first thin film transistor and the second thin film transistor are controlled to be alternately turned on by the first control signal and the second control signal, thereby further outputting a potential signal or a second control signal of the node Input to the third node, compared with the NAND gate circuit used in the prior art, can effectively reduce the number of transistors in the CMOS GOA circuit, reduce the frame size of the display product, and is advantageous for realizing ultra-narrow bezel or borderless display products.
  • FIG. 1 is a circuit diagram of a first embodiment of a CMOS GOA circuit of the present invention
  • FIG. 2 is a circuit diagram of a first stage GOA unit of a first embodiment of a CMOS GOA circuit of the present invention
  • FIG. 3 is a second stage GOA unit of the first embodiment of the CMOS GOA circuit of the present invention Circuit diagram
  • FIG. 4 is a circuit diagram of a penultimate stage GOA unit of the first embodiment of the CMOS GOA circuit of the present invention
  • FIG. 5 is a circuit diagram of a final stage GOA unit of the first embodiment of the CMOS GOA circuit of the present invention
  • FIG. 6 is a circuit diagram of a second embodiment of a CMOS GOA circuit of the present invention.
  • FIG. 7 is a circuit diagram of a first stage GOA unit of a second embodiment of a CMOS GOA circuit of the present invention.
  • Figure 8 is a circuit diagram of a second stage GOA unit of a second embodiment of the CMOS GOA circuit of the present invention.
  • FIG. 9 is a circuit diagram of a penultimate stage GOA unit of a second embodiment of the CMOS GOA circuit of the present invention.
  • FIG. 10 is a circuit diagram of a final stage GOA unit of a second embodiment of the CMOS GOA circuit of the present invention.
  • FIG. 11 is a timing diagram of a forward scan of a CMOS GOA circuit of the present invention.
  • FIG. 12 is a timing diagram of a reverse scan of a CMOS GOA circuit of the present invention.
  • Figure 13 is a block diagram of a CMOS GOA circuit of the present invention.
  • the present invention provides a CMOS GOA circuit, including: a multi-level GOA unit, wherein odd-numbered GOA units are cascaded, and even-level GOA units are cascaded;
  • Each level of the GOA unit includes: a forward and reverse scan control module 100, a control input module 200, a reset module 300, a latch module 400, a signal processing module 500, and an output buffer module 600;
  • N be positive integers, except for the first level, the second level, the second last level, and the last level GOA unit, in the Nth level GOA unit:
  • the forward/reverse scan control module 100 accesses the potential signal of the first node Q(N-2) of the upper two-stage N-2th GOA unit, and the first node Q of the lower two-stage N+2th GOA unit a potential signal of (N+2), a forward scan signal U2D, and a reverse scan signal D2U for controlling the GOA circuit to perform forward or reverse scanning by the potential change of the forward scan signal U2D and the reverse scan signal D2U .
  • the control input module 200 is electrically connected to the forward/reverse scan control module 100 and is connected to the Mth clock signal CK(M) and the Mth inverted clock signal XCK(M) for the Mth
  • the first node Q (N) of the upper two-stage N-2th GOA unit transmitted by the forward-reverse scan control module 100 under the control of the strip clock signal CK(M) and the M-th inverted clock signal XCK(M) -2) or the potential signal of the first node Q (N+2) of the lower N+2th GOA unit is inverted and output to the second node P(N);
  • the reset module 300 is connected to the reset signal Reset and the constant voltage high potential signal VGH, and is electrically connected to the second node P(N) for the potential of the first node Q(N) under the control of the reset signal Reset. The signal is cleared.
  • the latch module 400 is connected to the Mth clock signal CK(M) and the Mth inverted clock signal XCK(M), and is electrically connected to the first node Q(N) and the second node P(N). For inverting the potential signal of the second node P(N) and outputting it to the first node Q(N), and at the Mth clock signal CK(M) and the Mth inverted clock signal XCK(M) Controlling the potential signal of the first node Q(N), keeping the phase signals of the first node Q(N) and the second node P(N) opposite in phase;
  • the signal processing module 500 includes: a first thin film transistor T1 and a second thin film transistor T2; a gate of the first thin film transistor T1 is connected to a first control signal, a source is connected to an output node, and a drain is electrically connected. a third node K(N); a gate and a source of the second thin film transistor T2 are both connected to a second control signal, and a drain is electrically connected to the third node K(N), the first control signal and the The second control signal has an opposite phase, and the first thin film transistor T1 and the second thin film transistor T2 are alternately turned on by the first control signal and the second control signal, and the potential signal or the second control signal of the output node is input to the third Node K(N);
  • the output buffer module 600 is electrically connected to the third node K(N) for inverting the potential signal of the third node K(N) several times and outputting it as the gate scan driving signal Gate(N).
  • the forward/reverse scan control module 100 includes: a first transmission gate TG1 and a second transmission gate TG2
  • the control input module 200 includes: a first clocked inverter TF1
  • the reset module 300 includes:
  • the latch module 400 includes: a second clocked inverter TF2, and a first inverter IN1;
  • the low potential control end of the first transmission gate TG1 is connected to the forward scan signal U2D, the high potential control end is connected to the reverse scan signal D2U, and the input end is electrically connected to the first two stages of the N-2th GOA unit.
  • a node Q (N-2) the output is electrically connected to the input end of the first clocked inverter TF1;
  • the high potential control end of the second transmission gate TG2 is connected to the forward scan signal U2D, the low potential control end is connected to the reverse scan signal D2U, and the input end is electrically connected to the second stage of the N+2th GOA unit.
  • the high potential control end of the first clocked inverter TF1 is connected to the Mth clock signal CK(M), and the low potential control end is connected to the Mth inverted clock signal XCK(M), and the output is electrically connected.
  • the second node P(N) At the second node P(N);
  • the third thin film transistor T3 is a P-type thin film transistor, the gate thereof is connected to the reset signal Reset, the source is connected to the constant voltage high potential signal VGH, and the drain is electrically connected to the second node P(N);
  • the low potential control terminal of the second clocked inverter TF2 is connected to the Mth clock signal CK(M), and the high potential control terminal is connected to the Mth inverted clock signal XCK(M), and the input terminal is electrically connected.
  • the input end of the first inverter IN1 is electrically connected to the second node P(N), and the output end is electrically connected to the first node Q(N).
  • the signal processing module 500 and the output buffer module 600 of the CMOS GOA circuit of the present invention have two different structures, one is the first embodiment of the present invention, and the first
  • the first thin film transistor T1 and the second thin film transistor T2 are both N-type thin film transistors
  • the output node is the second node P(N)
  • the first control signal is the M+2 clock signal CK ( M+2)
  • the second control signal is the M+2th inverted clock signal XCK(M+2)
  • the output buffer module 600 performs an odd number of inversions on the potential signal of the third node K(N) It is then output as a gate scan drive signal Gate(N).
  • the first thin film transistor T1 and the second thin film transistor T2 are both P-type thin film transistors, and the output node is the first node Q (N). )), the first control signal is the M+2th inverted clock signal XCK(M+2), the second control signal is the M+2th clock signal CK(M+2), and the output buffer module 600 is The potential signal of the third node K(N) is inverted for an even number of times and output as a gate scan drive signal Gate(N).
  • the output buffer module 600 includes: a second inverter IN2, a third inverter IN3, and a fourth inverter IN4;
  • the input end of the second inverter IN2 is electrically connected to the third node K(N), and the output end is electrically connected to the input end of the third inverter IN3, and the output end of the third inverter IN3 is electrically Connected to the input of the fourth inverter IN4, the output of the fourth inverter IN4 outputs a scan drive signal Gate(N).
  • the output buffer module 600 includes: a second inverter IN2, a third inverter IN3, and the second inverter IN2
  • the input end is electrically connected to the third node K(N)
  • the output end is electrically connected to the input end of the third inverter IN3
  • the output end of the third inverter IN3 outputs the gate scan driving signal Gate(N) .
  • the clock signal includes four clock signals: a first clock signal CK(1), a second clock signal CK(2), a third clock signal CK(3), and a fourth clock signal.
  • No. CK(4) when the Mth clock signal CK(M) is the third clock signal CK(3), the M+2th clock signal CK(M+2) is the first clock signal CK(1)
  • the Mth clock signal CK(M) is the fourth clock signal CK(4)
  • the M+2th clock signal CK(M+2) is the second clock signal CK(2), the previous one
  • the falling edge of the clock signal is generated simultaneously with the rising edge of the next clock signal;
  • the cascaded odd-level GOA unit accesses the first clock signal CK(1) and the third clock signal CK(3), and the cascaded even-numbered GOA units access the second clock signal CK(2) and fourth Clock signal CK(4).
  • the inverted clock signal corresponding to the clock signal also includes four inverted clock signals: a first inverted clock signal XCK (1), a second inverted clock signal XCK (2), and a third inverted clock signal XCK ( 3), and the fourth inverted clock signal XCK (4), respectively, by the first clock signal CK (1), the second clock signal CK (2), the third clock signal CK (3), and The four clock signals CK(4) are inverted by an inverter.
  • the control input module 200 of the first-level GOA unit and the latch module 400 access the first clock signal CK(1) and the first strip
  • the phase clock signal XCK(1) the signal processing module 500 accesses the third clock signal CK(3) and the third inverted clock signal XCK(3)
  • the control input module 200 and the latch module of the first stage GOA unit 400 accesses the third clock signal CK(3) and the third inverted clock signal XCK(3)
  • the signal processing module 500 accesses the first clock signal CK(1) and the first inverted clock signal XCK ( 1)
  • the control input module 200 of the primary GOA unit and the latch module 400 access the second clock signal CK(2) and the second Inverting the clock signal XCK(2)
  • the signal processing module 500 accesses the fourth clock signal CK(4) and the fourth inverted clock signal XCK(4)
  • the control input module 200 of the first stage GOA unit and the latch The module
  • the input signal of the first transmission gate TG1 is connected to the start signal STV of the circuit
  • the input end of the second transmission gate TG2 is connected to the start signal STV of the circuit.
  • the input of the first transmission gate TG1 is also connected to the start signal STV of the circuit
  • the second transmission door The input of TG2 is also connected to the start signal STV of the circuit.
  • the first embodiment of the CMOS GOA circuit of the present invention works in forward scanning mode.
  • the forward scanning signal U2D provides a low potential and is opposite.
  • the first node Q(N-2) of the N-2th GOA unit provides a high potential
  • the first transfer gate TG1 is turned on
  • the second transfer gate TG2 is turned off
  • the N-2th GOA unit The high potential of the first node Q(N-2) is transmitted to the input terminal of the first clocked inverter TF1, and then the first clock signal CK(1) provides a high potential
  • the first inverted clock signal XCK(1) Providing a low potential, the first clocked inverter TF1 is turned on, and the high potential of the input terminal is inverted to the second node P(N), so that the second node P(N) is low, the second node P The potential of (N) is inverted by the first
  • the gate scan driving signal Gate(N) outputs a high potential
  • the third clock signal CK(3) provides a low potential
  • the third inverted clock signal XCK(3) provides a high potential
  • the first thin film transistor T1 is turned off.
  • the second thin film transistor T2 is turned on, the high potential of the third inverted clock signal XCK(3) is transmitted to the third node K(N), and the high potential of the third node K(N) is passed through the second, third, and
  • the fourth inverters IN2, IN3, and IN4 become low after being inverted three times, and the gate scan driving signal Gate(N) outputs a low potential, and then the first clock signal CK(1) provides a high potential again, the first inversion.
  • the clock signal XCK(1) again provides a low potential
  • the first node Q(N-2) of the N-2th GOA cell provides a low potential
  • the first clocked inverter TF1 Through the second point P (N) goes high, the first node Q (N) goes low, driving a scanning gate signal Gate (N) continuously outputs a low potential.
  • the forward scan signal U2D provides a low potential and the reverse scan signal D2U provides a high potential
  • the first clock signal CK(1) provides a high potential for the first time
  • the first inverted clock When the signal XCK(1) provides a low potential for the first time, the high potential of the first node Q(N) of the Nth stage GOA unit is transmitted to the input terminal of the first clocked inverter TF1, and the third clock signal CK(3) Providing a high potential, when the third inverted clock signal XCK(3) provides a low potential, the first clocked inverter TF1 is turned on, and the high potential of the first node Q(N) of the Nth stage GOA unit is inverted.
  • the first node Q(N+2) becomes high, and then the third clock signal CK(3) provides a low potential,
  • the third inverted clock signal XCK(3) When the high potential is applied, the second clocked inverter TF2 is turned on, the second node P(N+2) of the N+2th GOA unit is latched to a low potential, and the first node Q(N+2) is latched.
  • the first clock signal CK(1) provides a high potential for the second time.
  • the first inverted clock signal XCK(1) provides a low potential for the second time
  • the first thin film transistor T1 is turned on, and the second thin film transistor T2 is turned on.
  • the low potential of the second node P(N+2) of the N+2th GOA unit is transmitted to the third node K(N+2) of the N+2th GOA unit, and the third node K(N+2)
  • the low potential becomes high after three times of inversion by the second, third, and fourth inverters IN2, IN3, and IN4, and the gate scan driving signal Gate(N+2) of the N+2th GOA unit Outputting a high potential
  • the first clock signal CK(1) provides a low potential
  • the first inverted clock signal XCK(1) provides a high potential
  • the first thin film transistor T1 is turned off
  • the second thin film transistor T2 is turned on
  • first The high potential of the inverted clock signal XCK(1) is transmitted to the third node K(N+2) of the N+2th GOA unit, and the high potential of the third node K(N+2) is passed through the second, third, And the fourth inverters IN2, IN3, and IN4 become low after being inverted three times.
  • the gate scan driving signal Gate(N+2) of the N+2th GOA unit outputs a low potential, and then the third clock signal CK(3) again supplies a high potential, and the third inverted clock signal XCK(3) again Providing a low potential, the first node Q(N) of the Nth stage GOA unit provides a low potential, the first clocked inverter TF1 is turned on, and the second node P(N) of the N+2th GOA unit +2) becomes high, the first node Q(N+2) of the N+2th GOA unit becomes low, and the gate scan driving signal Gate(N+2) of the N+2th GOA unit continues The output is low, and so on, up to the last level of the GOA unit.
  • the working process of the second embodiment of the CMOS GOA circuit of the present invention is substantially the same as that of the first embodiment except that the source of the first thin film transistor T1 is directly connected. Entering the potential signal of the first node Q(N), and inverting and outputting the potential signal of the first node Q(N) twice, reducing the first-stage inverter, and further reducing the number of transistors in the CMOS GOA circuit , zoom out to show the border size of the product.
  • FIG. 12 is a timing diagram of the reverse scan of the CMOS GOA circuit of the present invention.
  • the reverse scan works in the same manner as the forward scan, except that the scan direction is changed from the first stage to the last stage. The last level is scanned to the first level, and the work process will not be described here.
  • the reset process is as follows: the reset signal Reset provides a low potential pulse, and the third thin film transistor T3 of each level of the GOA unit is turned on, and the constant voltage high potential VGH is written.
  • the second node P(N) of each level of the GOA unit is reset to a high potential, the first node Q(N) is reset to a low potential, and the gate scan driving signals Gate(N) of each stage output a low potential.
  • the CMOS GOA circuit of the present invention is applied to a display panel of a bilaterally driven interlaced scanning architecture, and the odd-level GOA units and the even-numbered GOA units of the display panel are respectively disposed on the left and right sides of the display panel. GOA units at all levels follow the scanning direction from the first The scan signal is output to the corresponding scan line in the display panel in order from the last stage to the last stage or from the last stage to the first stage.
  • the present invention provides a CMOS GOA circuit
  • the signal processing module of the CMOS GOA circuit includes first and second thin film transistors, wherein a gate of the first thin film transistor is connected to a first control signal, The source is connected to the output node, and the drain is electrically connected to the third node; the gate and the source of the second thin film transistor are both connected to the second control signal, and the drain is electrically connected to the third node, the first control The signal is opposite to the phase of the second control signal, and the first thin film transistor and the second thin film transistor are controlled to be alternately turned on by the first control signal and the second control signal, thereby inputting the potential signal or the second control signal of the output node To the third node, compared with the NAND gate circuit used in the prior art, the number of transistors in the CMOS GOA circuit can be effectively reduced, and the frame size of the display product can be reduced, which is advantageous for realizing an ultra-narrow bezel or a borderless display product.

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Abstract

一种CMOS GOA电路，该CMOS GOA电路的信号处理模块（500）包括第一和第二薄膜晶体管，其中，所述第一薄膜晶体管（T1）的栅极接入第一控制信号（CK（M+2）），源极接入输出节点（P（N）），漏极电性连接第三节点（K（N））；所述第二薄膜晶体管（T2）的栅极与源极均接入第二控制信号（XCK（M+2）），漏极电性连接第三节点（K（N）），所述第一控制信号（CK（M+2））与所述第二控制信号（XCK（M+2））的相位相反，通过所述第一控制信号（CK（M+2））与第二控制信号（XCK（M+2））控制第一薄膜晶体管（T1）与第二薄膜晶体管（T2）交替打开，进而将输出节点（P（N））的电位信号或第二控制信号（XCK（M+2））输入到第三节点（K（N）），相比于现有技术采用的与非门电路，能够有效减少CMOS GOA电路中的晶体管数量，缩小显示产品的边框大小，有利于实现超窄边框或无边框的显示产品。

Description

CMOS GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种CMOS GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是可以运用液晶显示面板的阵列制程将栅极驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
传统的CMOS GOA电路中采用与非门电路进行信号处理，需要的薄膜晶体管数量(通常为4个)较多，不利于窄边框面板的设计，因此，需要一种的新的CMOS GOA电路设计，减少CMOS GOA电路中的晶体管数量，缩小显示产品的边框大小。
发明内容
本发明的目的在于提供一种CMOS GOA电路，能够有效减少CMOS GOA电路中的晶体管数量，缩小显示产品的边框大小。
为实现上述目的，本发明提供了一种CMOS GOA电路，包括：多级GOA单元，其中奇数级GOA单元级联，偶数级GOA单元级联；
每一级GOA单元均包括：正反向扫描控制模块、控制输入模块、复位模块、锁存模块、信号处理模块、及输出缓冲模块；
设M、N均为正整数，除第一级、第二级、倒数第二级、以及最后一级GOA单元外，在第N级GOA单元中：
所述正反向扫描控制模块接入上两级第N-2级GOA单元的第一节点的电位信号、下两级第N+2级GOA单元的第一节点的电位信号、正向扫描信号、以及反向扫描信号，用于通过正向扫描信号以及反向扫描信号的电位变化控制GOA电路进行正向扫描或反向扫描；
所述控制输入模块与所述正反向扫描控制模块电性连接并接入第M条时钟信号、第M条反相时钟信号，用于在第M条时钟信号以及第M条反相时钟信号的控制下对正反向扫描控制模块传输来的上两级第N-2级GOA单元的第一节点或下两级第N+2级GOA单元的第一节点的电位信号进行反相并输出到第二节点；
所述复位模块接入复位信号和恒压高电位信号，并与第二节点电性连接，用于在复位信号的控制下对第一节点的电位信号进行清零处理；
所述锁存模块接入第M条时钟信号、第M条反相时钟信号，并电性连接第一节点和第二节点，用于将第二节点的电位信号反相后输出到第一节点，并在第M条时钟信号和第M条反相时钟信号的控制下锁存第一节点的电位信号，保持所述第一节点和第二节点的电位信号的相位相反；
所述信号处理模块包括：第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管的栅极接入第一控制信号，源极接入输出节点，漏极电性连接第三节点；所述第二薄膜晶体管的栅极与源极均接入第二控制信号，漏极电性连接第三节点，所述第一控制信号与所述第二控制信号的相位相反，通过所述第一控制信号与第二控制信号控制第一薄膜晶体管与第二薄膜晶体管交替打开，将输出节点的电位信号或第二控制信号输入到第三节点；
所述输出缓冲模块电性连接于第三节点，用于将第三节点的电位信号进行数次反相后作为栅极扫描驱动信号输出。
所述第一薄膜晶体管与第二薄膜晶体管均为N型薄膜晶体管，所述输出节点为第二节点，第一控制信号为第M+2条时钟信号，第二控制信号为 第M+2条反相时钟信号，所述输出缓冲模块对所述第三节点的电位信号进行奇数次反相后作为栅极扫描驱动信号输出。
所述第一薄膜晶体管与第二薄膜晶体管均为P型薄膜晶体管，所述输出节点为第一节点，第一控制信号为第M+2条反相时钟信号，第二控制信号为第M+2条时钟信号，所述输出缓冲模块对所述第三节点的电位信号进行偶数次反相后作为栅极扫描驱动信号输出。
所述正反向扫描控制模块包括：第一传输门以及第二传输门，所述控制输入模块包括：第一时钟控制反相器，所述复位模块包括：第三薄膜晶体管，所述锁存模块包括：第二时钟控制反相器、以及第一反相器；
所述第一传输门的低电位控制端接入正向扫描信号，高电位控制端接入反向扫描信号，输入端电性连接于上两级第N-2级GOA单元的第一节点，输出端电性连接于第一时钟控制反相器的输入端；
所述第二传输门的高电位控制端接入正向扫描信号，低电位控制端接入反向扫描信号，输入端电性连接于下两级第N+2级GOA单元的第一节点，输出端电性连接于第一时钟控制反相器的输入端；
所述第一时钟控制反相器的高电位控制端接入第M条时钟信号，低电位控制端接入第M条反相时钟信号，输出端电性连接于第二节点；
所述第三薄膜晶体管为P型薄膜晶体管，其栅极接入复位信号，源极接入恒压高电位信号，漏极电性连接于第二节点；
所述第二时钟控制反相器的低电位控制端接入第M条时钟信号，高电位控制端接入第M条反相时钟信号，输入端电性连接于第一节点，输出端电性连接于第二节点；
所述第一反相器的输入端电性连接于第二节点，输出端电性连接于第一节点。
所述输出缓冲模块包括：第二反相器、第三反相器、以及第四反相器；所述第二反相器的输入端电性连接第三节点，输出端电性连接于第三反相器的输入端，所述第三反相器的输出端电性连接于第四反相器的输入端，所述第四反相器的输出端输出栅极扫描驱动信号。
所述输出缓冲模块包括：第二反相器、第三反相器，所述第二反相器IN2的输入端电性连接第三节点，输出端电性连接于第三反相器IN3的输入端，所述第三反相器IN3的输出端输出栅极扫描驱动信号。
所述时钟信号包括四条时钟信号：第一条时钟信号、第二条时钟信号、第三条时钟信号、及第四条时钟信号；当第M条时钟信号为第三条时钟信号时，第M+2条时钟信号为第一条时钟信号，当第M条时钟信号为第四条 时钟信号时，第M+2条时钟信号为第二条时钟信号；
级联的奇数级GOA单元接入第一条时钟信号与第三条时钟信号，级联的偶数级GOA单元接入第二条时钟信号与第四条时钟信号。
当所述正向扫描信号提供低电位且反向扫描信号提供高电位时，进行正向扫描；当所述正向扫描信号提供高电位且反向扫描信号提供低电位时，进行反向扫描。
在第一级和第二级GOA单元中，所述第一传输门的输入端接入电路的起始信号；
在倒数第二级和最后一级GOA单元中，所述第二传输门的输入端接入电路的起始信号。
应用于双边驱动隔行扫描架构的显示面板，所述级联的奇数级GOA单元和级联的偶数级GOA单元分别设置于显示面板的左、右两边。
本发明还提供一种CMOS GOA电路，包括：多级GOA单元，其中奇数级GOA单元级联，偶数级GOA单元级联；
每一级GOA单元均包括：正反向扫描控制模块、控制输入模块、复位模块、锁存模块、信号处理模块、及输出缓冲模块；
设M、N均为正整数，除第一级、第二级、倒数第二级、以及最后一级GOA单元外，在第N级GOA单元中：
所述正反向扫描控制模块接入上两级第N-2级GOA单元的第一节点的电位信号、下两级第N+2级GOA单元的第一节点的电位信号、正向扫描信号、以及反向扫描信号，用于通过正向扫描信号以及反向扫描信号的电位变化控制GOA电路进行正向扫描或反向扫描；
所述控制输入模块与所述正反向扫描控制模块电性连接并接入第M条时钟信号、第M条反相时钟信号，用于在第M条时钟信号以及第M条反相时钟信号的控制下对正反向扫描控制模块传输来的上两级第N-2级GOA单元的第一节点或下两级第N+2级GOA单元的第一节点的电位信号进行反相并输出到第二节点；
所述复位模块接入复位信号和恒压高电位信号，并与第二节点电性连接，用于在复位信号的控制下对第一节点的电位信号进行清零处理；
所述锁存模块接入第M条时钟信号、第M条反相时钟信号，并电性连接第一节点和第二节点，用于将第二节点的电位信号反相后输出到第一节点，并在第M条时钟信号和第M条反相时钟信号的控制下锁存第一节点的电位信号，保持所述第一节点和第二节点的电位信号的相位相反；
所述信号处理模块包括：第一薄膜晶体管和第二薄膜晶体管；所述第 一薄膜晶体管的栅极接入第一控制信号，源极接入输出节点，漏极电性连接第三节点；所述第二薄膜晶体管的栅极与源极均接入第二控制信号，漏极电性连接第三节点，所述第一控制信号与所述第二控制信号的相位相反，通过所述第一控制信号与第二控制信号控制第一薄膜晶体管与第二薄膜晶体管交替打开，将输出节点的电位信号或第二控制信号输入到第三节点；
所述输出缓冲模块电性连接于第三节点，用于将第三节点的电位信号进行数次反相后作为栅极扫描驱动信号输出；
其中，所述第一薄膜晶体管与第二薄膜晶体管均为N型薄膜晶体管，所述输出节点为第二节点，第一控制信号为第M+2条时钟信号，第二控制信号为第M+2条反相时钟信号，所述输出缓冲模块对所述第三节点的电位信号进行奇数次反相后作为栅极扫描驱动信号输出；
其中，应用于双边驱动隔行扫描架构的显示面板，所述级联的奇数级GOA单元和级联的偶数级GOA单元分别设置于显示面板的左、右两边。
本发明的有益效果：本发明提供了一种CMOS GOA电路，该CMOS GOA电路的信号处理模块包括第一和第二薄膜晶体管，其中，所述第一薄膜晶体管的栅极接入第一控制信号，源极接入输出节点，漏极电性连接第三节点；所述第二薄膜晶体管的栅极与源极均接入第二控制信号，漏极电性连接第三节点，所述第一控制信号与所述第二控制信号的相位相反，通过所述第一控制信号与第二控制信号控制第一薄膜晶体管与第二薄膜晶体管交替打开，进而将输出节点的电位信号或第二控制信号输入到第三节点，相比于现有技术采用的与非门电路，能够有效减少CMOS GOA电路中的晶体管数量，缩小显示产品的边框大小，有利于实现超窄边框或无边框的显示产品。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的CMOS GOA电路的第一实施例的电路图；
图2为本发明的CMOS GOA电路的第一实施例的第一级GOA单元的电路图；
图3为本发明的CMOS GOA电路的第一实施例的第二级GOA单元的 电路图；
图4为本发明的CMOS GOA电路的第一实施例的倒数第二级GOA单元的电路图；
图5为本发明的CMOS GOA电路的第一实施例的最后一级GOA单元的电路图；
图6为本发明的CMOS GOA电路的第二实施例的电路图；
图7为本发明的CMOS GOA电路的第二实施例的第一级GOA单元的电路图；
图8为本发明的CMOS GOA电路的第二实施例的第二级GOA单元的电路图；
图9为本发明的CMOS GOA电路的第二实施例的倒数第二级GOA单元的电路图；
图10为本发明的CMOS GOA电路的第二实施例的最后一级GOA单元的电路图；
图11为本发明的CMOS GOA电路正向扫描时的时序图；
图12为本发明的CMOS GOA电路反向扫描时的时序图；
图13为本发明的CMOS GOA电路的架构图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1或图6，本发明提供一种CMOS GOA电路，包括：多级GOA单元，其中奇数级GOA单元级联，偶数级GOA单元级联；
每一级GOA单元均包括：正反向扫描控制模块100、控制输入模块200、复位模块300、锁存模块400、信号处理模块500、及输出缓冲模块600；
设M、N均为正整数，除第一级、第二级、倒数第二级、以及最后一级GOA单元外，在第N级GOA单元中：
所述正反向扫描控制模块100接入上两级第N-2级GOA单元的第一节点Q(N-2)的电位信号、下两级第N+2级GOA单元的第一节点Q(N+2)的电位信号、正向扫描信号U2D、以及反向扫描信号D2U，用于通过正向扫描信号U2D以及反向扫描信号D2U的电位变化控制GOA电路进行正向扫描或反向扫描。
所述控制输入模块200与所述正反向扫描控制模块100电性连接并接入第M条时钟信号CK(M)、第M条反相时钟信号XCK(M)，用于在第M 条时钟信号CK(M)以及第M条反相时钟信号XCK(M)的控制下对正反向扫描控制模块100传输来的上两级第N-2级GOA单元的第一节点Q(N-2)或下两级第N+2级GOA单元的第一节点Q(N+2)的电位信号进行反相并输出到第二节点P(N)；
所述复位模块300接入复位信号Reset和恒压高电位信号VGH，并与第二节点P(N)电性连接，用于在复位信号Reset的控制下对第一节点Q(N)的电位信号进行清零处理；
所述锁存模块400接入第M条时钟信号CK(M)、第M条反相时钟信号XCK(M)，并电性连接第一节点Q(N)和第二节点P(N)，用于将第二节点P(N)的电位信号反相后输出到第一节点Q(N)，并在第M条时钟信号CK(M)和第M条反相时钟信号XCK(M)的控制下锁存第一节点Q(N)的电位信号，保持所述第一节点Q(N)和第二节点P(N)的电位信号的相位相反；
所述信号处理模块500包括：第一薄膜晶体管T1和第二薄膜晶体管T2；所述第一薄膜晶体管T1的栅极接入第一控制信号，源极接入输出节点，漏极电性连接第三节点K(N)；所述第二薄膜晶体管T2的栅极与源极均接入第二控制信号，漏极电性连接第三节点K(N)，所述第一控制信号与所述第二控制信号的相位相反，通过所述第一控制信号与第二控制信号控制第一薄膜晶体管T1与第二薄膜晶体管T2交替打开，将输出节点的电位信号或第二控制信号输入到第三节点K(N)；
所述输出缓冲模块600电性连接于第三节点K(N)，用于将第三节点K(N)的电位信号进行数次反相后作为栅极扫描驱动信号Gate(N)输出。
具体地，请参阅图1或图6，在本发明第一和第二实施例中，所述正反向扫描控制模块100、控制输入模块200、复位模块300、以及锁存模块400的结构相同，其中，所述正反向扫描控制模块100包括：第一传输门TG1以及第二传输门TG2，所述控制输入模块200包括：第一时钟控制反相器TF1，所述复位模块300包括：第三薄膜晶体管T3，所述锁存模块400包括：第二时钟控制反相器TF2、以及第一反相器IN1；
所述第一传输门TG1的低电位控制端接入正向扫描信号U2D，高电位控制端接入反向扫描信号D2U，输入端电性连接于上两级第N-2级GOA单元的第一节点Q(N-2)，输出端电性连接于第一时钟控制反相器TF1的输入端；
所述第二传输门TG2的高电位控制端接入正向扫描信号U2D，低电位控制端接入反向扫描信号D2U，输入端电性连接于下两级第N+2级GOA单元的第一节点Q(N+2)，输出端电性连接于第一时钟控制反相器TF1的输 入端；
所述第一时钟控制反相器TF1的高电位控制端接入第M条时钟信号CK(M)，低电位控制端接入第M条反相时钟信号XCK(M)，输出端电性连接于第二节点P(N)；
所述第三薄膜晶体管T3为P型薄膜晶体管，其栅极接入复位信号Reset，源极接入恒压高电位信号VGH，漏极电性连接于第二节点P(N)；
所述第二时钟控制反相器TF2的低电位控制端接入第M条时钟信号CK(M)，高电位控制端接入第M条反相时钟信号XCK(M)，输入端电性连接于第一节点Q(N)，输出端电性连接于第二节点P(N)；
所述第一反相器IN1的输入端电性连接于第二节点P(N)，输出端电性连接于第一节点Q(N)。
具体地，请参阅图1与图6，本发明的CMOS GOA电路的信号处理模块500、以及输出缓冲模块600具有两种不同的结构，一种为本发明的第一实施例，在该第一实施例中所述第一薄膜晶体管T1与第二薄膜晶体管T2均为N型薄膜晶体管，所述输出节点为第二节点P(N)，第一控制信号为第M+2条时钟信号CK(M+2)，第二控制信号为第M+2条反相时钟信号XCK(M+2)，所述输出缓冲模块600对所述第三节点K(N)的电位信号进行奇数次反相后作为栅极扫描驱动信号Gate(N)输出。另一种为本发明的第二实施例，在该第二实施例中所述第一薄膜晶体管T1与第二薄膜晶体管T2均为P型薄膜晶体管，所述输出节点为第一节点Q(N))，第一控制信号为第M+2条反相时钟信号XCK(M+2)，第二控制信号为第M+2条时钟信号CK(M+2)，所述输出缓冲模块600对所述第三节点K(N)的电位信号进行偶数次反相后作为栅极扫描驱动信号Gate(N)输出。
优选地，如图1所示，在本发明的第一实施例中，所述输出缓冲模块600包括：第二反相器IN2、第三反相器IN3、以及第四反相器IN4；所述第二反相器IN2的输入端电性连接第三节点K(N)，输出端电性连接于第三反相器IN3的输入端，所述第三反相器IN3的输出端电性连接于第四反相器IN4的输入端，所述第四反相器IN4的输出端输出扫描驱动信号Gate(N)。
优选地，如图6所示，在本发明的第二实施例中，所述输出缓冲模块600包括：第二反相器IN2、第三反相器IN3，所述第二反相器IN2的输入端电性连接第三节点K(N)，输出端电性连接于第三反相器IN3的输入端，所述第三反相器IN3的输出端输出栅极扫描驱动信号Gate(N)。
需要说明的是，所述时钟信号包括四条时钟信号：第一条时钟信号CK(1)、第二条时钟信号CK(2)、第三条时钟信号CK(3)、及第四条时钟信 号CK(4)；当第M条时钟信号CK(M)为第三条时钟信号CK(3)时，第M+2条时钟信号CK(M+2)为第一条时钟信号CK(1)，当第M条时钟信号CK(M)为第四条时钟信号CK(4)时，第M+2条时钟信号CK(M+2)为第二条时钟信号CK(2)，前一条时钟信号的下降沿与后一条时钟信号的上升沿同时产生；
级联的奇数级GOA单元接入第一条时钟信号CK(1)与第三条时钟信号CK(3)，级联的偶数级GOA单元接入第二条时钟信号CK(2)与第四条时钟信号CK(4)。
所述反相时钟信号对应时钟信号也包括四条反相时钟信号：第一条反相时钟信号XCK(1)、第二条反相时钟信号XCK(2)、第三条反相时钟信号XCK(3)、及第四条反相时钟信号XCK(4)，分别由第一条时钟信号CK(1)、第二条时钟信号CK(2)、第三条时钟信号CK(3)、及第四条时钟信号CK(4)经由一反相器反相得到。
进一步地，对于级联的两级相邻的奇数级GOA单元来说，其中一级GOA单元的控制输入模块200与锁存模块400接入第一条时钟信号CK(1)和第一条反相时钟信号XCK(1)，信号处理模块500接入第三条时钟信号CK(3)和第三条反相时钟信号XCK(3)，另外一级GOA单元的控制输入模块200与锁存模块400接入第三条时钟信号CK(3)和第三条反相时钟信号XCK(3)，信号处理模块500接入第一条时钟信号CK(1)和第一条反相时钟信号XCK(1)，而对于级联的两级相邻的偶数级GOA单元来说，其中一级GOA单元的控制输入模块200与锁存模块400接入第二条时钟信号CK(2)和第二条反相时钟信号XCK(2)，信号处理模块500接入第四条时钟信号CK(4)和第四条反相时钟信号XCK(4)，另外一级GOA单元的控制输入模块200与锁存模块400接入第四条时钟信号CK(4)和第四条反相时钟信号XCK(4)，信号处理模块500接入第二条时钟信号CK(2)和第二条反相时钟信号XCK(2)。
具体地，当所述正向扫描信号U2D提供低电位且反向扫描信号D2U提供高电位时，进行正向扫描；当所述正向扫描信号U2D提供高电位且反向扫描信号D2U提供低电位时，进行反向扫描。
请参阅图2至图5，在本发明的第一实施例中，在第一级和第二级GOA单元中，所述第一传输门TG1的输入端接入电路的起始信号STV，在倒数第二级和最后一级GOA单元中，所述第二传输门TG2的输入端接入电路的起始信号STV，相应请参阅图7至图10，在本发明的第二实施例中，在第一级和第二级GOA单元中，所述第一传输门TG1的输入端也接入电路的起始信号STV，在倒数第二级和最后一级GOA单元中，所述第二传输门 TG2的输入端也接入电路的起始信号STV。
请参阅图11，并结合图1，本发明的CMOS GOA电路的第一实施例正向扫描时的工作过程为：在第N级GOA单元中，所述正向扫描信号U2D提供低电位且反向扫描信号D2U提供高电位，第N-2级GOA单元的第一节点Q(N-2)提供高电位，第一传输门TG1打开，第二传输门TG2关闭，第N-2级GOA单元的第一节点Q(N-2)的高电位传输到第一时钟控制反相器TF1的输入端，随后第一时钟信号CK(1)提供高电位，第一反相时钟信号XCK(1)提供低电位，所述第一时钟控制反相器TF1导通，将输入端的高电位反相传输到第二节点P(N)，使得第二节点P(N)为低电位，第二节点P(N)的电位经由第一反相器IN1反相后传输到第一节点Q(N)，使得第一节点Q(N)为高电位，随后第一时钟信号CK(1)提供低电位，第一反相时钟信号XCK(1)提供高电位，所述第二时钟控制反相器TF2导通，将第一节点Q(N)锁存为高电位，第二节点P(N)锁存为低电位，接着第三时钟信号CK(3)提供高电位，第三反相时钟信号XCK(3)提供低电位，第一薄膜晶体管T1导通，第二薄膜晶体管T2关闭，第二节点P(N)的低电位传输到第三节点K(N)，第三节点K(N)的低电位经由第二、第三、及第四反相器IN2、IN3、IN4三次反相后变为高电位，栅极扫描驱动信号Gate(N)输出高电位，接着所述第三时钟信号CK(3)提供低电位，第三反相时钟信号XCK(3)提供高电位，第一薄膜晶体管T1关闭，第二薄膜晶体管T2导通，第三反相时钟信号XCK(3)的高电位传输到第三节点K(N)，第三节点K(N)的高电位经由第二、第三、及第四反相器IN2、IN3、IN4三次反相后变为低电位，栅极扫描驱动信号Gate(N)输出低电位，接着第一时钟信号CK(1)再次提供高电位，第一反相时钟信号XCK(1)再次提供低电位，第N-2级GOA单元的第一节点Q(N-2)提供低电位，所述第一时钟控制反相器TF1导通，所述第二节点P(N)变为高电位，第一节点Q(N)变为低电位，栅极扫描驱动信号Gate(N)持续输出低电位。
在第N+2级GOA单元中，所述正向扫描信号U2D提供低电位且反向扫描信号D2U提供高电位，第一时钟信号CK(1)第一次提供高电位，第一反相时钟信号XCK(1)第一次提供低电位时，第N级GOA单元的第一节点Q(N)的高电位传输到第一时钟反相器TF1的输入端，第三时钟信号CK(3)提供高电位，第三反相时钟信号XCK(3)提供低电位时，第一时钟控制反相器TF1导通，第N级GOA单元的第一节点Q(N)的高电位被反相，使得第N+2级GOA单元的第二节点P(N+2)变为低电位，第一节点Q(N+2)变为高电位，然后第三时钟信号CK(3)提供低电位，第三反相时钟信号XCK(3)提 供高电位时，第二时钟控制反相器TF2导通，第N+2级GOA单元的第二节点P(N+2)锁存为低电位，第一节点Q(N+2)锁存为高电位，接着第一时钟信号CK(1)第二次提供高电位，第一反相时钟信号XCK(1)第二次提供低电位时，第一薄膜晶体管T1打开，第二薄膜晶体管T2关闭，第N+2级GOA单元的第二节点P(N+2)的低电位传输到第N+2级GOA单元的第三节点K(N+2)，第三节点K(N+2)的低电位经由第二、第三、及第四反相器IN2、IN3、IN4三次反相后变为高电位，第N+2级GOA单元的栅极扫描驱动信号Gate(N+2)输出高电位，接着所述第一时钟信号CK(1)提供低电位，第一反相时钟信号XCK(1)提供高电位，第一薄膜晶体管T1关闭，第二薄膜晶体管T2导通，第一反相时钟信号XCK(1)的高电位传输到第N+2级GOA单元的第三节点K(N+2)，第三节点K(N+2)的高电位经由第二、第三、及第四反相器IN2、IN3、IN4三次反相后变为低电位，第N+2级GOA单元的栅极扫描驱动信号Gate(N+2)输出低电位，接着第三时钟信号CK(3)再次提供高电位，第三反相时钟信号XCK(3)再次提供低电位，第N级GOA单元的第一节点Q(N)提供低电位，所述第一时钟控制反相器TF1导通，所述第N+2级GOA单元的第二节点P(N+2)变为高电位，第N+2级GOA单元的第一节点Q(N+2)变为低电位，第N+2级GOA单元的栅极扫描驱动信号Gate(N+2)持续输出低电位，依次类推直至最后一级GOA单元。
请参阅图11并结合图6，本发明的CMOS GOA电路的第二实施例正向扫描时的工作过程与所述第一实施例基本相同，区别仅在于第一薄膜晶体管T1的源极直接接入第一节点Q(N)的电位信号，并将第一节点Q(N)的电位信号进行两次反相后输出，减少了一级反相器，能够进一步的减少CMOS GOA电路的晶体管数量，缩小显示产品的边框大小。
请参阅图12，图12为本发明的CMOS GOA电路的反向扫描时的时序图，反向扫描的工作过程与正向扫描一致，只是扫描方向由第一级向最后一级扫描变为由最后一级向第一级扫描，此处不再对工作过程进行赘述。
此外，请参阅图11，在扫描开始前需要先进行复位，复位过程为：复位信号Reset提供低电位脉冲，将各级GOA单元的第三薄膜晶体管T3均打开，恒压高电位VGH写入将各级GOA单元的第二节点P(N)均复位为高电位，第一节点Q(N)复位为低电位，各级栅极扫描驱动信号Gate(N)均输出低电位。
请参阅图13，本发明的CMOS GOA电路应用于双边驱动隔行扫描架构的显示面板，显示面板级联的奇数级GOA单元和级联的偶数级GOA单元分别设置于显示面板的左、右两边，各级GOA单元按照扫描方向从第一 级至最后一级或从最后一级至第一级依次向显示面板内的对应的扫描线输出扫描信号。
综上所述，本发明提供了一种CMOS GOA电路，该CMOS GOA电路的信号处理模块包括第一和第二薄膜晶体管，其中，所述第一薄膜晶体管的栅极接入第一控制信号，源极接入输出节点，漏极电性连接第三节点；所述第二薄膜晶体管的栅极与源极均接入第二控制信号，漏极电性连接第三节点，所述第一控制信号与所述第二控制信号的相位相反，通过所述第一控制信号与第二控制信号控制第一薄膜晶体管与第二薄膜晶体管交替打开，进而将输出节点的电位信号或第二控制信号输入到第三节点，相比于现有技术采用的与非门电路，能够有效减少CMOS GOA电路中的晶体管数量，缩小显示产品的边框大小，有利于实现超窄边框或无边框的显示产品。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (16)

  1. 一种CMOS GOA电路，包括：多级GOA单元，其中奇数级GOA单元级联，偶数级GOA单元级联；
    每一级GOA单元均包括：正反向扫描控制模块、控制输入模块、复位模块、锁存模块、信号处理模块、及输出缓冲模块；
    设M、N均为正整数，除第一级、第二级、倒数第二级、以及最后一级GOA单元外，在第N级GOA单元中：
    所述正反向扫描控制模块接入上两级第N-2级GOA单元的第一节点的电位信号、下两级第N+2级GOA单元的第一节点的电位信号、正向扫描信号、以及反向扫描信号，用于通过正向扫描信号以及反向扫描信号的电位变化控制GOA电路进行正向扫描或反向扫描；
    所述控制输入模块与所述正反向扫描控制模块电性连接并接入第M条时钟信号、第M条反相时钟信号，用于在第M条时钟信号以及第M条反相时钟信号的控制下对正反向扫描控制模块传输来的上两级第N-2级GOA单元的第一节点或下两级第N+2级GOA单元的第一节点的电位信号进行反相并输出到第二节点；
    所述复位模块接入复位信号和恒压高电位信号，并与第二节点电性连接，用于在复位信号的控制下对第一节点的电位信号进行清零处理；
    所述锁存模块接入第M条时钟信号、第M条反相时钟信号，并电性连接第一节点和第二节点，用于将第二节点的电位信号反相后输出到第一节点，并在第M条时钟信号和第M条反相时钟信号的控制下锁存第一节点的电位信号，保持所述第一节点和第二节点的电位信号的相位相反；
    所述信号处理模块包括：第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管的栅极接入第一控制信号，源极接入输出节点，漏极电性连接第三节点；所述第二薄膜晶体管的栅极与源极均接入第二控制信号，漏极电性连接第三节点，所述第一控制信号与所述第二控制信号的相位相反，通过所述第一控制信号与第二控制信号控制第一薄膜晶体管与第二薄膜晶体管交替打开，将输出节点的电位信号或第二控制信号输入到第三节点；
    所述输出缓冲模块电性连接于第三节点，用于将第三节点的电位信号进行数次反相后作为栅极扫描驱动信号输出。
  2. 如权利要求1所述的CMOS GOA电路，其中，所述第一薄膜晶体管与第二薄膜晶体管均为N型薄膜晶体管，所述输出节点为第二节点，第 一控制信号为第M+2条时钟信号，第二控制信号为第M+2条反相时钟信号，所述输出缓冲模块对所述第三节点的电位信号进行奇数次反相后作为栅极扫描驱动信号输出。
  3. 如权利要求1所述的CMOS GOA电路，其中，所述第一薄膜晶体管与第二薄膜晶体管均为P型薄膜晶体管，所述输出节点为第一节点，第一控制信号为第M+2条反相时钟信号，第二控制信号为第M+2条时钟信号，所述输出缓冲模块对所述第三节点的电位信号进行偶数次反相后作为栅极扫描驱动信号输出。
  4. 如权利要求1所述的CMOS GOA电路，其中，所述正反向扫描控制模块包括：第一传输门以及第二传输门，所述控制输入模块包括：第一时钟控制反相器，所述复位模块包括：第三薄膜晶体管，所述锁存模块包括：第二时钟控制反相器、以及第一反相器；
    所述第一传输门的低电位控制端接入正向扫描信号，高电位控制端接入反向扫描信号，输入端电性连接于上两级第N-2级GOA单元的第一节点，输出端电性连接于第一时钟控制反相器的输入端；
    所述第二传输门的高电位控制端接入正向扫描信号，低电位控制端接入反向扫描信号，输入端电性连接于下两级第N+2级GOA单元的第一节点，输出端电性连接于第一时钟控制反相器的输入端；
    所述第一时钟控制反相器的高电位控制端接入第M条时钟信号，低电位控制端接入第M条反相时钟信号，输出端电性连接于第二节点；
    所述第三薄膜晶体管为P型薄膜晶体管，其栅极接入复位信号，源极接入恒压高电位信号，漏极电性连接于第二节点；
    所述第二时钟控制反相器的低电位控制端接入第M条时钟信号，高电位控制端接入第M条反相时钟信号，输入端电性连接于第一节点，输出端电性连接于第二节点；
    所述第一反相器的输入端电性连接于第二节点，输出端电性连接于第一节点。
  5. 如权利要求2所述的CMOS GOA电路，其中，所述输出缓冲模块包括：第二反相器、第三反相器、以及第四反相器；所述第二反相器的输入端电性连接第三节点，输出端电性连接于第三反相器的输入端，所述第三反相器的输出端电性连接于第四反相器的输入端，所述第四反相器的输出端输出栅极扫描驱动信号。
  6. 如权利要求3所述的CMOS GOA电路，其中，所述输出缓冲模块包括：第二反相器、第三反相器，所述第二反相器的输入端电性连接第三 节点，输出端电性连接于第三反相器的输入端，所述第三反相器的输出端输出栅极扫描驱动信号。
  7. 如权利要求3所述的CMOS GOA电路，其中，所述时钟信号包括四条时钟信号：第一条时钟信号、第二条时钟信号、第三条时钟信号、及第四条时钟信号；当第M条时钟信号为第三条时钟信号时，第M+2条时钟信号为第一条时钟信号，当第M条时钟信号为第四条时钟信号时，第M+2条时钟信号为第二条时钟信号；
    级联的奇数级GOA单元接入第一条时钟信号与第三条时钟信号，级联的偶数级GOA单元接入第二条时钟信号与第四条时钟信号。
  8. 如权利要求4所述的CMOS GOA电路，其中，当所述正向扫描信号提供低电位且反向扫描信号提供高电位时，进行正向扫描；当所述正向扫描信号提供高电位且反向扫描信号提供低电位时，进行反向扫描。
  9. 如权利要求4所述的CMOS GOA电路，其中，在第一级和第二级GOA单元中，所述第一传输门的输入端接入电路的起始信号；
    在倒数第二级和最后一级GOA单元中，所述第二传输门的输入端接入电路的起始信号。
  10. 如权利要求1所述的CMOS GOA电路，其中，应用于双边驱动隔行扫描架构的显示面板，所述级联的奇数级GOA单元和级联的偶数级GOA单元分别设置于显示面板的左、右两边。
  11. 一种CMOS GOA电路，包括：多级GOA单元，其中奇数级GOA单元级联，偶数级GOA单元级联；
    每一级GOA单元均包括：正反向扫描控制模块、控制输入模块、复位模块、锁存模块、信号处理模块、及输出缓冲模块；
    设M、N均为正整数，除第一级、第二级、倒数第二级、以及最后一级GOA单元外，在第N级GOA单元中：
    所述正反向扫描控制模块接入上两级第N-2级GOA单元的第一节点的电位信号、下两级第N+2级GOA单元的第一节点的电位信号、正向扫描信号、以及反向扫描信号，用于通过正向扫描信号以及反向扫描信号的电位变化控制GOA电路进行正向扫描或反向扫描；
    所述控制输入模块与所述正反向扫描控制模块电性连接并接入第M条时钟信号、第M条反相时钟信号，用于在第M条时钟信号以及第M条反相时钟信号的控制下对正反向扫描控制模块传输来的上两级第N-2级GOA单元的第一节点或下两级第N+2级GOA单元的第一节点的电位信号进行反相并输出到第二节点；
    所述复位模块接入复位信号和恒压高电位信号，并与第二节点电性连接，用于在复位信号的控制下对第一节点的电位信号进行清零处理；
    所述锁存模块接入第M条时钟信号、第M条反相时钟信号，并电性连接第一节点和第二节点，用于将第二节点的电位信号反相后输出到第一节点，并在第M条时钟信号和第M条反相时钟信号的控制下锁存第一节点的电位信号，保持所述第一节点和第二节点的电位信号的相位相反；
    所述信号处理模块包括：第一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管的栅极接入第一控制信号，源极接入输出节点，漏极电性连接第三节点；所述第二薄膜晶体管的栅极与源极均接入第二控制信号，漏极电性连接第三节点，所述第一控制信号与所述第二控制信号的相位相反，通过所述第一控制信号与第二控制信号控制第一薄膜晶体管与第二薄膜晶体管交替打开，将输出节点的电位信号或第二控制信号输入到第三节点；
    所述输出缓冲模块电性连接于第三节点，用于将第三节点的电位信号进行数次反相后作为栅极扫描驱动信号输出；
    其中，所述第一薄膜晶体管与第二薄膜晶体管均为N型薄膜晶体管，所述输出节点为第二节点，第一控制信号为第M+2条时钟信号，第二控制信号为第M+2条反相时钟信号，所述输出缓冲模块对所述第三节点的电位信号进行奇数次反相后作为栅极扫描驱动信号输出；
    其中，应用于双边驱动隔行扫描架构的显示面板，所述级联的奇数级GOA单元和级联的偶数级GOA单元分别设置于显示面板的左、右两边。
  12. 如权利要求11所述的CMOS GOA电路，其中，所述正反向扫描控制模块包括：第一传输门以及第二传输门，所述控制输入模块包括：第一时钟控制反相器，所述复位模块包括：第三薄膜晶体管，所述锁存模块包括：第二时钟控制反相器、以及第一反相器；
    所述第一传输门的低电位控制端接入正向扫描信号，高电位控制端接入反向扫描信号，输入端电性连接于上两级第N-2级GOA单元的第一节点，输出端电性连接于第一时钟控制反相器的输入端；
    所述第二传输门的高电位控制端接入正向扫描信号，低电位控制端接入反向扫描信号，输入端电性连接于下两级第N+2级GOA单元的第一节点，输出端电性连接于第一时钟控制反相器的输入端；
    所述第一时钟控制反相器的高电位控制端接入第M条时钟信号，低电位控制端接入第M条反相时钟信号，输出端电性连接于第二节点；
    所述第三薄膜晶体管为P型薄膜晶体管，其栅极接入复位信号，源极接入恒压高电位信号，漏极电性连接于第二节点；
    所述第二时钟控制反相器的低电位控制端接入第M条时钟信号，高电位控制端接入第M条反相时钟信号，输入端电性连接于第一节点，输出端电性连接于第二节点；
    所述第一反相器的输入端电性连接于第二节点，输出端电性连接于第一节点。
  13. 如权利要求11所述的CMOS GOA电路，其中，所述输出缓冲模块包括：第二反相器、第三反相器、以及第四反相器；所述第二反相器的输入端电性连接第三节点，输出端电性连接于第三反相器的输入端，所述第三反相器的输出端电性连接于第四反相器的输入端，所述第四反相器的输出端输出栅极扫描驱动信号。
  14. 如权利要求11所述的CMOS GOA电路，其中，所述时钟信号包括四条时钟信号：第一条时钟信号、第二条时钟信号、第三条时钟信号、及第四条时钟信号；当第M条时钟信号为第三条时钟信号时，第M+2条时钟信号为第一条时钟信号，当第M条时钟信号为第四条时钟信号时，第M+2条时钟信号为第二条时钟信号；
    级联的奇数级GOA单元接入第一条时钟信号与第三条时钟信号，级联的偶数级GOA单元接入第二条时钟信号与第四条时钟信号。
  15. 如权利要求12所述的CMOS GOA电路，其中，当所述正向扫描信号提供低电位且反向扫描信号提供高电位时，进行正向扫描；当所述正向扫描信号提供高电位且反向扫描信号提供低电位时，进行反向扫描。
  16. 如权利要求12所述的CMOS GOA电路，其中，在第一级和第二级GOA单元中，所述第一传输门的输入端接入电路的起始信号；
    在倒数第二级和最后一级GOA单元中，所述第二传输门的输入端接入电路的起始信号。
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CN107516505B (zh) * 2017-10-19 2021-01-15 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示面板
CN107633817B (zh) 2017-10-26 2023-12-05 京东方科技集团股份有限公司 源极驱动单元及其驱动方法、源极驱动电路、显示装置
CN107993620B (zh) * 2017-11-17 2020-01-10 武汉华星光电技术有限公司 一种goa电路
CN108109667B (zh) * 2017-12-15 2021-01-15 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示装置、驱动方法
CN108520725A (zh) * 2018-04-20 2018-09-11 京东方科技集团股份有限公司 一种源极驱动电路、显示设备及驱动方法
CN111403311B (zh) * 2020-04-07 2022-12-06 深圳市华星光电半导体显示技术有限公司 Goa电路、显示面板及修复方法
CN112185297B (zh) * 2020-10-26 2023-12-05 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动方法，栅极驱动电路和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100231497A1 (en) * 2009-03-13 2010-09-16 Yi-Suei Liao Display device providing bi-directional voltage stabilization
CN103915052A (zh) * 2013-01-05 2014-07-09 北京京东方光电科技有限公司 一种栅极驱动电路、方法及显示装置
CN104282287A (zh) * 2014-10-31 2015-01-14 合肥鑫晟光电科技有限公司 一种goa单元及驱动方法、goa电路和显示装置
CN105118463A (zh) * 2015-09-22 2015-12-02 深圳市华星光电技术有限公司 一种goa电路及液晶显示器
CN105427821A (zh) * 2015-12-25 2016-03-23 武汉华星光电技术有限公司 适用于In Cell型触控显示面板的GOA电路

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0320556B1 (en) * 1987-12-15 1991-02-27 International Business Machines Corporation Improved reference voltage generator for cmos memories
JP4005086B2 (ja) * 2003-01-20 2007-11-07 株式会社ルネサステクノロジ 半導体集積回路
US7289594B2 (en) * 2004-03-31 2007-10-30 Lg.Philips Lcd Co., Ltd. Shift registrer and driving method thereof
FR2920907B1 (fr) * 2007-09-07 2010-04-09 Thales Sa Circuit de commande des lignes d'un ecran plat a matrice active.
JP5669453B2 (ja) * 2010-06-22 2015-02-12 株式会社ジャパンディスプレイ 双方向シフトレジスタ、及びこれを用いた画像表示装置
CN102682727B (zh) * 2012-03-09 2014-09-03 北京京东方光电科技有限公司 移位寄存器单元、移位寄存器电路、阵列基板及显示器件
KR102128579B1 (ko) * 2014-01-21 2020-07-01 삼성디스플레이 주식회사 게이트 구동 회로 및 이를 구비한 표시 장치
CN104269132B (zh) * 2014-10-29 2016-08-03 京东方科技集团股份有限公司 一种移位寄存单元、显示面板和显示装置
CN104778928B (zh) * 2015-03-26 2017-04-05 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
CN105096891B (zh) * 2015-09-02 2017-03-29 深圳市华星光电技术有限公司 Cmos goa电路
CN105070263B (zh) * 2015-09-02 2017-06-27 深圳市华星光电技术有限公司 Cmos goa电路
CN105118466B (zh) * 2015-09-23 2018-02-09 深圳市华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
CN105185338B (zh) * 2015-09-28 2018-01-30 武汉华星光电技术有限公司 Cmos goa电路
CN105702223B (zh) * 2016-04-21 2018-01-30 武汉华星光电技术有限公司 减小时钟信号负载的cmos goa电路
CN105788557B (zh) * 2016-05-20 2018-06-19 武汉华星光电技术有限公司 Goa驱动电路
CN105810165B (zh) * 2016-05-20 2018-09-28 武汉华星光电技术有限公司 一种cmos goa电路结构及液晶显示面板
CN106057131B (zh) * 2016-05-27 2018-11-23 武汉华星光电技术有限公司 扫描驱动电路及具有该电路的平面显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100231497A1 (en) * 2009-03-13 2010-09-16 Yi-Suei Liao Display device providing bi-directional voltage stabilization
CN103915052A (zh) * 2013-01-05 2014-07-09 北京京东方光电科技有限公司 一种栅极驱动电路、方法及显示装置
CN104282287A (zh) * 2014-10-31 2015-01-14 合肥鑫晟光电科技有限公司 一种goa单元及驱动方法、goa电路和显示装置
CN105118463A (zh) * 2015-09-22 2015-12-02 深圳市华星光电技术有限公司 一种goa电路及液晶显示器
CN105427821A (zh) * 2015-12-25 2016-03-23 武汉华星光电技术有限公司 适用于In Cell型触控显示面板的GOA电路

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