WO2019227807A1 - Goa电路 - Google Patents

Goa电路 Download PDF

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Publication number
WO2019227807A1
WO2019227807A1 PCT/CN2018/108054 CN2018108054W WO2019227807A1 WO 2019227807 A1 WO2019227807 A1 WO 2019227807A1 CN 2018108054 W CN2018108054 W CN 2018108054W WO 2019227807 A1 WO2019227807 A1 WO 2019227807A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
node
clock signal
signal
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PCT/CN2018/108054
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English (en)
French (fr)
Inventor
李亚锋
邬金芳
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/308,813 priority Critical patent/US10796656B1/en
Publication of WO2019227807A1 publication Critical patent/WO2019227807A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technology, and in particular, to a GOA circuit.
  • Liquid crystal display (Liquid Crystal Display, LCD) has many advantages such as thin body, power saving, no radiation, etc., and has been widely used. Such as: LCD TVs, mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens, etc., which dominate the flat panel display field.
  • LCD Liquid Crystal Display
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of a liquid crystal display panel is to inject liquid crystal molecules between a thin film transistor array substrate (TFT array substrate, TFT array substrate) and a color filter substrate (Color Filter, CF), and apply driving to the two substrates.
  • the voltage controls the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture.
  • each pixel is electrically connected to a thin film transistor (TFT), the gate of the thin film transistor is connected to a horizontal scanning line, the source is connected to a vertical data line, and the drain (Drain ) Is connected to the pixel electrode.
  • TFT thin film transistor
  • the driving of the horizontal scanning lines of the active liquid crystal display panel is mainly completed by an external integrated circuit board (IC).
  • IC integrated circuit board
  • the GOA technology (Gate, Driver, Array) is the array substrate row driving technology, which can use the array process of the liquid crystal display panel to fabricate the gate driving circuit on the TFT array substrate to realize the driving method of the progressive scanning of the gate.
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product costs, and can make liquid crystal display panels more suitable for making narrow or borderless display products.
  • An existing GOA circuit includes a multi-level GOA unit, and each GOA unit includes a forward and reverse scanning control module, an output module, and a pull-down module.
  • the forward and reverse scan control module controls the potential of the first node according to the scan signal of the n-2th GOA unit, the scan signal of the n + 2th GOA unit, the forward scan control signal, and the reverse scan control signal.
  • the output module outputs a scanning signal according to the potential of the first node and the first clock signal.
  • the pull-down module pulls down the potential of the scan signal according to the second clock signal and maintains the potential of the first node at a low potential.
  • the pull-down module is provided with a thin-film transistor.
  • the gate of the thin-film transistor is electrically connected to the second node, the source is connected to a constant voltage low potential, the drain is electrically connected to the first node, and the second node is used for the pull-down scanning signal potential. Node. In an ideal state, when the first node is at a high potential and the voltage at the second node is at a low potential, the thin film transistor is turned off at this time, and the constant voltage and low potential will not affect the potential of the first node.
  • the drain-source voltage difference of the thin film transistor is the difference between the high potential of the first node and the constant voltage low potential, and the high potential of the first node is generally close to the constant voltage high potential, so that At this time, the drain-source voltage difference of the thin-film transistor is close to the difference between the constant-voltage high potential and the constant-voltage low potential.
  • the thin-film transistor is prone to leakage, which makes the constant-voltage low potential. Pulling the potential of the first node down by mistake will not guarantee the normal output of the scanning signal, which will affect the quality of the display.
  • the purpose of the present invention is to provide a GOA circuit, which can avoid the leakage current generated by the thin film transistor due to noise and coupling at the second node, and ensure the normal output of the scanning signal.
  • the present invention first provides a GOA circuit, including: a multi-level GOA unit, each level of the GOA unit includes: a forward and reverse scanning control module, an output module, a second node control module, and a first node control module And output control module;
  • N and M be positive integers, N ⁇ 3, in the Nth GOA unit:
  • the forward and reverse scan control module is configured to control the potential of the first node according to the scan signal of the N-2 level GOA unit, the scan signal of the N + 2 level GOA unit, the forward scan control signal, and the reverse scan control signal. ;
  • the output module is configured to output a scanning signal according to the Mth clock signal and the potential of the first node
  • the second node control module is configured to control the potential of the second node according to the M + 2 clock signal, the potential of the first node, and the constant voltage low potential;
  • the output control module is configured to pull down the potential of the scanning signal according to the potential of the second node and the constant voltage and low potential;
  • the first node control module includes a tenth thin film transistor, an eleventh thin film transistor, and a twelfth thin film transistor; a gate of the tenth thin film transistor is electrically connected to a second node, and a source is connected to a constant voltage low potential, The drain is electrically connected to the source of the twelfth thin film transistor; the gate of the eleventh thin film transistor is electrically connected to the second node, the drain is electrically connected to the first node, and the source is electrically connected to the twelfth thin film transistor.
  • the gate of the twelfth thin film transistor is electrically connected to the first node, and the drain is connected to a constant voltage high potential; the tenth thin film transistor, the eleventh thin film transistor, and the twelfth thin film transistor are all N-type thin film transistor.
  • the forward and reverse scanning control module includes a first thin film transistor and a second thin film transistor.
  • the gate of the first thin film transistor is connected to the scanning signal of the N-2 level GOA unit, and the source is connected to the forward scanning control signal.
  • the drain is electrically connected to the first node
  • the gate of the second thin film transistor is connected to the scanning signal of the N + 2 level GOA unit
  • the source is connected to the reverse scanning control signal
  • the drain is electrically connected to the first node.
  • the output module includes a third thin film transistor, a ninth thin film transistor, and a first capacitor.
  • the gate of the ninth thin film transistor is connected to a constant voltage high potential, the source is electrically connected to the first node, and the drain is electrically connected to the first node.
  • the gate of the three thin film transistors; the source of the third thin film transistor is connected to the Mth clock signal, and the drain outputs a scanning signal; the two ends of the first capacitor are electrically connected to the gate of the third thin film transistor and Drain.
  • the second node control module includes a fifth thin film transistor and a sixth thin film transistor; the gate of the fifth thin film transistor is electrically connected to the first node, the source is connected to a constant low voltage potential, and the drain is electrically connected to the second node. Node; the gate and source of the sixth thin film transistor are connected to the M + 2 clock signal, and the drain is electrically connected to the second node.
  • the output control module includes a fourth thin film transistor; a gate of the fourth thin film transistor is electrically connected to the second node, a source is connected to a constant voltage low potential, and a drain is electrically connected to a drain of the third thin film transistor.
  • Each level of GOA unit also includes a reset module, a bootstrap capacitor module, and a global control module;
  • the reset module includes a seventh thin film transistor; the gate and source of the seventh thin film transistor are connected to a reset signal, The drain is electrically connected to the second node;
  • the bootstrap capacitor module includes a second capacitor, one end of the second capacitor is electrically connected to the second node, and the other end is connected to a constant voltage low potential;
  • the global control module includes a first Eight thin film transistors, the gate of the eighth thin film transistor is connected to a global control signal, the source is connected to a constant voltage low potential, and the drain is electrically connected to the drain of the third thin film transistor.
  • the forward scanning control signal is at a high potential
  • the reverse scanning control signal is at a low potential
  • the forward scanning control signal is at a low potential and the reverse scanning control signal is at a high potential.
  • the GOA circuit includes four clock signals: a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; when the Mth clock signal is the third clock signal, the first The M + 2 clock signals are the first clock signal; when the Mth clock signal is the fourth clock signal, the M + 2 clock signal is the second clock signal.
  • the pulse periods of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are the same, and the falling edge of the previous clock signal and the rising edge of the subsequent clock signal are generated simultaneously.
  • the first node control module of a GOA circuit provided by the present invention includes a tenth thin film transistor, an eleventh thin film transistor, and a twelfth thin film transistor, all of which are N-type thin film transistors.
  • the gate-source voltage difference of the twelfth thin film transistor is its threshold voltage, so that the drain-source voltage difference of the eleventh thin film transistor is also the threshold voltage of the twelfth thin film transistor, so that the tenth thin film
  • the resistance value between the drain of the transistor and the first node is extremely large, which can avoid the occurrence of noise at the second node and the leakage current generated by the tenth thin film transistor when the coupling affects the potential of the first node to ensure the normal output of the scanning signal.
  • FIG. 1 is a circuit diagram of a GOA circuit of the present invention
  • FIG. 2 is a circuit diagram of a first-stage and a second-stage GOA unit of the GOA circuit of the present invention
  • FIG. 3 is a circuit diagram of a penultimate stage and a last stage GOA unit of the GOA circuit of the present invention
  • FIG. 4 is a timing diagram of the GOA circuit of the present invention during forward scanning
  • FIG. 5 is a timing diagram of the GOA circuit of the present invention during reverse scanning.
  • the GOA circuit of the present invention includes: a multi-level GOA unit, each level of the GOA unit includes: a forward and reverse scanning control module 100, an output module 200, a second node control module 300, and a first node The control module 400 and the output control module 500.
  • N and M be positive integers, N ⁇ 3, in the Nth GOA unit:
  • the forward and reverse scanning control module 100 is configured to perform forward scanning control based on the scanning signal G (N-2) of the N-2 level GOA unit, the scanning signal G (N + 2) of the N + 2 level GOA unit, The signal U2D and the reverse scanning control signal D2U control the potential of the first node Q (N).
  • the output module 200 is configured to output a scanning signal G (N) according to the Mth clock signal CK (M) and the potential of the first node Q (N).
  • the second node control module 300 is configured to control the potential of the second node P (N) according to the M + 2 clock signal CK (M + 2), the potential of the first node Q (N), and the constant voltage low potential VGL. .
  • the output control module 500 is configured to pull down the potential of the scan signal G (N) according to the potential of the second node P (N) and the constant voltage low potential VGL.
  • the first node control module 400 includes a tenth thin film transistor T10, an eleventh thin film transistor T11, and a twelfth thin film transistor T12; a gate of the tenth thin film transistor T10 is electrically connected to a second node P (N), The source is connected to the constant voltage low potential VGL, and the drain is electrically connected to the source of the twelfth thin film transistor T12; the gate of the eleventh thin film transistor T11 is electrically connected to the second node P (N), and the drain is electrically The first node Q (N) is electrically connected, and the source is electrically connected to the source of the twelfth thin film transistor T12; the gate of the twelfth thin film transistor T12 is electrically connected to the first node Q (N), and the drain is connected The constant voltage high potential VGH
  • the forward and reverse scan control module 100 includes a first thin film transistor T1 and a second thin film transistor T2.
  • the gate of the first thin film transistor T1 is connected to the scan signal G (N-2) of the N-2 level GOA unit.
  • the source is connected to the forward scanning control signal U2D, the drain is electrically connected to the first node Q (N), and the gate of the second thin film transistor T2 is connected to the scanning signal G (N of the N + 2 level GOA unit). +2), the source is connected to the reverse scanning control signal D2U, and the drain is electrically connected to the first node Q (N).
  • the output module 200 includes a third thin film transistor T3, a ninth thin film transistor T9, and a first capacitor C1.
  • the gate of the ninth thin film transistor T9 is connected to a constant voltage high potential VGH, the source is electrically connected to the first node Q (N), and the drain is electrically connected to the gate of the third thin film transistor T3.
  • the source of the third thin film transistor T3 is connected to the M-th clock signal CK (M), and the drain thereof outputs a scan signal G (N).
  • the two ends of the first capacitor C1 are electrically connected to the gate and the drain of the third thin film transistor T3, respectively.
  • the second node control module 300 includes a fifth thin film transistor T5 and a sixth thin film transistor T6.
  • the gate of the fifth thin film transistor T5 is electrically connected to the first node Q (N)
  • the source is connected to the constant voltage low potential VGL
  • the drain is electrically connected to the second node P (N).
  • the gate and the source of the sixth thin film transistor T6 are both connected to the M + 2th clock signal CK (M + 2), and the drain is electrically connected to the second node P (N).
  • the output terminal control module 500 includes a fourth thin film transistor T4.
  • the gate of the fourth thin film transistor T4 is electrically connected to the second node PN, the source is connected to the constant voltage low potential VGL, and the drain is electrically connected to the drain of the third thin film transistor T3.
  • each stage of the GOA unit further includes a reset module 600, a bootstrap capacitor module 700, and a global control module 800.
  • the reset module 600 includes a seventh thin film transistor T7.
  • the gate and the source of the seventh thin film transistor T7 are both connected to a reset signal Reset, and the drain is electrically connected to the second node P (N).
  • the bootstrap capacitor module 700 includes a second capacitor C2.
  • One end of the second capacitor C2 is electrically connected to the second node P (N), and the other end is connected to the constant voltage low potential VGL.
  • the global control module 800 includes an eighth thin film transistor T8.
  • the gate of the eighth thin film transistor T8 is connected to the global control signal GAS, the source is connected to the constant voltage low potential VGL, and the drain is electrically connected to the third thin film transistor T3. Drain.
  • the setting of the eighth thin film transistor T8 enables the GOA circuit of the present invention to be applied to a touch panel.
  • the eighth thin film transistor T8 of all GOA units can be turned on by the global control signal GAS, and all of the GOA units are turned on.
  • the output terminal is pulled down to facilitate the touch function.
  • Both the transistor T8 and the ninth thin film transistor T9 are N-type thin film transistors.
  • the transistor T8, the ninth thin film transistor T9, the tenth thin film transistor T10, the eleventh thin film transistor T11, and the twelfth thin film transistor T12 are all low temperature polysilicon (LTPS) thin film transistors.
  • LTPS low temperature polysilicon
  • the structure of the first-level and second-level GOA units is similar to that of the N-level GOA unit, except that in the first-level and second-level GOA units, the first thin film transistor T1 The gate is connected to the start signal STV.
  • the structure of the penultimate and final GOA units is similar to that of the Nth GOA unit, except that in the penultimate and final GOA units, the second thin film transistor T2 The gate is connected to the start signal STV.
  • the forward scanning control signal U2D is at a high potential, and the reverse scanning control signal D2U is at a low potential.
  • the forward scanning control signal U2D is at a low potential, and the reverse scanning control signal D2U is at a high potential.
  • the GOA circuit includes four clock signals: a first clock signal CK (1), a second clock signal CK (2), a third clock signal CK (3), and The fourth clock signal CK (4); when the Mth clock signal CK (M) is the third clock signal CK (3), the M + 2th clock signal CK (M + 2) is the first Clock signal CK (1); when the Mth clock signal CK (M) is the fourth clock signal CK (4), the M + 2th clock signal CK (M + 2) is the second clock Signal CK (2).
  • the pulse periods of the first clock signal CK (1), the second clock signal CK (2), the third clock signal CK (3), and the fourth clock signal CK (4) are the same.
  • the falling edge of one clock signal is generated simultaneously with the rising edge of the next clock signal.
  • the working process of the N-th GOA unit of the GOA circuit of the present invention during forward scanning is:
  • the reset signal Reset is high, the seventh thin film transistor T7 is turned on, and the high potential is written to the second node P (N).
  • the fourth thin film transistor T4, the tenth thin film transistor T10, and the eleventh thin film transistor T11 are all turned on.
  • the scan signal G (N) output from the first node Q (N) and the drain of the third thin film transistor T3 is pulled down to the constant voltage low potential VGL.
  • the scanning signal G (N-2) of the N-2 stage GOA unit is high, and the high potential of the forward scanning control signal U2D is written to the first node Q (N) so that the first node Q (N) is high.
  • both the third thin film transistor T3 and the fifth thin film transistor T5 are turned on, and the second node P (N) is at a low potential.
  • the M-th clock signal CK (M) is at a high potential
  • the scan signal G (N) output from the drain of the third thin film transistor T3 is at the same phase as the M-th clock signal CK (M) at a high potential.
  • the M clock signals CK (M) have a low potential
  • the scan signal G (N) output from the drain of the third thin film transistor T3 has the same phase as the M clock signal CK (M) and has a low potential.
  • the scan signal G (N + 2) of the N + 2 level GOA unit is high, the second thin film transistor T2 is turned on, and the first node Q (N) writes the low potential of the reverse scan control signal D2U, and
  • the M + 2 clock signal CK (M + 2) is at a high potential, the sixth thin film transistor T6 is turned on, and the high potential is written into the second node P (N), the fourth thin film transistor T4, and the tenth thin film transistor T10 and the eleventh thin film transistor T11 are all turned on, and the scan signal G (N) output from the drain of the first node Q (N) and the third thin film transistor T3 is pulled down to the constant voltage low potential VGL and maintained at the constant voltage Low potential VGL.
  • the working process of the N-th GOA unit of the GOA circuit of the present invention in reverse scanning is:
  • the reset signal Reset is high, the seventh thin film transistor T7 is turned on, and the high potential is written to the second node P (N).
  • the fourth thin film transistor T4, the tenth thin film transistor T10, and the eleventh thin film transistor T11 are all turned on.
  • the scan signal G (N) output from the first node Q (N) and the drain of the third thin film transistor T3 is pulled down to the constant voltage low potential VGL.
  • the scanning signal G (N + 2) of the N + 2 stage GOA unit is high, and the high potential of the reverse scanning control signal D2U is written into the first node Q (N) to make the first node Q (N) high.
  • both the third thin film transistor T3 and the fifth thin film transistor T5 are turned on, and the second node P (N) is at a low potential.
  • the M-th clock signal CK (M) is at a high potential
  • the scan signal G (N) output from the drain of the third thin film transistor T3 is at the same phase as the M-th clock signal CK (M) at a high potential.
  • the M clock signals CK (M) have a low potential
  • the scan signal G (N) output from the drain of the third thin film transistor T3 has the same phase as the M clock signal CK (M) and has a low potential.
  • the scanning signal G (N-2) of the N-2 stage GOA unit is high, the first thin film transistor T1 is turned on, and the first node Q (N) writes the low potential of the forward scanning control signal U2D, and
  • the M + 2 clock signal CK (M + 2) is at a high potential, the sixth thin film transistor T6 is turned on, and the high potential is written into the second node P (N), the fourth thin film transistor T4, and the tenth thin film transistor T10 and the eleventh thin film transistor T11 are all turned on, and the scan signal G (N) output from the drain of the first node Q (N) and the third thin film transistor T3 is pulled down to the constant voltage low potential VGL and maintained at the constant voltage Low potential VGL.
  • the voltage difference between the gate and the source of the twelfth thin film transistor T12 is its threshold voltage Vth, that is, the first The difference between the high voltage of the node Q (N) and the source voltage of the twelfth thin film transistor T12 is the threshold voltage Vth of the twelfth thin film transistor T12, and the drain of the eleventh thin film transistor T11 is electrically connected to the first node Q (N), the source is electrically connected to the source of the second thin film transistor T12, so that the drain-source voltage difference of the eleventh thin film transistor T11 is also equal to the threshold voltage Vth of the twelfth thin film transistor T12, so at this time,
  • the resistance value between the drain of the tenth thin film transistor T10 and the first node Q (N) is extremely large, which is equivalent to connecting a large resistance in series between the drain of the tenth thin film transistor T10 and
  • the tenth thin film transistor T10 will not generate leakage current, so the high potential of the first node Q (N) will not be affected, so it can be guaranteed
  • the output of the scanning signal G (N) is normal, which solves the problem that the GOA circuit is applied to display
  • the post-stage transmission as a multi-stage scanning signal output capability failure caused by problems such as split screen, the display performance of the display device.
  • the first node control module of the GOA circuit of the present invention includes a tenth thin film transistor, an eleventh thin film transistor, and a twelfth thin film transistor, all of which are N-type thin film transistors.
  • the potential of the first node is high
  • the gate-source voltage difference of the twelfth thin film transistor is its threshold voltage
  • the drain-source voltage difference of the eleventh thin film transistor is also the threshold voltage of the twelfth thin film transistor, so that the drain of the tenth thin film transistor is
  • the resistance value between the first node and the first node is extremely large, which can avoid noise at the second node and the leakage current generated by the tenth thin film transistor when the coupling affects the potential of the first node, and ensure that the output of the scanning signal is normal.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA电路，GOA电路的第一节点控制模块（400）包括均为N型薄膜晶体管的第十薄膜晶体管（T10）、第十一薄膜晶体管（T11）及第十二薄膜晶体管（T12），当第一节点（Q(N)）的电位为高电位时，第十二薄膜晶体管（T12）的栅源极电压差为其阈值电压（Vth），使得第十一薄膜晶体管（T11）的漏源极电压差也为第十二薄膜晶体管（T12）的阈值电压（Vth），从而使第十薄膜晶体管（T10）的漏极与第一节点（Q(N)）之间的电阻值极大，能够避免第二节点（P(N)）发生噪声、耦合时第十薄膜晶体管（T10）产生漏电流对第一节点（Q(N)）电位产生影响，保证扫描信号（G(N)）的输出正常。

Description

GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，源极(Source)连接至垂直方向的数据线，漏极(Drain)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。
而GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是可以运用液晶显示面板的阵列制程将栅极驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
现有的一种GOA电路包括多级GOA单元，每一级GOA单元均包括正反向扫描控制模块、输出模块及下拉模块。正反向扫描控制模块根据第n-2级GOA单元的扫描信号、第n+2级GOA单元的扫描信号、正向扫描控制信号及反向扫描控制信号控制第一节点的电位。输出模块根据第一节 点的电位及第一时钟信号输出扫描信号。下拉模块根据第二时钟信号下拉扫描信号的电位并将第一节点的电位维持在低电位。该下拉模块中设置有一薄膜晶体管，该薄膜晶体管的栅极电性连接第二节点，源极接入恒压低电位，漏极电性连接第一节点，第二节点是用于下拉扫描信号电位的节点。理想状态下，当第一节点为高电位时，第二节点的电压为低电位，此时该薄膜晶体管截止，恒压低电位不会对第一节点的电位造成影响，然而在实际工作中，当第一节点位于高电位阶段时，该薄膜晶体管的漏源极电压差为第一节点的高电位与恒压低电位的差值，而第一节点的高电位一般接近恒压高电位，使得此时该薄膜晶体管的漏源极电压差接近恒压高电位与恒压低电位的差值，此时一旦在第二节点发生噪声、耦合，该薄膜晶体管很容易发生漏电，使得恒压低电位将第一节点的电位误拉低，无法保证扫描信号的输出正常，影响显示的品质。
发明内容
本发明的目的在于提供一种GOA电路，能够避免因在第二节点发生噪声、耦合使薄膜晶体管产生漏电流，保证扫描信号的输出正常。
为实现上述目的，本发明首先提供一种GOA电路，包括：多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块、输出模块、第二节点控制模块、第一节点控制模块及输出端控制模块；
设N和M均为正整数，N≥3，在第N级GOA单元中：
所述正反向扫描控制模块用于根据第N-2级GOA单元的扫描信号、第N+2级GOA单元的扫描信号、正向扫描控制信号及反向扫描控制信号控制第一节点的电位；
所述输出模块用于根据第M条时钟信号及第一节点的电位输出扫描信号；
所述第二节点控制模块用于根据第M+2条时钟信号、第一节点的电位及恒压低电位控制第二节点的电位；
所述输出端控制模块用于根据第二节点的电位及恒压低电位下拉扫描信号的电位；
所述第一节点控制模块包括第十薄膜晶体管、第十一薄膜晶体管及第十二薄膜晶体管；所述第十薄膜晶体管的栅极电性连接第二节点，源极接入恒压低电位，漏极电性连接第十二薄膜晶体管的源极；所述第十一薄膜晶体管的栅极电性连接第二节点，漏极电性连接第一节点，源极电性连接第十二薄膜晶体管的源极；所述第十二薄膜晶体管的栅极电性连接第一节 点，漏极接入恒压高电位；所述第十薄膜晶体管、第十一薄膜晶体管及第十二薄膜晶体管均为N型薄膜晶体管。
所述正反向扫描控制模块包括第一薄膜晶体管及第二薄膜晶体管，所述第一薄膜晶体管的栅极接入第N-2级GOA单元的扫描信号，源极接入正向扫描控制信号，漏极电性连接第一节点，所述第二薄膜晶体管的栅极接入第N+2级GOA单元的扫描信号，源极接入反向扫描控制信号，漏极电性连接第一节点。
所述输出模块包括第三薄膜晶体管、第九薄膜晶体管及第一电容；所述第九薄膜晶体管的栅极接入恒压高电位，源极电性连接第一节点，漏极电性连接第三薄膜晶体管的栅极；所述第三薄膜晶体管的源极接入第M条时钟信号，漏极输出扫描信号；所述第一电容的两端分别电性连接第三薄膜晶体管的栅极和漏极。
所述第二节点控制模块包括第五薄膜晶体管及第六薄膜晶体管；所述第五薄膜晶体管的栅极电性连接第一节点，源极接入恒压低电位，漏极电性连接第二节点；所述第六薄膜晶体管的栅极和源极均接入第M+2条时钟信号，漏极电性连接第二节点。
所述输出端控制模块包括第四薄膜晶体管；所述第四薄膜晶体管的栅极电性连接第二节点，源极接入恒压低电位，漏极电性连接第三薄膜晶体管的漏极。
每一级GOA单元还包括重置模块、自举电容模块及全局控制模块；所述重置模块包括第七薄膜晶体管；所述第七薄膜晶体管的栅极及源极均接入重置信号，漏极电性连接第二节点；所述自举电容模块包括第二电容，所述第二电容的一端电性连接第二节点，另一端接入恒压低电位；所述全局控制模块包括第八薄膜晶体管，所述第八薄膜晶体管的栅极接入全局控制信号，源极接入恒压低电位，漏极电性连接第三薄膜晶体管的漏极。
正向扫描时，所述正向扫描控制信号为高电位，反向扫描控制信号为低电位。
反向扫描时，所述正向扫描控制信号为低电位，反向扫描控制信号为高电位。
所述GOA电路包括四条时钟信号：第一条时钟信号、第二条时钟信号、第三条时钟信号及第四条时钟信号；当所述第M条时钟信号为第三条时钟信号时，第M+2条时钟信号为第一条时钟信号；当所述第M条时钟信号为第四条时钟信号时，第M+2条时钟信号为第二条时钟信号。
所述第一条时钟信号、第二条时钟信号、第三条时钟信号及第四条时 钟信号的脉冲周期相同，前一条时钟信号的下降沿与后一条时钟信号的上升沿同时产生。
本发明的有益效果：本发明提供的一种GOA电路的第一节点控制模块包括均为N型薄膜晶体管的第十薄膜晶体管、第十一薄膜晶体管及第十二薄膜晶体管，当第一节点的电位为高电位时，第十二薄膜晶体管的栅源极电压差为其阈值电压，使得第十一薄膜晶体管的漏源极电压差也为第十二薄膜晶体管的阈值电压，从而使第十薄膜晶体管的漏极与第一节点之间的电阻值极大，能够避免第二节点发生噪声、耦合时第十薄膜晶体管产生漏电流对第一节点电位产生影响，保证扫描信号的输出正常。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的GOA电路的电路图；
图2为本发明的GOA电路的第一级及第二级GOA单元的电路图；
图3为本发明的GOA电路的倒数第二级及最后一级GOA单元的电路图；
图4为本发明的GOA电路在正向扫描时的时序图；
图5为本发明的GOA电路在反向扫描时的时序图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1至图5，本发明的GOA电路包括：多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块100、输出模块200、第二节点控制模块300、第一节点控制模块400及输出端控制模块500。
请参阅图1，设N和M均为正整数，N≥3，在第N级GOA单元中：
所述正反向扫描控制模块100用于根据第N-2级GOA单元的扫描信号G(N-2)、第N+2级GOA单元的扫描信号G(N+2)、正向扫描控制信号U2D及反向扫描控制信号D2U控制第一节点Q(N)的电位。
所述输出模块200用于根据第M条时钟信号CK(M)及第一节点Q(N) 的电位输出扫描信号G(N)。
所述第二节点控制模块300用于根据第M+2条时钟信号CK(M+2)、第一节点Q(N)的电位及恒压低电位VGL控制第二节点P(N)的电位。
所述输出端控制模块500用于根据第二节点P(N)的电位及恒压低电位VGL下拉扫描信号G(N)的电位。所述第一节点控制模块400包括第十薄膜晶体管T10、第十一薄膜晶体管T11及第十二薄膜晶体管T12；所述第十薄膜晶体管T10的栅极电性连接第二节点P(N)，源极接入恒压低电位VGL，漏极电性连接第十二薄膜晶体管T12的源极；所述第十一薄膜晶体管T11的栅极电性连接第二节点P(N)，漏极电性连接第一节点Q(N)，源极电性连接第十二薄膜晶体管T12的源极；所述第十二薄膜晶体管T12的栅极电性连接第一节点Q(N)，漏极接入恒压高电位VGH；所述第十薄膜晶体管T10、第十一薄膜晶体管T11及第十二薄膜晶体管T12均为N型薄膜晶体管。
具体地，请参阅图1，在本发明的一优选实施例中：
所述正反向扫描控制模块100包括第一薄膜晶体管T1及第二薄膜晶体管T2，所述第一薄膜晶体管T1的栅极接入第N-2级GOA单元的扫描信号G(N-2)，源极接入正向扫描控制信号U2D，漏极电性连接第一节点Q(N)，所述第二薄膜晶体管T2的栅极接入第N+2级GOA单元的扫描信号G(N+2)，源极接入反向扫描控制信号D2U，漏极电性连接第一节点Q(N)。
所述输出模块200包括第三薄膜晶体管T3、第九薄膜晶体管T9及第一电容C1。所述第九薄膜晶体管T9的栅极接入恒压高电位VGH，源极电性连接第一节点Q(N)，漏极电性连接第三薄膜晶体管T3的栅极。所述第三薄膜晶体管T3的源极接入第M条时钟信号CK(M)，漏极输出扫描信号G(N)。所述第一电容C1的两端分别电性连接第三薄膜晶体管T3的栅极和漏极。
所述第二节点控制模块300包括第五薄膜晶体管T5及第六薄膜晶体管T6。所述第五薄膜晶体管T5的栅极电性连接第一节点Q(N)，源极接入恒压低电位VGL，漏极电性连接第二节点P(N)。所述第六薄膜晶体管T6的栅极和源极均接入第M+2条时钟信号CK(M+2)，漏极电性连接第二节点P(N)。
所述输出端控制模块500包括第四薄膜晶体管T4。所述第四薄膜晶体管T4的栅极电性连接第二节点PN，源极接入恒压低电位VGL，漏极电性连接第三薄膜晶体管T3的漏极。
具体地，请参阅图1，每一级GOA单元还包括重置模块600、自举电容模块700及全局控制模块800；所述重置模块600包括第七薄膜晶体管 T7。所述第七薄膜晶体管T7的栅极及源极均接入重置信号Reset，漏极电性连接第二节点P(N)。所述自举电容模块700包括第二电容C2，所述第二电容C2的一端电性连接第二节点P(N)，另一端接入恒压低电位VGL。所述全局控制模块800包括第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极接入全局控制信号GAS，源极接入恒压低电位VGL，漏极电性连接第三薄膜晶体管T3的漏极。第八薄膜晶体管T8的设置使得本发明的GOA电路在应用于触控面板时，在触控阶段，可通过全局控制信号GAS控制所有GOA单元的第八薄膜晶体管T8导通，将所有GOA单元的输出端电位拉低，以便于实现触控功能。
具体地，所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8及第九薄膜晶体管T9均为N型薄膜晶体管。
优选地，所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11及第十二薄膜晶体管T12均为低温多晶硅(LTPS)薄膜晶体管。
具体地，请参阅图2，第一级及第二级GOA单元与第N级GOA单元的结构类似，区别仅在于：在第一级及第二级GOA单元中，所述第一薄膜晶体管T1的栅极接入起始信号STV。请参阅图3，倒数第二级及最后一级GOA单元与第N级GOA单元的结构类似，区别仅在于：在倒数第二级及最后一级GOA单元中，所述第二薄膜晶体管T2的栅极接入起始信号STV。
具体地，正向扫描时，所述正向扫描控制信号U2D为高电位，反向扫描控制信号D2U为低电位。反向扫描时，所述正向扫描控制信号U2D为低电位，反向扫描控制信号D2U为高电位。
具体地，请参阅图4及图5，所述GOA电路包括四条时钟信号：第一条时钟信号CK(1)、第二条时钟信号CK(2)、第三条时钟信号CK(3)及第四条时钟信号CK(4)；当所述第M条时钟信号CK(M)为第三条时钟信号CK(3)时，第M+2条时钟信号CK(M+2)为第一条时钟信号CK(1)；当所述第M条时钟信号CK(M)为第四条时钟信号CK(4)时，第M+2条时钟信号CK(M+2)为第二条时钟信号CK(2)。
进一步地，所述第一条时钟信号CK(1)、第二条时钟信号CK(2)、第三条时钟信号CK(3)及第四条时钟信号CK(4)的脉冲周期相同，前一条时钟信 号的下降沿与后一条时钟信号的上升沿同时产生。
结合图1及图4，本发明的GOA电路的第N级GOA单元在正向扫描时的工作过程为：
首先，重置信号Reset为高电位，第七薄膜晶体管T7导通，高电位写入第二节点P(N)，第四薄膜晶体管T4、第十薄膜晶体管T10、第十一薄膜晶体管T11均导通，第一节点Q(N)及第三薄膜晶体管T3漏极输出的扫描信号G(N)均被拉低至恒压低电位VGL。之后，第N-2级GOA单元的扫描信号G(N-2)为高电位，正向扫描控制信号U2D的高电位写入第一节点Q(N)使第一节点Q(N)为高电位，第三薄膜晶体管T3及第五薄膜晶体管T5均导通，第二节点P(N)为低电位。接着，第M条时钟信号CK(M)为高电位，第三薄膜晶体管T3漏极输出的扫描信号G(N)与第M条时钟信号CK(M)相位相同，为高电位，随后，第M条时钟信号CK(M)为低电位，第三薄膜晶体管T3漏极输出的扫描信号G(N)与第M条时钟信号CK(M)相位相同，为低电位。之后，第N+2级GOA单元的扫描信号G(N+2)为高电位，第二薄膜晶体管T2导通，第一节点Q(N)写入反向扫描控制信号D2U的低电位，与此同时，第M+2条时钟信号CK(M+2)为高电位，第六薄膜晶体管T6导通，高电位写入第二节点P(N)，第四薄膜晶体管T4、第十薄膜晶体管T10、第十一薄膜晶体管T11均导通，第一节点Q(N)及第三薄膜晶体管T3漏极输出的扫描信号G(N)均被拉低至恒压低电位VGL并维持在恒压低电位VGL。
结合图1及图5，本发明的GOA电路的第N级GOA单元在反向扫描的工作过程为：
首先，重置信号Reset为高电位，第七薄膜晶体管T7导通，高电位写入第二节点P(N)，第四薄膜晶体管T4、第十薄膜晶体管T10、第十一薄膜晶体管T11均导通，第一节点Q(N)及第三薄膜晶体管T3漏极输出的扫描信号G(N)均被拉低至恒压低电位VGL。之后，第N+2级GOA单元的扫描信号G(N+2)为高电位，反向扫描控制信号D2U的高电位写入第一节点Q(N)使第一节点Q(N)为高电位，第三薄膜晶体管T3及第五薄膜晶体管T5均导通，第二节点P(N)为低电位。接着，第M条时钟信号CK(M)为高电位，第三薄膜晶体管T3漏极输出的扫描信号G(N)与第M条时钟信号CK(M)相位相同，为高电位，随后，第M条时钟信号CK(M)为低电位，第三薄膜晶体管T3漏极输出的扫描信号G(N)与第M条时钟信号CK(M)相位相同，为低电位。之后，第N-2级GOA单元的扫描信号G(N-2)为高电位，第一薄膜晶体管T1导通，第一节点Q(N)写入正向扫描控制信号U2D的低电位，与 此同时，第M+2条时钟信号CK(M+2)为高电位，第六薄膜晶体管T6导通，高电位写入第二节点P(N)，第四薄膜晶体管T4、第十薄膜晶体管T10、第十一薄膜晶体管T11均导通，第一节点Q(N)及第三薄膜晶体管T3漏极输出的扫描信号G(N)均被拉低至恒压低电位VGL并维持在恒压低电位VGL。
需要说明的是，本发明的GOA电路中，当第一节点Q(N)为高电位时，第十二薄膜晶体管T12的栅源极之间的电压差为其阈值电压Vth，也即第一节点Q(N)的高电压与第十二薄膜晶体管T12的源极电压的差值为第十二薄膜晶体管T12的阈值电压Vth，而第十一薄膜晶体管T11的漏极电性连接第一节点Q(N)，源极与第二薄膜晶体管T12的源极电性连接，使得第十一薄膜晶体管T11的漏源极电压差也等于第十二薄膜晶体管T12的阈值电压Vth，从而此时，第十薄膜晶体管T10的漏极与第一节点Q(N)之间的电阻值极大，相当于在第十薄膜晶体管T10的漏极与第一节点Q(N)之间串联了一个大电阻，因此即使此时第二节点P(N)发生噪声、耦合，所述第十薄膜晶体管T10也不会产生漏电流，因此第一节点Q(N)的高电位不会受到影响，因此能够保证扫描信号G(N)的输出正常，进而解决在该GOA电路应用于显示装置中时，在多级级传后因为扫描信号输出能力衰竭而造成的分屏等问题，保证了显示装置的显示效果。
综上所述，本发明的GOA电路的第一节点控制模块包括均为N型薄膜晶体管的第十薄膜晶体管、第十一薄膜晶体管及第十二薄膜晶体管，当第一节点的电位为高电位时，第十二薄膜晶体管的栅源极电压差为其阈值电压，使得第十一薄膜晶体管的漏源极电压差也为第十二薄膜晶体管的阈值电压，从而使第十薄膜晶体管的漏极与第一节点之间的电阻值极大，能够避免第二节点发生噪声、耦合时第十薄膜晶体管产生漏电流对第一节点电位产生影响，保证扫描信号的输出正常。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种GOA电路，包括：多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块、输出模块、第二节点控制模块、第一节点控制模块及输出端控制模块；
    设N和M均为正整数，N≥3，在第N级GOA单元中：
    所述正反向扫描控制模块用于根据第N-2级GOA单元的扫描信号、第N+2级GOA单元的扫描信号、正向扫描控制信号及反向扫描控制信号控制第一节点的电位；
    所述输出模块用于根据第M条时钟信号及第一节点的电位输出扫描信号；
    所述第二节点控制模块用于根据第M+2条时钟信号、第一节点的电位及恒压低电位控制第二节点的电位；
    所述输出端控制模块用于根据第二节点的电位及恒压低电位下拉扫描信号的电位；
    所述第一节点控制模块包括第十薄膜晶体管、第十一薄膜晶体管及第十二薄膜晶体管；所述第十薄膜晶体管的栅极电性连接第二节点，源极接入恒压低电位，漏极电性连接第十二薄膜晶体管的源极；所述第十一薄膜晶体管的栅极电性连接第二节点，漏极电性连接第一节点，源极电性连接第十二薄膜晶体管的源极；所述第十二薄膜晶体管的栅极电性连接第一节点，漏极接入恒压高电位；所述第十薄膜晶体管、第十一薄膜晶体管及第十二薄膜晶体管均为N型薄膜晶体管。
  2. 如权利要求1所述的GOA电路，其中，所述正反向扫描控制模块包括第一薄膜晶体管及第二薄膜晶体管，所述第一薄膜晶体管的栅极接入第N-2级GOA单元的扫描信号，源极接入正向扫描控制信号，漏极电性连接第一节点；所述第二薄膜晶体管的栅极接入第N+2级GOA单元的扫描信号，源极接入反向扫描控制信号，漏极电性连接第一节点。
  3. 如权利要求1所述的GOA电路，其中，所述输出模块包括第三薄膜晶体管、第九薄膜晶体管及第一电容；所述第九薄膜晶体管的栅极接入恒压高电位，源极电性连接第一节点，漏极电性连接第三薄膜晶体管的栅极；所述第三薄膜晶体管的源极接入第M条时钟信号，漏极输出扫描信号；所述第一电容的两端分别电性连接第三薄膜晶体管的栅极和漏极。
  4. 如权利要求1所述的GOA电路，其中，所述第二节点控制模块包 括第五薄膜晶体管及第六薄膜晶体管；所述第五薄膜晶体管的栅极电性连接第一节点，源极接入恒压低电位，漏极电性连接第二节点；所述第六薄膜晶体管的栅极和源极均接入第M+2条时钟信号，漏极电性连接第二节点。
  5. 如权利要求1所述的GOA电路，其中，所述输出端控制模块包括第四薄膜晶体管；所述第四薄膜晶体管的栅极电性连接第二节点，源极接入恒压低电位，漏极电性连接第三薄膜晶体管的漏极。
  6. 如权利要求2所述的GOA电路，其中，每一级GOA单元还包括重置模块、自举电容模块及全局控制模块；所述重置模块包括第七薄膜晶体管；所述第七薄膜晶体管的栅极及源极均接入重置信号，漏极电性连接第二节点；所述自举电容模块包括第二电容，所述第二电容的一端电性连接第二节点，另一端接入恒压低电位；所述全局控制模块包括第八薄膜晶体管，所述第八薄膜晶体管的栅极接入全局控制信号，源极接入恒压低电位，漏极电性连接第三薄膜晶体管的漏极。
  7. 如权利要求1所述的GOA电路，其中，正向扫描时，所述正向扫描控制信号为高电位，反向扫描控制信号为低电位。
  8. 如权利要求1所述的GOA电路，其中，反向扫描时，所述正向扫描控制信号为低电位，反向扫描控制信号为高电位。
  9. 如权利要求1所述的GOA电路，还包括四条时钟信号：第一条时钟信号、第二条时钟信号、第三条时钟信号及第四条时钟信号；当所述第M条时钟信号为第三条时钟信号时，第M+2条时钟信号为第一条时钟信号；当所述第M条时钟信号为第四条时钟信号时，第M+2条时钟信号为第二条时钟信号。
  10. 如权利要求9所述的GOA电路，其中，所述第一条时钟信号、第二条时钟信号、第三条时钟信号及第四条时钟信号的脉冲周期相同，前一条时钟信号的下降沿与后一条时钟信号的上升沿同时产生。
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