WO2019100424A1 - 一种goa电路 - Google Patents

一种goa电路 Download PDF

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Publication number
WO2019100424A1
WO2019100424A1 PCT/CN2017/113532 CN2017113532W WO2019100424A1 WO 2019100424 A1 WO2019100424 A1 WO 2019100424A1 CN 2017113532 W CN2017113532 W CN 2017113532W WO 2019100424 A1 WO2019100424 A1 WO 2019100424A1
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Prior art keywords
thin film
film transistor
signal
goa circuit
gate
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PCT/CN2017/113532
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English (en)
French (fr)
Inventor
管延庆
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武汉华星光电技术有限公司
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Priority to US15/740,632 priority Critical patent/US10672354B2/en
Publication of WO2019100424A1 publication Critical patent/WO2019100424A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/063—Waveforms for resetting the whole screen at once
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit.
  • a liquid crystal display device has been widely used as a display component of an electronic device in various electronic products, and an array substrate row drives a Gate Driver On Array (GOA), which is a thin film transistor (TFT) liquid crystal display.
  • GOA Gate Driver On Array
  • the array process fabricates the gate row scan driving signal circuit on the array substrate to realize the driving mode of the gate progressive scanning, which has the advantages of reducing the production cost and realizing the narrow frame design of the panel, and is used for various displays.
  • Display panels based on Low Temperature Poly-silicon (LTPS) technology can be classified into NMOS type, PMOS type, and CMOS type and PMOS type according to the type of thin film transistor (TFT) used in the panel.
  • TFT thin film transistor
  • GOA circuits are divided into NMOS circuits, PMOS circuits, and CMOS circuits.
  • the NMOS circuit saves the PP (P-doping, that is, phosphorus ion doping) layer mask and process, which is beneficial to improving the yield and reducing the cost, so the development is stable.
  • the NMOS circuit has realistic industrial needs.
  • the large-size liquid crystal display panel has become a major trend in the industry.
  • the GOA load also increases accordingly. Therefore, the size and panel frame of each TFT in the GOA increase, which is disadvantageous. Achieve a narrow bezel of the liquid crystal display panel, and an increase in load will also increase the power consumption of the GOA module.
  • the present invention provides a GOA circuit, which can eliminate the residual image that occurs when the liquid crystal display panel is abnormally powered off, and improve the user experience.
  • the embodiment of the present invention provides a GOA circuit for a liquid crystal display panel, including a cascaded multi-level GOA circuit repeating unit, and each level of the GOA circuit repeating unit includes: a first forward-reverse scanning module 100, The first clock input module 101, the first signal point control module 103, the third signal point control module 104, the first output module 102, the first global signal action module 105, the second forward/reverse scan module 200, and the second clock input The module 201, the second signal point control module 203, the fourth signal point control module 204, the second output module 202, and the second global signal action module 205; wherein:
  • n be a positive integer, in addition to the first stage GOA circuit repeating unit and the last stage GOA circuit repeating unit, in the nth stage GOA circuit repeating unit:
  • the first forward/reverse scan module 100 and the second forward/negative scan module 200 are configured to control the GOA circuit to perform forward scan or reverse scan according to the first scan control signal or the second scan control signal;
  • the first output module 102 and the second output module 202 respectively access the first clock signal CK1, and sequentially output the nth scan signal Gn and the n+2th scan signal Gn by using the first clock signal respectively. +2;
  • the first clock input module 101 is configured to output a second clock signal CK2 or a fourth clock signal CK4 to the third signal point control module 104;
  • the second clock input module 201 is configured to output a fourth a clock signal CK4 or a second clock signal CK2 to the fourth signal point control module 204;
  • the first signal point control module 103 is configured to control the level of the first signal point Q(n) during the action of the nth stage GOA circuit repeating unit;
  • the second signal point control module 203 is configured to be in the nth stage Controlling the level of the second signal point Q'(n) during the action of the GOA circuit repeating unit;
  • the third signal point control module 104 is configured to control a level of the third signal point P(n) during the action of the nth stage GOA circuit repeating unit; the fourth signal point control module 204 is configured to be at the nth Controlling the level of the fourth signal point P'(n) during the action of the stage GOA circuit repeating unit;
  • the first global signal action module 105 and the second global signal action module 205 are configured to implement, when the power is off, all the scan signals in the repeating unit of the nth stage GOA circuit to be turned on by using the first global signal GAS1.
  • the first forward-reverse scan module 100 includes a tenth thin film transistor T10 and a fourteenth thin film transistor T14, and the gate of the tenth thin film transistor is connected to the output of the upper n-1th GOA circuit repeating unit.
  • the n-2th scan signal Gn-2 has a source connected to the first scan control signal, a drain electrically connected to the first node Q(n), and a gate of the fourteenth thin film transistor T14 connected to the nth stage GOA circuit
  • the n+2th scanning signal Gn+2 outputted by the repeating unit is connected to the second scan control signal, and the drain thereof is electrically connected to the first node Q(n);
  • the second forward-reverse-scanning module 200 includes: a twentieth thin film transistor T20 and a twenty-fourth thin film transistor T24, and the gate of the twentieth thin film transistor is connected to the nth of the n-th stage GOA circuit repeating unit output.
  • a strip scan signal Gn whose source is connected to the first scan control signal, whose drain is electrically connected to the second node Q'(n); the gate of the twenty-fourth thin film transistor T24 is connected to the next level n+1th GOA
  • the n+4th scan signal Gn+4 outputted by the circuit repeating unit has a source connected to the second scan control signal and a drain electrically connected to the second node Q'(n).
  • the first forward/reverse scan module 100, the first clock input module 101, the first signal point control module 103, and the first output module 102 are all electrically connected to the first signal point Q(n), and the third The signal point control module 104 and the first global signal action module 105 are both electrically connected to the third signal point P(n); the second forward/reverse scan module 200, the second clock input module 201, and the second signal point control module. 203.
  • the second output module 202 is electrically connected to the second signal point Q'(n), and the fourth signal point control module 204 and the second global signal action module 205 are electrically connected to the fourth signal point P'(n). .
  • the gate of the tenth thin film transistor T10 is connected to the circuit start signal STV;
  • the first stage GOA circuit repeating unit further includes a nineteenth thin film transistor T19, the gate of the nineteenth thin film transistor is connected to the first scan signal G1 outputted by the first stage GOA circuit repeating unit, and the source is connected Constant voltage low potential, the drain of which is connected to the tenth thin film transistor T10 The gate.
  • the gate of the twenty-fourth thin film transistor T24 is connected to the circuit start signal STV;
  • the last stage GOA circuit repeating unit further includes a twenty-ninth thin film transistor T29, the gate of the twenty-ninth thin film transistor being connected to the last scan signal Glast outputted by the last stage GOA circuit repeating unit, the source thereof A constant voltage low potential is connected, and a drain thereof is connected to the gate of the twenty-fourth thin film transistor T24.
  • the first output module 102 includes: a thirtieth thin film transistor T30, a thirty-first thin film transistor T31, and a thirty-second thin film transistor T32.
  • the source of the thirtieth thin film transistor T30 is electrically connected to the first node Q.
  • the gate thereof is connected to a constant voltage high potential;
  • the gate of the 31st thin film transistor T31 is connected to the drain of the thirtieth thin film transistor, and the drain thereof is connected to the first clock signal CK1;
  • the gate of the thirty-second thin film transistor T30 is connected to the third node P(n), the source thereof is connected to the constant voltage low potential, the drain thereof is connected to the source of the thirty-first thin film transistor T31, and is electrically connected
  • the second output module 202 includes: a forty-th thin film transistor T40, a forty-first thin film transistor T41, and a forty-second thin film transistor T42.
  • the source of the fortieth thin film transistor T40 is electrically connected to the second node Q' ( n), the gate is connected to a constant voltage high potential;
  • the fourth eleventh thin film transistor T41 is connected to the drain of the forty-th thin film transistor, and the drain thereof is connected to the first clock signal CK1;
  • the gate of the forty-two thin film transistor T40 is connected to the fourth node P'(n), the source thereof is connected to the constant voltage low potential, the drain thereof is connected to the source of the forty-th thin film transistor T41, and is electrically connected
  • the n+2th scan signal Gn+2 outputted by the unit of the nth stage GOA circuit repeats.
  • the first clock input module 101 includes: an eleventh thin film transistor T11 and a twelfth thin film transistor T12.
  • the gate of the eleventh thin film transistor T11 is connected to the first scan control signal, and the drain is connected.
  • a gate of the twelfth thin film transistor T12 is connected to the second scan control signal, a source thereof is connected to the fourth clock signal CK4, and a drain thereof is connected to the eleventh thin film transistor T11 Source
  • the second clock input module 201 includes: a 21st thin film transistor T21 and a 22nd thin film transistor T22.
  • the gate of the 21st thin film transistor T21 is connected to the first scan control signal, and the drain is connected. Entering a fourth clock signal CK4; a gate of the twenty-second thin film transistor T22
  • the second scan control signal is connected, the source thereof is connected to the second clock signal CK2, and the drain thereof is connected to the source of the 21st thin film transistor T21.
  • the first signal point control module 103 includes a sixteenth thin film transistor T16 and a tenth capacitor C10.
  • the sixteenth thin film transistor T16 is connected to the third signal point P(n), and the drain is connected to the first.
  • Signal point Q(n) whose source is connected to a constant voltage low potential; one end of the tenth capacitor C10 is connected to a constant voltage low potential, and the other end is connected to a first signal point Q(n);
  • the second signal point control module 203 includes a second sixteen thin film transistor T26 and a twentieth capacitor C20.
  • the second sixteen thin film transistor T26 is connected to the fourth signal point P'(n) and has a drain connection.
  • the second signal point Q'(n) has a source connected to the constant voltage low potential; one end of the twentieth capacitor C20 is connected to the constant voltage low potential, and the other end is connected to the second signal point Q'(n).
  • the third signal point control module 104 includes: a thirteenth thin film transistor T13, a fifteenth thin film transistor T15, and an eleventh capacitor C11, and a gate of the thirteenth thin film transistor T13 and the eleventh
  • the source of the thin film transistor T11 is connected, the drain thereof is connected to a constant voltage high potential, and the source thereof is connected to the third node P(n); the gate of the fifteenth thin film transistor T15 is connected to the first signal point Q(n)
  • the drain is connected to the constant voltage low potential, the source thereof is connected to the third signal point P(n); the eleventh capacitor C11 is connected to the constant voltage low potential at one end, and the third signal point P(n) is connected to the other end;
  • the fourth signal point control module 204 includes: a twenty-third thin film transistor T23, a twenty-fifth thin film transistor T25, and a twenty-first capacitor C21.
  • the gate of the twenty-third thin film transistor T23 and the first The source of the twenty-one thin film transistor T21 is connected, the drain thereof is connected to the constant voltage high potential, the source thereof is connected to the fourth node P'(n); the gate of the twenty-fifth thin film transistor T25 is connected to the second
  • the signal point Q'(n) has a drain connected to the constant voltage low potential, and a source connected to the fourth signal point P'(n); the second eleventh capacitor C21 is connected to the constant voltage low potential at one end, and the other end is connected Four signal points P'(n).
  • the first global signal action module 105 includes a seventeenth thin film transistor T17 and an eighteenth thin film transistor T18.
  • the seventeenth thin film transistor T17 has its gate connected to its source and its drain connected to the nth stage GOA circuit.
  • the nth scan signal Gn of the repeating unit; the gate of the eighteenth thin film transistor T18 is connected to the gate of the seventeenth thin film transistor T17, and is connected to the first global signal GAS1, and the drain thereof is connected Three signal points P(n) whose source is connected to a constant voltage low potential;
  • the second global signal action module 205 includes two seventeenth thin film transistors T27 and a twenty-eighth thin film transistor T28, and the gate of the twenty-seventh thin film transistor T27 is connected to the source thereof, and the drain thereof The pole is connected to the n+2th scan signal Gn+2 of the nth stage GOA circuit repeating unit; the gate of the twenty-eighth thin film transistor T28 is connected to the gate of the twenty-seventh thin film transistor T27, and The first global signal GAS1 is connected, the drain thereof is connected to the fourth signal point P'(n), and the source thereof is connected to the constant voltage low potential.
  • the thin film transistors are N-channel thin film transistors.
  • a GOA circuit for a liquid crystal display panel, which includes a cascaded multi-level GOA circuit repeating unit, and each level of the GOA circuit repeating unit includes: a first forward/reverse scan module (100), a first clock input module (101), a first signal point control module (103), a third signal point control module (104), a first output module (102), a first a global signal action module (105), a second forward/reverse scan module (200), a second clock input module (201), a second signal point control module (203), a fourth signal point control module (204), and a second An output module (202) and a second global signal action module (205); wherein:
  • n be a positive integer, in addition to the first stage GOA circuit repeating unit and the last stage GOA circuit repeating unit, in the nth stage GOA circuit repeating unit:
  • the first forward/reverse scan module (100) and the second forward/negative scan module (200) are configured to control the GOA circuit to perform forward scan or reverse according to the first scan control signal or the second scan control signal. scanning;
  • the first output module (102) and the second output module (202) respectively access the first clock signal (CK1), and sequentially output the nth scan signal (Gn) by using the first clock signal, The n+2th scan signal (Gn+2);
  • the first clock input module (101) is configured to output a second clock signal (CK2) or a fourth clock signal (CK4) to the third signal point control module (104); the second clock input The module (201) is configured to output a fourth clock signal (CK4) or a second clock signal (CK2) to the fourth signal point control module (204);
  • the first signal point control module (103) is configured to control a level of the first signal point (Q(n)) during the action of the nth stage GOA circuit repeating unit; the second signal point control module (203) For controlling the level of the second signal point (Q'(n)) during the action of the nth stage GOA circuit repeating unit;
  • the third signal point control module (104) is configured to perform a repeating unit function in the nth stage GOA circuit During the period, the level of the third signal point (P(n)) is controlled; the fourth signal point control module (204) is configured to control the fourth signal point (P' during the action of the nth stage GOA circuit repeating unit n)) level;
  • the first global signal action module (105) and the second global signal action module (205) are configured to implement, when the power is off, all the scan signals in the repeating unit of the nth stage GOA circuit are opened by using the first global signal (GAS1) ;
  • the first global signal action module (105) includes a seventeenth thin film transistor (T17) and an eighteenth thin film transistor (T18), and the gate of the seventeenth thin film transistor (T17) is connected to its source. a drain connected to the nth scan signal (Gn) of the nth stage GOA circuit repeating unit; a gate of the eighteenth thin film transistor (T18) and a gate of the seventeenth thin film transistor (T17) Connected and connected to the first global signal (GAS1), the drain of which is connected to the third signal point (P(n)), and the source thereof is connected to the constant voltage low potential;
  • the second global signal action module (205) includes two seventeenth thin film transistors (T27) and a twenty-eighth thin film transistor (T28), and the gate of the twenty-seventh thin film transistor (T27) is opposite to the source thereof. Connected, the drain thereof is connected to the n+2th scan signal (Gn+2) of the n-th stage GOA circuit repeating unit; the gate of the twenty-eighth thin film transistor (T28) and the twenty-seventh thin film transistor The gate of (T27) is connected and connected to the first global signal (GAS1), the drain thereof is connected to the fourth signal point (P'(n)), and the source thereof is connected to the constant voltage low potential.
  • GAS1 first global signal
  • P'(n) fourth signal point
  • the first forward/reverse scan module (100), the first clock input module (101), the first signal point control module (103), and the first output module (102) are all electrically connected to the first signal point ( Q(n)), the third signal point control module (104) and the first global signal action module (105) are both electrically connected to the third signal point (P(n)); the second forward and reverse scan The module (200), the second clock input module (201), the second signal point control module (203), and the second output module (202) are all electrically connected to the second signal point (Q'(n)), wherein the The four signal point control module (204) and the second global signal action module (205) are electrically coupled to the fourth signal point (P'(n)).
  • the first forward-reverse scan module (100) includes: a tenth thin film transistor (T10) and a fourteenth thin film transistor (T14), and the gate of the tenth thin film transistor is connected to the first level n-1
  • the nth scan signal (Gn-2) output by the GOA circuit repeating unit is connected to the first scan control signal No., its drain is electrically connected to the first node (Q(n));
  • the gate of the fourteenth thin film transistor (T14) is connected to the n+2th scan signal of the nth stage GOA circuit repeating unit output (Gn+2
  • the source is connected to the second scan control signal, and the drain thereof is electrically connected to the first node (Q(n));
  • the second forward-reverse scan module (200) includes: a twentieth thin film transistor (T20) and a twenty-fourth thin film transistor (T24), and a gate of the twentieth thin film transistor is connected to the nth-level GOA circuit
  • the nth scan signal (Gn) outputted by the repeating unit has a source connected to the first scan control signal, a drain electrically connected to the second node (Q'(n)), and a gate of the twenty-fourth thin film transistor (T24)
  • the pole is connected to the n+4th scan signal (Gn+4) outputted by the repeating unit of the n+1th GOA circuit of the next stage, the source thereof is connected to the second scan control signal, and the drain thereof is electrically connected to the second node (Q '(n)).
  • the gate of the tenth thin film transistor (T10) is connected to the circuit start signal (STV);
  • the first stage GOA circuit repeating unit further includes a nineteenth thin film transistor (T19), the gate of the nineteenth thin film transistor being connected to the first scan signal (G1) output by the first stage GOA circuit repeating unit,
  • the source is connected to a constant voltage low potential, and its drain is connected to the gate of the tenth thin film transistor (T10).
  • the gate of the twenty-fourth thin film transistor (T24) is connected to the circuit start signal (STV);
  • the last stage GOA circuit repeating unit further includes a twenty-nineth thin film transistor (T29), and the gate of the twenty-ninth thin film transistor is connected to the last scan signal (Glast) outputted by the last stage GOA circuit repeating unit.
  • the source is connected to the constant voltage low potential, and the drain thereof is connected to the gate of the twenty-fourth thin film transistor (T24).
  • the first output module (102) includes: a thirtieth thin film transistor (T30), a thirty-first thin film transistor (T31), and a thirty-second thin film transistor (T32), the thirtieth thin film transistor ( T30) the source is electrically connected to the first node Q(n), and the gate thereof is connected to the constant voltage high potential; the gate of the 31st thin film transistor (T31) is connected to the drain of the thirtieth thin film transistor, and the drain thereof The pole is connected to the first clock signal (CK1); the gate of the thirty-second thin film transistor (T30) is connected to the third node (P(n)), and the source thereof is connected to the constant voltage low potential, and the drain thereof is The source of the 31st thin film transistor (T31) is connected and electrically connected to the nth scan signal (Gn) outputted by the nth stage GOA circuit repeating unit;
  • the second output module (202) includes: a fortieth thin film transistor (T40), a forty-first thin film transistor (T41), and a forty-second thin film transistor (T42), the fortieth thin film transistor (T40)
  • the source is electrically connected to the second node (Q'(n)), the gate thereof is connected to the constant voltage high potential;
  • the gate of the forty-th thin film transistor (T41) is connected to the drain of the fortieth thin film transistor, The drain is connected to the first clock signal (CK1);
  • the gate of the forty-second thin film transistor (T40) is connected to the fourth node (P'(n)), and the source thereof is connected to the constant voltage low potential, and the drain thereof
  • the pole is connected to the source of the forty-th thin film transistor (T41), and is electrically connected to the n+2th scan signal (Gn+2) outputted by the n-th stage GOA circuit repeating unit.
  • the first clock input module (101) includes: an eleventh thin film transistor (T11), a twelfth thin film transistor (T12), and a gate of the eleventh thin film transistor (T11) is connected to the first scan. a control signal, the drain of which is connected to the second clock signal (CK2); the gate of the twelfth thin film transistor (T12) is connected to the second scan control signal, and the source thereof is connected to the fourth clock signal (CK4) a drain connected to a source of the eleventh thin film transistor (T11);
  • the second clock input module (201) includes: a twenty-first thin film transistor (T21), a twenty-second thin film transistor (T22), and a gate of the twenty-first thin film transistor (T21) is first connected Scanning the control signal, the drain of which is connected to the fourth clock signal (CK4); the gate of the twenty-second thin film transistor (T22) is connected to the second scan control signal, and the source thereof is connected to the second clock signal (CK2), whose drain is connected to the source of the twenty-first thin film transistor (T21).
  • the first signal point control module (103) includes a sixteenth thin film transistor (T16) and a tenth capacitor (C10), and the sixteenth thin film transistor (T16) gate is connected to the third signal point (P( n)), the drain is connected to the first signal point (Q(n)), and the source thereof is connected to the constant voltage low potential; one end of the tenth capacitor (C10) is connected to the constant voltage low potential, and the other end is connected to the first Signal point (Q(n));
  • the second signal point control module (203) includes a second sixteen thin film transistor (T26) and a twentieth capacitor (C20), and the second sixteen thin film transistor (T26) gate is connected to the fourth signal point (P '(n)), whose drain is connected to the second signal point (Q'(n)), its source is connected to a constant voltage low potential; one end of the twentieth capacitor (C20) is connected to a constant voltage low potential, and One end is connected to the second signal point (Q'(n)).
  • the third signal point control module (104) includes: a thirteenth thin film transistor (T13), a fifteenth thin film transistor (T15), and an eleventh capacitor (C11), and the thirteenth thin film transistor (T13) a gate connected to a source of the eleventh thin film transistor (T11) and having a drain connected thereto
  • the constant voltage is high, the source is connected to the third node (P(n)); the gate of the fifteenth thin film transistor (T15) is connected to the first signal point (Q(n)), and the drain is connected to the constant voltage Low potential, the source is connected to the third signal point (P(n)); the eleventh capacitor (C11) is connected to the constant voltage low potential at one end and the third signal point (P(n)) at the other end;
  • the fourth signal point control module (204) includes: a twenty-third thin film transistor (T23), a twenty-fifth thin film transistor (T25), and a twenty-first capacitance (C21), the twenty-third thin film transistor a gate of (T23) is connected to a source of the twenty-first thin film transistor (T21), a drain thereof is connected to a constant voltage high potential, and a source thereof is connected to the fourth node (P'(n));
  • the gate of the twenty-fifth thin film transistor (T25) is connected to the second signal point (Q'(n)), the drain thereof is connected to the constant voltage low potential, and the source thereof is connected to the fourth signal point (P'(n))
  • One end of the twenty-first capacitor (C21) is connected to a constant voltage low potential, and the other end is connected to a fourth signal point (P'(n)).
  • the present invention can implement the All Gate ON function in the power-off state by providing the first global signal action module and the second global signal action module in each level of the GOA circuit repeating unit, and the liquid crystal display panel can be The pixel switch is fully opened, so that the charge on the pixel electrode is released in time, and the charge of the pixel electrode is guided away through the data line of the liquid crystal display panel (ie, Data Line), thereby eliminating the residual image of the liquid crystal display panel when the power is off. Can eliminate the afterimage of the first and last lines, can improve the user experience.
  • Figure 1 is a circuit diagram of a repeating unit of an nth stage GOA circuit in an embodiment of a GOA circuit provided by the present invention.
  • FIG. 2 is a partial circuit diagram of a first stage GOA circuit repeating unit of an embodiment of a GOA circuit provided by the present invention
  • FIG. 3 is a final stage GOA circuit of an embodiment of a GOA circuit provided by the present invention a partial circuit diagram of the repeating unit;
  • FIG. 4 is a timing diagram of signals in a power-off mode in one embodiment of a GOA circuit.
  • the GOA circuit is used in a liquid crystal display panel, and includes: a first forward/reverse scan module 100, a first clock input module 101, a first signal point control module 103, and a third signal point control module. 104.
  • the first forward/reverse scan module 100, the first clock input module 101, the first signal point control module 103, and the first output module 102 are all electrically connected to the first signal point Q(n), and the third signal point
  • the control module 104 and the first global signal action module 105 are both electrically connected to the third signal point P(n);
  • the second output module 202 is electrically connected to the second signal point Q'(n), the fourth signal point control module 204 and the second global signal function module 205 are electrically connected to the fourth signal point P'(n);
  • n be a positive integer, in addition to the first stage GOA circuit repeating unit and the last stage GOA circuit repeating unit, in the nth stage GOA circuit repeating unit:
  • the first forward-reverse scan module 100 and the second forward-reverse scan module 200 are used for root Controlling the GOA circuit to perform a forward scan or a reverse scan according to the first scan control signal or the second scan control signal, wherein the first scan control signal and the second scan control signal are opposite in phase, it being understood that in the present invention
  • the GOA circuit can use the forward scan state of the liquid crystal display panel (ie, the first scan control signal U2D is high, the second scan control signal D2U is low), or the reverse scan state can be used (ie, the first scan control)
  • the signal U2D is low and the second scan control signal D2U is high.
  • the thin film transistor of the pixel unit can be turned on line by line.
  • the first output module 102 and the second output module 202 respectively access the first clock signal CK1, and sequentially output the nth scan signal Gn and the n+2th scan signal Gn by using the first clock signal respectively. +2;
  • the first clock input module 101 is configured to output a second clock signal CK2 or a fourth clock signal CK4 to the third signal point control module 104;
  • the second clock input module 201 is configured to output a fourth a clock signal CK4 or a second clock signal CK2 to the fourth signal point control module 204;
  • the first signal point control module 103 is configured to control a level of the first signal point Q(n) during the action of the nth stage GOA circuit repeating unit to control the first output module to be turned on for scanning signal output;
  • the two signal point control module 203 is configured to control the level of the second signal point Q'(n) during the action of the nth stage GOA circuit repeating unit to control the second output module to be turned on for scanning signal output;
  • the third signal point control module 104 is configured to control the level of the third signal point P(n) during the action of the nth stage GOA circuit repeating unit, specifically, the second clock signal CK2 or the fourth clock signal. Under the action of CK4, the level of the third signal point P(n) is pulled down; the fourth signal point control module 204 is configured to control the fourth signal point P' during the action of the nth stage GOA circuit repeating unit Level (such as pulling down its level);
  • the first global signal action module 105 and the second global signal action module 205 are configured to implement, when the power is off, all the scan signals in the repeating unit of the nth stage GOA circuit to be turned on by using the first global signal GAS1.
  • the first forward-reverse scan module 100 includes: a tenth thin film transistor T10 and a fourteenth thin film The transistor T14, the gate of the tenth thin film transistor is connected to the n-2th scan signal Gn-2 outputted by the repeating unit of the upper n-1th stage GOA circuit, and the source thereof is connected to the first scan control signal, The drain is electrically connected to the first node Q(n); the gate of the fourteenth thin film transistor T14 is connected to the n+2th scan signal Gn+2 outputted by the n-th stage GOA circuit repeating unit, and the source is connected to the second scan a control signal whose drain is electrically connected to the first node Q(n);
  • the second forward-reverse-scanning module 200 includes: a twentieth thin film transistor T20 and a twenty-fourth thin film transistor T24, and the gate of the twentieth thin film transistor is connected to the nth of the n-th stage GOA circuit repeating unit output.
  • a strip scan signal Gn whose source is connected to the first scan control signal, whose drain is electrically connected to the second node Q'(n); the gate of the twenty-fourth thin film transistor T24 is connected to the next level n+1th GOA
  • the n+4th scan signal Gn+4 outputted by the circuit repeating unit has a source connected to the second scan control signal and a drain electrically connected to the second node Q'(n).
  • the first output module 102 includes: a thirtieth thin film transistor T30, a thirty-first thin film transistor T31, and a thirty-second thin film transistor T32.
  • the source of the thirtieth thin film transistor T30 is electrically connected to the first node Q.
  • the gate thereof is connected to a constant voltage high potential;
  • the gate of the 31st thin film transistor T31 is connected to the drain of the thirtieth thin film transistor, and the drain thereof is connected to the first clock signal CK1;
  • the gate of the thirty-second thin film transistor T30 is connected to the third node P(n), the source thereof is connected to the constant voltage low potential, the drain thereof is connected to the source of the thirty-first thin film transistor T31, and is electrically connected
  • the second output module 202 includes: a forty-th thin film transistor T40, a forty-first thin film transistor T41, and a forty-second thin film transistor T42.
  • the source of the fortieth thin film transistor T40 is electrically connected to the second node Q' ( n), the gate is connected to a constant voltage high potential;
  • the fourth eleventh thin film transistor T41 is connected to the drain of the forty-th thin film transistor, and the drain thereof is connected to the first clock signal CK1;
  • the gate of the forty-two thin film transistor T40 is connected to the fourth node P'(n), the source thereof is connected to the constant voltage low potential, the drain thereof is connected to the source of the forty-th thin film transistor T41, and is electrically connected
  • the n+2th scan signal Gn+2 outputted by the unit of the nth stage GOA circuit repeats.
  • the first clock input module 101 includes: an eleventh thin film transistor T11 and a twelfth thin film transistor T12.
  • the gate of the eleventh thin film transistor T11 is connected to the first scan control signal, and the drain is connected.
  • the gate of the twelfth thin film transistor T12 is connected to the second scan control signal, the source thereof is connected to the fourth clock signal CK4, and the drain thereof is connected to the first a source of the eleven thin film transistor T11;
  • the second clock input module 201 includes: a 21st thin film transistor T21 and a 22nd thin film transistor T22.
  • the gate of the 21st thin film transistor T21 is connected to the first scan control signal, and the drain is connected.
  • the fourth clock signal CK4 is input; the gate of the twenty-second thin film transistor T22 is connected to the second scan control signal, the source thereof is connected to the second clock signal CK2, and the drain thereof is connected to the second eleventh The source of the thin film transistor T21.
  • the first signal point control module 103 includes a sixteenth thin film transistor T16 and a tenth capacitor C10.
  • the sixteenth thin film transistor T16 is connected to the third signal point P(n), and the drain is connected to the first.
  • Signal point Q(n) whose source is connected to a constant voltage low potential; one end of the tenth capacitor C10 is connected to a constant voltage low potential, and the other end is connected to a first signal point Q(n);
  • the second signal point control module 203 includes a second sixteen thin film transistor T26 and a twentieth capacitor C20.
  • the second sixteen thin film transistor T26 is connected to the fourth signal point P'(n) and has a drain connection.
  • the second signal point Q'(n) has a source connected to the constant voltage low potential; one end of the twentieth capacitor C20 is connected to the constant voltage low potential, and the other end is connected to the second signal point Q'(n).
  • the third signal point control module 104 includes: a thirteenth thin film transistor T13, a fifteenth thin film transistor T15, and an eleventh capacitor C11, and a gate of the thirteenth thin film transistor T13 and the eleventh
  • the source of the thin film transistor T11 is connected, the drain thereof is connected to a constant voltage high potential, and the source thereof is connected to the third node P(n); the gate of the fifteenth thin film transistor T15 is connected to the first signal point Q(n)
  • the drain is connected to the constant voltage low potential, the source thereof is connected to the third signal point P(n); the eleventh capacitor C11 is connected to the constant voltage low potential at one end, and the third signal point P(n) is connected to the other end; It can be understood that the turning on and off of the thirteenth thin film transistor T13 is controlled by the clock signal output by the first clock input module 101.
  • the fourth signal point control module 204 includes: a twenty-third thin film transistor T23, a twenty-fifth thin film transistor T25, and a twenty-first capacitor C21.
  • the gate of the twenty-third thin film transistor T23 and the first The source of the twenty-one thin film transistor T21 is connected, the drain thereof is connected to the constant voltage high potential, the source thereof is connected to the fourth node P'(n); the gate of the twenty-fifth thin film transistor T25 is connected to the second
  • the signal point Q'(n) has a drain connected to the constant voltage low potential, and a source connected to the fourth signal point P'(n); the second eleventh capacitor C21 is connected to the constant voltage low potential at one end, and the other end is connected Four signal points P'(n). It can be understood that the turning on and off of the twenty-third thin film transistor T23 is affected by the second clock input.
  • the clock signal output by the module 201 is controlled.
  • the first global signal action module 105 includes a seventeenth thin film transistor T17 and an eighteenth thin film transistor T18.
  • the seventeenth thin film transistor T17 has its gate connected to its source and its drain connected to the nth stage GOA circuit.
  • the nth scan signal Gn of the repeating unit; the gate of the eighteenth thin film transistor T18 is connected to the gate of the seventeenth thin film transistor T17, and is connected to the first global signal GAS1, and the drain thereof is connected Three signal points P(n) whose source is connected to a constant voltage low potential;
  • the second global signal action module 205 includes two seventeenth thin film transistors T27 and a twenty-eighth thin film transistor T28.
  • the gate of the twenty-seventh thin film transistor T27 is connected to its source, and its drain is connected to the nth stage GOA.
  • the n+2th scan signal Gn+2 of the circuit repeating unit; the gate of the twenty-eighth thin film transistor T28 is connected to the gate of the twenty-seventh thin film transistor T27, and is connected to the first global signal GAS1 has a drain connected to a fourth signal point P'(n) whose source is connected to a constant voltage low potential.
  • all of the thin film transistors are N-channel thin film transistors, and the drain and source of each thin film transistor are interchangeable.
  • FIG. 2 a partial circuit diagram of a first-stage GOA circuit repeating unit of an embodiment of a GOA circuit provided by the present invention is shown; it can be understood that only a part of the circuit is shown in FIG. The other part of the circuit is the same as the lower part of Fig. 1.
  • the first stage GOA circuit repeating unit shown in FIG. 2 is different from the nth stage GOA circuit repeating unit shown in FIG. 1 in that, in the first stage GOA circuit repeating unit, the tenth thin film transistor (T10) Gate access circuit start signal (STV);
  • the first stage GOA circuit repeating unit further includes a nineteenth thin film transistor (T19), the gate of the nineteenth thin film transistor being connected to the first scan signal (G1) output by the first stage GOA circuit repeating unit,
  • the source is connected to a constant voltage low potential, and its drain is connected to the gate of the tenth thin film transistor (T10).
  • FIG. 3 is a final stage GOA of an embodiment of a GOA circuit provided by the present invention. Part of the circuit diagram of the circuit repeating unit; it can be understood that only a part of the circuit is shown in Fig. 3, and the other part of the circuit is the same as the upper half of Fig. 1.
  • the final stage GOA circuit repeating unit shown in FIG. 3 differs from the nth stage GOA circuit repeating unit shown in FIG. 1 in that in the last stage GOA circuit repeating unit, the twenty-fourth thin film transistor ( T24) gate access circuit start signal (STV);
  • the last stage GOA circuit repeating unit further includes a twenty-nineth thin film transistor (T29), and the gate of the twenty-ninth thin film transistor is connected to the last scan signal (Glast) outputted by the last stage GOA circuit repeating unit.
  • the source is connected to the constant voltage low potential, and the drain thereof is connected to the gate of the twenty-fourth thin film transistor (T24).
  • the thin film transistor T29 can be turned on during the power-off, because the last scan signal is at a high potential, thereby pulling down the potential of the circuit start signal (STV), thereby making the final stage GOA circuit repeating unit
  • STV circuit start signal
  • the present invention provides a timing diagram of signals in a power-off mode in one embodiment of a GOA circuit.
  • the timing chart of each signal is as shown in FIG. 4, and the scan enable signal STV and the first global signal GAS1 are both high (H), the first scan control signal U2D, and the second scan control signal D2U. All clock signals CK are low (L).
  • the thin film transistors T18 and T17 are both in an on state, so that the third signal point P(n)
  • the level of the thin film transistor T16, T32 is in the off state; and since the thin film transistor T17 is turned on, the level of the drain is at a high potential, so that the scan signal Gn is turned on; similarly, the scan is performed at this time.
  • Signal Gn+1 is also turned on;
  • the All Gate ON function can be performed under the action of the first global signal GAS1.
  • the thin film transistor T19 is provided in the repeating unit of the first-stage GOA circuit, and the thin film transistor T29 is provided in the repeating unit of the last-stage GOA circuit, the image sticking phenomenon of the first and last lines can be eliminated.
  • the present invention can implement the All Gate ON function in the power-off state by providing the first global signal action module and the second global signal action module in each level of the GOA circuit repeating unit, and the liquid crystal display panel can be The pixel switch is fully turned on, so that the pixel electrode is released in time The charge on the liquid crystal display panel (Data Line) guides the charge of the pixel electrode away, eliminating the residual image of the liquid crystal display panel when the power is turned off, and eliminating the residual image of the first and last lines, thereby improving the user experience. .

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Abstract

本发明提供一种GOA电路，包括级联的多级GOA电路重复单元，每一级GOA电路重复单元均包括：第一正反向扫描模块(100)、第一时钟输入模块(101)、第一信号点控制模块(103)、第三信号点控制模块(104)、第一输出模块(102)、第一全局信号作用模块(105)、第二正反向扫描模块(200)、第二时钟输入模块(201)、第二信号点控制模块(203)、第四信号点控制模块(204)、第二输出模块(202)、第二全局信号作用模块(205)。本发明可以消除液晶显示面板在异常断电时出现的残影，提高用户体验。

Description

一种GOA电路
本申请要求于2017年11月22日提交中国专利局、申请号为201711175909.0、发明名称为“一种GOA电路”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路。
背景技术
目前，液晶显示装置作为电子设备的显示部件已经广泛的应用于各种电子产品中，而阵列基板行驱动抚州(Gate Driver OnArray，简称GOA)，是利用薄膜晶体管(Thin Film Transistor，TFT)液晶显示器阵列制程将栅极行扫描驱动信号电路制作在阵列基板上，以实现对栅极逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。
基于低温多晶硅(Low Temperature Poly-silicon，简称LTPS)技术的显示面板，根据面板内采用的薄膜晶体管(TFT)类型，可以分为NMOS型，PMOS型，以及皆有NMOS和PMOS型的CMOS。类似的，GOA电路分为NMOS电路，PMOS电路以及CMOS电路。NMOS电路相比于CMOS电路而言，由于NMOS电路省去PP(P掺杂，即磷离子参杂)这一层光罩及工序，对于提高良率以及降低成本都大有裨益，所以开发稳定的NMOS电路具有现实的产业需求。
当前大尺寸液晶显示面板已成为行业内发展的主要趋势，随着面板尺寸和栅极驱动行数的增加，GOA负载也相应增大，因而GOA中各TFT的尺寸和面板边框会增加，不利于实现液晶显示面板的窄边框，同时负载增大也会使GOA模块功耗增加。
同时，当液晶显示面板在异常断电情况下，若GOA电路无法有效的实现All Gate ON(即将GOA电路中的所有栅极驱动信号设置为有效电位，以 同时对液晶显示装置进行扫描)功能，当液晶显示面板将出现残影。
发明内容
为解决上述技术问题，本发明提供一种GOA电路，可以消除液晶显示面板在异常断电时出现的残影，提高用户体验。
相应地，本发明实施例提供一种GOA电路，用于液晶显示面板中，包括级联的多级GOA电路重复单元，每一级GOA电路重复单元均包括：第一正反向扫描模块100、第一时钟输入模块101、第一信号点控制模块103、第三信号点控制模块104、第一输出模块102、第一全局信号作用模块105、第二正反向扫描模块200、第二时钟输入模块201、第二信号点控制模块203、第四信号点控制模块204、第二输出模块202、第二全局信号作用模块205；其中：
设n为正整数，除第一级GOA电路重复单元和最后一级GOA电路重复单元外，在第n级GOA电路重复单元中：
所述第一正反向扫描模块100与所述第二正反向扫描模块200，用于根据第一扫描控制信号或第二扫描控制信号控制GOA电路进行正向扫描或反向扫描；
所述第一输出模块102、第二输出模块202分别接入第一条时钟信号CK1，并分别利用所述第一条时钟信号依次输出第n条扫描信号Gn、第n+2条扫描信号Gn+2；
所述第一时钟输入模块101，用于输出第二条时钟信号CK2或第四条时钟信号CK4至所述第三信号点控制模块104；所述第二时钟输入模块201用于输出第四条时钟信号CK4或第二条时钟信号CK2至所述第四信号点控制模块204；
所述第一信号点控制模块103用于在第n级GOA电路重复单元作用期间，控制第一信号点Q(n)的电平；所述第二信号点控制模块203用于在第n级GOA电路重复单元作用期间，控制第二信号点Q’(n)的电平；
所述第三信号点控制模块104用于在第n级GOA电路重复单元作用期间，控制第三信号点P(n)的电平；所述第四信号点控制模块204用于在第n 级GOA电路重复单元作用期间，控制第四信号点P’(n)的电平；
第一全局信号作用模块105和所述第二全局信号作用模块205，用于在断电时，利用第一全局信号GAS1实现第n级GOA电路重复单元中所有扫描信号打开。
其中，除第一级GOA电路重复单元和最后一级GOA电路重复单元外，在第n级GOA电路重复单元中：
所述第一正反向扫描模块100包括：第十薄膜晶体管T10和第十四薄膜晶体管T14，所述第十薄膜晶体管的栅极接入上一级第n-1级GOA电路重复单元输出的第n-2条扫描信号Gn-2，其源极接第一扫描控制信号，其漏极电连接第一节点Q(n)；第十四薄膜晶体管T14的栅极接入第n级GOA电路重复单元输出的第n+2条扫描信号Gn+2，其源极接第二扫描控制信号，其漏极电连接第一节点Q(n)；
所述第二正反向扫描模块200包括：第二十薄膜晶体管T20和第二十四薄膜晶体管T24，所述第二十薄膜晶体管的栅极接入第n级GOA电路重复单元输出的第n条扫描信号Gn，其源极接第一扫描控制信号，其漏极电连接第二节点Q’(n)；第二十四薄膜晶体管T24的栅极接入下一级第n+1级GOA电路重复单元输出的第n+4条扫描信号Gn+4，其源极接第二扫描控制信号，其漏极电连接第二节点Q’(n)。
其中，所述第一正反向扫描模块100、第一时钟输入模块101、第一信号点控制模块103、第一输出模块102均电连接于第一信号点Q(n)，所述第三信号点控制模块104和第一全局信号作用模块105均电连接于第三信号点P(n)；所述第二正反向扫描模块200、第二时钟输入模块201、第二信号点控制模块203、第二输出模块202均电连接于第二信号点Q’(n)，所述第四信号点控制模块204和第二全局信号作用模块205电连接于第四信号点P’(n)。
其中，在第一级GOA电路重复单元中，所述第十薄膜晶体管T10的栅极接入电路起始信号STV；
所述第一级GOA电路重复单元进一步包括第十九薄膜晶体管T19，所述第十九薄膜晶体管的栅极接入第一级GOA电路重复单元输出的第一条扫描信号G1，其源极连接恒压低电位，其漏极连接所述第十薄膜晶体管T10 的栅极。
其中，在最后一级GOA电路重复单元中，所述第二十四薄膜晶体管T24的栅极接入电路起始信号STV；
所述最后一级GOA电路重复单元进一步包括第二十九薄膜晶体管T29，所述第二十九薄膜晶体管的栅极接入最后一级GOA电路重复单元输出的最后一条扫描信号Glast，其源极连接恒压低电位，其漏极连接所述第二十四薄膜晶体管T24的栅极。
其中，所述第一输出模块102包括：第三十薄膜晶体管T30、第三十一薄膜晶体管T31以及第三十二薄膜晶体管T32，所述第三十薄膜晶体管T30源极电连接第一节点Q(n)，其栅极连接恒压高电位；所述第三十一薄膜晶体管T31栅极连接所述第三十薄膜晶体管的漏极，其漏极接入第一条时钟信号CK1；所述第三十二薄膜晶体管T30的栅极连接第三节点P(n)，其源极连接恒压低电位，其漏极与所述第三十一薄膜晶体管T31的源极相连接，并电连接于第n级GOA电路重复单元输出的第n条扫描信号Gn；
所述第二输出模块202包括：第四十薄膜晶体管T40、第四十一薄膜晶体管T41以及第四十二薄膜晶体管T42，所述第四十薄膜晶体管T40源极电连接第二节点Q’(n)，其栅极连接恒压高电位；所述第四十一薄膜晶体管T41栅极连接所述第四十薄膜晶体管的漏极，其漏极接入第一条时钟信号CK1；所述第四十二薄膜晶体管T40的栅极连接第四节点P’(n)，其源极连接恒压低电位，其漏极与所述第四十一薄膜晶体管T41的源极相连接，并电连接于第n级GOA电路重复单元输出的第n+2条扫描信号Gn+2。
其中，所述第一时钟输入模块101包括：第十一薄膜晶体管T11、第十二薄膜晶体管T12，所述第十一薄膜晶体管T11的栅极接入第一扫描控制信号，其漏极接入第二条时钟信号CK2；所述第十二薄膜晶体管T12的栅极接入第二扫描控制信号，其源极接入第四条时钟信号CK4，其漏极连接所述第十一薄膜晶体管T11的源极；
所述第二时钟输入模块201包括：第二十一薄膜晶体管T21、第二十二薄膜晶体管T22，所述第二十一薄膜晶体管T21的栅极接入第一扫描控制信号，其漏极接入第四条时钟信号CK4；所述第二十二薄膜晶体管T22的栅极 接入第二扫描控制信号，其源极接入第二条时钟信号CK2，其漏极连接所述第二十一薄膜晶体管T21的源极。
其中，所述第一信号点控制模块103包括第十六薄膜晶体管T16及第十电容C10，所述第十六薄膜晶体管T16栅极连接第三信号点P(n)，其漏极连接第一信号点Q(n)，其源极连接恒压低电位；所述第十电容C10的一端接入恒压低电位，另一端连接第一信号点Q(n)；
所述第二信号点控制模块203包括第二十六薄膜晶体管T26及第二十电容C20，所述第二十六薄膜晶体管T26栅极连接第四信号点P’(n)，其漏极连接第二信号点Q’(n)，其源极连接恒压低电位；所述第二十电容C20的一端接入恒压低电位，另一端连接第二信号点Q’(n)。
其中，所述第三信号点控制模块104包括：第十三薄膜晶体管T13、第十五薄膜晶体管T15以及第十一电容C11，所述第十三薄膜晶体管T13的栅极与所述第十一薄膜晶体管T11的源极相连接，其漏极接入恒压高电位，其源极连接第三节点P(n)；所述第十五薄膜晶体管T15的栅极连接第一信号点Q(n)，其漏极连接恒压低电位，其源极连接第三信号点P(n)；所述第十一电容C11一端连接恒压低电位，另一端连接第三信号点P(n)；
所述第四信号点控制模块204包括：第二十三薄膜晶体管T23、第二十五薄膜晶体管T25以及第二十一电容C21，所述第二十三薄膜晶体管T23的栅极与所述第二十一薄膜晶体管T21的源极相连接，其漏极接入恒压高电位，其源极连接第四节点P’(n)；所述第二十五薄膜晶体管T25的栅极连接第二信号点Q’(n)，其漏极连接恒压低电位，其源极连接第四信号点P’(n)；所述第二十一电容C21一端连接恒压低电位，另一端连接第四信号点P’(n)。
其中，第一全局信号作用模块105包括第十七薄膜晶体管T17和第十八薄膜晶体管T18，所述第十七薄膜晶体管T17的栅极与其源极相连接，其漏极连接第n级GOA电路重复单元的第n条扫描信号Gn；所述第十八薄膜晶体管T18的栅极与所述第十七薄膜晶体管T17的栅极相连接，并接入第一全局信号GAS1，其漏极连接第三信号点P(n)，其源极连接恒压低电位；
第二全局信号作用模块205包括二第十七薄膜晶体管T27和第二十八薄膜晶体管T28，所述第二十七薄膜晶体管T27的栅极与其源极相连接，其漏 极连接第n级GOA电路重复单元的第n+2条扫描信号Gn+2；所述第二十八薄膜晶体管T28的栅极与所述第二十七薄膜晶体管T27的栅极相连接，并接入第一全局信号GAS1，其漏极连接第四信号点P’(n)，其源极连接恒压低电位。
其中，所述所有薄膜晶体管均为N沟道的薄膜晶体管。
相应地，本发明实施例的另一方面，还提供一种一种GOA电路，用于液晶显示面板中，其包括级联的多级GOA电路重复单元，每一级GOA电路重复单元均包括：第一正反向扫描模块(100)、第一时钟输入模块(101)、第一信号点控制模块(103)、第三信号点控制模块(104)、第一输出模块(102)、第一全局信号作用模块(105)、第二正反向扫描模块(200)、第二时钟输入模块(201)、第二信号点控制模块(203)、第四信号点控制模块(204)、第二输出模块(202)、第二全局信号作用模块(205)；其中：
设n为正整数，除第一级GOA电路重复单元和最后一级GOA电路重复单元外，在第n级GOA电路重复单元中：
所述第一正反向扫描模块(100)与所述第二正反向扫描模块(200)，用于根据第一扫描控制信号或第二扫描控制信号控制GOA电路进行正向扫描或反向扫描；
所述第一输出模块(102)、第二输出模块(202)分别接入第一条时钟信号(CK1)，并分别利用所述第一条时钟信号依次输出第n条扫描信号(Gn)、第n+2条扫描信号(Gn+2)；
所述第一时钟输入模块(101)，用于输出第二条时钟信号(CK2)或第四条时钟信号(CK4)至所述第三信号点控制模块(104)；所述第二时钟输入模块(201)用于输出第四条时钟信号(CK4)或第二条时钟信号(CK2)至所述第四信号点控制模块(204)；
所述第一信号点控制模块(103)用于在第n级GOA电路重复单元作用期间，控制第一信号点(Q(n))的电平；所述第二信号点控制模块(203)用于在第n级GOA电路重复单元作用期间，控制第二信号点(Q’(n))的电平；
所述第三信号点控制模块(104)用于在第n级GOA电路重复单元作用 期间，控制第三信号点(P(n))的电平；所述第四信号点控制模块(204)用于在第n级GOA电路重复单元作用期间，控制第四信号点(P’(n))的电平；
第一全局信号作用模块(105)和所述第二全局信号作用模块(205)，用于在断电时，利用第一全局信号(GAS1)实现第n级GOA电路重复单元中所有扫描信号打开；
其中，所述第一全局信号作用模块(105)包括第十七薄膜晶体管(T17)和第十八薄膜晶体管(T18)，所述第十七薄膜晶体管(T17)的栅极与其源极相连接，其漏极连接第n级GOA电路重复单元的第n条扫描信号(Gn)；所述第十八薄膜晶体管(T18)的栅极与所述第十七薄膜晶体管(T17)的栅极相连接，并接入第一全局信号(GAS1)，其漏极连接第三信号点(P(n))，其源极连接恒压低电位；
所述第二全局信号作用模块(205)包括二第十七薄膜晶体管(T27)和第二十八薄膜晶体管(T28)，所述第二十七薄膜晶体管(T27)的栅极与其源极相连接，其漏极连接第n级GOA电路重复单元的第n+2条扫描信号(Gn+2)；所述第二十八薄膜晶体管(T28)的栅极与所述第二十七薄膜晶体管(T27)的栅极相连接，并接入第一全局信号(GAS1)，其漏极连接第四信号点(P’(n))，其源极连接恒压低电位。
其中，所述第一正反向扫描模块(100)、第一时钟输入模块(101)、第一信号点控制模块(103)、第一输出模块(102)均电连接于第一信号点(Q(n))，所述第三信号点控制模块(104)和第一全局信号作用模块(105)均电连接于第三信号点(P(n))；所述第二正反向扫描模块(200)、第二时钟输入模块(201)、第二信号点控制模块(203)、第二输出模块(202)均电连接于第二信号点(Q’(n))，所述第四信号点控制模块(204)和第二全局信号作用模块(205)电连接于第四信号点(P’(n))。
其中，除第一级GOA电路重复单元和最后一级GOA电路重复单元外，在第n级GOA电路重复单元中：
所述第一正反向扫描模块(100)包括：第十薄膜晶体管(T10)和第十四薄膜晶体管(T14)，所述第十薄膜晶体管的栅极接入上一级第n-1级GOA电路重复单元输出的第n-2条扫描信号(Gn-2)，其源极接第一扫描控制信 号，其漏极电连接第一节点(Q(n))；第十四薄膜晶体管(T14)的栅极接入第n级GOA电路重复单元输出的第n+2条扫描信号(Gn+2)，其源极接第二扫描控制信号，其漏极电连接第一节点(Q(n))；
所述第二正反向扫描模块(200)包括：第二十薄膜晶体管(T20)和第二十四薄膜晶体管(T24)，所述第二十薄膜晶体管的栅极接入第n级GOA电路重复单元输出的第n条扫描信号(Gn)，其源极接第一扫描控制信号，其漏极电连接第二节点(Q’(n))；第二十四薄膜晶体管(T24)的栅极接入下一级第n+1级GOA电路重复单元输出的第n+4条扫描信号(Gn+4)，其源极接第二扫描控制信号，其漏极电连接第二节点(Q’(n))。
其中，在第一级GOA电路重复单元中，所述第十薄膜晶体管(T10)的栅极接入电路起始信号(STV)；
所述第一级GOA电路重复单元进一步包括第十九薄膜晶体管(T19)，所述第十九薄膜晶体管的栅极接入第一级GOA电路重复单元输出的第一条扫描信号(G1)，其源极连接恒压低电位，其漏极连接所述第十薄膜晶体管(T10)的栅极。
其中，在最后一级GOA电路重复单元中，所述第二十四薄膜晶体管(T24)的栅极接入电路起始信号(STV)；
所述最后一级GOA电路重复单元进一步包括第二十九薄膜晶体管(T29)，所述第二十九薄膜晶体管的栅极接入最后一级GOA电路重复单元输出的最后一条扫描信号(Glast)，其源极连接恒压低电位，其漏极连接所述第二十四薄膜晶体管(T24)的栅极。
其中，所述第一输出模块(102)包括：第三十薄膜晶体管(T30)、第三十一薄膜晶体管(T31)以及第三十二薄膜晶体管(T32)，所述第三十薄膜晶体管(T30)源极电连接第一节点Q(n)，其栅极连接恒压高电位；所述第三十一薄膜晶体管(T31)栅极连接所述第三十薄膜晶体管的漏极，其漏极接入第一条时钟信号(CK1)；所述第三十二薄膜晶体管(T30)的栅极连接第三节点(P(n))，其源极连接恒压低电位，其漏极与所述第三十一薄膜晶体管(T31)的源极相连接，并电连接于第n级GOA电路重复单元输出的第n条扫描信号(Gn)；
所述第二输出模块(202)包括：第四十薄膜晶体管(T40)、第四十一薄膜晶体管(T41)以及第四十二薄膜晶体管(T42)，所述第四十薄膜晶体管(T40)源极电连接第二节点(Q’(n))，其栅极连接恒压高电位；所述第四十一薄膜晶体管(T41)栅极连接所述第四十薄膜晶体管的漏极，其漏极接入第一条时钟信号(CK1)；所述第四十二薄膜晶体管(T40)的栅极连接第四节点(P’(n))，其源极连接恒压低电位，其漏极与所述第四十一薄膜晶体管(T41)的源极相连接，并电连接于第n级GOA电路重复单元输出的第n+2条扫描信号(Gn+2)。
其中，所述第一时钟输入模块(101)包括：第十一薄膜晶体管(T11)、第十二薄膜晶体管(T12)，所述第十一薄膜晶体管(T11)的栅极接入第一扫描控制信号，其漏极接入第二条时钟信号(CK2)；所述第十二薄膜晶体管(T12)的栅极接入第二扫描控制信号，其源极接入第四条时钟信号(CK4)，其漏极连接所述第十一薄膜晶体管(T11)的源极；
所述第二时钟输入模块(201)包括：第二十一薄膜晶体管(T21)、第二十二薄膜晶体管(T22)，所述第二十一薄膜晶体管(T21)的栅极接入第一扫描控制信号，其漏极接入第四条时钟信号(CK4)；所述第二十二薄膜晶体管(T22)的栅极接入第二扫描控制信号，其源极接入第二条时钟信号(CK2)，其漏极连接所述第二十一薄膜晶体管(T21)的源极。
其中，所述第一信号点控制模块(103)包括第十六薄膜晶体管(T16)及第十电容(C10)，所述第十六薄膜晶体管(T16)栅极连接第三信号点(P(n))，其漏极连接第一信号点(Q(n))，其源极连接恒压低电位；所述第十电容(C10)的一端接入恒压低电位，另一端连接第一信号点(Q(n))；
所述第二信号点控制模块(203)包括第二十六薄膜晶体管(T26)及第二十电容(C20)，所述第二十六薄膜晶体管(T26)栅极连接第四信号点(P’(n))，其漏极连接第二信号点(Q’(n))，其源极连接恒压低电位；所述第二十电容(C20)的一端接入恒压低电位，另一端连接第二信号点(Q’(n))。
其中，所述第三信号点控制模块(104)包括：第十三薄膜晶体管(T13)、第十五薄膜晶体管(T15)以及第十一电容(C11)，所述第十三薄膜晶体管(T13)的栅极与所述第十一薄膜晶体管(T11)的源极相连接，其漏极接入 恒压高电位，其源极连接第三节点(P(n))；所述第十五薄膜晶体管(T15)的栅极连接第一信号点(Q(n))，其漏极连接恒压低电位，其源极连接第三信号点(P(n))；所述第十一电容(C11)一端连接恒压低电位，另一端连接第三信号点(P(n))；
所述第四信号点控制模块(204)包括：第二十三薄膜晶体管(T23)、第二十五薄膜晶体管(T25)以及第二十一电容(C21)，所述第二十三薄膜晶体管(T23)的栅极与所述第二十一薄膜晶体管(T21)的源极相连接，其漏极接入恒压高电位，其源极连接第四节点(P’(n))；所述第二十五薄膜晶体管(T25)的栅极连接第二信号点(Q’(n))，其漏极连接恒压低电位，其源极连接第四信号点(P’(n))；所述第二十一电容(C21)一端连接恒压低电位，另一端连接第四信号点(P’(n))。
实施本发明，具有如下有益效果：
综上所述，本发明通过在每一级GOA电路重复单元中设置有第一全局信号作用模块和第二全局信号作用模块，可以在断电时，实现All Gate ON功能，可以将液晶显示面板的像素开关完全打开，从而及时释放掉像素电极上的电荷，通过液晶显示面板的数据线(即Data Line)将像素电极的电荷导走，消除液晶显示面板在断电时出现的残影，同时能消除首尾行的残影，可以提高用户体验。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明提供的一种GOA电路的一个实施例中第n级GOA电路重复单元的电路图。
图2是本发明提供的一种GOA电路的一个实施例第一级GOA电路重复单元的部分电路图；
图3是本发明提供的一种GOA电路的一个实施例最后一级GOA电路 重复单元的部分电路图；
图4是本发明提供一种GOA电路一个实施例中在断电时各信号的时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚完整地描述，显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
如图1所示，示出了本发明提供的一种GOA电路的一个实施例中第n级GOA电路重复单元的电路图。在该实施例中，所述GOA电路用于液晶显示面板中，其包括：第一正反向扫描模块100、第一时钟输入模块101、第一信号点控制模块103、第三信号点控制模块104、第一输出模块102、第一全局信号作用模块105、第二正反向扫描模块200、第二时钟输入模块201、第二信号点控制模块203、第四信号点控制模块204、第二输出模块202、第二全局信号作用模块205；其中：
所述第一正反向扫描模块100、第一时钟输入模块101、第一信号点控制模块103、第一输出模块102均电连接于第一信号点Q(n)，所述第三信号点控制模块104和第一全局信号作用模块105均电连接于第三信号点P(n)；所述第二正反向扫描模块200、第二时钟输入模块201、第二信号点控制模块203、第二输出模块202均电连接于第二信号点Q’(n)，所述第四信号点控制模块204和第二全局信号作用模块205电连接于第四信号点P’(n)；
设n为正整数，除第一级GOA电路重复单元和最后一级GOA电路重复单元外，在第n级GOA电路重复单元中：
所述第一正反向扫描模块100与所述第二正反向扫描模块200，用于根 据第一扫描控制信号或第二扫描控制信号控制GOA电路进行正向扫描或反向扫描，其中所述第一扫描控制信号、第二扫描控制信号相位相反，可以理解的是，本发明中的GOA电路既可以使用液晶显示面板的正向扫描状态(即第一扫描控制信号U2D为高电位，第二扫描控制信号D2U为低电位)，也可以使用反向扫描状态，(即第一扫描控制信号U2D为低电位，第二扫描控制信号D2U为高电位)可以实现像素单元的薄膜晶体管逐行打开。
所述第一输出模块102、第二输出模块202分别接入第一条时钟信号CK1，并分别利用所述第一条时钟信号依次输出第n条扫描信号Gn、第n+2条扫描信号Gn+2；
所述第一时钟输入模块101，用于输出第二条时钟信号CK2或第四条时钟信号CK4至所述第三信号点控制模块104；所述第二时钟输入模块201用于输出第四条时钟信号CK4或第二条时钟信号CK2至所述第四信号点控制模块204；
所述第一信号点控制模块103用于在第n级GOA电路重复单元作用期间，控制第一信号点Q(n)的电平，以控制第一输出模块打开进行扫描信号输出；所述第二信号点控制模块203用于在第n级GOA电路重复单元作用期间，控制第二信号点Q’(n)的电平，以控制第二输出模块打开进行扫描信号输出；
所述第三信号点控制模块104用于在第n级GOA电路重复单元作用期间，控制第三信号点P(n)的电平，具体为在第二条时钟信号CK2或第四条时钟信号CK4的作用下，拉低第三信号点P(n)的电平；所述第四信号点控制模块204用于在第n级GOA电路重复单元作用期间，控制第四信号点P’(n)的电平(如拉低其电平)；
第一全局信号作用模块105和所述第二全局信号作用模块205，用于在断电时，利用第一全局信号GAS1实现第n级GOA电路重复单元中所有扫描信号打开。
其中，除第一级GOA电路重复单元和最后一级GOA电路重复单元外，在第n级GOA电路重复单元中：
所述第一正反向扫描模块100包括：第十薄膜晶体管T10和第十四薄膜 晶体管T14，所述第十薄膜晶体管的栅极接入上一级第n-1级GOA电路重复单元输出的第n-2条扫描信号Gn-2，其源极接第一扫描控制信号，其漏极电连接第一节点Q(n)；第十四薄膜晶体管T14的栅极接入第n级GOA电路重复单元输出的第n+2条扫描信号Gn+2，其源极接第二扫描控制信号，其漏极电连接第一节点Q(n)；
所述第二正反向扫描模块200包括：第二十薄膜晶体管T20和第二十四薄膜晶体管T24，所述第二十薄膜晶体管的栅极接入第n级GOA电路重复单元输出的第n条扫描信号Gn，其源极接第一扫描控制信号，其漏极电连接第二节点Q’(n)；第二十四薄膜晶体管T24的栅极接入下一级第n+1级GOA电路重复单元输出的第n+4条扫描信号Gn+4，其源极接第二扫描控制信号，其漏极电连接第二节点Q’(n)。
其中，所述第一输出模块102包括：第三十薄膜晶体管T30、第三十一薄膜晶体管T31以及第三十二薄膜晶体管T32，所述第三十薄膜晶体管T30源极电连接第一节点Q(n)，其栅极连接恒压高电位；所述第三十一薄膜晶体管T31栅极连接所述第三十薄膜晶体管的漏极，其漏极接入第一条时钟信号CK1；所述第三十二薄膜晶体管T30的栅极连接第三节点P(n)，其源极连接恒压低电位，其漏极与所述第三十一薄膜晶体管T31的源极相连接，并电连接于第n级GOA电路重复单元输出的第n条扫描信号Gn；
所述第二输出模块202包括：第四十薄膜晶体管T40、第四十一薄膜晶体管T41以及第四十二薄膜晶体管T42，所述第四十薄膜晶体管T40源极电连接第二节点Q’(n)，其栅极连接恒压高电位；所述第四十一薄膜晶体管T41栅极连接所述第四十薄膜晶体管的漏极，其漏极接入第一条时钟信号CK1；所述第四十二薄膜晶体管T40的栅极连接第四节点P’(n)，其源极连接恒压低电位，其漏极与所述第四十一薄膜晶体管T41的源极相连接，并电连接于第n级GOA电路重复单元输出的第n+2条扫描信号Gn+2。
其中，所述第一时钟输入模块101包括：第十一薄膜晶体管T11、第十二薄膜晶体管T12，所述第十一薄膜晶体管T11的栅极接入第一扫描控制信号，其漏极接入第二条时钟信号CK2；所述第十二薄膜晶体管T12的栅极接入第二扫描控制信号，其源极接入第四条时钟信号CK4，其漏极连接所述第 十一薄膜晶体管T11的源极；
所述第二时钟输入模块201包括：第二十一薄膜晶体管T21、第二十二薄膜晶体管T22，所述第二十一薄膜晶体管T21的栅极接入第一扫描控制信号，其漏极接入第四条时钟信号CK4；所述第二十二薄膜晶体管T22的栅极接入第二扫描控制信号，其源极接入第二条时钟信号CK2，其漏极连接所述第二十一薄膜晶体管T21的源极。
其中，所述第一信号点控制模块103包括第十六薄膜晶体管T16及第十电容C10，所述第十六薄膜晶体管T16栅极连接第三信号点P(n)，其漏极连接第一信号点Q(n)，其源极连接恒压低电位；所述第十电容C10的一端接入恒压低电位，另一端连接第一信号点Q(n)；
所述第二信号点控制模块203包括第二十六薄膜晶体管T26及第二十电容C20，所述第二十六薄膜晶体管T26栅极连接第四信号点P’(n)，其漏极连接第二信号点Q’(n)，其源极连接恒压低电位；所述第二十电容C20的一端接入恒压低电位，另一端连接第二信号点Q’(n)。
其中，所述第三信号点控制模块104包括：第十三薄膜晶体管T13、第十五薄膜晶体管T15以及第十一电容C11，所述第十三薄膜晶体管T13的栅极与所述第十一薄膜晶体管T11的源极相连接，其漏极接入恒压高电位，其源极连接第三节点P(n)；所述第十五薄膜晶体管T15的栅极连接第一信号点Q(n)，其漏极连接恒压低电位，其源极连接第三信号点P(n)；所述第十一电容C11一端连接恒压低电位，另一端连接第三信号点P(n)；可以理解的是，第十三薄膜晶体管T13的导通与断开受所述第一时钟输入模块101所输出时钟信号所控制。
所述第四信号点控制模块204包括：第二十三薄膜晶体管T23、第二十五薄膜晶体管T25以及第二十一电容C21，所述第二十三薄膜晶体管T23的栅极与所述第二十一薄膜晶体管T21的源极相连接，其漏极接入恒压高电位，其源极连接第四节点P’(n)；所述第二十五薄膜晶体管T25的栅极连接第二信号点Q’(n)，其漏极连接恒压低电位，其源极连接第四信号点P’(n)；所述第二十一电容C21一端连接恒压低电位，另一端连接第四信号点P’(n)。可以理解的是，第二十三薄膜晶体管T23的导通与断开受所述第二时钟输入 模块201所输出时钟信号所控制。
其中，第一全局信号作用模块105包括第十七薄膜晶体管T17和第十八薄膜晶体管T18，所述第十七薄膜晶体管T17的栅极与其源极相连接，其漏极连接第n级GOA电路重复单元的第n条扫描信号Gn；所述第十八薄膜晶体管T18的栅极与所述第十七薄膜晶体管T17的栅极相连接，并接入第一全局信号GAS1，其漏极连接第三信号点P(n)，其源极连接恒压低电位；
第二全局信号作用模块205包括二第十七薄膜晶体管T27和第二十八薄膜晶体管T28，所述第二十七薄膜晶体管T27的栅极与其源极相连接，其漏极连接第n级GOA电路重复单元的第n+2条扫描信号Gn+2；所述第二十八薄膜晶体管T28的栅极与所述第二十七薄膜晶体管T27的栅极相连接，并接入第一全局信号GAS1，其漏极连接第四信号点P’(n)，其源极连接恒压低电位。
可以理解的是，在上述的说明中，在一个例子中，所述所有薄膜晶体管均为N沟道的薄膜晶体管，且每一薄膜晶体管的漏极和源极可以互换。
如图2所示，示出了本发明提供的一种GOA电路的一个实施例第一级GOA电路重复单元的部分电路图；可以理解的是，在图2中仅示出了一部份电路，其另一部分电路与图1中下半部分的相同。图2所示出的第一级GOA电路重复单元与图1中示出的第n级GOA电路重复单元的区别在于，在第一级GOA电路重复单元中，所述第十薄膜晶体管(T10)的栅极接入电路起始信号(STV)；
所述第一级GOA电路重复单元进一步包括第十九薄膜晶体管(T19)，所述第十九薄膜晶体管的栅极接入第一级GOA电路重复单元输出的第一条扫描信号(G1)，其源极连接恒压低电位，其漏极连接所述第十薄膜晶体管(T10)的栅极。通过设置该结构，、可以在断电时，由于G1处于高电位，从而使薄膜晶体管T19导通，从而将电路起始信号(STV)的电位下拉，从而使第一级GOA电路重复单元的操作环境与其他级GOA电路重复单元接近，从而可以避免由于电路起始信号(STV)的电位过高而引起的首行残影现象。
图3所示，是本发明提供的一种GOA电路的一个实施例最后一级GOA 电路重复单元的部分电路图；可以理解的是，在图3中仅示出了一部份电路，其另一部分电路与图1中上半部分的相同。图3所示出的最后一级GOA电路重复单元与图1中示出的第n级GOA电路重复单元的区别在于，在最后一级GOA电路重复单元中，所述第二十四薄膜晶体管(T24)的栅极接入电路起始信号(STV)；
所述最后一级GOA电路重复单元进一步包括第二十九薄膜晶体管(T29)，所述第二十九薄膜晶体管的栅极接入最后一级GOA电路重复单元输出的最后一条扫描信号(Glast)，其源极连接恒压低电位，其漏极连接所述第二十四薄膜晶体管(T24)的栅极。通过设置该结构，可以在断电时，由于最后一条扫描信号处于高电位，从而使薄膜晶体管T29导通，从而将电路起始信号(STV)的电位下拉，从而使最后一级GOA电路重复单元的操作环境与其他级GOA电路重复单元接近，从而可以避免由于电路起始信号(STV)的电位过高而引起的尾行残影现象。
如图4所示，是本发明提供一种GOA电路一个实施例中在断电时各信号的时序图。在液晶显示面板断电时，各信号的时序图如图4所示，扫描启动信号STV和第一全局信号GAS1均为高电位(H)，第一扫描控制信号U2D、第二扫描控制信号D2U、所有时钟信号CK均为低电位(L)。此时，在每一级GOA电路重复单元中，在第一全局信号作用模块105中，由于GAS1为高电位，则薄膜晶体管T18、T17均处于导通状态，使第三信号点P(n)的电平下拉至低电位，薄膜晶体管T16、T32均处于截止状态；而由于薄膜晶体管T17导通，故其漏极的电平处于高电位，从而使扫描信号Gn打开；同理，此时扫描信号Gn+1也打开；
故，在断电时，在第一全局信号GAS1的作用下，可以现All Gate ON功能。同时，由于在第一级GOA电路重复单元中设置有薄膜晶体管T19，在最后一级GOA电路重复单元中设置有薄膜晶体管T29，可以消除首尾行的残影现象。
综上所述，本发明通过在每一级GOA电路重复单元中设置有第一全局信号作用模块和第二全局信号作用模块，可以在断电时，实现All Gate ON功能，可以将液晶显示面板的像素开关完全打开，从而及时释放掉像素电极 上的电荷，通过液晶显示面板的数据线(即Data Line)将像素电极的电荷导走，消除液晶显示面板在断电时出现的残影，同时能消除首尾行的残影，可以提高用户体验。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个......”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

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  1. 一种GOA电路，用于液晶显示面板中，其包括级联的多级GOA电路重复单元，每一级GOA电路重复单元均包括：第一正反向扫描模块(100)、第一时钟输入模块(101)、第一信号点控制模块(103)、第三信号点控制模块(104)、第一输出模块(102)、第一全局信号作用模块(105)、第二正反向扫描模块(200)、第二时钟输入模块(201)、第二信号点控制模块(203)、第四信号点控制模块(204)、第二输出模块(202)、第二全局信号作用模块(205)；其中：
    设n为正整数，除第一级GOA电路重复单元和最后一级GOA电路重复单元外，在第n级GOA电路重复单元中：
    所述第一正反向扫描模块(100)与所述第二正反向扫描模块(200)，用于根据第一扫描控制信号或第二扫描控制信号控制GOA电路进行正向扫描或反向扫描；
    所述第一输出模块(102)、第二输出模块(202)分别接入第一条时钟信号(CK1)，并分别利用所述第一条时钟信号依次输出第n条扫描信号(Gn)、第n+2条扫描信号(Gn+2)；
    所述第一时钟输入模块(101)，用于输出第二条时钟信号(CK2)或第四条时钟信号(CK4)至所述第三信号点控制模块(104)；所述第二时钟输入模块(201)用于输出第四条时钟信号(CK4)或第二条时钟信号(CK2)至所述第四信号点控制模块(204)；
    所述第一信号点控制模块(103)用于在第n级GOA电路重复单元作用期间，控制第一信号点(Q(n))的电平；所述第二信号点控制模块(203)用于在第n级GOA电路重复单元作用期间，控制第二信号点(Q’(n))的电平；
    所述第三信号点控制模块(104)用于在第n级GOA电路重复单元作用期间，控制第三信号点(P(n))的电平；所述第四信号点控制模块(204)用于在第n级GOA电路重复单元作用期间，控制第四信号点(P’(n))的电平；
    第一全局信号作用模块(105)和所述第二全局信号作用模块(205)，用于在断电时，利用第一全局信号(GAS1)实现第n级GOA电路重复单元 中所有扫描信号打开。
  2. 如权利要求1所述的电路，其中，所述第一正反向扫描模块(100)、第一时钟输入模块(101)、第一信号点控制模块(103)、第一输出模块(102)均电连接于第一信号点(Q(n))，所述第三信号点控制模块(104)和第一全局信号作用模块(105)均电连接于第三信号点(P(n))；所述第二正反向扫描模块(200)、第二时钟输入模块(201)、第二信号点控制模块(203)、第二输出模块(202)均电连接于第二信号点(Q’(n))，所述第四信号点控制模块(204)和第二全局信号作用模块(205)电连接于第四信号点(P’(n))。
  3. 如权利要求2所述的电路，其中，除第一级GOA电路重复单元和最后一级GOA电路重复单元外，在第n级GOA电路重复单元中：
    所述第一正反向扫描模块(100)包括：第十薄膜晶体管(T10)和第十四薄膜晶体管(T14)，所述第十薄膜晶体管的栅极接入上一级第n-1级GOA电路重复单元输出的第n-2条扫描信号(Gn-2)，其源极接第一扫描控制信号，其漏极电连接第一节点(Q(n))；第十四薄膜晶体管(T14)的栅极接入第n级GOA电路重复单元输出的第n+2条扫描信号(Gn+2)，其源极接第二扫描控制信号，其漏极电连接第一节点(Q(n))；
    所述第二正反向扫描模块(200)包括：第二十薄膜晶体管(T20)和第二十四薄膜晶体管(T24)，所述第二十薄膜晶体管的栅极接入第n级GOA电路重复单元输出的第n条扫描信号(Gn)，其源极接第一扫描控制信号，其漏极电连接第二节点(Q’(n))；第二十四薄膜晶体管(T24)的栅极接入下一级第n+1级GOA电路重复单元输出的第n+4条扫描信号(Gn+4)，其源极接第二扫描控制信号，其漏极电连接第二节点(Q’(n))。
  4. 如权利要求3所述的GOA电路，其中，在第一级GOA电路重复单元中，所述第十薄膜晶体管(T10)的栅极接入电路起始信号(STV)；
    所述第一级GOA电路重复单元进一步包括第十九薄膜晶体管(T19)，所述第十九薄膜晶体管的栅极接入第一级GOA电路重复单元输出的第一条 扫描信号(G1)，其源极连接恒压低电位，其漏极连接所述第十薄膜晶体管(T10)的栅极。
  5. 如权利要求3所述的GOA电路，其中，在最后一级GOA电路重复单元中，所述第二十四薄膜晶体管(T24)的栅极接入电路起始信号(STV)；
    所述最后一级GOA电路重复单元进一步包括第二十九薄膜晶体管(T29)，所述第二十九薄膜晶体管的栅极接入最后一级GOA电路重复单元输出的最后一条扫描信号(Glast)，其源极连接恒压低电位，其漏极连接所述第二十四薄膜晶体管(T24)的栅极。
  6. 如权利要求5所述的GOA电路，其中，所述第一输出模块(102)包括：第三十薄膜晶体管(T30)、第三十一薄膜晶体管(T31)以及第三十二薄膜晶体管(T32)，所述第三十薄膜晶体管(T30)源极电连接第一节点Q(n)，其栅极连接恒压高电位；所述第三十一薄膜晶体管(T31)栅极连接所述第三十薄膜晶体管的漏极，其漏极接入第一条时钟信号(CK1)；所述第三十二薄膜晶体管(T30)的栅极连接第三节点(P(n))，其源极连接恒压低电位，其漏极与所述第三十一薄膜晶体管(T31)的源极相连接，并电连接于第n级GOA电路重复单元输出的第n条扫描信号(Gn)；
    所述第二输出模块(202)包括：第四十薄膜晶体管(T40)、第四十一薄膜晶体管(T41)以及第四十二薄膜晶体管(T42)，所述第四十薄膜晶体管(T40)源极电连接第二节点(Q’(n))，其栅极连接恒压高电位；所述第四十一薄膜晶体管(T41)栅极连接所述第四十薄膜晶体管的漏极，其漏极接入第一条时钟信号(CK1)；所述第四十二薄膜晶体管(T40)的栅极连接第四节点(P’(n))，其源极连接恒压低电位，其漏极与所述第四十一薄膜晶体管(T41)的源极相连接，并电连接于第n级GOA电路重复单元输出的第n+2条扫描信号(Gn+2)。
  7. 如权利要求6所述的GOA电路，其中，所述第一时钟输入模块(101)包括：第十一薄膜晶体管(T11)、第十二薄膜晶体管(T12)，所述第十一薄 膜晶体管(T11)的栅极接入第一扫描控制信号，其漏极接入第二条时钟信号(CK2)；所述第十二薄膜晶体管(T12)的栅极接入第二扫描控制信号，其源极接入第四条时钟信号(CK4)，其漏极连接所述第十一薄膜晶体管(T11)的源极；
    所述第二时钟输入模块(201)包括：第二十一薄膜晶体管(T21)、第二十二薄膜晶体管(T22)，所述第二十一薄膜晶体管(T21)的栅极接入第一扫描控制信号，其漏极接入第四条时钟信号(CK4)；所述第二十二薄膜晶体管(T22)的栅极接入第二扫描控制信号，其源极接入第二条时钟信号(CK2)，其漏极连接所述第二十一薄膜晶体管(T21)的源极。
  8. 如权利要求7所述的GOA电路，其中，所述第一信号点控制模块(103)包括第十六薄膜晶体管(T16)及第十电容(C10)，所述第十六薄膜晶体管(T16)栅极连接第三信号点(P(n))，其漏极连接第一信号点(Q(n))，其源极连接恒压低电位；所述第十电容(C10)的一端接入恒压低电位，另一端连接第一信号点(Q(n))；
    所述第二信号点控制模块(203)包括第二十六薄膜晶体管(T26)及第二十电容(C20)，所述第二十六薄膜晶体管(T26)栅极连接第四信号点(P’(n))，其漏极连接第二信号点(Q’(n))，其源极连接恒压低电位；所述第二十电容(C20)的一端接入恒压低电位，另一端连接第二信号点(Q’(n))。
  9. 如权利要求8所述的GOA电路，其中，所述第三信号点控制模块(104)包括：第十三薄膜晶体管(T13)、第十五薄膜晶体管(T15)以及第十一电容(C11)，所述第十三薄膜晶体管(T13)的栅极与所述第十一薄膜晶体管(T11)的源极相连接，其漏极接入恒压高电位，其源极连接第三节点(P(n))；所述第十五薄膜晶体管(T15)的栅极连接第一信号点(Q(n))，其漏极连接恒压低电位，其源极连接第三信号点(P(n))；所述第十一电容(C11)一端连接恒压低电位，另一端连接第三信号点(P(n))；
    所述第四信号点控制模块(204)包括：第二十三薄膜晶体管(T23)、第二十五薄膜晶体管(T25)以及第二十一电容(C21)，所述第二十三薄膜 晶体管(T23)的栅极与所述第二十一薄膜晶体管(T21)的源极相连接，其漏极接入恒压高电位，其源极连接第四节点(P’(n))；所述第二十五薄膜晶体管(T25)的栅极连接第二信号点(Q’(n))，其漏极连接恒压低电位，其源极连接第四信号点(P’(n))；所述第二十一电容(C21)一端连接恒压低电位，另一端连接第四信号点(P’(n))。
  10. 如权利要求9所述的GOA电路，其中，第一全局信号作用模块(105)包括第十七薄膜晶体管(T17)和第十八薄膜晶体管(T18)，所述第十七薄膜晶体管(T17)的栅极与其源极相连接，其漏极连接第n级GOA电路重复单元的第n条扫描信号(Gn)；所述第十八薄膜晶体管(T18)的栅极与所述第十七薄膜晶体管(T17)的栅极相连接，并接入第一全局信号(GAS1)，其漏极连接第三信号点(P(n))，其源极连接恒压低电位；
    第二全局信号作用模块(205)包括二第十七薄膜晶体管(T27)和第二十八薄膜晶体管(T28)，所述第二十七薄膜晶体管(T27)的栅极与其源极相连接，其漏极连接第n级GOA电路重复单元的第n+2条扫描信号(Gn+2)；所述第二十八薄膜晶体管(T28)的栅极与所述第二十七薄膜晶体管(T27)的栅极相连接，并接入第一全局信号(GAS1)，其漏极连接第四信号点(P’(n))，其源极连接恒压低电位。
  11. 如权利要求10所述的GOA电路，其中，所述所有薄膜晶体管均为N沟道的薄膜晶体管。
  12. 一种GOA电路，用于液晶显示面板中，其中，包括级联的多级GOA电路重复单元，每一级GOA电路重复单元均包括：第一正反向扫描模块(100)、第一时钟输入模块(101)、第一信号点控制模块(103)、第三信号点控制模块(104)、第一输出模块(102)、第一全局信号作用模块(105)、第二正反向扫描模块(200)、第二时钟输入模块(201)、第二信号点控制模块(203)、第四信号点控制模块(204)、第二输出模块(202)、第二全局信号作用模块(205)；其中：
    设n为正整数，除第一级GOA电路重复单元和最后一级GOA电路重 复单元外，在第n级GOA电路重复单元中：
    所述第一正反向扫描模块(100)与所述第二正反向扫描模块(200)，用于根据第一扫描控制信号或第二扫描控制信号控制GOA电路进行正向扫描或反向扫描；
    所述第一输出模块(102)、第二输出模块(202)分别接入第一条时钟信号(CK1)，并分别利用所述第一条时钟信号依次输出第n条扫描信号(Gn)、第n+2条扫描信号(Gn+2)；
    所述第一时钟输入模块(101)，用于输出第二条时钟信号(CK2)或第四条时钟信号(CK4)至所述第三信号点控制模块(104)；所述第二时钟输入模块(201)用于输出第四条时钟信号(CK4)或第二条时钟信号(CK2)至所述第四信号点控制模块(204)；
    所述第一信号点控制模块(103)用于在第n级GOA电路重复单元作用期间，控制第一信号点(Q(n))的电平；所述第二信号点控制模块(203)用于在第n级GOA电路重复单元作用期间，控制第二信号点(Q’(n))的电平；
    所述第三信号点控制模块(104)用于在第n级GOA电路重复单元作用期间，控制第三信号点(P(n))的电平；所述第四信号点控制模块(204)用于在第n级GOA电路重复单元作用期间，控制第四信号点(P’(n))的电平；
    第一全局信号作用模块(105)和所述第二全局信号作用模块(205)，用于在断电时，利用第一全局信号(GAS1)实现第n级GOA电路重复单元中所有扫描信号打开；
    其中，所述第一全局信号作用模块(105)包括第十七薄膜晶体管(T17)和第十八薄膜晶体管(T18)，所述第十七薄膜晶体管(T17)的栅极与其源极相连接，其漏极连接第n级GOA电路重复单元的第n条扫描信号(Gn)；所述第十八薄膜晶体管(T18)的栅极与所述第十七薄膜晶体管(T17)的栅极相连接，并接入第一全局信号(GAS1)，其漏极连接第三信号点(P(n))，其源极连接恒压低电位；
    所述第二全局信号作用模块(205)包括二第十七薄膜晶体管(T27)和第二十八薄膜晶体管(T28)，所述第二十七薄膜晶体管(T27)的栅极与其 源极相连接，其漏极连接第n级GOA电路重复单元的第n+2条扫描信号(Gn+2)；所述第二十八薄膜晶体管(T28)的栅极与所述第二十七薄膜晶体管(T27)的栅极相连接，并接入第一全局信号(GAS1)，其漏极连接第四信号点(P’(n))，其源极连接恒压低电位。
  13. 如权利要求12所述的电路，其中，所述第一正反向扫描模块(100)、第一时钟输入模块(101)、第一信号点控制模块(103)、第一输出模块(102)均电连接于第一信号点(Q(n))，所述第三信号点控制模块(104)和第一全局信号作用模块(105)均电连接于第三信号点(P(n))；所述第二正反向扫描模块(200)、第二时钟输入模块(201)、第二信号点控制模块(203)、第二输出模块(202)均电连接于第二信号点(Q’(n))，所述第四信号点控制模块(204)和第二全局信号作用模块(205)电连接于第四信号点(P’(n))。
  14. 如权利要求12所述的电路，其中，除第一级GOA电路重复单元和最后一级GOA电路重复单元外，在第n级GOA电路重复单元中：
    所述第一正反向扫描模块(100)包括：第十薄膜晶体管(T10)和第十四薄膜晶体管(T14)，所述第十薄膜晶体管的栅极接入上一级第n-1级GOA电路重复单元输出的第n-2条扫描信号(Gn-2)，其源极接第一扫描控制信号，其漏极电连接第一节点(Q(n))；第十四薄膜晶体管(T14)的栅极接入第n级GOA电路重复单元输出的第n+2条扫描信号(Gn+2)，其源极接第二扫描控制信号，其漏极电连接第一节点(Q(n))；
    所述第二正反向扫描模块(200)包括：第二十薄膜晶体管(T20)和第二十四薄膜晶体管(T24)，所述第二十薄膜晶体管的栅极接入第n级GOA电路重复单元输出的第n条扫描信号(Gn)，其源极接第一扫描控制信号，其漏极电连接第二节点(Q’(n))；第二十四薄膜晶体管(T24)的栅极接入下一级第n+1级GOA电路重复单元输出的第n+4条扫描信号(Gn+4)，其源极接第二扫描控制信号，其漏极电连接第二节点(Q’(n))。
  15. 如权利要求12所述的GOA电路，其中，在第一级GOA电路重复 单元中，所述第十薄膜晶体管(T10)的栅极接入电路起始信号(STV)；
    所述第一级GOA电路重复单元进一步包括第十九薄膜晶体管(T19)，所述第十九薄膜晶体管的栅极接入第一级GOA电路重复单元输出的第一条扫描信号(G1)，其源极连接恒压低电位，其漏极连接所述第十薄膜晶体管(T10)的栅极。
  16. 如权利要求12所述的GOA电路，其中，在最后一级GOA电路重复单元中，所述第二十四薄膜晶体管(T24)的栅极接入电路起始信号(STV)；
    所述最后一级GOA电路重复单元进一步包括第二十九薄膜晶体管(T29)，所述第二十九薄膜晶体管的栅极接入最后一级GOA电路重复单元输出的最后一条扫描信号(Glast)，其源极连接恒压低电位，其漏极连接所述第二十四薄膜晶体管(T24)的栅极。
  17. 如权利要求12所述的GOA电路，其中，所述第一输出模块(102)包括：第三十薄膜晶体管(T30)、第三十一薄膜晶体管(T31)以及第三十二薄膜晶体管(T32)，所述第三十薄膜晶体管(T30)源极电连接第一节点Q(n)，其栅极连接恒压高电位；所述第三十一薄膜晶体管(T31)栅极连接所述第三十薄膜晶体管的漏极，其漏极接入第一条时钟信号(CK1)；所述第三十二薄膜晶体管(T30)的栅极连接第三节点(P(n))，其源极连接恒压低电位，其漏极与所述第三十一薄膜晶体管(T31)的源极相连接，并电连接于第n级GOA电路重复单元输出的第n条扫描信号(Gn)；
    所述第二输出模块(202)包括：第四十薄膜晶体管(T40)、第四十一薄膜晶体管(T41)以及第四十二薄膜晶体管(T42)，所述第四十薄膜晶体管(T40)源极电连接第二节点(Q’(n))，其栅极连接恒压高电位；所述第四十一薄膜晶体管(T41)栅极连接所述第四十薄膜晶体管的漏极，其漏极接入第一条时钟信号(CK1)；所述第四十二薄膜晶体管(T40)的栅极连接第四节点(P’(n))，其源极连接恒压低电位，其漏极与所述第四十一薄膜晶体管(T41)的源极相连接，并电连接于第n级GOA电路重复单元输出的第n+2条扫描信号(Gn+2)。
  18. 如权利要求12所述的GOA电路，其中，所述第一时钟输入模块(101)包括：第十一薄膜晶体管(T11)、第十二薄膜晶体管(T12)，所述第十一薄膜晶体管(T11)的栅极接入第一扫描控制信号，其漏极接入第二条时钟信号(CK2)；所述第十二薄膜晶体管(T12)的栅极接入第二扫描控制信号，其源极接入第四条时钟信号(CK4)，其漏极连接所述第十一薄膜晶体管(T11)的源极；
    所述第二时钟输入模块(201)包括：第二十一薄膜晶体管(T21)、第二十二薄膜晶体管(T22)，所述第二十一薄膜晶体管(T21)的栅极接入第一扫描控制信号，其漏极接入第四条时钟信号(CK4)；所述第二十二薄膜晶体管(T22)的栅极接入第二扫描控制信号，其源极接入第二条时钟信号(CK2)，其漏极连接所述第二十一薄膜晶体管(T21)的源极。
  19. 如权利要求12所述的GOA电路，其中，所述第一信号点控制模块(103)包括第十六薄膜晶体管(T16)及第十电容(C10)，所述第十六薄膜晶体管(T16)栅极连接第三信号点(P(n))，其漏极连接第一信号点(Q(n))，其源极连接恒压低电位；所述第十电容(C10)的一端接入恒压低电位，另一端连接第一信号点(Q(n))；
    所述第二信号点控制模块(203)包括第二十六薄膜晶体管(T26)及第二十电容(C20)，所述第二十六薄膜晶体管(T26)栅极连接第四信号点(P’(n))，其漏极连接第二信号点(Q’(n))，其源极连接恒压低电位；所述第二十电容(C20)的一端接入恒压低电位，另一端连接第二信号点(Q’(n))。
  20. 如权利要求12所述的GOA电路，其中，所述第三信号点控制模块(104)包括：第十三薄膜晶体管(T13)、第十五薄膜晶体管(T15)以及第十一电容(C11)，所述第十三薄膜晶体管(T13)的栅极与所述第十一薄膜晶体管(T11)的源极相连接，其漏极接入恒压高电位，其源极连接第三节点(P(n))；所述第十五薄膜晶体管(T15)的栅极连接第一信号点(Q(n))，其漏极连接恒压低电位，其源极连接第三信号点(P(n))；所述第十一电容 (C11)一端连接恒压低电位，另一端连接第三信号点(P(n))；
    所述第四信号点控制模块(204)包括：第二十三薄膜晶体管(T23)、第二十五薄膜晶体管(T25)以及第二十一电容(C21)，所述第二十三薄膜晶体管(T23)的栅极与所述第二十一薄膜晶体管(T21)的源极相连接，其漏极接入恒压高电位，其源极连接第四节点(P’(n))；所述第二十五薄膜晶体管(T25)的栅极连接第二信号点(Q’(n))，其漏极连接恒压低电位，其源极连接第四信号点(P’(n))；所述第二十一电容(C21)一端连接恒压低电位，另一端连接第四信号点(P’(n))。
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