WO2022007071A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2022007071A1
WO2022007071A1 PCT/CN2020/106729 CN2020106729W WO2022007071A1 WO 2022007071 A1 WO2022007071 A1 WO 2022007071A1 CN 2020106729 W CN2020106729 W CN 2020106729W WO 2022007071 A1 WO2022007071 A1 WO 2022007071A1
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WO
WIPO (PCT)
Prior art keywords
sub
gate
lines
display panel
pixels
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Application number
PCT/CN2020/106729
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English (en)
French (fr)
Inventor
王添鸿
钟云肖
金一坤
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/053,352 priority Critical patent/US11335230B2/en
Publication of WO2022007071A1 publication Critical patent/WO2022007071A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

Definitions

  • the present application relates to the technical field of display panels, and in particular, to a display panel.
  • a gate fanout is designed so that the gate drive circuit is electrically connected to the scan line through the gate fanout.
  • the line width of the gate fan-out trace is very small, resulting in a large load and a small capacitance, which in turn leads to a large signal delay on the gate fan-out trace, reducing the charging rate of the sub-pixels.
  • Embodiments of the present application provide a display panel to solve the problem of relatively large signal delay on the gate fan-out traces in the prior art.
  • An embodiment of the present application provides a display panel, which includes a display area and a non-display area located on one side of the display area; the display area includes a plurality of sub-pixels arranged in multiple rows and columns, and the sub-pixels are arranged in a one-to-one correspondence with the multiple columns of sub-pixels.
  • the fan-out traces extend to the non-display area along the column direction respectively, and every two columns of sub-pixels form a sub-pixel group, and two data lines are arranged between the two columns of sub-pixels in the sub-pixel group, and any adjacent ones of the data lines are arranged.
  • At least one sub-pixel group is spaced between the two gate fan-out lines; there is a gap between the two data lines in the sub-pixel group, and the width of the gate fan-out lines is equal to that in the sub-pixel group The sum of the width of the two data lines and the width of the gap.
  • the gate fan-out wiring and the data line are arranged in the same layer, and the gate fan-out wiring and the scan line are arranged in a different layer.
  • a gate insulating layer is provided between the gate fan-out wiring and the scan line, a via hole is provided in the gate insulating layer, and the gate fan-out wiring passes through the via hole and corresponds to the corresponding gate insulating layer.
  • the scan lines are electrically connected.
  • the display panel further includes a light shielding layer; the light shielding layer is arranged corresponding to the positions of the data lines, the scan lines and the gate fan-out lines.
  • the light-shielding layer includes a first light-shielding pattern and a second light-shielding pattern; the orthographic projection of the first light-shielding pattern on the film layer where the gate fan-out trace is located completely covers the gate fan-out trace, so The orthographic projection of the second shading pattern on the film layer where the data lines are located completely covers the two data lines in the sub-pixel group.
  • the length of the first light shielding pattern in the row direction is the same as the length of the second light shielding pattern in the row direction.
  • the non-display area includes a gate driving circuit and the source driving circuit; the gate driving circuit is electrically connected with the gate fan-out wiring, and the source driving circuit is connected with the data line Electrical connection.
  • the gate driving circuit includes a multi-level gate driving unit; the multi-level gate driving unit is electrically connected to the plurality of gate fan-out wires in a one-to-one correspondence.
  • the source driving circuit is located on the side of the gate driving circuit away from the display area, the multi-level gate driving units are arranged in parallel and spaced apart; the data lines are driven through the multi-level gate driving units The gap between the cells extends to the source driver circuit and is electrically connected with the source driver circuit.
  • An embodiment of the present application also provides a display panel, including a display area and a non-display area located on one side of the display area; the display area includes a plurality of sub-pixels arranged in multiple rows and columns, and the sub-pixels are arranged in a one-to-one correspondence with the multiple columns of sub-pixels.
  • the fan-out traces extend to the non-display area along the column direction respectively, and every two columns of sub-pixels form a sub-pixel group, and two data lines are arranged between the two columns of sub-pixels in the sub-pixel group, and any adjacent ones of the data lines are arranged. At least one sub-pixel group is spaced between the two gate fan-out lines; the width of the gate fan-out lines is not less than the sum of the widths of the two data lines in the sub-pixel group.
  • the gate fan-out wiring and the data line are arranged in the same layer, and the gate fan-out wiring and the scan line are arranged in a different layer.
  • a gate insulating layer is provided between the gate fan-out wiring and the scan line, a via hole is provided in the gate insulating layer, and the gate fan-out wiring passes through the via hole and corresponds to the corresponding gate insulating layer.
  • the scan lines are electrically connected.
  • the display panel further includes a light shielding layer; the light shielding layer is arranged corresponding to the positions of the data lines, the scan lines and the gate fan-out lines.
  • the light-shielding layer includes a first light-shielding pattern and a second light-shielding pattern; the orthographic projection of the first light-shielding pattern on the film layer where the gate fan-out trace is located completely covers the gate fan-out trace, so The orthographic projection of the second shading pattern on the film layer where the data lines are located completely covers the two data lines in the sub-pixel group.
  • the length of the first light shielding pattern in the row direction is the same as the length of the second light shielding pattern in the row direction.
  • the non-display area includes a gate drive circuit and a source drive circuit; the gate drive circuit is electrically connected to the gate fan-out wiring, and the source drive circuit is electrically connected to the data line connect.
  • the gate driving circuit includes a multi-level gate driving unit; the multi-level gate driving unit is electrically connected to the plurality of gate fan-out wires in a one-to-one correspondence.
  • the source driving circuit is located on the side of the gate driving circuit away from the display area, the multi-level gate driving units are arranged in parallel and spaced apart; the data lines are driven through the multi-level gate driving units The gap between the cells extends to the source driver circuit and is electrically connected with the source driver circuit.
  • the beneficial effects of the present application are: by arranging data lines and gate fan-out lines extending to the non-display area along the column direction, every two columns of sub-pixels constitute a group of sub-pixels, and between the two columns of sub-pixels in each group of sub-pixels There are two data lines, at least one group of sub-pixels is spaced between any two adjacent gate fan-out lines, and the width of the gate fan-out lines is not less than the sum of the widths of the two data lines in a group of sub-pixels , so as to reduce the signal delay on the gate fan-out line, improve the sub-pixel charging rate and prevent mischarging while realizing a narrow-frame display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the positional relationship of scan lines, data lines, and gate fan-out lines in a display panel according to an embodiment of the present application;
  • FIG. 3 is a schematic diagram of the positional relationship between a row of sub-pixels and a light shielding layer in a display panel according to an embodiment of the present application.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, “plurality” means two or more. Additionally, the term “comprising” and any variations thereof are intended to cover non-exclusive inclusion.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • an embodiment of the present application provides a display panel including a display area 10 and a non-display area 20.
  • the non-display area 20 is located on one side of the display area 10 to ensure that the display panel has extremely narrow borders or no borders on three sides. design.
  • the display area 10 includes a plurality of sub-pixels 1 arranged in a plurality of rows and columns, a plurality of data lines 2 arranged in a one-to-one correspondence with the multi-columns of the sub-pixels 1, and a plurality of scan lines 3 arranged in a one-to-one correspondence with the plurality of rows of the sub-pixels 1 . , and a plurality of gate fan-out traces 4 connected to the plurality of scan lines 3 in a one-to-one correspondence.
  • the plurality of data lines 2 extend to the non-display area 20 along the column direction A, that is, the display area 10 and the non-display area 20 are arranged along the column direction.
  • the plurality of scan lines 3 extend along the row direction B, and the plurality of data lines 2 and the plurality of scan lines 3 are arranged in different layers, so that the plurality of data lines 2 and the plurality of scan lines 3 are insulated and intersected to define a plurality of sub-pixels 1 .
  • a plurality of scan lines 3 are set in a one-to-one correspondence with a plurality of rows of sub-pixels 1, that is, the number of scan lines 3 is the same as the number of rows of sub-pixels 1, so that when scanning each row of sub-pixels 1, through the corresponding rows of sub-pixels 1.
  • the scan lines input scan signals to the sub-pixels 1 in the row.
  • a plurality of data lines 2 are arranged in a one-to-one correspondence with a plurality of columns of sub-pixels 1, that is, the number of data lines 2 is the same as the number of columns of sub-pixels 1, so that during the input scan signal of each row of sub-pixels 1, through each data line 2 sequentially A data signal is input to a corresponding column of sub-pixels 1 in the row of sub-pixels 1, and each sub-pixel 1 in the row of sub-pixels 1 is charged in turn.
  • the plurality of gate fan-out lines 4 extend to the non-display area 20 along the column direction A, that is, the plurality of gate fan-out lines 4 and the plurality of data lines 2 are arranged in the same layer and in parallel.
  • the number of gate fan-out lines 4 is the same as the number of scan lines 3 , and the plurality of gate fan-out lines 4 are electrically connected to the plurality of scan lines 3 in one-to-one correspondence.
  • every two columns of sub-pixels 1 may constitute a group of sub-pixels, that is, a sub-pixel group 30 .
  • a group of sub-pixels that is, in each sub-pixel group 30
  • two data lines 2 are provided at the gap between two columns of sub-pixels 1
  • the two columns of sub-pixels 1 are arranged in a one-to-one correspondence with the two data lines 2, that is, The two data lines 2 respectively input data signals to the two columns of sub-pixels 1 .
  • any two adjacent gate fan-out lines 4 are separated by at least one group of sub-pixels, that is, at least one sub-pixel group 30 is separated.
  • a sub-pixel group 30 is spaced between any two adjacent gate fan-out lines 4, that is, the gate fan-out line 4 is located in the gap between two adjacent sub-pixel groups 30, and the data Line 2 is located at the gap between the two columns of sub-pixels 1 in each sub-pixel group 30, so that the gate fan-out line 4 and the data line 2 are located at different gaps, that is, between the gate fan-out line 4 and the data line 2
  • At least one column of sub-pixels 2 is spaced apart, so as to prevent the gate fan-out traces 4 and the data lines 2 from being too close to be coupled with each other, resulting in uneven display (mura).
  • the width of the gate fan-out line 4 is not less than the sum of the widths of the two data lines 2 in a group of sub-pixels, and the width of the gate fan-out line 4 is smaller than the width of the gap between the adjacent two columns of sub-pixels, that is, the phase The spacing between two adjacent columns of sub-pixels.
  • the width of the gate fan-out trace 4 refers to the length of the gate fan-out trace 4 in the row direction B
  • the sum of the widths of the two data lines 2 refers to the sum of the lengths of the two data lines 2 in the row direction B.
  • the load size of the gate fan-out trace 4 is effectively reduced, and the capacitance is increased, thereby reducing the scanning signal on the gate fan-out trace 4 .
  • the width of the gate fan-out trace 4 is equal to the width of the two data lines 2 in the group of sub-pixels and the width of the gap Sum.
  • the delay on the gate fan-out trace 4 is reduced from 1.01us in the prior art to 0.87us, which effectively improves the delay of the scanning signal.
  • the display panel includes a substrate 40 , a first metal layer 50 on the substrate 40 , a gate insulating layer 60 on the substrate 40 and the first metal layer 50 , and a gate insulating layer 60 on the second metal layer 70 .
  • the first metal layer 50 includes scan lines 3
  • the second metal layer 70 includes data lines 2 and gate fan-out lines 4 .
  • the gate insulating layer 60 is provided with a via hole 5 at the connection between each gate fan-out trace 4 and its corresponding scan line 3 , so that each gate fan-out trace 4 is connected to its corresponding scan line 3 through the via hole 5 .
  • each sub-pixel 1 may include one thin film transistor 6 .
  • the first metal layer 50 also includes the gate of the thin film transistor 6, that is, the gate is arranged in the same layer as the scan line 3, and the gate of the thin film transistor 6 of each sub-pixel 1 is electrically connected to the scan line 3 corresponding to the row of the sub-pixel 1.
  • the scanning line 3 inputs the scanning signal to the sub-pixel 1 through the gate of the thin film transistor 6 .
  • the second metal layer 70 also includes the source and drain electrodes of the thin film transistor 6 , that is, the source electrode and the drain electrode are arranged in the same layer as the data line 2 and the gate fan-out line 4 , and the source electrode of the thin film transistor 6 of each sub-pixel 1 is located in the same layer.
  • the data line 2 corresponding to the column where the sub-pixel 1 is located is electrically connected, so that the data line 2 inputs a data signal to the sub-pixel 1 through the source of the thin film transistor 6 .
  • the materials of the first metal layer 50 and the second metal layer 70 can be conductive materials, such as copper, aluminum, silver and other metals or metal alloys.
  • the plurality of sub-pixels 1 may include red sub-pixels R, green sub-pixels G, blue sub-pixels B, etc., which are not specifically limited herein.
  • the non-display area 20 includes the gate driving circuit 7 and the source driving circuit 8 , that is, the gate driving circuit 7 and the source driving circuit 8 are located on the same side of the display area 10 .
  • the gate drive circuit 7 is electrically connected to the plurality of gate fan-out lines 4, so that the gate drive circuit 7 is electrically connected to the plurality of scan lines 3 through the plurality of gate fan-out lines 4, and each row of sub-pixels is scanned.
  • the gate driving circuit 7 outputs a scan signal to the sub-pixels 1 in the row through the corresponding gate fan-out wiring 4 and the corresponding scan line 3 .
  • the source driving circuit 8 is electrically connected to the plurality of data lines 2 , so that during each row of sub-pixels 1 inputting scan signals, the source driving circuit 8 sequentially sends each sub-pixel in the row of sub-pixels 1 through the plurality of data lines 2 1 Output data signal.
  • the gate driving circuit 7 includes a multi-level gate driving unit 71 , and the multi-level gate driving unit 71 is electrically connected to the plurality of gate fan-out wires 4 in one-to-one correspondence.
  • the multi-level gate driving units 71 are arranged in parallel and spaced apart, that is, the multi-level gate driving units 71 are arranged in sequence along the row direction B, and there is a gap between any adjacent two-level gate driving units 71 .
  • the first-level gate driving unit 71 corresponds to the position of the sub-pixels 1 in two adjacent columns, that is, the length of the first-level gate driving unit 71 in the row direction B is the same as the length in the row direction B of the sub-pixels 1 in the adjacent two columns, And the gap between adjacent two-stage gate driving units 71 corresponds to the position of the gap between two columns of sub-pixels in the sub-pixel group 30 .
  • the source driving circuit 8 is located on the side of the gate driving circuit 7 away from the display area 10 , that is, the gate driving circuit 7 is located between the source driving circuit 8 and the display area 10 .
  • the two data lines 2 in the sub-pixel group 30 extend to the non-display area 20 , extend to the source driving circuit 8 through the gap between the corresponding two-stage gate driving units 71 , and are electrically connected to the source driving circuit 8 .
  • the display panel further includes a light-shielding layer 9, and the light-shielding layer 9 is located on the side of the second metal layer 70 away from the substrate 40.
  • the light-shielding layer 9 is connected to a plurality of data lines 2 and a plurality of scan lines 3.
  • the orthographic projection of the light shielding layer 9 on the substrate 40 covers the plurality of data lines 2, the plurality of scan lines 3 and the plurality of gate fan-out lines 4 on the substrate.
  • the orthographic projection on 40 is used to block the plurality of data lines 2 , the plurality of scan lines 3 and the plurality of gate fan-out traces 4 .
  • the blocking layer 9 may be a black matrix.
  • the light-shielding layer 9 includes a plurality of first light-shielding patterns 91 arranged in a one-to-one correspondence with a plurality of gate fan-out traces 4, and a plurality of second light-shielding patterns arranged in a one-to-one correspondence with the two data lines 2 in the plurality of sub-pixel groups 30. 92 , and a plurality of third shading patterns (not shown in the figure) that are arranged in a one-to-one correspondence with the plurality of scan lines 3 .
  • each first shading pattern 91 on the substrate 40 covers the orthographic projection of its corresponding gate fan-out trace 4 on the substrate 40
  • the orthographic projection of each second shading pattern 92 on the substrate 40 covers The orthographic projection of the two data lines 2 in the corresponding sub-pixel group 30 on the substrate 40
  • the orthographic projection of each third shading pattern on the substrate 40 covers the corresponding scan line 3 on the substrate 40. Orthographic projection.
  • each first light-shielding pattern 91 in the row direction B is the same as the length of the second light-shielding pattern 92 in the row direction B, and the length of the first light-shielding pattern 91 in the row direction B is the same as the length of the gate fan-out trace 4
  • the width is the same, and the length of the second shading pattern 92 in the row direction B is the same as the sum of the width of the two data lines 2 in the sub-pixel group 30 and the width of the gap between the two data lines 2, so as to ensure the adjacent sub-pixels
  • the occlusion area between 1 and 1 is the same to avoid the thickness difference on the display, thereby optimizing the display effect.
  • every two columns of sub-pixels can form a group of sub-pixels, and between the two columns of sub-pixels in each group of sub-pixels
  • There are two data lines at least one group of sub-pixels is spaced between any two adjacent gate fan-out lines, and the width of the gate fan-out lines is not less than the width of the two data lines in a group of sub-pixels. and, so as to reduce the signal delay on the gate fan-out trace, improve the sub-pixel charging rate and prevent mischarging while realizing a narrow-frame display panel.

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Abstract

本申请公开了一种显示面板。显示面板包括多个子像素，多条数据线，多条扫描线，以及多条栅极扇出走线；每两列子像素构成子像素组，子像素组中的两列子像素之间设有两条数据线，任意相邻的两条栅极扇出走线之间间隔至少一个子像素组；栅极扇出走线的宽度不小于子像素组中两条数据线的宽度之和。

Description

显示面板
本申请要求于2020年7月7日提交中国专利局、申请号为202010648369.9、发明名称为“显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示面板技术领域，尤其涉及一种显示面板。
 背景技术
近年来，大尺寸、高解析度、超窄边框（UNB，Ultra Narrow Border）的显示屏成为市场趋势，广受市场关注的拼接屏更是对显示屏的极致窄边框提出需求。目前，将GOA（栅极驱动电路）设置在源极驱动电路同侧边框（GOA in Source Border技术），因其可用于实现三边极致窄边框的拼接显示而成为显示行业的热点。
为了实现栅极驱动电路与源极驱动电路的同侧设置，设计栅极扇出走线（Gate Fanout），使栅极驱动电路通过栅极扇出走线与扫描线电性连接。但栅极扇出走线的线宽非常小，导致其负载较大，电容较小，进而导致栅极扇出走线上的信号延迟较大，降低子像素的充电率。
 技术问题
本申请实施例提供一种显示面板，以解决现有技术中栅极扇出走线上的信号延迟较大的问题。
 技术解决方案
本申请实施例提供了一种显示面板，包括显示区和位于显示区一侧的非显示区；所述显示区包括呈多行多列排列的多个子像素，与多列子像素一一对应设置的多条数据线，与多行子像素一一对应设置的多条扫描线，以及与所述多条扫描线一一对应连接的多条栅极扇出走线；所述数据线和所述栅极扇出走线分别沿列方向延伸至所述非显示区，且每两列子像素构成子像素组，所述子像素组中的两列子像素之间设有两条所述数据线，任意相邻的两条所述栅极扇出走线之间间隔至少一个子像素组；所述子像素组中的两条数据线之间具有间隙，所述栅极扇出走线的宽度等于所述子像素组中两条数据线的宽度与所述间隙的宽度之和。
进一步地，所述栅极扇出走线与所述数据线同层设置，所述栅极扇出走线与所述扫描线不同层设置。
进一步地，所述栅极扇出走线与所述扫描线之间设有栅极绝缘层，所述栅极绝缘层中设有过孔，所述栅极扇出走线通过所述过孔与对应的扫描线电性连接。
进一步地，所述显示面板还包括遮光层；所述遮光层与所述数据线、所述扫描线和所述栅极扇出走线的位置对应设置。
进一步地，所述遮光层包括第一遮光图案和第二遮光图案；所述第一遮光图案在所述栅极扇出走线所在膜层上的正投影完全覆盖所述栅极扇出走线，所述第二遮光图案在所述数据线所在膜层上的正投影完全覆盖所述子像素组中的两条数据线。
进一步地，所述第一遮光图案在行方向上的长度与所述第二遮光图案在行方向上的长度相同。
进一步地，所述非显示区包括栅极驱动电路和所述源极驱动电路；所述栅极驱动电路与所述栅极扇出走线电性连接，所述源极驱动电路与所述数据线电性连接。
进一步地，所述栅极驱动电路包括多级栅极驱动单元；所述多级栅极驱动单元与所述多条栅极扇出走线一一对应电性连接。
进一步地，所述源极驱动电路位于所述栅极驱动电路背离所述显示区的一侧，所述多级栅极驱动单元并列且间隔设置；所述数据线经由所述多级栅极驱动单元之间的间隙延伸至所述源极驱动电路，并与所述源极驱动电路电性连接。
本申请实施例还提供一种显示面板，包括显示区和位于显示区一侧的非显示区；所述显示区包括呈多行多列排列的多个子像素，与多列子像素一一对应设置的多条数据线，与多行子像素一一对应设置的多条扫描线，以及与所述多条扫描线一一对应连接的多条栅极扇出走线；所述数据线和所述栅极扇出走线分别沿列方向延伸至所述非显示区，且每两列子像素构成子像素组，所述子像素组中的两列子像素之间设有两条所述数据线，任意相邻的两条所述栅极扇出走线之间间隔至少一个子像素组；所述栅极扇出走线的宽度不小于所述子像素组中两条数据线的宽度之和。
进一步地，所述栅极扇出走线与所述数据线同层设置，所述栅极扇出走线与所述扫描线不同层设置。
进一步地，所述栅极扇出走线与所述扫描线之间设有栅极绝缘层，所述栅极绝缘层中设有过孔，所述栅极扇出走线通过所述过孔与对应的扫描线电性连接。
进一步地，所述显示面板还包括遮光层；所述遮光层与所述数据线、所述扫描线和所述栅极扇出走线的位置对应设置。
进一步地，所述遮光层包括第一遮光图案和第二遮光图案；所述第一遮光图案在所述栅极扇出走线所在膜层上的正投影完全覆盖所述栅极扇出走线，所述第二遮光图案在所述数据线所在膜层上的正投影完全覆盖所述子像素组中的两条数据线。
进一步地，所述第一遮光图案在行方向上的长度与所述第二遮光图案在行方向上的长度相同。
进一步地，所述非显示区包括栅极驱动电路和源极驱动电路；所述栅极驱动电路与所述栅极扇出走线电性连接，所述源极驱动电路与所述数据线电性连接。
进一步地，所述栅极驱动电路包括多级栅极驱动单元；所述多级栅极驱动单元与所述多条栅极扇出走线一一对应电性连接。
进一步地，所述源极驱动电路位于所述栅极驱动电路背离所述显示区的一侧，所述多级栅极驱动单元并列且间隔设置；所述数据线经由所述多级栅极驱动单元之间的间隙延伸至所述源极驱动电路，并与所述源极驱动电路电性连接。
 有益效果
本申请的有益效果为：通过设置沿列方向延伸至非显示区的数据线和栅极扇出走线，使每两列子像素构成一组子像素，每组子像素中的两列子像素之间设有两条数据线，任意相邻的两条栅极扇出走线之间间隔至少一组子像素，并使栅极扇出走线的宽度不小于一组子像素中两条数据线的宽度之和，以在实现窄边框显示面板的同时，降低栅极扇出走线上的信号延迟，提高子像素充电率及防止错充。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的显示面板的结构示意图；
图2为本申请实施例提供的显示面板中扫描线、数据线和栅极扇出走线的位置关系示意图；
图3为本申请实施例提供的显示面板中一行子像素与遮光层的位置关系示意图。
 本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和实施例对本申请作进一步说明。
如图1所示，本申请实施例提供了一种显示面板包括显示区10和非显示区20，非显示区20位于显示区10的一侧，以保证显示面板三边极致窄边框或无边框设计。
所述显示区10包括呈多行多列排列的多个子像素1，与多列子像素1一一对应设置的多条数据线2，与多行子像素1一一对应设置的多条扫描线3，以及与所述多条扫描线3一一对应连接的多条栅极扇出走线4。其中，多条数据线2沿列方向A延伸至非显示区20，即显示区10与非显示区20沿列方向设置。多条扫描线3沿行方向B延伸，且多条数据线2与多条扫描线3不同层设置，使得多条数据线2与多条扫描线3绝缘交叉限定出多个子像素1。
多条扫描线3与多行子像素1一一对应设置，即扫描线3的条数与子像素1的行数相同，以在扫描每行子像素1时，通过该行子像素1对应的扫描线向该行子像素1输入扫描信号。多条数据线2与多列子像素1一一对应设置，即数据线2的条数与子像素1的列数相同，以在每行子像素1输入扫描信号期间，通过每条数据线2依次向该行子像素1中相应列子像素1输入数据信号，依次给该行子像素1中的每个子像素1充电。
多条栅极扇出走线4沿列方向A延伸至非显示区20，即多条栅极扇出走线4与多条数据线2同层且平行设置。栅极扇出走线4的条数与扫描线3的条数相同，且多条栅极扇出走线4与多条扫描线3一一对应电性连接。在扫描每行子像素1时，扫描信号通过相应的栅极扇出走线4，传输至对应的扫描线3，再传输至相应行子像素1中。
如图1所示，在多个子像素1中，任意相邻两列子像素1之间具有间隙，每两列子像素1可构成一组子像素，即子像素组30。在每组子像素，即每个子像素组30中，两列子像素1之间的间隙处设有两条数据线2，且该两列子像素1与该两条数据线2一一对应设置，即该两条数据线2分别对应向该两列子像素1输入数据信号。
任意相邻的两条栅极扇出走线4之间间隔至少一组子像素，即间隔至少一个子像素组30。如图1所示，任意相邻的两条栅极扇出走线4之间间隔一个子像素组30，即栅极扇出走线4位于相邻两个子像素组30之间的间隙处，而数据线2位于每个子像素组30中的两列子像素1之间的间隙处，使得栅极扇出走线4与数据线2位于不同的间隙处，即栅极扇出走线4与数据线2之间至少间隔一列子像素2，从而避免栅极扇出走线4与数据线2距离过近相互耦合（couple）导致显示不均（mura）。
其中，栅极扇出走线4的宽度不小于一组子像素中两条数据线2的宽度之和，且栅极扇出走线4的宽度小于相邻两列子像素之间的间隙宽度，即相邻两列子像素的间距。栅极扇出走线4的宽度是指栅极扇出走线4在行方向B上的长度，两条数据线2的宽度之和是指两条数据线2在行方向B上的长度之和。本实施例通过增加栅极扇出走线4的宽度，使其至少为数据线2宽度的两倍，有效降低其负载大小，提高其电容大小，从而降低扫描信号在栅极扇出走线4上的延迟，以在扫描每行子像素1时，降低扫描信号由低电平变为高电平（rising time）以及由高电平变为低电平（falling time）的时延，保证该行子像素1中每个子像素的充电时间，提高子像素1的充电率，防止错充。
在一个实施方式中，一组子像素中的两条数据线2之间具有间隙，栅极扇出走线4的宽度等于所述一组子像素中两条数据线2的宽度与该间隙的宽度之和。在实际应用中，栅极扇出走线4上的时延由现有技术的1.01us降低至0.87us，有效改善扫描信号的时延。
进一步地，数据线2与栅极扇出走线4同层设置，扫描线3与栅极扇出走线4不同层设置。如图2所示，显示面板包括衬底40、位于衬底40上的第一金属层50，位于衬底40和第一金属层50上的栅极绝缘层60，以及位于栅极绝缘层60上的第二金属层70。其中，第一金属层50包括扫描线3，第二金属层70包括数据线2和栅极扇出走线4。栅极绝缘层60在每个栅极扇出走线4与其对应的扫描线3的连接处设置过孔5，以使每个栅极扇出走线4通过过孔5与其对应的扫描线3连接。
另外，每个子像素1可以包括一个薄膜晶体管6。第一金属层50还包括薄膜晶体管6的栅极，即栅极与扫描线3同层设置，且每个子像素1的薄膜晶体管6的栅极与该子像素1所在行对应的扫描线3电性连接，使扫描线3通过薄膜晶体管6的栅极向该子像素1输入扫描信号。第二金属层70还包括薄膜晶体管6的源极和漏极，即源极和漏极与数据线2、栅极扇出走线4同层设置，且每个子像素1的薄膜晶体管6的源极与该子像素1所在列对应的数据线2电性连接，使数据线2通过薄膜晶体管6的源极向该子像素1输入数据信号。
第一金属层50和第二金属层70的材料可以为导电材料，如铜、铝、银等金属或金属合金。多个子像素1可以包括红色子像素R、绿色子像素G、蓝色子像素B等，在此不做具体限定。相邻两行子像素1之间具有间隙，每行子像素1对应的扫描线3位于该行子像素任意一侧的间隙中，以保证每行子像素1能够与其对应的扫描线3电性连接。
如图1所示，非显示区20包括栅极驱动电路7和所述源极驱动电路8，即栅极驱动电路7和源极驱动电路8位于显示区10的同一侧。栅极驱动电路7与多条栅极扇出走线4电性连接，从而使栅极驱动电路7通过多条栅极扇出走线4与多条扫描线3电性连接，在扫描每行子像素1时，栅极驱动电路7通过对应的栅极扇出走线4、对应的扫描线3向该行子像素1输出扫描信号。源极驱动电路8与多条数据线2电性连接，以在每行子像素1输入扫描信号期间，源极驱动电路8通过多条数据线2依次向该行子像素1中的每个子像素1输出数据信号。
具体地，如图1所示，栅极驱动电路7包括多级栅极驱动单元71，多级栅极驱动单元71与多条栅极扇出走线4一一对应电性连接。多级栅极驱动单元71并列且间隔设置，即多级栅极驱动单元71沿行方向B依次排列，且任意相邻的两级栅极驱动单元71之间具有间隙。一级栅极驱动单元71与相邻两列子像素1的位置相对应，即一级栅极驱动单元71在行方向B上的长度与相邻两列子像素1在行方向B上的长度相同，且相邻两级栅极驱动单元71之间的间隙与子像素组30中两列子像素之间的间隙位置相对应。
源极驱动电路8位于栅极驱动电路7背离显示区10的一侧，即栅极驱动电路7位于源极驱动电路8和显示区10之间。子像素组30中的两条数据线2延伸至非显示区20，经由对应的两级栅极驱动单元71之间的间隙延伸至源极驱动电路8，并与源极驱动电路8电性连接。
进一步地，如图3所示，显示面板还包括遮光层9，且遮光层9位于第二金属层70背离衬底40的一侧，遮光层9与多条数据线2、多条扫描线3和多条栅极扇出走线4的位置相对应，即遮光层9在衬底40上的正投影覆盖多条数据线2、多条扫描线3和多条栅极扇出走线4在衬底40上的正投影，以对多条数据线2、多条扫描线3和多条栅极扇出走线4进行遮挡。其中，遮挡层9可以为黑矩阵。
遮光层9包括与多条栅极扇出走线4一一对应设置的多个第一遮光图案91,与多个子像素组30中的两条数据线2一一对应设置的多个第二遮光图案92，以及与多条扫描线3一一对应设置的多个第三遮光图案（图中未示出）。每个第一遮光图案91在衬底40上的正投影覆盖其对应的栅极扇出走线4在衬底40上的正投影，每个第二遮光图案92在衬底40上的正投影覆盖其对应的子像素组30中的两条数据线2在衬底40上的正投影，每个第三遮光图案在衬底40上的正投影覆盖其对应的扫描线3在衬底40上的正投影。
每个第一遮光图案91在行方向B上的长度与第二遮光图案92在行方向B上的长度相同，且第一遮光图案91在行方向B上的长度与栅极扇出走线4的宽度相同，第二遮光图案92在行方向B上的长度与子像素组30中两条数据线2的宽度及该两条数据线2之间的间隙宽度之和相同，从而保证相邻子像素1之间的遮挡面积相同，避免显示上出现粗细差异，从而优化显示效果。
综上，本申请实施例能够通过设置沿列方向延伸至非显示区的数据线和栅极扇出走线，使每两列子像素构成一组子像素，每组子像素中的两列子像素之间设有两条数据线，任意相邻的两条栅极扇出走线之间间隔至少一组子像素，并使栅极扇出走线的宽度不小于一组子像素中两条数据线的宽度之和，以在实现窄边框显示面板的同时，降低栅极扇出走线上的信号延迟，提高子像素充电率及防止错充。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种显示面板，包括显示区和位于显示区一侧的非显示区；所述显示区包括呈多行多列排列的多个子像素，与多列子像素一一对应设置的多条数据线，与多行子像素一一对应设置的多条扫描线，以及与所述多条扫描线一一对应连接的多条栅极扇出走线；
    所述数据线和所述栅极扇出走线分别沿列方向延伸至所述非显示区，且每两列子像素构成子像素组，所述子像素组中的两列子像素之间设有两条所述数据线，任意相邻的两条所述栅极扇出走线之间间隔至少一个子像素组；
    所述子像素组中的两条数据线之间具有间隙，所述栅极扇出走线的宽度等于所述子像素组中两条数据线的宽度与所述间隙的宽度之和。
  2. 如权利要求1所述的显示面板，其中，所述栅极扇出走线与所述数据线同层设置，所述栅极扇出走线与所述扫描线不同层设置。
  3. 如权利要求1所述的显示面板，其中，所述栅极扇出走线与所述扫描线之间设有栅极绝缘层，所述栅极绝缘层中设有过孔，所述栅极扇出走线通过所述过孔与对应的扫描线电性连接。
  4. 如权利要求1所述的显示面板，其中，所述显示面板还包括遮光层；
    所述遮光层与所述数据线、所述扫描线和所述栅极扇出走线的位置对应设置。
  5. 如权利要求4所述的显示面板，其中，所述遮光层包括第一遮光图案和第二遮光图案；
    所述第一遮光图案在所述栅极扇出走线所在膜层上的正投影完全覆盖所述栅极扇出走线，所述第二遮光图案在所述数据线所在膜层上的正投影完全覆盖所述子像素组中的两条数据线。
  6. 如权利要求5所述的显示面板，其中，所述第一遮光图案在行方向上的长度与所述第二遮光图案在行方向上的长度相同。
  7. 如权利要求1所述的显示面板，其中，所述非显示区包括栅极驱动电路和源极驱动电路；
    所述栅极驱动电路与所述栅极扇出走线电性连接，所述源极驱动电路与所述数据线电性连接。
  8. 如权利要求7所述的显示面板，其中，所述栅极驱动电路包括多级栅极驱动单元；
    所述多级栅极驱动单元与所述多条栅极扇出走线一一对应电性连接。
  9. 如权利要求8所述的显示面板，其中，所述源极驱动电路位于所述栅极驱动电路背离所述显示区的一侧，所述多级栅极驱动单元并列且间隔设置；
    所述数据线经由所述多级栅极驱动单元之间的间隙延伸至所述源极驱动电路，并与所述源极驱动电路电性连接。
  10. 一种显示面板，包括显示区和位于显示区一侧的非显示区；所述显示区包括呈多行多列排列的多个子像素，与多列子像素一一对应设置的多条数据线，与多行子像素一一对应设置的多条扫描线，以及与所述多条扫描线一一对应连接的多条栅极扇出走线；
    所述数据线和所述栅极扇出走线分别沿列方向延伸至所述非显示区，且每两列子像素构成子像素组，所述子像素组中的两列子像素之间设有两条所述数据线，任意相邻的两条所述栅极扇出走线之间间隔至少一个子像素组；
    所述栅极扇出走线的宽度不小于所述子像素组中两条数据线的宽度之和。
  11. 如权利要求10所述的显示面板，其中，所述栅极扇出走线与所述数据线同层设置，所述栅极扇出走线与所述扫描线不同层设置。
  12. 如权利要求10所述的显示面板，其中，所述栅极扇出走线与所述扫描线之间设有栅极绝缘层，所述栅极绝缘层中设有过孔，所述栅极扇出走线通过所述过孔与对应的扫描线电性连接。
  13. 如权利要求10所述的显示面板，其中，所述显示面板还包括遮光层；
    所述遮光层与所述数据线、所述扫描线和所述栅极扇出走线的位置对应设置。
  14. 如权利要求13所述的显示面板，其中，所述遮光层包括第一遮光图案和第二遮光图案；
    所述第一遮光图案在所述栅极扇出走线所在膜层上的正投影完全覆盖所述栅极扇出走线，所述第二遮光图案在所述数据线所在膜层上的正投影完全覆盖所述子像素组中的两条数据线。
  15. 如权利要求14所述的显示面板，其中，所述第一遮光图案在行方向上的长度与所述第二遮光图案在行方向上的长度相同。
  16. 如权利要求10所述的显示面板，其中，所述非显示区包括栅极驱动电路和源极驱动电路；
    所述栅极驱动电路与所述栅极扇出走线电性连接，所述源极驱动电路与所述数据线电性连接。
  17. 如权利要求16所述的显示面板，其中，所述栅极驱动电路包括多级栅极驱动单元；
    所述多级栅极驱动单元与所述多条栅极扇出走线一一对应电性连接。
  18. 如权利要求17所述的显示面板，其中，所述源极驱动电路位于所述栅极驱动电路背离所述显示区的一侧，所述多级栅极驱动单元并列且间隔设置；
    所述数据线经由所述多级栅极驱动单元之间的间隙延伸至所述源极驱动电路，并与所述源极驱动电路电性连接。
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