WO2022011815A1 - 一种无边框显示面板、显示装置及拼接型显示装置 - Google Patents

一种无边框显示面板、显示装置及拼接型显示装置 Download PDF

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Publication number
WO2022011815A1
WO2022011815A1 PCT/CN2020/114641 CN2020114641W WO2022011815A1 WO 2022011815 A1 WO2022011815 A1 WO 2022011815A1 CN 2020114641 W CN2020114641 W CN 2020114641W WO 2022011815 A1 WO2022011815 A1 WO 2022011815A1
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Prior art keywords
sub
pixels
display area
light
thin film
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Application number
PCT/CN2020/114641
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English (en)
French (fr)
Inventor
郑武
靳增建
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/051,246 priority Critical patent/US11942461B2/en
Priority to EP20880335.3A priority patent/EP4184584A4/en
Priority to EA202190977A priority patent/EA202190977A1/ru
Publication of WO2022011815A1 publication Critical patent/WO2022011815A1/zh
Priority to US18/421,244 priority patent/US20240194658A1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels

Definitions

  • the present application relates to the field of display technology, and in particular, to a borderless display panel, a display device and a mosaic display device.
  • each small screen has an outer frame, and the outer frame cannot be displayed, that is, the screen ratio is too low, so there will inevitably be traces of splicing between the panels. It will cause visual imperfection and affect the display effect. Therefore, it is necessary to improve this defect.
  • the present application provides a borderless display panel, which is used to solve the technical problems of the display panel in the prior art that the outer frame of the display panel cannot be displayed, resulting in a too low screen ratio, and splicing marks will exist when splicing a large-size panel, which affects the display effect. .
  • An embodiment of the present application provides a borderless display panel, which is divided into a first display area, a second display area surrounding the first display area, and a third display area surrounding the second display area. Both the first display area and the second display area are provided with a plurality of sub-pixel driving thin film transistors.
  • the distribution density of the sub-pixel driving thin film transistors in the first display area is equal to the distribution density of the sub-pixel driving thin film transistors in the second display area.
  • Each of the first display area, the second display area, and the third display area is provided with a plurality of light-emitting sub-pixels.
  • the distribution density of the light-emitting sub-pixels in the first display area is greater than the distribution density of the light-emitting sub-pixels in the second display area.
  • no sub-pixel driving thin film transistor is arranged in the third display area.
  • Parts of the plurality of sub-pixel driving thin film transistors in the second display area are respectively connected to the plurality of light-emitting sub-pixels in the second display area.
  • Another part of the plurality of sub-pixel driving thin film transistors in the second display area is respectively connected to the plurality of light-emitting sub-pixels in the third display area through a plurality of metal wires.
  • the second display area is divided into a first straight area and a first corner area.
  • the third display area is divided into a second straight bar area and a second corner area.
  • the plurality of light-emitting sub-pixels in the second straight line area are respectively connected to the plurality of sub-pixel driving thin film transistors in the first straight line area through a plurality of the metal wires.
  • the plurality of light-emitting sub-pixels in the second corner area are respectively connected to the plurality of sub-pixel driving thin film transistors in the first corner area through a plurality of the metal wires.
  • metal traces connecting the light-emitting sub-pixels in the second linear region and the sub-pixel driving thin film transistors in the first linear region are in a horizontal direction or vertical orientation.
  • metal traces connecting the light-emitting sub-pixels in the second corner region and the sub-pixel driving thin film transistors in the first corner region are inclined in an oblique direction , the inclined direction forms a first included angle with the horizontal direction or the vertical direction.
  • the first included angle is an acute angle.
  • the number of the plurality of light-emitting sub-pixels in the second display area and the number of the plurality of light-emitting sub-pixels in the third display area The sum is equal to the number of the plurality of sub-pixel driving thin film transistors in the second display area.
  • the light-emitting sub-pixels include a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels, and consists of one of the red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels. Two of the green sub-pixels and one of the blue sub-pixels constitute a pixel unit.
  • the arrangement of the light-emitting sub-pixels is a matrix arrangement.
  • the pixel unit includes a first pixel unit and a second pixel unit.
  • the first pixel unit two of the green sub-pixels are located on one side, one of the red sub-pixels and one of the blue sub-pixels are located on the other side, and the red sub-pixel is located on the blue above the sub-pixels.
  • the second pixel unit two of the green sub-pixels are located on one side, one of the red sub-pixels and one of the blue sub-pixels are located on the other side, and the blue sub-pixel is located on the red above the sub-pixels.
  • the green sub-pixels are disposed corresponding to the middle and lower portions of the red sub-pixels and the blue sub-pixels, respectively.
  • the pixel units in any row are arranged cyclically in the order of the first pixel unit and the second pixel unit.
  • the light-emitting areas of the green sub-pixels are respectively smaller than the light-emitting areas of the red sub-pixels and the blue sub-pixels.
  • the shape of the light-emitting sub-pixels is a circle, a triangle, or a rectangle.
  • An embodiment of the present application provides a display device, including: a back frame, and a borderless display panel disposed on the back frame.
  • the borderless display panel is divided into a first display area, a second display area surrounding the first display area, and a third display area surrounding the second display area.
  • Both the first display area and the second display area are provided with a plurality of sub-pixel driving thin film transistors.
  • the distribution density of the sub-pixel driving thin film transistors in the first display area is equal to the distribution density of the sub-pixel driving thin film transistors in the second display area.
  • Each of the first display area, the second display area, and the third display area is provided with a plurality of light-emitting sub-pixels.
  • the distribution density of the light-emitting sub-pixels in the first display area is greater than the distribution density of the light-emitting sub-pixels in the second display area.
  • no sub-pixel driving thin film transistor is arranged in the third display area. Parts of the plurality of sub-pixel driving thin film transistors in the second display area are respectively connected to the plurality of light-emitting sub-pixels in the second display area. Another part of the plurality of sub-pixel driving thin film transistors in the second display area is respectively connected to the plurality of light-emitting sub-pixels in the third display area through a plurality of metal wires.
  • the second display area is divided into a first line area and a first corner area.
  • the third display area is divided into a second straight bar area and a second corner area.
  • the plurality of light-emitting sub-pixels in the second straight line area are respectively connected to the plurality of sub-pixel driving thin film transistors in the first straight line area through a plurality of the metal wires.
  • the plurality of light-emitting sub-pixels in the second corner area are respectively connected to the plurality of sub-pixel driving thin film transistors in the first corner area through a plurality of the metal wires.
  • the sum of the number of the plurality of light-emitting sub-pixels in the second display area and the number of the plurality of light-emitting sub-pixels in the third display area which is equal to the number of the plurality of sub-pixel driving thin film transistors in the second display area.
  • the light-emitting sub-pixel includes a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels, and consists of one red sub-pixel, two The green sub-pixel and one of the blue sub-pixels form a pixel unit.
  • Embodiments of the present application provide a mosaic-type display device, including: a back frame and a plurality of borderless display panels.
  • a plurality of the borderless display panels are arranged on the back frame and spliced to form a display surface.
  • each of the borderless display panels is divided into a first display area, a second display area surrounding the first display area, and a third display area surrounding the second display area.
  • Both the first display area and the second display area are provided with a plurality of sub-pixel driving thin film transistors.
  • the distribution density of the sub-pixel driving thin film transistors in the first display area is equal to the distribution density of the sub-pixel driving thin film transistors in the second display area.
  • Each of the first display area, the second display area, and the third display area is provided with a plurality of light-emitting sub-pixels.
  • the distribution density of the light-emitting sub-pixels in the first display area is greater than the distribution density of the light-emitting sub-pixels in the second display area.
  • no sub-pixel driving thin film transistor is arranged in the third display area.
  • Parts of the plurality of sub-pixel driving thin film transistors in the second display area are respectively connected to the plurality of light-emitting sub-pixels in the second display area.
  • Another part of the plurality of sub-pixel driving thin film transistors in the second display area is respectively connected to the plurality of light-emitting sub-pixels in the third display area through a plurality of metal wires.
  • the second display area is divided into a first straight area and a first corner area.
  • the third display area is divided into a second straight bar area and a second corner area.
  • the plurality of light-emitting sub-pixels in the second straight line area are respectively connected to the plurality of sub-pixel driving thin film transistors in the first straight line area through a plurality of the metal wires.
  • the plurality of light-emitting sub-pixels in the second corner area are respectively connected to the plurality of sub-pixel driving thin film transistors in the first corner area through a plurality of the metal wires.
  • the number of the plurality of light-emitting sub-pixels in the second display area is the same as the number of the light-emitting sub-pixels in the third display area
  • the sum of the number of the plurality of the light-emitting sub-pixels is equal to the number of the sub-pixel driving thin film transistors in the second display area.
  • the light-emitting sub-pixels include a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels, and consists of one of the red sub-pixels, the plurality of green sub-pixels, and the plurality of blue sub-pixels. Two of the green sub-pixels and one of the blue sub-pixels constitute a pixel unit.
  • a borderless display panel provided by the present application, by dividing the display area of the panel into a first display area, a second display area surrounding the first display area, and a third display area surrounding the second display area, the first display area
  • the distribution densities of the sub-pixel driving thin film transistors in the display area and the second display area are equal, and the distribution density of the light-emitting sub-pixels in the first display area is greater than the distribution density of the light-emitting sub-pixels in the second display area
  • no sub-pixel driving thin film transistors are arranged in the third display area, a part of the sub-pixel driving thin film transistors in the second display area are connected to the light-emitting sub-pixels in the second display area, and the second Another part of the sub-pixel driving thin film transistors in the display area is connected to the light-emitting sub-pixels in the third display area, so that borderless display can be realized, the screen ratio can be increased, the application range of the product can be increased, and the display caused by splic
  • FIG. 1 is a schematic diagram of a basic structure of a borderless display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a basic structure of a borderless display panel provided by another embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional view of the second display area and the third display area of the borderless display panel provided by the present application.
  • FIG. 4 is a schematic diagram of sub-pixel distribution of a borderless display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a basic structure of a display device provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a basic structure of a mosaic display device provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a basic structure of a borderless display panel provided by an embodiment of the present application
  • the borderless display panel is divided into a first display area 101 and a second display area 102 surrounding the first display area 101 .
  • a third display area 103 surrounding the second display area 102 a plurality of sub-pixel driving thin film transistors (not shown) are arranged in the first display area 101 and the second display area 102, so The distribution density of the sub-pixel driving thin film transistors in the first display area 101 is equal to the distribution density of the sub-pixel driving thin film transistors in the second display area 102 .
  • FIG. 1 is a schematic diagram of the sub-pixel driving circuit 104 in the first display area 101 and the sub-pixel driving circuit 105 in the second display area 102, wherein the sub-pixel The driving circuit 104 includes at least one of the sub-pixel driving thin film transistors, and the sub-pixel driving circuit 105 also includes at least one of the sub-pixel driving thin film transistors. Since the details of the sub-pixel driving circuits 104 and 105 are not the focus of the present application, detailed structural diagrams are not depicted or described in detail. As long as the sub-pixel driving circuits 104 and 105 can be used to drive the light-emitting sub-pixels, the present application does not limit the circuit details thereof.
  • sub-pixel driving circuits 104 and 105 are usually located below the light-emitting sub-pixels 106 and 107. In order to facilitate the display of their relative positions, both FIG. 1 and FIG. The sub-pixel drive circuits 104 and 105 and the light-emitting sub-pixels 106 and 107 are partially overlapped.
  • the first display area 101 , the second display area 102 , and the third display area 103 are all provided with a plurality of light-emitting sub-pixels 106 , 107 , and 108 .
  • the distribution density of the light-emitting sub-pixels 106 in the display area 101 is greater than the distribution density of the light-emitting sub-pixels 107 in the second display area 102 ; please refer to FIG.
  • the third display area 103 is not provided with Sub-pixel driving thin film transistors
  • a part of the plurality of sub-pixel driving thin film transistors in the second display area 102 are respectively connected with a plurality of the sub-pixel driving thin film transistors in the second display area 102
  • the light-emitting sub-pixels 107 are connected to each other, and the other parts of the plurality of sub-pixel driving thin film transistors (located in the sub-pixel driving circuit 2042 ) in the second display area 102 are respectively connected to the first sub-pixels through a plurality of metal wires 203 and 206 .
  • the plurality of light-emitting sub-pixels 202 and 205 in the three display areas 103 are connected to each other.
  • the distribution density of the sub-pixel driving thin film transistors (located in the sub-pixel driving circuit 204 ) in the second display area 102 is set to be the same as that of the sub-pixel driving thin film transistors in the first display area 101 .
  • the distribution density of the pixel driving thin film transistors (located in the sub-pixel driving circuit 104 ) is equal, and the distribution density of the light-emitting sub-pixels 107 in the second display area 102 is set to be smaller than that of the light-emitting sub-pixels in the first display area 101
  • the distribution density of 106 that is, the light-emitting sub-pixels 107 in the second display area 102 are only connected to a part of the sub-pixel driving thin film transistors (located in the sub-pixel driving circuit 2041) in the second display area 102, and at the same time, No sub-pixel driving thin film transistors are arranged in the third display area 103 , and the light-emitting sub-pixels 202 and 205 in the third display area 103 are connected to other light-emitting sub-pixels 202 and 205 in the second display area 102 through metal wires 203 and 206 .
  • a part of the sub-pixel driving thin film transistors (located in the sub-pixel driving
  • the sum of the number of the plurality of light-emitting sub-pixels 107 in the second display area 102 and the number of the plurality of light-emitting sub-pixels 202 and 205 in the third display area 103 equal to the number of the plurality of sub-pixel driving thin film transistors (located in the sub-pixel driving circuit 204 ) in the second display area 102 , that is, the plurality of light-emitting sub-pixels 107 in the second display area 102
  • a plurality of the light-emitting sub-pixels 202 and 205 in the third display area 103 and a plurality of the sub-pixel driving thin film transistors (located in the sub-pixel driving circuit 204 ) in the second display area 102 One-to-one correspondence, each sub-pixel driving thin film transistor corresponds to one light-emitting sub-pixel.
  • the distribution density of the light-emitting sub-pixels in the second display area 102 is reduced, and a part of the light-emitting sub-pixels is expanded into the third display area 103 (corresponding to the outer frame area of the prior art), so that the entire panel area can be realized. All have display function, and avoid splicing marks when splicing into large-size panels.
  • the borderless display panel further includes a source driving circuit 109, and the source driving circuit 109 is used to control the voltage (gray-scale value) of the light-emitting sub-pixels, so as to display corresponding brightness.
  • the source driving circuit 109 is usually located in the third display area 103 (corresponding to the outer frame area in the prior art), it is inconvenient to arrange the sub-pixel driving circuit in the third display area 103, so that the outer frame area in the prior art cannot be displayed. Moreover, the extent to which the space of the outer border area can be reduced is limited.
  • the present application extends a part of the light-emitting sub-pixels into the third display area 103 (corresponding to the outer frame area of the prior art), and the light-emitting sub-pixels 202 and 205 in the third display area 103 are routed through metal
  • the lines 203 and 206 are connected to another part of the sub-pixel driving thin film transistors (located in the sub-pixel driving circuit 2042) in the second display area 102, so that borderless display can be realized without affecting the design of gate lines and driving circuits .
  • the light-emitting sub-pixels include a plurality of red sub-pixels 110, a plurality of green sub-pixels 111, and a plurality of blue sub-pixels 112, and one of the red sub-pixels 110, Two of the green sub-pixels 111 and one of the blue sub-pixels 112 form a pixel unit.
  • the arrangement of the light-emitting sub-pixels is a matrix arrangement, and the pixel unit includes a first pixel unit 113 and a second pixel unit 114 .
  • the green sub-pixels 111 are located on one side, one of the red sub-pixels 110 and one of the blue sub-pixels 112 are located on the other side, and the red sub-pixel 110 are located above the blue sub-pixels 112; in the second pixel unit 114, two green sub-pixels 111 are located on one side, and one of the red sub-pixels 110 and one of the blue sub-pixels 112 is located on one side On the other side, the blue sub-pixel 112 is located above the red sub-pixel 110 .
  • the pixel units in any row are cyclically arranged in the order of the first pixel unit 113 and the second pixel unit 114 .
  • the shape of the light-emitting sub-pixel is a circle, a triangle, or a rectangle.
  • the red sub-pixel 110 and the blue sub-pixel 112 are both rectangular in shape
  • the green sub-pixel 111 is circular in shape.
  • the light-emitting areas of the green sub-pixels 111 are smaller than the light-emitting areas of the red sub-pixels 110 and the blue sub-pixels 112 , respectively. It should be noted that since the red sub-pixels 110 and the blue sub-pixels 112 have fast brightness attenuation and short lifespans, the red sub-pixels 110 and the blue sub-pixels 112 are provided with larger areas. , so that the brightness attenuation and lifespan of the three pixels are uniform.
  • the green sub-pixels 111 are disposed corresponding to the middle and lower parts of the red sub-pixels 110 and the blue sub-pixels 112 respectively. Specifically, taking the second pixel unit 114 as an example, that is, one of the green sub-pixels 111 corresponds to the middle position of the red sub-pixel 110 and the blue sub-pixel 112 , and the other green sub-pixel 111 corresponds to It is arranged below the red sub-pixel 110 .
  • the green sub-pixels 111 are arranged alternately with the red sub-pixels 110 and the blue sub-pixels 112 , and the green sub-pixels 111 correspond to the red sub-pixels 110 and the blue sub-pixels 112 between settings.
  • FIG. 2 a schematic diagram of the basic structure of a borderless display panel provided by another embodiment of the present application, the borderless display panel is divided into a first display area 101 and a second display area surrounding the first display area 101 102, and a third display area 103 surrounding the second display area 102; the plurality of light-emitting sub-pixels 106 in the first display area 101 are connected to the first display area 101 through a plurality of metal wires 201 respectively.
  • the sub-pixel driving thin film transistors in the plurality of sub-pixel driving circuits 104 are connected to each other; the second display area 102 is divided into a first straight area 1021 and a first corner area 1022, and the third display area 103 is divided into a second The straight area 1031 and the second corner area 1032; wherein, the plurality of light-emitting sub-pixels 202 in the second straight area 1031 are connected to the first straight area through a plurality of the metal wires 203 respectively.
  • the sub-pixel driving thin film transistors in the sub-pixel driving circuits 204 in the plurality of sub-pixel driving circuits 204 in 1021 are connected to each other, and the light-emitting sub-pixels 205 in the second corner area 1032 are respectively connected with the plurality of the metal wires 206 through the plurality of the metal wires 206.
  • the sub-pixel driving thin film transistors in the plurality of sub-pixel driving circuits 207 in the first corner region 1022 are connected to each other.
  • the metal traces 203 connecting the light-emitting sub-pixels 202 in the second straight region 1031 and the sub-pixel driving thin film transistors in the first straight region 1021 are substantially horizontal (two left and right). side) or vertical direction (upper and lower sides), FIG. 2 does not draw the metal traces 203 in a horizontal direction for the convenience of description.
  • the metal traces 206 connecting the light-emitting sub-pixels 205 in the second corner region 1032 and the sub-pixel driving thin film transistors in the first corner region 1022 are inclined in an inclined direction, and the inclined direction is in a horizontal or vertical direction.
  • the first included angle a the first included angle a is an acute angle. Specifically, the first included angle a is greater than 0 degrees and less than or equal to 45 degrees.
  • the second display area 102 is divided into a first straight area 1021 and a first corner area 1022
  • the third display area 103 is divided into a second straight area 1031 and a second corner area 1032, then connect the light-emitting sub-pixel 202 in the second straight area 1031 with the sub-pixel driving thin film transistor in the first straight area 1021, and connect the light-emitting sub-pixel 205 in the second corner area 1032 with the first corner
  • the sub-pixel driving thin film transistors in the area 1022 are connected to each other, that is, the light-emitting sub-pixels in the first straight area 1021 are extended horizontally or vertically, and the light-emitting sub-pixels in the first corner area 1022 are arranged at the first included angle a.
  • the oblique expansion can make all the light-emitting sub-pixels evenly arranged and improve the display quality.
  • the borderless display panel further includes a source driving circuit 109 and a GOA driving circuit 208 , and the GOA driving circuit 208 is used to control the turning on or off of the light-emitting sub-pixels of a certain row , the GOA driving circuit 208 includes at least one GOA thin film transistor (corresponding to the GOA thin film transistor 312 in FIG. 3 ). Since the GOA driving circuit 208 is usually located in the third display area 103 (corresponding to the outer frame area in the prior art), it is inconvenient to set the sub-pixel driving circuit in the third display area 103, so that the outer frame area in the prior art cannot be displayed. Moreover, the extent to which the space of the outer border area can be reduced is limited.
  • the present application extends a part of the light-emitting sub-pixels into the third display area 103 (corresponding to the outer frame area of the prior art), and connects the light-emitting sub-pixels in the third display area 103 with all the light-emitting sub-pixels through metal wirings.
  • Another part of the sub-pixel driving thin film transistors in the second display area 102 are connected to each other, so that borderless display can be realized without affecting the design of gate lines and driving circuits.
  • the frameless display panel includes a buffer layer 301 , a sub-pixel driving circuit 105 located on the buffer layer 301 and corresponding to the second display area 102 , and sub-pixels located in the sub-pixel driving circuit 105
  • the sub-pixel driving thin film transistor located in the sub-pixel driving circuit 105 includes an active layer 302 , a first insulating layer 303 located on the active layer 302 , and a first insulating layer 303 located on the first insulating layer 303 .
  • the two via holes 311 are connected to the other end of the active layer 302 .
  • the pixel electrode 314 is connected to the source stage 308 through a third via hole 315 .
  • the light-emitting sub-pixels 318 in the third display area 103 are connected to the sub-pixel driving thin film transistors in the sub-pixel driving circuit 105 in the second display area 102 through metal traces 320.
  • the metal traces 320 here can be disposed in the same layer as the pixel electrodes 314 , and the light-emitting sub-pixels 318 in the third display area 103 are connected to the source stage 308 through the metal traces 320 .
  • the sub-pixel driving thin film transistors in the sub-pixel driving circuit 105 in the second display area 102 are used to control the light-emitting sub-pixels in the third display area 103, so that borderless display can be realized without affecting the gate lines and Design of the drive circuit.
  • thin film transistors may not be provided in the third display area 103 , that is, the GOA thin film transistors 312 may be provided in other ways, and the present application is not limited to this.
  • an embodiment of the present application provides a display device 10 , including: a back frame 11 and a borderless display panel 12 disposed on the back frame 11 , wherein the borderless display panel 12 is the above-mentioned embodiment
  • the borderless display panel 12 is the above-mentioned embodiment
  • FIG. 1 and FIG. 2 for details, which will not be repeated here.
  • an embodiment of the present application provides a mosaic-type display device 20 , which includes a back frame 21 and a plurality of borderless display panels 22 , and the plurality of borderless display panels 22 are disposed on the back frame 21 and spliced into a display surface, wherein each of the borderless display panels 22 is the borderless display panel provided in the above-mentioned embodiment, please refer to FIG. 1 and FIG. 2 for details, and details are not repeated here.
  • any one of the multiple borderless display panels can work independently.
  • the frameless display panel provided by the embodiment of the present application for splicing no splicing traces will be produced, and the display effect will not be affected.
  • a borderless display panel provided by an embodiment of the present application, by dividing the display area of the panel into a first display area, a second display area surrounding the first display area, and a third display area surrounding the second display area In the display area, the distribution densities of the sub-pixel driving thin film transistors in the first display area and the second display area are equal, and the distribution density of the light-emitting sub-pixels in the first display area is greater than that in the second display area
  • the distribution density of the light-emitting sub-pixels in the third display area is not provided with sub-pixel driving thin film transistors, and a part of the sub-pixel driving thin-film transistors in the second display area and the light-emitting sub-pixels in the second display area are driven.

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Abstract

一种无边框显示面板、显示装置(10)及拼接型显示装置(20)。无边框显示面板区分为第一显示区(101)、包围第一显示区(101)的第二显示区(102)、以及包围第二显示区(102)的第三显示区(103)，第三显示区(103)内没有设置子像素驱动薄膜晶体管，第二显示区(102)内的多个子像素驱动薄膜晶体管的一部分分别通过多条金属走线(203、206)与第三显示区(103)内的多个发光子像素(108)相连。

Description

一种无边框显示面板、显示装置及拼接型显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种无边框显示面板、显示装置及拼接型显示装置。
 背景技术
随着显示技术的发展，工艺的进步，显示面板的应用领域也逐渐增多。例如广告、汽车、手机等行业。特别是汽车市场，例如车内全景显示、交通控制中心等应用场景对显示面板的尺寸要求比较高，这样就需要将多个小尺寸面板拼接成大尺寸屏幕，然后利用图像分割技术将信号分别传送给每个单独的显示屏进行组合显示。
但是由于多个小屏拼接成的大屏幕，其中各个小屏均存在外边框，而外边框无法显示，即屏占比太低，因此不可避免的会出现面板和面板之间有拼接的痕迹，会造成视觉上的不完善，影响显示效果。故，有必要改善这一缺陷。
 技术问题
本申请提供一种无边框显示面板，用于解决现有技术的显示面板，其外边框无法显示，导致屏占比太低，以及拼接成大尺寸面板会存在拼接痕迹，影响显示效果的技术问题。
 技术解决方案
本申请实施例提供一种无边框显示面板，区分为第一显示区、包围所述第一显示区的第二显示区、以及包围所述第二显示区的第三显示区。所述第一显示区和所述第二显示区内均设置有多个子像素驱动薄膜晶体管。所述第一显示区内的所述子像素驱动薄膜晶体管的分布密度与所述第二显示区内的所述子像素驱动薄膜晶体管的分布密度相等。所述第一显示区、所述第二显示区、以及所述第三显示区内均设置有多个发光子像素。所述第一显示区内的所述发光子像素的分布密度大于所述第二显示区内的所述发光子像素的分布密度。其中，所述第三显示区内没有设置子像素驱动薄膜晶体管。所述第二显示区内的多个所述子像素驱动薄膜晶体管的一部分分别与所述第二显示区内的多个所述发光子像素相连。所述第二显示区内的多个所述子像素驱动薄膜晶体管的另一部分分别通过多条金属走线与所述第三显示区内的多个所述发光子像素相连。
在本申请实施例提供的一种无边框显示面板中，所述第二显示区分为第一直条区和第一边角区。所述第三显示区分为第二直条区和第二边角区。所述第二直条区内的多个所述发光子像素分别通过多条所述金属走线与所述第一直条区内的多个所述子像素驱动薄膜晶体管相连。所述第二边角区内的多个所述发光子像素分别通过多条所述金属走线与所述第一边角区内的多个所述子像素驱动薄膜晶体管相连。
在本申请实施例提供的一种无边框显示面板中，连接所述第二直条区内的发光子像素与所述第一直条区内的子像素驱动薄膜晶体管的金属走线呈水平方向或竖直方向。
在本申请实施例提供的一种无边框显示面板中，连接所述第二边角区内的发光子像素与所述第一边角区内的子像素驱动薄膜晶体管的金属走线呈倾斜方向，所述倾斜方向与所述水平方向或所述竖直方向成第一夹角。
在本申请实施例提供的一种无边框显示面板中，所述第一夹角为锐角。
在本申请实施例提供的一种无边框显示面板中，所述第二显示区内的多个所述发光子像素的数量与所述第三显示区内的多个所述发光子像素的数量之和，等于所述第二显示区内的多个所述子像素驱动薄膜晶体管的数量。
在本申请实施例提供的一种无边框显示面板中，所述发光子像素包括多个红色子像素、多个绿色子像素、以及多个蓝色子像素，并且由一个所述红色子像素、两个所述绿色子像素、以及一个所述蓝色子像素组成一个像素单元。
在本申请实施例提供的一种无边框显示面板中，所述发光子像素的排布方式为矩阵排布。所述像素单元包括第一像素单元和第二像素单元。在所述第一像素单元中，两个所述绿色子像素位于一侧，一个所述红色子像素和一个所述蓝色子像素位于另一侧，且所述红色子像素位于所述蓝色子像素之上。在所述第二像素单元中，两个所述绿色子像素位于一侧，一个所述红色子像素和一个所述蓝色子像素位于另一侧，且所述蓝色子像素位于所述红色子像素之上。
在本申请实施例提供的一种无边框显示面板中，所述绿色子像素分别对应于所述红色子像素和所述蓝色子像素的中下部设置。
在本申请实施例提供的一种无边框显示面板中，任一行所述像素单元均按照第一像素单元、第二像素单元的顺序循环排布。
在本申请实施例提供的一种无边框显示面板中，所述绿色子像素的出光面积分别小于所述红色子像素和所述蓝色子像素的出光面积。
在本申请实施例提供的一种无边框显示面板中，所述发光子像素的形状为圆形、三角形、或矩形。
本申请实施例提供一种显示装置，包括：背框、以及设置于所述背框上的无边框显示面板。其中，所述无边框显示面板区分为第一显示区、包围所述第一显示区的第二显示区、以及包围所述第二显示区的第三显示区。所述第一显示区和所述第二显示区内均设置有多个子像素驱动薄膜晶体管。所述第一显示区内的所述子像素驱动薄膜晶体管的分布密度与所述第二显示区内的所述子像素驱动薄膜晶体管的分布密度相等。所述第一显示区、所述第二显示区、以及所述第三显示区内均设置有多个发光子像素。所述第一显示区内的所述发光子像素的分布密度大于所述第二显示区内的所述发光子像素的分布密度。其中，所述第三显示区内没有设置子像素驱动薄膜晶体管。所述第二显示区内的多个所述子像素驱动薄膜晶体管的一部分分别与所述第二显示区内的多个所述发光子像素相连。所述第二显示区内的多个所述子像素驱动薄膜晶体管的另一部分分别通过多条金属走线与所述第三显示区内的多个所述发光子像素相连。
在本申请实施例提供的一种显示装置中，所述第二显示区分为第一直条区和第一边角区。所述第三显示区分为第二直条区和第二边角区。所述第二直条区内的多个所述发光子像素分别通过多条所述金属走线与所述第一直条区内的多个所述子像素驱动薄膜晶体管相连。所述第二边角区内的多个所述发光子像素分别通过多条所述金属走线与所述第一边角区内的多个所述子像素驱动薄膜晶体管相连。
在本申请实施例提供的一种显示装置中，所述第二显示区内的多个所述发光子像素的数量与所述第三显示区内的多个所述发光子像素的数量之和，等于所述第二显示区内的多个所述子像素驱动薄膜晶体管的数量。
在本申请实施例提供的一种显示装置中，所述发光子像素包括多个红色子像素、多个绿色子像素、以及多个蓝色子像素，并且由一个所述红色子像素、两个所述绿色子像素、以及一个所述蓝色子像素组成一个像素单元。
本申请实施例提供一种拼接型显示装置，包括：背框、以及多个无边框显示面板。多个所述无边框显示面板设置于所述背框上并拼接成一个显示面。其中，每一个所述无边框显示面板区分为第一显示区、包围所述第一显示区的第二显示区、以及包围所述第二显示区的第三显示区。所述第一显示区和所述第二显示区内均设置有多个子像素驱动薄膜晶体管。所述第一显示区内的所述子像素驱动薄膜晶体管的分布密度与所述第二显示区内的所述子像素驱动薄膜晶体管的分布密度相等。所述第一显示区、所述第二显示区、以及所述第三显示区内均设置有多个发光子像素。所述第一显示区内的所述发光子像素的分布密度大于所述第二显示区内的所述发光子像素的分布密度。其中，所述第三显示区内没有设置子像素驱动薄膜晶体管。所述第二显示区内的多个所述子像素驱动薄膜晶体管的一部分分别与所述第二显示区内的多个所述发光子像素相连。所述第二显示区内的多个所述子像素驱动薄膜晶体管的另一部分分别通过多条金属走线与所述第三显示区内的多个所述发光子像素相连。
在本申请实施例提供的一种拼接型显示装置中，每一个所述无边框显示面板中，所述第二显示区分为第一直条区和第一边角区。所述第三显示区分为第二直条区和第二边角区。所述第二直条区内的多个所述发光子像素分别通过多条所述金属走线与所述第一直条区内的多个所述子像素驱动薄膜晶体管相连。所述第二边角区内的多个所述发光子像素分别通过多条所述金属走线与所述第一边角区内的多个所述子像素驱动薄膜晶体管相连。
在本申请实施例提供的一种拼接型显示装置中，每一个所述无边框显示面板中，所述第二显示区内的多个所述发光子像素的数量与所述第三显示区内的多个所述发光子像素的数量之和，等于所述第二显示区内的多个所述子像素驱动薄膜晶体管的数量。
在本申请实施例提供的一种拼接型显示装置中，所述发光子像素包括多个红色子像素、多个绿色子像素、以及多个蓝色子像素，并且由一个所述红色子像素、两个所述绿色子像素、以及一个所述蓝色子像素组成一个像素单元。
 有益效果
本申请提供的一种无边框显示面板，通过将面板的显示区分为第一显示区、包围第一显示区的第二显示区、以及包围第二显示区的第三显示区，所述第一显示区和所述第二显示区内的子像素驱动薄膜晶体管的分布密度相等，所述第一显示区内的发光子像素的分布密度大于所述第二显示区内的发光子像素的分布密度，所述第三显示区内不设置子像素驱动薄膜晶体管，将所述第二显示区内的一部分子像素驱动薄膜晶体管与所述第二显示区内的发光子像素相连，将所述第二显示区内的另一部分子像素驱动薄膜晶体管与所述第三显示区内的发光子像素相连，从而可实现无边框显示，提高屏占比，增加产品的应用范围，避免了拼接痕迹造成的显示差异。
 附图说明
图1是本申请实施例提供的无边框显示面板的基本结构示意图。
图2是本申请另一实施例提供的无边框显示面板的基本结构示意图。
图3是本申请提供的无边框显示面板的第二显示区和第三显示区的截面示意图。
图4是本申请实施例提供的无边框显示面板的子像素分布示意图。
图5是本申请实施例提供的显示装置的基本结构示意图。
图6是本申请实施例提供的拼接型显示装置的基本结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。在附图中，为了理解和便于描述，夸大了一些层和区域的尺寸。
如图1所示，为本申请实施例提供的无边框显示面板的基本结构示意图，所述无边框显示面板区分为第一显示区101、包围所述第一显示区101的第二显示区102、以及包围所述第二显示区102的第三显示区103，所述第一显示区101和所述第二显示区102内均设置有多个子像素驱动薄膜晶体管（图未绘示），所述第一显示区101内的所述子像素驱动薄膜晶体管的分布密度与所述第二显示区102内的所述子像素驱动薄膜晶体管的分布密度相等。
需要说明的是，图1中绘出的是所述第一显示区101内的子像素驱动电路104与所述第二显示区102内的子像素驱动电路105的示意图，其中，所述子像素驱动电路104中包含有至少一个所述子像素驱动薄膜晶体管，所述子像素驱动电路105中亦包含有至少一个所述子像素驱动薄膜晶体管。由于子像素驱动电路104、105的细节并非本申请的重点，因此并未描绘出详细的结构图，亦未加以详述。子像素驱动电路104、105只要能用以驱动发光子像素即可，本申请不限制其电路细节。另外需要说明的是，子像素驱动电路104、105通常位于发光子像素106、107的下方，为了便于显示其相对位置，图1与图2均是以俯视图的角度绘示，并且由于俯视视角的关系，子像素驱动电路104、105与发光子像素106、107有一部分呈现重叠的配置。
参阅图1、图2，所述第一显示区101、所述第二显示区102、以及所述第三显示区103内均设置有多个发光子像素106、107、108，所述第一显示区101内的所述发光子像素106的分布密度大于所述第二显示区102内的所述发光子像素107的分布密度；参阅图2，其中，所述第三显示区103内没有设置子像素驱动薄膜晶体管，所述第二显示区102内的多个所述子像素驱动薄膜晶体管的一部分(位于子像素驱动电路2041中)分别与所述第二显示区102内的多个所述发光子像素107相连，所述第二显示区102内的多个所述子像素驱动薄膜晶体管的另一部分(位于子像素驱动电路2042中)分别通过多条金属走线203、206与所述第三显示区103内的多个所述发光子像素202、205相连。
需要说明的是，本申请实施例通过将所述第二显示区102内的子像素驱动薄膜晶体管(位于子像素驱动电路204中)的分布密度设置为与所述第一显示区101内的子像素驱动薄膜晶体管(位于子像素驱动电路104中)的分布密度相等，将所述第二显示区102内的发光子像素107的分布密度设置为小于所述第一显示区101内的发光子像素106的分布密度，即所述第二显示区102内的发光子像素107只连接了所述第二显示区102内的一部分的子像素驱动薄膜晶体管(位于子像素驱动电路2041中)，同时，所述第三显示区103内不设置子像素驱动薄膜晶体管，将所述第三显示区103内的发光子像素202、205通过金属走线203、206与所述第二显示区102内的另一部分子像素驱动薄膜晶体管(位于子像素驱动电路2042中)相连，如此可实现无边框显示，且不会影响栅线和驱动电路的设计。
在一种实施例中，所述第二显示区102内的多个所述发光子像素107的数量与所述第三显示区103内的多个所述发光子像素202、205的数量之和，等于所述第二显示区102内的多个所述子像素驱动薄膜晶体管(位于子像素驱动电路204中)的数量，即所述第二显示区102内的多个所述发光子像素107加上所述第三显示区103内的多个所述发光子像素202、205，与所述第二显示区102内的多个所述子像素驱动薄膜晶体管(位于子像素驱动电路204中)一一对应，每一个子像素驱动薄膜晶体管均对应一个发光子像素。本申请实施例将第二显示区102内的发光子像素的分布密度减小，将一部分发光子像素扩展至第三显示区103（对应现有技术的外边框区）内，可实现整个面板区域都具有显示功能，当拼接成大尺寸面板时，避免产生拼接痕迹。
在一种实施例中，所述无边框显示面板还包括源驱动电路109，所述源驱动电路109用于控制发光子像素的电压（灰阶值），从而显示相应的亮度。由于源驱动电路109通常位于第三显示区103（对应现有技术的外边框区）内，因此第三显示区103不便设置子像素驱动电路，导致现有技术中的外边框区无法进行显示，且外边框区空间能缩小的程度有限。为了解决上述问题，本申请将一部分发光子像素扩展至第三显示区103（对应现有技术的外边框区）内，将所述第三显示区103内的发光子像素202、205通过金属走线203、206与所述第二显示区102内的另一部分子像素驱动薄膜晶体管(位于子像素驱动电路2042中)相连，如此可实现无边框显示，且不会影响栅线和驱动电路的设计。
参阅图1，在一种实施例中，所述发光子像素包括多个红色子像素110、多个绿色子像素111、以及多个蓝色子像素112，并且由一个所述红色子像素110、两个所述绿色子像素111、以及一个所述蓝色子像素112组成一个像素单元。其中，所述发光子像素的排布方式为矩阵排布，所述像素单元包括第一像素单元113和第二像素单元114。在所述第一像素单元113中，两个所述绿色子像素111位于一侧，一个所述红色子像素110和一个所述蓝色子像素112位于另一侧，且所述红色子像素110位于所述蓝色子像素112之上；在所述第二像素单元114中，两个所述绿色子像素111位于一侧，一个所述红色子像素110和一个所述蓝色子像素112位于另一侧，且所述蓝色子像素112位于所述红色子像素110之上。任一行所述像素单元均按照第一像素单元113、第二像素单元114的顺序循环排布。
在一种实施例中，所述发光子像素的形状为圆形、三角形、或矩形。例如，图1中所述红色子像素110和所述蓝色子像素112的形状均为矩形，所述绿色子像素111的形状为圆形。
在一种实施例中，所述绿色子像素111的出光面积分别小于所述红色子像素110和所述蓝色子像素112的出光面积。需要说明的是，由于所述红色子像素110和所述蓝色子像素112的亮度衰减较快，寿命较短，因此设置较大面积的所述红色子像素110和所述蓝色子像素112，使得三种像素的亮度衰减与寿命长短均一化。
参阅图4，在一种实施例中，所述绿色子像素111分别对应于所述红色子像素110和所述蓝色子像素112的中下部设置。具体的，以第二像素单元114为例，即一个所述绿色子像素111对应于所述红色子像素110和所述蓝色子像素112的中间位置设置，另一个所述绿色子像素111对应于所述红色子像素110的下方位置设置。即整体而言，所述绿色子像素111与所述红色子像素110和所述蓝色子像素112交错设置，所述绿色子像素111对应所述红色子像素110和所述蓝色子像素112之间设置。
如图2所示，本申请另一实施例提供的无边框显示面板的基本结构示意图，所述无边框显示面板区分为第一显示区101、包围所述第一显示区101的第二显示区102、以及包围所述第二显示区102的第三显示区103；所述第一显示区101内的多个发光子像素106分别通过多条金属走线201与所述第一显示区101内的多个子像素驱动电路104中的子像素驱动薄膜晶体管相连；所述第二显示区102分为第一直条区1021和第一边角区1022，所述第三显示区103分为第二直条区1031和第二边角区1032；其中，所述第二直条区1031内的多个所述发光子像素202分别通过多条所述金属走线203与所述第一直条区1021内的多个所述子像素驱动电路204中的子像素驱动薄膜晶体管相连，所述第二边角区1032内的多个所述发光子像素205分别通过多条所述金属走线206与所述第一边角区1022内的多个所述子像素驱动电路207中的子像素驱动薄膜晶体管相连。
在一种实施例中，连接所述第二直条区1031内的发光子像素202与所述第一直条区1021内的子像素驱动薄膜晶体管的金属走线203大致呈水平方向（左右两侧）或竖直方向（上下两侧），图2为了便于描述，并未将金属走线203绘制呈水平方向。连接所述第二边角区1032内的发光子像素205与所述第一边角区1022内的子像素驱动薄膜晶体管的金属走线206呈倾斜方向，倾斜方向与水平方向或竖直方向成第一夹角a，所述第一夹角a为锐角。具体地，所述第一夹角a为大于0度且小于或者等于45度。
需要说明的是，本实施例将第二显示区102分为第一直条区1021和第一边角区1022，将第三显示区103分为第二直条区1031和第二边角区1032，然后将第二直条区1031内的发光子像素202与第一直条区1021内的子像素驱动薄膜晶体管相连，将第二边角区1032内的发光子像素205与第一边角区1022内的子像素驱动薄膜晶体管相连，即将所述第一直条区1021内的发光子像素横向或者纵向扩展，将所述第一边角区1022内的发光子像素按第一夹角a斜向扩展，如此可使得所有的发光子像素均匀排布，提高显示质量。
如图2所示，在一种实施例中，所述无边框显示面板还包括源驱动电路109和GOA驱动电路208，所述GOA驱动电路208用于控制某一行的发光子像素的打开或关闭，所述GOA驱动电路208中包含有至少一个GOA薄膜晶体管（对应于图3中的GOA薄膜晶体管312）。由于GOA驱动电路208通常位于第三显示区103（对应现有技术的外边框区）内，因此第三显示区103不便设置子像素驱动电路，导致现有技术中的外边框区无法进行显示，且外边框区空间能缩小的程度有限。为了解决上述问题，本申请将一部分发光子像素扩展至第三显示区103（对应现有技术的外边框区）内，将所述第三显示区103内的发光子像素通过金属走线与所述第二显示区102内的另一部分子像素驱动薄膜晶体管相连，如此可实现无边框显示，且不会影响栅线和驱动电路的设计。
如图3所示，本申请提供的无边框显示面板的第二显示区和第三显示区的截面示意图，从图中可以很直观地看到本申请的各组成部分，以及各组成部分之间的相对位置关系，所述无边框显示面板包括缓冲层301、位于所述缓冲层301上且对应于第二显示区102的子像素驱动电路105、位于所述子像素驱动电路105内的子像素驱动薄膜晶体管、位于所述缓冲层301上且对应于第三显示区103的GOA薄膜晶体管312、位于所述子像素驱动电路105和所述GOA薄膜晶体管312上的平坦化层313、位于所述平坦化层313上的像素电极314、位于所述平坦化层313上的像素定义层316、位于所述像素电极314上且对应所述第二显示区102的发光子像素317、位于所述像素电极314上且对应所述第三显示区103的发光子像素318、以及位于所述像素定义层316上的支撑柱319。所述缓冲层301下方可设置基板(未绘示)。
其中，位于所述子像素驱动电路105内的子像素驱动薄膜晶体管包括有源层302、位于所述有源层302上的第一绝缘层303、位于所述第一绝缘层303上的第一金属层304、位于所述第一金属层304上的第二绝缘层305、位于所述第二绝缘层305上的第二金属层306、位于所述第二金属层306上的第三绝缘层307、以及位于所述第三绝缘层307上的源级308和漏极309，所述源级308通过第一过孔310与所述有源层302的一端相连，所述漏极309通过第二过孔311与所述有源层302的另一端相连。所述像素电极314通过第三过孔315与所述源级308相连。
需要说明的是，所述第三显示区103内的发光子像素318通过金属走线320与所述第二显示区102内的子像素驱动电路105内的子像素驱动薄膜晶体管相连，具体地，此处的金属走线320可与像素电极314同层设置，所述第三显示区103内的发光子像素318通过所述金属走线320与所述源级308相连。本申请实施例通过第二显示区102内的子像素驱动电路105内的子像素驱动薄膜晶体管控制所述第三显示区103内的发光子像素，可实现无边框显示，且不影响栅线和驱动电路的设计。
需要说明的是，所述第三显示区103内可不设置薄膜晶体管，即所述GOA薄膜晶体管312可以其他方式设置，本申请不以此为限。
参阅图5，本申请实施例提供一种显示装置10，包括：背框11、以及设置于所述背框11上的无边框显示面板12，其中，所述无边框显示面板12为上述实施例提供的无边框显示面板，具体请参阅图1和图2，此处不再赘述。
参阅图6，本申请实施例提供一种拼接型显示装置20，包括：背框21、以及多个无边框显示面板22，多个所述无边框显示面板22设置于所述背框21上并拼接成一个显示面，其中，每一个所述无边框显示面板22为上述实施例提供的无边框显示面板，具体请参阅图1和图2，此处不再赘述。
需要说明的是，多个所述无边框显示面板中的任一个都可以独立工作。采用本申请实施例提供的无边框显示面板进行拼接，不会产生拼接痕迹，不会影响显示效果。
综上所述，本申请实施例提供的一种无边框显示面板，通过将面板的显示区分为第一显示区、包围第一显示区的第二显示区、以及包围第二显示区的第三显示区，所述第一显示区和所述第二显示区内的子像素驱动薄膜晶体管的分布密度相等，所述第一显示区内的发光子像素的分布密度大于所述第二显示区内的发光子像素的分布密度，所述第三显示区内不设置子像素驱动薄膜晶体管，将所述第二显示区内的一部分子像素驱动薄膜晶体管与所述第二显示区内的发光子像素相连，将所述第二显示区内的另一部分子像素驱动薄膜晶体管与所述第三显示区内的发光子像素相连，从而可实现无边框显示，提高屏占比，增加产品的应用范围，避免了拼接痕迹造成的显示差异，解决了现有技术的显示面板，其外边框无法显示，导致屏占比太低，以及拼接成大尺寸面板会存在拼接痕迹，影响显示效果的技术问题。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种无边框显示面板，区分为第一显示区、包围所述第一显示区的第二显示区、以及包围所述第二显示区的第三显示区，其中，所述第一显示区和所述第二显示区内均设置有多个子像素驱动薄膜晶体管，所述第一显示区内的所述子像素驱动薄膜晶体管的分布密度与所述第二显示区内的所述子像素驱动薄膜晶体管的分布密度相等；所述第一显示区、所述第二显示区、以及所述第三显示区内均设置有多个发光子像素，所述第一显示区内的所述发光子像素的分布密度大于所述第二显示区内的所述发光子像素的分布密度；
    其中，所述第三显示区内没有设置子像素驱动薄膜晶体管，所述第二显示区内的多个所述子像素驱动薄膜晶体管的一部分分别与所述第二显示区内的多个所述发光子像素相连，所述第二显示区内的多个所述子像素驱动薄膜晶体管的另一部分分别通过多条金属走线与所述第三显示区内的多个所述发光子像素相连。
  2. 如权利要求1所述的无边框显示面板，其中，所述第二显示区分为第一直条区和第一边角区，所述第三显示区分为第二直条区和第二边角区，所述第二直条区内的多个所述发光子像素分别通过多条所述金属走线与所述第一直条区内的多个所述子像素驱动薄膜晶体管相连，所述第二边角区内的多个所述发光子像素分别通过多条所述金属走线与所述第一边角区内的多个所述子像素驱动薄膜晶体管相连。
  3. 如权利要求2所述的无边框显示面板，其中，连接所述第二直条区内的发光子像素与所述第一直条区内的子像素驱动薄膜晶体管的金属走线呈水平方向或竖直方向。
  4. 如权利要求2所述的无边框显示面板，其中，连接所述第二边角区内的发光子像素与所述第一边角区内的子像素驱动薄膜晶体管的金属走线呈倾斜方向，所述倾斜方向与所述水平方向或所述竖直方向成第一夹角。
  5. 如权利要求4所述的无边框显示面板，其中，所述第一夹角为锐角。
  6. 如权利要求1所述的无边框显示面板，其中，所述第二显示区内的多个所述发光子像素的数量与所述第三显示区内的多个所述发光子像素的数量之和，等于所述第二显示区内的多个所述子像素驱动薄膜晶体管的数量。
  7. 如权利要求6所述的无边框显示面板，其中，所述发光子像素包括多个红色子像素、多个绿色子像素、以及多个蓝色子像素，并且由一个所述红色子像素、两个所述绿色子像素、以及一个所述蓝色子像素组成一个像素单元。
  8. 如权利要求7所述的无边框显示面板，其中，所述发光子像素的排布方式为矩阵排布，所述像素单元包括第一像素单元和第二像素单元；
    在所述第一像素单元中，两个所述绿色子像素位于一侧，一个所述红色子像素和一个所述蓝色子像素位于另一侧，且所述红色子像素位于所述蓝色子像素之上；
    在所述第二像素单元中，两个所述绿色子像素位于一侧，一个所述红色子像素和一个所述蓝色子像素位于另一侧，且所述蓝色子像素位于所述红色子像素之上。
  9. 如权利要求8所述的无边框显示面板，其中，所述绿色子像素分别对应于所述红色子像素和所述蓝色子像素的中下部设置。
  10. 如权利要求8所述的无边框显示面板，其中，任一行所述像素单元均按照第一像素单元、第二像素单元的顺序循环排布。
  11. 如权利要求7所述的无边框显示面板，其中，所述绿色子像素的出光面积分别小于所述红色子像素和所述蓝色子像素的出光面积。
  12. 如权利要求6所述的无边框显示面板，其中，所述发光子像素的形状为圆形、三角形、或矩形。
  13. 一种显示装置，其包括：
    背框；以及
    无边框显示面板，设置于所述背框上，其中，所述无边框显示面板区分为第一显示区、包围所述第一显示区的第二显示区、以及包围所述第二显示区的第三显示区，所述第一显示区和所述第二显示区内均设置有多个子像素驱动薄膜晶体管，所述第一显示区内的所述子像素驱动薄膜晶体管的分布密度与所述第二显示区内的所述子像素驱动薄膜晶体管的分布密度相等；所述第一显示区、所述第二显示区、以及所述第三显示区内均设置有多个发光子像素，所述第一显示区内的所述发光子像素的分布密度大于所述第二显示区内的所述发光子像素的分布密度；
    其中，所述第三显示区内没有设置子像素驱动薄膜晶体管，所述第二显示区内的多个所述子像素驱动薄膜晶体管的一部分分别与所述第二显示区内的多个所述发光子像素相连，所述第二显示区内的多个所述子像素驱动薄膜晶体管的另一部分分别通过多条金属走线与所述第三显示区内的多个所述发光子像素相连。
  14. 如权利要求13所述的显示装置，其中，所述第二显示区分为第一直条区和第一边角区，所述第三显示区分为第二直条区和第二边角区，所述第二直条区内的多个所述发光子像素分别通过多条所述金属走线与所述第一直条区内的多个所述子像素驱动薄膜晶体管相连，所述第二边角区内的多个所述发光子像素分别通过多条所述金属走线与所述第一边角区内的多个所述子像素驱动薄膜晶体管相连。
  15. 如权利要求13所述的显示装置，其中，所述第二显示区内的多个所述发光子像素的数量与所述第三显示区内的多个所述发光子像素的数量之和，等于所述第二显示区内的多个所述子像素驱动薄膜晶体管的数量。
  16. 如权利要求15所述的显示装置，其中，所述发光子像素包括多个红色子像素、多个绿色子像素、以及多个蓝色子像素，并且由一个所述红色子像素、两个所述绿色子像素、以及一个所述蓝色子像素组成一个像素单元。
  17. 一种拼接型显示装置，其包括：
    背框；以及
    多个无边框显示面板，设置于所述背框上并拼接成一个显示面，其中，每一个所述无边框显示面板区分为第一显示区、包围所述第一显示区的第二显示区、以及包围所述第二显示区的第三显示区，所述第一显示区和所述第二显示区内均设置有多个子像素驱动薄膜晶体管，所述第一显示区内的所述子像素驱动薄膜晶体管的分布密度与所述第二显示区内的所述子像素驱动薄膜晶体管的分布密度相等；所述第一显示区、所述第二显示区、以及所述第三显示区内均设置有多个发光子像素，所述第一显示区内的所述发光子像素的分布密度大于所述第二显示区内的所述发光子像素的分布密度；
    其中，所述第三显示区内没有设置子像素驱动薄膜晶体管，所述第二显示区内的多个所述子像素驱动薄膜晶体管的一部分分别与所述第二显示区内的多个所述发光子像素相连，所述第二显示区内的多个所述子像素驱动薄膜晶体管的另一部分分别通过多条金属走线与所述第三显示区内的多个所述发光子像素相连。
  18. 如权利要求17所述的拼接型显示装置，其中，每一个所述无边框显示面板中，所述第二显示区分为第一直条区和第一边角区，所述第三显示区分为第二直条区和第二边角区，所述第二直条区内的多个所述发光子像素分别通过多条所述金属走线与所述第一直条区内的多个所述子像素驱动薄膜晶体管相连，所述第二边角区内的多个所述发光子像素分别通过多条所述金属走线与所述第一边角区内的多个所述子像素驱动薄膜晶体管相连。
  19. 如权利要求17所述的拼接型显示装置，其中，每一个所述无边框显示面板中，所述第二显示区内的多个所述发光子像素的数量与所述第三显示区内的多个所述发光子像素的数量之和，等于所述第二显示区内的多个所述子像素驱动薄膜晶体管的数量。
  20. 如权利要求19所述的拼接型显示装置，其中，所述发光子像素包括多个红色子像素、多个绿色子像素、以及多个蓝色子像素，并且由一个所述红色子像素、两个所述绿色子像素、以及一个所述蓝色子像素组成一个像素单元。
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