WO2019101019A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2019101019A1
WO2019101019A1 PCT/CN2018/116013 CN2018116013W WO2019101019A1 WO 2019101019 A1 WO2019101019 A1 WO 2019101019A1 CN 2018116013 W CN2018116013 W CN 2018116013W WO 2019101019 A1 WO2019101019 A1 WO 2019101019A1
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WO
WIPO (PCT)
Prior art keywords
line
lead
array substrate
common electrode
display area
Prior art date
Application number
PCT/CN2018/116013
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English (en)
French (fr)
Inventor
程鸿飞
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/482,050 priority Critical patent/US11092865B2/en
Priority to JP2019569873A priority patent/JP7356360B2/ja
Publication of WO2019101019A1 publication Critical patent/WO2019101019A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate and a display device.
  • the array substrate can be generally divided into a display area and a non-display area. Among them, a large number of traces are arranged in the non-display area, and a large number of electronic devices are arranged in the display area.
  • An aspect of the present disclosure provides an array substrate including: a display area and a non-display area; at least a signal line located in the display area; a signal line lead located in the non-display area; and a location in the non-display area And a connection portion connecting the signal line and the signal line lead; wherein the signal line and the signal line lead are two independent parts.
  • connection portion is located at a different layer from at least one of the signal line and the signal line lead.
  • the array substrate further includes: a plurality of gate lines and a plurality of data lines; and a plurality of the gate lines and the plurality of the data lines are vertically and vertically staggered and arranged in a matrix Sub-pixels.
  • the signal line includes: the gate line and the data line; the signal line lead includes: a gate line lead and a data line lead; wherein each of the gate lines respectively passes through a different The connecting portion is connected to the different gate line leads in a one-to-one correspondence; each of the data lines is connected to the different data line leads in a one-to-one correspondence through different connecting portions.
  • the gate line includes: a first linear body located at least in the display area; and a first bulk body located in the non-display area;
  • the gate line lead includes: a gate line lead body of the non-display area and a second block body located at an end of the gate line lead main body adjacent to the display area; the connection portion connecting the first block body and the second block Shape.
  • the data line includes: a second linear body located at least in the display area and a third bulk body located in the non-display area;
  • the data line lead includes: a data line lead body of the non-display area and a fourth block body located at an end of the data line lead main body adjacent to the display area;
  • the connecting portion connects the third block and the fourth block.
  • the signal line further includes a common electrode line
  • the signal line lead further includes a common electrode lead
  • the common electrode line is connected to the common electrode lead through the connection portion.
  • the common electrode lead is aligned with the extending direction of the data line, and each of the common electrode lines is respectively connected to the same common electrode lead through a different one of the connecting portions; or
  • the common electrode lead includes: a lead body that coincides with an extending direction of the data line; and a plurality of fifth block bodies connected to the lead body and extending toward the common electrode line direction, each of the fifth block shapes The body corresponds to one of the connecting portions, and each of the common electrode lines is connected to the corresponding fifth block by a different one of the connecting portions.
  • each of the common electrode lines is disposed between two adjacent gate lines; the common electrode line includes: at least a third linear body located in the display area and located at the non- a connector in the display region; wherein the connector includes a sixth block, and the connecting portion is coupled to the sixth block.
  • the connector further includes a strip-shaped sub-connector, the sub-connector strip direction is consistent with an extending direction of the data line, and the third linear body and the sixth The blocks are respectively located on two sides of the sub-connector along the vertical direction thereof, and the third linear body and the sixth block are respectively connected to the sub-connector in a staggered manner.
  • a distance of the sixth block from the first gate line is smaller than a distance of the third line from the first gate line, wherein the first gate line is: Among the two gate lines adjacent to the third linear body, one gate line farther from the third linear body.
  • a length of the sub-connector in an extending direction along the data line is smaller than a distance between two gate lines adjacent to the sub-connector, and the sub-connector is The length along the extending direction of the data line is greater than or equal to 3/4 of the distance between the two gate lines adjacent to the sub-connector.
  • the array substrate further includes: a first electrostatic protection line located in the non-display area, a first electrostatic protection unit; wherein the first electrostatic protection line and the extension of the data line The grid line leads are connected to the first electrostatic protection line through the first electrostatic protection unit; the array substrate further includes: a second electrostatic protection line and a second static electricity protection located in the non-display area a unit, wherein the second electrostatic protection line is in line with an extending direction of the gate line, and the data line is connected to the second electrostatic protection line through the second static electricity protection unit.
  • the first electrostatic protection line is located at a side of the common electrode lead that faces away from the display area; and the second electrostatic protection line is located at a side of the data line lead that is adjacent to the display area. side.
  • the first electrostatic protection line is integrated with the common electrode lead; or the array substrate further includes a third electrostatic protection unit located in the non-display area, the first The electrostatic protection wire is connected to the common electrode lead through the third electrostatic protection unit; and/or the array substrate further includes a fourth electrostatic protection unit located in the non-display area, and the second electrostatic protection line passes The fourth static electricity protection unit is connected to the common electrode lead.
  • any one of the first static electricity protection unit, the second static electricity protection unit, the third static electricity protection unit, and the fourth static electricity protection unit includes: a first transistor, a second transistor, a first connection end, and a second connection end; wherein a source, a gate of the first transistor and a drain of the second transistor are connected to the first connection end; a source, a gate and a second of the second transistor The drains of the one transistor are connected to the second connection end; the first connection end and the second connection end are used to respectively connect two conductors that need to be electrostatically discharged from each other.
  • the sub-pixel includes: a pixel electrode and a common electrode connected to the common electrode line; the pixel electrode includes a first strip-shaped sub-electrode, and the common electrode includes a second strip-shaped sub-electrode, The first strip-shaped sub-electrode is spaced apart from the second strip-shaped sub-electrode, and the first strip-shaped sub-electrode and the second strip-shaped sub-electrode are both parallel to the data line; the sub-connector is adjacent to the A boundary on one side of the display area is parallel to the first strip sub-electrode and the second strip sub-electrode.
  • the data lines are non-linear.
  • each of the pixel electrodes of the adjacent rows is different from the adjacent two data lines
  • the data lines are connected; in the same row of sub-pixels, each pixel electrode is connected to the data line on the same side of each sub-pixel of the row.
  • the array substrate further includes: a dummy pixel column and a dummy data line located in the non-display area; wherein the dummy pixel column is adjacent to a sub-pixel column in the display area, The dummy data line is disposed on a side of the dummy pixel column away from the display area; the dummy pixel includes: a dummy pixel electrode and a dummy common electrode; wherein each dummy pixel electrode in the dummy pixel column has The data line adjacent to the dummy pixel column and the dummy data line are not connected, and each dummy common electrode in the dummy pixel column is connected to the common electrode line.
  • the dummy data line is connected to the common electrode lead.
  • the dummy data lines are parallel to the data lines.
  • the dummy pixel electrode includes a first dummy strip electrode
  • the dummy common electrode includes a second dummy strip sub-electrode
  • the first dummy strip sub-electrode and the second dummy strip sub-electrode The electrodes are spaced apart and both are parallel to the data line.
  • connection portion and at least one of the signal line and the signal line lead are located in different layers, including: the connection portion and the signal line and the signal line a different layer of the lead wires, wherein the signal line and the signal line lead are in the same layer; wherein the connecting portion is connected to the signal line and the signal line lead through the first via hole and the second via hole respectively; or The connecting portion is in the same layer as the signal line lead, and the connecting portion is different from the signal line; wherein the connecting portion is directly connected to the signal line lead, and the connecting portion passes through the first via hole and The signal line is connected; or the connection portion is in the same layer as the signal line, the connection portion is different from the signal line lead; wherein the connection portion is directly connected to the signal line, and the connection is The portion is connected to the signal line lead through a second via.
  • the connecting portion is in the same layer and the same material as each pixel electrode in the sub-pixel.
  • the gate line is the same layer and the same material as the common electrode line and the gate line lead; and/or the data line and the data line lead, the common The electrode leads are all in the same layer and the same material.
  • the gate line is the same layer and the same material as the common electrode line and the gate line lead; and/or the data line and the data line lead, the common The electrode leads are all in the same layer and the same material.
  • the data line is in the same layer and the same material as the first electrostatic protection line; and/or the gate line is in the same layer and the same material as the second electrostatic protection line.
  • the gate line is the same layer and the same material as the common electrode line, the common electrode lead, and the data line lead; and/or the data line and the gate The wire leads are in the same layer and the same material.
  • the gate line is the same layer and the same material as the common electrode line, the common electrode lead, and the data line lead; and/or the data line and the gate
  • the wire leads are in the same layer and the same material; and/or the gate lines are in the same layer and the same material as the first electrostatic protection wire and the second electrostatic protection wire.
  • Another aspect of the present disclosure provides a display device comprising the array substrate of any of the above.
  • FIG. 1 is a schematic structural diagram of an array substrate according to some embodiments of the present disclosure
  • FIG. 2 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 3 is a schematic structural diagram of another array substrate according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 7 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 8 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an electrostatic protection unit in an array substrate according to some embodiments of the present disclosure.
  • FIG. 11 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 12 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 13 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • FIG. 14 is a schematic structural diagram of still another array substrate according to some embodiments of the present disclosure.
  • Figure 15 is a schematic view showing a combination of the cross-sectional structures of the O-O', A-A', B-B' and C-C' directions of Figure 9;
  • Figure 16 is a cross-sectional structural view of Figure 14 taken along the line D-D';
  • Figure 17 is a view showing another combination of the cross-sectional structures of the O-O', A-A', B-B' and C-C' directions of Figure 9;
  • Figure 18 is a schematic cross-sectional view of another cross-sectional view taken along line D-D' of Figure 14;
  • FIG. 19 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.
  • the array substrate 01 includes: a display area 01a and a non-display area 01b; at least a signal line S1 located in the display area 01a is located in the non-display area.
  • the two separate portions of the signal line S1 and the signal line lead S2 mean that the signal line S1 and the signal line lead S2 are not in contact with each other, that is, the signal line S1 and the signal line lead S2 are in the array substrate 01.
  • the orthographic projections on the substrate for placing the above structures are not in contact.
  • the signal line S1 and the signal line lead S2 are set to two independent parts (ie, disconnected in the embodiment of the present disclosure).
  • a large amount of static charge accumulated on the signal line lead S2 in the non-display area 01b is not transferred to the corresponding signal line in the display area 01a.
  • the probability that the electronic device electrically connected to the signal line S1 in the display area 01a is damaged by the electrostatic impact is reduced, thereby improving the yield of the product.
  • connection portion 100a and the signal line S1 and the signal line lead S2 are located at different layers.
  • the signal line S1 and the signal line lead S2 may be located in the same layer, that is, the two are formed by one patterning process; or, the signal line S1 and the signal line lead S2 may be located in different layers, that is, the two need to pass through two patterning processes.
  • the manufacturing method is not limited in this embodiment, and may be selected according to the type of the array substrate and the type of the signal line, as long as the connection portion 100a, the signal line S1, and the signal line lead S2 are not in the same layer. Not directly connected together.
  • a manner in which at least one of the connecting portion 100a and the signal line S1 and the signal line lead S2 are located at different layers may be, for example,
  • the connecting portion 100a and the signal line S1 and the signal line lead S2 are different layers, and the signal line S1 and the signal line lead S2 are in the same layer; wherein the connecting portion 100a passes through the first via hole V1, the second via hole V2 and the signal line S1, respectively.
  • the signal line lead S2 is connected.
  • the array substrate 01 of course further includes an insulating layer between the connecting portion 100a and the signal line S1 and the signal line lead S2 (one layer) Or the plurality of layers, the first via hole V1 and the second via hole V2 are openings penetrating the insulating layer, so that the connecting portion 100a can pass through the first via hole V1, the second via hole V2 and the signal line, respectively. S1, signal line lead S2 is connected.
  • the specific structure of the insulating layer can be used in related settings, and will not be described herein.
  • connection portion 100a and at least one of the signal line S1 and the signal line lead S2 are located at different layers may be, for example, also:
  • connection portion 100a is in the same layer as the signal line lead S2, and the connection portion 100a is different from the signal line S1.
  • the connection portion 100a is directly connected to the signal line lead S2, and the connection portion 100a is connected to the signal line S1 through the first via hole V1.
  • the array substrate 01 of course further includes an insulating layer between the connection portion 100a, the signal line lead S2 and the signal line S1 ( One or more layers, the first via hole V1 is a through portion opened in the insulating layer, so that the connection portion 100a can be connected to the signal line S1 through the first via hole V1.
  • connection portion 100a and at least one of the signal line S1 and the signal line lead S2 are located at different layers may be, for example,
  • connection portion 100a is in the same layer as the signal line S1, and the connection portion 100a is different from the signal line lead S2.
  • the connection portion 100a is directly connected to the signal line S1, and the connection portion 100a is connected to the signal line lead S2 through the second via hole V2.
  • connection portion 100a is in the same layer as the signal line S1 and is different from the signal line lead S2, the array substrate 01 of course includes the insulation between the connection portion 100a, the signal layer S1 and the signal line lead S2.
  • the layer (one or more layers), the second via hole V2 is a through portion opened in the insulating layer, so that the connection portion 100a can be connected to the signal line lead S2 through the second via hole V2.
  • the embodiment of the present disclosure further provides an array substrate.
  • the array substrate 01 further includes: a plurality of gate lines 10 and a plurality of data lines 20, and the plurality of gate lines 10 and the plurality of data lines 20 are horizontally and vertically interlaced. And defining a plurality of sub-pixels P arranged in a matrix.
  • the display area 01a is the area where all the sub-pixels P are located; the non-display area 01b is generally located around the display area 01a, that is, surrounding the display area.
  • FIG. 4 only shows the display area 01a and the non-display area 01b through the partial structure in the array substrate 01.
  • the periphery of the display area 01a is the non-display area 01b, which is not fully shown in FIG. Out.
  • the array substrate 01 includes a plurality of traces located in the display area 01a and the non-display area 01b, for example, gate lines, data lines, common electrode lines located in the display area, and gate lines connected to the gate lines in the non-display area Lead wires, data line leads connected to data lines, common electrode leads connected to common electrode lines, and the like.
  • the signal line S1 and the signal line lead S2 may be the gate line 10 and the gate line lead 11, respectively; or may be the data line 20 and the data line lead 21 respectively; or may be a common electrode
  • the one or more sets of routing structures may be selected to be the structure of the above-mentioned signal lines and signal line leads.
  • the signal line and the signal line lead respectively include one or more of the gate line and the gate line lead, the data line and the data line lead, the common electrode line, and the common electrode lead, and are implemented for the present disclosure. For further explanation.
  • the signal line includes a gate line 10
  • the signal line lead includes a gate line lead 11
  • the signal line further includes a data line 20
  • the signal line lead further includes a data line lead 21.
  • each of the gate lines 10 is connected to the different gate line leads 11 in a one-to-one correspondence through different connection portions 100.
  • the gate lines 10 and the gate line leads 11 extend in the same direction, and one end of the gate line lead 11 near the display area 01a is connected to the gate line 10 through the connection portion 100, and the other end is used for the gate drive IC.
  • the terminal is connected or connected to the output of the Gate Driver on Array (GOA).
  • connection portion 100 and the gate line 10 and the gate line lead 11 are located at different layers, the connection portion 100 generally needs to be connected to the gate line 10 and the gate line lead 11 through via holes, of course, the embodiment of the present disclosure Without being limited thereto, the connection portion 100 may be disposed in direct contact with the gate line 10 or the gate line lead 11 in accordance with the specific structure of the array substrate.
  • the gate line 10 includes: at least in the display area 01 a linear body 101 and a first bulk body 111 located in the non-display area 02;
  • the gate line lead 11 includes: a gate line lead main body 11a and a second block body located at an end portion of the gate line lead main body 11a close to the display area 01a
  • the connecting portion 100 connects the first block body 111 and the second block body 112.
  • each of the data lines 20 passes through different connection portions 100' and different data line leads 21, one by one. Corresponding connection.
  • the data line 20 and the data line lead 21 extend in the same direction, and one end of the data line lead 21 near the display area 01a is connected to the data line 20 through the connection portion 100', and the data line lead 21 is opposite. The other end is used to connect to the terminal of the source driver IC.
  • the connecting portion 100 ′ since the connecting portion 100 ′ is located at a different layer from the data line 20 and the data line lead 21 , the connecting portion 100 ′ generally needs to be connected to the data line 20 and the data line lead 21 through the via hole, of course, the embodiment of the present disclosure. It is not limited thereto, and the connection portion 100' may be disposed in direct contact with the data line 20 or the data line lead 21 in accordance with the specific structure of the array substrate.
  • the data line 20 includes: at least a second linear body 102 in the display area 01a and a third bulk body 113 located in the non-display area 01b;
  • the data line lead 21 includes: a data line lead main body 21a located in the non-display area 01b and a data line lead main body 21a near the display
  • the fourth block 114 at the end of the region 01a; the connecting portion 100' connects the third block 113 and the fourth block 114.
  • the signal line further includes a common electrode line 30 including a common electrode lead 31 connected to the common electrode lead 31 via the connection portion 100".
  • connection portion 100" and the common electrode line 30 and the common electrode lead 31 are located in different layers, the connection portion 100" generally needs to be connected to the common electrode line 30 and the common electrode lead 31 through the via hole, of course,
  • connection portion 100 ′′ may be disposed in direct contact with the common electrode line 30 or the common electrode lead 31 according to the specific structure of the array substrate.
  • the manner in which the above-described common electrode line 30 is connected to the common electrode lead 31 through the connection portion 100" may be as follows: Referring to FIG. 4, the common electrode line 30 coincides with the extending direction of the gate line 10, and each common electrode line 30 They are connected to the common electrode lead 31 through different connection portions 100", respectively.
  • all of the common electrode lines 30 may be connected to the common electrode lead 31 through the same connection portion 100", that is, the common electrode line 30 and the common electrode lead are connected in FIG. 4 without affecting other trace structures.
  • the plurality of connecting portions 100 ′′ of 31 are provided as a unitary structure that is connected together, which is not limited in the embodiment of the present disclosure.
  • each common electrode line of the example of the present disclosure 30 is connected to the common electrode lead 31 through different connection portions 100", respectively.
  • the common electrode lead 31 includes: a lead body 311 that is aligned with the extending direction of the data line 20, and a lead body 311 that is connected to the lead body 311 and extends toward the common electrode line 30. a plurality of fifth block bodies 115; each of the fifth block bodies 115 corresponds to one connecting portion 100", and each of the common electrode lines 30 is connected to the corresponding fifth block body 115 through a different connecting portion 100", Thereby an effective connection between the connection portion 100" and the common electrode lead 31 is ensured.
  • the common electrode lead may include only a portion of the lead body 311 illustrated in FIG. 4, that is, each common electrode line 30 is connected to the common electrode lead 31 through the connecting portion 100", which is not limited.
  • the common electrode line 30 generally includes: a third linear body 103 located at least in the display area 01a and a connecting body U located in the non-display area 01b; wherein the common electrode line 30 is correspondingly disposed on the adjacent two grids
  • the position between the lines 10, in general, the third linear body 103 coincides with the direction in which the gate lines 10 extend.
  • connection body U includes a sixth block body 116, and the connection portion 100" and the Six blocks 116 are connected.
  • the sixth block 116 is generally disposed at an end of the common electrode line 30 on the side close to the common electrode lead 31.
  • the structure is a block structure, which causes the cable to be dense, which easily causes a short circuit between the leads, resulting in poor signal transmission.
  • the connector U includes a strip-shaped sub-connector 110 in addition to the sixth block-shaped body 116 described above.
  • the strip direction of the body 110 coincides with the extending direction of the data line 20, and the third linear body 103 and the sixth block body 116 are respectively located on opposite sides of the sub-connecting body 110 in the vertical direction thereof, and the two are connected to the sub-connector 110 staggered (ie, misaligned) connections.
  • the distance D1 of the sixth block 116 from the first gate line is smaller than the distance D2 of the third line body 103 from the first gate line, wherein the first gate line is: two adjacent to the third linear body 103.
  • the sixth block 116 since the sixth block 116 is connected to the sub-connector 110, the sixth block 116 should be smaller in size than the sub-connector in the extending direction of the data line 20 for ease of wiring. 110 dimensions in this direction.
  • the following embodiments further illustrate the embodiments of the present disclosure by taking the common electrode line 30 including the sub-connector 110 as an example.
  • the third linear body 103 and the sixth block body 116 are located on both sides of the sub-connecting body 110 in the vertical direction thereof, and the misalignment of the two with the sub-connecting body 110 means that the sixth block body 116 is connected to the sub-connecting body.
  • the connection position of the body 110 is not on the extension line of the third linear body 103, that is, the provision of the sub-connector 110 enables the sixth block 116 to be displaced toward the first gate line, and the sub-connector 110 Connections make it easy to route wires and avoid short circuits between lines.
  • the length H1 of the sub-connector 110 in the extending direction along the data line 20 is smaller than the distance H2 between the two gate lines 10 adjacent to the sub-connector 110, and is greater than Or equal to 3/4 of the distance H2 between the two gate lines 10 adjacent to the sub-connector 110, that is, H2>H1 ⁇ (3/4)*H2.
  • the above arrangement can also enable the sub-connector 110 to shield the static charge in the trace structure located in the non-display area 01b, thereby further preventing static electricity.
  • the charge adversely affects the structure in the display area 01a.
  • the lengths of the first block body 111, the second block body 112, the third block body 111, the fourth block body 112, the fifth block body 115, and the sixth block body 116 are generally larger than the linear shape of the first linear body 101, the second linear body 102, and the third linear body 103. Width to ensure an effective connection between each block and the corresponding connection.
  • the array substrate 01 further includes a first electrostatic protection line 201 located in the non-display area 01b and extending in the direction in which the data line 20 extends.
  • the gate line lead 11 passes through the first static electricity protection unit 200a and the first static electricity protection.
  • Line 201 is connected.
  • the common electrode lead 31 is arranged with a plurality of fifth block bodies 115 on the side close to the display area, in order to facilitate wiring, a plurality of fifth blocks extending from the side of the common electrode lead 31 close to the display area are avoided.
  • the shape 115 causes an unnecessary influence.
  • the first electrostatic protection wire 201 is located on the side of the common electrode lead 11 facing away from the display area 01a.
  • the first electrostatic protection wire 201 and the common electrode lead 31 may have a unitary structure, that is, the first electrostatic protection wire 201 is in the same layer as the common electrode lead 31 and is of the same material.
  • the patterning process is fabricated to form a corresponding overall structure.
  • the first electrostatic protection wire 201 may be connected to the common electrode lead 31 through the third static electricity protection unit 200c; thus, the static charge accumulated on the gate wire lead 11 and the common electrode lead 31 can be accumulated.
  • the static charges can be effectively dispersed, thereby reducing the probability that the corresponding electronic device in the display region 01a is damaged by electrostatic shock.
  • the array substrate 01 further includes a second electrostatic protection line 202 located in the non-display area 01b and extending in the direction in which the gate line 10 extends.
  • the data line 20 is connected to the second electrostatic protection line 202 through the second static electricity protection unit 200b.
  • the data line lead 21 has a large number of trace structures on the side away from the display area (for example, a trace bound to the source drive IC, etc.), in order to facilitate wiring, while avoiding the side of the data line lead 21 away from the display area
  • the trace structure causes an unnecessary influence.
  • the second electrostatic protection line 202 is located on the side of the data line lead 21 near the display area 01a.
  • the second ESD protection line 202 can also be connected to the common electrode lead 31 described above through the fourth ESD protection unit 200d, so that the static charge accumulated on the common electrode lead 31 and the data line 20 can be obtained. Further dispersed evenly.
  • any one of the foregoing first static electricity protection unit 200a, the second static electricity protection unit 200b, the third static electricity protection unit 200c, and the fourth static electricity protection unit 200d provided by the embodiment of the present disclosure may have a structure as shown in FIG.
  • the first transistor T1 and the second transistor T2 are connected to each other: a first connection terminal A and a second connection terminal B; wherein, the source, the gate of the first transistor T1 and the drain of the second transistor T2
  • the first connection terminal A is connected, and the source, the gate of the second transistor T2 and the drain of the first transistor T1 are both connected to the second connection terminal B.
  • connection between the source and the gate of the first transistor T1 may be connected through a conductive pattern in the same layer as the pixel electrode, and the source and the gate of the second transistor T2 may also be connected through a conductive pattern in the same layer as the pixel electrode. .
  • the first connection end A and the second connection end B of any one of the first static electricity protection unit 200a, the second static electricity protection unit 200b, the third static electricity protection unit 200c, and the fourth static electricity protection unit 200d are respectively connected to two Conductors that require electrostatic discharge from each other.
  • the two conductors that need to be electrostatically discharged from each other may be the gate line lead 11 and the first electrostatic protection line 201 in FIG. 7 above, or may be the common electrode lead 31 and the first electrostatic protection line in FIG. 201, which may also be the data line 20 and the second electrostatic protection line 202 in FIG.
  • each of the sub-pixels includes: a pixel electrode PE and a common electrode CE connected to the common electrode line 30, wherein the pixel electrode PE is generally connected to the drain of the thin film transistor (for example, The common electrode CE may be connected to the common electrode line 30 in each sub-pixel (for example, may be connected through a via).
  • the pixel electrode PE includes a first strip-shaped sub-electrode 301
  • the common electrode CE includes a second strip-shaped sub-electrode 302
  • the first strip-shaped sub-electrode 301 is spaced apart from the second strip-shaped sub-electrode 302.
  • the first strip electrode 301 and the second strip sub-electrode 302 are both parallel to the data line 20, that is, the array substrate is an IPS (In Plane Switch) type array substrate.
  • the array substrate 01 is taken as an IPS type, and further description is made on the embodiments of the present disclosure.
  • first strip sub-electrode 301 and the second strip sub-electrode 302 are both parallel to the data line 20 means that the first strip-shaped sub-electrode 301 is parallel to the data line 20 of the corresponding position (ie, the corresponding position along the extending direction of the gate line).
  • the second strip electrode 302 is parallel to the data line 20 at the corresponding position (ie, the corresponding position along the extending direction of the gate line).
  • a transparent conductive material ie, a relatively high transmittance
  • a metal material ie, a relatively low resistivity
  • the data line 20 is linear; as shown in FIG. 12, the data line 20 is not linear, and is, for example, a bent structure.
  • the sub-pixel of the data line using the bent structure illustrated in FIG. 12 can make the display device including the array substrate have a larger viewing angle than the data line using the linear structure illustrated in FIG.
  • the sub-connector 110 in the common electrode line 30 is parallel to the first strip-shaped sub-electrode 301 and the second strip-shaped sub-electrode 302 at the boundary on the side close to the display area 01a. (i.e., parallel to the data line 30), it is possible to ensure that the pixel electrode and the common electrode can form a uniform electric field at a position close to the non-display area 01b, so that the quality of the display picture is better.
  • the sub-connector 110 may be disposed in parallel with the first strip-shaped sub-electrode 301 in the pixel electrode PE at a boundary on the side close to the display region 01a.
  • the pixel is generally driven by dot inversion.
  • the dot-reversal driving method of the pixel electrode in the related art requires loading the data line in a display frame time.
  • the polarity of the electrical signal is inverted N times.
  • the electrical signal loaded on the data line needs to be reversed at a frequency of 60*NHz, thereby enabling High consumption.
  • each sub-pixel P1 of the same column between adjacent two data lines (20 and 20') adjacent sub-pixels (P and P')
  • the pixel electrodes are respectively connected to different ones of the adjacent two data lines (20 and 20'), and each of the pixel electrodes of the same row is connected to a data line on the same side of the sub-pixel of the row.
  • each sub-pixel P is electrically connected to the right data line 20 through a thin film transistor, and the pixel electrode of the sub-pixel P' passes through the thin film transistor and the left side data.
  • the line 20' is electrically connected, and the pixel electrodes of the sub-pixels located in the same row are electrically connected to the data lines located on the same side of each sub-pixel.
  • the electrical signal loaded on the data line is reversed with polarity at a frequency of 60 Hz, so that the effect of dot inversion of the array substrate can be realized, thereby greatly reducing the loading on the data line.
  • the electrical signal is subjected to a frequency of polarity inversion, thereby reducing the power consumption of the display device including the array substrate.
  • the above example is only taken as an example of a display format of a frame rate of 60 Hz.
  • different display formats can be selected as needed.
  • the array substrate 01 further includes: a non-display area 01b, and a display The dummy pixel column P2 adjacent to the sub-pixel column in the region 01a,
  • the dummy pixel column P2 is provided with a dummy data line 20" (which may also be referred to as a dummy data line, that is, a dummy data line) on a side of the dummy pixel column remote from the display area 01a.
  • a dummy data line 20" (which may also be referred to as a dummy data line, that is, a dummy data line) on a side of the dummy pixel column remote from the display area 01a.
  • the dummy pixel P′ in the dummy pixel column P2 includes: the dummy pixel electrode PE′ and the dummy common electrode CE′, and the dummy pixel electrode PE′ in the dummy pixel column P2 and the adjacent data line 20 and the dummy data line 20" is not connected (see the portion shown by S in Fig. 14), and the dummy common electrode CE' in the dummy pixel column P2 is connected to the common electrode line 30.
  • the dummy pixel column is not used for actual display, so that the sub-pixel located at the edge of the display region can also form a uniform electric field, thereby being able to be normally stable. Display the screen to further improve the display.
  • the dummy common electrode CE' in the dummy pixel column P2 is generally in the same layer and the same material as the common electrode in the sub-pixel in the display region 01a, so that the dummy common electrode CE' and the common electrode in the sub-pixel can be fabricated by one patterning process.
  • the dummy pixel electrode PE' in the dummy pixel column P2 is generally in the same layer and the same material as the pixel electrode in the sub-pixel in the display area 01a, so that the dummy pixel electrode PE' and the pixel electrode in the sub-pixel can be fabricated by one patterning process.
  • a thin film transistor may not be disposed in the dummy pixel in the dummy pixel column such that each pixel electrode is not connected to the dummy data line.
  • the dummy data line 20" is parallel to the data line 20 to further ensure that the display device including the array substrate can be normally and stably displayed at a position close to the non-display area 01b.
  • the dummy data line 20" may also be formed in the same layer and the same material as the data line 20 located in the display area 01a, that is, both are formed by the same patterning process.
  • the dummy pixel electrode PE' includes the first dummy.
  • the strip sub-electrode 301 ′, the dummy common electrode CE ′ includes a second dummy strip sub-electrode 302 ′, and the first dummy strip sub-electrode 301 ′ is spaced apart from the second dummy strip sub-electrode 302 ′, and both are connected to the data line 20 parallel.
  • first dummy strip sub-electrode 301 ′ and the second dummy strip sub-electrode 302 ′ are parallel to the data line 20 means that the first dummy strip sub-electrode 301 ′ and the corresponding position (ie, the corresponding position along the extending direction of the gate line)
  • the data lines 20 are parallel;
  • the second dummy strip sub-electrodes 302' are parallel to the data lines 20 of the corresponding positions (i.e., corresponding positions along the extending direction of the gate lines).
  • the data line 20 may be non-linear, for example, a bent structure; and the data line 20 may be linear.
  • the above two or more types of trace structures can be fabricated by one patterning process, as follows:
  • FIG. 15 and FIG. 17 are two schematic diagrams of O-O', A-A', and B in FIG.
  • the cross-sectional views of the -B' and C-C' positions are simply combined. Of course, for the actual cross-sectional structures at various positions, the reference positions may be referred to.
  • the positions of O-O' in FIGS. 15 and 17 show the connection manner of the thin film transistor (TFT) in the sub-pixel P and the pixel electrode PE, and the cross-sectional structure of the position.
  • the thin film transistor TFT is an example of a bottom gate type.
  • a gate electrode 401, a gate insulating layer 402, an active layer 403, a source 404 and a drain 405 pattern layer, a passivation layer 406, and a pixel are sequentially disposed.
  • the electrode PE and the like are described.
  • the embodiment of the present disclosure is not limited thereto.
  • the thin film transistor TFT may also be a top gate type. Actually, the setting may be selected according to requirements, and the specific structure is not described again.
  • the gate line 10 is in the same layer as the common electrode line 30 and the gate line lead 11 , and is of the same material, that is, the gate line 10 and the common electrode line. 30.
  • the gate line lead 11 is formed by the same patterning process.
  • the gate lines 10 at the A-A' position and the gates at the O-O' position are generally formed in a single patterning process.
  • the data line 20 is formed in the same layer as the data line lead 21 and the common electrode lead 31, and the same material, that is, the data line 20, the data line lead 21, and the common electrode lead 31 are formed by the same patterning process.
  • the data line 20 at the source 404, the drain 405 and the B-B' position at the O-O' position is generally fabricated by one patterning process.
  • the data line 20 is in the same layer and the same material as the first electrostatic protection line 201, that is, the data line 20 and the first static electricity.
  • the protective line 201 is formed by the same patterning process.
  • the gate line 10 and the second electrostatic protection line 202 are in the same layer, and the materials, that is, the gate line 10 and the second static protection line 202 pass. The same patterning process was formed.
  • the specific inter-layer relationship can be referred to the foregoing FIG. 15.
  • the dummy data line 20" is connected to the common electrode lead 31, so that the dummy pixel column is not used for actual display when the display is performed, and the static charge accumulated on the trace in the non-display area can play a certain role.
  • the shielding is shielded to further ensure that the display of the display area can be displayed normally and stably.
  • the conductive pattern located in another layer may be connected as the intermediate connection body 120, or may be directly connected.
  • the two are in contact with each other, and the embodiment of the present disclosure does not limit this. In practice, the setting may be selected as needed.
  • the gate line 10 is in the same layer as the common electrode line 30, the common electrode lead 31, and the data line lead 21, and The same material, that is, the gate line 10 and the common electrode line 30, the common electrode lead 31, and the data line lead 21 are all formed by the same patterning process.
  • the data line 20 is formed in the same layer and the same material as the gate line lead 11, that is, the data line 20 and the gate line lead 11 are formed by the same patterning process.
  • the gate line 10 is in the same layer and the same material as the first electrostatic protection line 201 and the second electrostatic protection line 201. That is, the gate line 10 and the first electrostatic protection line 201 and the second electrostatic protection line 201 are both formed by the same patterning process.
  • the dummy data line 20" is connected to the common electrode lead 31, so that the dummy pixel column is not used for actual display when displaying, and the static charge accumulated on the trace in the non-display area A certain shielding isolation function is further ensured that the display screen of the display area can be displayed normally and stably.
  • the conductive pattern located in another layer may be connected as the intermediate connection body 120, or may be directly connected.
  • the two are in contact with each other, and the embodiment of the present disclosure does not limit this. In practice, the setting may be selected as needed.
  • connection portion 100 of the gate line 10 and the gate line lead 11, the connection portion 100' of the data line 20 and the data line lead 21, the common electrode line 30, and the common The connection portion 100" of the electrode lead 31, please continue to participate in FIG. 15 or FIG. 17, the connection portion (100, 100', 100") and the pixel electrode PE in the sub-pixel are in the same layer, and the same material, that is, connected The portions (100, 100', 100") and the pixel electrodes PE in the sub-pixels are each formed by the same patterning process.
  • the “patterning process” may include a photolithography process, or include a photolithography process and an etching process, and may further include printing, inkjet, and the like for forming.
  • a process for patterning a lithography process refers to a process of forming a pattern by using a photoresist, a reticle, an exposure machine, or the like, including a process of film formation, exposure, and development.
  • the respective patterning process can be selected in accordance with each specific structure formed in the embodiments of the present disclosure.
  • the words "connected” or “connected” and the like, including directly connected or connected, or indirectly connected or connected, are not limited to physical connections (for example, through via connections), Includes electrical connections.
  • the above-mentioned gate lines and the conductive patterns in the same layer as the gate lines may be one or more materials such as germanium, aluminum, titanium, magnesium or copper; the data lines and the conductive patterns in the same layer as the data lines may be, for example, germanium.
  • One or more materials of aluminum, titanium, magnesium or copper; the pixel electrode and the conductive pattern in the same layer as the pixel electrode may be a transparent conductive material such as Indium Tin Oxide (abbreviated as ITO), indium One or more of Indium Gallium Zinc Oxide (abbreviated as IGZO) and Indium Zinc Oxide (abbreviated as IZO).
  • ITO Indium Tin Oxide
  • IGZO Indium Gallium Zinc Oxide
  • IZO Indium Zinc Oxide
  • a metal material such as one or more materials selected from the group consisting of ruthenium, aluminum, titanium, magnesium or copper may also be used. limited.
  • the display device 02 includes the aforementioned array substrate 01.
  • the display device has the same advantageous effects as the array substrate provided by the foregoing embodiments. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the array substrate, details are not described herein again.
  • the above display device may further include: a pair of cassette substrates facing the array substrate; and a liquid crystal layer between the two.
  • the pair of the substrate may be a color filter substrate; or, when the array substrate is a COA (color filter on array) type array substrate, that is, a color filter film is formed on the array substrate, in this case, the box is
  • the corresponding substrate may be a cover glass.
  • the above display device may further include a backlight module and a driving circuit portion for providing a backlight.
  • a backlight module and a driving circuit portion for providing a backlight.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., having any display function. Product or part.

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Abstract

一种阵列基板（01）及显示装置（02），该阵列基板（01），包括：显示区（01a）和非显示区（01b）；至少位于显示区（01a）的信号线（S1）；位于非显示区（01b）的信号线引线（S2）；以及位于非显示区（01b）的、用于连接信号线（S1）与信号线引线（S2）的连接部（100a）；其中，信号线（S1）和信号线引线（S2）为两个独立部分。

Description

阵列基板及显示装置
本申请要求于2017年11月27日提交中国专利局、申请号为201721613630.1、申请名称为“一种阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及显示装置。
背景技术
阵列基板作为显示装置中的重要组成部分，一般可分为显示区和非显示区，其中，在非显示区排布有大量的走线，在显示区具有大量的电子器件。
公开内容
本公开一方面提供一种阵列基板，包括：显示区和非显示区；至少位于所述显示区的信号线；位于所述非显示区的信号线引线；以及位于所述非显示区的、用于连接所述信号线与所述信号线引线的连接部；其中，所述信号线和所述信号线引线为两个独立部分。
在本公开一些实施例中，所述连接部与，所述信号线和所述信号线引线中的至少一者位于不同层。
在本公开一些实施例中，所述阵列基板还包括：多条栅线和多条数据线；由多条所述栅线和多条所述数据线横纵交错界定出的呈矩阵排列的多个亚像素。
在本公开一些实施例中，所述信号线包括：所述栅线和所述数据线；所述信号线引线包括：栅线引线和数据线引线；其中，每条所述栅线分别通过不同的所述连接部与不同的所述栅线引线一一对应连接；每条所述数据线分别通过不同的所述连接部与不同的所述数据线引线一一对应连接。
在本公开一些实施例中，所述栅线包括：至少位于所述显示区内的第一线状体以及位于所述非显示区的第一块状体；所述栅线引线包括：位于所述非显示区的栅线引线主体以及位于所述栅线引线主体靠近所述显示区的端部的第二块状体；所述连接部连接所述第一块状体和所述第二块状体。
在本公开一些实施例中，所述数据线包括：至少位于所述显示区内的 第二线状体以及位于所述非显示区的第三块状体；所述数据线引线包括：位于所述非显示区的数据线引线主体以及位于所述数据线引线主体靠近所述显示区的端部的第四块状体；
所述连接部连接所述第三块状体和所述第四块状体。
在本公开一些实施例中，所述信号线还包括公共电极线，所述信号线引线还包括公共电极引线，且所述公共电极线通过所述连接部与所述公共电极引线连接。
在本公开一些实施例中，所述公共电极引线与所述数据线的延伸方向一致，每条所述公共电极线分别通过不同的所述连接部与同一个公共电极引线连接；或者，所述公共电极引线包括：与所述数据线的延伸方向一致的引线本体以及与所述引线本体连接且朝向所述公共电极线方向延伸的多个第五块状体，每个所述第五块状体对应于一个所述连接部，每一条所述公共电极线分别通过不同的所述连接部与对应的所述第五块状体连接。
在本公开一些实施例中，每条所述公共电极线设置于相邻两条栅线之间；所述公共电极线包括：至少位于所述显示区内的第三线状体以及位于所述非显示区内的连接体；其中，所述连接体包括第六块状体，所述连接部与所述第六块状体连接。
在本公开一些实施例中，所述连接体还包括条状的子连接体，所述子连接体条状方向与所述数据线的延伸方向一致，所述第三线状体与所述第六块状体分别位于所述子连接体沿其垂直方向上的两侧，且所述第三线状体、所述第六块状体分别与所述子连接体错开连接。
在本公开一些实施例中，所述第六块状体距离第一栅线的距离小于所述第三线状体距离所述第一栅线的距离，其中，所述第一栅线为：与该第三线状体相邻的两条栅线中，距离该第三线状体较远的一条栅线。
在本公开一些实施例中，所述子连接体在沿所述数据线的延伸方向上的长度小于与该子连接体相邻的两条栅线之间的距离，且所述子连接体在沿所述数据线的延伸方向上的长度大于或等于与该子连接体相邻的两条栅线之间的距离的3/4。
在本公开一些实施例中，所述阵列基板还包括：位于所述非显示区的第一静电保护线、第一静电防护单元；其中，所述第一静电保护线与所述数据线的延伸方向一致，所述栅线引线通过所述第一静电防护单元与所述第一静电保护线连接；所述阵列基板还包括：位于所述非显示区的第二静 电保护线和第二静电防护单元；其中，所述第二静电保护线与所述栅线的延伸方向一致，所述数据线通过所述第二静电防护单元与所述第二静电保护线连接。
在本公开一些实施例中，所述第一静电保护线位于所述公共电极引线背离所述显示区的一侧；所述第二静电保护线位于所述数据线引线靠近所述显示区的一侧。
在本公开一些实施例中，所述第一静电保护线与所述公共电极引线为一体结构；或者，所述阵列基板还包括位于所述非显示区的第三静电防护单元，所述第一静电保护线通过所述第三静电防护单元与所述公共电极引线连接；和/或，所述阵列基板还包括位于所述非显示区的第四静电防护单元，所述第二静电保护线通过所述第四静电防护单元与所述公共电极引线连接。
在本公开一些实施例中，所述第一静电防护单元、所述第二静电防护单元、所述第三静电防护单元以及所述第四静电防护单元中的任一者包括：第一晶体管、第二晶体管、第一连接端以及第二连接端；其中，第一晶体管的源极、栅极与第二晶体管的漏极均连接第一连接端；第二晶体管的源极、栅极与第一晶体管的漏极均连接第二连接端；所述第一连接端、所述第二连接端用于分别连接两个需要互相进行静电释放的导体。
在本公开一些实施例中，所述亚像素包括：像素电极以及与所述公共电极线连接的公共电极；所述像素电极包括第一条状子电极，所述公共电极包括第二条状子电极，所述第一条状子电极与所述第二条状子电极间隔设置，且所述第一条状子电极和所述第二条状子电极均与所述数据线平行；所述子连接体靠近所述显示区一侧的边界与所述第一条状子电极和所述第二条状子电极平行。
在本公开一些实施例中，所述数据线为非直线状。
在本公开一些实施例中，位于相邻两条数据线之间的同一列亚像素中，相邻行的所述亚像素中的各像素电极分别与所述相邻两条数据线中的不同数据线连接；在同一行亚像素中，各像素电极与位于该行的各亚像素同侧的所述数据线连接。
在本公开一些实施例中，所述阵列基板还包括：位于所述非显示区的哑像素列和哑数据线；其中，所述哑像素列与所述显示区中的亚像素列相邻，所述哑数据线设置在该哑像素列的远离所述显示区的一侧；所述哑像 素包括：哑像素电极和哑公共电极；其中，所述哑像素列中的各哑像素电极与，所述哑像素列相邻的所述数据线和所述哑数据线均不连接，所述哑像素列中的各哑公共电极与所述公共电极线均连接。
在本公开一些实施例中，所述哑数据线与所述公共电极引线连接。
在本公开一些实施例中，所述哑数据线与所述数据线平行。
在本公开一些实施例中，所述哑像素电极包括第一哑条状子电极，所述哑公共电极包括第二哑条状子电极，所述第一哑条状子电极与所述第二哑条状子电极间隔设置，且两者均与所述数据线平行。
在本公开一些实施例中，所述连接部与，所述信号线和所述信号线引线中的至少一者位于不同层，包括：所述连接部与，所述信号线和所述信号线引线不同层，且所述信号线和所述信号线引线同层；其中，所述连接部分别通过第一过孔、第二过孔与所述信号线、所述信号线引线连接；或者，所述连接部与所述信号线引线同层，所述连接部与所述信号线不同层；其中，所述连接部与所述信号线引线直接连接，所述连接部通过第一过孔与所述信号线连接；或者，所述连接部与所述信号线同层，所述连接部与所述信号线引线不同层；其中，所述连接部与所述信号线直接连接，所述连接部通过第二过孔与所述信号线引线连接。
在本公开一些实施例中，所述连接部与所述亚像素中的各像素电极同层、且同材料。
在本公开一些实施例中，所述栅线与所述公共电极线、所述栅线引线均同层、且同材料；和/或，所述数据线与所述数据线引线、所述公共电极引线均同层、且同材料。
在本公开一些实施例中，所述栅线与所述公共电极线、所述栅线引线均同层、且同材料；和/或，所述数据线与所述数据线引线、所述公共电极引线均同层、且同材料。
在本公开一些实施例中，所述数据线与所述第一静电保护线同层、且同材料；和/或，所述栅线与所述第二静电保护线同层、且同材料。
在本公开一些实施例中，所述栅线与所述公共电极线、所述公共电极引线、所述数据线引线均同层、且同材料；和/或，所述数据线与所述栅线引线同层、且同材料。
在本公开一些实施例中，所述栅线与所述公共电极线、所述公共电极引线、所述数据线引线均同层、且同材料；和/或，所述数据线与所述栅线 引线同层、且同材料；和/或，所述栅线与所述第一静电保护线、所述第二静电保护线同层、且同材料。
本公开另一方面提供一种显示装置，包括上述任一项所述的阵列基板。
附图说明
为了更清楚地说明本公开实施例和相关技术中的技术方案，下面将对实施例和相关技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一些实施例提供的一种阵列基板的结构示意图；
图2为本公开一些实施例提供的再一种阵列基板的结构示意图；
图3为本公开一些实施例提供的另一种阵列基板的结构示意图；
图4为本公开一些实施例提供的又一种阵列基板的结构示意图；
图5为本公开一些实施例提供的又一种阵列基板的结构示意图；
图6为本公开一些实施例提供的又一种阵列基板的结构示意图；
图7为本公开一些实施例提供的又一种阵列基板的结构示意图；
图8为本公开一些实施例提供的又一种阵列基板的结构示意图；
图9为本公开一些实施例提供的又一种阵列基板的结构示意图；
图10为本公开一些实施例提供的一种阵列基板中的静电防护单元的组成示意图；
图11为本公开一些实施例提供的又一种阵列基板的结构示意图；
图12为本公开一些实施例提供的又一种阵列基板的结构示意图；
图13为本公开一些实施例提供的又一种阵列基板的结构示意图；
图14为本公开一些实施例提供的又一种阵列基板的结构示意图；
图15为图9中O-O’、A-A’、B-B’以及C-C’方向的剖面结构的一种组合示意图；
图16为图14沿D-D’方向的一种剖面结构示意图；
图17为图9中O-O’、A-A’、B-B’以及C-C’方向的剖面结构的另一种组合示意图；
图18为图14沿D-D’方向的另一种剖面结构示意图；
图19为本公开一些实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在相关技术中，由于在阵列基板的制作过程中，非显示区中的走线容易积累大量的静电荷，当这些静电荷转移至显示区中时，会对显示区中的电子器件造成威胁，容易导致显示区中的电子器件受到静电冲击而造成损坏，影响阵列基板的良率。
本公开实施例一方面提供一种阵列基板，如图1至图3所示，该阵列基板01包括：显示区01a和非显示区01b；至少位于显示区01a的信号线S1、位于非显示区01b的信号线引线S2以及位于非显示区01b的、用于连接上述信号线S1与信号线引线S2的连接部100a；其中，信号线S1和信号线引线S2为两个独立部分。
上述信号线S1和信号线引线S2为两个独立部分是指，信号线S1和信号线引线S2两者之间不接触，也即是说，信号线S1和信号线引线S2在阵列基板01中的用于放置上述各结构的衬底基板上的正投影不接触。
这样一来，即使位于非显示区01b中的信号线引线S2上积累有大量的静电荷，由于本公开实施例中将信号线S1和信号线引线S2设置为两个独立部分(也即断开设置)，那么在信号线S1和信号线引线S2通过上述连接部100a连接之前，位于非显示区01b中的信号线引线S2上积累的大量的静电荷不会转移至显示区01a中相应信号线S1上，从而降低了显示区01a中的与上述信号线S1电性连通的电子器件因静电冲击而发生损坏的几率，进而提高了产品的良率。
示例的，在本公开实施例提供的上述阵列基板01中，连接部100a与，信号线S1和信号线引线S2中的至少一者位于不同层。
其中，信号线S1和信号线引线S2可以位于同层，即二者通过一次构图工艺制作形成；或者，信号线S1和信号线引线S2也可以位于不同层，即二者需要通过两次构图工艺制作形成，本实公开实施例对此不作限定，可根据阵列基板的类型、信号线的类型选择设置的方式，只要保证连接部100a、信号线S1以及信号线引线S2这三者不在同一层，不是直接连接在 一起的即可。
请参阅图1，连接部100a与，信号线S1和信号线引线S2中的至少一者位于不同层的方式，例如可以为：
连接部100a与，信号线S1和信号线引线S2不同层，且信号线S1和信号线引线S2同层；其中，连接部100a分别通过第一过孔V1、第二过孔V2与信号线S1、信号线引线S2连接。
由于连接部100a与，信号线S1和信号线引线S2不同层，因此，上述阵列基板01中当然还包括有位于连接部100a与，信号线S1和信号线引线S2之间的绝缘层(一层或多层)，上述第一过孔V1、第二过孔V2即为开设在该绝缘层的贯穿部分，以使得连接部100a能够分别通过第一过孔V1、第二过孔V2与信号线S1、信号线引线S2连接。
绝缘层的具体结构可沿用相关设置，此处不再赘述。
请参阅图2，连接部100a与，信号线S1和信号线引线S2中的至少一者位于不同层的方式，例如还可以为：
连接部100a与信号线引线S2同层，连接部100a与信号线S1不同层；其中，连接部100a与信号线引线S2直接连接，连接部100a通过第一过孔V1与信号线S1连接。
由于连接部100a与信号线引线S2同层，而与信号线S1不同层，因此，上述阵列基板01中当然还包括有位于连接部100a、信号线引线S2与信号线S1之间的绝缘层(一层或多层)，上述第一过孔V1即为开设在该绝缘层的贯穿部分，以使得连接部100a能够通过第一过孔V1与信号线S1连接。
请参阅图3，连接部100a与，信号线S1和信号线引线S2中的至少一者位于不同层的方式，例如又可以为：
连接部100a与信号线S1同层，连接部100a与信号线引线S2不同层；其中，连接部100a与信号线S1直接连接，连接部100a通过第二过孔V2与信号线引线S2连接。
由于连接部100a与信号线S1同层，而与信号线引线S2不同层，因此，上述阵列基板01中当然还包括有位于接部100a、信号线S1同层与信号线引线S2之间的绝缘层(一层或多层)，上述第二过孔V2即为开设在该绝缘层的贯穿部分，以使得连接部100a能够通过第二过孔V2与信号线引线S2连接。
本公开实施例还提供一种阵列基板，如图4所示，该阵列基板01还包括：多条栅线10和多条数据线20，多条栅线10和多条数据线20横纵交错并界定出呈矩阵排列的多个亚像素P。
这样，上述显示区01a即为，所有亚像素P的集合所在的区域；上述非显示区01b一般位于显示区01a的四周，即包围显示区。
可以理解的是，以上图4仅是通过阵列基板01中的局部结构，对显示区01a和非显示区01b进行示意，显示区01a的四周均为非显示区01b，图4中并未完全示出。
由于阵列基板01中包括有位于显示区01a和非显示区01b的大量走线，例如，位于显示区的栅线、数据线、公共电极线，以及位于非显示区中与栅线连接的栅线引线、与数据线连接的数据线引线、与公共电极线连接的公共电极引线等等。
基于此，请继续参阅图4，上述信号线S1和信号线引线S2，可以分别为栅线10和栅线引线11；也可以分别为数据线20和数据线引线21；还可以分别为公共电极线30和公共电极引线31；当然，以上组合仅为示意，信号线S1和信号线引线S2还可以分别是阵列基板01中的其他位于显示区01a和非显示区01b且连接的走线结构，本公开实施例对此不作限定，实际中可以选择上述一组或多组走线结构设置为上述的信号线和信号线引线的结构。以下实施例中均是以信号线和信号线引线分别包括：栅线和栅线引线、数据线和数据线引线、公共电极线和公共电极引线中的一组或者多组为例，对本公开实施例做进一步的说明。
以下通过各具体实施例对上述信号线S1和信号线引线S2的具体设置方式做进一步的说明。
请继续参阅图4所示，信号线包括栅线10，信号线引线包括栅线引线11；信号线还包括数据线20，信号线引线还包括数据线引线21。
示例的，每条栅线10分别通过不同的连接部100与不同的栅线引线11一一对应连接。
并且，为了易于布线，栅线10和栅线引线11的延伸方向一致，且该栅线引线11靠近显示区01a的一端通过连接部100与栅线10连接，另一端用于与栅极驱动IC的端子连接或者与阵列基板行驱动电路(Gate Driver on Array，缩写为GOA)的输出端连接。
在此基础上，由于连接部100与，栅线10和栅线引线11位于不同层， 因此，连接部100一般需要通过过孔与栅线10和栅线引线11连接，当然本公开实施例并不限制于此，也可以根据阵列基板的具体结构，将连接部100设置为与栅线10或栅线引线11直接接触连接。
示例的，为了保证连接部100与栅线10和栅线引线11之间能够有效地连接，以降低接触电阻，请继续参阅图4所示，栅线10包括：至少位于显示区01内的第一线状体101以及位于非显示区02的第一块状体111；栅线引线11包括：栅线引线主体11a以及位于栅线引线主体11a靠近显示区01a的端部的第二块状体112；连接部100连接第一块状体111和所述第二块状体112。
对于信号线包括数据线20，信号线引线还包括数据线引线21的情况，请继续参阅图4所示，每条数据线20分别通过不同的连接部100’与不同的数据线引线21一一对应连接。
并且，为了易于布线，数据线20和数据线引线21的延伸方向一致，且该数据线引线21靠近显示区01a的一端与通过连接部100’与数据线20连接，该数据线引线21相对的另一端用于与源极驱动IC的端子连接。
在此基础上，由于连接部100’与数据线20和数据线引线21位于不同层，因此，连接部100’一般需要通过过孔与数据线20和数据线引线21连接，当然本公开实施例并不限制于此，也可以根据阵列基板的具体结构，将连接部100’设置为与数据线20或数据线引线21直接接触连接。
示例的，为了保证连接部100’与数据线20和数据线引线21能够有效地连接，以降低接触电阻，本公开实施例优选的，请继续参阅图4所示，数据线20包括：至少位于显示区01a内的第二线状体102以及位于非显示区01b的第三块状体113；数据线引线21包括：位于非显示区01b的数据线引线主体21a以及位于数据线引线主体21a靠近显示区01a的端部的第四块状体114；连接部100’连接第三块状体113和第四块状体114。
请继续参阅图4所示，上述信号线还包括公共电极线30，信号线引线包括公共电极引线31，公共电极线30通过连接部100”与公共电极引线31连接。
在此基础上，由于连接部100”与，公共电极线30和公共电极引线31位于不同层，因此，连接部100”一般需要通过过孔与公共电极线30和公共电极引线31连接，当然本公开实施例并不限制于此，也可以根据阵列基板的具体结构，将连接部100”设置为与公共电极线30或公共电极 引线31直接接触连接。
这里，上述公共电极线30通过连接部100”与公共电极引线31连接的方式示例的可以是：参阅图4所示，公共电极线30与栅线10的延伸方向一致，每条公共电极线30分别通过不同的连接部100”与公共电极引线31连接。
当然，也可以是所有的公共电极线30通过同一连接部100”与公共电极引线31连接，即在不影响其他走线结构的情况下，将图4中对应连接公共电极线30和公共电极引线31的多个连接部100”设置为连接在一起的一体结构，本公开实施例对此不作限定。
考虑到非显示区01b布置的结构较多、且较为复杂，为避免多个连接部100”连接在一起的一体结构对其他走线造成不必要的影响，本公开示例的，每条公共电极线30分别通过不同的连接部100”与公共电极引线31连接。
对于公共电极引线31而言，可以参阅上述图4所示，该公共电极引线31包括：与数据线20的延伸方向一致的引线本体311以及与引线本体311连接且朝向公共电极线30方向延伸的多个第五块状体115；每个第五块状体115对应于一个连接部100”，每条公共电极线30分别通过不同的连接部100”与对应的第五块状体115连接，从而保证连接部100”与公共电极引线31之间的有效连接。
示例的，该公共电极引线可以仅包括图4中示意出的引线本体311的部分，即：每条公共电极线30通过连接部100”与该公共电极引线31连接，本公开实施例对此不作限定。
对于公共电极线30而言，一般包括：至少位于显示区01a内的第三线状体103以及位于非显示区01b内的连接体U；其中，该公共电极线30对应设置于相邻两条栅线10之间的位置，一般的，第三线状体103与栅线10的延伸方向一致。
在此情况下，为了保证连接部100”与公共电极线30之间同样能够有效地连接，请继续参阅图4所示，该连接体U包括第六块状体116，连接部100”与第六块状体116连接。
可以理解的是，该第六块状体116一般设置于公共电极线30靠近公共电极引线31一侧的端部。
在此基础上，由于公共电极线30中的第三线状体103与栅线10的延 伸方向一致，两者在端部均分别需要与公共电极引线31和栅线引线11连接，且在连接位置处一般均为块状体结构，这样会导致排线密集，容易使得各引线之间发生短路，造成信号传输不良。
为了解决上述技术问题，本公开实施例进一步提供以下结构，如图5所示，该连接体U除了包括上述的第六块状体116以外，还包括条状的子连接体110，该子连接体110的条状方向与数据线20的延伸方向一致，第三线状体103与第六块状体116分别位于该子连接体110沿其垂直方向上的两侧，且两者与子连接体110错开(即错位交叉)连接。
其中，第六块状体116距离第一栅线的距离D1小于第三线状体103距离第一栅线的距离D2，其中，第一栅线为：与该第三线状体103相邻的两条栅线10中距离该第三线状体103较远的一条栅线10。
可以理解的是，由于第六块状体116是连接在子连接体110上的，因此，在沿数据线20的延伸方向，为便于布线，第六块状体116的尺寸应小于子连接体110在该方向上的尺寸。
以下实施例均是以公共电极线30包括子连接体110为例对本公开实施例做进一步的说明。
上述第三线状体103与第六块状体116位于子连接体110沿其垂直方向上的两侧，且两者与子连接体110错位交叉连接是指，第六块状体116与子连接体110的连接位置，不在第三线状体103的延长线上，也即通过设置子连接体110能够使得第六块状体116能够向靠近第一栅线的方向偏离，并与子连接体110连接，从而易于排线，避免线路之间发生短路。
示例的，请继续参阅图5所示，子连接体110在沿数据线20的延伸方向上的长度H1小于与该子连接体110相邻的两条栅线10之间的距离H2，且大于或等于与该子连接体110相邻的两条栅线10之间的距离H2的3/4，也即，H2＞H1≥(3/4)*H2。
这样一来，在实现易于布线的基础上，上述设置方式还能使得子连接体110对位于非显示区01b中的走线结构中的静电荷起到一定的屏蔽作用，从而更进一步的避免静电荷对显示区01a内的结构造成不良影响。
可以理解的是，上述第一块状体111、第二块状体112、第三块状体111、第四块状体112、第五块状体115、第六块状体116的长度(即沿栅线的延伸方向上的相应尺寸)和宽度(即沿数据线的延伸方向的相应尺寸)一般均大于第一线状体101、第二线状体102、第三线状体103的线状宽度， 以保证各块状体与相应连接部之间的有效连接。
在此基础上，为了保证栅线引线11上积累的静电荷能够得到均匀分散，以避免对显示区01a中的栅线10以及与栅线10连接的例如薄膜晶体管等电子器件造成静电冲击，如图6所示，该阵列基板01还包括位于非显示区01b、且与数据线20的延伸方向一致的第一静电保护线201，栅线引线11通过第一静电防护单元200a与第一静电保护线201连接。
这样一来，当栅线引线11上积累的静电荷到达一定程度时，能够通过第一静电防护单元200a将静电荷分散至第一静电保护线201，从而降低了显示区01a中的相应电子器件因受到静电冲击而发生损坏的几率。
这里，由于公共电极引线31在靠近显示区的一侧排布有多个第五块状体115，为了易于布线，避免对公共电极引线31靠近显示区的一侧延伸出的多个第五块状体115造成不必要的影响，请继续参阅图6所示，第一静电保护线201位于公共电极引线11背离显示区01a一侧。
在此基础上，如图7所示，第一静电保护线201与公共电极引线31可以为一体结构，即：第一静电保护线201与公共电极引线31同层、且同材料，通过同一次构图工艺制作形成相应的整体结构。
也可以如图8所示，第一静电保护线201通过第三静电防护单元200c与公共电极引线31连接；这样一来，能够使得栅线引线11上积累的静电荷和公共电极引线31上积累的静电荷均能够得到有效地分散，进而降低显示区01a中的相应电子器件因受到静电冲击而发生损坏的几率。
为了保证数据线引线21上积累的静电荷也能够得到均匀分散，以避免对显示区01a中的数据线以及与数据线连接的例如薄膜晶体管等电子器件造成静电冲击，如图9所示，该阵列基板01还包括位于非显示区01b、且与栅线10延伸方向一致的第二静电保护线202，数据线20通过第二静电防护单元200b与第二静电保护线202连接。
这样一来，当数据线引线21上积累的静电荷到达一定程度时，能够通过第二静电防护单元200b将静电荷分散至第二静电保护线202，从而降低了显示区01a中的相应电子器件因受到静电冲击而发生损坏的几率。
由于数据线引线21在远离显示区的一侧具有大量的走线结构(例如与源极驱动IC绑定的走线等)，为了易于布线，同时避免对数据线引线21远离显示区的一侧的走线结构造成不必要的影响，请继续参阅图9所示，第二静电保护线202位于数据线引线21靠近显示区01a的一侧。
请继续参阅图9所示，第二静电保护线202还可以通过第四静电防护单元200d与上述的公共电极引线31连接，从而可以使得公共电极引线31和数据线20上积累的静电荷能够得到进一步均匀地分散。
对于本公开实施例提供的上述第一静电防护单元200a、第二静电防护单元200b、第三静电防护单元200c以及第四静电防护单元200d中的任一者，其结构均可以如图10所示，包括：第一晶体管T1和第二晶体管T2，两个连接端：第一连接端A和第二连接端B；其中，第一晶体管T1的源极、栅极与第二晶体管T2的漏极均连接第一连接端A，第二晶体管T2的源极、栅极与第一晶体管T1的漏极均连接第二连接端B。
其中，第一晶体管T1的源极、栅极之间的连接可以通过与像素电极同层的导电图案连接，第二晶体管T2的源极、栅极也可以通过与像素电极同层的导电图案连接。
上述第一静电防护单元200a、第二静电防护单元200b、第三静电防护单元200c以及第四静电防护单元200d中的任一者中的第一连接端A和第二连接端B分别连接两个需要互相进行静电释放的导体。
示例的，该两个需要互相进行静电释放的导体，可以是上述图7中的栅线引线11和第一静电保护线201，也可以是图8中的公共电极引线31和第一静电保护线201，还可以是图9中的数据线20与第二静电保护线202等等。
更进一步的，如图11或图12所示，每个亚像素均包括：像素电极PE以及与公共电极线30连接的公共电极CE，其中，像素电极PE一般与薄膜晶体管的漏极连接(例如，可以是通过过孔连接)，公共电极CE在每个亚像素中均与公共电极线30连接(例如，可以是通过过孔连接)。
其中，作为本公开实施例的一种示例，像素电极PE包括第一条状子电极301，公共电极CE包括第二条状子电极302，且第一条状子电极301与第二条状子电极302间隔设置，同时，第一条状子电极301和第二条状子电极302均与数据线20平行，即：该阵列基板为IPS(In Plane Switch，横向电场效应)型阵列基板。
以下实施例均是以该阵列基板01为IPS型为例，对本公开实施例进行的进一步的说明。
上述第一条状子电极301和第二条状子电极302均与数据线20平行是指，第一条状子电极301与对应位置(即沿栅线的延伸方向上的对应位置) 的数据线20平行；第二条状子电极302与对应位置(即沿栅线的延伸方向上的对应位置)的数据线20平行。
在此情况下，对于像素电极和公共电极而言，可以采用透明导电材料(即透过率相对较大)，也可以采用金属材料(即电阻率相对较小)，本公开实施例对此不作限定。
对于数据线20而言，可以参阅图11所示，数据线20为直线状；也可以参阅图12所示，数据线20非直线状，例如为弯折结构。
这里，相比图11示意出的采用直线结构的数据线而言，图12示意出的采用弯折结构的数据线的亚像素能够使得包括该阵列基板的显示装置具有更大的可视角度。
在此基础上，请继续参阅图11和图12，公共电极线30中的子连接体110在靠近显示区01a一侧的边界与第一条状子电极301和所述第二条状子电极302平行(也即，与数据线30平行)，从而能够保证像素电极与公共电极在靠近非显示区01b的位置也能够形成均匀的电场，使得显示画面的质量更好。
上述仅是以IPS型阵列基板为例进行说明的，本公开实施例并不限制于此，对于ADS(Advanced-Super Dimensional Switching，高级超维场开关)型阵列基板同样适用，例如，参考上述图11和图12中的结构，可以设置子连接体110在靠近显示区01a一侧的边界与像素电极PE中的第一条状子电极301平行即可。
在此基础上，在阵列基板应用于实际的显示时，为了解决由于像素电极上加载正向电压和负向电压不对称而导致的相应问题，相关技术中，一般采用点反转的方式驱动像素电极，以该阵列基板上设置有N行栅线为例，对于一帧显示画面而言，相关技术中采用点反转的方式驱动像素电极则需要在一显示帧的时间内，数据线上加载的电信号的极性反转N次，这样一来，以60Hz帧频的显示格式为例，数据线上加载的电信号则以需要以60*NHz的频率进行极性反转，从而使得能耗较高。
为了解决上述技术问题，如图13所示，位于相邻两条数据线(20和20’)之间的同一列的各亚像素P1中，相邻行的亚像素(P和P’)的像素电极分别与相邻两条数据线(20和20’)中的不同数据线连接，同一行的亚像素中的各像素电极与位于该行的亚像素同侧的数据线连接。
例如，请继续参阅图13，同一列亚像素P1中，各亚像素P的像素电 极通过薄膜晶体管与右侧的数据线20电性连接，亚像素P’的像素电极通过薄膜晶体管与左侧数据线20’电性连接，位于同一行的亚像素的像素电极与位于各亚像素同侧的数据线电性连接。
此处仅是示意的说明，相邻行的亚像素(P和P’)的像素电极分别与相邻两条数据线(20和20’)中的不同数据线连接的方式可以相互调换，只要保证相邻行的亚像素的像素电极分别与相邻两条数据线中的不同数据线连接即可。
这样一来，同样对于60Hz帧频的显示格式，数据线上加载的电信号则以60Hz的频率进行极性反转，即可实现阵列基板点反转的效果，从而大幅降低了数据线上加载的电信号进行极性反转的频率，进而使得包括该阵列基板的显示装置的能耗降低。
当然上述示例仅是以60Hz帧频的显示格式为例进行说明的，包括该阵列基板的显示装置在进行显示时，可以根据需要选择不同的显示格式。
更进一步的，为了保证包括上述阵列基板的显示装置在靠近非显示区的位置能够正常稳定的进行画面显示，如图14所示，该阵列基板01还包括：位于非显示区01b、且与显示区01a中亚像素列相邻的哑像素列P2，
该哑像素列P2在该哑像素列的远离显示区01a的一侧设置有哑数据线20”(也可以称为虚拟数据线，即Dummy Data Line)。
其中，该哑像素列P2中的哑像素P”包括：哑像素电极PE’和哑公共电极CE’，且哑像素列P2中的哑像素电极PE’与相邻的数据线20和哑数据线20”均不连接(可参见图14中的S示出部分)，哑像素列P2中哑公共电极CE’与公共电极线30连接。
这样一来，在包括有上述阵列基板的显示装置在进行显示时，该哑像素列不用于实际的显示，是为了保证位于显示区边缘的亚像素也能够形成均匀的电场，从而能够正常稳定的显示画面，从而进一步提高显示效果。
上述哑像素列P2中哑公共电极CE’一般与显示区01a中亚像素中的公共电极同层、且同材料，这样可以通过一次构图工艺制作哑公共电极CE’与亚像素中的公共电极。
哑像素列P2中的哑像素电极PE’一般与显示区01a中亚像素中的像素电极同层、且同材料，这样可以通过一次构图工艺制作哑像素电极PE’与亚像素中的像素电极。
哑像素列中的哑像素中可以不设置薄膜晶体管，以使得各像素电极与 哑数据线不连接。
请继续参阅图14所示，哑数据线20”与数据线20平行，以进一步保证包括上述阵列基板的显示装置在靠近非显示区01b的位置也能够正常稳定的显示画面。
为了简化工艺，哑数据线20”也可以与位于显示区01a中的数据线20同层、且同材料，即两者通过同一次构图工艺形成。
另外，为了能够通过该哑像素列进一步的对非显示区01b中的走线上积累的静电荷起到一定的屏蔽隔离作用，请继续参阅图14所示，哑像素电极PE’包括第一哑条状子电极301’，哑公共电极CE’包括第二哑条状子电极302’，并且第一哑条状子电极301’与第二哑条状子电极302’间隔设置，且两者均与数据线20平行。
上述第一哑条状子电极301’和第二哑条状子电极302’均与数据线20平行是指，第一哑条状子电极301’与对应位置(即沿栅线的延伸方向上的对应位置)的数据线20平行；第二哑条状子电极302’与对应位置(即沿栅线的延伸方向上的对应位置)的数据线20平行。
在上述图13和图14中，对于数据线20而言，数据线20可以为非直线状，例如为弯折结构；数据线20也可以为直线状。
在此基础上，为了简化阵列基板的制备工艺，以降低制作成本，可以将上述的两种或者两种以上的走线结构通过一次构图工艺进行制作，具体如下：
以下结合图9和图15以及图17对上述栅线10、栅线引线11、数据线20、数据线引线21、公共电极线30、公共电极引线31、第一静电保护线201、第二静电保护线102的层间关系做进一步的说明；其中，为了更好对各层间关系进行说明，图15和图17为示意的两种对图9中O-O’、A-A’、B-B’、C-C’位置的剖面图简单的组合在一起的示意图，当然，对于实际各位置的剖面结构，对应参考各位置即可。
另外，图15和图17中O-O’位置示出了亚像素P中薄膜晶体管(Thin Film Transistor，缩写为TFT)与像素电极PE的连接方式以及该位置的剖面结构，此处仅是以该薄膜晶体管TFT为底栅型为例，在衬底基板400上依次为栅极401、栅极绝缘层402、有源层403、源极404和漏极405图案层、钝化层406、像素电极PE等进行说明的，本公开实施例并不限制于此，该薄膜晶体管TFT也可以为顶栅型，实际中可以根据需要选择设置，具体 结构不再赘述。
作为本公开实施例的一种示例，请结合图9进一步参阅图15所示，栅线10与公共电极线30、栅线引线11同层、且同材料，即：栅线10与公共电极线30、栅线引线11通过同一次构图工艺制作形成。
其中，A-A’位置的栅线10与O-O’位置的栅极一般为一次构图工艺制作形成的一体结构。
数据线20与数据线引线21、公共电极引线31同层、且同材料，即：数据线20与数据线引线21、公共电极引线31通过同一次构图工艺制作形成。
其中，O-O’位置的源极404、漏极405与B-B’位置的数据线20一般为一次构图工艺制作而成。
在此基础上，请继续参阅图15中C-C’和B-B’位置所示，数据线20与第一静电保护线201同层、且同材料，即：数据线20与第一静电保护线201通过同一次构图工艺制作形成。
同时，请继续参阅图15中A-A’和B-B’位置所示，栅线10和第二静电保护线202同层、且材料，即：栅线10和第二静电保护线202通过同一次构图工艺制作形成。
在此基础上，对于图14中示意出的阵列基板，如图16(该图为上述图14沿D-D’位置的一种剖面图，具体层间关系可参考前述的图15)所示，哑数据线20”与公共电极引线31连接，这样一来，在进行显示时，该哑像素列不用于实际的显示，并且对非显示区中走线上积累的静电荷能够起到一定的屏蔽隔离作用，从而进一步保证显示区的显示画面能够正常稳定的显示。
其中，对于哑数据线20”与公共电极引线31连接方式，可以参阅图16所示，采用位于其他层(例如像素电极层)的导电图案作为中间连接体120的方式进行连接，也可以直接将两者进行接触连接，本公开实施例对此不作限定，实际中可以根据需要选择设置。
作为本公开实施例的另一种示例，如图17所示(请结合上述图9参阅图17)，栅线10与公共电极线30、公共电极引线31、数据线引线21均同层、且同材料，即：栅线10与公共电极线30、公共电极引线31、数据线引线21均通过同一次构图工艺制作形成。
请继续参阅图17所示，数据线20与栅线引线11同层、且同材料，即： 数据线20与栅线引线11通过同一次构图工艺制作形成。
进一步的，结合图17中A-A’、B-B’以及C-C’位置所示，栅线10与第一静电保护线201、第二静电保护线201均同层、且同材料，即：栅线10与第一静电保护线201、第二静电保护线201均通过同一次构图工艺制作形成。
在此基础上，对于上述图14中示出的阵列基板而言，如图18(该图为上述图14沿D-D’位置的另一种剖面图，其中层间关系可参考前述的图17)所示，哑数据线20”与公共电极引线31连接，这样一来，在进行显示时，该哑像素列不用于实际的显示，并且对非显示区中走线上积累的静电荷起到一定的屏蔽隔离作用，进一步保证显示区的显示画面能够正常稳定的显示。
其中，对于哑数据线20”与公共电极引线31连接方式，可以参阅图18所示，采用位于其他层(例如像素电极层)的导电图案作为中间连接体120的方式进行连接，也可以直接将两者进行接触连接，本公开实施例对此不作限定，实际中可以根据需要选择设置。
另外，对于前述各实施例中提供的连接部而言，例如，栅线10和栅线引线11的连接部100、数据线20和数据线引线21的连接部100’，公共电极线30和公共电极引线31的连接部100”，请继续参与图15或图17所示，连接部(100、100’、100”)与亚像素中的像素电极PE均同层、且同材料，也即连接部(100、100’、100”)与亚像素中的像素电极PE均通过同一次构图工艺形成。
需要说明的是，在本公开实施例中，所谓“构图工艺”，可指包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时进一步还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本公开实施例中所形成的各具体结构选择相应的构图工艺。
本公开实施例中，“连接”或者“相连”等类似的词语，包括直接连接或相连的方式，或者间接连接或相连的方式，并且不限定于物理连接(例如通过过孔连接)，也可以包括电性连接。
另外，上述栅线以及与栅线同层的导电图案可以采用例如钕、铝、钛、镁或铜中的一种或者多种材料；数据线以及与数据线同层的导电图案可以采用例如钕、铝、钛、镁或铜中的一种或者多种材料；像素电极以及与像 素电极同层的导电图案可以采用透明导电材料，例如铟锡氧化物(Indium Tin Oxide，缩写为ITO)、铟镓锌氧化物(Indium Gallium Zinc Oxide，缩写为IGZO)、铟锌氧化物(Indium Zinc Oxide，缩写为IZO)中的一种或多种。
对于像素电极而言，根据阵列基板的不同类型(例如IPS型)，也可以采用金属材料，例如，钕、铝、钛、镁或铜中的一种或者多种材料，本公开实施例对比不作限定。
本公开实施例另一方面还提供一种显示装置，如图19所示，该显示装置02包括前述的阵列基板01。
该显示装置具有与前述实施例提供的阵列基板相同的有益效果。由于前述实施例已经对阵列基板的结构和有益效果进行了详细的描述，此处不再赘述。
上述显示装置还可包括：与该阵列基板对盒的对盒基板；以及位于二者之间的液晶层。
示例的，该对盒基板可以为彩膜基板；或者，当该阵列基板为COA(color filter on array)型阵列基板，即阵列基板上制作有彩色滤色膜时，在此情况下，对盒基板相应的可以为盖板玻璃。
上述显示装置还可包括提供背光的背光模组、驱动电路部分，具体结构可参见相关技术，本此处不再赘述。
需要说明的是，在本公开实施例中，显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (31)

  1. 一种阵列基板，包括：
    显示区和非显示区；
    至少位于所述显示区的信号线；
    位于所述非显示区的信号线引线；
    以及位于所述非显示区的、用于连接所述信号线与所述信号线引线的连接部；
    其中，所述信号线和所述信号线引线为两个独立部分。
  2. 根据权利要求1所述的阵列基板，其中，所述连接部与，所述信号线和所述信号线引线中的至少一者位于不同层。
  3. 根据权利要求1或2所述的阵列基板，其中，所述阵列基板还包括：
    多条栅线和多条数据线；
    由多条所述栅线和多条所述数据线横纵交错界定出的呈矩阵排列的多个亚像素。
  4. 根据权利要求3所述的阵列基板，其中，所述信号线包括：所述栅线和所述数据线；所述信号线引线包括：栅线引线和数据线引线；
    其中，每条所述栅线分别通过不同的所述连接部与不同的所述栅线引线一一对应连接；
    每条所述数据线分别通过不同的所述连接部与不同的所述数据线引线一一对应连接。
  5. 根据权利要求3所述的阵列基板，其中，
    所述栅线包括：至少位于所述显示区内的第一线状体以及位于所述非显示区的第一块状体；
    所述栅线引线包括：位于所述非显示区的栅线引线主体以及位于所述栅线引线主体靠近所述显示区的端部的第二块状体；
    所述连接部连接所述第一块状体和所述第二块状体。
  6. 根据权利要求3所述的阵列基板，其中，
    所述数据线包括：至少位于所述显示区内的第二线状体以及位于所述非显示区的第三块状体；
    所述数据线引线包括：位于所述非显示区的数据线引线主体以及位于所述数据线引线主体靠近所述显示区的端部的第四块状体；
    所述连接部连接所述第三块状体和所述第四块状体。
  7. 根据权利要求4所述的阵列基板，其中，所述信号线还包括公共电极线，所述信号线引线还包括公共电极引线，且所述公共电极线通过所述连接部与所述公共电极引线连接。
  8. 根据权利要求7所述的阵列基板，其中，
    所述公共电极引线与所述数据线的延伸方向一致，每条所述公共电极线分别通过不同的所述连接部与同一个公共电极引线连接；
    或者，
    所述公共电极引线包括：与所述数据线的延伸方向一致的引线本体以及与所述引线本体连接且朝向所述公共电极线方向延伸的多个第五块状体，每个所述第五块状体对应于一个所述连接部，每一条所述公共电极线分别通过不同的所述连接部与对应的所述第五块状体连接。
  9. 根据权利要求7所述的阵列基板，其中，每条所述公共电极线设置于相邻两条栅线之间；
    所述公共电极线包括：至少位于所述显示区内的第三线状体以及位于所述非显示区内的连接体；其中，所述连接体包括第六块状体，所述连接部与所述第六块状体连接。
  10. 根据权利要求9所述的阵列基板，其中，所述连接体还包括条状的子连接体，所述子连接体条状方向与所述数据线的延伸方向一致，所述第三线状体与所述第六块状体分别位于所述子连接体沿其垂直方向上的两侧，且所述第三线状体、所述第六块状体分别与所述子连接体错开连接。
  11. 根据权利要求10所述的阵列基板，其中，所述第六块状体距离第一栅线的距离小于所述第三线状体距离所述第一栅线的距离，其中，所述第一栅线为：与该第三线状体相邻的两条栅线中，距离该第三线状体较远的一条栅线。
  12. 根据权利要求10所述的阵列基板，其中，所述子连接体在沿所述数据线的延伸方向上的长度小于与该子连接体相邻的两条栅线之间的距离，且所述子连接体在沿所述数据线的延伸方向上的长度大于或等于与该子连接体相邻的两条栅线之间的距离的3/4。
  13. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括：位于所述非显示区的第一静电保护线、第一静电防护单元；
    其中，所述第一静电保护线与所述数据线的延伸方向一致，所述栅线引线通过所述第一静电防护单元与所述第一静电保护线连接；
    所述阵列基板还包括：位于所述非显示区的第二静电保护线和第二静电防护单元；其中，所述第二静电保护线与所述栅线的延伸方向一致，所述数据线通过所述第二静电防护单元与所述第二静电保护线连接。
  14. 根据权利要求13所述的阵列基板，其中，
    所述第一静电保护线位于所述公共电极引线背离所述显示区的一侧；
    所述第二静电保护线位于所述数据线引线靠近所述显示区的一侧。
  15. 根据权利要求13所述的阵列基板，其中，
    所述第一静电保护线与所述公共电极引线为一体结构；或者，所述阵列基板还包括位于所述非显示区的第三静电防护单元，所述第一静电保护线通过所述第三静电防护单元与所述公共电极引线连接；
    和/或，
    所述阵列基板还包括位于所述非显示区的第四静电防护单元，所述第二静电保护线通过所述第四静电防护单元与所述公共电极引线连接。
  16. 根据权利要求15所述的阵列基板，其中，所述第一静电防护单元、所述第二静电防护单元、所述第三静电防护单元以及所述第四静电防护单元中的任一者包括：第一晶体管、第二晶体管、第一连接端以及第二连接端；
    其中，第一晶体管的源极、栅极与第二晶体管的漏极均连接第一连接端；第二晶体管的源极、栅极与第一晶体管的漏极均连接第二连接端；
    所述第一连接端、所述第二连接端用于分别连接两个需要互相进行静电释放的导体。
  17. 根据权利要求10所述的阵列基板，其中，所述亚像素包括：像素电极以及与所述公共电极线连接的公共电极；
    所述像素电极包括第一条状子电极，所述公共电极包括第二条状子电极，所述第一条状子电极与所述第二条状子电极间隔设置，且所述第一条状子电极和所述第二条状子电极均与所述数据线平行；
    所述子连接体靠近所述显示区一侧的边界与所述第一条状子电极和所述第二条状子电极平行。
  18. 根据权利要求17所述的阵列基板，其中，所述数据线为非直线状。
  19. 根据权利要求17或18所述的阵列基板，其中，位于相邻两条数据线之间的同一列亚像素中，相邻行的所述亚像素中的各像素电极分别与所述相邻两条数据线中的不同数据线连接；
    在同一行亚像素中，各像素电极与位于该行的各亚像素同侧的所述数据线连接。
  20. 根据权利要求17或18所述的阵列基板，其中，所述阵列基板还包括：位于所述非显示区的哑像素列和哑数据线；其中，所述哑像素列与所述显示区中的亚像素列相邻，所述哑数据线设置在该哑像素列的远离所述显示区的一侧；
    所述哑像素包括：哑像素电极和哑公共电极；其中，所述哑像素列中的各哑像素电极与，所述哑像素列相邻的所述数据线和所述哑数据线均不连接，所述哑像素列中的各哑公共电极与所述公共电极线均连接。
  21. 根据权利要求20所述的阵列基板，其中，所述哑数据线与所述公共电极引线连接。
  22. 根据权利要求20所述的阵列基板，其中，所述哑数据线与所述数据线平行。
  23. 根据权利要求20所述的阵列基板，其中，所述哑像素电极包括第一哑条状子电极，所述哑公共电极包括第二哑条状子电极，所述第一哑条状子电极与所述第二哑条状子电极间隔设置，且两者均与所述数据线平行。
  24. 根据权利要求2所述的阵列基板，其中，所述连接部与，所述信号线和所述信号线引线中的至少一者位于不同层，包括：
    所述连接部与，所述信号线和所述信号线引线不同层，且所述信号线和所述信号线引线同层；其中，所述连接部分别通过第一过孔、第二过孔与所述信号线、所述信号线引线连接；
    或者，所述连接部与所述信号线引线同层，所述连接部与所述信号线不同层；其中，所述连接部与所述信号线引线直接连接，所述连接部通过第一过孔与所述信号线连接；
    或者，所述连接部与所述信号线同层，所述连接部与所述信号线引线不同层；其中，所述连接部与所述信号线直接连接，所述连接部通过第二过孔与所述信号线引线连接。
  25. 根据权利要求17或18所述的阵列基板，其中，所述连接部与所述亚像素中的各像素电极同层、且同材料。
  26. 根据权利要求8所述的阵列基板，其中，
    所述栅线与所述公共电极线、所述栅线引线均同层、且同材料；
    和/或，所述数据线与所述数据线引线、所述公共电极引线均同层、且 同材料。
  27. 根据权利要求13所述的阵列基板，其中，
    所述栅线与所述公共电极线、所述栅线引线均同层、且同材料；
    和/或，所述数据线与所述数据线引线、所述公共电极引线均同层、且同材料。
  28. 根据权利要求13所述的阵列基板，其中，
    所述数据线与所述第一静电保护线同层、且同材料；
    和/或，所述栅线与所述第二静电保护线同层、且同材料。
  29. 根据权利要求8所述的阵列基板，其中，
    所述栅线与所述公共电极线、所述公共电极引线、所述数据线引线均同层、且同材料；
    和/或，所述数据线与所述栅线引线同层、且同材料。
  30. 根据权利要求13所述的阵列基板，其中，
    所述栅线与所述公共电极线、所述公共电极引线、所述数据线引线均同层、且同材料；
    和/或，所述数据线与所述栅线引线同层、且同材料；
    和/或，所述栅线与所述第一静电保护线、所述第二静电保护线同层、且同材料。
  31. 一种显示装置，包括权利要求1至30任一项所述的阵列基板。
PCT/CN2018/116013 2017-11-27 2018-11-16 阵列基板及显示装置 WO2019101019A1 (zh)

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