CN109375439A - 阵列基板及显示面板 - Google Patents
阵列基板及显示面板 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 58
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 239000010409 thin film Substances 0.000 claims abstract description 32
- 230000005611 electricity Effects 0.000 claims description 10
- 239000010408 film Substances 0.000 claims description 9
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 10
- 239000003292 glue Substances 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 50
- 238000010586 diagram Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000005034 decoration Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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Abstract
本发明提供一种阵列基板,包括显示区,设置有薄膜晶体管电路;非显示区,设置有驱动电路,防静电电路,以及虚拟薄膜晶体管电路;所述薄膜晶体管电路的栅极线,通过所述虚拟薄膜晶体管电路的栅极线与所述驱动电路电连接;所述防静电电路设置于所述虚拟薄膜晶体管电路的栅极线远离所述薄膜晶体管电路的末端;通过在所述薄膜晶体管电路和所述驱动电路之间设置虚拟薄膜晶体管电路和防静电电路,使得所述薄膜晶体管电路和所述驱动电路连接处在点亮时为黑态,将导致此处的框胶和液晶异常不会凸显出来,达到改善的效果,也避免了现有的静电在栅极线和多晶硅走线重叠区释放,从而造成栅极层和多晶硅有源层发生短路的技术问题,提高了阵列基板良率。
Description
技术领域
本发明涉及液晶显示技术领域,尤其涉及一种阵列基板及显示面板。
背景技术
现有阵列基板包括位于显示区内的栅极线、数据线等,以及位于边框区的驱动电路,显示区内的栅极线需要和驱动电路连接,将导致连接处的框胶和液晶异常。
所以,现有阵列基板存在栅极线与驱动电路连接处框胶和液晶异常的技术问题。
发明内容
本发明提供一种阵列基板,以缓解现有阵列基板存在栅极线与驱动电路连接处框胶和液晶异常的技术问题。
为解决上述问题,本发明提供的技术方案如下:
本发明提供一种阵列基板,包括:
显示区,设置有薄膜晶体管电路;
非显示区,设置有驱动电路,防静电电路,以及虚拟薄膜晶体管电路;
所述薄膜晶体管电路的栅极线,通过所述虚拟薄膜晶体管电路的栅极线与所述驱动电路电连接;所述防静电电路设置于所述虚拟薄膜晶体管电路的栅极线远离所述薄膜晶体管电路的末端。
在本发明的阵列基板中,所述防静电电路包括第一电极、第二电极、以及设置在所述第一电极和所述第二电极之间的绝缘层,所述第一电极与所述虚拟薄膜晶体管电路的栅极线电连接。
在本发明的阵列基板中,所述第一电极与所述虚拟薄膜晶体管电路的栅极线同层设置。
在本发明的阵列基板中,所述第一电极为所述虚拟薄膜晶体管电路的栅极线的末端。
在本发明的阵列基板中,所述第一电极为矩形结构。
在本发明的阵列基板中,所述第二电极与所述阵列基板的多晶硅有源层同层设置。
在本发明的阵列基板中,所述第二电极为条矩形结构。
在本发明的阵列基板中,多个所述防静电电路的所述第一电极共用一个所述第二电极。
在本发明的阵列基板中,所述第一电极朝向所述第二电极的方向设置有突起。
在本发明的阵列基板中,所述虚拟薄膜晶体管电路的数据线和所述栅极线中的至少一个,没有与所述多晶硅有源层电连接。
本发明的有益效果为:本发明提供一种阵列基板,包括显示区,设置有薄膜晶体管电路;非显示区,设置有驱动电路,防静电电路,以及虚拟薄膜晶体管电路;所述薄膜晶体管电路的栅极线,通过所述虚拟薄膜晶体管电路的栅极线与所述驱动电路电连接;所述防静电电路设置于所述虚拟薄膜晶体管电路的栅极线远离所述薄膜晶体管电路的末端;通过在所述薄膜晶体管电路和所述驱动电路之间设置虚拟薄膜晶体管电路,使得所述薄膜晶体管电路和所述驱动电路连接处在点亮时为黑态,将导致此处的框胶和液晶异常不会凸显出来,达到改善的效果,而通过在所述虚拟薄膜晶体管电路和所述驱动电路之间设置所述防静电电路,避免了现有的静电在栅极线和多晶硅走线重叠区释放,从而造成栅极层和多晶硅有源层发生短路的技术问题,提高了阵列基板良率。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明的阵列基板的结构示意图;
图2为本发明的阵列基板的膜层结构示意图。
具体实施方式
以下各实施例的说明是参考附加的图示,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是用以相同标号表示。
本发明提供一种阵列基板,以缓解现有阵列基板存在栅极线与驱动电路连接处框胶和液晶异常的技术问题。
如图1所示,为本发明的阵列基板的结构示意图。所述阵列基板包括显示区和非显示区,所述显示区设置有薄膜晶体管电路11,所述非显示区设置有虚拟薄膜晶体管电路12,防静电电路13,以及驱动电路14。所述薄膜晶体管电路11的栅极线112,通过所述虚拟薄膜晶体管电路12的栅极线122与所述驱动电路14电连接;所述防静电电路13设置于所述虚拟薄膜晶体管电路12的栅极线122远离所述薄膜晶体管电路11的末端。
所述薄膜晶体管电路11包括自上而下分层设置的数据线111、栅极线112、多晶硅走线113,以及设置在数据线111和多晶硅走线113之间,覆盖所述栅极线112的第一绝缘层(图未示出);所述虚拟薄膜晶体管电路12包括自上而下分层设置的数据线121、栅极线122、多晶硅走线123,以及设置在数据线121和多晶硅走线123之间,覆盖所述栅极线122的第二绝缘层(图未示出)。
所述虚拟薄膜晶体管电路12的数据线121和栅极线122中的至少一个,没有与多晶硅有源层电连接,即未设置过孔,因此在实际点亮的时候数据线121与多晶硅走线123的重叠区124为黑态,由于所述薄膜晶体管电路11与所述驱动电路14之间易发生框胶和液晶的异常,通过在所述薄膜晶体管电路11与所述驱动电路34之间设置所述虚拟虚拟薄膜晶体管电路12,实际点亮时交界处为黑态,使得异常不会凸显出来。
在所述虚拟薄膜晶体管电路12中,由于基板在制程中会产生积累静电,当静电在所述虚拟薄膜晶体管电路12的所述栅极线122上传输时,会经过所述栅极线122和所述多晶硅走线123的重叠区125,由于所述栅极线122和多晶硅走线123之间还设置有第二绝缘层(图中未示出),而静电易在绝缘材料上聚集,因此会在所述重叠区125释放,从而导致栅极金属层和多晶硅有源层发生短路,最终导致不良的发生。
所述防静电电路13包括第一电极131,第二电极132,以及设置在所述第一电极131和所述第二电极132之间的第三绝缘层(图未示出),所述第一电极131为所述虚拟薄膜晶体管电路12的栅极线122的末端。由于静电易在绝缘材料上聚集的特性,通过在所述虚拟薄膜晶体管电路12末端设置所述防静电电路13,可将所述阵列基板制程中产生的静电聚集在所述防静电电路13的第一电极131处,再经由所述防静电电路13的第二电极132释放,避免了现有的静电在虚拟薄膜晶体管电路12的所述重叠区125释放,从而造成栅极层和多晶硅有源层发生短路的技术问题,提高了阵列基板良率。
如图2所示,为本发明的阵列基板的膜层结构示意图,所述阵列基板包括显示区和非显示区,所述显示区设置有薄膜晶体管电路21,所述非显示区设置有虚拟薄膜晶体管电路22,防静电电路23,以及驱动电路(未标出)。
所述薄膜晶体管电路21包括基板10、设于所述基板10上的多晶硅有源层20、覆盖所述多晶硅有源层20的栅极绝缘层30、设于所述栅极绝缘层30上的栅极40、在所述栅极绝缘层30上覆盖所述栅极40的层间绝缘层50及设于所述层间绝缘层50上的源极60和漏极70,所述栅极40通过第一过孔400电性连接至所述多晶硅有源层20,所述源极60通过第二过孔600电性连接至所述多晶硅有源层20,所述漏极70通过第三过孔700电性连接至所述多晶硅有源层20。
所述虚拟薄膜晶体管电路22包括基板10、设于所述基板10上的多晶硅有源层20、覆盖所述多晶硅有源层20的栅极绝缘层30、设于所述栅极绝缘层30上的栅极41、设于所述栅极绝缘层30上覆盖所述栅极41的层间绝缘层50,以及设于所述层间绝缘层50上的源极61和漏极71,所述栅极41通过第四过孔410电性连接至所述多晶硅有源层20,所述源极61和所述漏极71与所述多晶硅有源层20之间未设置有过孔。
在一种实施例中,所述虚拟薄膜晶体管电路22的数据线和栅极线中的至少一个,没有与所述多晶硅有源层20电连接。所述虚拟薄膜晶体管电路22的数据线即所述源极61和所述漏极71,所述虚拟薄膜晶体管电路22的栅极线即所述栅极41,具体地,分三种情况。
一是在所述虚拟薄膜晶体管电路22中,所述栅极41与所述多晶硅有源层20之间设置有过孔并电性连接,所述源极61和所述漏极71与所述多晶硅有源层20之间未设置有过孔。
二是所述虚拟薄膜晶体管电路22中,所述栅极41与所述多晶硅有源层20之间未设置有过孔,所述源极61和所述漏极71和所述与所述多晶硅有源层20之间设置有过孔并电性连接。
三是所述虚拟薄膜晶体管电路22中,所述栅极41与所述多晶硅有源层20之间、所述源极61和所述漏极71与所述多晶硅有源层20之间均未设置有过孔。
在显示面板中,所述薄膜晶体管电路21与所述驱动电路之间易发生框胶和液晶的异常,直接改善较难实现,故在两者之间增加所述虚拟薄膜晶体管电路22,由于所述虚拟薄膜晶体管电路22的数据线和栅极线中的至少一个,没有与所述多晶硅有源层20电连接,即实际上点亮的时候数据线与多晶硅有源层的重叠处为黑态,让异常不会凸显出来,达到改善的效果。
如图2所示,所述防静电电路23包括第一电极42、第二电极43、以及设置在所述第一电极42和所述第二电极43之间的绝缘层300,所述第一电极42与所述虚拟薄膜晶体管电路22的栅极线41电连接。所述第一电极42与所述第二电极43之间可以形成一存储电容,静电可以在所述存储电容中释放。
在一种实施例中,所述第一电极42与所述虚拟薄膜晶体管电路22的栅极线41同层设置。
在一种实施例中,所述第一电极42为所述虚拟薄膜晶体管电路22的栅极线41的末端。所述阵列基板的栅极线包括所述薄膜晶体管电路21的所述栅极40、所述虚拟薄膜晶体管电路22的所述栅极41、所述防静电电路23的所述第一电极42,三者依次电连接并延伸至所述驱动电路中。
在一种实施例中,所述第二电极43与所述阵列基板的多晶硅有源层20同层设置。所述第二电极43与所述阵列基板的公共电极所在的金属层连接,以疏导所述阵列基板的静电。
在一种实施例中,所述第一电极42为矩形结构。所述第一电极42的具体形状还可以有多种选择,例如圆形、梯形等,只要其符合静电释放的要求即可。
在一种实施例中,所述第二电极43为矩形结构。所述第一电极42的具体形状还可以有多种选择,例如圆形、梯形等,只要其符合静电释放的要求即可。
在一种实施例中,多个所述防静电电路23的所述第一电极42共用一个所述第二电极43。多个所述第一电极42可将静电释放给同一个所述第二电极43,所述第二电极43与所述阵列基板的公共电极所在的金属层连接,以疏导所述阵列基板的静电,这种多个所述防静电电路23的所述第一电极42共用一个所述第二电极43,可减少所述阵列基板的所述第二电极43的数量,使所述阵列基板的结构简单。
在一种实施例中,所述第一电极42朝向所述第二电极43的方向设置有突起。静电在所述突起上聚集,可以更好地传递给所述第二电极43。
根据上述实施例可知:
本发明提供一种阵列基板,包括显示区,设置有薄膜晶体管电路;非显示区,设置有驱动电路,防静电电路,以及虚拟薄膜晶体管电路;所述薄膜晶体管电路的栅极线,通过所述虚拟薄膜晶体管电路的栅极线与所述驱动电路电连接;所述防静电电路设置于所述虚拟薄膜晶体管电路的栅极线远离所述薄膜晶体管电路的末端;通过在所述薄膜晶体管电路和所述驱动电路之间设置虚拟薄膜晶体管电路,使得所述薄膜晶体管电路和所述驱动电路连接处在点亮时为黑态,将导致此处的框胶和液晶异常不会凸显出来,达到改善的效果,而通过在所述虚拟薄膜晶体管电路和所述驱动电路之间设置所述防静电电路,避免了现有的静电在栅极线和多晶硅走线重叠区释放,从而造成栅极层和多晶硅有源层发生短路的技术问题,提高了阵列基板良率。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。
Claims (10)
1.一种阵列基板,其特征在于,包括:
显示区,设置有薄膜晶体管电路;
非显示区,设置有驱动电路,防静电电路,以及虚拟薄膜晶体管电路;
所述薄膜晶体管电路的栅极线,通过所述虚拟薄膜晶体管电路的栅极线与所述驱动电路电连接;所述防静电电路设置于所述虚拟薄膜晶体管电路的栅极线远离所述薄膜晶体管电路的末端。
2.如权利要求1所述的阵列基板,其特征在于,所述防静电电路包括第一电极、第二电极、以及设置在所述第一电极和所述第二电极之间的绝缘层,所述第一电极与所述虚拟薄膜晶体管电路的栅极线电连接。
3.如权利要求2所述的阵列基板,其特征在于,所述第一电极与所述虚拟薄膜晶体管电路的栅极线同层设置。
4.如权利要求3所述的阵列基板,其特征在于,所述第一电极为所述虚拟薄膜晶体管电路的栅极线的末端。
5.如权利要求3所述的阵列基板,其特征在于,所述第一电极为矩形结构。
6.如权利要求2所述的阵列基板,其特征在于,所述第二电极与所述阵列基板的多晶硅有源层同层设置。
7.如权利要求6所述的阵列基板,其特征在于,所述第二电极为矩形结构。
8.如权利要求2所述的阵列基板,其特征在于,多个所述防静电电路的所述第一电极共用一个所述第二电极。
9.如权利要求2所述的阵列基板,其特征在于,所述第一电极朝向所述第二电极的方向设置有突起。
10.如权利要求6所述的阵列基板,其特征在于,所述虚拟薄膜晶体管电路的数据线和所述栅极线中的至少一个,没有与所述多晶硅有源层电连接。
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CN108803173A (zh) * | 2018-07-02 | 2018-11-13 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法、显示装置 |
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CN110854135A (zh) * | 2019-10-29 | 2020-02-28 | 武汉华星光电技术有限公司 | 一种阵列基板、显示面板及阵列基板的制造方法 |
CN110854135B (zh) * | 2019-10-29 | 2023-09-26 | 武汉华星光电技术有限公司 | 一种阵列基板、显示面板及阵列基板的制造方法 |
CN113281943A (zh) * | 2021-05-19 | 2021-08-20 | 武汉华星光电技术有限公司 | 显示面板及显示装置 |
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CN114185209B (zh) * | 2022-02-17 | 2022-05-27 | 成都中电熊猫显示科技有限公司 | 阵列基板、显示面板和显示装置 |
Also Published As
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US20210098496A1 (en) | 2021-04-01 |
US11037961B2 (en) | 2021-06-15 |
WO2020124903A1 (zh) | 2020-06-25 |
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