JP7356360B2 - アレイ基板及び表示装置 - Google Patents
アレイ基板及び表示装置 Download PDFInfo
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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Description
Claims (18)
- アレイ基板であって、
表示領域及び非表示領域と、
少なくとも前記表示領域に位置する信号線であって、複数のゲート線、複数のデータ線、及び共通電極線を含む、信号線と、
前記非表示領域に位置する信号線リードであって、ゲート線リード、データ線リード及び共通電極リードを含む、信号線リードと、
前記非表示領域に位置し、前記信号線と前記信号線リードとを接続するための接続部であって、各ゲート線はそれぞれ異なる接続部を介して異なる前記ゲート線リードに一対一に接続され、各データ線はそれぞれ異なる前記接続部を介して異なる前記データ線リードに一対一に接続され、かつ前記共通電極線は前記接続部を介して前記共通電極リードに接続される、接続部とを備え、
前記信号線と前記信号線リードとは2つの独立した部分であり、
前記共通電極線は、少なくとも前記表示領域内に位置する第3の線状体と、前記非表示領域内に位置する接続体とを含み、前記接続体は、第6のブロック体を含み、前記接続部は、前記第6のブロック体に接続され、
前記接続体は帯状のサブ接続体をさらに含み、前記サブ接続体の帯状方向は、前記データ線の延伸方向と一致し、前記第3の線状体と前記第6のブロック体は、前記サブ接続体の垂直方向に沿った両側にそれぞれ位置し、かつ、前記第3の線状体と前記第6のブロック体は、それぞれ前記サブ接続体にずれて接続される、アレイ基板。 - 前記接続部は、前記信号線と前記信号線リードの少なくとも一方と異なる層に位置する、請求項1に記載のアレイ基板。
- 前記アレイ基板は、さらに、複数の前記ゲート線と複数の前記データ線とが縦横に交差して区画されたマトリクス状に排列する複数のサブ画素を含む、請求項1又は2に記載のアレイ基板。
- 前記ゲート線は、少なくとも前記表示領域に位置する第1の線状体と、前記非表示領域に位置する第1のブロック体とを含み、
前記ゲート線リードは、前記非表示領域に位置するゲート線リード本体と、前記ゲート線リード本体の前記表示領域に近い端部に位置する第2のブロック体とを含み、
前記接続部は、前記第1のブロック体と前記第2のブロック体とを接続する、請求項3に記載のアレイ基板。 - 前記データ線は、少なくとも前記表示領域内に位置する第2の線状体と前記非表示領域に位置する第3のブロック体をさらに含み、
前記データ線リードは、前記非表示領域に位置するデータ線リード本体と、前記データ線リード本体の前記表示領域に近い端部に位置する第4のブロック体とをさらに含み、
前記接続部は、前記第3のブロック体と前記第4のブロック体とを接続する、請求項3に記載のアレイ基板。 - 前記共通電極リードと前記データ線は延伸方向が一致し、各共通電極線は、それぞれ異なる接続部を介して前記共通電極リードに接続される;
又は、
前記共通電極リードは、前記データ線の延伸方向に一致するリード本体と、前記リード本体に接続されると共に、前記共通電極線方向に向かって延伸する複数の第5のブロック体とを含み、各第5のブロック体は1つの接続部に対応し、各共通電極線は、それぞれ異なる接続部を介して対応する前記第5のブロック体に接続される、請求項1に記載のアレイ基板。 - 各前記共通電極線は、隣接する2つのゲート線の間に配置される、請求項1に記載のアレイ基板。
- 前記第6のブロック体から第1のゲート線までの距離は、前記第3の線状体から前記第1のゲート線までの距離よりも小さく、前記第1のゲート線は、該第3の線状体に隣接する2本のゲート線のうち、該第3の線状体から遠い方の1本のゲート線である、請求項1に記載のアレイ基板。
- 前記サブ接続体の前記データ線の延伸方向に沿った長さは、該サブ接続体に隣接する2本のゲート線間の距離よりも小さく、かつ、前記サブ接続体の前記データ線の延伸方向に沿った長さは、該サブ接続体に隣接する2本のゲート線間の距離の3/4以上である、請求項1に記載のアレイ基板。
- 前記アレイ基板は、前記非表示領域に位置する第1の静電気保護配線と、第1の静電気保護ユニットとをさらに含み;
前記第1の静電気保護配線は前記データ線の延伸方向に一致し、前記ゲート線リードは前記第1の静電気保護ユニットを介して前記第1の静電気保護配線に接続され;
前記アレイ基板は、前記非表示領域に位置する第2の静電気保護配線と第2の静電気保護ユニットとをさらに含み、前記第2の静電気保護配線は、前記ゲート線の延伸方向と一致し、前記データ線は、前記第2の静電気保護ユニットを介して前記第2の静電気保護配線に接続され;
前記第1の静電気保護配線は、前記共通電極リードの前記表示領域から離れる側に位置し、
前記第2の静電気保護配線は、前記データ線リードの前記表示領域に近い側に位置する、請求項6に記載のアレイ基板。 - 前記第1の静電気保護配線は前記共通電極リードと一体構造である;又は、前記アレイ基板は、前記非表示領域に位置する第3の静電気保護ユニットをさらに含み、前記第1の静電気保護配線は、前記第3の静電気保護ユニットを介して前記共通電極リードに接続される;
又は、
前記アレイ基板は、前記非表示領域に位置する第4の静電気保護ユニットをさらに含み、前記第2の静電気保護配線は、前記第4の静電気保護ユニットを介して前記共通電極リードに接続される、請求項10に記載のアレイ基板。 - 前記第1の静電気保護ユニット、前記第2の静電気保護ユニット、前記第3の静電気保護ユニット、及び前記第4の静電気保護ユニットのいずれか1つは、第1のトランジスタと、第2のトランジスタと、第1の接続端と、第2の接続端とを有し、
前記第1のトランジスタのソース、ゲート、及び第2のトランジスタのドレインはいずれも第1の接続端に接続され、第2のトランジスタのソース、ゲート及び第1のトランジスタのドレインは、いずれも第2の接続端に接続され、
前記第1の接続端と前記第2の接続端は、前記アレイ基板の互いに静電気を放電する必要のある2つの導電体にそれぞれ接続するように配置される、請求項11に記載のアレイ基板。 - 前記サブ画素は、画素電極と、前記共通電極線に接続された共通電極とを含み;
前記画素電極は、第1の帯状サブ電極を含み、前記共通電極は、第2の帯状サブ電極を含み、前記第1の帯状サブ電極と前記第2の帯状サブ電極とは間隔をあけて配置され、かつ、前記第1の帯状サブ電極と前記第2の帯状サブ電極はいずれも前記データ線に平行であり;
前記サブ接続体の前記表示領域に近い側の境界は、前記第1の帯状サブ電極と前記第2の帯状サブ電極に平行である、請求項3に記載のアレイ基板。 - 隣接する2つのデータ線の間に位置する同一列のサブ画素のうち、隣接する行の前記サブ画素における各画素電極は、前記隣接する2つのデータ線のうちの異なるデータ線にそれぞれ接続され;
同一行のサブ画素において、各画素電極は、当該行の各サブ画素と同じ側に位置する前記データ線に接続される、請求項13に記載のアレイ基板。 - 前記アレイ基板は、前記非表示領域に位置するダミー画素列とダミーデータ線をさらに含み、前記ダミー画素列は、前記表示領域における前記非表示領域に近いサブ画素列に隣接し、前記ダミーデータ線は、該ダミー画素列の前記表示領域から離れる側に配置され;
前記ダミー画素列におけるダミー画素は、ダミー画素電極とダミー共通電極とを含み;前記ダミー画素列の各ダミー画素電極は、前記ダミー画素列に隣接する前記データ線と前記ダミーデータ線のいずれにも接続されず、前記ダミー画素列の各ダミー共通電極は、前記共通電極線のいずれにも接続され;
前記ダミーデータ線は前記共通電極リードに接続される、請求項13に記載のアレイ基板。 - 前記ダミー画素電極は、第1のダミー帯状サブ電極を含み、前記ダミー共通電極は、第2のダミー帯状サブ電極を含み、前記第1のダミー帯状サブ電極と前記第2のダミー帯状サブ電極とは間隔をあけて配置され、かつ、両者はいずれも前記データ線に平行である、請求項15に記載のアレイ基板。
- 前記接続部と、前記信号線と、前記信号線リードとの少なくとも一方は、異なる層に位置し;
前記接続部は、前記信号線と前記信号線リードと異なる層に位置し、かつ、前記信号線と前記信号線リードとは同じ層に位置し、前記接続部は、それぞれ第1のビア、第2のビアを介して、前記信号線と、前記信号線リードとに接続される形態、
又は、前記接続部は前記信号線リードと同じ層に位置し、前記接続部は前記信号線と異なる層に位置し、前記接続部は前記信号線リードに直接接続され、前記接続部は第1のビアを介して前記信号線に接続される形態、
または、前記接続部は前記信号線と同じ層に位置し、前記接続部は前記信号線リードと異なる層に位置し、前記接続部は前記信号線に直接接続され、前記接続部は、第2のビアを介して前記信号線リードに接続される形態と、を含む、請求項1に記載のアレイ基板。 - 請求項1~17のいずれか1項に記載のアレイ基板を備える表示装置。
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