WO2019210724A1 - 解复用器、包括该解复用器的阵列基板及显示装置 - Google Patents

解复用器、包括该解复用器的阵列基板及显示装置 Download PDF

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Publication number
WO2019210724A1
WO2019210724A1 PCT/CN2019/074093 CN2019074093W WO2019210724A1 WO 2019210724 A1 WO2019210724 A1 WO 2019210724A1 CN 2019074093 W CN2019074093 W CN 2019074093W WO 2019210724 A1 WO2019210724 A1 WO 2019210724A1
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Prior art keywords
thin film
data line
film transistor
control gate
connection portion
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PCT/CN2019/074093
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English (en)
French (fr)
Inventor
龙春平
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京东方科技集团股份有限公司
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Priority to US16/607,575 priority Critical patent/US11282863B2/en
Priority to JP2019556814A priority patent/JP7358240B2/ja
Priority to EP19796781.3A priority patent/EP3790051A4/en
Publication of WO2019210724A1 publication Critical patent/WO2019210724A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a demultiplexer, an array substrate including the same, and a display device.
  • Display devices have been widely used in consumer electronics such as mobile phones, notebook computers, personal computers, and personal digital assistants. Due to the requirements of the narrow bezel of the display device, it is a big challenge to complete the wiring of the demultiplexer, the data line and its leads on the high-resolution small and medium-sized display panel.
  • the present disclosure provides a demultiplexer including first to sixth thin film transistors.
  • the first to third thin film transistors are located on the same side in the demultiplexer, and the fourth to sixth thin film transistors are located in the demultiplexer and the first thin film a transistor to the opposite side of the third thin film transistor; the sources of the first to third thin film transistors are connected together to form a first input end of the demultiplexer; the fourth thin film transistor Sources of the sixth thin film transistor are connected together to form a second input terminal of the demultiplexer; drains of the first to sixth thin film transistors are respectively used as the demultiplexer a first output terminal to a sixth output terminal; a gate of the first thin film transistor and the fifth thin film transistor is connected to the first control terminal, and a gate of the third thin film transistor and the fourth thin film transistor is connected to the second control The gates of the second thin film transistor and the sixth thin film transistor are connected to the third control terminal.
  • the present disclosure also provides an array substrate including a first data line lead and a second data line lead, first to sixth data lines, and the above demultiplexer.
  • the first to third control terminals are configured as first to third control gate lines arranged in parallel; the first to third thin film transistors are located adjacent to the demultiplexer a first control gate line and away from a side of the third control gate line, the fourth to sixth thin film transistors being located adjacent to the third control gate line of the demultiplexer and away from the One side of the first control gate line;
  • the first input terminal is connected to the first data line lead;
  • the second input end is connected to the second data line lead; used as the first output end to
  • the drains of the first to sixth thin film transistors of the sixth output are configured such that drains of the first to third thin film transistors are respectively connected to the first data line and the third data line And connecting to the fifth data line; the drains of the fourth to sixth thin film transistors are respectively connected to the second data line, the fourth data line, and the sixth data line
  • the first input is integrally formed with the first data line lead
  • the second input is integrally formed with the second data line lead
  • the first data line lead and the second data line lead are located on a side of the array substrate adjacent to the first control gate line and away from the third control gate line;
  • the first to sixth data lines are located on a side of the array substrate adjacent to the third control gate line and away from the first control gate line.
  • the gates of the first to sixth thin film transistors are disposed in different layers from the first to third control gate lines; the first to sixth thin film transistors A source and a drain, the first to sixth data lines, and the first and second data line leads are disposed in the same layer as the first to third control gate lines.
  • the demultiplexer further includes first to sixth gate connections, lead connections and first data line connections, third data line connections, and fifth data lines a connection portion, wherein gates of the first to third thin film transistors pass through the first gate connection portion to the third gate connection portion and the first control gate line, respectively The third control gate line and the second control gate line are connected; the gates of the fourth thin film transistor to the sixth thin film transistor are respectively connected through the fourth gate connection portion to the sixth gate portion Connected to the second control gate line, the first control gate line, and the third control gate line; the lead connection portion is configured to connect the second data line lead and the fourth thin film transistor a source connection to a sixth thin film transistor; the first data line connection portion, the third data line connection portion, and the fifth data line connection portion are configured to connect the first data line, the third data line, and The fifth data line is respectively connected to the first thin film transistor The drain of the third thin film transistor is connected.
  • the lead connection portion includes a first lead connection portion and a second lead connection portion; the first lead connection portion is disposed in a different layer from the first control gate line to the third control gate line, and The first lead connection portion is respectively connected to the second data line lead and the second lead connection portion; the second lead connection portion is connected to sources of the fourth to sixth thin film transistors, And the second lead connection portion is disposed in the same layer as the first control gate line to the third control gate line.
  • the gates of the first to sixth thin film transistors are disposed in the same layer as the first to sixth gate connections.
  • the first data line connection portion is connected to the drain of the first data line and the first thin film transistor, and is different from the first control gate line to the third control gate line Providing that the third data line connection portion includes a first partial portion, a second partial portion, and a third partial portion, the second partial portion being connected between the first partial portion and the third partial portion, Wherein the first sub-section and the third data line are disposed in different layers, intersect with the fourth data line, and are connected to the third data line and the second sub-section; a portion intersecting the first control gate line to the third control gate line and disposed in a different layer, and connected to the second portion and a drain of the second thin film transistor; the fifth data line connection portion And a drain connected to the fifth data line and the third thin film transistor, and intersecting the first control gate line to the third control gate line and disposed in different layers.
  • the gates of the first to sixth thin film transistors are disposed in the same layer as the first to third control gate lines, and the first to sixth thin film transistors are Source and drain, the first to sixth data lines, and the first and second data line leads and the first to third control lines .
  • the gates of the first to sixth thin film transistors are disposed in a different layer from the first to sixth gate connections.
  • the first to third thin film transistors are sequentially arranged in a direction in which the first control gate line to the third control gate line extend, the fourth to sixth thin film transistors Arranged sequentially along a direction in which the first control gate line to the third control gate line extend, and the first to sixth data lines extend along the first to third control gate lines
  • the directions are arranged in order.
  • a sum of channel width to length ratios of the first to third thin film transistors is greater than 10; and a sum of channel width to length ratios of the four thin film transistors to the sixth thin film transistors is greater than 10.
  • a source of the first thin film transistor and a source of the second thin film transistor are a first common source shared by the first thin film transistor and the second thin film transistor;
  • a source of the fourth thin film transistor and a source of the fifth thin film transistor are a second common source shared by the fourth thin film transistor and the fifth thin film transistor.
  • the array substrate further includes a base substrate, a first insulating layer, and a second insulating layer.
  • An active layer of the first to sixth thin film transistors is disposed on the base substrate; the first insulating layer is disposed on the base substrate, and the first thin film transistor is sixth to sixth Above the active layer of the thin film transistor; a gate of the first to sixth thin film transistors is disposed on the first insulating layer; the second insulating layer is disposed on the first insulating layer, and Above the gates of the first to sixth thin film transistors; the source and drain of the first to sixth thin film transistors, the first to third control gate lines, the The first data line lead and the second data line lead, and the first to sixth data lines are disposed on the second insulating layer.
  • the array substrate further includes a base substrate, a first insulating layer, and a second insulating layer.
  • the gates of the first to sixth thin film transistors are disposed on the base substrate; the first insulating layer is disposed on the base substrate, and the first to sixth thin films are disposed on the substrate Above the gate of the transistor; an active layer of the first to sixth thin film transistors is disposed on the first insulating layer; the second insulating layer is disposed on the first insulating layer, and Above the active layers of the first to sixth thin film transistors; the source and drain of the first to sixth thin film transistors, the first to third control gate lines, the The first data line lead and the second data line lead, and the first to sixth data lines are disposed on the second insulating layer.
  • the present disclosure also provides a display device including the above array substrate.
  • FIG. 1 is a schematic diagram of a demultiplexer provided by an embodiment of the present disclosure
  • FIG. 2 is a top plan view of an array substrate according to an embodiment of the present disclosure
  • Figure 3a is a cross-sectional view taken along line A-A of Figure 2, in accordance with an embodiment of the present disclosure
  • Figure 3b is a cross-sectional view taken along line B-B of Figure 2, in accordance with an embodiment of the present disclosure
  • FIG. 4a is a cross-sectional view taken along line A-A of FIG. 2, in accordance with another embodiment of the present disclosure
  • 4b is a cross-sectional view taken along line B-B of FIG. 2 in accordance with this other embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a demultiplexer including first to sixth thin film transistors.
  • the first to third thin film transistors are located on the same side in the demultiplexer, and the fourth to sixth thin film transistors are located in the demultiplexer and the first thin film The transistor is on the opposite side of the third thin film transistor.
  • Sources 13, 13, 33 of the first to third thin film transistors are connected together to form a first input terminal IN1 of the demultiplexer.
  • Sources 43, 43, 63 of the fourth to sixth thin film transistors are connected together to form a second input terminal IN2 of the demultiplexer.
  • the drains 12, 22, 32, 42, 52, 62 of the first to sixth thin film transistors are used as the first to sixth output terminals OUT1 to OUT6 of the demultiplexer, respectively.
  • the gates 11 and 51 of the first and fifth thin film transistors are connected to the first control terminal CRL1, and the gates 31 and 41 of the third and fourth thin film transistors are connected to the second control terminal CRL2.
  • the gates 21, 61 of the second and sixth thin film transistors are connected to the third control terminal CRL3.
  • an embodiment of the present disclosure provides an array substrate including first and second data line leads 201, 202, first to sixth data lines 106, and 106 located in a non-display area, and The demultiplexer shown in Figure 1.
  • the first to third control terminals CRL1 to CRL3 are configured to be arranged in parallel to the first to third control gate lines 301 to 301. 303.
  • the first to third thin film transistors are located on a side of the demultiplexer adjacent to the first control gate line 301 and away from the third control gate line 303, and along the first to third control gate lines 301 to 303 The directions of extension are sequentially arranged.
  • the fourth to sixth thin film transistors are located on a side of the demultiplexer adjacent to the third control gate line 303 and away from the first control gate line 301, and along the first to third control gate lines 301 to 301
  • the direction in which the lines 303 extend is sequentially arranged.
  • the first input terminal IN1 is connected to the first data line lead 201.
  • the second input terminal IN2 is connected to the second data line lead 202.
  • the drains of the first to sixth thin film transistors serving as the first to sixth output terminals OUT1 to OUT6 are connected to respective ones of the first to sixth data lines 101 to 106, respectively.
  • the first to sixth data lines 101 to 106 are sequentially arranged in the direction in which the first to third control gate lines 301 to 303 extend.
  • the first input terminal IN1 is integrally formed with the first data line lead 201
  • the second input terminal IN2 is integrally formed with the second data line lead 202.
  • the data line leads are used to receive display drive signals from the driver chip, the demultiplexer is used to decompose one signal into a plurality of signals, and the data lines are used to transmit the signals decomposed by the demultiplexer to subsequent devices.
  • the sources 13, 13, 33 of the first to third thin film transistors are connected to the first data line lead 201.
  • the sources 43 , 43 , 63 of the fourth to sixth thin film transistors are connected to the second data line lead 202 .
  • the gates 11, 21, 31 of the first to third thin film transistors are connected to the first control gate line 301, the third control gate line 303, and the second control gate line 302, respectively.
  • the gates 41, 51, 61 of the fourth to sixth thin film transistors are connected to the second control gate line 302, the first control gate line 301, and the third control gate line 303, respectively.
  • the drains 12, 22, 32 of the first to third thin film transistors are respectively connected to the first data line 101, the third data line 103, and the fifth data line 105; the fourth thin film transistor The drains 42, 52, 62 to the sixth thin film transistor are connected to the second data line 102, the fourth data line 104, and the sixth data line 106, respectively.
  • the color filter substrate of the cartridge pair with the array substrate includes a plurality of pixel units, each of the pixel units includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein the first data line 101 and the first The four data lines 104 respectively correspond to the first pixel unit and the red pixel of the second pixel unit adjacent to each other among the plurality of pixel units; the second data line 102 and the fifth data line 105 respectively correspond to the first pixel unit and The green sub-pixel of the second pixel unit; the third data line 103 and the sixth data line 106 correspond to the blue sub-pixels of the first pixel unit and the second pixel unit, respectively.
  • the first data line 101, the second data line 102, and the third data line 103 correspond to a red sub-pixel, a green sub-pixel, and a blue sub-pixel of one pixel unit
  • the sixth data line 106 corresponds to a red sub-pixel, a green sub-pixel, and a blue sub-pixel of another adjacent pixel unit, and two thin film transistors connected to any adjacent two data lines are connected to different data lines
  • the lead wire can realize the dot inversion and column inversion mode of the array substrate under the premise of reducing the driving IC pin, increasing the peripheral circuit area and reducing the power consumption of the circuit, thereby improving the display picture quality.
  • the first data line lead 201 and the second data line lead 202 are located on a side of the array substrate adjacent to the first control gate line 301; the first to sixth data lines 106 to 106 are located on the array substrate
  • the side adjacent to the third control gate line 303, that is, the data line lead and the data line are respectively located on opposite sides of the control gate line, which is more advantageous for saving wiring space.
  • the gates of the first to sixth thin film transistors are disposed in a different layer from the first to third control gate lines 301 to 303, and to the source of the thin film transistor located in the display region.
  • a drain (not shown) different layer arrangement; a source and a drain of the first to sixth thin film transistors, first to sixth data lines 101 to sixth data lines 106, and first data line leads 201 and The two data line leads 202 are disposed in the same layer as the first control gate line 301 to the third control gate line 303; the first control gate line 301 to the third control gate line 303 and the source and drain of the thin film transistor located in the display region ( The same layer setting is not shown in the figure.
  • the demultiplexer further includes first to sixth gate connection portions 801 to 806, a lead connection portion, and three data line connection portions.
  • the gates 11, 21, and 31 of the first to third thin film transistors pass through the first gate connection portion 801 to the third gate connection portion 803, and the first control gate line 301 and the third control gate line 303, respectively.
  • the gates 41, 51, 61 of the fourth to sixth thin film transistors pass through the fourth gate connection portion 804 to the sixth gate connection portion 806 and the second control gate line 302, the first control gate line 301, and the The three control gate lines 303 are connected.
  • the gate electrode 11 of the first thin film transistor is connected to the first control gate line 301 through the first gate connection portion 801, and the first gate connection portion 801 is connected to the first control gate line 301 through the via hole.
  • the gate electrode 21 of the second thin film transistor is connected to the third control gate line 303 through the second gate connection portion 802, and the second gate connection portion 802 is connected to the third control gate line 303 through the via hole.
  • the gate 31 of the third thin film transistor is connected to the second control gate line 302 through the third gate connection portion 803, and the third gate connection portion 803 is connected to the second control gate line 302 through the via hole.
  • the gate electrode 41 of the fourth thin film transistor is connected to the second control gate line 302 through the fourth gate connection portion 804, and the fourth gate connection portion 804 is connected to the second control gate line 302 through the via hole.
  • the gate electrode 51 of the fifth thin film transistor is connected to the first control gate line 301 through the fifth gate connection portion 805, and the fifth gate connection portion 805 is connected to the first control gate line 301 through the via hole.
  • the gate electrode 61 of the sixth thin film transistor is connected to the third control gate line 303 through the sixth gate connection portion 806, and the sixth gate connection portion 806 is connected to the third control gate line 303 through the via hole.
  • the lead connection portion is configured to connect the second data line lead 202 with the sources 43 , 43 , 63 of the fourth to sixth thin film transistors.
  • the lead connection portion includes a first lead connection portion 401 and a second lead connection portion 402; the first lead connection portion 401 is disposed in a different layer from the first control gate line 301 to the third control gate line 303, and the first lead connection is The portions 401 are respectively connected to the second data line lead 202 and the second lead connecting portion 402; the second lead connecting portion 402 is connected to the sources 43 , 43 , 63 of the fourth to sixth thin film transistors, and is connected to the first control The gate line 301 to the third control gate line 303 are disposed in the same layer. Thereby, the connection of the data line lead to the source of the thin film transistor can be achieved.
  • the three data line connections are configured to connect the first data line 101, the third data line 103, and the fifth data line 105 to the drains 12, 22, 32 of the first thin film transistor to the third thin film transistor, respectively.
  • the three data line connecting portions are a first data line connecting portion 501, a third data line connecting portion, and a fifth data line connecting portion 701, respectively, wherein the first data line connecting portion is 501 is respectively connected to the first data line 101 and the drain 12 of the first thin film transistor, and the first data line connection portion 501 is disposed in a different layer from the first control gate line 301 to the third control gate line 303.
  • the third data line connection portion includes a first sub-section 601a, a second sub-section 601b, and a third sub-section 601c, and the second sub-section 601b is connected between the first sub-section 601a and the third sub-section 601c, wherein
  • the sub-section 601a is disposed in a different layer from the third data line 103, intersects with the fourth data line 104, and the first sub-portion 601a is connected to the third data line 103 and the second sub-section 601b, respectively.
  • the third sub-section 601c intersects the first control gate line 301 to the third control gate line 303 and is disposed in a different layer, and is respectively connected to the second sub-portion 601b and the drain electrode 22 of the second thin film transistor.
  • the fifth data line connection portion 701 is connected to the fifth data line 105 and the drain 32 of the third thin film transistor, respectively, and the fifth data line connection portion 701 crosses the first control gate line 301 to the third control gate line 303 and is different. Layer settings. Thereby, the connection of the data line to the drain of the thin film transistor can be achieved.
  • the first lead connection portion 401 is connected to the second data line lead 202 through the via hole 79, and the first lead connection portion 401 passes through the via hole (not shown in the figure) Shown) connected to the second lead connection 402.
  • the first data line connecting portion 501 is connected to the drain 12 of the first thin film transistor through the via 71, and the first data line connecting portion 501 is connected to the first data line 101 through the via 81; the drain 12 of the first thin film transistor
  • the first active layer 14 is connected via a via 72; the source 13 of the first thin film transistor is connected to the first active layer 14 via a via 73.
  • the first sub-section 601a is connected to the third data line 103 through a via (not shown), and the first sub-section 601a is connected to the second sub-section 601b via a via (not shown).
  • the third portion 601c is connected to the second portion 601b through the via 85, and the third portion 601c is connected to the drain 22 of the second thin film transistor through the via 75; the drain 22 of the second thin film transistor passes through the via 74. It is connected to the first active layer 14.
  • the fifth data line connection portion 701 is connected to the fifth data line 105 through the via 86, and the fifth data line connection portion 701 is connected through the via hole 76 and the drain 32 of the third thin film transistor; the drain 32 of the third thin film transistor
  • the source 33 is connected to the second active layer 34 via a via 77; the source 33 of the third thin film transistor is connected to the second active layer 34 via a via 78.
  • the drain 42 of the fourth thin film transistor is connected to the third active layer 44 through the via 82; the source 43 of the fourth thin film transistor is connected to the third active layer 44 through the via 83; the drain 52 of the fifth thin film transistor The third active layer 44 is connected through the via 84.
  • the drain 62 of the sixth thin film transistor is connected to the fourth active layer 64 through the via 88; the source 63 of the sixth thin film transistor is connected to the fourth active layer 64 through the via 87.
  • the gates of the first to sixth thin film transistors are disposed in a different layer from the first to third control gate lines 301 to 303. Moreover, the first to sixth gate connection portions 801 to 806 included in the demultiplexer are disposed in the same layer as the gates of the first to sixth thin film transistors.
  • the gates of the first to sixth thin film transistors are disposed in the same layer as the first to third control gate lines, and the source and drain of the first to sixth thin film transistors
  • the first to sixth data lines, and the first and second data line leads are disposed in a different layer from the first to third control lines.
  • the demultiplexer further includes first to sixth gate connections, lead connections, and three data line connections.
  • the first gate connection portion 801 to the sixth gate connection portion 806 are disposed in a different layer from the gates of the first to sixth thin film transistors; the structure and function of the lead connection portion and the three data line connection portions are The embodiments are similar, and have been described in detail in the previous embodiments, and are not described herein again.
  • the sum of the channel width to length ratios of the first to third thin film transistors is greater than 10; and the sum of the channel width to length ratios of the fourth to sixth thin film transistors is greater than 10. It has been found through experimentation that by setting the sum of the channel width-to-length ratios of the thin film transistors to be larger than 10, the charging current can be increased, thereby improving the charging efficiency.
  • the channel width to length ratio refers to the ratio of the width to the length of the channel, wherein the width of the channel is the length of the active layer of the thin film transistor in the extending direction of the drain or the source; the length of the channel is a thin film The separation distance between the source and the drain of the transistor.
  • the active layer of the thin film transistor may include amorphous silicon, low temperature polycrystalline silicon, or an oxide semiconductor.
  • the source of the first thin film transistor and the source of the second thin film transistor are the first common source 13 shared by the first thin film transistor and the second thin film transistor, and the first common source 13 passes at least one
  • the hole 73 is electrically connected to the first active layer 14;
  • the source of the fourth thin film transistor and the source of the fifth thin film transistor are the second common source 43 shared by the fourth thin film transistor and the fifth thin film transistor, and the second common source
  • the pole 43 is electrically connected to the third active layer 44 through at least one via 83.
  • the array substrate further includes a base substrate 1, a buffer layer 2, a first insulating layer 3, and a second insulating layer 4.
  • the array substrate employs a top gate structure.
  • the buffer layer 2 is provided on the base substrate 1.
  • the active layers of the first to sixth thin film transistors are disposed on the buffer layer 2.
  • the first insulating layer 3 is disposed on the buffer layer 2 and over the active layers of the first to sixth thin film transistors.
  • the gates of the first to sixth thin film transistors are disposed on the first insulating layer 3.
  • the second insulating layer 4 is disposed on the first insulating layer 3 and above the gates of the first to sixth thin film transistors.
  • the source and drain of the first to sixth thin film transistors, the first to third control gate lines, the data line leads, and the data lines are disposed on the second insulating layer 4.
  • the array substrate employs a bottom gate structure.
  • the gates of the first to sixth thin film transistors are disposed on the base substrate; the first insulating layer is disposed on the base substrate, and the first to sixth thin film transistors are disposed.
  • an active layer of the first to sixth thin film transistors is disposed on the first insulating layer; a second insulating layer is disposed on the first insulating layer, and in the first to sixth thin film transistors Above the active layer; the source and drain of the first to sixth thin film transistors, the first to third control gate lines, the data line leads and the data lines are disposed on the second insulating layer.
  • the first to third thin film transistors of the demultiplexer are located on one side of the demultiplexer adjacent to the first control gate line, and the four thin film transistors are The six thin film transistors are located on the side of the demultiplexer adjacent to the third control gate line, thereby saving the wiring space of the demultiplexer and the data lines and their leads on the panel, and facilitating the wiring on the small and medium size display panels. .
  • the present disclosure also provides a display device including the above array substrate provided by the present disclosure.
  • the display device provided by the present disclosure can save the wiring space of the demultiplexer and the data line and its lead on the panel by using the above array substrate provided by the present disclosure, thereby facilitating the wiring on the small and medium size display panel.

Abstract

本公开提供一种解复用器、一种阵列基板和一种显示装置。所述阵列基板包括多条数据线引线、并排布置的多条数据线、以及所述解复用器。所述解复用器包括平行布置的第一控制栅线至第三控制栅线，以及第一薄膜晶体管至第六薄膜晶体管。第一薄膜晶体管至第三薄膜晶体管位于解复用器的邻近第一控制栅线的一侧，四薄膜晶体管至第六薄膜晶体管位于解复用器的邻近第三控制栅线的一侧，并且第一薄膜晶体管至第六薄膜晶体管的漏极分别与所述多条数据线中的相应的数据线连接。

Description

解复用器、包括该解复用器的阵列基板及显示装置
相关申请的交叉引用
本公开要求于2018年5月4日提交的中国专利申请No.201820659349.X的优先权，该中国专利申请通过引用的方式全文并入本公开中。
技术领域
本公开涉及显示技术领域，具体地，涉及一种解复用器、包括该解复用器的阵列基板及显示装置。
背景技术
显示装置已被广泛地应用于手机、笔记本电脑、个人电脑及个人数字助理等的消费电子产品。由于显示装置的窄边框的要求，在高分辨率的中小尺寸的显示面板上完成解复用器、数据线及其引线的布线，是一项较大的挑战。
发明内容
本公开提供一种解复用器，包括第一薄膜晶体管至第六薄膜晶体管。所述第一薄膜晶体管至第三薄膜晶体管在所述解复用器中位于同一侧，并且所述第四薄膜晶体管至第六薄膜晶体管在所述解复用器中位于与所述第一薄膜晶体管至第三薄膜晶体管相对的另一侧；所述第一薄膜晶体管至第三薄膜晶体管的源极连接在一起，以形成所述解复用器的第一输入端；所述第四薄膜晶体管至第六薄膜晶体管的源极连接在一起，以形成所述解复用器的第二输入端；所述第一薄膜晶体管至第六薄膜晶体管的漏极分别用作所述解复用器的第一输出端至第六输出端；所述第一薄膜晶体管和第五薄膜晶体管的栅极连接至第一控制端，所述第三薄膜晶体管和第四薄膜晶体管的栅极连接至第二控制端，所述第二薄膜晶体管和第六薄膜晶体管的栅极连接至第三控制端。
本公开还提供一种阵列基板，包括第一数据线引线和第二数据线引线、第一数据线至第六数据线、以及上述解复用器。所述第一控制端至第三控制端被配置为平行布置的第一控制栅线至第三控制栅线；所述第一薄膜晶体管至第三薄膜晶体管位于所述解复用器的邻近所述第一控制栅线并且远离所述第三控制栅线的一侧，所述第四薄膜晶体管至第六薄膜晶体管位于所述解复用器的邻近所述第三控制栅线并且远离所述第一控制栅线的一侧；所述第一输入端连接到所述第一数据线引线；所述第二输入端连接到所述第二数据线引线；用作所述第一输出端至第六输出端的所述第一薄膜晶体管至第六薄膜晶体管的漏极被配置为所述第一薄膜晶体管至第三薄膜晶体管的漏极分别与所述第一数据线、所述第三数据线和所述第五数据线连接；所述第四薄膜晶体管至第六薄膜晶体管的漏极分别与所述第二数据线、所述第四数据线和所述第六数据线连接。
在一些实施例中，所述第一输入端与所述第一数据线引线一体地形成，所述第二输入端与所述第二数据线引线一体地形成。
在一些实施例中，所述第一数据线引线和所述第二数据线引线位于所述阵列基板的邻近所述第一控制栅线并且远离所述第三控制栅线的一侧；所述第一数据线至第六数据线位于所述阵列基板的邻近所述第三控制栅线并且远离所述第一控制栅线的一侧。
在一些实施例中，所述第一薄膜晶体管至第六薄膜晶体管的栅极与所述第一控制栅线至第三控制栅线异层设置；所述第一薄膜晶体管至第六薄膜晶体管的源极和漏极、所述第一数据线至第六数据线、以及所述第一数据线引线和第二数据线引线与所述第一控制栅线至第三控制栅线同层设置。
在一些实施例中，所述解复用器还包括第一栅极连接部至第六栅极连接部、引线连接部和第一数据线连接部、第三数据线连接部和第五数据线连接部，其中，所述第一薄膜晶体管至所述第三薄膜晶体管的栅极分别通过所述第一栅极连接部至所述第三栅极连接部与所述第一控制栅线、所述第三控制栅线和所述第二控 制栅线连接；所述第四薄膜晶体管至所述第六薄膜晶体管的栅极分别通过所述第四栅极连接部至所述第六栅极连接部与所述第二控制栅线、所述第一控制栅线和所述第三控制栅线连接；所述引线连接部被配置为将所述第二数据线引线与所述第四薄膜晶体管至第六薄膜晶体管的源极连接；所述第一数据线连接部、第三数据线连接部和第五数据线连接部被配置为将所述第一数据线、所述第三数据线和所述第五数据线分别与所述第一薄膜晶体管至所述第三薄膜晶体管的漏极连接。
在一些实施例中，所述引线连接部包括第一引线连接部和第二引线连接部；所述第一引线连接部与所述第一控制栅线至第三控制栅线异层设置，且所述第一引线连接部分别与所述第二数据线引线和所述第二引线连接部连接；所述第二引线连接部与所述第四薄膜晶体管至第六薄膜晶体管的源极连接，且所述第二引线连接部与所述第一控制栅线至第三控制栅线同层设置。
在一些实施例中，所述第一薄膜晶体管至第六薄膜晶体管的栅极与所述第一栅极连接部至第六栅极连接部同层设置。
在一些实施例中，所述第一数据线连接部与所述第一数据线和所述第一薄膜晶体管的漏极连接，并且与所述第一控制栅线至第三控制栅线异层设置；所述第三数据线连接部包括第一分部、第二分部和第三分部，所述第二分部连接在所述第一分部和所述第三分部之间，其中，所述第一分部与所述第三数据线异层设置，与所述第四数据线交叉设置，并且与所述第三数据线和所述第二分部连接；所述第三分部与所述第一控制栅线至第三控制栅线交叉且异层设置，且与所述第二分部和所述第二薄膜晶体管的漏极连接；所述第五数据线连接部与所述第五数据线和所述第三薄膜晶体管的漏极连接，并且与所述第一控制栅线至第三控制栅线交叉且异层设置。
在一些实施例中，所述第一薄膜晶体管至第六薄膜晶体管的栅极与所述第一控制栅线至第三控制栅线同层设置，且所述第一薄膜晶体管至第六薄膜晶体管的源极和漏极、所述第一数据线至 第六数据线、以及所述第一数据线引线和第二数据线引线与所述第一控制栅线至第三控制栅线异层设置。
在一些实施例中，所述第一薄膜晶体管至第六薄膜晶体管的栅极与所述第一栅极连接部至第六栅极连接部异层设置。
在一些实施例中，所述第一薄膜晶体管至第三薄膜晶体管沿着所述第一控制栅线至第三控制栅线延伸的方向顺序地排列，所述第四薄膜晶体管至第六薄膜晶体管沿着所述第一控制栅线至第三控制栅线延伸的方向顺序地排列，并且所述第一数据线至第六数据线沿着所述第一控制栅线至第三控制栅线延伸的方向顺序地排列。
在一些实施例中，所述第一薄膜晶体管至第三薄膜晶体管的沟道宽长比之和大于10；所述四薄膜晶体管至第六薄膜晶体管的沟道宽长比之和大于10。
在一些实施例中，所述第一薄膜晶体管的源极和所述第二薄膜晶体管的源极是所述第一薄膜晶体管和所述第二薄膜晶体管共用的第一共用源极；所述第四薄膜晶体管的源极和所述第五薄膜晶体管的源极是所述第四薄膜晶体管和所述第五薄膜晶体管共用的第二共用源极。
在一些实施例中，所述阵列基板还包括衬底基板、第一绝缘层和第二绝缘层。所述第一薄膜晶体管至第六薄膜晶体管的有源层设置在所述衬底基板上；所述第一绝缘层设置在所述衬底基板上，且在所述第一薄膜晶体管至第六薄膜晶体管的有源层上方；所述第一薄膜晶体管至第六薄膜晶体管的栅极设置在所述第一绝缘层上；所述第二绝缘层设置在所述第一绝缘层上，且在所述第一薄膜晶体管至第六薄膜晶体管的栅极上方；所述第一薄膜晶体管至第六薄膜晶体管的源极和漏极、所述第一控制栅线至第三控制栅线、所述第一数据线引线和第二数据线引线、和所述第一数据线至第六数据线设置在所述第二绝缘层上。
在一些实施例中，所述阵列基板还包括衬底基板、第一绝缘层和第二绝缘层。所述第一薄膜晶体管至第六薄膜晶体管的栅极 设置在所述衬底基板上；所述第一绝缘层设置在所述衬底基板上，且在所述第一薄膜晶体管至第六薄膜晶体管的栅极上方；所述第一薄膜晶体管至第六薄膜晶体管的有源层设置在所述第一绝缘层上；所述第二绝缘层设置在所述第一绝缘层上，且在所述第一薄膜晶体管至第六薄膜晶体管的有源层上方；所述第一薄膜晶体管至第六薄膜晶体管的源极和漏极、所述第一控制栅线至第三控制栅线、所述第一数据线引线和第二数据线引线、和所述第一数据线至第六数据线设置在所述第二绝缘层上。
本公开还提供一种显示装置，其包括上述阵列基板。
附图说明
图1为本公开的实施例提供的解复用器的示意图；
图2为本公开的实施例提供的阵列基板的俯视图；
图3a为根据本公开的实施例的沿图2中的A-A线截取的剖视图；
图3b为根据本公开的实施例的沿图2中的B-B线截取的剖视图；
图4a为根据本公开的另一实施例的沿图2中的A-A线截取的剖视图；
图4b为根据本公开的该另一实施例的沿图2中的B-B线截取的剖视图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图来对本公开提供的解复用器、阵列基板及显示装置进行详细描述。
参照图1和图2，本公开的实施例提供了一种解复用器，其包括第一薄膜晶体管至第六薄膜晶体管。所述第一薄膜晶体管至第三薄膜晶体管在所述解复用器中位于同一侧，并且所述第四薄膜晶体管至第六薄膜晶体管在所述解复用器中位于与所述第一薄 膜晶体管至第三薄膜晶体管相对的另一侧。所述第一薄膜晶体管至第三薄膜晶体管的源极13、13、33连接在一起，以形成所述解复用器的第一输入端IN1。所述第四薄膜晶体管至第六薄膜晶体管的源极43、43、63连接在一起，以形成所述解复用器的第二输入端IN2。所述第一薄膜晶体管至第六薄膜晶体管的漏极12、22、32、42、52、62分别用作所述解复用器的第一输出端OUT1至第六输出端OUT6。所述第一薄膜晶体管和第五薄膜晶体管的栅极11、51连接至第一控制端CRL1，所述第三薄膜晶体管和第四薄膜晶体管的栅极31、41连接至第二控制端CRL2，所述第二薄膜晶体管和第六薄膜晶体管的栅极21、61连接至第三控制端CRL3。
参照图2，本公开的实施例提供了一种阵列基板，其包括位于非显示区的第一数据线引线201和第二数据线引线202、第一数据线101至第六数据线106、以及如图1所示的解复用器。
如图1和图2所示，在本公开的实施例提供的阵列基板中，第一控制端CRL1至第三控制端CRL3被配置为平行布置的第一控制栅线301至第三控制栅线303。第一薄膜晶体管至第三薄膜晶体管位于解复用器的邻近第一控制栅线301并且远离第三控制栅线303的一侧，并且沿着第一控制栅线301至第三控制栅线303延伸的方向顺序地排列。第四薄膜晶体管至第六薄膜晶体管位于解复用器的邻近第三控制栅线303并且远离第一控制栅线301的一侧，并且沿着所述第一控制栅线301至第三控制栅线303延伸的方向顺序地排列。第一输入端IN1连接到第一数据线引线201。第二输入端IN2连接到第二数据线引线202。用作所述第一输出端OUT1至第六输出端OUT6的第一薄膜晶体管至第六薄膜晶体管的漏极分别与第一数据线101至第六数据线106中的相应的数据线连接。第一数据线101至第六数据线106沿着第一控制栅线301至第三控制栅线303延伸的方向顺序地排列。
这样，可以节省解复用器、数据线及其引线在面板上的布线空间，从而有利于在中小尺寸的显示面板上完成布线。
在本公开的实施例中，第一输入端IN1与第一数据线引线201 一体地形成，第二输入端IN2与第二数据线引线202一体地形成。
通常，数据线引线用于从驱动芯片接收显示驱动信号，解复用器用于将一个信号分解为多个信号，数据线用于将经过解复用器分解的信号传输至后续装置。
下面对薄膜晶体管、数据线及其引线和控制栅线的连接方式进行详细描述。具体地，如图2所示，第一薄膜晶体管至第三薄膜晶体管的源极13、13、33与第一数据线引线201连接。第四薄膜晶体管至第六薄膜晶体管的源极43、43、63与第二数据线引线202连接。
在本公开的实施例中，第一薄膜晶体管至第三薄膜晶体管的栅极11、21、31分别与第一控制栅线301、第三控制栅线303和第二控制栅线302连接。第四薄膜晶体管至第六薄膜晶体管的栅极41、51、61分别与第二控制栅线302、第一控制栅线301和第三控制栅线303连接。
在本公开的实施例中，第一薄膜晶体管至第三薄膜晶体管的漏极12、22、32分别与第一数据线101、第三数据线103和第五数据线105连接；第四薄膜晶体管至第六薄膜晶体管的漏极42、52、62分别与第二数据线102、第四数据线104和第六数据线106连接。
在本公开的实施例中，与阵列基板对盒的彩膜基板包括多个像素单元，每个像素单元包括红色子像素、绿色子像素和蓝色子像素，其中，第一数据线101和第四数据线104分别对应所述多个像素单元中的彼此相邻的第一像素单元和第二像素单元的红色子像素；第二数据线102和第五数据线105分别对应第一像素单元和第二像素单元的绿色子像素；第三数据线103和第六数据线106分别对应第一像素单元和第二像素单元的蓝色子像素。
由于第一数据线101、第二数据线102、第三数据线103对应于一个像素单元的红色子像素、绿色子像素和蓝色子像素，并且第四数据线104、第五数据线105、第六数据线106对应于相邻的另一个像素单元的红色子像素、绿色子像素和蓝色子像素，并且 连接到任意相邻的两条数据线的两个薄膜晶体管连接到不同的数据线引线；因此可以在减少驱动IC引脚、不增加周边电路面积和降低电路功耗的前提下，实现阵列基板的点反转和列反转模式，有利于提高显示画面品质。
在本公开的实施例中，第一数据线引线201和第二数据线引线202位于阵列基板的邻近第一控制栅线301的一侧；第一数据线101至第六数据线106位于阵列基板的邻近第三控制栅线303的一侧，也就是说，数据线引线与数据线分别位于控制栅线的相对侧，这更有利于节省布线空间。
在本公开的实施例中，第一薄膜晶体管至第六薄膜晶体管的栅极与第一控制栅线301至第三控制栅线303异层设置，且与位于显示区的薄膜晶体管的源极和漏极(图中未示出)异层设置；第一薄膜晶体管至第六薄膜晶体管的源极和漏极、第一数据线101至第六数据线106、以及第一数据线引线201和第二数据线引线202与第一控制栅线301至第三控制栅线303同层设置；第一控制栅线301至第三控制栅线303与位于显示区的薄膜晶体管的源极和漏极(图中未示出)同层设置。
在本公开的实施例中，解复用器还包括第一栅极连接部801至第六栅极连接部806、引线连接部和三个数据线连接部。其中，第一薄膜晶体管至第三薄膜晶体管的栅极11、21、31分别通过第一栅极连接部801至第三栅极连接部803与第一控制栅线301、第三控制栅线303和第二控制栅线302连接。第四薄膜晶体管至第六薄膜晶体管的栅极41、51、61分别通过第四栅极连接部804至第六栅极连接部806与第二控制栅线302、第一控制栅线301和第三控制栅线303连接。
具体来说，第一薄膜晶体管的栅极11通过第一栅极连接部801与第一控制栅线301连接，第一栅极连接部801通过过孔与第一控制栅线301连接。第二薄膜晶体管的栅极21通过第二栅极连接部802与第三控制栅线303连接，第二栅极连接部802通过过孔与第三控制栅线303连接。第三薄膜晶体管的栅极31通过第三 栅极连接部803与第二控制栅线302连接，第三栅极连接部803通过过孔与第二控制栅线302连接。第四薄膜晶体管的栅极41通过第四栅极连接部804与第二控制栅线302连接，第四栅极连接部804通过过孔与第二控制栅线302连接。第五薄膜晶体管的栅极51通过第五栅极连接部805与第一控制栅线301连接，第五栅极连接部805通过过孔与第一控制栅线301连接。第六薄膜晶体管的栅极61通过第六栅极连接部806与第三控制栅线303连接，第六栅极连接部806通过过孔与第三控制栅线303连接。
在本公开的实施例中，引线连接部被配置为将第二数据线引线202与第四薄膜晶体管至第六薄膜晶体管的源极43、43、63连接。具体地，引线连接部包括第一引线连接部401和第二引线连接部402；第一引线连接部401与第一控制栅线301至第三控制栅线303异层设置，且第一引线连接部401分别与第二数据线引线202和第二引线连接部402连接；第二引线连接部402与第四薄膜晶体管至第六薄膜晶体管的源极43、43、63连接，并且与第一控制栅线301至第三控制栅线303同层设置。由此，可以实现数据线引线与薄膜晶体管的源极的连接。
三个数据线连接部被配置为将第一数据线101、第三数据线103和第五数据线105分别与第一薄膜晶体管至所述第三薄膜晶体管的漏极12、22、32连接。具体地，在本公开的实施例中，三个数据线连接部分别为第一数据线连接部501、第三数据线连接部和第五数据线连接部701，其中，第一数据线连接部501分别与第一数据线101和第一薄膜晶体管的漏极12连接，且第一数据线连接部501与第一控制栅线301至第三控制栅线303异层设置。第三数据线连接部包括第一分部601a、第二分部601b和第三分部601c，第二分部601b连接在第一分部601a和第三分部601c之间，其中，第一分部601a与第三数据线103异层设置，与第四数据线104交叉设置，并且第一分部601a分别与第三数据线103和第二分部601b连接。第三分部601c与第一控制栅线301至第三控制栅线303交叉且异层设置，且分别与第二分部601b和第二薄膜晶 体管的漏极22连接。第五数据线连接部701分别与第五数据线105和第三薄膜晶体管的漏极32连接，且第五数据线连接部701与第一控制栅线301至第三控制栅线303交叉且异层设置。由此，可以实现数据线与薄膜晶体管的漏极的连接。
如图3a和图3b所示，在本公开的实施例中，第一引线连接部401通过过孔79与第二数据线引线202连接，且第一引线连接部401通过过孔(图中未示出)和第二引线连接部402连接。第一数据线连接部501通过过孔71与第一薄膜晶体管的漏极12连接，且第一数据线连接部501通过过孔81与第一数据线101连接；第一薄膜晶体管的漏极12通过过孔72与第一有源层14连接；第一薄膜晶体管的源极13通过过孔73与第一有源层14连接。第一分部601a通过过孔(图中未示出)与第三数据线103连接，且第一分部601a通过过孔(图中未示出)与第二分部601b连接。第三分部601c通过过孔85与第二分部601b连接，且第三分部601c通过过孔75与第二薄膜晶体管的漏极22连接；第二薄膜晶体管的漏极22通过过孔74与第一有源层14连接。第五数据线连接部701通过过孔86与第五数据线105连接，且第五数据线连接部701通过过孔76和第三薄膜晶体管的漏极32连接；第三薄膜晶体管的漏极32通过过孔77与第二有源层34连接；第三薄膜晶体管的源极33通过过孔78与第二有源层34连接。
第四薄膜晶体管的漏极42通过过孔82与第三有源层44连接；第四薄膜晶体管的源极43通过过孔83与第三有源层44连接；第五薄膜晶体管的漏极52通过过孔84与第三有源层44连接。第六薄膜晶体管的漏极62通过过孔88与第四有源层64连接；第六薄膜晶体管的源极63通过过孔87与第四有源层64连接。
第一薄膜晶体管至第六薄膜晶体管的栅极与第一控制栅线301至第三控制栅线303异层设置。而且，解复用器包括的第一栅极连接部801至第六栅极连接部806与所述第一薄膜晶体管至第六薄膜晶体管的栅极同层设置。
在一些实施例中，第一薄膜晶体管至第六薄膜晶体管的栅极 与第一控制栅线至第三控制栅线同层设置，且第一薄膜晶体管至第六薄膜晶体管的源极和漏极、第一数据线至第六数据线、以及第一数据线引线和第二数据线引线与第一控制栅线至第三控制栅线异层设置。
在这种情况下，与之前的实施例相类似的，解复用器还包括第一栅极连接部至第六栅极连接部、引线连接部和三个数据线连接部。第一栅极连接部801至第六栅极连接部806与所述第一薄膜晶体管至第六薄膜晶体管的栅极异层设置；引线连接部和三个数据线连接部的结构和功能与之前的实施例相类似，由于在之前的实施例中已有了详细描述，在此不再赘述。
在一些实施例中，第一薄膜晶体管至第三薄膜晶体管的沟道宽长比之和大于10；四薄膜晶体管至第六薄膜晶体管的沟道宽长比之和大于10。通过试验发现，通过将薄膜晶体管的沟道宽长比之和设置为大于10，可以增大充电电流，从而提高充电效率。这里，沟道宽长比是指沟道的宽度与长度的比值，其中，沟道的宽度为薄膜晶体管的有源层在漏极或源极的延伸方向上的长度；沟道的长度为薄膜晶体管的源极与漏极之间的间隔距离。
薄膜晶体管的有源层可以包括非晶硅、低温多晶硅、或氧化物半导体。
在一些实施例中，第一薄膜晶体管的源极和第二薄膜晶体管的源极是第一薄膜晶体管和第二薄膜晶体管共用的第一共用源极13，第一共用源极13通过至少一个过孔73与第一有源层14电连接；第四薄膜晶体管的源极和第五薄膜晶体管的源极是第四薄膜晶体管和第五薄膜晶体管共用的第二共用源极43，第二共用源极43通过至少一个过孔83与第三有源层44电连接。这样，可以增大薄膜晶体管的沟道宽长比。
在本公开的实施例中，阵列基板还包括衬底基板1、缓冲层2、第一绝缘层3和第二绝缘层4。在一些实施例中，阵列基板采用顶栅结构。如图3a和图3b所示，缓冲层2设置在衬底基板1上。第一薄膜晶体管至第六薄膜晶体管的有源层设置在缓冲层2上。 第一绝缘层3设置在缓冲层2上，且在第一薄膜晶体管至第六薄膜晶体管的有源层上方。第一薄膜晶体管至第六薄膜晶体管的栅极设置在第一绝缘层3上。第二绝缘层4设置在第一绝缘层3上，且在第一薄膜晶体管至第六薄膜晶体管的栅极上方。第一薄膜晶体管至第六薄膜晶体管的源极和漏极、第一控制栅线至第三控制栅线、数据线引线和数据线设置在第二绝缘层4上。
在一些实施例中，阵列基板采用底栅结构。如图4a和图4b所示，第一薄膜晶体管至第六薄膜晶体管的栅极设置在衬底基板上；第一绝缘层设置在衬底基板上，且在第一薄膜晶体管至第六薄膜晶体管的栅极上方；第一薄膜晶体管至第六薄膜晶体管的有源层设置在第一绝缘层上；第二绝缘层设置在第一绝缘层上，且在第一薄膜晶体管至第六薄膜晶体管的有源层上方；第一薄膜晶体管至第六薄膜晶体管的源极和漏极、第一控制栅线至第三控制栅线、数据线引线和数据线设置在第二绝缘层上。
综上所述，根据本公开提供的阵列基板，由于解复用器的第一薄膜晶体管至第三薄膜晶体管位于解复用器的邻近第一控制栅线的一侧，并且四薄膜晶体管至第六薄膜晶体管位于解复用器的邻近第三控制栅线的一侧，因此可以节省解复用器与数据线及其引线在面板上的布线空间，有利于在中小尺寸的显示面板上完成布线。
本公开还提供一种显示装置，其包括本公开提供的上述阵列基板。
本公开提供的显示装置，其通过采用本公开提供的上述阵列基板，可以节省解复用器与数据线及其引线在面板上的布线空间，从而有利于在中小尺寸的显示面板上完成布线。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (22)

  1. 一种解复用器，包括第一薄膜晶体管至第六薄膜晶体管，其中，
    所述第一薄膜晶体管至第三薄膜晶体管在所述解复用器中位于同一侧，并且所述第四薄膜晶体管至第六薄膜晶体管在所述解复用器中位于与所述第一薄膜晶体管至第三薄膜晶体管相对的另一侧；
    所述第一薄膜晶体管至第三薄膜晶体管的源极连接在一起，以形成所述解复用器的第一输入端；
    所述第四薄膜晶体管至第六薄膜晶体管的源极连接在一起，以形成所述解复用器的第二输入端；
    所述第一薄膜晶体管至第六薄膜晶体管的漏极分别用作所述解复用器的第一输出端至第六输出端；
    所述第一薄膜晶体管和第五薄膜晶体管的栅极连接至第一控制端，所述第三薄膜晶体管和第四薄膜晶体管的栅极连接至第二控制端，所述第二薄膜晶体管和第六薄膜晶体管的栅极连接至第三控制端。
  2. 根据权利要求1所述的解复用器，其中，所述第一薄膜晶体管至第三薄膜晶体管的沟道宽长比之和大于10；所述四薄膜晶体管至第六薄膜晶体管的沟道宽长比之和大于10。
  3. 根据权利要求1或2所述的解复用器，其中，所述第一薄膜晶体管的源极和所述第二薄膜晶体管的源极是所述第一薄膜晶体管和所述第二薄膜晶体管共用的第一共用源极；
    所述第四薄膜晶体管的源极和所述第五薄膜晶体管的源极是所述第四薄膜晶体管和所述第五薄膜晶体管共用的第二共用源极。
  4. 一种阵列基板，包括第一数据线引线和第二数据线引线、第一数据线至第六数据线、以及权利要求1所述的解复用器，其中，
    所述第一控制端至第三控制端被配置为平行布置的第一控制栅线至第三控制栅线；
    所述第一薄膜晶体管至第三薄膜晶体管位于所述解复用器的邻近所述第一控制栅线并且远离所述第三控制栅线的一侧，所述第四薄膜晶体管至第六薄膜晶体管位于所述解复用器的邻近所述第三控制栅线并且远离所述第一控制栅线的一侧；
    所述第一输入端连接到所述第一数据线引线；
    所述第二输入端连接到所述第二数据线引线；
    用作所述第一输出端至第六输出端的所述第一薄膜晶体管至第六薄膜晶体管的漏极被配置为所述第一薄膜晶体管至第三薄膜晶体管的漏极分别与所述第一数据线、所述第三数据线和所述第五数据线连接；所述第四薄膜晶体管至第六薄膜晶体管的漏极分别与所述第二数据线、所述第四数据线和所述第六数据线连接。
  5. 根据权利要求4所述的阵列基板，其中，所述第一输入端与所述第一数据线引线一体地形成，所述第二输入端与所述第二数据线引线一体地形成。
  6. 根据权利要求5所述的阵列基板，其中，所述第一数据线引线和所述第二数据线引线位于所述阵列基板的邻近所述第一控制栅线并且远离所述第三控制栅线的一侧；所述第一数据线至第六数据线位于所述阵列基板的邻近所述第三控制栅线并且远离所述第一控制栅线的一侧。
  7. 根据权利要求5或6所述的阵列基板，其中，所述第一薄膜晶体管至第六薄膜晶体管的栅极与所述第一控制栅线至第三控制栅线异层设置；所述第一薄膜晶体管至第六薄膜晶体管的源极 和漏极、所述第一数据线至第六数据线、以及所述第一数据线引线和第二数据线引线与所述第一控制栅线至第三控制栅线同层设置。
  8. 根据权利要求5-7中任一项所述的阵列基板，其中，所述解复用器还包括第一栅极连接部至第六栅极连接部、引线连接部和第一数据线连接部、第三数据线连接部和第五数据线连接部，其中，
    所述第一薄膜晶体管至所述第三薄膜晶体管的栅极分别通过所述第一栅极连接部至所述第三栅极连接部与所述第一控制栅线、所述第三控制栅线和所述第二控制栅线连接；所述第四薄膜晶体管至所述第六薄膜晶体管的栅极分别通过所述第四栅极连接部至所述第六栅极连接部与所述第二控制栅线、所述第一控制栅线和所述第三控制栅线连接；
    所述引线连接部被配置为将所述第二数据线引线与所述第四薄膜晶体管至第六薄膜晶体管的源极连接；
    所述第一数据线连接部、第三数据线连接部和第五数据线连接部被配置为将所述第一数据线、所述第三数据线和所述第五数据线分别与所述第一薄膜晶体管至所述第三薄膜晶体管的漏极连接。
  9. 根据权利要求8所述的阵列基板，其中，所述引线连接部包括第一引线连接部和第二引线连接部；所述第一引线连接部与所述第一控制栅线至第三控制栅线异层设置，且所述第一引线连接部分别与所述第二数据线引线和所述第二引线连接部连接；所述第二引线连接部与所述第四薄膜晶体管至第六薄膜晶体管的源极连接，且所述第二引线连接部与所述第一控制栅线至第三控制栅线同层设置。
  10. 根据权利要求8所述的阵列基板，其中，所述第一薄膜 晶体管至第六薄膜晶体管的栅极与所述第一栅极连接部至第六栅极连接部同层设置。
  11. 根据权利要求8所述的阵列基板，其中，
    所述第一数据线连接部与所述第一数据线和所述第一薄膜晶体管的漏极连接，并且与所述第一控制栅线至第三控制栅线异层设置；
    所述第三数据线连接部包括第一分部、第二分部和第三分部，所述第二分部连接在所述第一分部和所述第三分部之间，其中，所述第一分部与所述第三数据线异层设置，与所述第四数据线交叉设置，并且与所述第三数据线和所述第二分部连接；所述第三分部与所述第一控制栅线至第三控制栅线交叉且异层设置，且与所述第二分部和所述第二薄膜晶体管的漏极连接；
    所述第五数据线连接部与所述第五数据线和所述第三薄膜晶体管的漏极连接，并且与所述第一控制栅线至第三控制栅线交叉且异层设置。
  12. 根据权利要求5或6所述的阵列基板，其中，所述第一薄膜晶体管至第六薄膜晶体管的栅极与所述第一控制栅线至第三控制栅线同层设置，且所述第一薄膜晶体管至第六薄膜晶体管的源极和漏极、所述第一数据线至第六数据线、以及所述第一数据线引线和第二数据线引线与所述第一控制栅线至第三控制栅线异层设置。
  13. 根据权利要求12所述的阵列基板，其中，所述解复用器还包括第一栅极连接部至第六栅极连接部、引线连接部和第一数据线连接部、第三数据线连接部和第五数据线连接部，其中，
    所述第一薄膜晶体管至所述第三薄膜晶体管的栅极分别通过所述第一栅极连接部至所述第三栅极连接部与所述第一控制栅线、所述第三控制栅线和所述第二控制栅线连接；所述第四薄膜 晶体管至所述第六薄膜晶体管的栅极分别通过所述第四栅极连接部至所述第六栅极连接部与所述第二控制栅线、所述第一控制栅线和所述第三控制栅线连接；
    所述引线连接部被配置为将所述第二数据线引线与所述第四薄膜晶体管至第六薄膜晶体管的源极连接；
    所述第一数据线连接部、第三数据线连接部和第五数据线连接部被配置为将所述第一数据线、所述第三数据线和所述第五数据线分别与所述第一薄膜晶体管至所述第三薄膜晶体管的漏极连接。
  14. 根据权利要求13所述的阵列基板，其中，所述引线连接部包括第一引线连接部和第二引线连接部；所述第一引线连接部与所述第一控制栅线至第三控制栅线异层设置，且所述第一引线连接部分别与所述第二数据线引线和所述第二引线连接部连接；所述第二引线连接部与所述第四薄膜晶体管至第六薄膜晶体管的源极连接，且所述第二引线连接部与所述第一控制栅线至第三控制栅线同层设置。
  15. 根据权利要求13所述的阵列基板，其中，所述第一薄膜晶体管至第六薄膜晶体管的栅极与所述第一栅极连接部至第六栅极连接部异层设置。
  16. 根据权利要求13所述的阵列基板，其中，
    所述第一数据线连接部与所述第一数据线和所述第一薄膜晶体管的漏极连接，并且与所述第一控制栅线至第三控制栅线异层设置；
    所述第三数据线连接部包括第一分部、第二分部和第三分部，所述第二分部连接在所述第一分部和所述第三分部之间，其中，所述第一分部与所述第三数据线异层设置，与所述第四数据线交叉设置，并且与所述第三数据线和所述第二分部连接；所述第三 分部与所述第一控制栅线至第三控制栅线交叉且异层设置，且与所述第二分部和所述第二薄膜晶体管的漏极连接；
    所述第五数据线连接部与所述第五数据线和所述第三薄膜晶体管的漏极连接，并且与所述第一控制栅线至第三控制栅线交叉且异层设置。
  17. 根据权利要求4所述的阵列基板，其中，
    所述第一薄膜晶体管至第三薄膜晶体管沿着所述第一控制栅线至第三控制栅线延伸的方向顺序地排列，
    所述第四薄膜晶体管至第六薄膜晶体管沿着所述第一控制栅线至第三控制栅线延伸的方向顺序地排列，并且
    所述第一数据线至第六数据线沿着所述第一控制栅线至第三控制栅线延伸的方向顺序地排列。
  18. 根据权利要求4-6中任一项所述的阵列基板，其中，所述第一薄膜晶体管至第三薄膜晶体管的沟道宽长比之和大于10；所述四薄膜晶体管至第六薄膜晶体管的沟道宽长比之和大于10。
  19. 根据权利要求18所述的阵列基板，其中，所述第一薄膜晶体管的源极和所述第二薄膜晶体管的源极是所述第一薄膜晶体管和所述第二薄膜晶体管共用的第一共用源极；
    所述第四薄膜晶体管的源极和所述第五薄膜晶体管的源极是所述第四薄膜晶体管和所述第五薄膜晶体管共用的第二共用源极。
  20. 根据权利要求19所述的阵列基板，还包括衬底基板、第一绝缘层和第二绝缘层，其中，
    所述第一薄膜晶体管至第六薄膜晶体管的有源层设置在所述衬底基板上；
    所述第一绝缘层设置在所述衬底基板上，且在所述第一薄膜 晶体管至第六薄膜晶体管的有源层上方；
    所述第一薄膜晶体管至第六薄膜晶体管的栅极设置在所述第一绝缘层上；
    所述第二绝缘层设置在所述第一绝缘层上，且在所述第一薄膜晶体管至第六薄膜晶体管的栅极上方；
    所述第一薄膜晶体管至第六薄膜晶体管的源极和漏极、所述第一控制栅线至第三控制栅线、所述第一数据线引线和第二数据线引线、和所述第一数据线至第六数据线设置在所述第二绝缘层上。
  21. 根据权利要求19所述的阵列基板，还包括衬底基板、第一绝缘层和第二绝缘层，其中，
    所述第一薄膜晶体管至第六薄膜晶体管的栅极设置在所述衬底基板上；
    所述第一绝缘层设置在所述衬底基板上，且在所述第一薄膜晶体管至第六薄膜晶体管的栅极上方；
    所述第一薄膜晶体管至第六薄膜晶体管的有源层设置在所述第一绝缘层上；
    所述第二绝缘层设置在所述第一绝缘层上，且在所述第一薄膜晶体管至第六薄膜晶体管的有源层上方；
    所述第一薄膜晶体管至第六薄膜晶体管的源极和漏极、所述第一控制栅线至第三控制栅线、所述第一数据线引线和第二数据线引线、和所述第一数据线至第六数据线设置在所述第二绝缘层上。
  22. 一种显示装置，包括权利要求4-21中任一项所述的阵列基板。
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