WO2023216304A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2023216304A1
WO2023216304A1 PCT/CN2022/094132 CN2022094132W WO2023216304A1 WO 2023216304 A1 WO2023216304 A1 WO 2023216304A1 CN 2022094132 W CN2022094132 W CN 2022094132W WO 2023216304 A1 WO2023216304 A1 WO 2023216304A1
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WO
WIPO (PCT)
Prior art keywords
fan
sub
circuit
area
out wiring
Prior art date
Application number
PCT/CN2022/094132
Other languages
English (en)
French (fr)
Inventor
许作远
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US17/780,040 priority Critical patent/US11961447B2/en
Publication of WO2023216304A1 publication Critical patent/WO2023216304A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel and a display device.
  • display devices are required to be thinner, lighter and have narrower borders to improve the user experience.
  • Figure 1 is a schematic diagram of an exemplary display panel 1', including a display area 2' and a non-display area 3', wherein the non-display area 3' is sequentially provided with a demultiplexer (demux) circuit area 4', Fan-out routing area 5' and bonding area 6'.
  • demultiplexer demux
  • Fan-out routing area 5' Fan-out routing area 5'
  • bonding area 6' bonding area
  • the demultiplexer provided in the demultiplexer circuit area 4' is used to transmit data signals to the data lines in the display panel 1' to match the imbalance in the number of driver chip pins and signal lines in the display area to achieve signal demultiplexing.
  • Time-sharing transmission Since the length of the fan-out traces located on both sides of the fan-out trace area 5' is relatively large, that is, the impedance is relatively large, in order to meet the pixel charging requirements, the size of the demultiplexer circuit area 4' needs to be designed to be larger, resulting in multiple The decomposer circuit area 4' takes up a lot of space, which is not conducive to narrowing the frame.
  • the present application provides a display panel and a display device that can reduce the area occupied by the circuit area and the fan-out wiring area in the non-display area on the basis of meeting the pixel charging requirements to achieve narrow borders.
  • the present application provides a display panel, including a display area and a non-display area arranged around the display area; the non-display area includes a circuit area arranged adjacent to the display area in a first direction; a fan-out wiring area located on the side of the circuit area away from the display area;
  • the fan-out wiring area includes a first fan-out wiring group; the first fan-out wiring group includes a plurality of first fan-out wiring lines whose lengths gradually decrease in a second direction, and the second direction and the first fan-out wiring group include One direction is perpendicular to each other;
  • the circuit area includes a plurality of first sub-circuit areas distributed sequentially in the second direction and connected to a plurality of the first fan-out traces in a one-to-one correspondence; the plurality of first sub-circuit areas are close to the One side of the display area is parallel to the second direction and located on the same straight line, and the width of the plurality of first sub-circuit areas in the first direction gradually decreases in the second direction.
  • the side of the plurality of first sub-circuit areas away from the display area is stepped.
  • each of the first sub-circuit areas is provided with a first demultiplexer circuit; the first demultiplexer circuit includes a corresponding first fan-out wiring circuit. At least two first switching transistors are connected; the number of the first switching transistors in each first sub-circuit area is the same;
  • the channel size of the first switching transistor is positively related to the width of the corresponding first sub-circuit region in the first direction.
  • the non-display area further includes a binding area located in the fan-out wiring area away from the circuit area;
  • the first fan-out trace includes a first trace segment, a second trace segment and a third trace segment connected in sequence; one end of the first trace segment is connected to the corresponding first sub-circuit area, and the other end is connected to the first sub-circuit area.
  • One node is connected to one end of the second wiring segment; the other end of the second wiring segment is connected to one end of the third wiring segment at the second node, and the other end of the third wiring segment is connected to the The above binding area connection;
  • the line segments formed by connecting the first nodes in the plurality of first fan-out routing lines are on the same straight line and the angle between the extending direction and the first direction is an acute angle; the plurality of first fan-out routing lines are The line segments formed by connecting the second nodes in the line are on the same straight line and the angle between the extension direction and the first direction is an acute angle.
  • the fan-out wiring area also includes a second fan-out wiring group arranged side by side with the first fan-out wiring group in the second direction; the first fan-out wiring group The first fan-out wiring group with a smaller length in the wire group is arranged close to the second fan-out wiring group; the second fan-out wiring group includes a length gradually decreasing in the direction toward the first fan-out wiring group. Multiple small second door outgoing lines;
  • the circuit area also includes a plurality of second sub-circuit areas arranged side by side with the plurality of first sub-circuit areas in the second direction; a plurality of the second sub-circuit areas and a plurality of the second sub-circuit areas.
  • the fan-out traces are electrically connected in a one-to-one correspondence; the plurality of second sub-circuit areas and the plurality of first sub-circuit areas are located on the same straight line near the display area, and the plurality of second sub-circuit areas are located on the same straight line.
  • the width of a region in the first direction gradually decreases toward the first sub-circuit region.
  • each second sub-circuit area is provided with a second demultiplexer circuit;
  • the second demultiplexer circuit includes a circuit corresponding to the second fan-out wiring At least two second switching transistors are connected; the number of the second switching transistors in each second sub-circuit area is the same;
  • the channel size of the second switching transistor is positively related to the width of the corresponding second sub-circuit region in the first direction.
  • the first fan-out wiring group and the second fan-out wiring group are axially symmetrical in the first direction, and the plurality of first sub-circuit areas are connected to a plurality of The second sub-circuit area is axially symmetrical in the first direction.
  • the fan-out wiring area also includes a third fan-out wiring group located between the first fan-out wiring group and the second fan-out wiring group; the third fan-out wiring group
  • the fan-out wiring group includes a plurality of third fan-out wiring lines, and the length of any one of the third fan-out wiring lines is shorter than the first fan-out wiring line and the second fan-out wiring line adjacent to the third fan-out wiring group. The length of any one of the fanout traces;
  • the circuit area further includes a plurality of third sub-circuit areas located between the plurality of first sub-circuit areas and the plurality of second sub-circuit areas and distributed in the second direction; a plurality of the The third sub-circuit area is connected to a plurality of third fan-out traces in a one-to-one correspondence;
  • the plurality of third sub-circuit areas are located on the same straight line as the side of the plurality of first sub-circuit areas close to the display area, and the side of the plurality of third sub-circuit areas away from the display area is located on the same straight line. arranged on a straight line and parallel to the second direction; the width of the plurality of third sub-circuit areas in the first direction is smaller than the width of the first sub-circuit areas adjacent to the third sub-circuit area and The width of any one of the second sub-circuit areas in the first direction.
  • each of the third sub-circuit areas is provided with a third demultiplexer circuit; the third demultiplexer circuit includes a corresponding third fan-out wiring circuit. At least two third switching transistors are connected; the number of the third switching transistors in each of the third sub-circuit areas is the same;
  • the channel size of the second switching transistor is positively related to the width of the corresponding third sub-circuit region in the first direction.
  • the number of switching transistors in the first sub-circuit area is equal to the number of switching transistors in the second sub-circuit area, and is equal to the number of switching transistors in the third sub-circuit area.
  • the number of switching transistors is equal.
  • the application also provides a display device, including a display panel and a drive circuit board electrically connected to the display panel;
  • the display panel includes a display area and a non-display area arranged around the display area; the non-display area includes a circuit area arranged adjacent to the display area in a first direction and a circuit area located away from the circuit area.
  • the fan-out wiring area on one side of the display area;
  • the fan-out wiring area includes a first fan-out wiring group; the first fan-out wiring group includes a plurality of first fan-out wiring lines whose lengths gradually decrease in a second direction, and the second direction and the first fan-out wiring group include One direction is perpendicular to each other;
  • the circuit area includes a plurality of first sub-circuit areas distributed sequentially in the second direction and connected to a plurality of the first fan-out traces in a one-to-one correspondence; the plurality of first sub-circuit areas are close to the One side of the display area is parallel to the second direction and located on the same straight line, and the width of the plurality of first sub-circuit areas in the first direction gradually decreases in the second direction;
  • the driving circuit board is electrically connected to a side of the first fan-out wiring group away from the circuit area.
  • the side of the plurality of first sub-circuit areas away from the display area is stepped.
  • each first sub-circuit area is provided with a first demultiplexer circuit; the first demultiplexer circuit includes a circuit corresponding to the first fan-out wiring. At least two first switching transistors are connected; the number of the first switching transistors in each first sub-circuit area is the same;
  • the channel size of the first switching transistor is positively related to the width of the corresponding first sub-circuit region in the first direction.
  • the non-display area further includes a binding area located in the fan-out wiring area away from the circuit area;
  • the first fan-out trace includes a first trace segment, a second trace segment and a third trace segment connected in sequence; one end of the first trace segment is connected to the corresponding first sub-circuit area, and the other end is connected to the first sub-circuit area.
  • One node is connected to one end of the second wiring segment; the other end of the second wiring segment is connected to one end of the third wiring segment at the second node, and the other end of the third wiring segment is connected to the The above binding area connection;
  • the line segments formed by connecting the first nodes in the plurality of first fan-out routing lines are on the same straight line and the angle between the extending direction and the first direction is an acute angle; the plurality of first fan-out routing lines are The line segments formed by connecting the second nodes in the line are on the same straight line and the angle between the extension direction and the first direction is an acute angle.
  • the fan-out wiring area also includes a second fan-out wiring group arranged side by side with the first fan-out wiring group in the second direction; the first fan-out wiring group The first fan-out wiring group with a smaller length in the wire group is arranged close to the second fan-out wiring group; the second fan-out wiring group includes a length gradually decreasing in the direction toward the first fan-out wiring group. Multiple small second door outgoing lines;
  • the circuit area also includes a plurality of second sub-circuit areas arranged side by side with the plurality of first sub-circuit areas in the second direction; a plurality of the second sub-circuit areas and a plurality of the second sub-circuit areas.
  • the fan-out traces are electrically connected in a one-to-one correspondence; the plurality of second sub-circuit areas and the plurality of first sub-circuit areas are located on the same straight line near the display area, and the plurality of second sub-circuit areas are located on the same straight line.
  • the width of a region in the first direction gradually decreases toward the first sub-circuit region.
  • each second sub-circuit area is provided with a second demultiplexer circuit; the second demultiplexer circuit includes a corresponding second fan-out wiring circuit. At least two second switching transistors are connected; the number of the second switching transistors in each second sub-circuit area is the same;
  • the channel size of the second switching transistor is positively related to the width of the corresponding second sub-circuit region in the first direction.
  • the first fan-out wiring group and the second fan-out wiring group are axially symmetrical in the first direction, and the plurality of first sub-circuit areas and the plurality of The second sub-circuit area is axially symmetrical in the first direction.
  • the fan-out wiring area also includes a third fan-out wiring group located between the first fan-out wiring group and the second fan-out wiring group; the third fan-out wiring group
  • the fan-out wiring group includes a plurality of third fan-out wiring lines, and the length of any one of the third fan-out wiring lines is shorter than the first fan-out wiring line and the second fan-out wiring line adjacent to the third fan-out wiring group. The length of any one of the fanout traces;
  • the circuit area further includes a plurality of third sub-circuit areas located between the plurality of first sub-circuit areas and the plurality of second sub-circuit areas and distributed in the second direction; a plurality of the The third sub-circuit area is connected to a plurality of third fan-out traces in a one-to-one correspondence;
  • the plurality of third sub-circuit areas are located on the same straight line as the side of the plurality of first sub-circuit areas close to the display area, and the side of the plurality of third sub-circuit areas away from the display area is located on the same straight line. arranged on a straight line and parallel to the second direction; the width of the plurality of third sub-circuit areas in the first direction is smaller than the width of the first sub-circuit areas adjacent to the third sub-circuit area and The width of any one of the second sub-circuit areas in the first direction.
  • each third sub-circuit area is provided with a third demultiplexer circuit; the third demultiplexer circuit includes a circuit corresponding to the third fan-out wiring. At least two third switching transistors are connected; the number of the third switching transistors in each of the third sub-circuit areas is the same;
  • the channel size of the second switching transistor is positively related to the width of the corresponding third sub-circuit region in the first direction.
  • the number of switching transistors in the first sub-circuit area is equal to the number of switching transistors in the second sub-circuit area, and is equal to the number of switching transistors in the third sub-circuit area.
  • the number of switching transistors is equal.
  • the length of the multiple first fan-out traces in the fan-out trace area gradually decreases in the second direction, that is, the impedance gradually decreases, which can meet the pixel charging requirements.
  • the width of the plurality of first sub-circuit areas corresponding to the plurality of first fan-out traces in the circuit area in the first direction gradually decreases in the second direction, so that the side of the circuit area away from the display area It is in a concave shape, which effectively reduces the area occupied by the circuit area, allowing the fan-out wiring area to move toward the display area, which is conducive to achieving narrower borders.
  • Figure 1 is a schematic structural diagram of an exemplary display panel.
  • FIG. 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 3 is an enlarged schematic diagram of the circuit area, fan-out routing area and bonding area in Figure 2.
  • FIG. 4 is a schematic diagram of a first demultiplexer circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a second demultiplexer circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a third demultiplexer circuit provided by an embodiment of the present application.
  • FIG. 7 is a comparison diagram of the total height of the circuit area, fan-out wiring area, and binding area in the display panel provided by the embodiment of the present application and the exemplary display panel provided in FIG. 1 .
  • FIG. 8 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • features defined as “first” and “second” may explicitly or implicitly include one or more of the described features.
  • “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be mechanical connection, electrical connection or mutual communication; it can be direct connection, or indirect connection through an intermediary, it can be internal connection of two elements or interaction of two elements relation.
  • the term “above” or “below” a first feature on a second feature may include direct contact between the first and second features, or may also include the first and second features. Not in direct contact but through additional characteristic contact between them.
  • the terms “above”, “above” and “above” a first feature on a second feature include the first feature being directly above and diagonally above the second feature, or simply mean that the first feature is higher in level than the second feature.
  • “Below”, “under” and “under” the first feature is the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature is less horizontally than the second feature.
  • the size of the demultiplexer circuit area 4' is designed to be larger, and the width of the demultiplexer circuit area 4' in the first direction is the same everywhere, for example, the width is W1, resulting in that the demultiplexer circuit area 4' occupies The space is large, which is not conducive to achieving narrow borders.
  • an embodiment of the present application provides a display panel 1.
  • the display panel 1 includes a display area 2 and a non-display area 3 arranged around the display area 2; the non-display area 3 includes The circuit area 4 is arranged adjacent to the display area 2 in a first direction (for example, the vertical downward direction) and the fan-out wiring area 5 is located on the side of the circuit area 4 away from the display area 2; the fan-out wiring area 5 includes a third One fan-out wiring group 6; the first fan-out wiring group 6 includes a plurality of first fan-out wiring lines 7 whose length gradually decreases (that is, the impedance gradually decreases) in the second direction (for example, the horizontal rightward direction).
  • the circuit area 4 includes a plurality of first sub-circuit areas 8 that are sequentially distributed in the second direction and connected to a plurality of first fan-out lines 7 in one-to-one correspondence; a plurality of first sub-circuits
  • the side of the area 8 close to the display area 2 is parallel to the second direction and located on the same straight line, and the width W of the plurality of first sub-circuit areas 8 in the first direction gradually decreases in the second direction.
  • the length of the fan-out traces in the fan-out trace area is positively related to the impedance.
  • the height of the plurality of first fan-out traces 7 in the first direction gradually increases in the second direction.
  • each first sub-circuit area 8 is provided with a first demultiplexer circuit 9; the first demultiplexer circuit 9 includes electrical circuits connected to the corresponding first fan-out wiring 7. At least two first switching transistors T1 are connected; the number of first switching transistors T1 in each first sub-circuit area 8 is the same; the channel size (for example, channel length) of the first switching transistor T1 is the same as that of the corresponding first switching transistor T1. The width of the sub-circuit area 8 in the first direction is positively correlated. It should be noted that the embodiment of the present application does not limit the number of the first switching transistors T1 in the first demultiplexer circuit 9. For convenience of description, the embodiment of the present application takes two first switching transistors T1 as an example. describe.
  • each first demultiplexer circuit 9 includes two first switching transistors T1 and two electrically connected gate electrodes of the two first switching transistors T1 in a one-to-one correspondence.
  • control signal lines CK1, CK2; the first poles of the two first switching transistors T1 are electrically connected to the two data lines (D(m), D(m+a)) of the display area 2 respectively, m and a is a positive integer, and the second poles of the two first switching transistors T1 are electrically connected to the same first fan-out line 7 (for example, S(m)).
  • the plurality of first sub-circuit areas 8 share two control signal lines (CK1, CK2); the first electrode is either the source electrode or the drain electrode, and the second electrode is different from the source electrode or the drain electrode.
  • the first demultiplexer circuit 9 can transmit the data signal on the corresponding first fan-out line 7 to two different data lines in a time-sharing manner.
  • the size of the first sub-circuit area 8 corresponding to it (for example, in the direction perpendicular to the display panel 1 (projected area) is designed to be larger; for the first fan-out trace 7 with smaller impedance, the size of the first sub-circuit area 8 correspondingly connected to it can be designed to be smaller, as long as it meets the pixel charging requirements. Since the impedance of the plurality of first fan-out traces 7 in the first fan-out trace group 6 gradually decreases in the second direction, the size of the corresponding plurality of first sub-circuit areas 8 in the second direction gradually decreases. It can be understood that the size of the first sub-circuit area 8 of the present application matches the impedance of the corresponding first fan-out trace 7 to meet the pixel charging requirements.
  • the side of the plurality of first sub-circuit areas 8 close to the display area 2 is parallel to the second direction and located on the same straight line, and the plurality of first sub-circuit areas 8 in the first direction are parallel to each other.
  • the side of the circuit area 4 away from the display area 2 faces the direction of the display area 2 Concave.
  • the area of the circuit area 4 in this application is effectively reduced, so that the position of the fan-out wiring area 5 can face the display area 2 direction, thereby reducing the area of the non-display area 3 occupied by the circuit area 4 and the fan-out wiring area 5, which is beneficial to reducing the lower frame.
  • the side of the plurality of first sub-circuit areas 8 away from the display area 2 is in a stepped shape; the length of the side of each first sub-circuit area 8 close to the display area 2 is equal, and each first sub-circuit area 8 has the same length.
  • the lengths of the sides of the circuit area 8 away from the display area 2 are equal. It can be understood that the side of each first sub-circuit area 8 away from the display area 2 is parallel to the second direction.
  • the non-display area 3 also includes a binding area 10 located in the fan-out wiring area 5 away from the circuit area 4;
  • the first fan-out wiring 7 includes a first wiring segment 11 and a second wiring segment connected in sequence.
  • Line segment 12 and third line segment 13; one end of the first line segment 11 is connected to the corresponding first sub-circuit area 8, and the other end is connected to one end of the second line segment 12 at the first node P;
  • the second line segment 12 The other end of is connected to one end of the third wiring segment 13 at the second node Q, and the other end of the third wiring segment 13 is connected to the binding area 10;
  • the first nodes P among the plurality of first fan-out wirings 7 are connected to each other.
  • the formed line segments are located on the same straight line, and the angle between the extending direction and the first direction is an acute angle; the line segments formed by connecting the second nodes Q in the plurality of first fan-out traces 7 are located on the same straight line, and the extending direction is at an acute angle with the first direction.
  • the angle between one direction is an acute angle.
  • the extension direction of the first wiring segment 11 and the third wiring segment 13 is parallel to the first direction
  • the angle between the second wiring segment 12 and the first wiring segment 11 is an obtuse angle
  • the second wiring segment 12 is an obtuse angle
  • the angle between the line segment 12 and the third wiring segment 13 is an obtuse angle.
  • the angle at which the extension direction of the second wiring segment 12 of the first fan-out wiring 7 deviates from the first direction or the pitch between the plurality of first fan-out wiring 7 can be adjusted to make the plurality of first fan-out wirings 7
  • the line segments formed by connecting the first nodes P in the fan out wiring 7 are on the same straight line, and the angle between the extension direction and the first direction is an acute angle.
  • the fan-out wiring area 5 also includes a second fan-out wiring group 14 arranged side by side with the first fan-out wiring group 6 in the second direction; the longer fan-out wiring group 6 in the first fan-out wiring group 6
  • the small first fan-out routing wires 7 are arranged close to the second fan-out routing wire group 14; the second fan-out routing wire group 14 includes a plurality of second fan-out routing wires whose lengths gradually decrease in the direction toward the first fan-out routing wire group 6 15.
  • the circuit area 4 also includes a plurality of second sub-circuit areas 16 arranged side by side with the plurality of first sub-circuit areas 8 in the second direction; a plurality of second sub-circuit areas 16 and a plurality of second fan-out traces. 15 are electrically connected in a one-to-one correspondence; the plurality of second sub-circuit areas 16 and the plurality of first sub-circuit areas 8 are located on the same straight line near the display area 2, and the plurality of second sub-circuit areas 16 are in the first direction.
  • the width gradually decreases in the direction toward the first sub-circuit area 8 .
  • each second sub-circuit area 16 is provided with a second demultiplexer circuit 17; the second demultiplexer circuit 17 includes electrical circuits connected to the corresponding second fan-out wiring 15. At least two second switching transistors T2 are connected; the number of second switching transistors T2 in each second sub-circuit area 16 is the same; the channel size of the second switching transistor T2 is the same as that of the corresponding second sub-circuit area 16 in the first The width in one direction is positively related.
  • each second demultiplexer circuit 17 includes two second switching transistors T2 and two control signal lines (CK1) electrically connected to the gates of the two second switching transistors T2 in one-to-one correspondence. , CK2); the first poles of the two second switching transistors T2 are electrically connected to the two data lines (D(n), D(n+b)) of the display area 2 respectively, n and b are positive integers, and The second poles of the two second switching transistors T2 are electrically connected to the same second fan-out line 15 (for example, S(n)).
  • the plurality of second sub-circuit areas 16 share two control signal lines (CK1, CK2).
  • the second demultiplexer circuit 17 can transmit the data signal on the corresponding second fan-out line 15 to two different data lines in a time-sharing manner.
  • first fan-out wiring group 6 and the second fan-out wiring group 14 are axially symmetrical in the first direction
  • the plurality of first sub-circuit areas 8 and the plurality of second sub-circuit areas 16 are axially symmetrical in the first direction.
  • Symmetry; the number of first switching transistors T1 in the first demultiplexer circuit 9 and the number of second switching transistors T2 in the second demultiplexer circuit 17 are the same.
  • the plurality of second fan-out traces 15 and the plurality of first fan-out traces 7 are axially symmetrical in the first direction. Specifically, the lengths of the plurality of second fan-out wiring lines 15 gradually decrease in the direction toward the first fan-out wiring group 6; and the heights of the plurality of second fan-out wiring lines 15 in the first direction increase toward the first fan-out wiring group 6. The direction of the outlet wiring group 6 gradually increases.
  • the fan-out wiring area 5 also includes a third fan-out wiring group 18 located between the first fan-out wiring group 6 and the second fan-out wiring group 14;
  • the outgoing wire group 18 includes a plurality of third fan outgoing wires 19.
  • the length of any third fan outgoing wire 19 is shorter than the first fan outgoing wire 7 and the second fan outgoing wire 15 adjacent to the third fan outgoing wire group 18. the length of any one of them.
  • the circuit area 4 also includes a plurality of third sub-circuit areas 20 located between the plurality of first sub-circuit areas 8 and the plurality of second sub-circuit areas 16 and distributed in the second direction; a plurality of third sub-circuit areas 20 .
  • the circuit area 20 is connected to the plurality of third fan-out traces 19 in a one-to-one correspondence; the plurality of third sub-circuit areas 20 are located on the same straight line as the side of the plurality of first sub-circuit areas 8 close to the display area 2, and the plurality of third sub-circuit areas 20 are connected in a one-to-one correspondence.
  • the side of the sub-circuit area 20 away from the display area 2 is located on the same straight line and is arranged parallel to the second direction; the width of the plurality of third sub-circuit areas 20 in the first direction is smaller than that of the first adjacent third sub-circuit area 20 The width of any one of the sub-circuit area 8 and the second sub-circuit area 16 in the first direction.
  • the area occupied by the plurality of first sub-circuit areas 8 may be called In the first circuit area 22, the area occupied by the plurality of second sub-circuit areas 16 is called the second circuit area 23, and the area occupied by the plurality of third sub-circuit areas 20 is called the third circuit area 24; wherein, The first circuit area 22, the third circuit area 24 and the second circuit area 23 are adjacent in sequence.
  • each third sub-circuit area 20 is provided with a third demultiplexer circuit 21; the third demultiplexer circuit 21 includes an electrical circuit connected to the corresponding third fan-out trace 19. At least two third switching transistors T3 are connected; the number of third switching transistors T3 in each third sub-circuit area 20 is the same.
  • the channel size of the second switching transistor T2 is positively related to the width of the corresponding third sub-circuit region 20 in the first direction; and the channel size of the second switching transistor T2 is larger than the channel size of any first switching transistor T1 The size and the channel size of any one of the second switching transistors T2 are small.
  • the number of third switching transistors T3 in the third demultiplexer circuit 21 is the same as the number of second switching transistors T2 in the second demultiplexer circuit 17 .
  • the third demultiplexer circuit 21 shares two control signal lines with the second demultiplexer circuit 17 and the first demultiplexer circuit 9 .
  • each third demultiplexer circuit 21 includes two third switching transistors T3 and two control signal lines (CK1) electrically connected to the gates of the two third switching transistors T3 in one-to-one correspondence. , CK2); the first poles of the two third switching transistors T3 are electrically connected to the two data lines (D(k), D(k+c)) of the display area 2 respectively, k and c are positive integers, and The second poles of the two third switching transistors T3 are electrically connected to the same third fan-out line 19 (for example, S(k)).
  • the plurality of third sub-circuit areas 20 share two control signal lines (CK1, CK2).
  • the third demultiplexer circuit 21 can transmit the data signal on the corresponding third fan-out line 19 to two different data lines in a time-sharing manner.
  • the impedances of the plurality of third fan-out traces 19 are the same; in another specific implementation, the impedances of the plurality of third fan-out traces 19 may be different, which is not limited in this application.
  • the circuit area 4 and the fan-out wiring area 5 have the same symmetry axis L; wherein, a plurality of first sub-circuit areas 8 and a plurality of second sub-circuit areas 16 are symmetrical about the symmetry axis L, and The plurality of third sub-circuit areas 20 are symmetrical about the symmetry axis L; the first fan-out wiring group 6 and the second fan-out wiring group 14 are symmetrical about the symmetry axis L, and the plurality of third fan-out wiring groups 18 in the third fan-out wiring group 18 are symmetrical about the symmetry axis L.
  • the outgoing trace 19 is symmetrical about the axis of symmetry L.
  • the first switching transistor T1, the second switching transistor T2 and the third switching transistor T3 are all thin film transistors.
  • the binding area 10 is used for binding driver ICs or flexible circuit boards; the binding area 10 includes a plurality of first fan-out traces 7 , a plurality of second fan-out traces 15 and a plurality of third fan-out traces 19 A plurality of binding pads are connected in one-to-one correspondence at one end away from the circuit area 4 .
  • the total height of the circuit area 4, the fan-out wiring area 5 and the binding area 10 in the first direction in the embodiment of the present application is the same as the circuit area 4', the fan-out wiring area 5 shown in Figure 1
  • the difference between ' and the total height of the binding area 6 ' in the first direction is ⁇ W.
  • ⁇ W W1-W2; where W1 is the maximum width of the circuit area 4 in the first direction, and W2 is the minimum width of the circuit area 4 in the first direction.
  • W1 is the maximum width of the circuit area 4 in the first direction
  • W2 is the minimum width of the circuit area 4 in the first direction.
  • the value of ⁇ W is not limited to this, and is specifically determined by the layout of the fan-out traces in fan-out trace area 5.
  • the width of the circuit area 4 composed of the first sub-circuit area 8, the second sub-circuit area 16 and the third sub-circuit area 20 in the first direction gradually increases from both sides in the direction of the symmetry axis L.
  • Reduction for example, the width is reduced from W1 to W2
  • the side of the circuit area 4 away from the display area 2 is concave, which effectively reduces the area occupied by the circuit area 4 on the basis of meeting the pixel charging requirements, so that
  • the fan-out wiring area 5 can move toward the display area 2, which is beneficial to achieving narrow bezels.
  • the circuit area 4 is only composed of the first sub-circuit area 8 and the second sub-circuit area 16; correspondingly, the fan-out wiring area 5 is only composed of The first fan-out wiring group 6 and the second fan-out wiring group 14 are composed.
  • the circuit area 4 can also be composed of only the first sub-circuit area 8 or the second sub-circuit area 16.
  • the fan-out wiring area 5 can only be composed of the first fan-out wiring group 6 or the second sub-circuit area 16. Two fan outgoing wiring groups 14 are formed.
  • the side of the circuit area 4 away from the display area 2 is concave toward the side facing the display area 2, so that the fan-out wiring area 5 can move toward the display area 2, which is beneficial to realizing a narrow frame of the display panel 1. change.
  • this application also provides a display device 25 .
  • the display device 25 includes the display panel 1 in the previous embodiment and a drive circuit board 26 electrically connected to the display panel 1 .
  • the driving circuit board 26 is electrically connected to the side of the first fan-out wiring group, the second fan-out wiring group and the third fan-out wiring group in the fan-out wiring area 5 away from the circuit area 4 .
  • the driving circuit board 26 provides data signals to the data lines of the display area 2 through the fan-out wiring of the fan-out wiring area 5 and the demultiplexer circuit of the circuit area 4 .
  • the drive circuit board 26 is a drive IC or a flexible circuit board, and is bound and connected to the binding area 10 to realize the electrical connection of the fan-out wiring with the fan-out wiring area 5 .
  • the width of the circuit area 4 in the first direction gradually decreases from both sides to the middle direction, so that the side of the circuit area 4 away from the display area 2 is concave, on the basis of meeting the pixel charging requirements. , effectively reducing the area occupied by the circuit area 4, so that the fan-out wiring area 5 can move toward the direction of the display area 2, which is beneficial to achieving a narrow frame of the display device 25.

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Abstract

一种显示面板（1）和显示装置（25），包括显示区（2）和非显示区（3）；非显示区（3）包括沿第一方向与显示区（2）依次并排设置的电路区（4）和扇出走线区（5）；扇出走线区（5）包括在和第一方向垂直的第二方向上长度逐渐减小的多条第一扇出走线（7）；电路区包括与多条第一扇出走线（7）一一对应的多个第一子电路区（8）；多个第一子电路区（8）在第一方向上的宽度W沿第二方向逐渐减小。

Description

显示面板和显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板和显示装置。
 背景技术
随着显示技术的发展，显示装置要求轻薄化、窄边框，以提升用户的使用体验。
图1是一种示例性的显示面板1’的示意图，包括显示区2’和非显示区3’，其中，非显示区3’中依次设置有多路分解器（demux）电路区4’、扇出走线区5’和绑定区6’。通常，多路分解器电路区4’、扇出走线区5’以及绑定区6’所在的非显示区成为下边框区。
其中，多路分解器电路区4’中设置的多路分解器用于向显示面板1’中的数据线传输数据信号，以匹配驱动芯片引脚与显示区内信号线的数量失衡，实现信号的分时传输。由于扇出走线区5’中位于两侧的扇出走线的长度较大，即阻抗较大，为了满足像素充电需求，需要将多路分解器电路区4’的尺寸设计较大，导致多路分解器电路区4’占用空间较多，不利于实现窄边框化。
 技术问题
本申请提供一种显示面板和显示装置，可以在满足像素充电需求的基础上，减小非显示区的电路区和扇出走线区占据的面积，以实现窄边框化。
 技术解决方案
第一方面，本申请提供一种显示面板，包括显示区以及围绕所述显示区设置的非显示区；所述非显示区包括在第一方向上与所述显示区相邻设置的电路区以及位于所述电路区远离所述显示区一侧的扇出走线区；
所述扇出走线区包括第一扇出走线组；所述第一扇出走线组包括在第二方向上长度逐渐减小的多条第一扇出走线，所述第二方向和所述第一方向相互垂直；
所述电路区包括在所述第二方向上依次分布且与多条所述第一扇出走线一一对应连接的多个第一子电路区；多个所述第一子电路区靠近所述显示区的一边与所述第二方向平行且位于同一条直线上，且多个所述第一子电路区在所述第一方向上的宽度在所述第二方向上逐渐减小。
在本申请所提供的显示面板中，多个所述第一子电路区远离所述显示区的一侧呈阶梯状。
在本申请所提供的显示面板中，每个所述第一子电路区设有一第一多路分解器电路；所述第一多路分解器电路包括与对应的所述第一扇出走线电连接的至少两个第一开关晶体管；每个所述第一子电路区中的所述第一开关晶体管的数量相同；
所述第一开关晶体管的沟道尺寸与对应的所述第一子电路区在所述第一方向上的宽度正向相关。
在本申请所提供的显示面板中，所述非显示区还包括位于所述扇出走线区远离所述电路区的绑定区；
所述第一扇出走线包括依次连接的第一走线段、第二走线段和第三走线段；所述第一走线段的一端和对应的所述第一子电路区连接，另一端在第一节点处与所述第二走线段的一端连接；所述第二走线段的另一端在第二节点处与所述第三走线段的一端连接，所述第三走线段的另一端与所述绑定区连接；
多条所述第一扇出走线中的所述第一节点相互连接形成的线段位于同一直线上且延伸方向与所述第一方向之间的夹角为锐角；多条所述第一扇出走线中的所述第二节点相互连接形成的线段位于同一直线上且延伸方向与所述第一方向之间的夹角为锐角。
在本申请所提供的显示面板中，所述扇出走线区还包括在所述第二方向上与所述第一扇出走线组并排设置的第二扇出走线组；所述第一扇出走线组中长度较小的所述第一扇出走线靠近所述第二扇出走线组设置；所述第二扇出走线组包括在朝所述第一扇出走线组的方向上长度逐渐减小的多条第二扇出走线；
所述电路区还包括在所述第二方向上与所述多个第一子电路区并排设置的多个第二子电路区；多个所述第二子电路区与多个所述第二扇出走线一一对应电连接；多个所述第二子电路区与多个所述第一子电路区靠近所述显示区的一边位于同一条直线上，且多个所述第二子电路区在所述第一方向上的宽度在朝所述第一子电路区的方向上逐渐减小。
在本申请所提供的显示面板中，每个所述第二子电路区设有一第二多路分解器电路；所述第二多路分解器电路包括与对应的所述第二扇出走线电连接的至少两个第二开关晶体管；每个所述第二子电路区中的所述第二开关晶体管的数量相同；
所述第二开关晶体管的沟道尺寸与对应的所述第二子电路区的在所述第一方向上的宽度正向相关。
在本申请所提供的显示面板中，所述第一扇出走线组和所述第二扇出走线组在所述第一方向上轴对称，且多个所述第一子电路区与多个所述第二子电路区在所述第一方向上轴对称。
在本申请所提供的显示面板中，所述扇出走线区还包括位于所述第一扇出走线组和所述第二扇出走线组之间的第三扇出走线组；所述第三扇出走线组包括多条第三扇出走线，任意一条所述第三扇出走线的长度小于与所述第三扇出走线组相邻设置的所述第一扇出走线和所述第二扇出走线中的任意一个的长度；
所述电路区还包括位于所述多个第一子电路区和所述多个第二子电路区之间且在所述第二方向上分布的多个第三子电路区；多个所述第三子电路区与多个所述第三扇出走线一一对应连接；
多个所述第三子电路区与多个所述第一子电路区靠近所述显示区的一边位于同一直线上，且多个所述第三子电路区远离所述显示区的一边位于同一直线上且与所述第二方向平行设置；多个所述第三子电路区在所述第一方向上的宽度小于与所述第三子电路区相邻的所述第一子电路区和所述第二子电路区中任意一个在所述第一方向上的宽度。
在本申请所提供的显示面板中，每个所述第三子电路区设有一第三多路分解器电路；所述第三多路分解器电路包括与对应的所述第三扇出走线电连接的至少两个第三开关晶体管；每个所述第三子电路区中的所述第三开关晶体管的数量相同；
所述第二开关晶体管的沟道尺寸与对应的所述第三子电路区的在所述第一方向上的宽度正向相关。
在本申请所提供的显示面板中，所述第一子电路区中的开关晶体管的数量与所述第二子电路区中的开关晶体管的数量相等，且与所述第三子电路区中的开关晶体管的数量相等。
第二方面，本申请还提供一种显示装置，包括显示面板和与所述显示面板电连接的驱动电路板；
所述显示面板包括显示区以及围绕所述显示区设置的非显示区；所述非显示区包括在第一方向上与所述显示区相邻设置的电路区以及位于所述电路区远离所述显示区一侧的扇出走线区；
所述扇出走线区包括第一扇出走线组；所述第一扇出走线组包括在第二方向上长度逐渐减小的多条第一扇出走线，所述第二方向和所述第一方向相互垂直；
所述电路区包括在所述第二方向上依次分布且与多条所述第一扇出走线一一对应连接的多个第一子电路区；多个所述第一子电路区靠近所述显示区的一边与所述第二方向平行且位于同一条直线上，且多个所述第一子电路区在所述第一方向上的宽度在所述第二方向上逐渐减小；
所述驱动电路板与所述第一扇出走线组远离所述电路区的一侧电连接。
在本申请所提供的显示装置中，多个所述第一子电路区远离所述显示区的一侧呈阶梯状。
在本申请所提供的显示装置中，每个所述第一子电路区设有一第一多路分解器电路；所述第一多路分解器电路包括与对应的所述第一扇出走线电连接的至少两个第一开关晶体管；每个所述第一子电路区中的所述第一开关晶体管的数量相同；
所述第一开关晶体管的沟道尺寸与对应的所述第一子电路区在所述第一方向上的宽度正向相关。
在本申请所提供的显示装置中，所述非显示区还包括位于所述扇出走线区远离所述电路区的绑定区；
所述第一扇出走线包括依次连接的第一走线段、第二走线段和第三走线段；所述第一走线段的一端和对应的所述第一子电路区连接，另一端在第一节点处与所述第二走线段的一端连接；所述第二走线段的另一端在第二节点处与所述第三走线段的一端连接，所述第三走线段的另一端与所述绑定区连接；
多条所述第一扇出走线中的所述第一节点相互连接形成的线段位于同一直线上且延伸方向与所述第一方向之间的夹角为锐角；多条所述第一扇出走线中的所述第二节点相互连接形成的线段位于同一直线上且延伸方向与所述第一方向之间的夹角为锐角。
在本申请所提供的显示装置中，所述扇出走线区还包括在所述第二方向上与所述第一扇出走线组并排设置的第二扇出走线组；所述第一扇出走线组中长度较小的所述第一扇出走线靠近所述第二扇出走线组设置；所述第二扇出走线组包括在朝所述第一扇出走线组的方向上长度逐渐减小的多条第二扇出走线；
所述电路区还包括在所述第二方向上与所述多个第一子电路区并排设置的多个第二子电路区；多个所述第二子电路区与多个所述第二扇出走线一一对应电连接；多个所述第二子电路区与多个所述第一子电路区靠近所述显示区的一边位于同一条直线上，且多个所述第二子电路区在所述第一方向上的宽度在朝所述第一子电路区的方向上逐渐减小。
在本申请所提供的显示装置中，每个所述第二子电路区设有一第二多路分解器电路；所述第二多路分解器电路包括与对应的所述第二扇出走线电连接的至少两个第二开关晶体管；每个所述第二子电路区中的所述第二开关晶体管的数量相同；
所述第二开关晶体管的沟道尺寸与对应的所述第二子电路区的在所述第一方向上的宽度正向相关。
在本申请所提供的显示装置中，所述第一扇出走线组和所述第二扇出走线组在所述第一方向上轴对称，且多个所述第一子电路区与多个所述第二子电路区在所述第一方向上轴对称。
在本申请所提供的显示装置中，所述扇出走线区还包括位于所述第一扇出走线组和所述第二扇出走线组之间的第三扇出走线组；所述第三扇出走线组包括多条第三扇出走线，任意一条所述第三扇出走线的长度小于与所述第三扇出走线组相邻设置的所述第一扇出走线和所述第二扇出走线中的任意一个的长度；
所述电路区还包括位于所述多个第一子电路区和所述多个第二子电路区之间且在所述第二方向上分布的多个第三子电路区；多个所述第三子电路区与多个所述第三扇出走线一一对应连接；
多个所述第三子电路区与多个所述第一子电路区靠近所述显示区的一边位于同一直线上，且多个所述第三子电路区远离所述显示区的一边位于同一直线上且与所述第二方向平行设置；多个所述第三子电路区在所述第一方向上的宽度小于与所述第三子电路区相邻的所述第一子电路区和所述第二子电路区中任意一个在所述第一方向上的宽度。
在本申请所提供的显示装置中，每个所述第三子电路区设有一第三多路分解器电路；所述第三多路分解器电路包括与对应的所述第三扇出走线电连接的至少两个第三开关晶体管；每个所述第三子电路区中的所述第三开关晶体管的数量相同；
所述第二开关晶体管的沟道尺寸与对应的所述第三子电路区的在所述第一方向上的宽度正向相关。
在本申请所提供的显示装置中，所述第一子电路区中的开关晶体管的数量与所述第二子电路区中的开关晶体管的数量相等，且与所述第三子电路区中的开关晶体管的数量相等。
 有益效果
相较于现有技术，本申请提供的显示面板和显示装置，扇出走线区的多条第一扇出走线在第二方向上长度逐渐减小，即阻抗逐渐减小，在满足像素充电需求的基础上，电路区中与多条第一扇出走线对应连接的多个第一子电路区在第一方向上的宽度在第二方向上逐渐减小，使得电路区远离显示区的一侧呈内凹状，有效的减小了电路区占据的面积，使得扇出走线区可以朝向显示区的方向移动，有利于实现窄边框化。
 附图说明
图1为一种示例性的显示面板的结构示意图。
图2为本申请实施例提供的显示面板的结构示意图。
图3为图2中电路区、扇出走线区和绑定区的放大示意图。
图4为本申请实施例提供的第一多路分解器电路的示意图。
图5为本申请实施例提供的第二多路分解器电路的示意图。
图6为本申请实施例提供的第三多路分解器电路的示意图。
图7为本申请实施例提供的显示面板与图1提供的示例性的显示面板中的电路区、扇出走线区和绑定区的总高度对比图。
图8为本申请实施例提供的一种显示装置的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
在图1所示的一种示例性的显示面板1’中，由于扇出走线区5’中位于两侧的扇出走线的长度较大，即阻抗较大，为了满足像素充电需求，通常将多路分解器电路区4’的尺寸设计较大，且该多路分解器电路区4’在第一方向上的宽度处处相等，例如宽度为W1，导致多路分解器电路区4’占据的空间较大，不利于实现窄边框化。
如图2和图3所示，为了解决上述问题，本申请实施例提供了一种显示面板1，显示面板1包括显示区2以及围绕显示区2设置的非显示区3；非显示区3包括在第一方向（例如竖直向下的方向）上与显示区2相邻设置的电路区4以及位于电路区4远离显示区2一侧的扇出走线区5；扇出走线区5包括第一扇出走线组6；第一扇出走线组6包括在第二方向（例如水平向右的方向）上长度逐渐减小（即阻抗逐渐减小）的多条第一扇出走线7，第二方向和第一方向相互垂直；电路区4包括在第二方向上依次分布且与多条第一扇出走线7一一对应连接的多个第一子电路区8；多个第一子电路区8靠近显示区2的一边与第二方向平行且位于同一条直线上，且多个第一子电路区8在第一方向上的宽度W在第二方向上逐渐减小。
需要说明的是，本申请中，扇出走线区的扇出走线的长度与阻抗正向相关。
可以理解的，多条第一扇出走线7在第一方向上的高度在第二方向上逐渐增大。
具体的，如图3和图4所示，每个第一子电路区8设有一第一多路分解器电路9；第一多路分解器电路9包括与对应的第一扇出走线7电连接的至少两个第一开关晶体管T1；每个第一子电路区8中的第一开关晶体管T1的数量相同；第一开关晶体管T1的沟道尺寸（例如沟道长度）与对应的第一子电路区8在第一方向上的宽度正向相关。需要说明的是，本申请实施例对第一多路分解器电路9中的第一开关晶体管T1的数量不做限制，为方便描述，本申请实施例以两个第一开关晶体管T1为例进行描述。
可以理解的，第一子电路区8在第一方向上的宽度越大，则其面积越大，且对应的第一开关晶体管T1的的沟道尺寸越大。
在一具体实施方式中，如图4所示，每个第一多路分解器电路9包括两个第一开关晶体管T1以及与两个第一开关晶体管T1的栅极一一对应电连接的两条控制信号线（CK1，CK2）；两个第一开关晶体管T1的第一极分别与显示区2的两条数据线（D(m)，D(m+a)）对应电连接，m和a为正整数，且两个第一开关晶体管T1的第二极与同一条第一扇出走线7（例如S(m)）电连接。可以理解的，多个第一子电路区8共用两条控制信号线（CK1，CK2）；第一极为源极和漏极中的任意一种，第二极为源极和漏极中不同于第一极的一种。第一多路分解器电路9可以将对应的一条第一扇出走线7上的数据信号分时传递给两条不同的数据线。
具体的，对于阻抗较大的第一扇出走线7，为了满足像素充电需求（保证数据信号正常传递），与其对应连接的第一子电路区8的尺寸（例如在垂直于显示面板1方向上的投影面积）设计较大；对于阻抗较小的第一扇出走线7，与其对应连接的第一子电路区8的尺寸可以设计较小，只要满足像素充电需求即可。由于第一扇出走线组6中的多条第一扇出走线7在第二方向上阻抗逐渐减小，故对应的多个第一子电路区8在第二方向上的尺寸逐渐减小。可以理解的，本申请的第一子电路区8的尺寸与对应的第一扇出走线7的阻抗相匹配，以满足像素充电需求。
具体的，如图3所示，多个第一子电路区8靠近显示区2的一边与第二方向平行且位于同一条直线上，且多个第一子电路区8在第一方向上的宽度在第二方向上逐渐减小，即多个第一子电路区8远离显示区2的一侧呈渐变式变化，具体表现为电路区4远离显示区2的一侧朝向显示区2的方向内凹。与图1所示的示例性的显示面板1’中的电路区4’相比，本申请中的电路区4的面积有效的减小了，使得扇出走线区5的位置可以朝向显示区2的方向移动，从而减小了电路区4和扇出走线区5占据的非显示区3的面积，有利于减小下边框。
在一具体实施方式中，多个第一子电路区8远离显示区2的一侧呈阶梯状；每个第一子电路区8靠近显示区2的一边的长度相等，且每个第一子电路区8远离显示区2的一边的长度相等。可以理解的，每个第一子电路区8远离显示区2的一边与第二方向平行。
具体的，如图3所示，非显示区3还包括位于扇出走线区5远离电路区4的绑定区10；第一扇出走线7包括依次连接的第一走线段11、第二走线段12和第三走线段13；第一走线段11的一端和对应的第一子电路区8连接，另一端在第一节点P处与第二走线段12的一端连接；第二走线段12的另一端在第二节点Q处与第三走线段13的一端连接，第三走线段13的另一端与绑定区10连接；多条第一扇出走线7中的第一节点P相互连接形成的线段位于同一直线上且延伸方向与第一方向之间的夹角为锐角；多条第一扇出走线7中的第二节点Q相互连接形成的线段位于同一直线上且延伸方向与第一方向之间的夹角为锐角。
在一具体实施方式中，第一走线段11和第三走线段13的延伸方向与第一方向平行，第二走线段12与第一走线段11之间的夹角为钝角，且第二走线段12与第三走线段13之间的夹角为钝角。
具体的，可以通过调整第一扇出走线7的第二走线段12的延伸方向偏离第一方向的角度或调整多个第一扇出走线7之间的线距（pitch），使多条第一扇出走线7中的第一节点P相互连接形成的线段位于同一直线上且延伸方向与第一方向之间的夹角为锐角。
具体的，如图3所示，扇出走线区5还包括在第二方向上与第一扇出走线组6并排设置的第二扇出走线组14；第一扇出走线组6中长度较小的第一扇出走线7靠近第二扇出走线组14设置；第二扇出走线组14包括在朝向第一扇出走线组6的方向上长度逐渐减小的多条第二扇出走线15。相应的，电路区4还包括在第二方向上与多个第一子电路区8并排设置的多个第二子电路区16；多个第二子电路区16与多个第二扇出走线15一一对应电连接；多个第二子电路区16与多个第一子电路区8靠近显示区2的一边位于同一条直线上，且多个第二子电路区16在第一方向上的宽度在朝向第一子电路区8的方向上逐渐减小。
具体的，如图3和图5所示，每个第二子电路区16设有一第二多路分解器电路17；第二多路分解器电路17包括与对应的第二扇出走线15电连接的至少两个第二开关晶体管T2；每个第二子电路区16中的第二开关晶体管T2的数量相同；第二开关晶体管T2的沟道尺寸与对应的第二子电路区16在第一方向上的宽度正向相关。
在一具体实施方式中，每个第二多路分解器电路17包括两个第二开关晶体管T2以及与两个第二开关晶体管T2的栅极一一对应电连接的两条控制信号线（CK1，CK2）；两个第二开关晶体管T2的第一极分别与显示区2的两条数据线（D(n)，D(n+b)）对应电连接，n和b为正整数，且两个第二开关晶体管T2的第二极与同一条第二扇出走线15（例如S(n)）电连接。可以理解的，多个第二子电路区16共用两条控制信号线（CK1，CK2）。第二多路分解器电路17可以将对应的一条第二扇出走线15上的数据信号分时传递给两条不同的数据线。
具体的，第一扇出走线组6和第二扇出走线组14在第一方向上轴对称，且多个第一子电路区8与多个第二子电路区16在第一方向上轴对称；第一多路分解器电路9中的第一开关晶体管T1的数量和第二多路分解器电路17中的第二开关晶体管T2的数量相同。
可以理解的，多个第二扇出走线15与多个第一扇出走线7在第一方向上轴对称。具体的，多条第二扇出走线15的长度在朝向第一扇出走线组6的方向上逐渐减小；且多条第二扇出走线15在第一方向上的高度在朝向第一扇出走线组6的方向上逐渐增大。
在一具体实施方式中，如图3所示，扇出走线区5还包括位于第一扇出走线组6和第二扇出走线组14之间的第三扇出走线组18；第三扇出走线组18包括多条第三扇出走线19，任意一条第三扇出走线19的长度小于与第三扇出走线组18相邻设置的第一扇出走线7和第二扇出走线15中任意一个的长度。
相应的，电路区4还包括位于多个第一子电路区8和多个第二子电路区16之间且在第二方向上分布的多个第三子电路区20；多个第三子电路区20与多个第三扇出走线19一一对应连接；多个第三子电路区20与多个第一子电路区8靠近显示区2的一边位于同一直线上，且多个第三子电路区20远离显示区2的一边位于同一直线上且与第二方向平行设置；多个第三子电路区20在第一方向上的宽度小于与第三子电路区20相邻的第一子电路区8和第二子电路区16中任意一个在第一方向上的宽度。
具体的，为了更好的区分多个第一子电路区8、多个第二子电路区16和多个第三子电路区20，可以将多个第一子电路区8占据的区域称为第一电路区22，将多个第二子电路区16占据的区域称为第二电路区23，且将多个第三子电路区20占据的区域称为第三电路区24；其中，第一电路区22、第三电路区24和第二电路区23依次邻接。
具体的，如图3和图6所示，每个第三子电路区20设有一第三多路分解器电路21；第三多路分解器电路21包括与对应的第三扇出走线19电连接的至少两个第三开关晶体管T3；每个第三子电路区20中的第三开关晶体管T3的数量相同。第二开关晶体管T2的沟道尺寸与对应的第三子电路区20在第一方向上的宽度正向相关；且第二开关晶体管T2的沟道尺寸较任意一个第一开关晶体管T1的沟道尺寸和任意一个第二开关晶体管T2的沟道尺寸小。第三多路分解器电路21中的第三开关晶体管T3的数量和第二多路分解器电路17中的第二开关晶体管T2的数量相同。
可以理解的，第三多路分解器电路21与第二多路分解器电路17以及第一多路分解器电路9共用两条控制信号线。
在一具体实施方式中，每个第三多路分解器电路21包括两个第三开关晶体管T3以及与两个第三开关晶体管T3的栅极一一对应电连接的两条控制信号线（CK1，CK2）；两个第三开关晶体管T3的第一极分别与显示区2的两条数据线（D(k)，D(k+c)）对应电连接，k和c为正整数，且两个第三开关晶体管T3的第二极与同一条第三扇出走线19（例如S(k)）电连接。可以理解的，多个第三子电路区20共用两条控制信号线（CK1，CK2）。第三多路分解器电路21可以将对应的一条第三扇出走线19上的数据信号分时传递给两条不同的数据线。
在一具体实施方式中，多条第三扇出走线19的阻抗相同；在另一具体实施方式中，多条第三扇出走线19的阻抗可以不同，本申请对此不做限制。
具体的，如图3所示，电路区4和扇出走线区5具有同一对称轴L；其中，多个第一子电路区8和多个第二子电路区16关于对称轴L对称，且多个第三子电路区20关于对称轴L对称；第一扇出走线组6和第二扇出走线组14关于对称轴L对称，且第三扇出走线组18中的多条第三扇出走线19关于对称轴L对称。
具体的，第一开关晶体管T1、第二开关晶体管T2和第三开关晶体管T3均为薄膜晶体管。
具体的，绑定区10用于绑定驱动IC或柔性线路板；绑定区10包括与多个第一扇出走线7、多个第二扇出走线15和多个第三扇出走线19远离电路区4的一端一一对应连接的多个绑定衬垫。
如图7所示，本申请实施例中的电路区4、扇出走线区5和绑定区10在第一方向上的总高度与图1所示的电路区4’、扇出走线区5’和绑定区6’在第一方向上的总高度之间的差值为∆W。可以理解的，本申请较现有技术可以将下边框向显示区的方向缩窄∆W。在一具体实施方式中，∆W=W1-W2；其中，W1为电路区4在第一方向上的最大宽度，W2为电路区4在第一方向上的最小宽度。当然，∆W的值不限于此，具体由扇出走线区5中的扇出走线的布局决定。
本申请实施例中，由第一子电路区8、第二子电路区16和第三子电路区20构成的电路区4在第一方向上的宽度从两侧向对称轴L的方向上逐渐减小（例如宽度从W1减小到W2），使得电路区4远离显示区2的一侧呈内凹状，在满足像素充电需求的基础上，有效的减小了电路区4占据的面积，使得扇出走线区5可以朝向显示区2的方向移动，有利于实现窄边框化。
需要说明的是，在另一实施例中，与前述实施例不同的在于，电路区4仅由第一子电路区8和第二子电路区16构成；对应的，扇出走线区5仅由第一扇出走线组6和第二扇出走线组14构成。当然，在另一实施例中，电路区4也可以仅有第一子电路区8或第二子电路区16构成，对应的，扇出走线区5仅由第一扇出走线组6或第二扇出走线组14构成。这些实施例中的电路区4远离显示区2的一侧均向朝显示区2的一侧内凹，使得扇出走线区5可以朝向显示区2的方向移动，有利于实现显示面板1窄边框化。
如图8所示，本申请还提供了一种显示装置25，显示装置25包括前述实施例中的显示面板1以及与显示面板1电连接的驱动电路板26。驱动电路板26与扇出走线区5中的第一扇出走线组、第二扇出走线组和第三扇出走线组远离电路区4的一侧电连接。驱动电路板26通过扇出走线区5的扇出走线和电路区4的多路分解器电路向显示区2的数据线提供数据信号。
具体的，驱动电路板26为驱动IC或柔性线路板，与绑定区10绑定连接，从而实现与扇出走线区5的扇出走线电连接。
本实施例中，电路区4在第一方向上的宽度从两侧向中间的方向上逐渐减小，使得电路区4远离显示区2的一侧呈内凹状，在满足像素充电需求的基础上，有效的减小了电路区4占据的面积，使得扇出走线区5可以朝向显示区2的方向移动，有利于实现显示装置25窄边框化。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板和显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，包括显示区以及围绕所述显示区设置的非显示区；所述非显示区包括在第一方向上与所述显示区相邻设置的电路区以及位于所述电路区远离所述显示区一侧的扇出走线区；
    所述扇出走线区包括第一扇出走线组；所述第一扇出走线组包括在第二方向上长度逐渐减小的多条第一扇出走线，所述第二方向和所述第一方向相互垂直；
    所述电路区包括在所述第二方向上依次分布且与多条所述第一扇出走线一一对应连接的多个第一子电路区；多个所述第一子电路区靠近所述显示区的一边与所述第二方向平行且位于同一条直线上，且多个所述第一子电路区在所述第一方向上的宽度在所述第二方向上逐渐减小。
  2. 根据权利要求1所述的显示面板，其中，多个所述第一子电路区远离所述显示区的一侧呈阶梯状。
  3. 根据权利要求1所述的显示面板，其中，每个所述第一子电路区设有一第一多路分解器电路；所述第一多路分解器电路包括与对应的所述第一扇出走线电连接的至少两个第一开关晶体管；每个所述第一子电路区中的所述第一开关晶体管的数量相同；
    所述第一开关晶体管的沟道尺寸与对应的所述第一子电路区在所述第一方向上的宽度正向相关。
  4. 根据权利要求1所述的显示面板，其中，所述非显示区还包括位于所述扇出走线区远离所述电路区的绑定区；
    所述第一扇出走线包括依次连接的第一走线段、第二走线段和第三走线段；所述第一走线段的一端和对应的所述第一子电路区连接，另一端在第一节点处与所述第二走线段的一端连接；所述第二走线段的另一端在第二节点处与所述第三走线段的一端连接，所述第三走线段的另一端与所述绑定区连接；
    多条所述第一扇出走线中的所述第一节点相互连接形成的线段位于同一直线上且延伸方向与所述第一方向之间的夹角为锐角；多条所述第一扇出走线中的所述第二节点相互连接形成的线段位于同一直线上且延伸方向与所述第一方向之间的夹角为锐角。
  5. 根据权利要求1所述的显示面板，其中，所述扇出走线区还包括在所述第二方向上与所述第一扇出走线组并排设置的第二扇出走线组；所述第一扇出走线组中长度较小的所述第一扇出走线靠近所述第二扇出走线组设置；所述第二扇出走线组包括在朝所述第一扇出走线组的方向上长度逐渐减小的多条第二扇出走线；
    所述电路区还包括在所述第二方向上与所述多个第一子电路区并排设置的多个第二子电路区；多个所述第二子电路区与多个所述第二扇出走线一一对应电连接；多个所述第二子电路区与多个所述第一子电路区靠近所述显示区的一边位于同一条直线上，且多个所述第二子电路区在所述第一方向上的宽度在朝所述第一子电路区的方向上逐渐减小。
  6. 根据权利要求5所述的显示面板，其中，每个所述第二子电路区设有一第二多路分解器电路；所述第二多路分解器电路包括与对应的所述第二扇出走线电连接的至少两个第二开关晶体管；每个所述第二子电路区中的所述第二开关晶体管的数量相同；
    所述第二开关晶体管的沟道尺寸与对应的所述第二子电路区的在所述第一方向上的宽度正向相关。
  7. 根据权利要求6所述的显示面板，其中，所述第一扇出走线组和所述第二扇出走线组在所述第一方向上轴对称，且多个所述第一子电路区与多个所述第二子电路区在所述第一方向上轴对称。
  8. 根据权利要求5所述的显示面板，其中，所述扇出走线区还包括位于所述第一扇出走线组和所述第二扇出走线组之间的第三扇出走线组；所述第三扇出走线组包括多条第三扇出走线，任意一条所述第三扇出走线的长度小于与所述第三扇出走线组相邻设置的所述第一扇出走线和所述第二扇出走线中的任意一个的长度；
    所述电路区还包括位于所述多个第一子电路区和所述多个第二子电路区之间且在所述第二方向上分布的多个第三子电路区；多个所述第三子电路区与多个所述第三扇出走线一一对应连接；
    多个所述第三子电路区与多个所述第一子电路区靠近所述显示区的一边位于同一直线上，且多个所述第三子电路区远离所述显示区的一边位于同一直线上且与所述第二方向平行设置；多个所述第三子电路区在所述第一方向上的宽度小于与所述第三子电路区相邻的所述第一子电路区和所述第二子电路区中任意一个在所述第一方向上的宽度。
  9. 根据权利要求8所述的显示面板，其中，每个所述第三子电路区设有一第三多路分解器电路；所述第三多路分解器电路包括与对应的所述第三扇出走线电连接的至少两个第三开关晶体管；每个所述第三子电路区中的所述第三开关晶体管的数量相同；
    所述第二开关晶体管的沟道尺寸与对应的所述第三子电路区的在所述第一方向上的宽度正向相关。
  10. 根据权利要求8所述的显示面板，其中，所述第一子电路区中的开关晶体管的数量与所述第二子电路区中的开关晶体管的数量相等，且与所述第三子电路区中的开关晶体管的数量相等。
  11. 一种显示装置，包括权利要求1所述的显示面板和与所述显示面板电连接的驱动电路板；所述驱动电路板与所述第一扇出走线组远离所述电路区的一侧电连接。
  12. 根据权利要求11所述的显示装置，其中，多个所述第一子电路区远离所述显示区的一侧呈阶梯状。
  13. 根据权利要求11所述的显示装置，其中，每个所述第一子电路区设有一第一多路分解器电路；所述第一多路分解器电路包括与对应的所述第一扇出走线电连接的至少两个第一开关晶体管；每个所述第一子电路区中的所述第一开关晶体管的数量相同；
    所述第一开关晶体管的沟道尺寸与对应的所述第一子电路区在所述第一方向上的宽度正向相关。
  14. 根据权利要求11所述的显示装置，其中，所述非显示区还包括位于所述扇出走线区远离所述电路区的绑定区；
    所述第一扇出走线包括依次连接的第一走线段、第二走线段和第三走线段；所述第一走线段的一端和对应的所述第一子电路区连接，另一端在第一节点处与所述第二走线段的一端连接；所述第二走线段的另一端在第二节点处与所述第三走线段的一端连接，所述第三走线段的另一端与所述绑定区连接；
    多条所述第一扇出走线中的所述第一节点相互连接形成的线段位于同一直线上且延伸方向与所述第一方向之间的夹角为锐角；多条所述第一扇出走线中的所述第二节点相互连接形成的线段位于同一直线上且延伸方向与所述第一方向之间的夹角为锐角。
  15. 根据权利要求11所述的显示装置，其中，所述扇出走线区还包括在所述第二方向上与所述第一扇出走线组并排设置的第二扇出走线组；所述第一扇出走线组中长度较小的所述第一扇出走线靠近所述第二扇出走线组设置；所述第二扇出走线组包括在朝所述第一扇出走线组的方向上长度逐渐减小的多条第二扇出走线；
    所述电路区还包括在所述第二方向上与所述多个第一子电路区并排设置的多个第二子电路区；多个所述第二子电路区与多个所述第二扇出走线一一对应电连接；多个所述第二子电路区与多个所述第一子电路区靠近所述显示区的一边位于同一条直线上，且多个所述第二子电路区在所述第一方向上的宽度在朝所述第一子电路区的方向上逐渐减小。
  16. 根据权利要求15所述的显示装置，其中，每个所述第二子电路区设有一第二多路分解器电路；所述第二多路分解器电路包括与对应的所述第二扇出走线电连接的至少两个第二开关晶体管；每个所述第二子电路区中的所述第二开关晶体管的数量相同；
    所述第二开关晶体管的沟道尺寸与对应的所述第二子电路区的在所述第一方向上的宽度正向相关。
  17. 根据权利要求16所述的显示装置，其中，所述第一扇出走线组和所述第二扇出走线组在所述第一方向上轴对称，且多个所述第一子电路区与多个所述第二子电路区在所述第一方向上轴对称。
  18. 根据权利要求15所述的显示装置，其中，所述扇出走线区还包括位于所述第一扇出走线组和所述第二扇出走线组之间的第三扇出走线组；所述第三扇出走线组包括多条第三扇出走线，任意一条所述第三扇出走线的长度小于与所述第三扇出走线组相邻设置的所述第一扇出走线和所述第二扇出走线中的任意一个的长度；
    所述电路区还包括位于所述多个第一子电路区和所述多个第二子电路区之间且在所述第二方向上分布的多个第三子电路区；多个所述第三子电路区与多个所述第三扇出走线一一对应连接；
    多个所述第三子电路区与多个所述第一子电路区靠近所述显示区的一边位于同一直线上，且多个所述第三子电路区远离所述显示区的一边位于同一直线上且与所述第二方向平行设置；多个所述第三子电路区在所述第一方向上的宽度小于与所述第三子电路区相邻的所述第一子电路区和所述第二子电路区中任意一个在所述第一方向上的宽度。
  19. 根据权利要求18所述的显示装置，其中，每个所述第三子电路区设有一第三多路分解器电路；所述第三多路分解器电路包括与对应的所述第三扇出走线电连接的至少两个第三开关晶体管；每个所述第三子电路区中的所述第三开关晶体管的数量相同；
    所述第二开关晶体管的沟道尺寸与对应的所述第三子电路区的在所述第一方向上的宽度正向相关。
  20. 根据权利要求18所述的显示装置，其中，所述第一子电路区中的开关晶体管的数量与所述第二子电路区中的开关晶体管的数量相等，且与所述第三子电路区中的开关晶体管的数量相等。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170047356A1 (en) * 2015-08-13 2017-02-16 Samsung Display Co., Ltd. Array substrate
US20170062408A1 (en) * 2015-09-02 2017-03-02 Samsung Display Co., Ltd. Display panel and display device having the same
CN109634003A (zh) * 2019-02-21 2019-04-16 厦门天马微电子有限公司 一种显示面板及显示装置
CN111323949A (zh) * 2020-04-15 2020-06-23 昆山国显光电有限公司 阵列基板及显示面板
CN112867244A (zh) * 2021-02-26 2021-05-28 厦门天马微电子有限公司 一种显示面板和显示装置
CN113093946A (zh) * 2021-04-21 2021-07-09 厦门天马微电子有限公司 一种显示面板及显示装置
CN114419996A (zh) * 2022-01-21 2022-04-29 武汉华星光电技术有限公司 显示面板

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015178334A1 (ja) * 2014-05-22 2015-11-26 シャープ株式会社 アクティブマトリクス基板および表示装置
CN105158998B (zh) * 2015-09-14 2017-10-17 深圳市华星光电技术有限公司 一种液晶显示装置及其显示面板
CN107065336B (zh) * 2017-06-13 2020-05-01 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN110364082B (zh) * 2018-04-10 2022-03-18 上海和辉光电股份有限公司 一种柔性显示面板和柔性显示装置
CN114597246A (zh) * 2018-12-06 2022-06-07 武汉华星光电半导体显示技术有限公司 显示面板
CN109656067B (zh) * 2019-01-29 2022-06-03 京东方科技集团股份有限公司 显示基板、显示面板及显示装置
CN111383554B (zh) * 2019-11-06 2021-12-17 上海中航光电子有限公司 显示面板及显示装置
US11930671B2 (en) * 2019-12-20 2024-03-12 Chengdu Boe Optoelectronics Technology Co., Ltd. Flexible display panel and manufacturing method thereof, and flexible display apparatus
US11552109B2 (en) * 2020-01-21 2023-01-10 Sharp Kabushiki Kaisha Circuit substrate and display device
CN111564111B (zh) * 2020-05-29 2023-03-31 上海中航光电子有限公司 一种显示面板和显示装置
KR20220023913A (ko) * 2020-08-21 2022-03-03 삼성디스플레이 주식회사 표시 패널 및 이를 포함하는 표시 장치
CN214098977U (zh) * 2020-11-03 2021-08-31 惠科股份有限公司 一种显示面板和显示装置
CN214848636U (zh) * 2021-05-21 2021-11-23 北京小米移动软件有限公司 阵列基板、显示面板和终端

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170047356A1 (en) * 2015-08-13 2017-02-16 Samsung Display Co., Ltd. Array substrate
US20170062408A1 (en) * 2015-09-02 2017-03-02 Samsung Display Co., Ltd. Display panel and display device having the same
CN109634003A (zh) * 2019-02-21 2019-04-16 厦门天马微电子有限公司 一种显示面板及显示装置
CN111323949A (zh) * 2020-04-15 2020-06-23 昆山国显光电有限公司 阵列基板及显示面板
CN112867244A (zh) * 2021-02-26 2021-05-28 厦门天马微电子有限公司 一种显示面板和显示装置
CN113093946A (zh) * 2021-04-21 2021-07-09 厦门天马微电子有限公司 一种显示面板及显示装置
CN114419996A (zh) * 2022-01-21 2022-04-29 武汉华星光电技术有限公司 显示面板

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