WO2021027076A1 - 覆晶薄膜组件及显示面板组件 - Google Patents

覆晶薄膜组件及显示面板组件 Download PDF

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Publication number
WO2021027076A1
WO2021027076A1 PCT/CN2019/114000 CN2019114000W WO2021027076A1 WO 2021027076 A1 WO2021027076 A1 WO 2021027076A1 CN 2019114000 W CN2019114000 W CN 2019114000W WO 2021027076 A1 WO2021027076 A1 WO 2021027076A1
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WO
WIPO (PCT)
Prior art keywords
chip
auxiliary
film
area
display panel
Prior art date
Application number
PCT/CN2019/114000
Other languages
English (en)
French (fr)
Inventor
傅晓立
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US16/617,270 priority Critical patent/US20210405714A1/en
Publication of WO2021027076A1 publication Critical patent/WO2021027076A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/189—Power distribution
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display

Definitions

  • This application relates to the field of display technology, and in particular to a chip-on-film assembly and a display panel assembly.
  • the chip-on-film component when a chip-on-film component is used to connect the display panel and the circuit board, the chip-on-film component is prone to peeling off at the edge of one end of the chip-on-film component close to the display panel, causing signal lines to break and causing abnormal display of the display panel.
  • the purpose of the embodiments of the present application is to provide a chip on film component and a display panel assembly, which can solve the problem that the edge of the existing chip on film component close to the end of the display panel is prone to peeling of the chip on film, which causes the signal line to break, thereby causing the display
  • the panel shows abnormal technical problems.
  • An embodiment of the present application provides a chip-on-film assembly, including: a substrate, the substrate including a first auxiliary area, a second auxiliary area, and a chip provided between the first auxiliary area and the second auxiliary area A chip on film area, the first auxiliary area, the chip on film area, and the second auxiliary area are sequentially arranged along a first direction;
  • the side of the chip on film region close to the first auxiliary region and the side of the chip on film region close to the second auxiliary region are both provided with a plurality of signal traces, and the first Both the auxiliary area and the second auxiliary area are used to prevent disconnection of the signal wiring;
  • the width of the first auxiliary area along the first direction is equal to the width of the second auxiliary area along the first direction; the material of the substrate is a flexible material.
  • the substrate has a first end and a second end opposite to each other in a second direction, and the first direction is perpendicular to the second direction;
  • the end is bound to the display panel and is electrically connected to the display panel;
  • the second end is bound to the circuit board and is electrically connected to the circuit board.
  • the first auxiliary area and the second auxiliary area are both provided with a plurality of first binding points, and the first binding point is close to the first end portion Set and bind on the display panel.
  • a plurality of the first binding points are arranged at intervals along the first direction.
  • the chip on film area is provided with a plurality of second binding points and a plurality of third binding points, and the second binding points are close to the first end portion Is arranged and bound on the display panel, and the third binding point is arranged close to the second end and bound on the circuit board.
  • the first binding point is freely connected to the display panel
  • the second binding point is electrically connected to the display panel
  • the third binding point It is electrically connected with the circuit board.
  • the width of the first auxiliary area along the first direction and the width of the second auxiliary area along the first direction are both between 0.4 cm and 0.7 Between centimeters.
  • An embodiment of the present application also provides a flip-chip thin film assembly, including: a substrate, the substrate including a first auxiliary region, a second auxiliary region, and a coating disposed between the first auxiliary region and the second auxiliary region A crystal film area, the first auxiliary area, the chip on film area, and the second auxiliary area are sequentially arranged along a first direction;
  • the side of the chip on film region close to the first auxiliary region and the side of the chip on film region close to the second auxiliary region are both provided with a plurality of signal traces, and the first Both the auxiliary area and the second auxiliary area are used to prevent disconnection of the signal wiring.
  • the substrate has a first end and a second end opposite to each other in a second direction, and the first direction is perpendicular to the second direction;
  • the end is bound to the display panel and is electrically connected to the display panel;
  • the second end is bound to the circuit board and is electrically connected to the circuit board.
  • the first auxiliary area and the second auxiliary area are both provided with a plurality of first binding points, and the first binding point is close to the first end portion Set and bind on the display panel.
  • a plurality of the first binding points are arranged at intervals along the first direction.
  • the chip on film area is provided with a plurality of second binding points and a plurality of third binding points, and the second binding points are close to the first end portion Is arranged and bound on the display panel, and the third binding point is arranged close to the second end and bound on the circuit board.
  • the first binding point is freely connected to the display panel
  • the second binding point is electrically connected to the display panel
  • the third binding point It is electrically connected with the circuit board.
  • the width of the first auxiliary area along the first direction and the width of the second auxiliary area along the first direction are both between 0.4 cm and 0.7 Between centimeters.
  • the width of the first auxiliary region along the first direction is equal to the width of the second auxiliary region along the first direction.
  • the material of the substrate is a flexible material.
  • An embodiment of the present application also provides a display panel assembly, which includes a chip-on-film assembly.
  • the chip-on-film assembly includes a substrate.
  • the substrate includes a first auxiliary area, a second auxiliary area, and a first auxiliary area.
  • a chip on film area between the area and the second auxiliary area, the first auxiliary area, the chip on film area, and the second auxiliary area are sequentially arranged along the first direction;
  • the side of the chip on film region close to the first auxiliary region and the side of the chip on film region close to the second auxiliary region are both provided with a plurality of signal traces, and the first Both the auxiliary area and the second auxiliary area are used to prevent disconnection of the signal wiring.
  • the substrate has a first end and a second end opposite to each other in a second direction, and the first direction is perpendicular to the second direction; the first end The part is bound to the display panel and is electrically connected to the display panel; the second end part is bound to the circuit board and is electrically connected to the circuit board.
  • the first auxiliary area and the second auxiliary area are both provided with a plurality of first binding points, and the first binding points are arranged close to the first end And bound to the display panel.
  • a plurality of the first binding points are arranged at intervals along the first direction.
  • the chip-on-film assembly and the display panel assembly provided by the embodiments of the present application have a first auxiliary area and a second auxiliary area provided on both sides of the chip-on-film area to prevent the edge of the chip-on-film assembly from peeling off and cause the signal line in the chip-on-film area to break , Which in turn can improve product yield and display quality.
  • FIG. 1 is a schematic diagram of the first structure of a chip on film component provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a second structure of a chip on film component provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a display panel assembly provided by an embodiment of the application.
  • first and second are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of this application, “multiple articles” means two or more than two unless otherwise specifically defined.
  • FIG. 1 is a schematic diagram of the first structure of a chip-on-film component provided by an embodiment of the application.
  • the chip-on-film assembly 10 includes a substrate 100.
  • the substrate 100 includes a first auxiliary area 101, a second auxiliary area 102, and a substrate disposed between the first auxiliary area 101 and the second auxiliary area 102.
  • the chip on film area 103, the first auxiliary area 101, the chip on film area 103, and the second auxiliary area 102 are sequentially arranged along the first direction.
  • the first direction is not specifically limited, the first direction may be a horizontal direction, and the first direction may also be a vertical direction.
  • the material used for the substrate 100 is a flexible material.
  • the substrate 100 has a first end 110 and a second end 120 opposite to each other in the second direction.
  • the second direction is perpendicular to the first direction.
  • the first end 110 is bound to a display panel (not shown in the figure) and is electrically connected to the display panel; the second end 120 is bound On the circuit board (not marked in the figure) and electrically connected to the circuit board.
  • the chip-on-film area 103 is provided with a plurality of second binding points 123 and a plurality of third binding points 133, the second binding points 123 are arranged close to the first end 110, and the third binding points 133 are close to the first end 110.
  • the two ends 120 are provided.
  • the first end 110 is bound to the display panel by a plurality of second binding points 123, and the second end 120 is bound by a plurality of third binding points.
  • the fixed point 133 is bound to the circuit board.
  • a plurality of signal wires 130 are provided on the side of the chip on film region 103 close to the first auxiliary region 101 and on the side of the chip on film region 103 close to the second auxiliary region 102.
  • Each signal wiring 130 extends from the first end 110 to the second end 120.
  • the display panel and the circuit board are electrically connected through the signal wiring 130.
  • a plurality of signal traces 130 are arranged along the first direction.
  • a plurality of signal traces 130 are arranged along the first direction.
  • the first auxiliary area 101 and the second auxiliary area 102 are used as buffer areas of the signal wiring 130 to prevent the signal wiring 130 from being disconnected. That is, the distance between the multiple signal traces 130 on the side close to the first auxiliary region 101 and the edge of the substrate 100 is increased, which reduces the multiple signal traces on the side close to the first auxiliary region 101 on the flip-chip thin film assembly 10. There is a risk of wire breakage due to peeling of the flip chip film on the wire 130.
  • the distance between the multiple signal traces 130 on the side close to the second auxiliary region 102 and the edge of the substrate 100 is increased, which reduces the multiple signal traces on the side close to the second auxiliary region 102 on the flip chip assembly 10 130 There is a risk of wire breakage due to peeling of the flip chip.
  • an integrated chip 140, a plurality of first chip wiring lines 150, and a plurality of second chip wiring lines 160 are also provided on the flip chip film area.
  • Each first chip trace 150 extends from the first end 110 to the integrated chip 140
  • each second chip trace 160 extends from the integrated chip 140 to the second end 120.
  • the integrated chip 140, the multiple first chip signal traces 150, and the multiple second chip traces 160 are arranged on the multiple signal traces 130 on the side close to the first auxiliary region 101 and close to the second Between the multiple signal traces 130 on one side of the auxiliary area 102.
  • the integrated chip 140 is disposed on the flip-chip film area 103, the first chip trace 150 and the second chip trace 160 connected to the integrated chip 140 are also easily broken.
  • the provision of the first auxiliary area 101 and the second auxiliary area 102 in the embodiment of the present application can also protect the integrated chip 140, the first chip wiring 150 and the second chip wiring 160.
  • the width of the first auxiliary region 101 along the first direction and the width of the second auxiliary region 102 along the first direction are both between 0.4 cm and 0.7 cm.
  • the embodiment of the present application has repeatedly tested the width of the first auxiliary area 101 along the first direction and the width of the second auxiliary area 102 along the first direction.
  • the setting is between 0.4 cm and 0.7 cm, the multiple signal traces 130 on the side close to the first auxiliary region 101 and the side close to the second auxiliary region 102 on the flip chip device 10 can be greatly reduced. There is a risk of disconnection of multiple signal traces 130 due to peeling of the flip chip film.
  • the width of the first auxiliary area 101 along the first direction is equal to the width of the second auxiliary area 102 along the first direction.
  • the chip-on-film component 10 provided by the embodiment of the present application has a first auxiliary area 101 and a second auxiliary area 102 on both sides of the chip-on-film area 102 to prevent the edge of the chip-on-film component 10 from peeling off and cause signals in the chip-on-film area 103
  • the trace 130 is broken, which can improve the product yield and display quality.
  • FIG. 2 is a schematic diagram of the second structure of the chip-on-chip thin film assembly provided by the embodiment of the application.
  • the difference between the chip-on-film assembly 20 shown in FIG. 2 and the chip-on-film assembly shown in FIG. 1 is that the chip-on-film assembly 20 shown in FIG. 2 is provided with a first auxiliary area 201 and a second auxiliary area 202. Multiple first binding points 270.
  • the chip-on-film assembly 20 includes a substrate 200 including a first auxiliary area 201, a second auxiliary area 202, and a second auxiliary area 202 disposed between the first auxiliary area 201 and the second auxiliary area 202.
  • the chip on film area 203, the first auxiliary area 201, the chip on film area 203, and the second auxiliary area 202 are sequentially arranged along the first direction.
  • the first direction is not specifically limited, the first direction may be a horizontal direction, and the first direction may also be a vertical direction.
  • first auxiliary area 201 and the second auxiliary area 202 are both provided with a plurality of first binding points 270, and the first binding points 270 are arranged close to the first end 210.
  • the plurality of first binding points 270 are arranged at intervals along the first direction.
  • the material used for the substrate 200 is a flexible material.
  • the substrate 200 has a first end 210 and a second end 220 opposite to each other in the second direction. Wherein, the second direction is perpendicular to the first direction.
  • the first end 210 is bound to the display panel (marked in the figure) and is electrically connected to the display panel; the second end 220 is bound On the circuit board (not marked in the figure) and electrically connected to the circuit board.
  • a plurality of second binding points 223 and a plurality of third binding points 233 are arranged on the chip-on-film area 203, the second binding points 223 are arranged close to the first end 210, and the third binding points 223 are close to the first end 210.
  • Two ends 220 are provided.
  • the first end 210 is bound to the display panel through a plurality of first binding points 270 and a plurality of second binding points 223, and the second The end 220 is bound to the circuit board by a plurality of third binding 233 points.
  • the first binding point 270 is freely connected to the display panel, the second binding point 223 is electrically connected to the display panel, and the third binding point 233 is electrically connected to the circuit board. It should be noted that the empty connection between the first binding point 270 and the display panel is to protect the signal wiring 230 and enhance the stability of the connection between the flip chip assembly 20 and the display panel. That is, no electrical signal flows through the first binding point 270.
  • a plurality of signal traces 230 are provided on the side of the chip on film region 203 close to the first auxiliary region 201 and on the side of the chip on film region 203 close to the second auxiliary region 202.
  • Each signal wiring 230 extends from the first end 210 to the second end 220.
  • the display panel and the circuit board are electrically connected through the signal wiring 230.
  • a plurality of signal traces 230 are arranged along the first direction.
  • the first auxiliary area 201 and the second auxiliary area 202 are used as buffer areas of the signal wiring 230 to prevent the signal wiring 230 from being disconnected. That is, the distance between the multiple signal traces 230 on the side close to the first auxiliary region 201 and the edge of the substrate 200 is increased, which reduces the multiple signal traces on the side close to the first auxiliary region 201 of the flip chip component 20. There is a risk of wire breakage due to peeling of the flip chip film.
  • the distance between the multiple signal traces 230 on the side close to the second auxiliary region 202 and the edge of the substrate 200 is increased, which reduces the multiple signal traces on the side close to the second auxiliary region 202 on the flip chip module 20 230 There is a risk of wire breakage due to peeling of the flip chip film.
  • an integrated chip 240, a plurality of first chip traces 250, and a plurality of second chip traces 260 are also provided on the flip-chip film area 203.
  • Each first chip trace 240 extends from the first end 210 to the integrated chip 240
  • each second chip trace 260 extends from the integrated chip 240 to the second end 220.
  • the integrated chip 240, the multiple first chip signal traces 250, and the multiple second chip traces 260 are arranged on the multiple signal traces 230 on the side close to the first auxiliary region 201 and close to the second Between the multiple signal traces 230 on one side of the auxiliary area 202.
  • the integrated chip 240 is disposed on the flip-chip film area 203, the first chip trace 250 and the second chip trace 260 connected to the integrated chip 240 are also easily broken.
  • the provision of the first auxiliary area 201 and the second auxiliary area 202 in the embodiment of the present application can also protect the integrated chip 240, the first chip wiring 250, and the second chip wiring 260.
  • the first auxiliary area 201 and the second auxiliary area 202 are provided on both sides of the chip on film area 203, so as to prevent the edge of the chip on film component 20 from peeling off and lead to signal routing in the chip on film area.
  • the line 230 is broken, which can improve the product yield and display quality.
  • FIG. 3 is a schematic structural diagram of a display panel assembly provided by an embodiment of the application.
  • the present application also provides a display panel assembly 30, which includes the above-mentioned flip chip assembly 10/20/, a circuit board 40 and a display panel 50.
  • the above-mentioned description can be referred to for the chip-on-chip component, which will not be repeated here.

Abstract

一种覆晶薄膜组件（10），包括：基板（100），包括第一辅助区域（101）、第二辅助区域（102）以及覆晶薄膜区域（103），第一辅助区域（101）、覆晶薄膜区域（103）、第二辅助区域（102）沿着第一方向依次设置；覆晶薄膜区域（103）上靠近第一辅助区域（101）的一侧以及覆晶薄膜区域（103）上靠近第二辅助区域（102）的一侧均设置有多条信号走线（130），第一辅助区域（101）以及第二辅助区域（102）均用于防止信号走线（130）断线。

Description

覆晶薄膜组件及显示面板组件 技术领域
本申请涉及显示技术领域，具体涉及一种覆晶薄膜组件及显示面板组件。
 背景技术
现有技术中，采用覆晶薄膜组件来连接显示面板与电路板时，覆晶薄膜组件靠近显示面板的一端的边缘容易出现覆晶薄膜剥离，导致信号线断裂，进而使得显示面板显示异常。
 技术问题
本申请实施例的目的在于提供一种覆晶薄膜组件及显示面板组件，能够解决现有的覆晶薄膜组件靠近显示面板的一端的边缘容易出现覆晶薄膜剥离，导致信号线断裂，进而使得显示面板显示异常的技术问题。
 技术解决方案
本申请实施例提供一种覆晶薄膜组件，包括：包括：基板，所述基板包括第一辅助区域、第二辅助区域以及设置在所述第一辅助区域与所述第二辅助区域之间的覆晶薄膜区域，所述第一辅助区域、所述覆晶薄膜区域、所述第二辅助区域沿着第一方向依次设置；
其中，所述覆晶薄膜区域上靠近所述第一辅助区域的一侧以及所述覆晶薄膜区域上靠近所述第二辅助区域的一侧均设置有多条信号走线，所述第一辅助区域以及所述第二辅助区域均用于防止所述信号走线断线；
所述第一辅助区域沿着所述第一方向的宽度等于所述第二辅助区域沿着所述第一方向的宽度；所述基板的材料为柔性材料。
在本申请所述的覆晶薄膜组件中，所述基板在第二方向上具有相对的第一端部和第二端部，所述第一方向与所述第二方向垂直；所述第一端部绑定在显示面板上，并与所述显示面板电性连接；所述第二端部绑定在电路板上，并与所述电路板电性连接。
在本申请所述的覆晶薄膜组件中，所述第一辅助区域以及所述第二辅助区域均设置有多个第一绑定点，所述第一绑定点靠近所述第一端部设置并绑定在所述显示面板上。
在本申请所述的覆晶薄膜组件中，多个所述第一绑定点沿着所述第一方向间隔排列。
在本申请所述的覆晶薄膜组件中，所述覆晶薄膜区域设置有多个第二绑定点和多个第三绑定点，所述第二绑定点靠近所述第一端部设置并绑定在所述显示面板上，所述第三绑定点靠近所述第二端部设置并绑定在所述电路板上。
在本申请所述的覆晶薄膜组件中，所述第一绑定点与所述显示面板空接，所述第二绑定点与所述显示面板电性连接，所述第三绑定点与所述电路板电性连接。
在本申请所述的覆晶薄膜组件中，所述第一辅助区域沿着所述第一方向的宽度以及所述第二辅助区域沿着所述第一方向的宽度均介于0.4厘米至0.7厘米之间。
本申请实施例还提供一种覆晶薄膜组件，包括：基板，所述基板包括第一辅助区域、第二辅助区域以及设置在所述第一辅助区域与所述第二辅助区域之间的覆晶薄膜区域，所述第一辅助区域、所述覆晶薄膜区域、所述第二辅助区域沿着第一方向依次设置；
其中，所述覆晶薄膜区域上靠近所述第一辅助区域的一侧以及所述覆晶薄膜区域上靠近所述第二辅助区域的一侧均设置有多条信号走线，所述第一辅助区域以及所述第二辅助区域均用于防止所述信号走线断线。
在本申请所述的覆晶薄膜组件中，所述基板在第二方向上具有相对的第一端部和第二端部，所述第一方向与所述第二方向垂直；所述第一端部绑定在显示面板上，并与所述显示面板电性连接；所述第二端部绑定在电路板上，并与所述电路板电性连接。
在本申请所述的覆晶薄膜组件中，所述第一辅助区域以及所述第二辅助区域均设置有多个第一绑定点，所述第一绑定点靠近所述第一端部设置并绑定在所述显示面板上。
在本申请所述的覆晶薄膜组件中，多个所述第一绑定点沿着所述第一方向间隔排列。
在本申请所述的覆晶薄膜组件中，所述覆晶薄膜区域设置有多个第二绑定点和多个第三绑定点，所述第二绑定点靠近所述第一端部设置并绑定在所述显示面板上，所述第三绑定点靠近所述第二端部设置并绑定在所述电路板上。
在本申请所述的覆晶薄膜组件中，所述第一绑定点与所述显示面板空接，所述第二绑定点与所述显示面板电性连接，所述第三绑定点与所述电路板电性连接。
在本申请所述的覆晶薄膜组件中，所述第一辅助区域沿着所述第一方向的宽度以及所述第二辅助区域沿着所述第一方向的宽度均介于0.4厘米至0.7厘米之间。
在本申请所述的覆晶薄膜组件中，所述第一辅助区域沿着所述第一方向的宽度等于所述第二辅助区域沿着所述第一方向的宽度。
在本申请所述的覆晶薄膜组件中，所述基板的材料为柔性材料。
本申请实施例还提供一种显示面板组件，其包括覆晶薄膜组件，所述覆晶薄膜组件包括：基板，所述基板包括第一辅助区域、第二辅助区域以及设置在所述第一辅助区域与所述第二辅助区域之间的覆晶薄膜区域，所述第一辅助区域、所述覆晶薄膜区域、所述第二辅助区域沿着第一方向依次设置；
其中，所述覆晶薄膜区域上靠近所述第一辅助区域的一侧以及所述覆晶薄膜区域上靠近所述第二辅助区域的一侧均设置有多条信号走线，所述第一辅助区域以及所述第二辅助区域均用于防止所述信号走线断线。
在本申请所述的显示面板组件中，所述基板在第二方向上具有相对的第一端部和第二端部，所述第一方向与所述第二方向垂直；所述第一端部绑定在显示面板上，并与所述显示面板电性连接；所述第二端部绑定在电路板上，并与所述电路板电性连接。
在本申请所述的显示面板组件中，所述第一辅助区域以及所述第二辅助区域均设置有多个第一绑定点，所述第一绑定点靠近所述第一端部设置并绑定在所述显示面板上。
在本申请所述的显示面板组件中，多个所述第一绑定点沿着所述第一方向间隔排列。
 有益效果
本申请实施例提供的覆晶薄膜组件及显示面板组件，通过在覆晶薄膜区域的两边设置第一辅助区域和第二辅助区域，避免覆晶薄膜组件边缘剥离导致覆晶薄膜区域的信号线断裂，进而可以提高产品良率以及显示质量。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的覆晶薄膜组件的第一种结构示意图；
图2为本申请实施例提供的覆晶薄膜组件的第二种结构示意图；以及
图3为本申请实施例提供的显示面板组件的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多条”的含义是两条或两条以上，除非另有明确具体的限定。
请参阅图1，图1为本申请实施例提供的覆晶薄膜组件的第一种结构示意图。如图1所示，该覆晶薄膜组件10，包括：基板100，该基板100包括第一辅助区域101、第二辅助区域102以及设置在第一辅助区域101与第二辅助区域102之间的覆晶薄膜区域103，第一辅助区域101、覆晶薄膜区域103、第二辅助区域102沿着第一方向依次设置。需要说明的是，在本申请实施例中，第一方向具体不做限制，第一方向可以为水平方向，第一方向也可以为竖直方向。
该基板100采用的材料为柔性材料。具体的，该基板100在第二方向上具有相对设置的第一端部110和第二端部120。其中，第二方向与第一方向垂直设置。在一种实施方式中，该覆晶薄膜组件10在使用时，第一端部110绑定在显示面板（图中未标示）上，并与显示面板电性连接；第二端部120绑定在电路板（图中未标示）上，并与电路板电性连接。
其中，覆晶薄膜区域103上设置有多个第二绑定点123和多个第三绑定点133，第二绑定点123靠近第一端部110设置，第三绑定点133靠近第二端部120设置。在一种实施例方式中，该覆晶薄膜组件10在使用时，第一端部110通过多个第二绑定点123绑定在显示面板上，第二端部120通过多个第三绑定点133绑定在电路板上。
覆晶薄膜区域103上靠近第一辅助区域101的一侧以及覆晶薄膜区域103上靠近第二辅助区域102的一侧均设置有多条信号走线130。每条信号走线130均由第一端部110延伸至第二端部120，该覆晶薄膜组件10在使用时，通过信号走线130将显示面板与电路板电性连接。具体的，覆晶薄膜区域103上靠近第一辅助区域101的一侧，多条信号走线130沿着第一方向设置。覆晶薄膜区域103上靠近第二辅助区域102的一侧，多条信号走线130沿着第一方向设置。
本申请实施例通过将第一辅助区域101以及第二辅助区域102作为信号走线130的缓冲区域，可以防止信号走线130断线。也即，靠近第一辅助区域101一侧的多条信号走线130距离基板100的边缘的距离增加，降低了该覆晶薄膜组件10上靠近第一辅助区域101的一侧的多条信号走线130出现覆晶薄膜剥离导致断线的风险。同样，靠近第二辅助区域102一侧的多条信号走线130距离基板100的边缘的距离增加，降低了该覆晶薄膜组件10上靠近第二辅助区域102的一侧的多条信号走线130出现覆晶薄膜剥离导致断线的风险。
另外，在覆晶薄膜区域上还设置有集成芯片140、多条第一芯片走线150以及多条第二芯片走线160。每条第一芯片走线150均由第一端部110延伸至集成芯片140上，每条第二芯片走线160均由集成芯片140延伸至第二端部120。在本申实施例中，集成芯片140、多条第一芯片信号走线150以及多条第二芯片走线160设置在靠近第一辅助区域101一侧的多条信号走线130以及靠近第二辅助区域102一侧的多条信号走线130之间。
由于集成芯片140设置在覆晶薄膜区域103上，与集成芯片140连接的第一芯片走线150和第二芯片走线160也极易断线。本申请实施例设置第一辅助区域101以及第二辅助区域102同样也可以对集成芯片140、第一芯片走线150以及第二芯片走线160进行保护。
在一种实施方式中，第一辅助区域101沿着第一方向的宽度以及第二辅助区域102沿着第一方向的宽度均介于0.4厘米至0.7厘米之间。为了尽量缩减该覆晶薄膜组件10在第一方向的宽度，本申请实施例通过反复试验，第一辅助区域101沿着第一方向的宽度以及第二辅助区域102沿着第一方向的宽度均设置在介于0.4厘米至0.7厘米之间，便可以极大降低该覆晶薄膜组件10上靠近第一辅助区域101的一侧的多条信号走线130以及靠近第二辅助区域102的一侧的多条信号走线130出现覆晶薄膜剥离导致断线的风险。
进一步的，在另一种实施方式中，第一辅助区域101沿着第一方向的宽度等于第二辅助区域102沿着第一方向的宽度。
本申请实施例提供的覆晶薄膜组件10，通过在覆晶薄膜区域102的两边设置第一辅助区域101和第二辅助区域102，避免覆晶薄膜组件10边缘剥离导致覆晶薄膜区域103的信号走线130断裂，进而可以提高产品良率以及显示质量.
请参阅图2，图2为本申请实施例提供的覆晶薄膜组件的第二种结构示意图。其中，图2所示的覆晶薄膜组件20与图1所示覆晶薄膜组件的区别在于，图2所示的覆晶薄膜组件20在第一辅助区域201和第二辅助区域202上设置有多个第一绑定点270。
如图2所示，该覆晶薄膜组件20，包括：基板200，该基板200包括第一辅助区域201、第二辅助区域202以及设置在第一辅助区域201与第二辅助区域202之间的覆晶薄膜区域203，第一辅助区域201、覆晶薄膜区域203、第二辅助区域202沿着第一方向依次设置。需要说明的是，在本申请实施例中，第一方向具体不做限制，第一方向可以为水平方向，第一方向也可以为竖直方向。
其中，第一辅助区域201以及第二辅助区域202均设置有多个第一绑定点270，第一绑定点270靠近第一端部210设置。多个第一绑定点270沿着第一方向间隔排列。
该基板200采用的材料为柔性材料。具体的，该基板200在第二方向上具有相对设置的第一端部210和第二端部220。其中，第二方向与第一方向垂直设置。在一种实施方式中，该覆晶薄膜组件20在使用时，第一端部210绑定在显示面板（图中为标示）上，并与显示面板电性连接；第二端部220绑定在电路板（图中未标示）上，并与电路板电性连接。
其中，覆晶薄膜区域203上设置有多个第二绑定点223和多个第三绑定点233，第二绑定点223靠近第一端部210设置，第三绑定点223靠近第二端部220设置。在一种实施例方式中，该覆晶薄膜组件20在使用时，第一端部210通过多个第一绑定点270以及多个第二绑定点223绑定在显示面板上，第二端部220通过多个第三绑定233点绑定在电路板上。第一绑定点270与显示面板空接，第二绑定点223与显示面板电性连接，第三绑定点233与电路板电性连接。需要说明的是，第一绑定点270与显示面板空接是为了保护信号走线230，并加强覆晶薄膜组件20与显示面板之间的连接稳定性。也即，第一绑定点270上并无电信号流过。
覆晶薄膜区域203上靠近第一辅助区域201的一侧以及覆晶薄膜区域203上靠近第二辅助区域202的一侧均设置有多条信号走线230。每条信号走线230均由第一端部210延伸至第二端部220，该覆晶薄膜组件20在使用时，通过信号走线230将显示面板与电路板电性连接。具体的，覆晶薄膜区域203上靠近第一辅助区域201的一侧，多条信号走线230沿着第一方向设置。覆晶薄膜区域203上靠近第二辅助区域202的一侧，多条信号走线230沿着第一方向设置。
本申请实施例通过将第一辅助区域201以及第二辅助区域202作为信号走线230的缓冲区域，可以防止信号走线230断线。也即，靠近第一辅助区域201一侧的多条信号走线230距离基板200的边缘的距离增加，降低了该覆晶薄膜组件20上靠近第一辅助区域201的一侧的多条信号走线出现覆晶薄膜剥离导致断线的风险。同样，靠近第二辅助区域202一侧的多条信号走线230距离基板200的边缘的距离增加，降低了该覆晶薄膜组件20上靠近第二辅助区域202的一侧的多条信号走线230出现覆晶薄膜剥离导致断线的风险。
另外，在覆晶薄膜区域203上还设置有集成芯片240、多条第一芯片走线250以及多条第二芯片走线260。每条第一芯片走线240均由第一端部210延伸至集成芯片240上，每条第二芯片走线260均由集成芯片240延伸至第二端部220。在本申实施例中，集成芯片240、多条第一芯片信号走线250以及多条第二芯片走线260设置在靠近第一辅助区域201一侧的多条信号走线230以及靠近第二辅助区域202一侧的多条信号走线230之间。
由于集成芯片240设置在覆晶薄膜区域203上，与集成芯片240连接的第一芯片走线250和第二芯片走线260也极易断线。本申请实施例设置第一辅助区域201以及第二辅助区域202同样也可以对集成芯片240、第一芯片走线250以及第二芯片走线260进行保护。
本申请实施例提供的覆晶薄膜组件20，通过在覆晶薄膜区域203的两边设置第一辅助区域201和第二辅助区域202，避免覆晶薄膜组件20边缘剥离导致覆晶薄膜区域的信号走线230断裂，进而可以提高产品良率以及显示质量。
请参阅图3，图3为本申请实施例提供的显示面板组件的结构示意图。如图3所示，本申请还提供了一种显示面板组件30，其包括以上所述的覆晶薄膜组件10/20/以及电路板40和显示面板50。该覆晶薄膜组件可参照以上描述，在此不做赘述。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种覆晶薄膜组件，其包括：基板，所述基板包括第一辅助区域、第二辅助区域以及设置在所述第一辅助区域与所述第二辅助区域之间的覆晶薄膜区域，所述第一辅助区域、所述覆晶薄膜区域、所述第二辅助区域沿着第一方向依次设置；
    其中，所述覆晶薄膜区域上靠近所述第一辅助区域的一侧以及所述覆晶薄膜区域上靠近所述第二辅助区域的一侧均设置有多条信号走线，所述第一辅助区域以及所述第二辅助区域均用于防止所述信号走线断线；
    所述第一辅助区域沿着所述第一方向的宽度等于所述第二辅助区域沿着所述第一方向的宽度；所述基板的材料为柔性材料。
  2. 根据权利要求1所述的覆晶薄膜组件，其中，所述基板在第二方向上具有相对的第一端部和第二端部，所述第一方向与所述第二方向垂直；所述第一端部绑定在显示面板上，并与所述显示面板电性连接；所述第二端部绑定在电路板上，并与所述电路板电性连接。
  3. 根据权利要求2所述的覆晶薄膜组件，其中，所述第一辅助区域以及所述第二辅助区域均设置有多个第一绑定点，所述第一绑定点靠近所述第一端部设置并绑定在所述显示面板上。
  4. 根据权利要求3所述的覆晶薄膜组件，其中，多个所述第一绑定点沿着所述第一方向间隔排列。
  5. 根据权利要求3所述的覆晶薄膜组件，其中，所述覆晶薄膜区域设置有多个第二绑定点和多个第三绑定点，所述第二绑定点靠近所述第一端部设置并绑定在所述显示面板上，所述第三绑定点靠近所述第二端部设置并绑定在所述电路板上。
  6. 根据权利要求5所述的覆晶薄膜组件，其中，所述第一绑定点与所述显示面板空接，所述第二绑定点与所述显示面板电性连接，所述第三绑定点与所述电路板电性连接。
  7. 根据权利要求1所述的覆晶薄膜组件，其中，所述第一辅助区域沿着所述第一方向的宽度以及所述第二辅助区域沿着所述第一方向的宽度均介于0.4厘米至0.7厘米之间。
  8. 一种覆晶薄膜组件，其包括：基板，所述基板包括第一辅助区域、第二辅助区域以及设置在所述第一辅助区域与所述第二辅助区域之间的覆晶薄膜区域，所述第一辅助区域、所述覆晶薄膜区域、所述第二辅助区域沿着第一方向依次设置；
    其中，所述覆晶薄膜区域上靠近所述第一辅助区域的一侧以及所述覆晶薄膜区域上靠近所述第二辅助区域的一侧均设置有多条信号走线，所述第一辅助区域以及所述第二辅助区域均用于防止所述信号走线断线。
  9. 根据权利要求8所述的覆晶薄膜组件，其中，所述基板在第二方向上具有相对的第一端部和第二端部，所述第一方向与所述第二方向垂直；所述第一端部绑定在显示面板上，并与所述显示面板电性连接；所述第二端部绑定在电路板上，并与所述电路板电性连接。
  10. 根据权利要求9所述的覆晶薄膜组件，其中，所述第一辅助区域以及所述第二辅助区域均设置有多个第一绑定点，所述第一绑定点靠近所述第一端部设置并绑定在所述显示面板上。
  11. 根据权利要求10所述的覆晶薄膜组件，其中，多个所述第一绑定点沿着所述第一方向间隔排列。
  12. 根据权利要求10所述的覆晶薄膜组件，其中，所述覆晶薄膜区域设置有多个第二绑定点和多个第三绑定点，所述第二绑定点靠近所述第一端部设置并绑定在所述显示面板上，所述第三绑定点靠近所述第二端部设置并绑定在所述电路板上。
  13. 根据权利要求12所述的覆晶薄膜组件，其中，所述第一绑定点与所述显示面板空接，所述第二绑定点与所述显示面板电性连接，所述第三绑定点与所述电路板电性连接。
  14. 根据权利要求8所述的覆晶薄膜组件，其中，所述第一辅助区域沿着所述第一方向的宽度以及所述第二辅助区域沿着所述第一方向的宽度均介于0.4厘米至0.7厘米之间。
  15. 根据权利要求8所述的覆晶薄膜组件，其中，所述第一辅助区域沿着所述第一方向的宽度等于所述第二辅助区域沿着所述第一方向的宽度。
  16. 根据权利要求8所述的覆晶薄膜组件，其中，所述基板的材料为柔性材料。
  17. 一种显示面板组件，其包括覆晶薄膜组件，所述覆晶薄膜组件包括：基板，所述基板包括第一辅助区域、第二辅助区域以及设置在所述第一辅助区域与所述第二辅助区域之间的覆晶薄膜区域，所述第一辅助区域、所述覆晶薄膜区域、所述第二辅助区域沿着第一方向依次设置；
    其中，所述覆晶薄膜区域上靠近所述第一辅助区域的一侧以及所述覆晶薄膜区域上靠近所述第二辅助区域的一侧均设置有多条信号走线，所述第一辅助区域以及所述第二辅助区域均用于防止所述信号走线断线。
  18. 根据权利要求17所述的显示面板组件，其中，所述基板在第二方向上具有相对的第一端部和第二端部，所述第一方向与所述第二方向垂直；所述第一端部绑定在显示面板上，并与所述显示面板电性连接；所述第二端部绑定在电路板上，并与所述电路板电性连接。
  19. 根据权利要求18所述的显示面板组件，其中，所述第一辅助区域以及所述第二辅助区域均设置有多个第一绑定点，所述第一绑定点靠近所述第一端部设置并绑定在所述显示面板上。
  20. 根据权利要求19所述的显示面板组件，其中，多个所述第一绑定点沿着所述第一方向间隔排列。
PCT/CN2019/114000 2019-08-09 2019-10-29 覆晶薄膜组件及显示面板组件 WO2021027076A1 (zh)

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