WO2022205551A1 - 覆晶薄膜组、显示面板及显示模组 - Google Patents

覆晶薄膜组、显示面板及显示模组 Download PDF

Info

Publication number
WO2022205551A1
WO2022205551A1 PCT/CN2021/090474 CN2021090474W WO2022205551A1 WO 2022205551 A1 WO2022205551 A1 WO 2022205551A1 CN 2021090474 W CN2021090474 W CN 2021090474W WO 2022205551 A1 WO2022205551 A1 WO 2022205551A1
Authority
WO
WIPO (PCT)
Prior art keywords
binding
chip
output
substrate
terminals
Prior art date
Application number
PCT/CN2021/090474
Other languages
English (en)
French (fr)
Inventor
刘金风
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/294,842 priority Critical patent/US20230137683A1/en
Publication of WO2022205551A1 publication Critical patent/WO2022205551A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/82—Interconnections, e.g. terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates

Definitions

  • the present invention relates to the field of display technology, and in particular, to a chip-on-film set, a display panel and a display module.
  • a common COF is bound to a driver chip.
  • the output end of the COF is connected to the display panel, and the input end of the COF is connected to the PCB (Printed Circuit Board, printed circuit board).
  • the output signal of the driver chip is compared with the number of input signals.
  • the pin arrangement at the end of the COF connected to the PCB is sparse, and the pin arrangement at the end connected to the display panel is denser. Therefore, after the resolution of the display panel is increased, the arrangement space of the pins of the output end of the COF is greatly affected.
  • Embodiments of the present invention provide a chip-on-film set, a display panel, and a display module, so as to solve the problem that in the existing display module, in order to improve the resolution of the display panel, more COFs need to be bound under a panel of the same size , resulting in a technical problem of insufficient COF binding space.
  • An embodiment of the present invention provides a chip-on-chip film set, including:
  • a plurality of driving chips are located on the surface of the substrate, the plurality of driving chips are electrically connected to the input terminals, and the plurality of driving chips are electrically connected to the plurality of output terminals in a one-to-one correspondence.
  • the plurality of output ends are arranged in a row along the second end of the substrate.
  • the plurality of output ends are arranged in a plurality of rows along the second end of the substrate.
  • any of the output ends includes a plurality of output pins, and the output pins of the output ends of any two adjacent rows are arranged in a staggered arrangement.
  • each of the output pins of any row is located in a gap between two of the output pins of an adjacent row.
  • the output pins of the output terminals of each row are arranged in different layers.
  • the second end of the substrate includes a first connection part and a second connection part oppositely arranged, and at least one output end is provided on any connection part, and the output end It is located on a side surface of one of the connecting parts opposite to the other connecting part.
  • the input terminal includes a plurality of input pins arranged in a row along the first terminal of the substrate.
  • the width of the input pin is greater than the width of the output pin.
  • An embodiment of the present invention further provides a display panel, the display panel includes a display area and a non-display area, the non-display area is provided with a plurality of binding areas, and any of the binding areas includes a plurality of binding terminals; Wherein, any one of the binding regions is used for binding connection with the chip-on-film group of any of the above embodiments.
  • the plurality of binding terminals of any one of the binding regions are arranged in the same line.
  • the multiple binding terminals of any one of the binding areas are arranged in multiple rows.
  • any one of the binding terminals includes a plurality of binding pins, and the binding pins of any two adjacent rows are arranged in a staggered manner.
  • the binding area of the display panel includes a first surface and a second surface opposite to each other, and the first surface and the second surface are respectively provided with at least one of the binding terminals.
  • An embodiment of the present invention further provides a display module, including the display panel in any of the above embodiments, and a plurality of chip-on-film groups in any of the above embodiments; wherein, any binding area of the display panel It is bound and connected with one of the chip-on-film groups.
  • a plurality of binding terminals of any one of the binding regions are bound and connected to a plurality of output terminals of one of the chip-on-chip film groups in a one-to-one correspondence.
  • the plurality of output terminals are arranged in a row along the second end of the substrate, and the plurality of binding terminals of any one of the binding regions are arranged in a row.
  • the plurality of output terminals are arranged in multiple rows along the second end of the substrate, and the plurality of binding terminals in any one of the binding regions are arranged in multiple rows .
  • any one of the output terminals includes a plurality of output pins, and the output pins of the output terminals in any two adjacent rows are arranged in a staggered position; any one of the binding terminals includes a plurality of output pins.
  • the binding pins in any two adjacent rows are arranged in dislocation; wherein, the output pins in multiple rows are bound and connected in a one-to-one correspondence with the binding pins in multiple rows.
  • the second end of the substrate includes a first connection part and a second connection part oppositely arranged, and at least one output end is provided on any connection part, and the output end is located on one side surface opposite to the other connecting part;
  • the binding area of the display panel includes a first surface and a second surface opposite to each other, and the first surface and the second surface are respectively provided with at least One of the binding terminals; wherein, the first connecting portion is bound and connected to the first surface, and the second connecting portion is bound and connected to the second surface.
  • a plurality of driving chips are integrated on a chip-on-film group and bound to the same binding area on the display panel, which can improve the space utilization rate of the COF and solve the problem of insufficient binding space for the COF of high-resolution products. question.
  • FIG. 1 is a schematic structural diagram of a display module provided by an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a chip-on-film group provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a chip-on-film group provided by another embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a display panel according to another embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a chip-on-film group provided by other embodiments of the present invention.
  • FIG. 7 is a schematic structural diagram of a display panel provided by other embodiments of the present invention.
  • FIG. 8 is a schematic structural diagram of the first chip-on-film of the chip-on-film group in FIG. 6 .
  • FIG. 9 is a schematic structural diagram of a second chip on film of the chip on film group in FIG. 6 .
  • the present application provides a chip-on-film set, a display panel and a display module.
  • a display panel and a display module.
  • the present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.
  • an embodiment of the present invention provides a display module 1000 including a display panel 100 and a plurality of chip-on-film groups 200 bound to the display panel 100 .
  • any one of the chip-on-film groups 200 includes a substrate 21 , an input end 23 , a plurality of output ends 24 , and a plurality of driving chips 22 , and the input end 23 is located on the first side of the substrate 21 .
  • One end 201, the plurality of output ends 24 are located at the second end 202 of the substrate 21 opposite to the first end 201, the plurality of driving chips 22 are located on the surface of the substrate 21, and the plurality of The driving chip 22 is electrically connected to the input terminal 23 , and the plurality of driving chips 22 are electrically connected to the plurality of output terminals 24 in one-to-one correspondence.
  • the display panel 100 includes a display area 102 and a non-display area 101 , the non-display area 101 is provided with a plurality of binding areas 1011 , and any of the binding areas 1011 includes a plurality of binding areas 1011 .
  • the terminal 11 is fixed, wherein any one of the binding regions 1011 is used for binding with the chip-on-film group 200 .
  • the display module 1000 further includes a printed circuit board 300 , wherein one end of the chip-on-film group 200 is bound and connected to the display panel 100 , and the chip-on-film group The opposite end of 200 is bound and connected to the printed circuit board 300, and the printed circuit board 300 passes through the FFC (Flexible Flat Cable, flexible flat cable) cable 400 is electrically connected to the external control circuit board 500, and multiple chip-on-film groups 200 can be electrically connected to the same control circuit board 500 through two printed circuit boards 300 in different regions. .
  • the control circuit board 500 transmits signals to the signal lines in the display panel 100 through the chip on film group 200 .
  • the binding areas, the multiple binding areas 1011 may be arranged in parallel along the edge of the display panel 100 .
  • the plurality of chip-on-film groups 200 are bound to the plurality of binding regions 1011 in a one-to-one correspondence.
  • the number of output signals is much larger than the number of input signals.
  • the driver chip taking a source driver chip that outputs 960 channels as an example, there are 45 input pins and 960 output pins, so when the display panel After the resolution of 100 is increased, the impact on the binding space of the output end of the COF is relatively large, and the embodiment of the present invention mainly improves the pin arrangement design of the output end of the COF.
  • the output ends 24 of the chip-on-film group 200 are arranged in a row along the second end 202 of the substrate 21 .
  • the number of chip-on-film groups 200 bound to the display panel 100 can be reduced, thereby saving the number of adjacent two chip-on-film groups 200.
  • the space occupied by the gaps between COFs can improve the space utilization of COFs and solve the problem of insufficient COF binding space.
  • the substrate 21 can be a flexible substrate, including but not limited to polyimide (PI) material.
  • PI polyimide
  • Each of the output ends 24 includes a plurality of output pins 241 , and the plurality of output pins 241 are arranged in a row along the second end 202 of the substrate 21 .
  • the plurality of binding terminals 11 of any binding area 1011 of the display panel 100 are arranged in the same row, and the number of the plurality of binding terminals 11 is greater than that of the chip-on-film group 200 The number of output terminals 24 is the same.
  • Each of the bonding terminals 11 includes a plurality of bonding pins 111 , and the plurality of bonding pins 111 can be arranged in the same line along the edge of the non-display area 101 .
  • the multiple binding pins 111 of any binding area 1011 on the display panel 100 are bound and connected to the multiple output pins 241 of a chip-on-film group 200 in one-to-one correspondence.
  • the chip-on-film group 200 in FIG. 2 is schematically illustrated by taking an example of including two driving chips 22 , and each driving chip 22 is electrically connected to one output terminal 24 correspondingly.
  • the arrangement direction of the two (multiple) driver chips 22 is the same as the arrangement direction of the plurality of output terminals 24 , which is beneficial to the wiring design for electrically connecting the driver chips 22 and the output terminals 24 and avoids mutual interference between the various wirings.
  • the input end 23 of the chip-on-film group 200 is electrically connected to the control circuit board 500 through the printed circuit board 300 and the FFC cable 400 .
  • the input end 23 includes a plurality of input pins 231 , and the plurality of input pins 231 can be arranged in a row along the first end 201 of the substrate 21 .
  • the input pins 231 are used for electrical connection with the printed circuit board 300 .
  • the driving chip 22 may be a source driving chip, which inputs driving signals to the display panel 100 .
  • the driving chip 22 may be a gate driving chip, which inputs scanning signals to the display panel 100 .
  • the width of the input pins 231 may be greater than the width of the output pins 241 .
  • the width of the chip-on-film group 200 by increasing the width of the chip-on-film group 200, a plurality of driving chips 22 are integrated on one chip-on-film group 200, and the width of the output pins 241 is reduced.
  • the average binding space occupied by any driver chip 22 in this embodiment is smaller than the binding space occupied by the driver chip 22 in the prior art, so the embodiment of the present invention can improve the space utilization rate of the COF.
  • the multiple output terminals 24 of the chip-on-film group 200 in this embodiment are arranged in multiple rows.
  • the binding area 1011 of the display panel 100 has multiple The binding terminals 11 are arranged in multiple rows, and the output terminals 24 are bound and connected to the binding terminals 11 in one-to-one correspondence.
  • any one of the output terminals 24 includes a plurality of output pins 241, and the output pins 241 of the output terminals 24 of any two adjacent rows are arranged in dislocation; correspondingly, Any one of the binding terminals 11 includes a plurality of binding pins 111, and the binding pins 111 of the binding terminals 11 in any two adjacent rows are arranged in a staggered position; wherein, the output pins 241 in multiple rows One-to-one binding connection with the binding pins 111 in multiple rows.
  • the output pins 241 of each row can be arranged in a staggered position.
  • each output pin 241 in any row is located in a gap between two output pins 241 in an adjacent row, that is, any straight line extending along the column direction and passing through the output pin 241
  • the orthographic projection of L1 on the substrate 21 does not intersect with the orthographic projection of the output pins 241 of adjacent rows on the first substrate 21 .
  • the output pins 241 of the output terminals 24 of each row may be disposed in different layers, and the output pins 241 of each adjacent row may be insulated from each other by an insulating layer.
  • each insulating layer cannot block the output pins 241 of the lower layer, and the output pins 241 of the lower layer need to be exposed.
  • the present embodiment takes two rows of output terminals 24 and two driver chips 22 as an example for description.
  • the two rows of output terminals 24 are respectively electrically connected to two driver chips 22 , and a row close to the edge of the second terminal 202
  • the output terminal 24 is the output terminal 24 of the first row, and the output terminal 24 of one row away from the edge of the second terminal 202 is the output terminal of the second row.
  • the output pins 241 of the first row can be formed on the second end 202 of the first substrate 21,
  • the first end 201 forms an input pin 231 .
  • the plurality of leads are used for electrically connecting each output pin 241 and the output end of the driving chip 22 , or for electrically connecting each input pin 231 and the input end of the driving chip 22 .
  • an insulating layer is deposited on the first metal layer, and the insulating layer is etched to expose at least the output pins 241 and input pins 231 of the first row; and then a second metal layer is deposited on the insulating layer, and the second metal layer is deposited on the insulating layer.
  • the second metal layer is etched to form the second row of output pins and patterned leads.
  • a via hole may be opened on the insulating layer, and the lead formed by the second metal layer can be switched to the lower metal layer through the via hole, so as to realize the electrical connection between the second output pin and the corresponding driving chip 22. connect.
  • Materials of the first metal layer and the second metal layer include, but are not limited to, copper.
  • the present embodiment integrates multiple driver chips 22 on one chip-on-film group 200, and designs multiple rows of output pins 241 to reduce the number of output pins 241.
  • the width of the output pins makes it possible to accommodate more output pins on the COF under the condition of the same COF binding width, which can greatly improve the space utilization of the COF.
  • the second end of the chip-on-film group 200 provided in this embodiment includes two connecting parts, and the two connecting parts are respectively connected to any one of the display panel 100 .
  • the upper and lower surfaces of the binding area are bound and connected to make full use of the effective binding space of the display panel 100 and solve the problem of insufficient binding space for high-resolution products.
  • the second end of the substrate 21 of the chip-on-film group 200 includes a first connecting part 2021 and a second connecting part 2022 arranged oppositely, and at least one of the connecting parts is provided on any connecting part.
  • An output end 24, and the output end 24 is a surface on one side opposite to the other connecting part.
  • the binding area of the display panel 100 includes a first surface 103 and a second surface 104 opposite to each other, and the first surface 103 and the second surface 104 are respectively provided with at least one of the Bind terminal 11.
  • first connecting portion 2021 is bound and connected to the first surface 103
  • second connecting portion 2022 is bound and connected to the second surface 104 .
  • the multiple output ends 24 may be arranged in parallel along the length direction of the corresponding connecting portion.
  • the specific arrangement can refer to the description of FIG. 2 ; the multiple output ends 24 can also be arranged in multiple rows along the length direction of their corresponding connecting parts, and the specific arrangement can refer to the arrangement of FIG. 4 .
  • the binding terminals 11 on the surface corresponding to the binding area of the display panel 100 are arranged in the same way as the output terminals 24 .
  • the same arrangement is used to realize the binding of the display panel 100 and the chip-on-film group 200 .
  • each connection part 2021 and the second connection part 2022 each include one output terminal 24, and each output terminal 24 includes a plurality of output pins 241 arranged in a row; correspondingly, any one of the display panel 100
  • the first surface 103 and the second surface 104 of the binding area are respectively provided with a binding terminal 11 , and each binding terminal 11 includes a plurality of binding pins 111 arranged in the same line; wherein, the first connection part 2021 A row of output pins 241 on the first surface 103 is bound and connected to a row of binding pins 111 on the first surface 103 , and a row of output pins 241 on the second connection portion 2022 is bound to a row of pins on the second surface 104 .
  • 111 bind connection.
  • the chip-on-film group 200 in this embodiment can be formed by laminating a first chip-on film 203 and a second chip-on film 204 .
  • the first chip on film 203 includes a first substrate 211 , at least one driver chip 22 is located on the surface of the first substrate 211 , and at least one output terminal 24 is located at one end of the first substrate 211 .
  • the second flip chip 204 includes a second substrate 212 , at least one driver chip 22 is located on the surface of the second substrate 212 , and at least one output terminal 24 is located at one end of the second substrate 212 .
  • a part of the input pins 231 of the input end 23 of the chip on film group 200 may be located on the first chip on film 203 , and another part of the input pins 231 may be located on the second chip on film 204 .
  • all the input pins 231 of the input end 23 of the chip on film group 200 may be located on the same chip on film.
  • the output pins 241 and the driving chip 22 are prepared on the first substrate 211 and the second substrate 212 , the first chip-on film 203 and the second chip-on film 204 are pressed together to make them
  • the two ends with the input pins 231 are press-fitted and connected, and the two ends with the output pins 241 are not press-fitted, so that the two ends become free ends to form the first connection portion 2021 and
  • the second connecting portion 2022 is used to realize separate binding and connection between the chip-on-film group 200 and the upper and lower surfaces (the first surface and the second surface) of the binding area of the display panel 100 .
  • the first surface 103 is one of the light-emitting surface of the display panel 100 and the surface opposite to the light-emitting surface, and the second surface 104 is the other one.
  • the first surface 103 is a light emitting surface
  • the second surface 104 is a second surface opposite to the light emitting surface.
  • a via hole needs to be provided in the binding area 1011 of the display panel 100, so that the binding pin 111 on the second surface 104 side can pass through the via hole and be connected with each other.
  • the signal lines on one side of the light-emitting surface are electrically connected.
  • a chip-on-film group 200 is formed by laminating two chip-on-films, which can save a bonding process between the input end 23 and the printed circuit board 300 .
  • the first substrate 211 and the second substrate 212 are both flexible substrates, including but not limited to flexible materials such as polyimide (PI).
  • PI polyimide
  • the display panel 100 mentioned in the above embodiments includes but is not limited to one of an LCD display panel and an OLED display panel.
  • double-layer chip-on-chip films are superimposed and bound to the front and back sides of the binding area 1011 of the display panel 100 respectively, so as to make full use of the effective space of the display panel, improve the utilization rate of the COF space, and solve the problem of high-resolution products. Insufficient binding space.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

公开一种覆晶薄膜组、显示面板及显示模组，覆晶薄膜组包括：衬底、位于衬底的第一端的输入端、位于衬底与第一端相对的第二端的多个输出端、位于衬底表面的多个驱动芯片，多个驱动芯片电连接输入端，且多个驱动芯片与多个输出端一一对应电连接，由此可提高COF的空间利用率，解决高解析度产品的COF绑定空间不足的问题。

Description

覆晶薄膜组、显示面板及显示模组 技术领域
本发明涉及显示技术领域，尤其涉及一种覆晶薄膜组、显示面板及显示模组。
 背景技术
随着显示技术的发展，人们对显示屏的高对比度、高分辨率、窄边框、薄型化的需求日益强烈，显示屏的分辨率逐步从HD提升到FHD、UD乃至于8K。一般通过COF（Chip on film，覆晶薄膜）与显示屏绑定连接的方式，将驱动芯片的数据信号输送到显示屏内，有利于显示屏的窄边框设计。但随着显示屏分辨率的提高，给薄膜晶体管充电所需的数据信号也越来越多。65寸8K产品相较于65寸4K产品的解析度更高，需要更多的COF驱动，同样的面板尺寸下需要绑定更多的COF，因此在8K超高清的产品上应用往往会出现供COF绑定的空间不足的问题。
目前常见的一个COF上均绑定一个驱动芯片，COF的输出端连接至显示面板，其输入端连接至PCB(Printed Circuit Board，印刷电路板)，而驱动芯片的输出信号相较于输入信号数量多很多，因而COF连接至PCB的一端的引脚排布较疏，连接至显示面板的一端引脚排布较密。因此提高显示面板的分辨率后，对COF的输出端的引脚的排布空间影响较大。
综上，现有的COF的布线设计有待于改进。
 技术问题
本发明实施例提供一种覆晶薄膜组、显示面板及显示模组，以解决现有的显示模组中，为了提高显示面板的分辨率，在相同尺寸的面板下需要绑定更多的COF，导致COF绑定空间不足的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种覆晶薄膜组，包括：
衬底；
输入端，位于所述衬底的第一端；
多个输出端，位于所述衬底与所述第一端相对的第二端；
多个驱动芯片，位于所述衬底的表面，所述多个驱动芯片电连接所述输入端，且所述多个驱动芯片与所述多个输出端一一对应电连接。
在本发明的一些实施例中，所述多个输出端沿所述衬底的第二端同行排布。
在本发明的一些实施例中，所述多个输出端沿所述衬底的第二端呈多行排布。
在本发明的一些实施例中，任一所述输出端包括多个输出引脚，任意相邻两行的所述输出端的所述输出引脚错位排列。
在本发明的一些实施例中，任一行的每一所述输出引脚位于相邻行的两所述输出引脚之间的缝隙内。
在本发明的一些实施例中，各行的输出端的输出引脚异层设置。
在本发明的一些实施例中，所述衬底的第二端包括相对设置的第一连接部和第二连接部，任一连接部上设有至少一个所述输出端，且所述输出端位于其中一连接部与另一连接部相对的一侧表面。
在本发明的一些实施例中，所述输入端包括沿所述衬底的第一端同行排布的多个输入引脚。
在本发明的一些实施例中，所述输入引脚的宽度大于所述输出引脚的宽度。本发明实施例还提供一种显示面板，所述显示面板包括显示区和非显示区，所述非显示区设有多个绑定区，任一所述绑定区包括多个绑定端子；其中，任一所述绑定区用于与上述任一实施例的覆晶薄膜组绑定连接。
在本发明的一些实施例中，任一所述绑定区的所述多个绑定端子同行排布。
在本发明的一些实施例中，任一所述绑定区的所述多个绑定端子呈多行排布。
在本发明的一些实施例中，任一所述绑定端子包括多个绑定引脚，任意相邻两行的所述绑定引脚错位排列。
在本发明的一些实施例中，所述显示面板的绑定区包括相对的第一表面和第二表面，所述第一表面和所述第二表面分别设有至少一个所述绑定端子。
本发明实施例还提供一种显示模组，包括上述任一实施例中的显示面板，及上述任一实施例中的多个覆晶薄膜组；其中，所述显示面板的任一绑定区与一所述覆晶薄膜组绑定连接。
在本发明的一些实施例中，任一所述绑定区的多个绑定端子与一所述覆晶薄膜组的多个输出端一一对应绑定连接。
在本发明的一些实施例中，所述多个输出端沿所述衬底的第二端同行排布，任一所述绑定区的所述多个绑定端子同行排布。
在本发明的一些实施例中，所述多个输出端沿所述衬底的第二端呈多行排布，任一所述绑定区的所述多个绑定端子呈多行排布。
在本发明的一些实施例中，任一所述输出端包括多个输出引脚，任意相邻两行的所述输出端的所述输出引脚错位排列；任一所述绑定端子包括多个绑定引脚，任意相邻两行的所述绑定引脚错位排列；其中，多行所述输出引脚与多行所述绑定引脚一一对应绑定连接。
在本发明的一些实施例中，所述衬底的第二端包括相对设置的第一连接部和第二连接部，任一连接部上设有至少一个所述输出端，且所述输出端位于其中一连接部与另一连接部相对的一侧表面；所述显示面板的绑定区包括相对的第一表面和第二表面，所述第一表面和所述第二表面分别设有至少一个所述绑定端子；其中，所述第一连接部与所述第一表面绑定连接，所述第二连接部与所述第二表面绑定连接。
 有益效果
本发明实施例将多个驱动芯片集成于一个覆晶薄膜组上，与显示面板上的同一绑定区绑定，可提高COF的空间利用率，解决高解析度产品的COF绑定空间不足的问题。
 附图说明
图1为本发明实施例提供的显示模组的结构示意图。
图2为本发明实施例提供的覆晶薄膜组的结构示意图。
图3为本发明实施例提供的显示面板的结构示意图。
图4为本发明又一实施例提供的覆晶薄膜组的结构示意图。
图5为本发明又一实施例提供的显示面板的结构示意图。
图6本发明其他实施例提供的覆晶薄膜组的结构示意图。
图7本发明其他实施例提供的显示面板的结构示意图。
图8为图6中的覆晶薄膜组的第一覆晶薄膜的结构示意图。
图9为图6中的覆晶薄膜组的第二覆晶薄膜的结构示意图。
 本发明的实施方式
本申请提供一种覆晶薄膜组、显示面板及显示模组，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本发明针对现有的显示屏，为了提高显示面板的分辨率，在相同尺寸的面板下需要绑定更多的COF，导致COF绑定空间不足的技术问题，提出本实施例以克服该缺陷。
请参阅图1，本发明实施例提供一种显示模组1000，包括显示面板100和多个覆晶薄膜组200，所述多个覆晶薄膜组200与所述显示面板100绑定。
其中，请参阅图2，任一所述覆晶薄膜组200包括衬底21、输入端23、多个输出端24、多个驱动芯片22，所述输入端23位于所述衬底21的第一端201，所述多个输出端24位于所述衬底21与所述第一端201相对的第二端202，所述多个驱动芯片22位于衬底21的表面，且所述多个驱动芯片22电连接所述输入端23，且所述多个驱动芯片22与所述多个输出端24一一对应电连接。
请参阅图1和图3，所述显示面板100包括显示区102和非显示区101，所述非显示区101设有多个绑定区1011，任一所述绑定区1011包括多个绑定端子11，其中，任一所述绑定区1011用于与所述覆晶薄膜组200绑定。
更进一步地，请参阅图1，所述显示模组1000还包括印制电路板300，其中，所述覆晶薄膜组200的一端与所述显示面板100绑定连接，所述覆晶薄膜组200相对的另一端与所述印制电路板300绑定连接，所述印制电路板300通过FFC（Flexible Flat Cable，柔软扁平线缆）排线400电连接至外部的控制电路板500上，多个覆晶薄膜组200可分区域通过两块印制电路板300电连接至同一所述控制电路板500上。所述控制电路板500将信号通过所述覆晶薄膜组200传递至显示面板100内的信号线上。
具体地，在本发明的实施例中，绑定区,所述多个绑定区1011可沿着所述显示面板100的边缘同行设置。所述多个覆晶薄膜组200与所述多个绑定区1011分别一一对应绑定。
根据驱动芯片的特点，其输出信号较输入信号的数量多很多，例如以输出960个通道的源极驱动芯片为例，其输入引脚有45个，输出引脚有960个，因此当显示面板100的分辨率提高后，对于COF的输出端的绑定空间的影响较大，本发明实施例主要针对COF的输出端的引脚排布设计作出改进。
请参阅图2和图3，在本发明的一些实施例中，所述覆晶薄膜组200的多个输出端24沿所述衬底21的第二端202同行排布。通过将多个驱动芯片22集成在一个覆晶薄膜组200上，由此可减少与所述显示面板100绑定的覆晶薄膜组200的数量，从而节省掉相邻两覆晶薄膜组200之间的间隙占据的空间，在一定程度上可提升COF的空间利用率，解决COF绑定空间不足的问题。
所述衬底21可为软性基板，包括但不限于聚酰亚胺（PI）材料。
每一所述输出端24包括多个输出引脚241，所述多个输出引脚241沿所述衬底21的第二端202同行排布。
对应地，请参阅图3，所述显示面板100的任一绑定区1011的多个绑定端子11同行排布，该多个绑定端子11的数量与所述覆晶薄膜组200的多个输出端24的数量相同。
每一所述绑定端子11包括多个绑定引脚111，所述多个绑定引脚111可沿所述非显示区101的边缘同行排布，在显示面板100与覆晶薄膜组200绑定时，所述显示面板100上的任一绑定区1011的多个绑定引脚111与一个覆晶薄膜组200的多个输出引脚241一一对应绑定连接。
图2的覆晶薄膜组200以包括两个驱动芯片22为例进行示意性说明，每一驱动芯片22对应电连接一个输出端24。
优选地，两个（多个）驱动芯片22的排列方向与多个输出端24的排列方向相同，有利于电连接驱动芯片22和输出端24的布线设计，避免各个布线之间相互干扰。
所述覆晶薄膜组200的输入端23通过印制电路板300、FFC排线400电连接至所述控制电路板500上。
所述输入端23包括多个输入引脚231，所述多个输入引脚231可沿所述衬底21的第一端201同行排布。所述输入引脚231用于与所述印制电路板300电连接。
所述驱动芯片22可为源极驱动芯片，向所述显示面板100输入驱动信号，在其他实施例中，所述驱动芯片22可为栅驱动芯片，向所述显示面板100输入扫描信号。
由于输入引脚231的数量相较于输出引脚241的数量少的多，因此所述输入引脚231的宽度可大于输出引脚241的宽度。
本实施例通过增加覆晶薄膜组200的宽度，在一个覆晶薄膜组200上集成多个驱动芯片22，并减小输出引脚241的宽度，相比于现有技术的一个COF上设置一个驱动芯片的设计来说，本实施例任一驱动芯片22占据的平均绑定空间会小于现有技术的驱动芯片22占据的绑定空间，因此本发明实施例可提升COF的空间利用率。
请参阅图4和图5，与上述实施例不同的是，本实施例中的覆晶薄膜组200多个输出端24呈多行排布，对应地，显示面板100的绑定区1011的多个绑定端子11呈多行排布，该多个输出端24与该多个绑定端子11一一对应绑定连接。通过将多个输出端24分多行布置，一方面能够降低任一覆晶薄膜组200与显示面板100绑定时所需的宽度，解决高解析度产品的COF绑定空间不足的问题，另一方面能够节省覆晶薄膜组200的制作成本。
进一步地，请参阅图4和图5，任一所述输出端24包括多个输出引脚241，任意相邻两行的所述输出端24的所述输出引脚241错位排列；对应地，任一所述绑定端子11包括多个绑定引脚111，任意相邻两行的所述绑定端子11的所述绑定引脚111错位排列；其中，多行所述输出引脚241与多行所述绑定引脚111一一对应绑定连接。
由于每行的输出引脚241与其电连接的驱动芯片22之间需要布置有走线，因此需要为连接至各行的输出引脚241提供布线空间。为了避免连接到各行的输出引脚241之间的布线相互干扰，可将各行输出引脚241错位排布。
优选地，任一行中的每一所述输出引脚241位于相邻行的两所述输出引脚241之间的缝隙内，即沿列方向延伸的任意一条穿过该输出引脚241的直线L1在所述衬底21上的正投影与相邻行的输出引脚241在所述第一衬底21上的正投影没有交集。
此外，各行输出端24的输出引脚241可异层设置，每相邻行之间输出引脚241之间可通过一层绝缘层相互绝缘隔开。但需注意的是，每一绝缘层不能遮挡下层的输出引脚241，需裸露出下层的输出引脚241。
请参阅图4，本实施例以两行输出端24和两个驱动芯片22为例进行说明，两行输出端24分别对应电连接两个驱动芯片22，靠近所述第二端202边缘的一行输出端24为第一行的输出端24，远离所述第二端202边缘的一行输出端24为第二行的输出端。
具体地，可通过在第一衬底21上沉积第一金属层，并对第一金属层进行蚀刻，以在第一衬底21的第二端202形成第一行的输出引脚241，在第一端201形成输入引脚231。该多条引线用于电性连接各个输出引脚241与驱动芯片22的输出端，或用于电性连接各个输入引脚231与驱动芯片22的输入端。
再在第一金属层上沉积绝缘层，并对绝缘层进行刻蚀，以至少露出第一行的输出引脚241和输入引脚231；再在绝缘层上沉积第二金属层，并对第二金属层进行刻蚀，以形成第二行的输出引脚和图案化的引线。其中，绝缘层上可开设有过孔，由所述第二金属层形成的引线可通过所述过孔换线至下层的金属层，实现第二输出引脚和与其对应的驱动芯片22的电连接。
所述第一金属层和所述第二金属层的材料包括但不限于铜。
相比于现有技术的一个COF上设置一个驱动芯片的设计来说，本实施例在一个覆晶薄膜组200上集成多个驱动芯片22的同时，并设计多行输出引脚241，减小输出引脚的宽度，使得在同样的COF绑定宽度的条件下，COF上能够容纳更多的输出引脚，能够大幅度提升COF的空间利用率。相较于图2中的实施例，本实施例可不必增加覆晶薄膜组的绑定宽度，因此可进一步提升覆晶薄膜组的空间利用率。
请参阅图6和图7，相较于前两个实施例，本实施例提供的覆晶薄膜组200第二端包括两个连接部，所述两个连接部分别与显示面板100的任一绑定区的上下表面绑定连接，以充分利用显示面板100的有效绑定空间，解决高解析度产品的绑定空间不足的问题。
具体地，请参阅图6，所述覆晶薄膜组200的衬底21的第二端包括相对设置的第一连接部2021和第二连接部2022，任一连接部上设有至少一个所述输出端24，且所述输出端24为于其中一连接部与另一连接部相对的一侧表面。
请参阅图7，对应地，所述显示面板100的绑定区包括相对的第一表面103和第二表面104，所述第一表面103和所述第二表面104分别设有至少一个所述绑定端子11。
请参阅图6和图7，其中，所述第一连接部2021与所述第一表面103绑定连接，所述第二连接部2022与所述第二表面104绑定连接。
一些实施例中，所述第一连接部2021或所述第二连接部2022上的所述输出端24有多个时，多个输出端24可沿其对应的连接部的长度方向同行排布，具体排布方式可参考对图2的描述；多个输出端24也可沿其对应的连接部的长度方向呈多行排布，具体排布方式可参考对图4的排布。
可以理解的是，每个连接部上的输出端24呈一行排布或呈多行排布时，相应地，显示面板100的绑定区对应的表面上的绑定端子11呈与输出端24相同的排布方式，以实现显示面板100与覆晶薄膜组200的绑定。
请参阅图6和图7，本发明实施例以每个连接部上设有一个输出端24为例进行示意性说明。所述第一连接部2021、所述第二连接部2022均包括一个输出端24，每个输出端24包括同行排布的多个输出引脚241；对应地，所述显示面板100的任一绑定区的第一表面103、第二表面104分别设有一个绑定端子11，每个绑定端子11包括同行排布的多个绑定引脚111；其中，所述第一连接部2021上的一行输出引脚241与第一表面103上的一行绑定引脚111绑定连接，所述第二连接部2022上的一行输出引脚241与第二表面104上的一行绑定引脚111绑定连接。
请参阅图6、图8和图9，本实施例的覆晶薄膜组200可由第一覆晶薄膜203、第二覆晶薄膜204压合而成。
具体地，所述第一覆晶薄膜203包括第一衬底211，至少一个驱动芯片22位于所述第一衬底211表面，至少一个输出端24位于所述第一衬底211的一端。
所述第二覆晶薄膜204包括第二衬底212，至少一个驱动芯片22位于所述第二衬底212表面，至少一个输出端24位于所述第二衬底212的一端。
所述覆晶薄膜组200的输入端23的一部分输入引脚231可位于所述第一覆晶薄膜203上，另一部分输入引脚231可位于所述第二覆晶薄膜204上。
在其他实施例中，所述覆晶薄膜组200的输入端23的全部输入引脚231可位于同一覆晶薄膜上。
在第一衬底211和第二衬底212上制备好输入引脚231、输出引脚241以及驱动芯片22后，将第一覆晶薄膜203和第二覆晶薄膜204进行压合，使其具有输入引脚231的两端进行压合连接，将具有输出引脚241的两端不进行压合，使该两端成为自由端以形成所述覆晶薄膜组200的第一连接部2021和第二连接部2022，从而实现覆晶薄膜组200与显示面板100的绑定区的上下表面（第一表面、第二表面）分开绑定连接。
所述第一表面103为所述显示面板100的出光面和与所述出光面相对的表面中的一者，所述第二表面104为其中的另一者。本实施例中所述第一表面103为出光面，所述第二表面104为与所述出光面相对的第二表面。
由于数据线和扫描线等信号线均设置于出光面一侧，因此显示面板100的绑定区1011需设置过孔，使得第二表面104一侧的绑定引脚111通过所述过孔与出光面一侧的信号线实现电性连接。
请参阅图8和图9，采用两张覆晶薄膜压合而成一张覆晶薄膜组200，可节省一道输入端23与印制电路板300的绑定制程。
所述第一衬底211和第二衬底212均为软性基板，包括但不限于聚酰亚胺（PI）等柔性材料。
上述各个实施例提及的显示面板100包括但不限于LCD显示面板、OLED显示面板中的一种。
本实施例通过双层覆晶薄膜叠加在一起，分别与显示面板100的绑定区1011的正、反面绑定，充分利用显示面板的有效空间，提高COF空间的利用率，解决高解析产品的绑定空间不足的问题。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种覆晶薄膜组，包括：
    衬底；
    输入端，位于所述衬底的第一端；
    多个输出端，位于所述衬底与所述第一端相对的第二端；以及
    多个驱动芯片，位于所述衬底的表面，所述多个驱动芯片电连接所述输入端，且所述多个驱动芯片与所述多个输出端一一对应电连接。
  2. 根据权利要求1所述的覆晶薄膜组，其中，所述多个输出端沿所述衬底的第二端同行排布。
  3. 根据权利要求1所述的覆晶薄膜组，其中，所述多个输出端沿所述衬底的第二端呈多行排布。
  4. 根据权利要求3所述的覆晶薄膜组，其中，任一所述输出端包括多个输出引脚，任意相邻两行的所述输出端的所述输出引脚错位排列。
  5. 根据权利要求4所述的覆晶薄膜组，其中，任一行的每一所述输出引脚位于相邻行的两所述输出引脚之间的缝隙内。
  6. 根据权利要求3所述的覆晶薄膜组，其中，各行的输出端的输出引脚异层设置。
  7. 根据权利要求1所述的覆晶薄膜组，其中，所述衬底的第二端包括相对设置的第一连接部和第二连接部，任一连接部上设有至少一个所述输出端，且所述输出端位于其中一连接部与另一连接部相对的一侧表面。
  8. 根据权利要求1所述的覆晶薄膜组，其中，所述输入端包括沿所述衬底的第一端同行排布的多个输入引脚。
  9. 根据权利要求7所述的覆晶薄膜组，其中，所述输入引脚的宽度大于所述输出引脚的宽度。
  10. 一种显示面板，包括显示区和非显示区，所述非显示区设有多个绑定区，任一所述绑定区包括多个绑定端子；其中，任一所述绑定区用于与一权利要求1所述的覆晶薄膜组绑定连接。
  11. 根据权利要求10所述的显示面板，其中，任一所述绑定区的所述多个绑定端子同行排布。
  12. 根据权利要求10所述的显示面板，其中，任一所述绑定区的所述多个绑定端子呈多行排布。
  13. 根据权利要求12所述的显示面板，其中，任一所述绑定端子包括多个绑定引脚，任意相邻两行的所述绑定引脚错位排列。
  14. 根据权利要求10所述的显示面板，其中，所述显示面板的绑定区包括相对的第一表面和第二表面，所述第一表面和所述第二表面分别设有至少一个所述绑定端子。
  15. 一种显示模组，包括显示面板及多个覆晶薄膜组，其中，
    所述覆晶薄膜组包括：衬底；输入端，位于所述衬底的第一端；多个输出端，位于所述衬底与所述第一端相对的第二端；以及多个驱动芯片，位于所述衬底的表面，所述多个驱动芯片电连接所述输入端，且所述多个驱动芯片与所述多个输出端一一对应电连接；
    所述显示面板包括：显示区和非显示区，所述非显示区设有多个绑定区，任一所述绑定区包括多个绑定端子；其中，
    所述显示面板的任一绑定区与一所述覆晶薄膜组绑定连接。
  16. 根据权利要求15所述的显示模组，其中，任一所述绑定区的多个绑定端子与一所述覆晶薄膜组的多个输出端一一对应绑定连接。
  17. 根据权利要求16所述的显示模组，其中，所述多个输出端沿所述覆晶薄膜组的衬底的第二端同行排布，任一所述绑定区的所述多个绑定端子同行排布。
  18. 根据权利要求16所述的显示模组，其中，所述多个输出端沿所述覆晶薄膜组的衬底的第二端呈多行排布，任一所述绑定区的所述多个绑定端子呈多行排布。
  19. 根据权利要求18所述的显示模组，其中，任一所述输出端包括多个输出引脚，任意相邻两行的所述输出端的所述输出引脚错位排列；任一所述绑定端子包括多个绑定引脚，任意相邻两行的所述绑定端子的所述绑定引脚错位排列；其中，多行所述输出引脚与多行所述绑定引脚一一对应绑定连接。
  20. 根据权利要求15所述的显示模组，其中，所述覆晶薄膜组的衬底的第二端包括相对设置的第一连接部和第二连接部，任一连接部上设有至少一个输出端，且所述输出端位于其中一连接部与另一连接部相对的一侧表面；所述显示面板的绑定区包括相对的第一表面和第二表面，所述第一表面和所述第二表面分别设有至少一个绑定端子；其中，所述第一连接部与所述第一表面绑定连接，所述第二连接部与所述第二表面绑定连接。
PCT/CN2021/090474 2021-04-01 2021-04-28 覆晶薄膜组、显示面板及显示模组 WO2022205551A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/294,842 US20230137683A1 (en) 2021-04-01 2021-04-28 Chip on film assembly, display panel, and display module

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110356984.7A CN113178132A (zh) 2021-04-01 2021-04-01 覆晶薄膜组、显示面板及显示模组
CN202110356984.7 2021-04-01

Publications (1)

Publication Number Publication Date
WO2022205551A1 true WO2022205551A1 (zh) 2022-10-06

Family

ID=76923001

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/090474 WO2022205551A1 (zh) 2021-04-01 2021-04-28 覆晶薄膜组、显示面板及显示模组

Country Status (3)

Country Link
US (1) US20230137683A1 (zh)
CN (1) CN113178132A (zh)
WO (1) WO2022205551A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113589893A (zh) * 2021-07-28 2021-11-02 Tcl华星光电技术有限公司 覆晶薄膜以及显示装置
CN113759620B (zh) * 2021-08-19 2023-09-29 北海惠科光电技术有限公司 显示面板和显示装置
CN113707700B (zh) * 2021-08-31 2023-05-26 京东方科技集团股份有限公司 一种显示模组、制备方法以及显示装置
CN114596777A (zh) * 2022-03-03 2022-06-07 深圳市华星光电半导体显示技术有限公司 显示模组及移动终端
CN115206187B (zh) * 2022-07-04 2024-02-06 Tcl华星光电技术有限公司 一种覆晶薄膜组
CN115798375B (zh) * 2022-11-14 2024-07-23 惠科股份有限公司 覆晶薄膜、显示面板及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150171006A1 (en) * 2013-12-13 2015-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Package and Methods of Forming the Same
CN108183095A (zh) * 2017-12-29 2018-06-19 武汉华星光电半导体显示技术有限公司 柔性显示面板及其覆晶薄膜结构
CN108241240A (zh) * 2018-02-08 2018-07-03 上海天马微电子有限公司 一种显示面板以及显示装置
CN109686720A (zh) * 2018-11-08 2019-04-26 友达光电股份有限公司 覆晶薄膜封装结构及显示装置
CN209216555U (zh) * 2019-01-29 2019-08-06 合肥京东方显示技术有限公司 一种覆晶薄膜及显示装置
CN110827773A (zh) * 2018-08-10 2020-02-21 三星显示有限公司 显示设备
CN111968525A (zh) * 2020-09-23 2020-11-20 京东方科技集团股份有限公司 一种覆晶薄膜、显示基板及显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3549760B2 (ja) * 1999-02-18 2004-08-04 シャープ株式会社 平面型表示装置
CN110579915A (zh) * 2019-08-06 2019-12-17 深圳市华星光电技术有限公司 覆晶薄膜组、显示模组及覆晶薄膜组的邦定方法
CN111176037A (zh) * 2020-02-26 2020-05-19 深圳市华星光电半导体显示技术有限公司 覆晶薄膜组、覆晶薄膜组的绑定方法和显示装置
CN111668622A (zh) * 2020-06-18 2020-09-15 京东方科技集团股份有限公司 电连接结构、显示面板及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150171006A1 (en) * 2013-12-13 2015-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Package and Methods of Forming the Same
CN108183095A (zh) * 2017-12-29 2018-06-19 武汉华星光电半导体显示技术有限公司 柔性显示面板及其覆晶薄膜结构
CN108241240A (zh) * 2018-02-08 2018-07-03 上海天马微电子有限公司 一种显示面板以及显示装置
CN110827773A (zh) * 2018-08-10 2020-02-21 三星显示有限公司 显示设备
CN109686720A (zh) * 2018-11-08 2019-04-26 友达光电股份有限公司 覆晶薄膜封装结构及显示装置
CN209216555U (zh) * 2019-01-29 2019-08-06 合肥京东方显示技术有限公司 一种覆晶薄膜及显示装置
CN111968525A (zh) * 2020-09-23 2020-11-20 京东方科技集团股份有限公司 一种覆晶薄膜、显示基板及显示装置

Also Published As

Publication number Publication date
CN113178132A (zh) 2021-07-27
US20230137683A1 (en) 2023-05-04

Similar Documents

Publication Publication Date Title
WO2022205551A1 (zh) 覆晶薄膜组、显示面板及显示模组
US6734941B2 (en) Liquid crystal display device
KR101195688B1 (ko) 플렉시블 기판 및 전기 회로 구조체
US7283193B2 (en) Wiring board interconnection arrangement and display device including same
US7002812B2 (en) Electronic module and method for fabricating the same
JP3549760B2 (ja) 平面型表示装置
CN104835416A (zh) 显示装置
US11069320B2 (en) Chip-on-film and display device
US7420821B2 (en) Electronic module and driving circuit board therefor
JP4997593B2 (ja) 表示装置
CN111430421A (zh) 显示装置及其制造方法
US6052171A (en) Liquid crystal display with electrically connected integrated circuits and opposite voltage line between input and output wirings
US20220240382A1 (en) Flexible circuit board and method of manufacturing the same, and display module thereof
WO2015096234A1 (zh) 一种覆晶薄膜 cof 模组、显示面板和显示器
US7144758B2 (en) Manufacturing method of semiconductor device, including differently spaced bump electrode arrays
JP2006210809A (ja) 配線基板および実装構造体、電気光学装置および電子機器
CN114596777A (zh) 显示模组及移动终端
JP2000330480A (ja) 表示装置
WO2021134836A1 (zh) 一种显示装置
TWI783875B (zh) 顯示面板
CN110827696A (zh) 双面显示屏及显示装置
US20230371184A1 (en) Display panel and display device
CN115206187B (zh) 一种覆晶薄膜组
WO2022082651A1 (zh) 显示装置
US11410589B2 (en) Display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21934203

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21934203

Country of ref document: EP

Kind code of ref document: A1